- POSH OpenFPGA (UofU)
- A FPGA IP generator using XML-based architecture description including three parts: FPGA-Verilog, FPGA-SPICE, FPGA-Bitstream.
- Archipelago (Berkeley)
- A parameterizable and user expandable FPGA with toolflow support
- PRGA (Princeton University)
- A customizable, scalable, versatile, extensible open-source framework for building and using custom FPGAs
- ZUMA (UBC)
- Fine Grain FPGA Overlay Architecture and Tools
- literate-broccoli (Will Long)
- An open source FPGA architecture
- https://hackaday.io/project/12151-open-source-fpga
- Tritoncore (Jack Davidson)
- A very simple and minimal FPGA that is implemented in CHISEL
- Jack Davidson's undergrad project at UCSD
- Trollstigen FPGA (Blayne Kettlewell, Tom Cheng, Harrison Liew, Guanshun Yu)
- Another very simple and minimal FPGA that is implemented in CHISEL.
- The author's VLSI Design Lab (E6350) course project.
- garnet (Stanford)
- Garnet is a framework to investigate and experiment with implementing CGRA using new generator infrastructure.
- CGRA-ME (Toronto)
- An architectural modelling and exploration (ME) framework
- CCF (ASU)
- CCF (CGRA Compilation Framework) is an end-to-end prototype demonstrating the code generation and simulation process for CGRA accelerators.
- CML-CGRA (ASU)
- SMRA v2.0 (or Software Managed Reconfigurable Accelerator) is initiative of the compiler-microarchitecture lab to boost and promote development of reconfigurable accelerators, containing REGIMap, Instruction Generator/Compiler Backend and Architectural Simulator (gem5).