- NVDLA (NVIDIA)
- A free and open architecture that promotes a standard way to design deep learning inference accelerators
- VTA (UW)
- A programmable accelerator that exposes a RISC-like programming abstraction to describe compute and memory operations at the tensor level
- DANA (BU)
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
- C-LSTM (PKU, Syracuse)
- Enabling Efficient LSTM using Structured Compression Techniques on FPGAs.
- E-LSTM (HKU, PKU)
- An efficient implementation of LSTM inference on the RISC-V based embedded system
- AccDNN (IBM, UIUC)
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration
- bnn-fpga (Cornell)
- An open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA
- MAERI (GaTech)
- A DNN accelerator with reconfigurable interconnects to support flexible dataflow
- PipeCNN (BJTU)
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
- zynqnet (ETH)
- An FPGA-Accelerated Embedded Convolutional Neural Network
- HLS4ML
- A package for machine learning inference in FPGAs.
- OpenGPU2020
- 支持OpenGL ES 1.1的GPU内核
- OpenASIC H.265 Encoder (Fudan)
- H.265 Video Encoder IP Core 是开源的H.265硬件视频编码器，实现了H.265（或叫HEVC）的大部分功能