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arduFPGA_game_console_arduboy_emulator.rdf
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<?xml version="1.0" encoding="UTF-8"?>
<RadiantProject version="4.1" title="arduFPGA_game_console_arduboy_emulator" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
<Options/>
<Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="top_sim" top="top"/>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb_fs_phy/src_v/usb_fs_phy.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb_fs_phy/src_v/usb_transceiver.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usb_cdc_core.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usb_cdc_top.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usb_desc_rom.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usbf_crc16.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usbf_defs.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usbf_device_core.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usbf_sie_rx.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/core_usb2uart/src_v/usbf_sie_tx.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/usb2uart/usb2uart.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/io-s-h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/mega-alu.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/mega-core.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/mega-debug-mem-sel.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/mega-def.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/mega-ram.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/mega-reg.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/mega-rom.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-eep.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-pio.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-pll.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-rng-as-adc.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-rtc.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-spi-m.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-tim-8bit.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-tim-10bit.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-tim-16bit.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega-uart.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-atmega/atmega_twi.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-standalone/spi-slave.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-screen/interlaced-ntsc.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-screen/ssd1306-to-vga.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/io-other/pwm.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-mega-xmega/template/atmega32u4_arduboy.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="source/impl_1/sim.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../hdl-core-common/util/io-dmux.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="source/impl_1/top.v" type="Verilog" type_short="Verilog">
<Options top_module="top"/>
</Source>
<Source name="PLL_DEV_48M/PLL_DEV_48M.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="l1_boot_ld.mem" type="Unknown Type" type_short="Unknown">
<Options/>
</Source>
<Source name="source/impl_1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="source/impl_1/arduFPGA_iCE40UP5K_game.pdc" type="Physical Constraints File" type_short="PDC" excluded="TRUE">
<Options/>
</Source>
<Source name="source/impl_1/arduFPGA_iCE40UP5K_game_USBC.pdc" type="Physical Constraints File" type_short="PDC">
<Options/>
</Source>
<Source name="source/impl_1/impl_1.ldc" type="LSE Design Constraints File" type_short="LDC">
<Options/>
</Source>
<Source name="usb_cdc_descriptor.mem" type="Unknown Type" type_short="Unknown">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="arduFPGA_game_console_arduboy_emulator.sty"/>
</RadiantProject>