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Sigve's log
0200 starting more testing of the new fitness core mapping. Seems instruction cache is still a little buggy, trying to find the cause.
Been at the lab for 34 hours doing integration testing and report writing, case printing, lots of randomness.
Woops, forgot to log the last few days. Done a bunch of reporting.
We've made a fake com thing in VHDL and put it on the FPGA.
FPGA/SCU-bus: chip enable is not mapped, woops. We need to monkey-patch this with a wire.
FPGA.BUS15 is loadless, it might need to be resoldered.
FPGA.ADDR0 is loadless, it might need to be resoldered.
FPGA.ADDR1 is loadless, it might need to be resoldered.
FPGA.ADDR2 is loadless, it might need to be resoldered.
FPGA.ADDR4 is loadless, it might need to be resoldered.
FPGA.ADDR5 is loadless, it might need to be resoldered.
FPGA.ADDR7 is loadless, it might need to be resoldered.
FPGA.ADDR9 is loadless, it might need to be resoldered.
NB: Top pin of FPGA B above JTAG is ground
Header 83 is not on any header Chip enable is not conected
Working headers:
- Addresses work
- Data work
- States
- Proc Enable, Write Enable, LBUB
- All but 25,26,27,29
Wired parts of toplevel, someone else is going to have to help me with the rest of it The issue is that I don't know how to wire up the shared memory buses in a smooth manner with signals coming directly out of entity components. I've spent a lot of time making sure that the different slvs have the correct size in all the different components (pc slvs, I'm looking at you), so that should at least work much better now.
Going to ES to borrow their 3d-printer at 11am (20131114 now, time flies in the lab), they have a 3d-printer that isn't as ghetto-patched as idi's. Going to print case-back.
After I have started the printing, I'm going to bed probably.
Start 0400.
More report writing. The report is almost 100 pages long now. I'm not stopping until 100 pages is reached.
1149: 100 pages reached! I totally added a \newline to get that last page.
Did some more report writing somewhere between 2am and 10am.
#20131105
Start working at lab at 14. Working on report. Wrote some introduction stuff. End 1805.
Started working in the lab with Bjørn 1800. Going to work on the fitness core.
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Yup, I'm going to start logging meticulously. I'm going to keep it all on this single page.
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Started logging. Going to backlog, so to speak, i.e. write log for previous days. That means that logs that are before this date were not written at that time, but rather today!
Worked on the galapagos-assembler, updating to match new spec.
Updated the .vim syntax highlighter to accomodate for the new changes in the isa. Specifically: conditions. Also added support for multi-line comments. Worked on the galapagos-assembler, updating it to work on new spec, also multiline comments.
Cleaned up VHDL, removed lame header comments, fixed up the PRNG module. Worked on the assembler.
Wrote .vim syntax highlighter for the galapagos assembly. Worked more on galapagos-assember.
Wrote galapagos-assember.
Wrote a PRNG test program in C to test fast random algorithms to see if they are suitable for our purposes. The test uses dieharder. The random algo as it is now is quite fast, but is not that great in terms of randomness. If we throw away some of the bits generated, it will become much better, according to the tests.
Tidying and clerical work in the report.
Improved tooling in the report repo.
Work on the ISA documentation.
Work on the ISA documentation.
Work on the ISA documentation.
Did lots of work on the ISA documentation.
Did lots of work on the ISA documentation.
Started working on the ISA documentation.
Implemented a continuous GA simulation in python to see if continuous GA is usable. As it turns out, it is arguably better.
Discussion with FPGA group in Bjørn's office about the genetics pipeline architecture, and specifically, how to implement the specimen memory banks. The idea of continuous GA cropped up, but we need to do a test to verify if it actually works.
Put a minimal report shell on github, added some latex tips and instructions.