-
Notifications
You must be signed in to change notification settings - Fork 4.9k
/
Copy pathhwintrinsicarm64.cpp
3247 lines (2704 loc) · 116 KB
/
hwintrinsicarm64.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "jitpch.h"
#include "hwintrinsic.h"
#ifdef FEATURE_HW_INTRINSICS
//------------------------------------------------------------------------
// Arm64VersionOfIsa: Gets the corresponding 64-bit only InstructionSet for a given InstructionSet
//
// Arguments:
// isa -- The InstructionSet ID
//
// Return Value:
// The 64-bit only InstructionSet associated with isa
static CORINFO_InstructionSet Arm64VersionOfIsa(CORINFO_InstructionSet isa)
{
switch (isa)
{
case InstructionSet_AdvSimd:
return InstructionSet_AdvSimd_Arm64;
case InstructionSet_Aes:
return InstructionSet_Aes_Arm64;
case InstructionSet_ArmBase:
return InstructionSet_ArmBase_Arm64;
case InstructionSet_Crc32:
return InstructionSet_Crc32_Arm64;
case InstructionSet_Dp:
return InstructionSet_Dp_Arm64;
case InstructionSet_Sha1:
return InstructionSet_Sha1_Arm64;
case InstructionSet_Sha256:
return InstructionSet_Sha256_Arm64;
case InstructionSet_Rdm:
return InstructionSet_Rdm_Arm64;
case InstructionSet_Sve:
return InstructionSet_Sve_Arm64;
default:
return InstructionSet_NONE;
}
}
//------------------------------------------------------------------------
// lookupInstructionSet: Gets the InstructionSet for a given class name
//
// Arguments:
// className -- The name of the class associated with the InstructionSet to lookup
//
// Return Value:
// The InstructionSet associated with className
static CORINFO_InstructionSet lookupInstructionSet(const char* className)
{
assert(className != nullptr);
if (className[0] == 'A')
{
if (strcmp(className, "AdvSimd") == 0)
{
return InstructionSet_AdvSimd;
}
if (strcmp(className, "Aes") == 0)
{
return InstructionSet_Aes;
}
if (strcmp(className, "ArmBase") == 0)
{
return InstructionSet_ArmBase;
}
}
else if (className[0] == 'C')
{
if (strcmp(className, "Crc32") == 0)
{
return InstructionSet_Crc32;
}
}
else if (className[0] == 'D')
{
if (strcmp(className, "Dp") == 0)
{
return InstructionSet_Dp;
}
}
else if (className[0] == 'R')
{
if (strcmp(className, "Rdm") == 0)
{
return InstructionSet_Rdm;
}
}
else if (className[0] == 'S')
{
if (strcmp(className, "Sha1") == 0)
{
return InstructionSet_Sha1;
}
if (strcmp(className, "Sha256") == 0)
{
return InstructionSet_Sha256;
}
if (strcmp(className, "Sve") == 0)
{
return InstructionSet_Sve;
}
}
else if (className[0] == 'V')
{
if (strncmp(className, "Vector64", 8) == 0)
{
return InstructionSet_Vector64;
}
else if (strncmp(className, "Vector128", 9) == 0)
{
return InstructionSet_Vector128;
}
}
return InstructionSet_ILLEGAL;
}
//------------------------------------------------------------------------
// lookupIsa: Gets the InstructionSet for a given class name and enclsoing class name
//
// Arguments:
// className -- The name of the class associated with the InstructionSet to lookup
// innerEnclosingClassName -- The name of the inner enclosing class or nullptr if one doesn't exist
// outerEnclosingClassName -- The name of the outer enclosing class or nullptr if one doesn't exist
//
// Return Value:
// The InstructionSet associated with className and enclosingClassName
//
CORINFO_InstructionSet HWIntrinsicInfo::lookupIsa(const char* className,
const char* innerEnclosingClassName,
const char* outerEnclosingClassName)
{
assert(className != nullptr);
if (innerEnclosingClassName == nullptr)
{
// No nested class is the most common, so fast path it
return lookupInstructionSet(className);
}
// Since lookupId is only called for the xplat intrinsics
// or intrinsics in the platform specific namespace, we assume
// that it will be one we can handle and don't try to early out.
CORINFO_InstructionSet enclosingIsa = lookupIsa(innerEnclosingClassName, outerEnclosingClassName, nullptr);
if (strcmp(className, "Arm64") == 0)
{
return Arm64VersionOfIsa(enclosingIsa);
}
return InstructionSet_ILLEGAL;
}
//------------------------------------------------------------------------
// lookupIval: Gets a the implicit immediate value for the given intrinsic
//
// Arguments:
// id - The intrinsic for which to get the ival
//
// Return Value:
// The immediate value for the given intrinsic or -1 if none exists
int HWIntrinsicInfo::lookupIval(NamedIntrinsic id)
{
switch (id)
{
case NI_Sve_Compute16BitAddresses:
return 1;
case NI_Sve_Compute32BitAddresses:
return 2;
case NI_Sve_Compute64BitAddresses:
return 3;
case NI_Sve_Compute8BitAddresses:
return 0;
default:
unreached();
}
return -1;
}
//------------------------------------------------------------------------
// isFullyImplementedIsa: Gets a value that indicates whether the InstructionSet is fully implemented
//
// Arguments:
// isa - The InstructionSet to check
//
// Return Value:
// true if isa is supported; otherwise, false
bool HWIntrinsicInfo::isFullyImplementedIsa(CORINFO_InstructionSet isa)
{
switch (isa)
{
// These ISAs are fully implemented
case InstructionSet_AdvSimd:
case InstructionSet_AdvSimd_Arm64:
case InstructionSet_Aes:
case InstructionSet_Aes_Arm64:
case InstructionSet_ArmBase:
case InstructionSet_ArmBase_Arm64:
case InstructionSet_Crc32:
case InstructionSet_Crc32_Arm64:
case InstructionSet_Dp:
case InstructionSet_Dp_Arm64:
case InstructionSet_Rdm:
case InstructionSet_Rdm_Arm64:
case InstructionSet_Sha1:
case InstructionSet_Sha1_Arm64:
case InstructionSet_Sha256:
case InstructionSet_Sha256_Arm64:
case InstructionSet_Sve:
case InstructionSet_Sve_Arm64:
case InstructionSet_Vector64:
case InstructionSet_Vector128:
return true;
default:
return false;
}
}
//------------------------------------------------------------------------
// isScalarIsa: Gets a value that indicates whether the InstructionSet is scalar
//
// Arguments:
// isa - The InstructionSet to check
//
// Return Value:
// true if isa is scalar; otherwise, false
bool HWIntrinsicInfo::isScalarIsa(CORINFO_InstructionSet isa)
{
switch (isa)
{
case InstructionSet_ArmBase:
case InstructionSet_ArmBase_Arm64:
case InstructionSet_Crc32:
case InstructionSet_Crc32_Arm64:
{
return true;
}
default:
{
return false;
}
}
}
//------------------------------------------------------------------------
// getHWIntrinsicImmOps: Gets the immediate Ops for an intrinsic
//
// Arguments:
// intrinsic -- NamedIntrinsic associated with the HWIntrinsic to lookup
// sig -- signature of the intrinsic call.
// immOp1Ptr [OUT] -- The first immediate Op
// immOp2Ptr [OUT] -- The second immediate Op, if any. Otherwise unchanged.
//
void Compiler::getHWIntrinsicImmOps(NamedIntrinsic intrinsic,
CORINFO_SIG_INFO* sig,
GenTree** immOp1Ptr,
GenTree** immOp2Ptr)
{
if (!HWIntrinsicInfo::HasImmediateOperand(intrinsic))
{
return;
}
// Position of the immediates from top of stack
int imm1Pos = -1;
int imm2Pos = -1;
HWIntrinsicInfo::GetImmOpsPositions(intrinsic, sig, &imm1Pos, &imm2Pos);
if (imm1Pos >= 0)
{
*immOp1Ptr = impStackTop(imm1Pos).val;
assert(HWIntrinsicInfo::isImmOp(intrinsic, *immOp1Ptr));
}
if (imm2Pos >= 0)
{
*immOp2Ptr = impStackTop(imm2Pos).val;
assert(HWIntrinsicInfo::isImmOp(intrinsic, *immOp2Ptr));
}
}
//------------------------------------------------------------------------
// getHWIntrinsicImmTypes: Gets the type/size for an immediate for an intrinsic
// if it differs from the default type/size of the instrinsic
//
// Arguments:
// intrinsic -- NamedIntrinsic associated with the HWIntrinsic to lookup
// sig -- signature of the intrinsic call.
// immNumber -- Which immediate to use (1 for most intrinsics)
// simdBaseType -- base type of the intrinsic
// simdType -- vector size of the intrinsic
// op1ClsHnd -- cls handler for op1
// op2ClsHnd -- cls handler for op2
// op2ClsHnd -- cls handler for op3
// immSimdSize [IN/OUT] -- Size of the immediate to override
// immSimdBaseType [IN/OUT] -- Base type of the immediate to override
//
void Compiler::getHWIntrinsicImmTypes(NamedIntrinsic intrinsic,
CORINFO_SIG_INFO* sig,
unsigned immNumber,
var_types simdBaseType,
CorInfoType simdBaseJitType,
CORINFO_CLASS_HANDLE op1ClsHnd,
CORINFO_CLASS_HANDLE op2ClsHnd,
CORINFO_CLASS_HANDLE op3ClsHnd,
unsigned* immSimdSize,
var_types* immSimdBaseType)
{
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);
if (category == HW_Category_SIMDByIndexedElement)
{
assert(immNumber == 1);
CorInfoType indexedElementBaseJitType;
var_types indexedElementBaseType;
*immSimdSize = 0;
if (sig->numArgs == 2)
{
indexedElementBaseJitType = getBaseJitTypeAndSizeOfSIMDType(op1ClsHnd, immSimdSize);
indexedElementBaseType = JitType2PreciseVarType(indexedElementBaseJitType);
}
else if (sig->numArgs == 3)
{
indexedElementBaseJitType = getBaseJitTypeAndSizeOfSIMDType(op2ClsHnd, immSimdSize);
indexedElementBaseType = JitType2PreciseVarType(indexedElementBaseJitType);
}
else
{
assert(sig->numArgs == 4);
indexedElementBaseJitType = getBaseJitTypeAndSizeOfSIMDType(op3ClsHnd, immSimdSize);
indexedElementBaseType = JitType2PreciseVarType(indexedElementBaseJitType);
if (intrinsic == NI_Dp_DotProductBySelectedQuadruplet)
{
assert(((simdBaseType == TYP_INT) && (indexedElementBaseType == TYP_BYTE)) ||
((simdBaseType == TYP_UINT) && (indexedElementBaseType == TYP_UBYTE)));
// The second source operand of sdot, udot instructions is an indexed 32-bit element.
indexedElementBaseType = simdBaseType;
}
if (intrinsic == NI_Sve_DotProductBySelectedScalar)
{
assert(((simdBaseType == TYP_INT) && (indexedElementBaseType == TYP_BYTE)) ||
((simdBaseType == TYP_UINT) && (indexedElementBaseType == TYP_UBYTE)) ||
((simdBaseType == TYP_LONG) && (indexedElementBaseType == TYP_SHORT)) ||
((simdBaseType == TYP_ULONG) && (indexedElementBaseType == TYP_USHORT)));
// The second source operand of sdot, udot instructions is an indexed 32-bit element.
indexedElementBaseType = simdBaseType;
}
}
assert(indexedElementBaseType == simdBaseType);
}
else if (intrinsic == NI_AdvSimd_Arm64_InsertSelectedScalar)
{
if (immNumber == 2)
{
CorInfoType otherBaseJitType = getBaseJitTypeAndSizeOfSIMDType(op3ClsHnd, immSimdSize);
*immSimdBaseType = JitType2PreciseVarType(otherBaseJitType);
assert(otherBaseJitType == simdBaseJitType);
}
// For imm1 use default simd sizes.
}
// For all other imms, use default simd sizes
}
//------------------------------------------------------------------------
// lookupImmBounds: Gets the lower and upper bounds for the imm-value of a given NamedIntrinsic
//
// Arguments:
// intrinsic -- NamedIntrinsic associated with the HWIntrinsic to lookup
// simdType -- vector size
// baseType -- base type of the Vector64/128<T>
// immNumber -- which immediate operand to check for (most intrinsics only have one)
// pImmLowerBound [OUT] - The lower incl. bound for a value of the intrinsic immediate operand
// pImmUpperBound [OUT] - The upper incl. bound for a value of the intrinsic immediate operand
//
void HWIntrinsicInfo::lookupImmBounds(
NamedIntrinsic intrinsic, int simdSize, var_types baseType, int immNumber, int* pImmLowerBound, int* pImmUpperBound)
{
HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);
bool hasImmediateOperand = HasImmediateOperand(intrinsic);
assert(hasImmediateOperand);
assert(pImmLowerBound != nullptr);
assert(pImmUpperBound != nullptr);
int immLowerBound = 0;
int immUpperBound = 0;
if (category == HW_Category_ShiftLeftByImmediate)
{
// The left shift amount is in the range 0 to the element width in bits minus 1.
immUpperBound = BITS_PER_BYTE * genTypeSize(baseType) - 1;
}
else if (category == HW_Category_ShiftRightByImmediate)
{
// The right shift amount, in the range 1 to the element width in bits.
immLowerBound = 1;
immUpperBound = BITS_PER_BYTE * genTypeSize(baseType);
}
else if (category == HW_Category_SIMDByIndexedElement)
{
if (intrinsic == NI_Sve_DuplicateSelectedScalarToVector)
{
// For SVE_DUP, the upper bound on index does not depend on the vector length.
immUpperBound = (512 / (BITS_PER_BYTE * genTypeSize(baseType))) - 1;
}
else
{
immUpperBound = Compiler::getSIMDVectorLength(simdSize, baseType) - 1;
}
}
else
{
switch (intrinsic)
{
case NI_AdvSimd_DuplicateSelectedScalarToVector64:
case NI_AdvSimd_DuplicateSelectedScalarToVector128:
case NI_AdvSimd_Extract:
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_ExtractVector64:
case NI_AdvSimd_Insert:
case NI_AdvSimd_InsertScalar:
case NI_AdvSimd_LoadAndInsertScalar:
case NI_AdvSimd_LoadAndInsertScalarVector64x2:
case NI_AdvSimd_LoadAndInsertScalarVector64x3:
case NI_AdvSimd_LoadAndInsertScalarVector64x4:
case NI_AdvSimd_Arm64_LoadAndInsertScalarVector128x2:
case NI_AdvSimd_Arm64_LoadAndInsertScalarVector128x3:
case NI_AdvSimd_Arm64_LoadAndInsertScalarVector128x4:
case NI_AdvSimd_StoreSelectedScalar:
case NI_AdvSimd_Arm64_StoreSelectedScalar:
case NI_AdvSimd_Arm64_DuplicateSelectedScalarToVector128:
case NI_AdvSimd_Arm64_InsertSelectedScalar:
case NI_Sve_FusedMultiplyAddBySelectedScalar:
case NI_Sve_FusedMultiplySubtractBySelectedScalar:
case NI_Sve_ExtractVector:
immUpperBound = Compiler::getSIMDVectorLength(simdSize, baseType) - 1;
break;
case NI_Sve_CreateTrueMaskByte:
case NI_Sve_CreateTrueMaskDouble:
case NI_Sve_CreateTrueMaskInt16:
case NI_Sve_CreateTrueMaskInt32:
case NI_Sve_CreateTrueMaskInt64:
case NI_Sve_CreateTrueMaskSByte:
case NI_Sve_CreateTrueMaskSingle:
case NI_Sve_CreateTrueMaskUInt16:
case NI_Sve_CreateTrueMaskUInt32:
case NI_Sve_CreateTrueMaskUInt64:
case NI_Sve_Count16BitElements:
case NI_Sve_Count32BitElements:
case NI_Sve_Count64BitElements:
case NI_Sve_Count8BitElements:
immLowerBound = (int)SVE_PATTERN_POW2;
immUpperBound = (int)SVE_PATTERN_ALL;
break;
case NI_Sve_SaturatingDecrementBy16BitElementCount:
case NI_Sve_SaturatingDecrementBy32BitElementCount:
case NI_Sve_SaturatingDecrementBy64BitElementCount:
case NI_Sve_SaturatingDecrementBy8BitElementCount:
case NI_Sve_SaturatingIncrementBy16BitElementCount:
case NI_Sve_SaturatingIncrementBy32BitElementCount:
case NI_Sve_SaturatingIncrementBy64BitElementCount:
case NI_Sve_SaturatingIncrementBy8BitElementCount:
case NI_Sve_SaturatingDecrementBy16BitElementCountScalar:
case NI_Sve_SaturatingDecrementBy32BitElementCountScalar:
case NI_Sve_SaturatingDecrementBy64BitElementCountScalar:
case NI_Sve_SaturatingIncrementBy16BitElementCountScalar:
case NI_Sve_SaturatingIncrementBy32BitElementCountScalar:
case NI_Sve_SaturatingIncrementBy64BitElementCountScalar:
if (immNumber == 1)
{
immLowerBound = 1;
immUpperBound = 16;
}
else
{
assert(immNumber == 2);
immLowerBound = (int)SVE_PATTERN_POW2;
immUpperBound = (int)SVE_PATTERN_ALL;
}
break;
case NI_Sve_GatherPrefetch8Bit:
case NI_Sve_GatherPrefetch16Bit:
case NI_Sve_GatherPrefetch32Bit:
case NI_Sve_GatherPrefetch64Bit:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
immLowerBound = (int)SVE_PRFOP_PLDL1KEEP;
immUpperBound = (int)SVE_PRFOP_CONST15;
break;
case NI_Sve_AddRotateComplex:
immLowerBound = 0;
immUpperBound = 1;
break;
case NI_Sve_MultiplyAddRotateComplex:
immLowerBound = 0;
immUpperBound = 3;
break;
case NI_Sve_MultiplyAddRotateComplexBySelectedScalar:
// rotation comes after index in the intrinsic's signature,
// but flip the order here so we check the larger range first.
// This conforms to the existing logic in LinearScan::BuildHWIntrinsic
// when determining if we need an internal register for the jump table.
// This flipped ordering is reflected in HWIntrinsicInfo::GetImmOpsPositions.
if (immNumber == 1)
{
// Bounds for rotation
immLowerBound = 0;
immUpperBound = 3;
}
else
{
// Bounds for index
assert(immNumber == 2);
immLowerBound = 0;
immUpperBound = 1;
}
break;
case NI_Sve_TrigonometricMultiplyAddCoefficient:
immLowerBound = 0;
immUpperBound = 7;
break;
default:
unreached();
}
}
assert(immLowerBound <= immUpperBound);
*pImmLowerBound = immLowerBound;
*pImmUpperBound = immUpperBound;
}
//------------------------------------------------------------------------
// impNonConstFallback: generate alternate code when the imm-arg is not a compile-time constant
//
// Arguments:
// intrinsic -- intrinsic ID
// simdType -- Vector type
// simdBaseJitType -- base JIT type of the Vector64/128<T>
//
// Return Value:
// return the IR of semantic alternative on non-const imm-arg
//
GenTree* Compiler::impNonConstFallback(NamedIntrinsic intrinsic, var_types simdType, CorInfoType simdBaseJitType)
{
bool isRightShift = true;
switch (intrinsic)
{
case NI_AdvSimd_ShiftLeftLogical:
case NI_AdvSimd_ShiftLeftLogicalScalar:
isRightShift = false;
FALLTHROUGH;
case NI_AdvSimd_ShiftRightLogical:
case NI_AdvSimd_ShiftRightLogicalScalar:
case NI_AdvSimd_ShiftRightArithmetic:
case NI_AdvSimd_ShiftRightArithmeticScalar:
{
// AdvSimd.ShiftLeft* and AdvSimd.ShiftRight* can be replaced with AdvSimd.Shift*, which takes op2 in a simd
// register
GenTree* op2 = impPopStack().val;
GenTree* op1 = impSIMDPopStack();
// AdvSimd.ShiftLogical does right-shifts with negative immediates, hence the negation
if (isRightShift)
{
op2 = gtNewOperNode(GT_NEG, genActualType(op2->TypeGet()), op2);
}
NamedIntrinsic fallbackIntrinsic;
switch (intrinsic)
{
case NI_AdvSimd_ShiftLeftLogical:
case NI_AdvSimd_ShiftRightLogical:
fallbackIntrinsic = NI_AdvSimd_ShiftLogical;
break;
case NI_AdvSimd_ShiftLeftLogicalScalar:
case NI_AdvSimd_ShiftRightLogicalScalar:
fallbackIntrinsic = NI_AdvSimd_ShiftLogicalScalar;
break;
case NI_AdvSimd_ShiftRightArithmetic:
fallbackIntrinsic = NI_AdvSimd_ShiftArithmetic;
break;
case NI_AdvSimd_ShiftRightArithmeticScalar:
fallbackIntrinsic = NI_AdvSimd_ShiftArithmeticScalar;
break;
default:
unreached();
}
GenTree* tmpOp = gtNewSimdCreateBroadcastNode(simdType, op2, simdBaseJitType, genTypeSize(simdType));
return gtNewSimdHWIntrinsicNode(simdType, op1, tmpOp, fallbackIntrinsic, simdBaseJitType,
genTypeSize(simdType));
}
default:
return nullptr;
}
}
//------------------------------------------------------------------------
// impSpecialIntrinsic: Import a hardware intrinsic that requires special handling as a GT_HWINTRINSIC node if possible
//
// Arguments:
// intrinsic -- id of the intrinsic function.
// clsHnd -- class handle containing the intrinsic function.
// method -- method handle of the intrinsic function.
// sig -- signature of the intrinsic call.
// entryPoint -- The entry point information required for R2R scenarios
// simdBaseJitType -- generic argument of the intrinsic.
// retType -- return type of the intrinsic.
// mustExpand -- true if the intrinsic must return a GenTree*; otherwise, false
//
// Return Value:
// The GT_HWINTRINSIC node, or nullptr if not a supported intrinsic
//
GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_CLASS_HANDLE clsHnd,
CORINFO_METHOD_HANDLE method,
CORINFO_SIG_INFO* sig R2RARG(CORINFO_CONST_LOOKUP* entryPoint),
CorInfoType simdBaseJitType,
var_types retType,
unsigned simdSize,
bool mustExpand)
{
const HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrinsic);
const int numArgs = sig->numArgs;
// The vast majority of "special" intrinsics are Vector64/Vector128 methods.
// The only exception is ArmBase.Yield which should be treated differently.
if (intrinsic == NI_ArmBase_Yield)
{
assert(sig->numArgs == 0);
assert(JITtype2varType(sig->retType) == TYP_VOID);
assert(simdSize == 0);
return gtNewScalarHWIntrinsicNode(TYP_VOID, intrinsic);
}
bool isScalar = (category == HW_Category_Scalar);
assert(!HWIntrinsicInfo::isScalarIsa(HWIntrinsicInfo::lookupIsa(intrinsic)));
assert(numArgs >= 0);
var_types simdBaseType = JitType2PreciseVarType(simdBaseJitType);
assert(varTypeIsArithmetic(simdBaseType));
GenTree* retNode = nullptr;
GenTree* op1 = nullptr;
GenTree* op2 = nullptr;
GenTree* op3 = nullptr;
GenTree* op4 = nullptr;
#ifdef DEBUG
bool isValidScalarIntrinsic = false;
#endif
switch (intrinsic)
{
case NI_Vector64_Abs:
case NI_Vector128_Abs:
{
assert(sig->numArgs == 1);
op1 = impSIMDPopStack();
retNode = gtNewSimdAbsNode(retType, op1, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_op_Addition:
case NI_Vector128_op_Addition:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack();
op1 = impSIMDPopStack();
retNode = gtNewSimdBinOpNode(GT_ADD, retType, op1, op2, simdBaseJitType, simdSize);
break;
}
case NI_AdvSimd_BitwiseClear:
case NI_Vector64_AndNot:
case NI_Vector128_AndNot:
{
assert(sig->numArgs == 2);
// We don't want to support creating AND_NOT nodes prior to LIR
// as it can break important optimizations. We'll produces this
// in lowering instead so decompose into the individual operations
// on import
op2 = impSIMDPopStack();
op1 = impSIMDPopStack();
op2 = gtFoldExpr(gtNewSimdUnOpNode(GT_NOT, retType, op2, simdBaseJitType, simdSize));
retNode = gtNewSimdBinOpNode(GT_AND, retType, op1, op2, simdBaseJitType, simdSize);
break;
}
case NI_AdvSimd_OrNot:
{
assert(sig->numArgs == 2);
// We don't want to support creating OR_NOT nodes prior to LIR
// as it can break important optimizations. We'll produces this
// in lowering instead so decompose into the individual operations
// on import
op2 = impSIMDPopStack();
op1 = impSIMDPopStack();
op2 = gtFoldExpr(gtNewSimdUnOpNode(GT_NOT, retType, op2, simdBaseJitType, simdSize));
retNode = gtNewSimdBinOpNode(GT_OR, retType, op1, op2, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_As:
case NI_Vector64_AsByte:
case NI_Vector64_AsDouble:
case NI_Vector64_AsInt16:
case NI_Vector64_AsInt32:
case NI_Vector64_AsInt64:
case NI_Vector64_AsNInt:
case NI_Vector64_AsNUInt:
case NI_Vector64_AsSByte:
case NI_Vector64_AsSingle:
case NI_Vector64_AsUInt16:
case NI_Vector64_AsUInt32:
case NI_Vector64_AsUInt64:
case NI_Vector128_As:
case NI_Vector128_AsByte:
case NI_Vector128_AsDouble:
case NI_Vector128_AsInt16:
case NI_Vector128_AsInt32:
case NI_Vector128_AsInt64:
case NI_Vector128_AsNInt:
case NI_Vector128_AsNUInt:
case NI_Vector128_AsSByte:
case NI_Vector128_AsSingle:
case NI_Vector128_AsUInt16:
case NI_Vector128_AsUInt32:
case NI_Vector128_AsUInt64:
case NI_Vector128_AsVector:
case NI_Vector128_AsVector4:
{
assert(!sig->hasThis());
assert(numArgs == 1);
// We fold away the cast here, as it only exists to satisfy
// the type system. It is safe to do this here since the retNode type
// and the signature return type are both the same TYP_SIMD.
retNode = impSIMDPopStack();
SetOpLclRelatedToSIMDIntrinsic(retNode);
assert(retNode->gtType == getSIMDTypeForSize(getSIMDTypeSizeInBytes(sig->retTypeSigClass)));
break;
}
case NI_Vector128_AsVector2:
{
assert(sig->numArgs == 1);
assert((simdSize == 16) && (simdBaseType == TYP_FLOAT));
assert(retType == TYP_SIMD8);
op1 = impSIMDPopStack();
retNode = gtNewSimdGetLowerNode(TYP_SIMD8, op1, simdBaseJitType, simdSize);
break;
}
case NI_Vector128_AsVector3:
{
assert(sig->numArgs == 1);
assert((simdSize == 16) && (simdBaseType == TYP_FLOAT));
assert(retType == TYP_SIMD12);
op1 = impSIMDPopStack();
retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, simdBaseJitType, simdSize);
break;
}
case NI_Vector128_AsVector128:
{
assert(!sig->hasThis());
assert(numArgs == 1);
assert(retType == TYP_SIMD16);
switch (getSIMDTypeForSize(simdSize))
{
case TYP_SIMD8:
{
assert((simdSize == 8) && (simdBaseType == TYP_FLOAT));
op1 = impSIMDPopStack();
if (op1->IsCnsVec())
{
GenTreeVecCon* vecCon = op1->AsVecCon();
vecCon->gtType = TYP_SIMD16;
vecCon->gtSimdVal.f32[2] = 0.0f;
vecCon->gtSimdVal.f32[3] = 0.0f;
return vecCon;
}
op1 = gtNewSimdHWIntrinsicNode(retType, op1, NI_Vector64_ToVector128Unsafe, simdBaseJitType, 8);
GenTree* idx = gtNewIconNode(2, TYP_INT);
GenTree* zero = gtNewZeroConNode(TYP_FLOAT);
op1 = gtNewSimdWithElementNode(retType, op1, idx, zero, simdBaseJitType, 16);
idx = gtNewIconNode(3, TYP_INT);
zero = gtNewZeroConNode(TYP_FLOAT);
retNode = gtNewSimdWithElementNode(retType, op1, idx, zero, simdBaseJitType, 16);
break;
}
case TYP_SIMD12:
{
assert((simdSize == 12) && (simdBaseType == TYP_FLOAT));
op1 = impSIMDPopStack();
if (op1->IsCnsVec())
{
GenTreeVecCon* vecCon = op1->AsVecCon();
vecCon->gtType = TYP_SIMD16;
vecCon->gtSimdVal.f32[3] = 0.0f;
return vecCon;
}
op1 = gtNewSimdHWIntrinsicNode(retType, op1, NI_Vector128_AsVector128Unsafe, simdBaseJitType, 12);
GenTree* idx = gtNewIconNode(3, TYP_INT);
GenTree* zero = gtNewZeroConNode(TYP_FLOAT);
retNode = gtNewSimdWithElementNode(retType, op1, idx, zero, simdBaseJitType, 16);
break;
}
case TYP_SIMD16:
{
// We fold away the cast here, as it only exists to satisfy
// the type system. It is safe to do this here since the retNode type
// and the signature return type are both the same TYP_SIMD.
retNode = impSIMDPopStack();
SetOpLclRelatedToSIMDIntrinsic(retNode);
assert(retNode->gtType == getSIMDTypeForSize(getSIMDTypeSizeInBytes(sig->retTypeSigClass)));
break;
}
default:
{
unreached();
}
}
break;
}
case NI_Vector128_AsVector128Unsafe:
{
assert(sig->numArgs == 1);
assert(retType == TYP_SIMD16);
assert(simdBaseJitType == CORINFO_TYPE_FLOAT);
assert((simdSize == 8) || (simdSize == 12));
op1 = impSIMDPopStack();
retNode = gtNewSimdHWIntrinsicNode(retType, op1, NI_Vector128_AsVector128Unsafe, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_op_BitwiseAnd:
case NI_Vector128_op_BitwiseAnd:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack();
op1 = impSIMDPopStack();
retNode = gtNewSimdBinOpNode(GT_AND, retType, op1, op2, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_op_BitwiseOr:
case NI_Vector128_op_BitwiseOr:
{
assert(sig->numArgs == 2);
op2 = impSIMDPopStack();
op1 = impSIMDPopStack();
retNode = gtNewSimdBinOpNode(GT_OR, retType, op1, op2, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_Ceiling:
case NI_Vector128_Ceiling:
{
assert(sig->numArgs == 1);
if (!varTypeIsFloating(simdBaseType))
{
retNode = impSIMDPopStack();
break;
}
op1 = impSIMDPopStack();
retNode = gtNewSimdCeilNode(retType, op1, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConditionalSelect:
case NI_Vector128_ConditionalSelect:
{
assert(sig->numArgs == 3);
op3 = impSIMDPopStack();
op2 = impSIMDPopStack();
op1 = impSIMDPopStack();
retNode = gtNewSimdCndSelNode(retType, op1, op2, op3, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConvertToDouble:
case NI_Vector128_ConvertToDouble:
{
assert(sig->numArgs == 1);
assert((simdBaseType == TYP_LONG) || (simdBaseType == TYP_ULONG));
intrinsic = (simdSize == 8) ? NI_AdvSimd_Arm64_ConvertToDoubleScalar : NI_AdvSimd_Arm64_ConvertToDouble;
op1 = impSIMDPopStack();
retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConvertToInt32Native:
case NI_Vector128_ConvertToInt32Native:
{
if (BlockNonDeterministicIntrinsics(mustExpand))
{
break;
}
FALLTHROUGH;
}
case NI_Vector64_ConvertToInt32:
case NI_Vector128_ConvertToInt32:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
op1 = impSIMDPopStack();
retNode = gtNewSimdCvtNativeNode(retType, op1, CORINFO_TYPE_INT, simdBaseJitType, simdSize);
break;
}
case NI_Vector64_ConvertToInt64Native:
case NI_Vector128_ConvertToInt64Native:
{
if (BlockNonDeterministicIntrinsics(mustExpand))
{
break;
}
FALLTHROUGH;