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Note the x0 in fcvtzs. The float value is cast to int64, then the lower half gets sign-extended. The expected behavior would be to directly convert to int32 with saturation, i.e.:
This would be more in line with the casting behavior of CoreCLR. This would also fix the test /JIT/SIMD/VectorConvert_ro_Target_64Bit/, which is to be reenabled at that point.
The text was updated successfully, but these errors were encountered:
The issue has been encountered in #85163
The code
private static float Z(float y) => (float)(int)y;
translates on arm64 to:Note the
x0
infcvtzs
. Thefloat
value is cast toint64
, then the lower half gets sign-extended. The expected behavior would be to directly convert toint32
with saturation, i.e.:This would be more in line with the casting behavior of CoreCLR. This would also fix the test
/JIT/SIMD/VectorConvert_ro_Target_64Bit/
, which is to be reenabled at that point.The text was updated successfully, but these errors were encountered: