From fb3cca678a194eac3cd6819643dfde35b6cf2922 Mon Sep 17 00:00:00 2001 From: Ruihan-Yin Date: Tue, 14 Jan 2025 14:04:05 -0800 Subject: [PATCH] add rcl/rcr tp and latency info --- src/coreclr/jit/codegenxarch.cpp | 5 ++--- src/coreclr/jit/emitxarch.cpp | 2 ++ src/coreclr/jit/instrsxarch.h | 4 ++-- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index bd80187eea6a44..f2df925df2203e 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -9134,9 +9134,8 @@ void CodeGen::genAmd64EmitterUnitTestsApx() theEmitter->emitIns_R_I(INS_sar_N, EA_4BYTE, REG_ECX, 0x05); theEmitter->emitIns_R_I(INS_rol_N, EA_4BYTE, REG_ECX, 0x05); theEmitter->emitIns_R_I(INS_ror_N, EA_4BYTE, REG_ECX, 0x05); - // TODO-xarch-apx: not enable these 2 for now. - // theEmitter->emitIns_R_I(INS_rcl_N, EA_4BYTE, REG_ECX, 0x05); - // theEmitter->emitIns_R_I(INS_rcr_N, EA_4BYTE, REG_ECX, 0x05); + theEmitter->emitIns_R_I(INS_rcl_N, EA_4BYTE, REG_ECX, 0x05); + theEmitter->emitIns_R_I(INS_rcr_N, EA_4BYTE, REG_ECX, 0x05); theEmitter->emitIns_R(INS_neg, EA_2BYTE, REG_EAX); theEmitter->emitIns_R(INS_not, EA_2BYTE, REG_EAX); diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp index 61d5d9b6a91749..77f8787a3e2457 100644 --- a/src/coreclr/jit/emitxarch.cpp +++ b/src/coreclr/jit/emitxarch.cpp @@ -19230,6 +19230,8 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins case INS_rcr: case INS_rcl: + case INS_rcr_N: + case INS_rcl_N: result.insThroughput = PERFSCORE_THROUGHPUT_6C; result.insLatency += PERFSCORE_LATENCY_6C; break; diff --git a/src/coreclr/jit/instrsxarch.h b/src/coreclr/jit/instrsxarch.h index 57c536c3af1442..3c6285405a0747 100644 --- a/src/coreclr/jit/instrsxarch.h +++ b/src/coreclr/jit/instrsxarch.h @@ -913,10 +913,10 @@ INST2(ror_N, "ror", IUM_RW, 0x0008C0, 0x0008C0, INST2(rcl, "rcl", IUM_RW, 0x0010D2, BAD_CODE, INS_TT_NONE, Undefined_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) INST2(rcl_1, "rcl", IUM_RW, 0x0010D0, 0x0010D0, INS_TT_NONE, Writes_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) -INST2(rcl_N, "rcl", IUM_RW, 0x0010C0, 0x0010C0, INS_TT_NONE, Undefined_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit) +INST2(rcl_N, "rcl", IUM_RW, 0x0010C0, 0x0010C0, INS_TT_NONE, Undefined_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) INST2(rcr, "rcr", IUM_RW, 0x0018D2, BAD_CODE, INS_TT_NONE, Undefined_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) INST2(rcr_1, "rcr", IUM_RW, 0x0018D0, 0x0018D0, INS_TT_NONE, Writes_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) -INST2(rcr_N, "rcr", IUM_RW, 0x0018C0, 0x0018C0, INS_TT_NONE, Undefined_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit) +INST2(rcr_N, "rcr", IUM_RW, 0x0018C0, 0x0018C0, INS_TT_NONE, Undefined_OF | Writes_CF | Reads_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) INST2(shl, "shl", IUM_RW, 0x0020D2, BAD_CODE, INS_TT_NONE, Undefined_OF | Writes_SF | Writes_ZF | Undefined_AF | Writes_PF | Writes_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) INST2(shl_1, "shl", IUM_RW, 0x0020D0, 0x0020D0, INS_TT_NONE, Writes_OF | Writes_SF | Writes_ZF | Undefined_AF | Writes_PF | Writes_CF | INS_FLAGS_Has_Wbit | Encoding_REX2) INST2(shl_N, "shl", IUM_RW, 0x0020C0, 0x0020C0, INS_TT_NONE, Undefined_OF | Writes_SF | Writes_ZF | Undefined_AF | Writes_PF | Writes_CF | INS_FLAGS_Has_Wbit | Encoding_REX2)