Feature: Implement AXI completion queue per ID to ensure ordering rules

[dpretet]

The core currently doesn't support correctly AMBA completion ordering rules if a master issues multiples outstanding requests with the same ID among different slaves.

To address the limitation, an axicb_slv_switch must embed multiple FIFOs (queues) to store incoming read/write completions and a FIFO to store the AID order transmitted to the slaves, used to follow the correct order when emptying the queues and serving the completions.

In order to save area, this new feature should be deactivatable if a system doesn't need this strong ordering. In some situation, solution may be to use a different ID or ID mask per slave and manage the ordering inside the master issuing the request.

For AXI4 read completion, the completion queues should store RLAST along RDATA to detect the end of packet and switch to the next completion routing. This will consume 1 bit along each data, but another solution could be to store ARLEN along ARID and use a counter to track the completion until the last data phase.