- Nexys A7 FPGA Board
- Xilinx Vivado
The wrapperProc.v file contains the top module which instantiates the SoC_Tile and provides it with the clock. The SoC tile generated by Scala has been updated by replacing the multi-dimensional arrays with Xilinx block RAM. The contents of the instruction memory can be updated by updating the main.mem file and then using the updatemem utility by executing the following command in the bitstream folder to generate a new bitstream named out.bit.
updatemem -force -debug -meminfo wrapperProc.mmi -data main.mem -bit wrapperProc.bit -proc proc/wb_inter_connect/imem/imem/IM/xpm_memory_spram_inst/xpm_memory_base_inst -out out.bit