diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py
index 956f4ce..901c766 100644
--- a/liteeth/phy/rmii.py
+++ b/liteeth/phy/rmii.py
@@ -65,9 +65,8 @@ def __init__(self, pads, clk_signal):
 
         # Output (Sync).
         # --------------
-        self.specials += SDROutput(i=converter.source.valid, o=pads.tx_en, clk=clk_signal)
-        for i in range(2):
-            self.specials += SDROutput(i=converter.source.data[i], o=pads.tx_data[i], clk=clk_signal)
+        self.specials += SDROutput(i=converter.source.valid, o=pads.tx_en,   clk=clk_signal)
+        self.specials += SDROutput(i=converter.source.data,  o=pads.tx_data, clk=clk_signal)
 
 
 # LiteEth PHY RMII RX ------------------------------------------------------------------------------
@@ -83,9 +82,8 @@ def __init__(self, pads, clk_signal):
         # -------------
         crs_dv_i  = Signal()
         rx_data_i = Signal(2)
-        self.specials += SDRInput(i=pads.crs_dv, o=crs_dv_i, clk=clk_signal)
-        for i in range(2):
-            self.specials += SDRInput(i=pads.rx_data[i], o=rx_data_i[i], clk=clk_signal)
+        self.specials += SDRInput(i=pads.crs_dv,  o=crs_dv_i,  clk=clk_signal)
+        self.specials += SDRInput(i=pads.rx_data, o=rx_data_i, clk=clk_signal)
 
         # Speed Timer for 10Mbps/100Mbps.
         # -------------------------------