From 3e4ef0fe3898d621d44d6c0e9f0f8b3b0968b512 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Wed, 15 Jan 2025 09:37:20 +0100 Subject: [PATCH] phy: rmii: use multibit io MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit now that https://github.com/enjoy-digital/litex/pull/2105 is merged, we can simplify the SDR IO in the rmii phy. Signed-off-by: Fin Maaß --- liteeth/phy/rmii.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/liteeth/phy/rmii.py b/liteeth/phy/rmii.py index 956f4ce..901c766 100644 --- a/liteeth/phy/rmii.py +++ b/liteeth/phy/rmii.py @@ -65,9 +65,8 @@ def __init__(self, pads, clk_signal): # Output (Sync). # -------------- - self.specials += SDROutput(i=converter.source.valid, o=pads.tx_en, clk=clk_signal) - for i in range(2): - self.specials += SDROutput(i=converter.source.data[i], o=pads.tx_data[i], clk=clk_signal) + self.specials += SDROutput(i=converter.source.valid, o=pads.tx_en, clk=clk_signal) + self.specials += SDROutput(i=converter.source.data, o=pads.tx_data, clk=clk_signal) # LiteEth PHY RMII RX ------------------------------------------------------------------------------ @@ -83,9 +82,8 @@ def __init__(self, pads, clk_signal): # ------------- crs_dv_i = Signal() rx_data_i = Signal(2) - self.specials += SDRInput(i=pads.crs_dv, o=crs_dv_i, clk=clk_signal) - for i in range(2): - self.specials += SDRInput(i=pads.rx_data[i], o=rx_data_i[i], clk=clk_signal) + self.specials += SDRInput(i=pads.crs_dv, o=crs_dv_i, clk=clk_signal) + self.specials += SDRInput(i=pads.rx_data, o=rx_data_i, clk=clk_signal) # Speed Timer for 10Mbps/100Mbps. # -------------------------------