From 715098f2f1a321fae82c00cc51d100d5ad9f194b Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Mon, 22 Jul 2024 12:23:47 +1000
Subject: [PATCH] soc/cores/i2c: add dts support

Will require target integration
---
 litex/soc/cores/i2c.py | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/litex/soc/cores/i2c.py b/litex/soc/cores/i2c.py
index 702b35c228..4b4596b02a 100644
--- a/litex/soc/cores/i2c.py
+++ b/litex/soc/cores/i2c.py
@@ -10,7 +10,8 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
-from litex.gen import *
+
+from litex.gen import LiteXModule, dts_property
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr_eventmanager import *
 
@@ -203,6 +204,10 @@ def __init__(self, clock_width):
 #     ("idle",  1),
 # ])
 class I2CMaster(LiteXModule):
+    dts_compatible = "litex,cores-i2c" # litex,i2c is used for bitbang.I2CMaster()
+    dts_properties = dts_property("#address-cells", 1)
+    dts_properties += dts_property("#size-cells", 0)
+
     def __init__(self, pads, bus=None):
         if bus is None:
             bus = wishbone.Interface(data_width=32)