diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 8fc806fa2e..394485f759 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1473,6 +1473,7 @@ def add_identifier(self, name="identifier", identifier="LiteX SoC", with_build_t
         else:
             self.add_config("BIOS_NO_BUILD_TIME")
         self.add_module(name=name, module=Identifier(identifier))
+        self.add_constant(name, identifier)
 
     # Add UART -------------------------------------------------------------------------------------
     def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=16):
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 14e3b53bed..34a430bfca 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -247,7 +247,6 @@ def __init__(self, platform, clk_freq,
         # Add Identifier.
         if ident != "":
             self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
-            self.add_constant("identifier", ident)
 
         # Add UARTBone.
         if with_uartbone: