[Xtensa] Add Boolean Extension feature

Boolean Extension support consists of:
- v1i1 boolean vector type backed by BR boolean register class
- calling convection for boolean variables
- boolean instructions implementing logical operators
- truncation and zero-extension operations for conversion to scalars
- register spill and fill logic

Author: maciej-czekaj

clang/lib/Basic/Targets/Xtensa.cpp

@@ -75,6 +75,7 @@ bool XtensaTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("fp", HasFP)
       .Case("windowed", HasWindowed)
+      .Case("bool", HasBoolean)
       .Default(false);
 }
 
@@ -84,6 +85,8 @@ bool XtensaTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   for (const auto &Feature : Features) {
     if (Feature == "+fp")
       HasFP = true;
+    else if (Feature == "+bool")
+      HasBoolean = true;
     else if (Feature == "+windowed")
       HasWindowed = true;
   }

clang/lib/Basic/Targets/Xtensa.h

@@ -33,6 +33,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo {
   std::string CPU;
   bool HasFP = false;
   bool HasWindowed = false;
+  bool HasBoolean = false;
 
 public:
   XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
@@ -49,7 +50,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo {
     WIntType = UnsignedInt;
     UseZeroLengthBitfieldAlignment = true;
     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
-    resetDataLayout("e-m:e-p:32:32-i64:64-i128:128-n32");
+    resetDataLayout("e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32");
   }
 
   void getTargetDefines(const LangOptions &Opts,

clang/lib/CodeGen/Targets/Xtensa.cpp

@@ -98,6 +98,13 @@ ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty,
     return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
   }
 
+  // xtbool
+  if (getTarget().hasFeature("bool") && Size == 1 && Ty->isVectorType()) {
+    llvm::Type *ResType =
+        llvm::FixedVectorType::get(llvm::Type::getInt1Ty(getVMContext()), 1);
+    return ABIArgInfo::getDirect(ResType);
+  }
+
   // Aggregates which are <= 6*32 will be passed in registers if possible,
   // so coerce to integers.
   if ((Size <= (MaxNumArgGPRs * 32)) && (!MustUseStack)) {

llvm/lib/Target/Xtensa/XtensaCallingConv.td

@@ -14,11 +14,15 @@
 class CCIfAlign<string Align, CCAction A>
   : CCIf<!strconcat("ArgFlags.getNonZeroOrigAlign() == ", Align), A>;
 
+class CCIfFeature<string Feature, CCAction A>:
+  CCIf<!strconcat("State.getMachineFunction().getSubtarget<XtensaSubtarget>().has", Feature, "()"), A>;
+
 //===----------------------------------------------------------------------===//
 // Xtensa return value calling convention
 //===----------------------------------------------------------------------===//
 def RetCC_Xtensa : CallingConv<[
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+  CCIfFeature<"Boolean",CCIfType<[v1i1], CCAssignToReg<[B0]>>>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
 
   //First two return values go in a2, a3, a4, a5
@@ -39,6 +43,7 @@ def CSRWE_Xtensa : CalleeSavedRegs<(add)> {
 
 def RetCCW_Xtensa : CallingConv<[
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+  CCIfFeature<"Boolean",CCIfType<[v1i1], CCAssignToReg<[B0]>>>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
 
   //First two return values go in a10, a11, a12, a13

llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp

@@ -375,15 +375,32 @@ void XtensaFrameLowering::processFunctionBeforeFrameFinalized(
     MachineFunction &MF, RegScavenger *RS) const {
   const XtensaSubtarget &STI = MF.getSubtarget<XtensaSubtarget>();
 
+  // Presence of SPILL_* pseudo-instructions requires spill slots
+  int NeedRegs = 0;
+  for (const MachineBasicBlock &MBB : MF) {
+    for (const MachineInstr &MI : MBB) {
+      unsigned Opcode = MI.getOpcode();
+      if (Opcode == Xtensa::SPILL_BOOL)
+        NeedRegs += 1;
+
+      if (Opcode == Xtensa::RESTORE_BOOL)
+        NeedRegs += 3;
+    }
+  }
+  NeedRegs = std::min(16, NeedRegs);
+
   // In WinABI mode add register scavenging slot
   // FIXME: It may be posssible to add spill slot by more optimal way
   if (STI.isWinABI() &&
-      (MF.getFrameInfo().estimateStackSize(MF) > STACK_SIZE_THRESHOLD)) {
+      ((MF.getFrameInfo().estimateStackSize(MF) > STACK_SIZE_THRESHOLD) ||
+      (NeedRegs > 0))) {
     MachineFrameInfo &MFI = MF.getFrameInfo();
     const TargetRegisterClass &RC = Xtensa::ARRegClass;
     const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
     unsigned Size = TRI.getSpillSize(RC);
     Align Alignment = TRI.getSpillAlign(RC);
-    RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false));
+    for (int i = 0; i < NeedRegs; i++)
+      RS->addScavengingFrameIndex(
+          MFI.CreateStackObject(Size, Alignment, false));
   }
 }

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

@@ -64,6 +64,16 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
     addRegisterClass(MVT::f32, &Xtensa::FPRRegClass);
   }
 
+  if (Subtarget.hasBoolean()) {
+    addRegisterClass(MVT::v1i1, &Xtensa::BRRegClass);
+    setOperationAction(ISD::Constant, MVT::v1i1, Expand);
+    for (MVT VT : MVT::integer_valuetypes()) {
+      setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v1i1, Promote);
+      setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v1i1, Promote);
+      setLoadExtAction(ISD::EXTLOAD, VT, MVT::v1i1, Promote);
+    }
+  }
+
   // Set up special registers.
   setStackPointerRegisterToSaveRestore(Xtensa::SP);
 
@@ -768,6 +778,11 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT,
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
   static const MCPhysReg IntRegs[] = {Xtensa::A2, Xtensa::A3, Xtensa::A4,
                                       Xtensa::A5, Xtensa::A6, Xtensa::A7};
+  static const MCPhysReg BoolRegs[] = {
+      Xtensa::B0,  Xtensa::B1,  Xtensa::B2,  Xtensa::B3,
+      Xtensa::B4,  Xtensa::B5,  Xtensa::B6,  Xtensa::B7,
+      Xtensa::B8,  Xtensa::B9,  Xtensa::B10, Xtensa::B11,
+      Xtensa::B12, Xtensa::B13, Xtensa::B14, Xtensa::B15};
 
   if (ArgFlags.isByVal()) {
     Align ByValAlign = ArgFlags.getNonZeroByValAlign();
@@ -824,6 +839,9 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT,
       Reg = State.AllocateReg(IntRegs);
     State.AllocateReg(IntRegs);
     LocVT = MVT::i32;
+  } else if (ValVT == MVT::v1i1) {
+    Reg = State.AllocateReg(BoolRegs);
+    LocVT = ValVT;
   } else
     llvm_unreachable("Cannot handle this ValVT.");
 
@@ -918,6 +936,8 @@ SDValue XtensaTargetLowering::LowerFormalArguments(
 
       if (RegVT == MVT::i32) {
         RC = &Xtensa::ARRegClass;
+      } else if (RegVT == MVT::v1i1) {
+        RC = &Xtensa::BRRegClass;
       } else
         llvm_unreachable("RegVT not supported by FormalArguments Lowering");
 
@@ -3403,6 +3423,27 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
     }
     return MBB;
   }
+  case Xtensa::MOVBA_P: {
+    const TargetRegisterClass *AR = getRegClassFor(MVT::i32);
+
+    Register Dst1 = MRI.createVirtualRegister(AR);
+    Register Dst2 = MRI.createVirtualRegister(AR);
+    MachineOperand Breg = MI.getOperand(0);
+    MachineOperand Src = MI.getOperand(1);
+
+    /*
+      MOVBA_P2 Breg, Dst1, Dest2, Src
+    */
+
+    BuildMI(*MBB, MI, DL, TII.get(Xtensa::MOVBA_P2), Breg.getReg())
+        .addReg(Dst1, RegState::Define | RegState::EarlyClobber)
+        .addReg(Dst2, RegState::Define | RegState::EarlyClobber)
+        .addReg(Src.getReg());
+
+    MI.eraseFromParent();
+
+    return MBB;
+  }
   default:
     return EmitDSPInstrWithCustomInserter(MI, MBB, TII, MF, MRI, DL);
     // llvm_unreachable("Unexpected instr type to insert");

llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp

@@ -105,7 +105,13 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   else if (STI.hasSingleFloat() && Xtensa::ARRegClass.contains(SrcReg) &&
            Xtensa::FPRRegClass.contains(DestReg))
     Opcode = Xtensa::WFR;
-  else
+  else if (STI.hasBoolean() && Xtensa::BRRegClass.contains(SrcReg) &&
+           Xtensa::BRRegClass.contains(DestReg)) {
+    BuildMI(MBB, MBBI, DL, get(Xtensa::ORB), DestReg)
+        .addReg(SrcReg, getKillRegState(KillSrc))
+        .addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  } else
     llvm_unreachable("Impossible reg-to-reg copy");
 
   BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
@@ -148,6 +154,9 @@ void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
   } else if (RC == &Xtensa::FPRRegClass) {
     LoadOpcode = Xtensa::LSI;
     StoreOpcode = Xtensa::SSI;
+  } else if (RC == &Xtensa::BRRegClass) {
+    LoadOpcode = Xtensa::RESTORE_BOOL;
+    StoreOpcode = Xtensa::SPILL_BOOL;
   } else
     llvm_unreachable("Unsupported regclass to load or store");
 }

llvm/lib/Target/Xtensa/XtensaInstrInfo.td

@@ -892,6 +892,11 @@ def ROTW : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins imm8n_7:$imm),
 //===----------------------------------------------------------------------===//
 // Boolean Instructions
 //===----------------------------------------------------------------------===//
+class BIN_PAT<SDPatternOperator node, Instruction inst,
+  ValueType src_vt, ValueType dst_vt = src_vt> 
+  : Pat<(dst_vt (node src_vt:$f1, src_vt:$f2)),
+        (inst src_vt:$f1, src_vt:$f2)>;
+
 
 def ALL4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s),
                    "all4\t$t, $s", []>, Requires<[HasBoolean]> {
@@ -907,6 +912,12 @@ def ANDB : RRR_Inst<0x00, 0x02, 0x00, (outs BR:$r), (ins BR:$s, BR:$t),
                    "andb\t$r, $s, $t", []>, Requires<[HasBoolean]>;
 def ANDBC : RRR_Inst<0x00, 0x02, 0x01, (outs BR:$r), (ins BR:$s, BR:$t),
                     "andbc\t$r, $s, $t", []>, Requires<[HasBoolean]>;
+def ORB : RRR_Inst<0x00, 0x02, 0x02, (outs BR:$r), (ins BR:$s, BR:$t),
+                  "orb\t$r, $s, $t", []>, Requires<[HasBoolean]>;
+def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t),
+                   "orbc\t$r, $s, $t", []>, Requires<[HasBoolean]>;
+def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t),
+                   "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>;
 
 def ANY4 : RRR_Inst<0x00, 0x00, 0x00, (outs BR:$t), (ins BR:$s),
                    "any4\t$t, $s", []>, Requires<[HasBoolean]> {
@@ -942,21 +953,67 @@ let isBranch = 1, isTerminator = 1, Predicates = [HasBoolean] in {
   }
 }
 
-def MOVF : RRR_Inst<0x00, 0x03, 0x0C, (outs AR:$r), (ins AR:$s, BR:$t),
+let Constraints = "$dr = $r,@earlyclobber $dr" in {
+  def MOVF : RRR_Inst<0x00, 0x03, 0x0C, (outs AR:$dr), (ins AR:$r, AR:$s, BR:$t),
                    "movf\t$r, $s, $t", []>, Requires<[HasBoolean]>;
-def MOVT : RRR_Inst<0x00, 0x03, 0x0D, (outs AR:$r), (ins AR:$s, BR:$t),
-                   "movt\t$r, $s, $t", []>, Requires<[HasBoolean]>;
 
-def ORB : RRR_Inst<0x00, 0x02, 0x02, (outs BR:$r), (ins BR:$s, BR:$t),
-                  "orb\t$r, $s, $t", []>, Requires<[HasBoolean]>;
-def ORBC : RRR_Inst<0x00, 0x02, 0x03, (outs BR:$r), (ins BR:$s, BR:$t),
-                   "orbc\t$r, $s, $t", []>, Requires<[HasBoolean]>;
-def XORB : RRR_Inst<0x00, 0x02, 0x04, (outs BR:$r), (ins BR:$s, BR:$t),
-                   "xorb\t$r, $s, $t", []>, Requires<[HasBoolean]>;
+  def MOVT : RRR_Inst<0x00, 0x03, 0x0D, (outs AR:$dr), (ins AR:$r, AR:$s, BR:$t),
+                   "movt\t$r, $s, $t", []>, Requires<[HasBoolean]>;
+}
 
 def : Pat<(Xtensa_br_t BR:$b, bb:$target), (BT BR:$b, bb:$target)>;
 def : Pat<(Xtensa_br_f BR:$b, bb:$target), (BF BR:$b, bb:$target)>;
 
+let Predicates = [HasBoolean] in {
+
+  def OR_BR_PAT: BIN_PAT<or,ORB,v1i1>;
+  def XOR_BR_PAT: BIN_PAT<xor,XORB,v1i1>;
+  def AND_BR_PAT: BIN_PAT<and,ANDB,v1i1>;
+
+  // vselect C T F = C * T + ~C * F
+  def : Pat<(v1i1 (vselect v1i1:$c, v1i1:$t, v1i1:$f)),
+          (ORB (ANDB $t, $f), (ANDBC $f, $c))>;
+
+  
+  def MOVBA_P2: Pseudo<(outs BR:$r, AR:$x, AR:$y), (ins AR:$s),
+                        "!movba $r, $x, $y, $s", []> {
+    let Defs = [BREG];
+  }
+   
+  def MOVBA_P: Pseudo<(outs BR:$r), (ins AR:$s),
+                        "!movba $r, $s", []> {
+    let usesCustomInserter = 1;
+    let Defs = [BREG];
+    //let Uses = [BREG];
+  }
+
+  def EXTUI_BR_P: Pseudo<(outs AR:$r), (ins AR:$s, BR:$b),
+                        "!extui_br $r, $s, $b", []>;
+  def SLLI_BR_P: Pseudo<(outs AR:$r), (ins AR:$s, BR:$b),
+                        "!slli_br $r, $s, $b", []>;
+
+  def : Pat<(v1i1 (build_vector AR:$a)), (MOVBA_P AR:$a)>;
+
+  def : Pat<(i32 (vector_extract (v1i1 BR:$b), (i32 0))),
+            (EXTUI_BR_P (RSR BREG), BR:$b)>;
+
+  def : Pat<(v1i1 (load addr_ish1:$addr)), (MOVBA_P (L8UI mem8:$addr))>;
+
+  def : Pat<(store BR:$b, addr_ish1:$addr), (S8I (EXTUI_BR_P (RSR BREG), BR:$b), mem32:$addr)>;
+
+  def SPILL_BOOL: Pseudo<(outs), (ins BR:$b, mem8:$mem),
+                            "!spill_bool $b, $mem",[]> {
+    let mayStore = 1;
+  }
+
+  def RESTORE_BOOL: Pseudo<(outs BR:$out), (ins mem8:$mem),
+                            "!restore_bool $out, $mem",[]> {
+    let mayLoad = 1;
+    let Defs = [BREG];
+  }
+}
+
+
 //===----------------------------------------------------------------------===//
 // Floating-Point Instructions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Xtensa/XtensaOperators.td

@@ -25,9 +25,9 @@ def SDT_XtensaSelectCC            : SDTypeProfile<1, 5,
                                                   SDTCisVT<5, i32>]>;
 
 def SDT_XtensaMOVSP               : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, i32>]>;
-def SDT_XtensaBrBool              : SDTypeProfile<0, 2, [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]>;
+def SDT_XtensaBrBool              : SDTypeProfile<0, 2, [SDTCisVT<0, v1i1>, SDTCisVT<1, OtherVT>]>;
 def SDT_XtensaBrCCFP              : SDTypeProfile<0, 4, [SDTCisVT<0, i32>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, SDTCisVT<3, OtherVT>]>;
-def SDT_XtensaCmp                 : SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>;
+def SDT_XtensaCmp                 : SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, SDTCisVT<1, f32>, SDTCisVT<2, f32>]>;
 def SDT_XtensaMADD                : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, f32>]>;
 def SDT_XtensaMOVS                : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisVT<0, f32>]>;
 def SDT_XtensaSelectCCFP          : SDTypeProfile<1, 5, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>;