- ELEC4609 - Integrated Circuit Design and Fabrication, Carleton University
- Digital Project: Static Logic PRSG (Pseudo Random Sequence Generator)
- Source design
- Die shots
- Post-fab test results
It turns out that being too spatially optimized is not a good thing for chip fab and performance. This highly compact layout design leads to poor signal output later in the post-fab test. So play safe, don't push it too far. 😓