diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aa43404e8f0c..f1a8863bbe28 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -229,6 +229,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ tegra30-colibri.dtb \ + tegra30-lge-p880.dtb \ + tegra30-lge-p895.dtb \ tegra30-tec-ng.dtb \ tegra114-dalmore.dtb \ tegra124-apalis.dtb \ diff --git a/arch/arm/dts/tegra30-lge-p880.dts b/arch/arm/dts/tegra30-lge-p880.dts new file mode 100644 index 000000000000..1db361084873 --- /dev/null +++ b/arch/arm/dts/tegra30-lge-p880.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "tegra30-lge-x3.dtsi" + +/ { + model = "LG Optimus 4X HD"; + compatible = "lge,p880", "nvidia,tegra30"; + + aliases { + mmc1 = &sdmmc3; /* uSD slot */ + }; + + host1x@50000000 { + status = "okay"; + dc@54200000 { + status = "okay"; + rgb { + status = "okay"; + + nvidia,panel = <&bridge>; + + display-timings { + timing@0 { + /* 1280x720@60Hz */ + clock-frequency = <68000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <92>; + hback-porch = <62>; + hsync-len = <4>; + vsync-len = <1>; + vfront-porch = <6>; + vback-porch = <3>; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + gpio-keyboard { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "jdi,dx12d100vm0eaa"; + + enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + bridge-spi = <&spi_bus>; + }; +}; diff --git a/arch/arm/dts/tegra30-lge-p895.dts b/arch/arm/dts/tegra30-lge-p895.dts new file mode 100644 index 000000000000..a17261059b77 --- /dev/null +++ b/arch/arm/dts/tegra30-lge-p895.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "tegra30-lge-x3.dtsi" + +/ { + model = "LG Optimus Vu"; + compatible = "lge,p895", "nvidia,tegra30"; + + host1x@50000000 { + status = "okay"; + dc@54200000 { + status = "okay"; + rgb { + status = "okay"; + + nvidia,panel = <&bridge>; + + display-timings { + timing@0 { + /* 1024x768@60Hz */ + clock-frequency = <62000000>; + hactive = <768>; + vactive = <1024>; + hfront-porch = <116>; + hback-porch = <81>; + hsync-len = <5>; + vsync-len = <2>; + vfront-porch = <24>; + vback-porch = <8>; + }; + }; + }; + }; + }; + + gpio-keyboard { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "hitachi,tx13d100vm0eaa"; + + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + vcc-supply = <&vcc_3v0_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + backlight = <&backlight>; + bridge-spi = <&spi_bus>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vcc_3v0_lcd: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vcc_3v0_lcd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + iovcc_1v8_lcd: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "iovcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-lge-x3.dtsi b/arch/arm/dts/tegra30-lge-x3.dtsi new file mode 100644 index 000000000000..261382994136 --- /dev/null +++ b/arch/arm/dts/tegra30-lge-x3.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include + +#include "tegra30.dtsi" + +/ { + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c1 = &gen2_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + spi0 = &dsi_spi; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + backlight: lm3533@36 { + compatible = "ti,lm3533"; + reg = <0x36>; + + enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + }; + + muic@44 { + compatible = "maxim,max14526-muic"; + reg = <0x44>; + + maxim,ap-usb; + + usif-gpios = <&gpio TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>; + dp2t-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>; + }; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max77663@1c { + compatible = "maxim,max77663"; + reg = <0x1c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + regulators { + vdd_1v8_vio: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_usd: ldo3 { + regulator-name = "vdd_sdmmc3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + dsi_spi: spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + + spi_bus: bridge-spi@2 { + compatible = "lge,bridge-spi"; + reg = <2>; + + spi-cpol; + spi-cpha; + + spi-max-frequency = <1000000>; + }; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + micro_usb: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keyboard { + compatible = "gpio-kbd"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + bridge: bridge { + compatible = "solomon,ssd2825"; + + enable-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>; + + panel = <&panel>; + }; +}; diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 229443b3d4f6..dab932c4b54a 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -28,6 +28,10 @@ config TARGET_TRANSFORMER_T30 bool "Asus Tegra30 Transformer board" select BOARD_LATE_INIT +config TARGET_X3_T30 + bool "LG X3 Tegra30 board" + select BOARD_LATE_INIT + endchoice config SYS_SOC @@ -39,5 +43,6 @@ source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" source "board/toradex/colibri_t30/Kconfig" source "board/avionic-design/tec-ng/Kconfig" +source "board/lg/x3-t30/Kconfig" endif diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig new file mode 100644 index 000000000000..20ea4f5f3243 --- /dev/null +++ b/board/lg/x3-t30/Kconfig @@ -0,0 +1,26 @@ +if TARGET_X3_T30 + +config SYS_BOARD + default "x3-t30" + +config SYS_VENDOR + default "lg" + +config SYS_CONFIG_NAME + default "x3-t30" + +config DEVICE_P880 + bool "Enable support for LG Optimus 4X HD" + default n + help + LG Optimus 4X HD derives from x3 board but has slight + differences. + +config DEVICE_P895 + bool "Enable support for LG Optimus Vu" + default n + help + LG Optimus Vu derives from x3 board but has slight + differences. + +endif diff --git a/board/lg/x3-t30/MAINTAINERS b/board/lg/x3-t30/MAINTAINERS new file mode 100644 index 000000000000..707efe39d474 --- /dev/null +++ b/board/lg/x3-t30/MAINTAINERS @@ -0,0 +1,6 @@ +X3 BOARD +M: Svyatoslav Ryhel +S: Maintained +F: board/lg/x3-t30/ +F: include/configs/x3-t30.h +F: configs/x3_t30_defconfig diff --git a/board/lg/x3-t30/Makefile b/board/lg/x3-t30/Makefile new file mode 100644 index 000000000000..623b3cf2db20 --- /dev/null +++ b/board/lg/x3-t30/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation +# +# (C) Copyright 2021 +# Svyatoslav Ryhel + +obj-$(CONFIG_SPL_BUILD) += x3-t30-spl.o + +obj-y += x3-t30.o x3-late.o diff --git a/board/lg/x3-t30/pinmux-config-x3.h b/board/lg/x3-t30/pinmux-config-x3.h new file mode 100644 index 000000000000..f5df322324e7 --- /dev/null +++ b/board/lg/x3-t30/pinmux-config-x3.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2021, Svyatoslav Ryhel. + */ + +#ifndef _PINMUX_CONFIG_X3_H_ +#define _PINMUX_CONFIG_X3_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +static struct pmux_pingrp_config tegra3_x3_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ +// DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), // device specific + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), +// LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), // device specific + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* HDMI-CEC pinmux */ + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0_PO1, SPI3, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, SPI3, UP, NORMAL, OUTPUT), // LCD_BRIDGE_RESET_N + DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, SPI3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT), +// DEFAULT_PINMUX(ULPI_DATA5_PO6, SPI2, UP, TRISTATE, INPUT), // unconfigured +// DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, UP, NORMAL, INPUT), // unconfigured + DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, DOWN, NORMAL, OUTPUT), // LCD_EN + DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT), + + /* DAP3 pinmux */ + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD2, DOWN, NORMAL, INPUT), + + /* CLK2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, OUTPUT), + + /* LCD pinmux */ + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), // unconfigured + DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDI + DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDO + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_CS + DEFAULT_PINMUX(LCD_DC0_PN6, RSVD3, NORMAL, NORMAL, OUTPUT), // LCD_CP_EN / BL + DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SCL + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_PCLK + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_HSYNC + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_VSYNC + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, OUTPUT), // LCD_RESET_N + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), // LCD_MAKER_ID + DEFAULT_PINMUX(LCD_DC1_PD2, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD2, NORMAL, NORMAL, INPUT), + + /* VI-group pinmux */ + LV_PINMUX(VI_D0_PT4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11_PT3, RSVD2, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* UART-B pinmux */ +// DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), // device specific + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + + /* UART-C pinmux */ + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + + /* PU-gpio group pinmux */ +// DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), // device specific +// DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), // device specific +// DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), // device specific +// DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), // device specific + DEFAULT_PINMUX(PU5, RSVD4, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, PWM3, DOWN, NORMAL, INPUT), + + /* DAP4 pinmux */ + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + + /* CLK3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), // MIPI_BRIDGE_CLK + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // device specific + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PCC2, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, KBC, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), + + /* CLK */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT), +// DEFAULT_PINMUX(CORE_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(CPU_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(PWR_INT_N, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(CLK_32K_IN, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + /* DAP1 pinmux */ + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + + /* CLK1 pinmux */ + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, DOWN, NORMAL, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), // device specific + + /* DAP2 pinmux */ + DEFAULT_PINMUX(DAP2_FS_PA2, HDA, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, HDA, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, HDA, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, HDA, DOWN, NORMAL, INPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI2, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), // device specific +// DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), // device specific + DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_MISO_PX1, GMI, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI6, UP, NORMAL, INPUT), // unconfigured +// DEFAULT_PINMUX(SPI2_SCK_PX2, SPI6, UP, NORMAL, INPUT), // unconfigured + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), +// DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), // unconfigured + + /* PEX pinmux */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, TRISTATE, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WAIT_PI7, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, TRISTATE, INPUT), // LCD_RGB_DE + DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), // device specific + DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, UP, NORMAL, INPUT), +// DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), // device specific + DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, GMI, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14_PH6, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD15_PH7, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, NORMAL, OUTPUT), // RGB_IC_EN + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_RST_N_PI4, GMI, UP, NORMAL, INPUT), +}; + +#ifdef CONFIG_DEVICE_P880 +static struct pmux_pingrp_config tegra3_p880_pinmux[] = { + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, TRISTATE, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, NORMAL, NORMAL, INPUT), + + /* UART-B pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, UP, NORMAL, OUTPUT), + + /* GPIO group pinmux */ + DEFAULT_PINMUX(PU0, UARTA, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU1, UARTA, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PU2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB0, I2S4, NORMAL, TRISTATE, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, UP, TRISTATE, OUTPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, DOWN, NORMAL, OUTPUT), +}; +#endif /* CONFIG_DEVICE_P880 */ + +#ifdef CONFIG_DEVICE_P895 +static struct pmux_pingrp_config tegra3_p895_pinmux[] = { + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), + + /* UART-B pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + + /* Gpio group pinmux */ + DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // LCD_EN_3V0 + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), + + /* SPI pinmux */ + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), + + /* GMI pinmux */ + DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), +}; +#endif /* CONFIG_DEVICE_P895 */ +#endif /* _PINMUX_CONFIG_X3_H_ */ diff --git a/board/lg/x3-t30/x3-late.c b/board/lg/x3-t30/x3-late.c new file mode 100644 index 000000000000..2946908478ff --- /dev/null +++ b/board/lg/x3-t30/x3-late.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 + * Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TEGRA_FUSE_BASE 0x7000F800 +#define TEGRA_CAR_BASE 0x60006000 + +#define FUSE_VENDOR_CODE 0x200 +#define FUSE_FAB_CODE 0x204 +#define FUSE_LOT_CODE_0 0x208 +#define FUSE_LOT_CODE_1 0x20c +#define FUSE_WAFER_ID 0x210 +#define FUSE_X_COORDINATE 0x214 +#define FUSE_Y_COORDINATE 0x218 + +#define FUSE_VENDOR_CODE_MASK 0xf +#define FUSE_FAB_CODE_MASK 0x3f +#define FUSE_WAFER_ID_MASK 0x3f +#define FUSE_X_COORDINATE_MASK 0x1ff +#define FUSE_Y_COORDINATE_MASK 0x1ff + +static u32 tegra_fuse_readl(unsigned long offset) +{ + return readl(TEGRA_FUSE_BASE + offset); +} + +static void tegra_set_fuse(void) +{ + u32 reg; + + gpio_request(TEGRA_GPIO(K, 7), "fuse_en"); + gpio_direction_output(TEGRA_GPIO(K, 7), 0); + gpio_set_value(TEGRA_GPIO(K, 7), 1); + + reg = readl_relaxed(TEGRA_CAR_BASE + 0x48); + reg |= BIT(28); + writel(reg, TEGRA_CAR_BASE + 0x48); + + /* + * Enable FUSE clock. This needs to be hardcoded because the clock + * subsystem is not active during early boot. + */ + reg = readl(TEGRA_CAR_BASE + 0x14); + reg |= BIT(7); + writel(reg, TEGRA_CAR_BASE + 0x14); +} + +static unsigned long long tegra_chip_uid(void) +{ + u64 uid = 0ull; + u32 reg; + u32 cid; + u32 vendor; + u32 fab; + u32 lot; + u32 wafer; + u32 x; + u32 y; + u32 i; + + tegra_set_fuse(); + + /* This used to be so much easier in prior chips. Unfortunately, there + is no one-stop shopping for the unique id anymore. It must be + constructed from various bits of information burned into the fuses + during the manufacturing process. The 64-bit unique id is formed + by concatenating several bit fields. The notation used for the + various fields is with the UID composed + thusly: + + Where: + Field Bits Position Data + ------- ---- -------- ---------------------------------------- + CID 4 60 Chip id + VENDOR 4 56 Vendor code + FAB 6 50 FAB code + LOT 26 24 Lot code (5-digit base-36-coded-decimal, + re-encoded to 26 bits binary) + WAFER 6 18 Wafer id + X 9 9 Wafer X-coordinate + Y 9 0 Wafer Y-coordinate + ------- ---- + Total 64 + */ + + /* chip id is 0 for tegra 3 */ + cid = 0; + + vendor = tegra_fuse_readl(FUSE_VENDOR_CODE) & FUSE_VENDOR_CODE_MASK; + fab = tegra_fuse_readl(FUSE_FAB_CODE) & FUSE_FAB_CODE_MASK; + + /* Lot code must be re-encoded from a 5 digit base-36 'BCD' number + to a binary number. */ + lot = 0; + reg = tegra_fuse_readl(FUSE_LOT_CODE_0) << 2; + + for (i = 0; i < 5; ++i) { + u32 digit = (reg & 0xFC000000) >> 26; + lot *= 36; + lot += digit; + reg <<= 6; + } + + wafer = tegra_fuse_readl(FUSE_WAFER_ID) & FUSE_WAFER_ID_MASK; + x = tegra_fuse_readl(FUSE_X_COORDINATE) & FUSE_X_COORDINATE_MASK; + y = tegra_fuse_readl(FUSE_Y_COORDINATE) & FUSE_Y_COORDINATE_MASK; + + uid = ((unsigned long long)cid << 60ull) + | ((unsigned long long)vendor << 56ull) + | ((unsigned long long)fab << 50ull) + | ((unsigned long long)lot << 24ull) + | ((unsigned long long)wafer << 18ull) + | ((unsigned long long)x << 9ull) + | ((unsigned long long)y << 0ull); + + return uid; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* First 3 bytes refer to LG vendor */ + u8 btmacaddr[6] = { 0x00, 0x00, 0x00, 0xD0, 0xC9, 0x88 }; + + /* Generate device 3 bytes based on chip sd */ + u64 bt_device = tegra_chip_uid() >> 24ull; + + btmacaddr[0] = bt_device & 0x0F; + btmacaddr[1] = (bt_device >> 6) & 0x0F; + btmacaddr[2] = (bt_device >> 12) & 0x0F; + + /* Set BT MAC address */ + fdt_find_and_setprop(blob, "/serial@70006200/bluetooth", + "local-bd-address", btmacaddr, 6, 1); + return 0; +} +#endif + +void nvidia_board_late_init(void) +{ + char serialno_str[17]; + + /* Set chip id as serialno */ + sprintf(serialno_str, "%016llx", tegra_chip_uid()); + env_set("serial#", serialno_str); + env_set("platform", "Tegra 3 T30"); +} diff --git a/board/lg/x3-t30/x3-t30-spl.c b/board/lg/x3-t30/x3-t30-spl.c new file mode 100644 index 000000000000..a7be429e3e19 --- /dev/null +++ b/board/lg/x3-t30/x3-t30-spl.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * T30 LGE X3 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2022 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +/* I2C addr is in 8 bit */ +#define MAX77663_I2C_ADDR 0x38 + +#define MAX77663_REG_SD0 0x16 +#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) +#define MAX77663_REG_SD1 0x17 +#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) +#define MAX77663_REG_LDO4 0x2B +#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) + +#define MAX77620_REG_GPIO1 0x37 +#define MAX77620_REG_GPIO1_DATA (0x0800 | MAX77620_REG_GPIO1) +#define MAX77620_REG_GPIO4 0x3A +#define MAX77620_REG_GPIO4_DATA (0x0100 | MAX77620_REG_GPIO4) + +void enable_pmic_cpu_power(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write_addr(MAX77663_I2C_ADDR, 2); + tegra_i2c_ll_write_data(MAX77663_REG_SD1_DATA, I2C_SEND_2_BYTES); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write_addr(MAX77663_I2C_ADDR, 2); + tegra_i2c_ll_write_data(MAX77663_REG_SD0_DATA, I2C_SEND_2_BYTES); + udelay(1000); + + /* Bring up VDD_RTC to 1.200V. */ + tegra_i2c_ll_write_addr(MAX77663_I2C_ADDR, 2); + tegra_i2c_ll_write_data(MAX77663_REG_LDO4_DATA, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* Set GPIO4 and GPIO1 states */ + tegra_i2c_ll_write_addr(MAX77663_I2C_ADDR, 2); + tegra_i2c_ll_write_data(MAX77620_REG_GPIO4_DATA, I2C_SEND_2_BYTES); + tegra_i2c_ll_write_data(MAX77620_REG_GPIO1_DATA, I2C_SEND_2_BYTES); +} diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c new file mode 100644 index 000000000000..01658f94c879 --- /dev/null +++ b/board/lg/x3-t30/x3-t30.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2022 + * Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pinmux-config-x3.h" + +#ifdef CONFIG_TEGRA_CRYPTO +#include +#include "uboot_aes.h" +#endif + +#define PMC_CLK_OUT_CNTRL_0 0x01A8 + +#define MAX77663_I2C_ADDR 0x1C /* 7 bit */ +#define MAX77663_REG_SD2 0x18 +#define MAX77663_REG_LDO2 0x27 +#define MAX77663_REG_LDO3 0x29 +#define MAX77663_REG_LDO5 0x2D +#define MAX77663_REG_ONOFF_CFG1 0x41 +#define MAX77663_ONOFF_PWR_OFF 0x02 + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev); + if (ret) { + printf("%s: Cannot find PMIC I2C chip\n", __func__); + return 0; + } + + ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= MAX77663_ONOFF_PWR_OFF; + + ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1); + if (ret) + return ret; + + /* wait some time and then print error */ + mdelay(5000); + + printf("Failed to power off!!!\n"); + return 1; +} +#endif + +#ifdef CONFIG_TEGRA_CRYPTO +/* + * Pass sbk for boards where it is common + */ +void get_secure_key(u8 *key) +{ + /* SBK is device/board specific */ +#ifdef CONFIG_DEVICE_P880 + u8 sbk[AES128_KEY_LENGTH] = { + 0xc1, 0x82, 0x69, 0xee, 0x09, 0x00, 0xce, 0x58, + 0x48, 0x2a, 0xbe, 0x34, 0xbf, 0xf1, 0xbc, 0x01 + }; +#endif +#ifdef CONFIG_DEVICE_P895 + u8 sbk[AES128_KEY_LENGTH] = { + 0x95, 0x08, 0x21, 0xad, 0x09, 0x64, 0xce, 0x58, + 0xfe, 0x98, 0xbe, 0x34, 0xbf, 0xf1, 0xac, 0x02 + }; +#endif + + memcpy(key, sbk, AES128_KEY_LENGTH); +} +#endif + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra3_x3_pinmux_common, + ARRAY_SIZE(tegra3_x3_pinmux_common)); + +#ifdef CONFIG_DEVICE_P880 + pinmux_config_pingrp_table(tegra3_p880_pinmux, + ARRAY_SIZE(tegra3_p880_pinmux)); +#endif + +#ifdef CONFIG_DEVICE_P895 + pinmux_config_pingrp_table(tegra3_p895_pinmux, + ARRAY_SIZE(tegra3_p895_pinmux)); +#endif +} + +#ifdef CONFIG_MMC_SDHCI_TEGRA +/* + * Do I2C/PMU writes to bring up SD card and eMMC bus power + */ +void board_sdmmc_voltage_init(void) +{ + struct udevice *dev; + uchar val; + int ret; + + ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev); + if (ret) { + debug("%s: Cannot find PMIC I2C chip\n", __func__); + return; + } + + /* 0x60 for 1.8v, bit7:0 = voltage */ + val = 0x60; + ret = dm_i2c_write(dev, MAX77663_REG_SD2, &val, 1); + if (ret) + printf("vdd_1v8_vio set failed: %d\n", ret); + + /* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77663_REG_LDO2, &val, 1); + if (ret) + printf("avdd_usb set failed: %d\n", ret); + + /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xEC; + ret = dm_i2c_write(dev, MAX77663_REG_LDO3, &val, 1); + if (ret) + printf("vdd_usd set failed: %d\n", ret); + + /* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xE9; + ret = dm_i2c_write(dev, MAX77663_REG_LDO5, &val, 1); + if (ret) + printf("vcore_emmc set failed: %d\n", ret); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up uSD and eMMC power */ + board_sdmmc_voltage_init(); +} +#endif /* MMC */ + +int nvidia_board_init(void) +{ + u32 value; + + clock_start_periph_pll(PERIPH_ID_EXTPERIPH3, CLOCK_ID_PERIPH, + 24 * 1000000); + clock_enable(PERIPH_ID_EXTPERIPH3); + udelay(5); + reset_set_enable(PERIPH_ID_EXTPERIPH3, 0); + + /* Configure clk_out_3 */ + value = tegra_pmc_readl(PMC_CLK_OUT_CNTRL_0); + tegra_pmc_writel(value | BIT(18) | BIT(22) | BIT(23), + PMC_CLK_OUT_CNTRL_0); + + return 0; +} diff --git a/configs/p880.config b/configs/p880.config new file mode 100644 index 000000000000..2c119e5d584f --- /dev/null +++ b/configs/p880.config @@ -0,0 +1,4 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-lge-p880" +CONFIG_DEVICE_P880=y +CONFIG_SYS_PROMPT="Tegra30 (P880) # " +CONFIG_PANEL_RENESAS_R69328=y diff --git a/configs/p895.config b/configs/p895.config new file mode 100644 index 000000000000..4275fc6fc1d9 --- /dev/null +++ b/configs/p895.config @@ -0,0 +1,4 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra30-lge-p895" +CONFIG_DEVICE_P895=y +CONFIG_SYS_PROMPT="Tegra30 (P895) # " +CONFIG_PANEL_KOE_TX13D100VM0EAA=y diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig new file mode 100644 index 000000000000..07e4987184da --- /dev/null +++ b/configs/x3_t30_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_SYS_TEXT_BASE=0x80110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra30-lge-x3" +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_TEGRA_CRYPTO=y +CONFIG_TEGRA_LEGACY_PT=y +CONFIG_TEGRA30=y +CONFIG_TARGET_X3_T30=y +CONFIG_SYS_LOAD_ADDR=0x81000000 +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_UART_PHYS=0x70006300 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80090000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra30 (x3) # " +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2084 +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_SPL_DM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SYS_I2C_TEGRA=y +CONFIG_GPIO_KEYBOARD=y +CONFIG_EXTCON_MAX14526=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="LGE" +CONFIG_USB_GADGET_VENDOR_NUM=0x1004 +CONFIG_USB_GADGET_PRODUCT_NUM=0x7100 +CONFIG_CI_UDC=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_TEGRA20=y +CONFIG_BACKLIGHT_LM3533=y +CONFIG_BRIDGE_SOLOMON_SSD2825=y +CONFIG_CONSOLE_RECORD=y +CONFIG_CONSOLE_RECORD_OUT_SIZE=0x10000 +CONFIG_FASTBOOT_CMD_OEM_CONSOLE=y +CONFIG_FASTBOOT_CMD_OEM_CMD=y diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h new file mode 100644 index 000000000000..d13ca15d47f0 --- /dev/null +++ b/include/configs/x3-t30.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2010,2012 + * NVIDIA Corporation + * + * (C) Copyright 2022 + * Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra30-common.h" + +#define X3_SD_LOAD_KERNEL \ + "echo Loading Kernel;" \ + "if load mmc ${bootdev}:${bootpart} ${kernel_addr_r} ${kernel_file};" \ + "then echo Loading DTB;" \ + "load mmc ${bootdev}:${bootpart} ${fdt_addr_r} ${fdtfile};" \ + "fdt addr ${fdt_addr_r};" \ + "fdt rm /firmware;" \ + "fdt rm /reserved-memory/trustzone@bfe00000;" \ + "echo Loading Initramfs;" \ + "if load mmc ${bootdev}:${bootpart} ${ramdisk_addr_r} ${ramdisk_file};" \ + "then echo Booting Kernel;" \ + "run bootrdkernel;" \ + "else echo Booting Kernel;" \ + "run bootkernel; fi;" + +#ifdef CONFIG_DEVICE_P880 +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "LG Optimus 4X HD" + +#define X3_BOOTMENU_3_4 \ + "bootmenu_3=mount microsd=usb start && ums 0 mmc 1; bootmenu\0" \ + "bootmenu_4=mount /cache=usb start && ums 0 mmc 0:4; bootmenu\0" + +#define X3_BOOTCOMMAND \ + "echo Loading from uSD...;" \ + "setenv bootargs console=ttyS0,115200n8 root=/dev/mmcblk1p2 rw gpt;" \ + "setenv bootdev 1;" \ + "setenv bootpart 1;" \ + X3_SD_LOAD_KERNEL \ + "else echo Loading from uSD failed!;" \ + "echo Loading from eMMC...;" \ + "setenv bootargs console=ttyS0,115200n8 root=/dev/mmcblk0p8 rw gpt;" \ + "setenv bootdev 0;" \ + "setenv bootpart 4;" \ + X3_SD_LOAD_KERNEL \ + "else echo Loading Kernel FAILED! Turning power off;" \ + "poweroff;" \ + "fi;" \ + "fi;" +#endif + +#ifdef CONFIG_DEVICE_P895 +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "LG Optimus Vu" + +#define X3_BOOTMENU_3_4 \ + "bootmenu_3=mount /boot=usb start && ums 0 mmc 0:4; bootmenu\0" \ + "bootmenu_4=mount /root=usb start && ums 0 mmc 0:8; bootmenu\0" + +#define X3_BOOTCOMMAND \ + "echo Loading from eMMC...;" \ + "setenv bootargs console=ttyS0,115200n8 root=/dev/mmcblk0p8 rw gpt;" \ + "setenv bootdev 0;" \ + "setenv bootpart 4;" \ + X3_SD_LOAD_KERNEL \ + "else echo Loading Kernel FAILED! Turning power off;" \ + "poweroff;" \ + "fi;" +#endif + +#define X3_BOOT_CUSTOM_KERNEL \ + "boot_custom_kernel=echo Loading Kernel;" \ + "load ${dev_type} ${mmcdev}:${mmcpart} ${kernel_addr_r} ${kernel_file};" \ + "echo Loading DTB;" \ + "load ${dev_type} ${mmcdev}:${mmcpart} ${fdt_addr_r} ${dtb_file};" \ + "fdt addr ${fdt_addr_r};" \ + "fdt rm /firmware;" \ + "fdt rm /reserved-memory/trustzone@bfe00000;" \ + "echo Loading Initramfs;" \ + "if load ${dev_type} ${mmcdev}:${mmcpart} ${ramdisk_addr_r} ${ramdisk_file};" \ + "then echo Booting Kernel;" \ + "run bootrdkernel;" \ + "else echo Booting Kernel;" \ + "run bootkernel; fi\0" + +#define X3_BOOT_SCRIPT \ + X3_BOOT_CUSTOM_KERNEL \ + "boot_script=echo Loading boot script;" \ + "if load mmc 0:4 ${scriptaddr} uboot-x3.bcs;" \ + "then env import -t -r ${scriptaddr} ${filesize};" \ + "run boot_custom_kernel;" \ + "else if load mmc 1:1 ${scriptaddr} uboot-x3.bcs;" \ + "then env import -t -r ${scriptaddr} ${filesize};" \ + "run boot_custom_kernel;" \ + "else echo Boot Configuration NOT FOUND!;" \ + "echo Press ANY key to return to bootmenu;" \ + "continue; bootmenu; fi;" \ + "fi\0" + +#define X3_BOOT_SOS \ + "boot_sos=echo Reading SOS partition;" \ + "mmc dev;" \ + "if mmc read ${kernel_addr_r} ${sos_offset_m} ${sos_size};" \ + "then echo Booting Kernel;" \ + "bootm ${kernel_addr_r};" \ + "else echo Reading SOS failed;" \ + "echo Press ANY key to return to bootmenu;" \ + "continue; bootmenu; fi\0" + +#define X3_BOOT_LNX \ + "boot_lnx=echo Reading LNX partition;" \ + "mmc dev;" \ + "if mmc read ${kernel_addr_r} ${lnx_offset_m} ${lnx_size};" \ + "then echo Booting Kernel;" \ + "bootm ${kernel_addr_r};" \ + "else echo Reading LNX failed;" \ + "echo Press ANY key to return to bootmenu;" \ + "continue; bootmenu; fi\0" + +#define X3_FLASH_UBOOT \ + "flash_uboot=echo Preparing RAM;" \ + "mw ${bct_addr_r} 0 ${bct_block_size_r};" \ + "mw ${ebt_addr_r} 0 ${ebt_block_size_r};" \ + "echo Reading BCT;" \ + "mmc dev 0 1;" \ + "mmc read ${bct_addr_r} 0 ${bct_block_size};" \ + "echo Reading bootloader;" \ + "if load mmc 0:4 ${ebt_addr_r} ${bootloader_file};" \ + "then echo Calculating bootloader size;" \ + "size mmc 0:4 ${bootloader_file};" \ + "ebtupdate ${bct_addr_r} ${ebt_addr_r} ${filesize};" \ + "echo Writing bootloader to eMMC;" \ + "mmc dev 0 1;" \ + "mmc write ${bct_addr_r} 0 ${bct_block_size};" \ + "mmc dev 0 2;" \ + "mmc write ${bct_addr_r} 0 ${bct_block_size};" \ + "mmc dev;" \ + "mmc write ${ebt_addr_r} ${ebt_block_shift} ${ebt_block_size};" \ + "echo Bootloader written successfully;" \ + "echo Press ANY key to reboot device; continue; reset;" \ + "else echo Reading bootloader failed;" \ + "echo Press ANY key to return to bootmenu; continue; bootmenu; fi\0" + +#define X3_BOOTMENU \ + X3_BOOT_SCRIPT \ + X3_BOOT_SOS \ + X3_BOOT_LNX \ + X3_FLASH_UBOOT \ + "bootmenu_0=boot with script=run boot_script\0" \ + "bootmenu_1=boot LNX=run boot_lnx\0" \ + "bootmenu_2=boot SOS=run boot_sos\0" \ + X3_BOOTMENU_3_4 \ + "bootmenu_5=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ + "bootmenu_6=update bootloader=run flash_uboot\0" \ + "bootmenu_7=reboot RCM=enterrcm\0" \ + "bootmenu_8=reboot=reset\0" \ + "bootmenu_9=power off=poweroff\0" \ + "bootmenu_delay=-1\0" + +#define X3_EMMC_LAYOUT \ + "bct_addr_r=0x81000000\0" \ + "bct_block_size_r=0x200000\0" \ + "bct_block_size=0x1000\0" \ + "ebt_addr_r=0x81200000\0" \ + "ebt_block_size_r=0x600000\0" \ + "ebt_block_size=0x3000\0" \ + "ebt_block_shift=0x1000\0" \ + "sos_offset_m=0x7000\0" \ + "sos_size=0x5000\0" \ + "lnx_offset_m=0xC000\0" \ + "lnx_size=0x5000\0" + +#define BOARD_EXTRA_ENV_SETTINGS \ + "kernel_file=vmlinuz\0" \ + "ramdisk_file=uInitrd\0" \ + "bootloader_file=u-boot-dtb-tegra.bin\0" \ + "bootkernel=bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "bootrdkernel=bootz ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ + "check_button=gpio input ${gpio_button}; test $? -eq 0\0" \ + X3_EMMC_LAYOUT \ + X3_BOOTMENU + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "setenv gpio_button 116;" \ + "if run check_button;" \ + "then bootmenu; else " \ + X3_BOOTCOMMAND \ + "fi;" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */