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Copy pathMMU_v1.qsf
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MMU_v1.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 15:03:44 September 10, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# MMU_v1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE15F23C8
set_global_assignment -name TOP_LEVEL_ENTITY F2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:03:44 SEPTEMBER 10, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VHDL_FILE MMU_v1.vhdl
set_global_assignment -name VECTOR_WAVEFORM_FILE RegSim.vwf
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE /home/codetector/projects/imsai/MMU_VHDL/RegSim.vwf
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VHDL_FILE Register.vhdl
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VECTOR_WAVEFORM_FILE "F-mul.vwf"
set_location_assignment PIN_T2 -to fi
set_location_assignment PIN_A19 -to out1
set_location_assignment PIN_A20 -to out2
set_location_assignment PIN_A18 -to rOUT
set_location_assignment PIN_A16 -to bOUT
set_location_assignment PIN_A17 -to gOUT
set_location_assignment PIN_A15 -to dbg1
set_location_assignment PIN_A14 -to dbg2
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to dbg1
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to dbg2
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to fi
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to gOUT
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to out1
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to out2
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to rOUT
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dbg1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dbg2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to out2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to out1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fi
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top