VGA_CLOCK_PLL.qip

set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "VGA_CLOCK_PLL.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "VGA_CLOCK_PLL_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "VGA_CLOCK_PLL_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "VGA_CLOCK_PLL.ppf"]