diff --git a/.github/CONTRIBUTING.md b/.github/CONTRIBUTING.md new file mode 100644 index 00000000..7dc24400 --- /dev/null +++ b/.github/CONTRIBUTING.md @@ -0,0 +1,51 @@ +# Contributing + +Contributions are welcome! + +## Adding a resource + +Most awesome lists are written in a single long Markdown file (see [awesome-list](https://github.com/topics/awesome-list)). However, in this repository each resource is described in a separate Markdown file (see [content/items](../content/items)). The frontmatter is used to provide data about the resource, while the body can contain a long description. The prototype of the frontmatter is the following: + +```yml +--- +title: "name of the tool" +description: "description" +author: ["first author", "second author"] +links: + gh: "https://github.com/user/repo" + gl: "https://gitlab.com/user/repo" + web: "https://example.com" + docs: "https://doc.example.com" +tags: [ + "a_tag", + "another_tag" +] +categories: [ + "a_category" +] +--- + +Long description of the resource +``` + +> NOTE: links are optional, and non-exclusive. + +Further guidelines: + +* Add one resource/file per pull request and explain why it is awesome. +* Keep descriptions in the frontmatter concise. +* See list of defined categories in [config.yml](../config.yml). + * Add a new category if needed. If done, a description of the category must be included. +* Regular chores: + * Search previous suggestions before making a new one. + * Check spelling and grammar. + * Remove any trailing whitespace. + +## Modifying the site/theme + +The website is built with [Hugo](https://github.com/gohugoio/hugo), using a theme based on [Bare Hugo](https://github.com/orf/bare-hugo-theme). The theme is a submodule of the `master` branch. However, at the same time, the customized version is hosted in branch `theme` of this same repo. Hence, users willing to contribute to the theme need to: + +- Clone this repo recursively, or `git submodule init` and `git submodule update`. +- Change directory to `themes/bare-hugo-theme`. +- Make changes, commit them and push a feature branch. +- Open a pull request againt branch `theme`, NOT `master`. \ No newline at end of file diff --git a/.github/workflows/site.yml b/.github/workflows/site.yml new file mode 100644 index 00000000..6c711c50 --- /dev/null +++ b/.github/workflows/site.yml @@ -0,0 +1,46 @@ +name: 'site' + +on: + push: + pull_request: + schedule: + - cron: '0 0 * * 5' + +jobs: + site: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v1 + with: + submodules: recursive + - name: Get Hugo and Theme + run: | + curl -fsSL https://github.com/gohugoio/hugo/releases/download/v0.62.1/hugo_extended_0.62.1_Linux-64bit.tar.gz | sudo tar xzf - -C /usr/local/bin hugo + sudo chmod +x /usr/local/bin/hugo + - name: Build site + run: | + hugo version + hugo + - uses: actions/upload-artifact@master + with: + name: site + path: public + - name: 'publish site to gh-pages' + if: github.event_name != 'pull_request' && github.repository == 'hdl/awesome' + env: + GH_DEPKEY: ${{ secrets.GHA_DEPLOY_KEY }} + run: | + cd public/ + touch .nojekyll + git init + git add . + git config --local user.email "push@gha" + git config --local user.name "GHA" + git commit -a -m "update ${{ github.sha }}" + git remote add origin "git@github.com:${{ github.repository }}" + eval `ssh-agent -t 60 -s` + echo "$GH_DEPKEY" | ssh-add - + mkdir -p ~/.ssh/ + ssh-keyscan github.com >> ~/.ssh/known_hosts + git push -u origin +HEAD:gh-pages + ssh-agent -k diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..aa2b2aa3 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "themes/bare-hugo-theme"] + path = themes/bare-hugo-theme + url = https://github.com/hdl/awesome diff --git a/LICENSE.md b/LICENSE.md new file mode 100644 index 00000000..76825073 --- /dev/null +++ b/LICENSE.md @@ -0,0 +1,41 @@ +# CC0 1.0 Universal + +CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE LEGAL SERVICES. DISTRIBUTION OF THIS DOCUMENT DOES NOT CREATE AN ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES REGARDING THE USE OF THIS DOCUMENT OR THE INFORMATION OR WORKS PROVIDED HEREUNDER, AND DISCLAIMS LIABILITY FOR DAMAGES RESULTING FROM THE USE OF THIS DOCUMENT OR THE INFORMATION OR WORKS PROVIDED HEREUNDER. + +### Statement of Purpose + +The laws of most jurisdictions throughout the world automatically confer exclusive Copyright and Related Rights (defined below) upon the creator and subsequent owner(s) (each and all, an "owner") of an original work of authorship and/or a database (each, a "Work"). + +Certain owners wish to permanently relinquish those rights to a Work for the purpose of contributing to a commons of creative, cultural and scientific works ("Commons") that the public can reliably and without fear of later claims of infringement build upon, modify, incorporate in other works, reuse and redistribute as freely as possible in any form whatsoever and for any purposes, including without limitation commercial purposes. These owners may contribute to the Commons to promote the ideal of a free culture and the further production of creative, cultural and scientific works, or to gain reputation or greater distribution for their Work in part through the use and efforts of others. + +For these and/or other purposes and motivations, and without any expectation of additional consideration or compensation, the person associating CC0 with a Work (the "Affirmer"), to the extent that he or she is an owner of Copyright and Related Rights in the Work, voluntarily elects to apply CC0 to the Work and publicly distribute the Work under its terms, with knowledge of his or her Copyright and Related Rights in the Work and the meaning and intended legal effect of CC0 on those rights. + +1. __Copyright and Related Rights.__ A Work made available under CC0 may be protected by copyright and related or neighboring rights ("Copyright and Related Rights"). Copyright and Related Rights include, but are not limited to, the following: + + i. the right to reproduce, adapt, distribute, perform, display, communicate, and translate a Work; + + ii. moral rights retained by the original author(s) and/or performer(s); + + iii. publicity and privacy rights pertaining to a person's image or likeness depicted in a Work; + + iv. rights protecting against unfair competition in regards to a Work, subject to the limitations in paragraph 4(a), below; + + v. rights protecting the extraction, dissemination, use and reuse of data in a Work; + + vi. database rights (such as those arising under Directive 96/9/EC of the European Parliament and of the Council of 11 March 1996 on the legal protection of databases, and under any national implementation thereof, including any amended or successor version of such directive); and + + vii. other similar, equivalent or corresponding rights throughout the world based on applicable law or treaty, and any national implementations thereof. + +2. __Waiver.__ To the greatest extent permitted by, but not in contravention of, applicable law, Affirmer hereby overtly, fully, permanently, irrevocably and unconditionally waives, abandons, and surrenders all of Affirmer's Copyright and Related Rights and associated claims and causes of action, whether now known or unknown (including existing as well as future claims and causes of action), in the Work (i) in all territories worldwide, (ii) for the maximum duration provided by applicable law or treaty (including future time extensions), (iii) in any current or future medium and for any number of copies, and (iv) for any purpose whatsoever, including without limitation commercial, advertising or promotional purposes (the "Waiver"). Affirmer makes the Waiver for the benefit of each member of the public at large and to the detriment of Affirmer's heirs and successors, fully intending that such Waiver shall not be subject to revocation, rescission, cancellation, termination, or any other legal or equitable action to disrupt the quiet enjoyment of the Work by the public as contemplated by Affirmer's express Statement of Purpose. + +3. __Public License Fallback.__ Should any part of the Waiver for any reason be judged legally invalid or ineffective under applicable law, then the Waiver shall be preserved to the maximum extent permitted taking into account Affirmer's express Statement of Purpose. In addition, to the extent the Waiver is so judged Affirmer hereby grants to each affected person a royalty-free, non transferable, non sublicensable, non exclusive, irrevocable and unconditional license to exercise Affirmer's Copyright and Related Rights in the Work (i) in all territories worldwide, (ii) for the maximum duration provided by applicable law or treaty (including future time extensions), (iii) in any current or future medium and for any number of copies, and (iv) for any purpose whatsoever, including without limitation commercial, advertising or promotional purposes (the "License"). The License shall be deemed effective as of the date CC0 was applied by Affirmer to the Work. Should any part of the License for any reason be judged legally invalid or ineffective under applicable law, such partial invalidity or ineffectiveness shall not invalidate the remainder of the License, and in such case Affirmer hereby affirms that he or she will not (i) exercise any of his or her remaining Copyright and Related Rights in the Work or (ii) assert any associated claims and causes of action with respect to the Work, in either case contrary to Affirmer's express Statement of Purpose. + +4. __Limitations and Disclaimers.__ + + a. No trademark or patent rights held by Affirmer are waived, abandoned, surrendered, licensed or otherwise affected by this document. + + b. Affirmer offers the Work as-is and makes no representations or warranties of any kind concerning the Work, express, implied, statutory or otherwise, including without limitation warranties of title, merchantability, fitness for a particular purpose, non infringement, or the absence of latent or other defects, accuracy, or the present or absence of errors, whether or not discoverable, all to the greatest extent permissible under applicable law. + + c. Affirmer disclaims responsibility for clearing rights of other persons that may apply to the Work or any use thereof, including without limitation any person's Copyright and Related Rights in the Work. Further, Affirmer disclaims responsibility for obtaining any necessary consents, permissions or other rights required for any use of the Work. + + d. Affirmer understands and acknowledges that Creative Commons is not a party to this document and has no duty or obligation with respect to this CC0 or use of the Work. diff --git a/README.md b/README.md new file mode 100644 index 00000000..d4f55b33 --- /dev/null +++ b/README.md @@ -0,0 +1,27 @@ +**This repository is in a very early planning phase, and it was uploaded in order to gather feedback from the community. This branch should be expected to be force-pushed without prior notice. We encourage users/contributors/collegues to open issues to bring up the matters for discussion before contributing modifications.** + +# Awesome resources for Hardware Description + +

+ + 'site' workflow Status + +

+ +A curated list of awesome tools, frameworks, IP cores, libraries, and more! + +If you miss any project, check the [issues and pull requests](https://github.com/HDL/awesome/issues?utf8=%E2%9C%93&q=) of this repo. Some proposals might be kept on hold until they get enough reaction from the community. Should it still be missing, open a [Pull Request](https://github.com/HDL/awesome/compare)! See [CONTRIBUTING](./github/CONTRIBUTING.md) for guidelines about how to clasify new projects. + +## References + +This repository was created on 2020/02/02 to merge the content of the following existing lists: + +- [vhdl/awesome-vhdl](https://github.com/vhdl/awesome-vhdl) +- [drom/awesome-hdl](https://github.com/drom/awesome-hdl) +- [fukatani/awesome-hdl](https://github.com/fukatani/awesome-hdl) +- [ben-marshall/awesome-open-hardware-verification](https://github.com/ben-marshall/awesome-open-hardware-verification) + +Find other awesome lists: [github.com/topics/awesome-list](https://github.com/topics/awesome-list) diff --git a/config.yml b/config.yml new file mode 100644 index 00000000..22b8bdf6 --- /dev/null +++ b/config.yml @@ -0,0 +1,48 @@ +baseURL: "https://hdl.github.io/awesome" +title: "Awesome resources for Hardware Description" +theme: "bare-hugo-theme" +enableGitInfo: true + +params: + shorttitle: "Awesome HDL" + description: 'Tools, frameworks, IP cores, libraries and more!' + # PostCSS is harder than it should be to get working on a theme + # example site. It's easy on _your_ site. + postcss: false + social: + - icon: "github-circle" + url: "https://github.com/hdl/awesome" + categories: + "Libraries": "" + "Libraries:IP Core Libraries": "libraries containing multiple IP cores" + "Libraries:IP Core Collections": "collections containing multiple IP cores" + "IP Cores": "single IP cores" + "Frameworks": "" + "Frameworks:Verification": "frameworks for verification" + "Verification Models": "single verification models" + "Verification Models:Memory": "verification model for Memories" + "Verification Models:Interface": "verification model for Interfaces" + "Tools": "" + "Tools:Grammars": "" + "Tools:Parsers": "" + "Tools:Simulators": "" + "Tools:Package Managers": "" + "Tools:Waveform Viewer": "" + "Services": "" + "Services:Code Quality": "" + "Services:Continuous Integration": "" + "Services:Continuous Documentation": "" + "Resources": "" + "Resources:Books": "" + "Resources:Twitter": "" + "Resources:Websites": "" + "Resources:Weekly": "" + +menu: + main: + - identifier: "categories" + name: "Categories" + url: "/categories/" + - identifier: "tags" + name: "Tags" + url: "/tags/" diff --git a/content/items/_index.md b/content/items/_index.md new file mode 100644 index 00000000..6e796cbb --- /dev/null +++ b/content/items/_index.md @@ -0,0 +1,5 @@ ++++ +aliases = ["all", "projects", "tools"] +title = "All awesome resources" +tags = ["index"] ++++ diff --git a/content/items/cocotb.md b/content/items/cocotb.md new file mode 100644 index 00000000..9c3249ba --- /dev/null +++ b/content/items/cocotb.md @@ -0,0 +1,21 @@ +--- +title: "Coroutine Co-simulation Test Bench (cocotb)" +description: "A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python" +author: ["author"] +links: + gh: "https://github.com/cocotb/cocotb" + docs: "https://cocotb.rtfd.io" +tags: [ + "verification", + "vhdl", + "verilog", + "systemverilog", +] +categories: [ + "Frameworks" +] +--- + +This is a long description... + +... about cocotb. diff --git a/content/items/eda-twiki.md b/content/items/eda-twiki.md new file mode 100644 index 00000000..e1a2c2a3 --- /dev/null +++ b/content/items/eda-twiki.md @@ -0,0 +1,17 @@ +--- +title: "eda-twiki" +description: "Wiki of the VHDL Analysis and Standardization Group (VASG)" +author: ["author"] +links: + web: "http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome" +tags: [ + "vhdl" +] +categories: [ + "Resources:Websites" +] +--- + +This is a long description... + +... about eda-twiki. diff --git a/content/items/fphdl.md b/content/items/fphdl.md new file mode 100644 index 00000000..6ea4e3f8 --- /dev/null +++ b/content/items/fphdl.md @@ -0,0 +1,15 @@ +--- +title: "fphdl" +description: "VHDL-2008 Support Library" +author: ["author"] +links: + gh: "https://github.com/FPHDL/fphdl/" +tags: [ + "libraries", + "vhdl", +] +--- + +This is a long description... + +... about fphdl. diff --git a/content/items/ghdl.md b/content/items/ghdl.md new file mode 100644 index 00000000..d4fa2260 --- /dev/null +++ b/content/items/ghdl.md @@ -0,0 +1,20 @@ +--- +title: "GHDL" +description: "Open-source analyzer, compiler, simulator and synthesiser for VHDL" +author: ["Tristan Gingold"] +links: + gh: "https://github.com/ghdl/ghdl" + docs: "https://ghdl.rtfd.io" +tags: [ + "analiser", + "compiler", + "simulator", + "synthesis", + "parser", + "vhdl", +] +--- + +This is a long description... + +... about GHDL. diff --git a/content/items/hdlConvertor.md b/content/items/hdlConvertor.md new file mode 100644 index 00000000..cdb06bc4 --- /dev/null +++ b/content/items/hdlConvertor.md @@ -0,0 +1,17 @@ +--- +title: "hdlConvertor" +description: "System Verilog and VHDL parser, preprocessor and code generator for Python/C++ written" +author: ["author"] +links: + gh: "https://github.com/Nic30/hdlConvertor" +tags: [ + "parser", + "preprocessor", + "vhdl", + "systemverilog", +] +--- + +This is a long description... + +... about hdlConvertor. diff --git a/content/items/iverilog.md b/content/items/iverilog.md new file mode 100644 index 00000000..1ae26cc1 --- /dev/null +++ b/content/items/iverilog.md @@ -0,0 +1,15 @@ +--- +title: "Icarus Verilog (iverilog)" +description: "Verilog simulation and synthesis tool" +author: ["author"] +links: + web: "http://iverilog.icarus.com/" +tags: [ + "simulator", + "verilog", +] +--- + +This is a long description... + +... about iverilog. diff --git a/content/items/netlistsvg.md b/content/items/netlistsvg.md new file mode 100644 index 00000000..7dbb5d9c --- /dev/null +++ b/content/items/netlistsvg.md @@ -0,0 +1,16 @@ +--- +title: "netlistsvg" +description: "Draw SVG schematics from a Yosys JSON netlists" +author: ["author"] +links: + gh: "https://github.com/nturley/netlistsvg" +tags: [ + "netlist", + "schematics", + "documentation", +] +--- + +This is a long description... + +... about netlistsvg. diff --git a/content/items/nvc.md b/content/items/nvc.md new file mode 100644 index 00000000..931d117c --- /dev/null +++ b/content/items/nvc.md @@ -0,0 +1,15 @@ +--- +title: "NVC" +description: "A GPLv3 VHDL compiler and simulator aiming for IEEE 1076-2002 compliance" +author: ["author"] +links: + gh: "https://github.com/nickg/nvc" +tags: [ + "synthesis", + "vhdl", +] +--- + +This is a long description... + +... about nvc. diff --git a/content/items/osvvm.md b/content/items/osvvm.md new file mode 100644 index 00000000..c9537ab3 --- /dev/null +++ b/content/items/osvvm.md @@ -0,0 +1,20 @@ +--- +title: "Open Source VHDL Verification Methodology (OSVVM)" +description: "description" +author: ["Jim Lewis"] +links: + gh: "https://github.com/OSVVM/OSVVM" +tags: [ + "verification", + "framework", + "vhdl", +] +categories: [ + "Frameworks", + "Frameworks:Verification" +] +--- + +This is a long description... + +... about OSVVM. diff --git a/content/items/poc.md b/content/items/poc.md new file mode 100644 index 00000000..1f17f09e --- /dev/null +++ b/content/items/poc.md @@ -0,0 +1,19 @@ +--- +title: "Pile of Cores libray (PoC)" +description: "A library of free, open-source and platform independent IP cores" +author: ["author"] +links: + gh: "https://github.com/VLSI-EDA/PoC" +tags: [ + "libraries", + "ip-core", + "vhdl", +] +categories: [ + "Libraries:IP Core Libraries" +] +--- + +This is a long description... + +... about PoC. diff --git a/content/items/pyvhdlparser.md b/content/items/pyvhdlparser.md new file mode 100644 index 00000000..617babf9 --- /dev/null +++ b/content/items/pyvhdlparser.md @@ -0,0 +1,16 @@ +--- +title: "pyVHDLParser" +description: "A token-stream based parser for VHDL-2008" +author: ["Patrick Lehmann"] +links: + gh: "https://github.com/Paebbels/pyVHDLParser" +date: "2019-12-28" +tags: [ + "parser", + "vhdl", +] +--- + +This is a long description... + +... about pyVHDLParser. diff --git a/content/items/rust_hdl.md b/content/items/rust_hdl.md new file mode 100644 index 00000000..7d2e59cf --- /dev/null +++ b/content/items/rust_hdl.md @@ -0,0 +1,16 @@ +--- +title: "rust_hdl" +description: "Collection of HDL related tools" +author: ["Olof Kraigher"] +links: + gh: "https://github.com/kraigher/rust_hdl" +tags: [ + "parser", + "language-server", + "vhdl", +] +--- + +This is a long description... + +... about rust_hdl. diff --git a/content/items/tsfpga.md b/content/items/tsfpga.md new file mode 100644 index 00000000..97981fc4 --- /dev/null +++ b/content/items/tsfpga.md @@ -0,0 +1,17 @@ +--- +title: "tsfpga" +description: "Tools for managing modern FPGA project" +author: ["Lukas Vik"] +links: + gl: "https://gitlab.com/truestream/tsfpga" +tags: [ + "libraries", + "ip-core", + "vhdl", + "vivado", +] +--- + +This is a long description... + +... about tsfpga. diff --git a/content/items/uvvm.md b/content/items/uvvm.md new file mode 100644 index 00000000..ddc3631e --- /dev/null +++ b/content/items/uvvm.md @@ -0,0 +1,19 @@ +--- +title: "Universal VHDL Verification Methodology (UVVM)" +description: "description" +author: ["author"] +links: + gh: "https://github.com/UVVM/UVVM" +tags: [ + "verification", + "framework", + "vhdl", +] +categories: [ + "Frameworks" +] +--- + +This is a long description... + +... about UVVM. diff --git a/content/items/vasg_packages.md b/content/items/vasg_packages.md new file mode 100644 index 00000000..feacfe98 --- /dev/null +++ b/content/items/vasg_packages.md @@ -0,0 +1,14 @@ +--- +title: "VASG Packages" +description: "Open source materials referenced by the IEEE 1076 standard" +author: ["author"] +links: + gl: "https://opensource.ieee.org/vasg/Packages" +tags: [ + "vhdl", +] +--- + +This is a long description... + +... about VASG Packages. diff --git a/content/items/verilator.md b/content/items/verilator.md new file mode 100644 index 00000000..a60bb4ef --- /dev/null +++ b/content/items/verilator.md @@ -0,0 +1,18 @@ +--- +title: "verilator" +description: "Open-source compiler/simulator for syntehsizable Verilog or SystemVerilog" +author: ["author"] +links: + web: "https://www.veripool.org/wiki/verilator" +tags: [ + "analiser", + "compiler", + "simulator", + "verilog", + "systemverilog", +] +--- + +This is a long description... + +... about verilator. diff --git a/content/items/vhdl-extras.md b/content/items/vhdl-extras.md new file mode 100644 index 00000000..c99a1d57 --- /dev/null +++ b/content/items/vhdl-extras.md @@ -0,0 +1,15 @@ +--- +title: "VHDL-extras" +description: "Bits of code that are not found in the standard VHDL libraries" +author: ["Kevin Thibedeau"] +links: + gh: "https://github.com/kevinpt/vhdl-extras" +tags: [ + "libraries", + "vhdl", +] +--- + +This is a long description... + +... about VHDL-extras. diff --git a/content/items/vtr.md b/content/items/vtr.md new file mode 100644 index 00000000..54d668fa --- /dev/null +++ b/content/items/vtr.md @@ -0,0 +1,16 @@ +--- +title: "Verilog to Routing (VTR)" +description: "Open source CAD flow for FPGA research" +author: ["author"] +links: + web: "https://verilogtorouting.org/" + gh: "https://github.com/verilog-to-routing/vtr-verilog-to-routing" +tags: [ + "synthesis", + "verilog", +] +--- + +This is a long description... + +... about VTR. diff --git a/content/items/vunit.md b/content/items/vunit.md new file mode 100644 index 00000000..c8de5adf --- /dev/null +++ b/content/items/vunit.md @@ -0,0 +1,23 @@ +--- +title: "VUnit" +description: "Open source unit testing framework for VHDL/SystemVerilog" +author: ["Lars Asplund", "Olof Kraigher"] +links: + gh: "https://github.com/VUnit/vunit" + web: "http://vunit.github.io/" +date: "2014-11-25" +tags: [ + "framework", + "testing", + "verification", + "vhdl", + "systemverilog", +] +categories: [ + "Frameworks" +] +--- + +This is a long description... + +... about VUnit. diff --git a/content/items/wavedrom.md b/content/items/wavedrom.md new file mode 100644 index 00000000..2d018ae0 --- /dev/null +++ b/content/items/wavedrom.md @@ -0,0 +1,18 @@ +--- +title: "wavedrom" +description: "Javascript wave graph visualizer for documentations and sim" +author: ["author"] +links: + gh: "https://github.com/drom/wavedrom" +tags: [ + "vcd", + "documentation", +] +categories: [ + "Tools:Waveform Viewer" +] +--- + +This is a long description... + +... about wavedrom. diff --git a/content/items/yosys.md b/content/items/yosys.md new file mode 100644 index 00000000..31ca8e33 --- /dev/null +++ b/content/items/yosys.md @@ -0,0 +1,16 @@ +--- +title: "Yosys Open SYnthesis Suite (Yosys)" +description: "A framework for RTL synthesis" +author: ["author"] +links: + web: "http://www.clifford.at/yosys/" + gh: "https://github.com/YosysHQ/yosys" +tags: [ + "synthesis", + "verilog", +] +--- + +This is a long description... + +... about Yosys. diff --git a/static/img/favicon/android-chrome-192x192.png b/static/img/favicon/android-chrome-192x192.png new file mode 100644 index 00000000..a5083e9a Binary files /dev/null and b/static/img/favicon/android-chrome-192x192.png differ diff --git a/static/img/favicon/android-chrome-512x512.png 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"/img/favicon/android-chrome-512x512.png", + "sizes": "512x512", + "type": "image/png" + } + ], + "theme_color": "#ffffff", + "background_color": "#ffffff", + "display": "standalone" +} diff --git a/static/img/logo.png b/static/img/logo.png new file mode 100644 index 00000000..c4ebf3cf Binary files /dev/null and b/static/img/logo.png differ diff --git a/static/img/logo.svg b/static/img/logo.svg new file mode 100644 index 00000000..68e3a2bb --- /dev/null +++ b/static/img/logo.svg @@ -0,0 +1,156 @@ + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/themes/bare-hugo-theme b/themes/bare-hugo-theme new file mode 160000 index 00000000..2d9ac8cf --- /dev/null +++ b/themes/bare-hugo-theme @@ -0,0 +1 @@ +Subproject commit 2d9ac8cf49efbbabd1bc0bde1f6ca728263eb65a diff --git a/todo/ben.md b/todo/ben.md new file mode 100644 index 00000000..d2bfbca3 --- /dev/null +++ b/todo/ben.md @@ -0,0 +1,378 @@ +# Open Hardware Verification + +*A curated List of Free and Open Source hardware verification tools and frameworks.* + +The aim here is to curate a (mostly) comprehensive list of available tools for verifying +the functional correctness of Free and Open Source Hardware designs. The list can +include: +- [Tools](#Tools) which contain or implement verification related functionality +- [Testbench Frameworks](#Frameworks) which make writing testbenches easier +- [Verification Guides](#Guides) and blog posts on how to actually go about verifying a hardware design +- [Conferences](#Conferences) where new work on open source hardware verification is talked about + +Pull requests and submissions are encouraged! + +**Some Rules:** + +This list focuses on *Verification* and not *design*. While there are lots of cool new +languages and frameworks aimed at making hardware design easier (or at least, *not Verilog/VHDL*), +verification can sometimes get left out in the cold. + +While some new design tools/languages claim that "our new design tool `X` makes verification +easier because it is written in high level language `Y`", it can often be much harder to find +evidence of this in terms of re-usable verification IP/frameworks/methods which are written +in "new language/tool `Y`". It might seem mean, but being a new design language which +*theoretically* makes verification easier is not enough to merit inclusion on this list. What's +needed is *practical* demonstration of making verification easier. This can be through libraries or +IP which use "new language/tool `Y`", or in depth tutorials which explain how to use it for proper +design verification. + +If you're after hardware *design* tools, these awesome lists are a good place to start: +- [awesome-hdl](https://github.com/drom/awesome-hdl) + +Further, entries in this list should not only be open source themselves, but *be usable* by +people developing open source hardware using open source tools. For example, if company `X` +releases a set of re-usable verification components written using +[UVM](https://www.accellera.org/downloads/standards/uvm) +and SystemVerilog, is there an Free and Open Source SystemVerilog implementation which can make +use of them? + +## Contents + +**Tools:** + +- [Symbiyosys](#Symbiyosys) +- [Verilator](#Verilator) +- [LibreCores CI](#LibreCores-CI) +- [AAPG (Automated Assembly Program Generator)](#AAPG) +- [riscv-dv](#riscv-dv) +- [covered](#covered) +- [svlint](#svlint) +- [sv-parser](#sv-parser) +- [rggen](#rggen) (Code generation tool for configuration and status registers) +- [EBMC / CBMC](#ebmc--cbmc) (Model checker for C/C++ and hardware designs) + +**Frameworks:** + +- [cocotb](#cocotb) +- [riscv-formal](#riscv-formal) +- [UVVM](#UVVM) +- [OSVVM](#OSVVM) +- [VUnit](#VUnit) +- [V3](#V3) + +**Components / VIPs** + +- [uvm_axi](#uvm_axi) +- [AXI Bus Formal VIP](#axi-bus-formal-vip) +- [AXI Bus Functional Model tvip-axi](#AXI-Bus-Functional-Model---tvip-axi) +- [APB Bus Functional Model tvip-apb](#APB-Bus-Functional-Model---tvip-apb) + +**Guides:** + +- [Dan Gisselquist Formal Verification Blogs](#Dan-Gisselquist-Formal-Verification-Blogs) + +**Conferences:** + +- [ORCONF](#ORCONF) +- [OSDA](#OSDA) +- [CHIPS Alliance Workshop on Open Source Design Verification](#CHIPS-Alliance-Workshop-on-Open-Source-Design-Verification) + +--- + +## Tools: + +### SymbiYosys + +*"SymbiYosis a front-end driver program for Yosys-based formal hardware +verification flows. SymbiYosys provides flows for the following formal tasks: +Bounded verification of safety properties (assertions), +Unbounded verification of safety properties, +Generation of test benches from cover statements, +Verification of liveness properties"* + +SymbiYosys requires [Yosys](https://github.com/YosysHQ/yosys) (an open +source synthesis tool) and one or more formal reasoning engines (listed +[here](https://symbiyosys.readthedocs.io/en/latest/quickstart.html#prerequisites)to work. + +- Written In: Python +- Write Assertions In: Verilog/SystemVerilog Assertions (SVA) +- Supports: Formal verification of correctness properties. +- Link: https://symbiyosys.readthedocs.io/en/latest/ + +### Verilator + +Verilator is "the fastest free Verilog HDL simulator". From a verification +perspective it supports *line coverage*, *signal toggle coverage* and limited +specification of *functional coverage* using SystemVerilog Assertions. +It also allows one to write testbenches in C++ or SystemC. + +- Written In: C++ +- Write testbenches in: C++/SystemC +- Supports: Design simuation, *Coverage collection from simulations*. +- Link: https://www.veripool.org/projects/verilator/wiki/Intro + +### LibreCores CI + +*"LibreCores CI is a service, which provides Continuous Integration of projects being hosted on LibreCores. The objective of the service is to improve the contributor experience and to increase trust to projects by providing automated testing and health metrics of the projects."* + +- Currently under development at the time of writing (Dec 2018) +- Aims to allow automation of testing for hardware designs. Think "Travis for hardware". +- Link: https://www.librecores.org/static/librecores-ci + +## AAPG + +*"Automated Assembly Program Generator (aapg) is a tool that is intended to generate random RISC-V programs to test RISC-V cores."* + +From the [Shakti](https://gitlab.com/shaktiproject) RISC-V core project. +Acts as a way to generate random stimulus for a RISC-V core. +Output of the programs can then be checked between DUT and a GRM. + +- Link: https://gitlab.com/shaktiproject/tools/aapg +- License: BSD 3-clause +- Written In: Python + +## riscv-dv + +Similar to [AAPG](#AAPG), but this time from Google. +Generates randomised RISC-V programs which can +then be run by the DUT and A GRM and checked for equivilence. +It has knowledge of interesting features like page tables, CSR access and +trap/interrupt handling. +Can generate randomised instruction streams with features like loops +and function calls etc. + +This project cannot be used with current free open source HDL simulators +since it relies on the object orientated parts of UVM. It is still a +useful piece of Verification IP though, and serves as a guide for other +similar projects. + +- Link: https://github.com/google/riscv-dv +- License: Apache-2.0 +- Written In: SystemVerilog + UVM + +### covered + +*"Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test."* ... *"Covered reads in the Verilog design files and a VCD, LXT or FST formatted dumpfile from a diagnostic run and generates a database file called a Coverage Description Database (CDD) file"* ... "*Once a CDD file is created, the user can use Covered to generate various human-readable coverage reports in an ASCII format or use Covered's GUI to interactively look at coverage results*". + +- Link: https://github.com/anders-code/verilog-covered +- License: GPL-2.0 +- Written In: C + +### svlint + +An open source, MIT licensed SystemVerilog linting tool. Built on top of an open source [SystemVerilog parser](#sv-parser). + +- Link: https://github.com/dalance/svlint +- License: MIT +- Written In: Rust + +### sv-parser + +An open source, MIT/Apache licensed SystemVerilog parser/ Useful for quickly building custom tools / checkers. + +- Link: https://github.com/dalance/sv-parser +- License: MIT / Apache +- Written In: Rust + +### RgGen + +"*RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will +automatically generate soruce code related to configuration and status +registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from +human readable register map specifications.*" + +- Link: https://github.com/rggen/rggen +- License: MIT +- Written in: Ruby + + +### EBMC / CBMC + +**EBMC:** + +"*EBMC is a Model Checker for hardware designs. It includes both bounded and +unbounded analysis, i.e., it can both discover bugs and is also able to prove +the absence of bugs. It can read Netlists (ISCAS89 format), Verilog, System +Verilog and SMV files. Properties can be given in LTL or a fragment of System +Verilog Assertions.*" + +- Link: http://www.cprover.org/ebmc/ +- Licence: http://www.cprover.org/ebmc/download/license.txt +- Written in: _Unknown_. + +Note: Only the binaries for EBMC can be downloaded, no source-code is +available. It's included on this list because it is a powerful tool which +would otherwise not be available to the open hardware community. +For a completely free and open tool with similar capabilities, +look at [SymbiYosys](#Symbiyosys). + +**CBMC:** + +"*CBMC is a Bounded Model Checker for C and C++ programs.*" + +"*Furthermore, it can check C and C++ for consistency with other languages, +such as Verilog. The verification is performed by unwinding the loops in the +program and passing the resulting equation to a decision procedure.*" + +- Link: http://www.cprover.org/cbmc/ + - Source: https://github.com/diffblue/cbmc +- Licence: https://github.com/diffblue/cbmc/blob/develop/LICENSE +- Written in: C++. + + +## Frameworks: + +### Cocotb +*"cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python."* + +- Licence: [Revised BSD License](https://github.com/potentialventures/cocotb/blob/master/LICENSE) +- Implemented in: Python +- Write Testbeches In: Python +- Link: https://github.com/potentialventures/cocotb + +### riscv-formal + +A re-usable formal verification framework for RISC-V CPU designs. +Uses the [Yosys/SymbiYosys](#SymbiYosys) tools. + +- License: [ISC](https://github.com/SymbioticEDA/riscv-formal/blob/master/COPYING) +- Written In: Verilog +- Link: https://github.com/SymbioticEDA/riscv-formal + +### UVVM + +*"Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement"* + +There is also an accompanying library of user contributed VIPs: [UVVM_Community_VIPs](https://github.com/UVVM/UVVM_Community_VIPs). + +- License: [MIT](https://github.com/UVVM/UVVM/blob/master/LICENSE) +- Written In: VHDL +- Write Testbenches In: VHDL +- Supports: [a bunch of stuff](https://github.com/UVVM/UVVM#main-features) +- Link: https://github.com/UVVM/UVVM + +### OSVVM + +*"Open Source VHDL Verification Methodology (OSVVM) provides an ASIC level VHDL verification methodology that is simple enough to use even on small FPGA projects. OSVVM offers the same capabilities as those based on other verification languages:"* + +The GitHub organisation includes some AXI4 [Verification IP](https://github.com/OSVVM/VerificationIP) + +- License: ? +- Written In: VHDL +- Supports: Constrained Random Test Generation, Functional Coverage Collection, [and more](https://osvvm.org/about-os-vvm) +- Link: https://osvvm.org/ +- GitHub: https://github.com/OSVVM/OSVVM + +### VUnit + +*"VUnit is an open source unit testing framework for VHDL/SystemVerilog \[...\] It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn’t replace but rather complements traditional testing methodologies by supporting a “test early and often” approach through automation."* + +Based partially on [OSVVM](#OSVVM) + +- Written In: VHDL/Python +- Write Testbenches In: VHDL/System Verilog +- License: [Mozilla Public License, v. 2.0.](https://github.com/VUnit/vunit/blob/master/LICENSE.txt) baring OSVVM components. +- Link: https://vunit.github.io/index.html + +### V3 + +*"V3 is a new and extensible framework for hardware verification and debugging researches on both Boolean-level and word-level designs. It is a powerful tool for users and an elaborate framework for developers as well."* + +Academic project, looks unmaintained since 2014. + +- Written In: C++ +- Write Testbenches In: Unclear? +- License: [Non-commercial](https://github.com/chengyinwu/V3/blob/master/COPYING) +- Supports: formal methods based approaches using AGIER / SAT Solving over verilog input files. Not entirely clear how one specifies correctness properties. +- Link: https://github.com/chengyinwu/V3 + +## Components / VIPs + +### uvm_axi + +A bus functional model for ARM's AXI bus protocol. Looks like it has been written as a standard UVM Verification Package. +Being written in SystemVerilog (using all of its object orientated, behavioural modelling features) makes it hard +to re-use with the current set of FOSS simulators. It is still a good example of re-usable verification IP. + +Last commit in 2013, so likely un-maintained. + +- Link: https://github.com/funningboy/uvm_axi +- Written in: System Verilog +- Write Testbenches In: System Verilog +- License: GNU Lesser General Public License + +### AXI Bus Formal VIP + +A set of formal properties for checking for correct protocol behaviour in an AXI bus. +Used as part of a Wishbone-AXI bus bridge, but usable with any AXI bus. +There is a great blog post on it's use [here](https://zipcpu.com/formal/2018/12/28/axilite.html) from ZipCPU. +It works with SymbiYosys. + +- Link: https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v +- Written in: Verilog +- Write Testbenches In: Verilog +- License: None specified + +### AXI Bus Functional Model - tvip-axi + +Bus function model for AMBA AXI protocol. +Supports master and slave agents, AXI4 and AXI4-Lite protocols. +Configurable address/data/id widths. +Supports in/out-of-order responses, delayed responses and read interleaving. + +- Link: https://github.com/taichi-ishitani/tvip-axi +- Written in: SystemVerilog and UVM +- License: Apache-2.0 + +### APB Bus Functional Model - tvip-apb + +Bus function model for AMBA APB protocol + +- Link: https://github.com/taichi-ishitani/tvip-apb +- Written in: SystemVerilog and UVM +- License: Apache-2.0 + + +## Guides: + +### Dan Gisselquist Formal Verification Blogs + +A set of posts on experiences using [Symbiyosys/Yosys](#Symbiyosys) for formally verifying a CPU design. +Includes lots of useful insights and guides for specific and general use cases. + +- Link: https://zipcpu.com/formal/formal.html + +## Conferences: + +### ORCONF + +*"ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space."* + +- Link: https://orconf.org/ + +### OSDA + +*"Workshop on Open Source Design Automation (OSDA)"* + +*"This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry. These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate 'open access' for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions."* + +- Longer Description: https://osda.gitlab.io/motivation.html +- Link: https://osda.gitlab.io/ + +### CHIPS Alliance Workshop on Open Source Design Verification + +*"The workshop invites contributions from industry, academia and hobbyists, either as talk or tutorial. Proposals should cover open source design simulation and verification, for example in the following categories (but not limited to): + + Open source simulation tools + Open source design verification tools + Open source rapid prototyping tools and methodologies + Open source libraries for design verification + Open source standards and methodologies for design verification + Industry case studies of usage and integration of the aforementioned + +Most importantly, your submitted proposal should cover the open source aspect."* + +- Link: https://chipsalliance.org/workshops-meetings/ +- Date: November 14-15, 2019 +- Location: Munich, Germany diff --git a/todo/drom.md b/todo/drom.md new file mode 100644 index 00000000..254cf33a --- /dev/null +++ b/todo/drom.md @@ -0,0 +1,130 @@ +# Hardware development + +## HDL doc + +* Verilog [IEEE Std 1364-2001](https://inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf), [Quick Ref Guide](http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf), [SystemVerilog 3.1a](http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf), [Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification](http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf) +* VHDL standards [IEEE Std 1076-2000](http://edg.uchicago.edu/~tang/VHDLref.pdf) +* SystemC standards [IEEE Std 1666-2011](http://paginas.fe.up.pt/~ee07166/lib/exe/fetch.php?media=1666-2011.pdf) + +## HDL simulators and compilers + +* [Lola-2](https://inf.ethz.ch/personal/wirth/Lola/Lola2.pdf) + - [Oberon-2013](https://inf.ethz.ch/personal/wirth/Lola/) - Project Oberon, 2013 Edition, written in [Oberon-07](http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/) [License](https://inf.ethz.ch/personal/wirth/ProjectOberon/license.txt) + +## Meta HDL and Transpilers + +* C++ + - [SystemC](https://www.doulos.com/knowhow/systemc/) - an IEEE standard meta-HDL + - [VisualHDL](http://sysprogs.com/legacy/visualhdl/) - an integrated development environment (IDE) rapid design for FPGAs + +* Haskell + - [concat](https://github.com/conal/concat) Haskell to hardware, 2016+ + - https://github.com/conal/talk-2015-haskell-to-hardware + - [CλaSH](https://github.com/clash-lang/clash-compiler) - A functional hardware description language + - [pipelineDSL](https://github.com/p12nGH/pipelineDSL) - A Haskell DSL for describing hardware pipelines + +* Java + - [jhdl](http://www.jhdl.org/) ..2006 + - [PSHDL](http://pshdl.org/) + +* JavaScript + - [reqack](https://github.com/drom/reqack) - elastic circuit toolchain + - [hdl-js](https://github.com/DmitrySoshnikov/hdl-js) - Hardware description language (HDL) parser, and Hardware simulator. + - [shdl](https://github.com/jcbuisson/shdl) - Simple Hardware Description Language + +* Julia + - [Julia-Verilog](https://github.com/interplanetary-robot/Verilog.jl) - a Verilog-generation DSL for Julia., 2017 + +* Python + - [HWT](https://github.com/Nic30/hwt) Meta HDL, verification env. IP-core generator, analysis tools, HDL glue + - [garnet](https://github.com/StanfordAHA/garnet) Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+ + - [magma](https://github.com/phanrahan/magma/) - Meta HDL, 2017+ + - [migen](https://github.com/m-labs/migen) - Meta HDL, 2011+ + - [MyHDL](https://github.com/myhdl/myhdl) - Process based HDL, verification framework included, 2004+ + - [Pyrope](https://masc.soe.ucsc.edu/pyrope.html) - Python-like language supporting "fluid pipelines" and "live flow", 2017+ + - [PyRTL](https://github.com/UCSBarchlab/PyRTL) - Meta HDL, simulator suitable for research. + - [PyMTL](https://github.com/cornell-brg/pymtl) - Process based HDL, verification framework included, 2014+ + - [veriloggen](https://github.com/PyHDI/veriloggen) - Python, Verilog centric meta HDL with HLS like features, 2015-? + +* Ruby + - [RHDL](https://github.com/philtomson/RHDL) + +* Rust + - [hoodlum](https://github.com/tcr/hoodlum) - Meta HDL, 2016+ + - [kaze](https://github.com/yupferris/kaze) - Meta HDL, 2019+ + +* Scala + - [chisel](https://github.com/freechipsproject/chisel3) - Meta HDL, 2012+ + - [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) - Meta HDL 2012+ + +## HLS + +* [hlslibs](https://github.com/hlslibs) - ac_math, ac_dsp, ac_types +* [legup](http://legup.eecg.utoronto.ca/) - 2011-2015, LLVM based c->verilog +* [bambu](http://panda.dei.polimi.it/?page_id=31) - 2003-?, GCC based c->verilog +* [augh](http://tima.imag.fr/sls/research-projects/augh/) - c->verilog, DSP support +* https://github.com/utwente-fmt - abstract hls, verification libraries +* [Shang](https://github.com/etherzhhb/Shang) - 2012-2014, LLVM based, c->verilog +* [xronos](https://github.com/endrix/xronos) - 2012, java, simple HLS +* [Potholes](https://github.com/SamuelBayliss/Potholes) - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET +* [hls_recurse](https://github.com/m8pple/hls_recurse) - 2015-2016 - conversion of recursive fn. for stackless architectures +* [hg_lvl_syn](https://github.com/funningboy/hg_lvl_syn) - 2010, ILP, Force Directed scheduler +* [abc](https://people.eecs.berkeley.edu/~alanmi/abc/) <2008-?, A System for Sequential Synthesis and Verification +* [polyphony](https://github.com/ktok07b6/polyphony) - 2015-2017, simple python to hdl +* [DelayGraph](https://github.com/ni/DelayGraph) - 2016, C#, register assignment algorithms +* [ahaHLS](https://github.com/dillonhuff/ahaHLS) - 2019, An open source high level synthesis (HLS) tool using LLVM +* [combinatorylogic/soc](https://github.com/combinatorylogic/soc) - 2019, An experimental System-on-Chip with a custom compiler toolchain. + +## Other HDL languages + +* [act](https://github.com/asyncvlsi/act) - asynchronous circuit/compiler tools +* [autopiper](https://github.com/google/autopiper) +* [TL-Verilog](https://makerchip.com) - 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools + +## Hardware Intermediate Representations + +* [coreir](https://github.com/rdaly525/coreir) - 2016-?, LLVM HW compiler## License +* [lgraph](https://github.com/masc-ucsc/lgraph) - 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design +* [firrtl](https://github.com/freechipsproject/firrtl) - 2016-?, Flexible Intermediate Representation for RTL + +## Libraries with information about boards/chips + +* [loam](https://github.com/phanrahan/loam) - Buildsystem for magma +* [litex](https://github.com/enjoy-digital/litex) - Buildsystem for migen + +## Visualization and Documentation generators + +* [bitfield](https://github.com/drom/bitfield) - Javascript bit field diagram renderer +* [d3-wave](https://github.com/Nic30/d3-wave) - Javascript wave graph visualizer for RTL simulations +* [d3-hwschematic](https://github.com/Nic30/d3-hwschematic) - Javascript hierarchycal schematic visualizer for HDLs +* [sphinx-hwt](https://github.com/Nic30/sphinx-hwt) - Plugin for sphinx documentation generator which adds shematic into html documentaion. + +## HDL parsers + +* [sv-parser](https://github.com/dalance/sv-parser) - IEEE 1800-2017 System Verilog Parser written in Rust + +## Other Simulation tools + +* [midas](https://github.com/ucb-bar/midas) - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL + +# Open Hardware + +* [opencores.org](https://opencores.org/) - webpage which hosts many openhardware projects +* [ohwr](https://ohwr.org/welcome) - Open Hardware Repository, Cern open hardware community. +* [enjoy-digital repositories](https://github.com/enjoy-digital?tab=repositories) - Migen, SoC level modules +* [ZipCPU repositories](https://github.com/ZipCPU?tab=repositories) - Verilog, mostly peripherals, DSP +* [rhea](https://github.com/cfelton/rhea) - MyHDL, SoC level modules +* [FPGAwars FPGA-peripherals](https://github.com/FPGAwars/FPGA-peripherals) - Verilog, simple peripherals +* [PoC](https://github.com/VLSI-EDA/PoC) - VHDL, utils +* [picorv32](https://github.com/cliffordwolf/picorv32) - Verilog, A Size-Optimized RISC-V SoC +* [openrisc](https://github.com/openrisc) - OpenRISC, FuseSoC, peripherals and cpu parts +* [NyuziProcessor](https://github.com/jbush001/NyuziProcessor) - GPGPU +* [Miaow](http://miaowgpu.org/) - Miaow, Southern Island compatible ISA compute only GPGPU +* [VexRiscv](https://github.com/SpinalHDL/VexRiscv) - RISC-V written in SpinalHDL +* [Awesome Open Hardware Verification](https://github.com/ben-marshall/awesome-open-hardware-verification/) - A list of open source tools and frameworks for hardware verification. + +## License + +[![CC0](http://mirrors.creativecommons.org/presskit/buttons/88x31/svg/cc-zero.svg)](https://creativecommons.org/publicdomain/zero/1.0/) + +To the extent possible under law, [Aliaksei Chapyzhenka](http://drom.io) has waived all copyright and related or neighboring rights to this work. diff --git a/todo/fukatani.md b/todo/fukatani.md new file mode 100644 index 00000000..d3d8fccd --- /dev/null +++ b/todo/fukatani.md @@ -0,0 +1,75 @@ +# Awesome HDL [![Awesome](https://cdn.rawgit.com/sindresorhus/awesome/d7305f38d29fed78fa85652e3a63e154dd8e8829/media/badge.svg)](https://github.com/sindresorhus/awesome) + +A curated list of awesome HDL, libraries and implementation (by language). Inspired by awesome-machine-learning. + +If you want to contribute to this list (please do), please feel free to send me a pull request . + +## Table of Contents + + + +- [Verilog-Toolkit](#verilog-toolkit) +- [Verilog-Implementation](#verilog-implementation) +- [Verilog-Books](#verilog-books) +- [VHDL-Toolkit](#vhdl-toolkit) +- [VHDL-Implementation](#vhdl-implementation) +- [Tutorial](#tutorial) +- [Paper](#paper) + + + + +## Verilog-Toolkit +* [verilog-mode](https://github.com/veripool/verilog-mode) - Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. + +* [Pyverilog](https://github.com/PyHDI/Pyverilog) - Python-based Hardware Design Processing Toolkit for Verilog HDL. + +* [veriloggen](https://github.com/PyHDI/veriloggen) - A library for constructing a Verilog HDL source code by Python. + +* [PyCoRAM](https://github.com/PyHDI/PyCoRAM) - Python-based Portable IP-core Synthesis Framework for FPGA-based Computing. + +* [Pyverilog-toolbox](https://github.com/fukatani/Pyverilog_toolbox) - Pyverilog-based verification/design tool including code clone finder, metrics calculator and so on. + + +## Hardware-Implementation-by-Verilog +* [miaow](https://github.com/VerticalResearchGroup/miaow) - An open source GPU based off of the AMD Southern Islands ISA. + +* [amiga2000-gfxcard](https://github.com/mntmn/amiga2000-gfxcard) - MNT VA2000, an Amiga 2000 Graphics Card (Zorro II), written in Verilog. + +* [gplgpu](https://github.com/asicguy/gplgpu) - GPL v3 2D/3D graphics engine in verilog. + +* [oh](https://github.com/parallella/oh) - Silicon validated Open Verilog library for IC and FPGA designers. + +* [FPGA-Litecoin-Miner](https://github.com/kramble/FPGA-Litecoin-Miner) - Litecoin script miner implemented with FPGA on-chip memory. + +* [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) - Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). + + +## Verilog-Books +* [SystemVerilog Assertions Handbook](https://verificationacademy.com/forums/systemverilog/new-book-systemverilog-assertions-handbook-4th-edition) - Assertion Guide for static and dynamic verification. + +* [Writing Testbenches using SystemVerilog](http://www.springer.com/us/book/9780387292212) - Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source. + + +## VHDL-Toolkit +* [sublime-vhdl](https://github.com/yangsu/sublime-vhdl) - VHDL Package for Sublime Text 2/3. + + +## Hardware-Implementation-by-VHDL +* [Open-Source-FPGA-Bitcoin-Miner](https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner) - A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. + +* [space-invaders-vhdl](https://github.com/fabioperez/space-invaders-vhdl) - Space Invaders game implemented with VHDL. + + +## Tutorial + +* [IntroToSpartanFPGABook](https://github.com/hamsternz/IntroToSpartanFPGABook) - A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards. + +* [EDA playground](https://www.edaplayground.com/) - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. + + +## Paper + +* [Asynchronous & Synchronous Reset Design Techniques](http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf) + +* [Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog](http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf) \ No newline at end of file diff --git a/todo/todo.md b/todo/todo.md new file mode 100644 index 00000000..8b4a815e --- /dev/null +++ b/todo/todo.md @@ -0,0 +1 @@ +- Add JSON output(s) and provide a link to download. \ No newline at end of file