ram_pc.vhd.bak

-- 读写寄存器
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.constants.all;

entity ram_pc is
port(clk:in std_logic;
	  addr:in std_logic_vector(pcLength downto 0);
	  data:in std_logic_vector(instrucLength downto 0);
	  wr,rd:in std_logic; -- 0-read 1-write;
	  q:out std_logic_vector(instrucLength downto 0));
end ram_pc;

architecture exp of ram_pc is
type t_ram is array(pcLength downto 0) of std_logic_vector(instrucLength downto 0);
begin
process(clk,wr)
variable ramdata:t_ram;
variable temp_data:std_logic_vector(instrucLength downto 0);
begin
if rising_edge(clk) then
	if rd='1' then  --read
		temp_data:=ramdata(conv_integer(addr));
		q<=temp_data;
	elsif wr='1' then
		temp_data:=data;
		ramdata(conv_integer(addr)):=temp_data;
	else
		null;
	end if;
end if;
end process;
end architecture;