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Merge from 'master' to 'sycl-web' (#8)
 CONFLICT (content): Merge conflict in clang/include/clang/Basic/DiagnosticSemaKinds.td
2 parents 030a52d + 3aec298 commit a551db5

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17 files changed

+71
-169
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17 files changed

+71
-169
lines changed

‎clang/include/clang/Basic/DiagnosticSemaKinds.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10811,12 +10811,6 @@ def err_matrix_separate_incomplete_index: Error<
1081110811
def err_matrix_subscript_comma: Error<
1081210812
"comma expressions are not allowed as indices in matrix subscript expressions">;
1081310813

10814-
def warn_mismatched_import : Warning<
10815-
"import %select{module|name}0 (%1) does not match the import %select{module|name}0 (%2) of the "
10816-
"previous declaration">;
10817-
def warn_import_on_definition : Warning<
10818-
"import %select{module|name}0 cannot be applied to a function with a definition">;
10819-
1082010814
// SYCL-specific diagnostics
1082110815
def err_sycl_kernel_incorrectly_named : Error<
1082210816
"kernel %select{name is missing"

‎clang/include/clang/Sema/Sema.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3153,10 +3153,6 @@ class Sema final {
31533153
const InternalLinkageAttr &AL);
31543154
CommonAttr *mergeCommonAttr(Decl *D, const ParsedAttr &AL);
31553155
CommonAttr *mergeCommonAttr(Decl *D, const CommonAttr &AL);
3156-
WebAssemblyImportNameAttr *mergeImportNameAttr(
3157-
Decl *D, const WebAssemblyImportNameAttr &AL);
3158-
WebAssemblyImportModuleAttr *mergeImportModuleAttr(
3159-
Decl *D, const WebAssemblyImportModuleAttr &AL);
31603156

31613157
void mergeDeclAttributes(NamedDecl *New, Decl *Old,
31623158
AvailabilityMergeKind AMK = AMK_Redeclaration);

‎clang/lib/Sema/SemaDecl.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2598,10 +2598,6 @@ static bool mergeDeclAttribute(Sema &S, NamedDecl *D,
25982598
NewAttr = S.mergeSpeculativeLoadHardeningAttr(D, *SLHA);
25992599
else if (const auto *SLHA = dyn_cast<NoSpeculativeLoadHardeningAttr>(Attr))
26002600
NewAttr = S.mergeNoSpeculativeLoadHardeningAttr(D, *SLHA);
2601-
else if (const auto *IMA = dyn_cast<WebAssemblyImportModuleAttr>(Attr))
2602-
NewAttr = S.mergeImportModuleAttr(D, *IMA);
2603-
else if (const auto *INA = dyn_cast<WebAssemblyImportNameAttr>(Attr))
2604-
NewAttr = S.mergeImportNameAttr(D, *INA);
26052601
else if (Attr->shouldInheritEvenIfAlreadyPresent() || !DeclHasAttr(D, Attr))
26062602
NewAttr = cast<InheritableAttr>(Attr->clone(S.Context));
26072603

‎clang/lib/Sema/SemaDeclAttr.cpp

Lines changed: 19 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -6467,75 +6467,45 @@ static void handleWebAssemblyExportNameAttr(Sema &S, Decl *D, const ParsedAttr &
64676467
D->addAttr(UsedAttr::CreateImplicit(S.Context));
64686468
}
64696469

6470-
WebAssemblyImportModuleAttr *
6471-
Sema::mergeImportModuleAttr(Decl *D, const WebAssemblyImportModuleAttr &AL) {
6472-
auto *FD = cast<FunctionDecl>(D);
6473-
6474-
if (const auto *ExistingAttr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
6475-
if (ExistingAttr->getImportModule() == AL.getImportModule())
6476-
return nullptr;
6477-
Diag(ExistingAttr->getLocation(), diag::warn_mismatched_import) << 0
6478-
<< ExistingAttr->getImportModule() << AL.getImportModule();
6479-
Diag(AL.getLoc(), diag::note_previous_attribute);
6480-
return nullptr;
6481-
}
6482-
if (FD->hasBody()) {
6483-
Diag(AL.getLoc(), diag::warn_import_on_definition) << 0;
6484-
return nullptr;
6470+
static void handleWebAssemblyImportModuleAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
6471+
if (!isFunctionOrMethod(D)) {
6472+
S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
6473+
<< "'import_module'" << ExpectedFunction;
6474+
return;
64856475
}
6486-
return ::new (Context) WebAssemblyImportModuleAttr(Context, AL,
6487-
AL.getImportModule());
6488-
}
64896476

6490-
WebAssemblyImportNameAttr *
6491-
Sema::mergeImportNameAttr(Decl *D, const WebAssemblyImportNameAttr &AL) {
64926477
auto *FD = cast<FunctionDecl>(D);
6493-
6494-
if (const auto *ExistingAttr = FD->getAttr<WebAssemblyImportNameAttr>()) {
6495-
if (ExistingAttr->getImportName() == AL.getImportName())
6496-
return nullptr;
6497-
Diag(ExistingAttr->getLocation(), diag::warn_mismatched_import) << 1
6498-
<< ExistingAttr->getImportName() << AL.getImportName();
6499-
Diag(AL.getLoc(), diag::note_previous_attribute);
6500-
return nullptr;
6501-
}
6502-
if (FD->hasBody()) {
6503-
Diag(AL.getLoc(), diag::warn_import_on_definition) << 1;
6504-
return nullptr;
6478+
if (FD->isThisDeclarationADefinition()) {
6479+
S.Diag(D->getLocation(), diag::err_alias_is_definition) << FD << 0;
6480+
return;
65056481
}
6506-
return ::new (Context) WebAssemblyImportNameAttr(Context, AL,
6507-
AL.getImportName());
6508-
}
6509-
6510-
static void
6511-
handleWebAssemblyImportModuleAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
6512-
auto *FD = cast<FunctionDecl>(D);
65136482

65146483
StringRef Str;
65156484
SourceLocation ArgLoc;
65166485
if (!S.checkStringLiteralArgumentAttr(AL, 0, Str, &ArgLoc))
65176486
return;
6518-
if (FD->hasBody()) {
6519-
S.Diag(AL.getLoc(), diag::warn_import_on_definition) << 0;
6520-
return;
6521-
}
65226487

65236488
FD->addAttr(::new (S.Context)
65246489
WebAssemblyImportModuleAttr(S.Context, AL, Str));
65256490
}
65266491

6527-
static void
6528-
handleWebAssemblyImportNameAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
6492+
static void handleWebAssemblyImportNameAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
6493+
if (!isFunctionOrMethod(D)) {
6494+
S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
6495+
<< "'import_name'" << ExpectedFunction;
6496+
return;
6497+
}
6498+
65296499
auto *FD = cast<FunctionDecl>(D);
6500+
if (FD->isThisDeclarationADefinition()) {
6501+
S.Diag(D->getLocation(), diag::err_alias_is_definition) << FD << 0;
6502+
return;
6503+
}
65306504

65316505
StringRef Str;
65326506
SourceLocation ArgLoc;
65336507
if (!S.checkStringLiteralArgumentAttr(AL, 0, Str, &ArgLoc))
65346508
return;
6535-
if (FD->hasBody()) {
6536-
S.Diag(AL.getLoc(), diag::warn_import_on_definition) << 1;
6537-
return;
6538-
}
65396509

65406510
FD->addAttr(::new (S.Context) WebAssemblyImportNameAttr(S.Context, AL, Str));
65416511
}

‎clang/test/AST/ast-dump-wasm-attr-export.c

Lines changed: 0 additions & 33 deletions
This file was deleted.

‎clang/test/AST/ast-dump-wasm-attr-import.c

Lines changed: 0 additions & 36 deletions
This file was deleted.

‎clang/test/Driver/hip-include-path.hip

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,13 +19,13 @@
1919
// NOWRAP-NOT: clang/{{.*}}/include/cuda_wrappers
2020
// HIP: {{.*}}Inputs/rocm/include
2121
// NOHIP-NOT: {{.*}}Inputs/rocm/include
22-
// COMMON: {{.*}}include/c++
22+
// skip check of standard C++ include path
2323
// COMMON: clang/{{.*}}/include
2424

2525
// COMMON-LABEL: clang{{.*}} -cc1 -triple x86_64
2626
// WRAP: clang/{{.*}}/include/cuda_wrappers
2727
// NOWRAP-NOT: clang/{{.*}}/include/cuda_wrappers
2828
// HIP: {{.*}}Inputs/rocm/include
2929
// NOHIP-NOT: {{.*}}Inputs/rocm/include
30-
// COMMON: {{.*}}include/c++
30+
// skip check of standard C++ include path
3131
// COMMON: clang/{{.*}}/include

‎clang/test/Sema/attr-wasm.c

Lines changed: 0 additions & 27 deletions
This file was deleted.

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1725,7 +1725,7 @@ class AMDGPUBufferAtomicNoRtn : Intrinsic <
17251725
llvm_i32_ty, // vindex(VGPR)
17261726
llvm_i32_ty, // offset(SGPR/VGPR/imm)
17271727
llvm_i1_ty], // slc(imm)
1728-
[], "", [SDNPMemOperand]>,
1728+
[ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
17291729
AMDGPURsrcIntrinsic<1, 0>;
17301730

17311731
class AMDGPUGlobalAtomicNoRtn : Intrinsic <

‎llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,7 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
216216

217217
bool InsertExport = false;
218218

219+
bool Changed = false;
219220
for (BasicBlock *BB : PDT.getRoots()) {
220221
if (isa<ReturnInst>(BB->getTerminator())) {
221222
if (!isUniformlyReached(DA, *BB))
@@ -281,6 +282,7 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
281282
BB->getTerminator()->eraseFromParent();
282283
BranchInst::Create(TransitionBB, DummyReturnBB, BoolTrue, BB);
283284
}
285+
Changed = true;
284286
}
285287
}
286288

@@ -299,6 +301,7 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
299301
BB->getTerminator()->eraseFromParent();
300302
BranchInst::Create(UnreachableBlock, BB);
301303
}
304+
Changed = true;
302305
}
303306

304307
if (!ReturningBlocks.empty()) {
@@ -322,15 +325,16 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
322325
// actually reached here.
323326
ReturnInst::Create(F.getContext(), RetVal, UnreachableBlock);
324327
ReturningBlocks.push_back(UnreachableBlock);
328+
Changed = true;
325329
}
326330
}
327331

328332
// Now handle return blocks.
329333
if (ReturningBlocks.empty())
330-
return false; // No blocks return
334+
return Changed; // No blocks return
331335

332336
if (ReturningBlocks.size() == 1 && !InsertExport)
333-
return false; // Already has a single return block
337+
return Changed; // Already has a single return block
334338

335339
const TargetTransformInfo &TTI
336340
= getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1422,8 +1422,10 @@ multiclass BufferAtomicPatterns_NO_RTN<SDPatternOperator name, ValueType vt,
14221422
>;
14231423
}
14241424

1425+
let SubtargetPredicate = HasAtomicFaddInsts in {
14251426
defm : BufferAtomicPatterns_NO_RTN<SIbuffer_atomic_fadd, f32, "BUFFER_ATOMIC_ADD_F32">;
14261427
defm : BufferAtomicPatterns_NO_RTN<SIbuffer_atomic_pk_fadd, v2f16, "BUFFER_ATOMIC_PK_ADD_F16">;
1428+
}
14271429

14281430
def : GCNPat<
14291431
(SIbuffer_atomic_cmpswap

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14460,7 +14460,6 @@ static SDValue PerformVMOVNCombine(SDNode *N,
1446014460
static SDValue PerformVQMOVNCombine(SDNode *N,
1446114461
TargetLowering::DAGCombinerInfo &DCI) {
1446214462
SDValue Op0 = N->getOperand(0);
14463-
SDValue Op1 = N->getOperand(1);
1446414463
unsigned IsTop = N->getConstantOperandVal(2);
1446514464

1446614465
unsigned NumElts = N->getValueType(0).getVectorNumElements();

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41439,14 +41439,22 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
4143941439
getTargetConstantBitsFromNode(N0, NumBitsPerElt, UndefElts, EltBits)) {
4144041440
assert(EltBits.size() == VT.getVectorNumElements() &&
4144141441
"Unexpected shift value type");
41442-
for (APInt &Elt : EltBits) {
41443-
if (X86ISD::VSHLI == Opcode)
41442+
// Undef elements need to fold to 0. It's possible SimplifyDemandedBits
41443+
// created an undef input due to no input bits being demanded, but user
41444+
// still expects 0 in other bits.
41445+
for (unsigned i = 0, e = EltBits.size(); i != e; ++i) {
41446+
APInt &Elt = EltBits[i];
41447+
if (UndefElts[i])
41448+
Elt = 0;
41449+
else if (X86ISD::VSHLI == Opcode)
4144441450
Elt <<= ShiftVal;
4144541451
else if (X86ISD::VSRAI == Opcode)
4144641452
Elt.ashrInPlace(ShiftVal);
4144741453
else
4144841454
Elt.lshrInPlace(ShiftVal);
4144941455
}
41456+
// Reset undef elements since they were zeroed above.
41457+
UndefElts = 0;
4145041458
return getConstVector(EltBits, UndefElts, VT.getSimpleVT(), DAG, SDLoc(N));
4145141459
}
4145241460

‎llvm/test/CodeGen/AMDGPU/fail-select-buffer-atomic-fadd.ll

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -o /dev/null %s 2>&1 | FileCheck -check-prefix=FAIL %s
2+
; RUN: not --crash llc -march=amdgcn -mcpu=hawaii -o /dev/null %s 2>&1 | FileCheck -check-prefix=FAIL %s
3+
; RUN: not --crash llc -march=amdgcn -mcpu=fiji -o /dev/null %s 2>&1 | FileCheck -check-prefix=FAIL %s
4+
; RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -o /dev/null %s 2>&1 | FileCheck -check-prefix=FAIL %s
5+
; RUN: not --crash llc -march=amdgcn -mcpu=gfx1010 -o /dev/null %s 2>&1 | FileCheck -check-prefix=FAIL %s
6+
7+
; Make sure selection of these intrinsics fails on targets that do not
8+
; have the instruction available.
9+
; FIXME: Should also really make sure the v2f16 version fails.
10+
11+
; FAIL: LLVM ERROR: Cannot select: {{.+}}: ch = BUFFER_ATOMIC_FADD
12+
define amdgpu_cs void @atomic_fadd(<4 x i32> inreg %arg0) {
13+
call void @llvm.amdgcn.buffer.atomic.fadd.f32(float 1.0, <4 x i32> %arg0, i32 0, i32 112, i1 false)
14+
ret void
15+
}
16+
17+
declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1 immarg) #0
18+
19+
attributes #0 = { nounwind }

‎llvm/test/CodeGen/X86/vec_shift5.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ define <4 x i32> @test10() {
149149
define <2 x i64> @test11() {
150150
; X32-LABEL: test11:
151151
; X32: # %bb.0:
152-
; X32-NEXT: movaps {{.*#+}} xmm0 = <u,u,3,0>
152+
; X32-NEXT: movaps {{.*#+}} xmm0 = [0,0,3,0]
153153
; X32-NEXT: retl
154154
;
155155
; X64-LABEL: test11:
@@ -219,7 +219,7 @@ define <4 x i32> @test15() {
219219
define <2 x i64> @test16() {
220220
; X32-LABEL: test16:
221221
; X32: # %bb.0:
222-
; X32-NEXT: movaps {{.*#+}} xmm0 = <u,u,248,0>
222+
; X32-NEXT: movaps {{.*#+}} xmm0 = [0,0,248,0]
223223
; X32-NEXT: retl
224224
;
225225
; X64-LABEL: test16:

‎llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -703,3 +703,12 @@ define void @test_mfma_f32_32x32x1f32(float %arg0, float %arg1, <32 x i32> %arg2
703703

704704
ret void
705705
}
706+
707+
declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
708+
define amdgpu_cs void @test_buffer_atomic_fadd(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %offset, i1 %slc) {
709+
; CHECK: immarg operand has non-immediate parameter
710+
; CHECK-NEXT: i1 %slc
711+
; CHECK-ENXT: call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
712+
call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %offset, i1 %slc)
713+
ret void
714+
}

‎llvm/utils/gn/secondary/clang/test/BUILD.gn

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ write_lit_config("lit_site_cfg") {
4848
"CLANG_DEFAULT_CXX_STDLIB=", # Empty string means "default value" here.
4949
"CLANG_DEFAULT_LINKER=",
5050
"CLANG_TOOLS_DIR=" + rebase_path("$root_out_dir/bin", dir),
51+
"CLANG_VENDOR_UTI=org.llvm.clang",
5152

5253
# This is only used if LLVM_USE_SANITIZER includes lsan and the host
5354
# OS is macOS. Since the GN build currently never uses LLVM_USE_SANITIZER,

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