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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | +; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GCN %s |
| 3 | + |
| 4 | +; An assert was hit when frame offset register was used to address FrameIndex. |
| 5 | +define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <4 x i32> addrspace(1)* %input, <4 x float> addrspace(1)* %output, i32 %i) { |
| 6 | +; GCN-LABEL: kernel_background_evaluate: |
| 7 | +; GCN: ; %bb.0: ; %entry |
| 8 | +; GCN-NEXT: s_load_dword s6, s[0:1], 0x24 |
| 9 | +; GCN-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 |
| 10 | +; GCN-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 |
| 11 | +; GCN-NEXT: s_mov_b32 s38, -1 |
| 12 | +; GCN-NEXT: s_mov_b32 s39, 0x31c16000 |
| 13 | +; GCN-NEXT: s_mov_b32 s33, s3 |
| 14 | +; GCN-NEXT: s_mov_b64 s[0:1], s[36:37] |
| 15 | +; GCN-NEXT: v_mov_b32_e32 v1, 0x2000 |
| 16 | +; GCN-NEXT: v_mov_b32_e32 v2, 0x4000 |
| 17 | +; GCN-NEXT: s_mov_b64 s[2:3], s[38:39] |
| 18 | +; GCN-NEXT: v_mov_b32_e32 v3, 0 |
| 19 | +; GCN-NEXT: v_mov_b32_e32 v4, 0x400000 |
| 20 | +; GCN-NEXT: s_add_u32 s32, s33, 0xc0000 |
| 21 | +; GCN-NEXT: v_add_nc_u32_e64 v32, 4, 0x4000 |
| 22 | +; GCN-NEXT: ; implicit-def: $vcc_hi |
| 23 | +; GCN-NEXT: s_getpc_b64 s[4:5] |
| 24 | +; GCN-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4 |
| 25 | +; GCN-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+4 |
| 26 | +; GCN-NEXT: s_waitcnt lgkmcnt(0) |
| 27 | +; GCN-NEXT: v_mov_b32_e32 v0, s6 |
| 28 | +; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] |
| 29 | +; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 |
| 30 | +; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| 31 | +; GCN-NEXT: ; mask branch BB0_2 |
| 32 | +; GCN-NEXT: s_cbranch_execz BB0_2 |
| 33 | +; GCN-NEXT: BB0_1: ; %if.then4.i |
| 34 | +; GCN-NEXT: buffer_load_dword v0, v32, s[36:39], s32 offen |
| 35 | +; GCN-NEXT: buffer_load_dword v1, v32, s[36:39], s32 offen offset:4 |
| 36 | +; GCN-NEXT: s_waitcnt vmcnt(0) |
| 37 | +; GCN-NEXT: v_add_nc_u32_e32 v0, v1, v0 |
| 38 | +; GCN-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0 |
| 39 | +; GCN-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0 |
| 40 | +; GCN-NEXT: buffer_store_dword v0, v0, s[36:39], s33 offen |
| 41 | +; GCN-NEXT: BB0_2: ; %shader_eval_surface.exit |
| 42 | +; GCN-NEXT: s_endpgm |
| 43 | +entry: |
| 44 | + %sd = alloca < 1339 x i32>, align 16, addrspace(5) |
| 45 | + %state = alloca <4 x i32>, align 4, addrspace(5) |
| 46 | + %rslt = call i32 @svm_eval_nodes(float addrspace(5)* %kg, <1339 x i32> addrspace(5)* %sd, <4 x i32> addrspace(5)* %state, i32 0, i32 4194304) |
| 47 | + %cmp = icmp eq i32 %rslt, 0 |
| 48 | + br i1 %cmp, label %shader_eval_surface.exit, label %if.then4.i |
| 49 | + |
| 50 | +if.then4.i: ; preds = %entry |
| 51 | + %rng_hash.i.i = getelementptr inbounds < 4 x i32>, <4 x i32> addrspace(5)* %state, i32 0, i32 1 |
| 52 | + %tmp0 = load i32, i32 addrspace(5)* %rng_hash.i.i, align 4 |
| 53 | + %rng_offset.i.i = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %state, i32 0, i32 2 |
| 54 | + %tmp1 = load i32, i32 addrspace(5)* %rng_offset.i.i, align 4 |
| 55 | + %add.i.i = add i32 %tmp1, %tmp0 |
| 56 | + %add1.i.i = add i32 %add.i.i, 0 |
| 57 | + %mul.i.i.i.i = mul i32 %add1.i.i, 1103515245 |
| 58 | + %add.i.i.i.i = add i32 %mul.i.i.i.i, 12345 |
| 59 | + store i32 %add.i.i.i.i, i32 addrspace(5)* undef, align 16 |
| 60 | + br label %shader_eval_surface.exit |
| 61 | + |
| 62 | +shader_eval_surface.exit: ; preds = %entry |
| 63 | + ret void |
| 64 | +} |
| 65 | + |
| 66 | +declare hidden i32 @svm_eval_nodes(float addrspace(5)*, <1339 x i32> addrspace(5)*, <4 x i32> addrspace(5)*, i32, i32) local_unnamed_addr |
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