From f1454efd0e5256502346f26e3c24abd36b702811 Mon Sep 17 00:00:00 2001 From: Artem Gindinson Date: Thu, 18 Jul 2019 19:35:19 +0300 Subject: [PATCH] Sync with SPIR-V Translator de0957d85bcaa The sync brings the following commits: [de0957d85bcaa] Disabling mem2reg by default [e963d8deacece] Translate __fpga_reg builtin to FPGARegINTEL instruction Signed-off-by: Artem Gindinson --- llvm-spirv/lib/SPIRV/OCLUtil.h | 1 + llvm-spirv/lib/SPIRV/SPIRVReader.cpp | 46 ++ llvm-spirv/lib/SPIRV/SPIRVWriter.cpp | 55 ++- llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h | 4 +- .../lib/SPIRV/libSPIRV/SPIRVInstruction.h | 23 + .../lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h | 1 + llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp | 11 + llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h | 2 + .../lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 1 + .../lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h | 1 + llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp | 2 + llvm-spirv/test/AtomicCompareExchange_cl20.ll | 29 +- .../test/DebugInfo/BuiltinCallLocation.cl | 2 +- .../test/DebugInfo/DebugDeclareUnused.cl | 4 +- llvm-spirv/test/IntelFPGAReg.ll | 451 ++++++++++++++++++ llvm-spirv/test/OpSwitch32.ll | 2 +- llvm-spirv/test/OpSwitch64.ll | 2 +- llvm-spirv/test/image-unoptimized.ll | 77 --- 18 files changed, 603 insertions(+), 111 deletions(-) create mode 100644 llvm-spirv/test/IntelFPGAReg.ll delete mode 100644 llvm-spirv/test/image-unoptimized.ll diff --git a/llvm-spirv/lib/SPIRV/OCLUtil.h b/llvm-spirv/lib/SPIRV/OCLUtil.h index 1f17468ac434b..d952634a572e7 100644 --- a/llvm-spirv/lib/SPIRV/OCLUtil.h +++ b/llvm-spirv/lib/SPIRV/OCLUtil.h @@ -165,6 +165,7 @@ const static char Dot[] = "dot"; const static char EnqueueKernel[] = "enqueue_kernel"; const static char FMax[] = "fmax"; const static char FMin[] = "fmin"; +const static char FPGARegIntel[] = "__builtin_intel_fpga_reg"; const static char GetFence[] = "get_fence"; const static char GetImageArraySize[] = "get_image_array_size"; const static char GetImageChannelOrder[] = "get_image_channel_order"; diff --git a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp index d5708d23ad6d6..967398bc52705 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp +++ b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp @@ -1756,6 +1756,52 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F, case OpGetKernelNDrangeSubGroupCount: return mapValue( BV, transSGSizeQueryBI(static_cast(BV), BB)); + case OpFPGARegINTEL: { + IRBuilder<> Builder(BB); + + SPIRVFPGARegINTELInstBase *BC = + static_cast(BV); + + PointerType *Int8PtrTyPrivate = + Type::getInt8PtrTy(*Context, SPIRAS_Private); + IntegerType *Int32Ty = Type::getInt32Ty(*Context); + + Value *UndefInt8Ptr = UndefValue::get(Int8PtrTyPrivate); + Value *UndefInt32 = UndefValue::get(Int32Ty); + + Constant *GS = Builder.CreateGlobalStringPtr(kOCLBuiltinName::FPGARegIntel); + + Type *Ty = transType(BC->getType()); + Value *Val = transValue(BC->getOperand(0), F, BB); + + Value *ValAsArg = Val; + Type *RetTy = Ty; + auto IID = Intrinsic::annotation; + if (!isa(Ty)) { + // All scalar types can be bitcasted to a same-sized integer + if (!isa(Ty) && !isa(Ty)) { + RetTy = IntegerType::get(*Context, Ty->getPrimitiveSizeInBits()); + ValAsArg = Builder.CreateBitCast(Val, RetTy); + } + // If pointer type or struct type + else { + IID = Intrinsic::ptr_annotation; + auto *PtrTy = dyn_cast(Ty); + if (PtrTy && isa(PtrTy->getElementType())) + RetTy = PtrTy; + // Whether a struct or a pointer to some other type, + // bitcast to i8* + else { + RetTy = Int8PtrTyPrivate; + ValAsArg = Builder.CreateBitCast(Val, Int8PtrTyPrivate); + } + } + } + + Value *Args[] = {ValAsArg, GS, UndefInt8Ptr, UndefInt32}; + auto *IntrinsicCall = Builder.CreateIntrinsic(IID, RetTy, Args); + return mapValue(BV, IntrinsicCall); + } default: { auto OC = BV->getOpCode(); if (isSPIRVCmpInstTransToLLVMInst(static_cast(BV))) { diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp index 8219935fc5bec..34f1256880621 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp +++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp @@ -87,7 +87,7 @@ using namespace OCLUtil; namespace SPIRV { -cl::opt SPIRVMemToReg("spirv-mem2reg", cl::init(true), +cl::opt SPIRVMemToReg("spirv-mem2reg", cl::init(false), cl::desc("LLVM/SPIR-V translation enable mem2reg")); cl::opt SPIRVNoDerefAttr( @@ -258,7 +258,7 @@ SPIRVType *LLVMToSPIRV::transType(Type *T) { return mapType(T, BM->addFloatType(T->getPrimitiveSizeInBits())); // A pointer to image or pipe type in LLVM is translated to a SPIRV - // sampler or pipe type. + // (non-pointer) image or pipe type. if (T->isPointerTy()) { auto ET = T->getPointerElementType(); assert(!ET->isFunctionTy() && "Function pointer type is not allowed"); @@ -1322,6 +1322,22 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II, return DbgTran->createDebugDeclarePlaceholder(cast(II), BB); case Intrinsic::dbg_value: return DbgTran->createDebugValuePlaceholder(cast(II), BB); + case Intrinsic::annotation: { + SPIRVType *Ty = transType(II->getType()); + + GetElementPtrInst *GEP = dyn_cast(II->getArgOperand(1)); + if (!GEP) + return nullptr; + Constant *C = cast(GEP->getOperand(0)); + // TODO: Refactor to use getConstantStringInfo() + StringRef AnnotationString = + cast(C->getOperand(0))->getAsCString(); + + if (AnnotationString == kOCLBuiltinName::FPGARegIntel) + return BM->addFPGARegINTELInst(Ty, transValue(II->getOperand(0), BB), BB); + + return nullptr; + } case Intrinsic::var_annotation: { SPIRVValue *SV; if (auto *BI = dyn_cast(II->getArgOperand(0))) { @@ -1332,6 +1348,7 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II, GetElementPtrInst *GEP = cast(II->getArgOperand(1)); Constant *C = cast(GEP->getOperand(0)); + // TODO: Refactor to use getConstantStringInfo() StringRef AnnotationString = cast(C->getOperand(0))->getAsString(); @@ -1352,28 +1369,34 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II, } else { GI = dyn_cast(II->getOperand(0)); } - SPIRVType *Ty = transType(GI->getSourceElementType()); - - SPIRVWord MemberNumber = - dyn_cast(GI->getOperand(2))->getZExtValue(); GetElementPtrInst *GEP = dyn_cast(II->getArgOperand(1)); Constant *C = dyn_cast(GEP->getOperand(0)); + // TODO: Refactor to use getConstantStringInfo() StringRef AnnotationString = - dyn_cast(C->getOperand(0))->getAsString(); + dyn_cast(C->getOperand(0))->getAsCString(); - std::vector> Decorations = - parseAnnotations(AnnotationString); + if (GI) { + auto *Ty = transType(GI->getSourceElementType()); + SPIRVWord MemberNumber = + dyn_cast(GI->getOperand(2))->getZExtValue(); - if (Decorations.empty()) { - Ty->addMemberDecorate(new SPIRVMemberDecorateUserSemanticAttr( - Ty, MemberNumber, - AnnotationString.substr(0, AnnotationString.size() - 1))); + std::vector> Decorations = + parseAnnotations(AnnotationString); + + if (Decorations.empty()) { + Ty->addMemberDecorate(new SPIRVMemberDecorateUserSemanticAttr( + Ty, MemberNumber, AnnotationString)); + } else { + addIntelFPGADecorationsForStructMember(Ty, MemberNumber, Decorations); + } + II->replaceAllUsesWith(II->getOperand(0)); } else { - addIntelFPGADecorationsForStructMember(Ty, MemberNumber, Decorations); + auto *Ty = transType(II->getType()); + auto *BI = dyn_cast(II->getOperand(0)); + if (AnnotationString == kOCLBuiltinName::FPGARegIntel) + return BM->addFPGARegINTELInst(Ty, transValue(BI, BB), BB); } - - II->replaceAllUsesWith(II->getOperand(0)); return 0; } default: diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h index bc14c7f3913df..97af2669f868a 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h @@ -117,7 +117,8 @@ enum SPIRVExtensionKind { SPV_INTEL_blocking_pipes, SPV_INTEL_device_side_avc_motion_estimation, SPV_KHR_no_integer_wrap_decoration, - SPV_INTEL_fpga_memory_attributes + SPV_INTEL_fpga_memory_attributes, + SPV_INTEL_fpga_reg }; typedef std::set SPIRVExtSet; @@ -128,6 +129,7 @@ template <> inline void SPIRVMap::init() { "SPV_INTEL_device_side_avc_motion_estimation"); add(SPV_KHR_no_integer_wrap_decoration, "SPV_KHR_no_integer_wrap_decoration"); add(SPV_INTEL_fpga_memory_attributes, "SPV_INTEL_fpga_memory_attributes"); + add(SPV_INTEL_fpga_reg, "SPV_INTEL_fpga_reg"); } template <> inline void SPIRVMap::init() { diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h index 19aab59ff1d07..2616fbbc5af90 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h @@ -873,6 +873,29 @@ class SPIRVPhi : public SPIRVInstruction { std::vector Pairs; }; +class SPIRVFPGARegINTELInstBase : public SPIRVInstTemplateBase { +public: + SPIRVCapVec getRequiredCapability() const override { + return getVec(CapabilityFPGARegINTEL); + } + + SPIRVExtSet getRequiredExtensions() const override { + return getSet(SPV_INTEL_fpga_reg); + } + +protected: + void validate() const override { + SPIRVInstruction::validate(); + + assert(OpCode == OpFPGARegINTEL && + "Invalid op code for FPGARegINTEL instruction"); + assert(getType() == getValueType(Ops[0]) && "Inconsistent type"); + } +}; + +typedef SPIRVInstTemplate + SPIRVFPGARegINTEL; + class SPIRVCompare : public SPIRVInstTemplateBase { protected: void validate() const override { diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h index 2aca2ff2a15fb..f4c37339f9eb4 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h @@ -1002,6 +1002,7 @@ inline bool isValid(spv::Op V) { case OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL: case OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL: case OpSubgroupAvcSicGetInterRawSadsINTEL: + case OpFPGARegINTEL: return true; default: return false; diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp index 977e6674d67f6..b4d332f92ec0f 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp @@ -363,6 +363,8 @@ class SPIRVModuleImpl : public SPIRVModule { SPIRVInstruction *addVectorInsertDynamicInst(SPIRVValue *, SPIRVValue *, SPIRVValue *, SPIRVBasicBlock *) override; + SPIRVInstruction *addFPGARegINTELInst(SPIRVType *, SPIRVValue *, + SPIRVBasicBlock *) override; virtual SPIRVId getExtInstSetId(SPIRVExtInstSetKind Kind) const override; @@ -1290,6 +1292,15 @@ SPIRVInstruction *SPIRVModuleImpl::addCopyMemorySizedInst( BB); } +SPIRVInstruction *SPIRVModuleImpl::addFPGARegINTELInst(SPIRVType *Type, + SPIRVValue *V, + SPIRVBasicBlock *BB) { + return addInstruction( + SPIRVInstTemplateBase::create(OpFPGARegINTEL, Type, getId(), + getVec(V->getId()), BB, this), + BB); +} + SPIRVInstruction *SPIRVModuleImpl::addVariable( SPIRVType *Type, bool IsConstant, SPIRVLinkageTypeKind LinkageType, SPIRVValue *Initializer, const std::string &Name, diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h index c61dd1e777382..ba5b5194ad872 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h @@ -375,6 +375,8 @@ class SPIRVModule { SPIRVValue *, SPIRVValue *, SPIRVBasicBlock *) = 0; + virtual SPIRVInstruction *addFPGARegINTELInst(SPIRVType *, SPIRVValue *, + SPIRVBasicBlock *) = 0; virtual SPIRVId getExtInstSetId(SPIRVExtInstSetKind Kind) const = 0; // I/O functions diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index 8c05fd13b1655..fdc6d1acfb8e3 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -490,6 +490,7 @@ template <> inline void SPIRVMap::init() { add(CapabilityFPGAMemoryAttributesINTEL, "FPGAMemoryAttributesINTEL"); add(CapabilityFPGALoopControlsINTEL, "FPGALoopControlsINTEL"); add(CapabilityBlockingPipesINTEL, "BlockingPipesINTEL"); + add(CapabilityFPGARegINTEL, "FPGARegINTEL"); } SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap) diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h index 49404bab4a28d..608e18eb92b0b 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h @@ -431,3 +431,4 @@ _SPIRV_OP(SubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL, 5815) _SPIRV_OP(SubgroupAvcSicGetInterRawSadsINTEL, 5816) _SPIRV_OP(ReadPipeBlockingINTEL, 5946) _SPIRV_OP(WritePipeBlockingINTEL, 5947) +_SPIRV_OP(FPGARegINTEL, 5949) diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp index d83d4efc12fff..cb8f039704ca5 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp +++ b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp @@ -681,6 +681,7 @@ enum Capability { CapabilityFPGAMemoryAttributesINTEL = 5824, CapabilityFPGALoopControlsINTEL = 5888, CapabilityBlockingPipesINTEL = 5945, + CapabilityFPGARegINTEL = 5948, CapabilityMax = 0x7fffffff, }; @@ -1127,6 +1128,7 @@ enum Op { OpSubgroupAvcSicGetInterRawSadsINTEL = 5816, OpReadPipeBlockingINTEL = 5946, OpWritePipeBlockingINTEL = 5947, + OpFPGARegINTEL = 5949, OpMax = 0x7fffffff, }; diff --git a/llvm-spirv/test/AtomicCompareExchange_cl20.ll b/llvm-spirv/test/AtomicCompareExchange_cl20.ll index b7a16a23fb0c7..f81d052e46d10 100644 --- a/llvm-spirv/test/AtomicCompareExchange_cl20.ll +++ b/llvm-spirv/test/AtomicCompareExchange_cl20.ll @@ -11,9 +11,6 @@ target triple = "spir-unknown-unknown" ; Int64Atomics capability must be declared only if atomic builtins have 64-bit integers arguments. ; CHECK-NOT: Capability Int64Atomics -; CHECK: Name [[Pointer:[0-9]+]] "object" -; CHECK: Name [[ComparatorPtr:[0-9]+]] "expected" -; CHECK: Name [[Value:[0-9]+]] "desired" ; CHECK: 4 TypeInt [[int:[0-9]+]] 32 0 ; CHECK: Constant [[int]] [[DeviceScope:[0-9]+]] 1 ; CHECK: Constant [[int]] [[SequentiallyConsistent_MS:[0-9]+]] 16 @@ -22,9 +19,9 @@ target triple = "spir-unknown-unknown" ; Function Attrs: nounwind define spir_func void @test(i32 addrspace(4)* %object, i32 addrspace(4)* %expected, i32 %desired) #0 { -; CHECK: FunctionParameter [[int_ptr]] [[Pointer]] -; CHECK: FunctionParameter [[int_ptr]] [[ComparatorPtr]] -; CHECK: FunctionParameter [[int]] [[Value]] +; CHECK: FunctionParameter [[int_ptr]] [[object:[0-9]+]] +; CHECK: FunctionParameter [[int_ptr]] [[expected:[0-9]+]] +; CHECK: FunctionParameter [[int]] [[desired:[0-9]+]] entry: %object.addr = alloca i32 addrspace(4)*, align 4 @@ -39,11 +36,16 @@ entry: %0 = load i32 addrspace(4)*, i32 addrspace(4)** %object.addr, align 4 %1 = load i32 addrspace(4)*, i32 addrspace(4)** %expected.addr, align 4 %2 = load i32, i32* %desired.addr, align 4 - - %call = call spir_func zeroext i1 @_Z30atomic_compare_exchange_strongPVU3AS4U7_AtomiciPU3AS4ii(i32 addrspace(4)* %0, i32 addrspace(4)* %1, i32 %2) -; CHECK: Load [[int]] [[Comparator:[0-9]+]] [[ComparatorPtr]] +; CHECK: Store [[object_addr:[0-9]+]] [[object]] +; CHECK: Store [[expected_addr:[0-9]+]] [[expected]] +; CHECK: Store [[desired_addr:[0-9]+]] [[desired]] +; CHECK: Load [[int_ptr]] [[Pointer:[0-9]+]] [[object_addr]] +; CHECK: Load [[int_ptr]] [[exp:[0-9]+]] [[expected_addr]] +; CHECK: Load [[int]] [[Value:[0-9]+]] [[desired_addr]] +; CHECK: Load [[int]] [[Comparator:[0-9]+]] [[exp]] ; CHECK-NEXT: 9 AtomicCompareExchange [[int]] [[Result:[0-9]+]] [[Pointer]] [[DeviceScope]] [[SequentiallyConsistent_MS]] [[SequentiallyConsistent_MS]] [[Value]] [[Comparator]] -; CHECK-NEXT: Store [[ComparatorPtr]] [[Result]] + %call = call spir_func zeroext i1 @_Z30atomic_compare_exchange_strongPVU3AS4U7_AtomiciPU3AS4ii(i32 addrspace(4)* %0, i32 addrspace(4)* %1, i32 %2) +; CHECK-NEXT: Store [[exp]] [[Result]] ; CHECK-NEXT: IEqual [[bool]] [[CallRes:[0-9]+]] [[Result]] [[Comparator]] ; CHECK-NOT: [[Result]] %frombool = zext i1 %call to i8 @@ -57,10 +59,13 @@ entry: %5 = load i32 addrspace(4)*, i32 addrspace(4)** %expected.addr, align 4 %6 = load i32, i32* %desired.addr, align 4 +; CHECK: Load [[int_ptr]] [[Pointer:[0-9]+]] [[object_addr]] +; CHECK: Load [[int_ptr]] [[exp:[0-9]+]] [[expected_addr]] +; CHECK: Load [[int]] [[Value:[0-9]+]] [[desired_addr]] +; CHECK: Load [[int]] [[ComparatorWeak:[0-9]+]] [[exp]] %call2 = call spir_func zeroext i1 @_Z28atomic_compare_exchange_weakPVU3AS4U7_AtomiciPU3AS4ii(i32 addrspace(4)* %4, i32 addrspace(4)* %5, i32 %6) -; CHECK: Load [[int]] [[ComparatorWeak:[0-9]+]] [[ComparatorPtr]] ; CHECK-NEXT: 9 AtomicCompareExchangeWeak [[int]] [[Result:[0-9]+]] [[Pointer]] [[DeviceScope]] [[SequentiallyConsistent_MS]] [[SequentiallyConsistent_MS]] [[Value]] [[ComparatorWeak]] -; CHECK-NEXT: Store [[ComparatorPtr]] [[Result]] +; CHECK-NEXT: Store [[exp]] [[Result]] ; CHECK-NEXT: IEqual [[bool]] [[CallRes:[0-9]+]] [[Result]] [[ComparatorWeak]] ; CHECK-NOT: [[Result]] diff --git a/llvm-spirv/test/DebugInfo/BuiltinCallLocation.cl b/llvm-spirv/test/DebugInfo/BuiltinCallLocation.cl index 49b0cdd6fcc4c..38fc45c090252 100644 --- a/llvm-spirv/test/DebugInfo/BuiltinCallLocation.cl +++ b/llvm-spirv/test/DebugInfo/BuiltinCallLocation.cl @@ -8,7 +8,7 @@ // CHECK-SPIRV: Label // CHECK-SPIRV: ExtInst {{.*}} DebugScope // CHECK-SPIRV: ExtInst {{.*}} sin -// CHECK-LLVM: call spir_func float @_Z3sinf(float %x) {{.*}} !dbg ![[loc:[0-9]+]] +// CHECK-LLVM: call spir_func float @_Z3sinf(float %{{.*}}) {{.*}} !dbg ![[loc:[0-9]+]] // CHECK-LLVM: ![[loc]] = !DILocation(line: 14, column: 10, scope: !{{.*}}) float f(float x) { return sin(x); diff --git a/llvm-spirv/test/DebugInfo/DebugDeclareUnused.cl b/llvm-spirv/test/DebugInfo/DebugDeclareUnused.cl index f51c790aa74b8..9e624a3fac6b5 100644 --- a/llvm-spirv/test/DebugInfo/DebugDeclareUnused.cl +++ b/llvm-spirv/test/DebugInfo/DebugDeclareUnused.cl @@ -1,7 +1,7 @@ // Check that we can translate llvm.dbg.declare for a local variable which was -// deleted by mem2reg pass(enabled by default in llvm-spirv) +// deleted by mem2reg pass(disabled by default in llvm-spirv) -// RUN: %clang_cc1 %s -triple spir -disable-llvm-passes -debug-info-kind=standalone -emit-llvm-bc -o - | llvm-spirv -o %t.spv +// RUN: %clang_cc1 %s -triple spir -disable-llvm-passes -debug-info-kind=standalone -emit-llvm-bc -o - | llvm-spirv -spirv-mem2reg -o %t.spv // RUN: llvm-spirv %t.spv -to-text -o - | FileCheck %s --check-prefix=CHECK-SPIRV // RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM diff --git a/llvm-spirv/test/IntelFPGAReg.ll b/llvm-spirv/test/IntelFPGAReg.ll new file mode 100644 index 0000000000000..075ffa5b727b2 --- /dev/null +++ b/llvm-spirv/test/IntelFPGAReg.ll @@ -0,0 +1,451 @@ +; LLVM IR for the test can be generated by SYCL Clang Compiler - +; see https://github.com/intel/llvm +; SYCL source code can be found below: + +; struct st { +; int a; +; float b; +; }; +; +; union un { +; int a; +; char c[4]; +; }; +; +; class A { +; public: +; A(int a) { +; m_val = a; +; } +; A(const A &a) { +; m_val = a.m_val; +; } +; private: +; int m_val; +; }; +; +; typedef int myInt; + +; void foo() { +; int a=123; +; myInt myA = 321; +; int b = __builtin_intel_fpga_reg(a); +; int myB = __builtin_intel_fpga_reg(myA); +; int c = __builtin_intel_fpga_reg(2.0f); +; int d = __builtin_intel_fpga_reg( __builtin_intel_fpga_reg( b+12 )); +; int e = __builtin_intel_fpga_reg( __builtin_intel_fpga_reg( a+b )); +; int f; +; f = __builtin_intel_fpga_reg(a); +; +; struct st i = {1, 5.0f}; +; struct st i2 = i; +; struct st ii = __builtin_intel_fpga_reg(i); +; struct st iii; +; iii = __builtin_intel_fpga_reg(ii); +; +; struct st *iiii = __builtin_intel_fpga_reg(&iii); +; +; union un u1 = {1}; +; union un u2, *u3; +; u2 = __builtin_intel_fpga_reg(u1); +; +; u3 = __builtin_intel_fpga_reg(&u2); +; +; A ca(213); +; A cb = __builtin_intel_fpga_reg(ca); + +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv %t.bc -o %t.spv +; RUN: llvm-spirv %t.spv -to-text -o %t.spt +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV + +; RUN: llvm-spirv -r %t.spv -o %t.rev.bc +; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV: Capability FPGARegINTEL +; CHECK-SPIRV: Extension "SPV_INTEL_fpga_reg" + +; CHECK-SPIRV-DAG: TypeInt [[TYPE_INT64:[0-9]+]] 64 0 +; CHECK-SPIRV-DAG: TypeInt [[TYPE_INT32:[0-9]+]] 32 0 +; CHECK-SPIRV-DAG: TypeInt [[TYPE_INT8:[0-9]+]] 8 0 +; CHECK-SPIRV-DAG: TypePointer [[TYPE_PTR:[0-9]+]] 7 [[TYPE_INT8]]{{ *$}} + +; CHECK-LLVM-DAG: @[[STR:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR1:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR2:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR3:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR4:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR5:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR6:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR7:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR8:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR9:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR10:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR11:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR12:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR13:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg +; CHECK-LLVM-DAG: @[[STR14:[0-9]+]] = {{.*}}__builtin_intel_fpga_reg + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir64-unknown-linux-sycldevice" + +%struct._ZTS2st.st = type { i32, float } +%union._ZTS2un.un = type { i32 } +%"class._ZTSZ4mainE3$_0.anon" = type { i8 } +%class._ZTS1A.A = type { i32 } + +$_ZN1AC1Ei = comdat any + +$_ZN1AC2Ei = comdat any + +@.str = private unnamed_addr constant [25 x i8] c"__builtin_intel_fpga_reg\00", section "llvm.metadata" +@.str.1 = private unnamed_addr constant [9 x i8] c"test.cpp\00", section "llvm.metadata" +@__const._Z3foov.i = private unnamed_addr constant %struct._ZTS2st.st { i32 1, float 5.000000e+00 }, align 4 +@__const._Z3foov.u1 = private unnamed_addr constant %union._ZTS2un.un { i32 1 }, align 4 + +; Function Attrs: nounwind +define spir_kernel void @_ZTSZ4mainE11fake_kernel() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 { +entry: + %0 = alloca %"class._ZTSZ4mainE3$_0.anon", align 1 + %1 = bitcast %"class._ZTSZ4mainE3$_0.anon"* %0 to i8* + call void @llvm.lifetime.start.p0i8(i64 1, i8* %1) #4 + %2 = addrspacecast %"class._ZTSZ4mainE3$_0.anon"* %0 to %"class._ZTSZ4mainE3$_0.anon" addrspace(4)* + call spir_func void @"_ZZ4mainENK3$_0clEv"(%"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %2) + %3 = bitcast %"class._ZTSZ4mainE3$_0.anon"* %0 to i8* + call void @llvm.lifetime.end.p0i8(i64 1, i8* %3) #4 + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: inlinehint nounwind +define internal spir_func void @"_ZZ4mainENK3$_0clEv"(%"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %this) #2 align 2 { +entry: + %this.addr = alloca %"class._ZTSZ4mainE3$_0.anon" addrspace(4)*, align 8 + store %"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %this, %"class._ZTSZ4mainE3$_0.anon" addrspace(4)** %this.addr, align 8, !tbaa !5 + %this1 = load %"class._ZTSZ4mainE3$_0.anon" addrspace(4)*, %"class._ZTSZ4mainE3$_0.anon" addrspace(4)** %this.addr, align 8 + call spir_func void @_Z3foov() + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: nounwind +define spir_func void @_Z3foov() #3 { +entry: + %a = alloca i32, align 4 + %myA = alloca i32, align 4 + %b = alloca i32, align 4 + %myB = alloca i32, align 4 + %c = alloca i32, align 4 + %d = alloca i32, align 4 + %e = alloca i32, align 4 + %f = alloca i32, align 4 + %i = alloca %struct._ZTS2st.st, align 4 + %i2 = alloca %struct._ZTS2st.st, align 4 + %ii = alloca %struct._ZTS2st.st, align 4 + %agg-temp = alloca %struct._ZTS2st.st, align 4 + %iii = alloca %struct._ZTS2st.st, align 4 + %ref.tmp = alloca %struct._ZTS2st.st, align 4 + %agg-temp2 = alloca %struct._ZTS2st.st, align 4 + %iiii = alloca %struct._ZTS2st.st addrspace(4)*, align 8 + %u1 = alloca %union._ZTS2un.un, align 4 + %u2 = alloca %union._ZTS2un.un, align 4 + %u3 = alloca %union._ZTS2un.un addrspace(4)*, align 8 + %ref.tmp3 = alloca %union._ZTS2un.un, align 4 + %agg-temp4 = alloca %union._ZTS2un.un, align 4 + %ca = alloca %class._ZTS1A.A, align 4 + %cb = alloca %class._ZTS1A.A, align 4 + %agg-temp5 = alloca %class._ZTS1A.A, align 4 + %ap = alloca i32 addrspace(4)*, align 8 + %bp = alloca i32 addrspace(4)*, align 8 + %0 = bitcast i32* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #4 + store i32 123, i32* %a, align 4, !tbaa !9 + %1 = bitcast i32* %myA to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %1) #4 + store i32 321, i32* %myA, align 4, !tbaa !9 + %2 = bitcast i32* %b to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %2) #4 + %3 = load i32, i32* %a, align 4, !tbaa !9 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR]] + %4 = call i32 @llvm.annotation.i32(i32 %3, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 35) + store i32 %4, i32* %b, align 4, !tbaa !9 + %5 = bitcast i32* %myB to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %5) #4 + %6 = load i32, i32* %myA, align 4, !tbaa !9 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR1]] + %7 = call i32 @llvm.annotation.i32(i32 %6, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 39) + store i32 %7, i32* %myB, align 4, !tbaa !9 + %8 = bitcast i32* %c to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %8) #4 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR2]] + %9 = call i32 @llvm.annotation.i32(i32 1073741824, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 43) + %10 = bitcast i32 %9 to float + %conv = fptosi float %10 to i32 + store i32 %conv, i32* %c, align 4, !tbaa !9 + %11 = bitcast i32* %d to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %11) #4 + %12 = load i32, i32* %b, align 4, !tbaa !9 + %add = add nsw i32 %12, 12 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR3]] + %13 = call i32 @llvm.annotation.i32(i32 %add, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 48) + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR4]] + %14 = call i32 @llvm.annotation.i32(i32 %13, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 48) + store i32 %14, i32* %d, align 4, !tbaa !9 + %15 = bitcast i32* %e to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %15) #4 + %16 = load i32, i32* %a, align 4, !tbaa !9 + %17 = load i32, i32* %b, align 4, !tbaa !9 + %add1 = add nsw i32 %16, %17 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR5]] + %18 = call i32 @llvm.annotation.i32(i32 %add1, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 54) + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR6]] + %19 = call i32 @llvm.annotation.i32(i32 %18, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 54) + store i32 %19, i32* %e, align 4, !tbaa !9 + %20 = bitcast i32* %f to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %20) #4 + %21 = load i32, i32* %a, align 4, !tbaa !9 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT32]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i32 @llvm.annotation.i32(i32 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR7]] + %22 = call i32 @llvm.annotation.i32(i32 %21, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 62) + store i32 %22, i32* %f, align 4, !tbaa !9 + %23 = bitcast %struct._ZTS2st.st* %i to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %23) #4 + %24 = bitcast %struct._ZTS2st.st* %i to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %24, i8* align 4 bitcast (%struct._ZTS2st.st* @__const._Z3foov.i to i8*), i64 8, i1 false) + %25 = bitcast %struct._ZTS2st.st* %i2 to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %25) #4 + %26 = bitcast %struct._ZTS2st.st* %i2 to i8* + %27 = bitcast %struct._ZTS2st.st* %i to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %26, i8* align 4 %27, i64 8, i1 false), !tbaa.struct !11 + %28 = bitcast %struct._ZTS2st.st* %ii to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %28) #4 + %29 = bitcast %struct._ZTS2st.st* %agg-temp to i8* + %30 = bitcast %struct._ZTS2st.st* %i to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %29, i8* align 4 %30, i64 8, i1 false), !tbaa.struct !11 + %31 = bitcast %struct._ZTS2st.st* %agg-temp to i8* + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_PTR]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i8* @llvm.ptr.annotation.p0i8(i8* %[[CAST1:[a-z0-9]+]], i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR8]] + ; CHECK-LLVM-DAG: %[[CAST1]] = bitcast %struct._ZTS2st.st* %agg-temp to i8* + %32 = call i8* @llvm.ptr.annotation.p0i8(i8* %31, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 69) + %33 = bitcast i8* %32 to %struct._ZTS2st.st* + %34 = bitcast %struct._ZTS2st.st* %ii to i8* + %35 = bitcast %struct._ZTS2st.st* %33 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %34, i8* align 4 %35, i64 8, i1 false) + %36 = bitcast %struct._ZTS2st.st* %iii to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %36) #4 + %37 = bitcast %struct._ZTS2st.st* %ref.tmp to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %37) #4 + %38 = bitcast %struct._ZTS2st.st* %agg-temp2 to i8* + %39 = bitcast %struct._ZTS2st.st* %ii to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %38, i8* align 4 %39, i64 8, i1 false), !tbaa.struct !11 + %40 = bitcast %struct._ZTS2st.st* %agg-temp2 to i8* + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_PTR]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i8* @llvm.ptr.annotation.p0i8(i8* %[[CAST2:[a-z0-9]+]], i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR9]] + ; CHECK-LLVM-DAG: %[[CAST2]] = bitcast %struct._ZTS2st.st* %agg-temp2 to i8* + %41 = call i8* @llvm.ptr.annotation.p0i8(i8* %40, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 80) + %42 = bitcast i8* %41 to %struct._ZTS2st.st* + %43 = bitcast %struct._ZTS2st.st* %ref.tmp to i8* + %44 = bitcast %struct._ZTS2st.st* %42 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %43, i8* align 4 %44, i64 8, i1 false) + %45 = bitcast %struct._ZTS2st.st* %iii to i8* + %46 = bitcast %struct._ZTS2st.st* %ref.tmp to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %45, i8* align 4 %46, i64 8, i1 false), !tbaa.struct !11 + %47 = bitcast %struct._ZTS2st.st* %ref.tmp to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %47) #4 + %48 = bitcast %struct._ZTS2st.st addrspace(4)** %iiii to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %48) #4 + %49 = ptrtoint %struct._ZTS2st.st* %iii to i64 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT64]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i64 @llvm.annotation.i64(i64 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR10]] + %50 = call i64 @llvm.annotation.i64(i64 %49, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 94) + %51 = inttoptr i64 %50 to %struct._ZTS2st.st* + %52 = addrspacecast %struct._ZTS2st.st* %51 to %struct._ZTS2st.st addrspace(4)* + store %struct._ZTS2st.st addrspace(4)* %52, %struct._ZTS2st.st addrspace(4)** %iiii, align 8, !tbaa !5 + %53 = bitcast %union._ZTS2un.un* %u1 to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %53) #4 + %54 = bitcast %union._ZTS2un.un* %u1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %54, i8* align 4 bitcast (%union._ZTS2un.un* @__const._Z3foov.u1 to i8*), i64 4, i1 false) + %55 = bitcast %union._ZTS2un.un* %u2 to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %55) #4 + %56 = bitcast %union._ZTS2un.un addrspace(4)** %u3 to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %56) #4 + %57 = bitcast %union._ZTS2un.un* %ref.tmp3 to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %57) #4 + %58 = bitcast %union._ZTS2un.un* %agg-temp4 to i8* + %59 = bitcast %union._ZTS2un.un* %u1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %58, i8* align 4 %59, i64 4, i1 false), !tbaa.struct !14 + %60 = bitcast %union._ZTS2un.un* %agg-temp4 to i8* + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_PTR]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i8* @llvm.ptr.annotation.p0i8(i8* %[[CAST4:[a-z0-9]+]], i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR11]] + ; CHECK-LLVM-DAG: %[[CAST4]] = bitcast %union._ZTS2un.un* %agg-temp4 to i8* + %61 = call i8* @llvm.ptr.annotation.p0i8(i8* %60, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 103) + %62 = bitcast i8* %61 to %union._ZTS2un.un* + %63 = bitcast %union._ZTS2un.un* %ref.tmp3 to i8* + %64 = bitcast %union._ZTS2un.un* %62 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %63, i8* align 4 %64, i64 8, i1 false) + %65 = bitcast %union._ZTS2un.un* %u2 to i8* + %66 = bitcast %union._ZTS2un.un* %ref.tmp3 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %65, i8* align 4 %66, i64 4, i1 false), !tbaa.struct !14 + %67 = bitcast %union._ZTS2un.un* %ref.tmp3 to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %67) #4 + %68 = ptrtoint %union._ZTS2un.un* %u2 to i64 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT64]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i64 @llvm.annotation.i64(i64 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR12]] + %69 = call i64 @llvm.annotation.i64(i64 %68, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 117) + %70 = inttoptr i64 %69 to %union._ZTS2un.un* + %71 = addrspacecast %union._ZTS2un.un* %70 to %union._ZTS2un.un addrspace(4)* + store %union._ZTS2un.un addrspace(4)* %71, %union._ZTS2un.un addrspace(4)** %u3, align 8, !tbaa !5 + %72 = bitcast %class._ZTS1A.A* %ca to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %72) #4 + %73 = addrspacecast %class._ZTS1A.A* %ca to %class._ZTS1A.A addrspace(4)* + call spir_func void @_ZN1AC1Ei(%class._ZTS1A.A addrspace(4)* %73, i32 213) + %74 = bitcast %class._ZTS1A.A* %cb to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %74) #4 + %75 = bitcast %class._ZTS1A.A* %agg-temp5 to i8* + %76 = bitcast %class._ZTS1A.A* %ca to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %75, i8* align 4 %76, i64 4, i1 false), !tbaa.struct !16 + %77 = bitcast %class._ZTS1A.A* %agg-temp5 to i8* + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_PTR]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i8* @llvm.ptr.annotation.p0i8(i8* %[[CAST5:[a-z0-9]+]], i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR13]] + ; CHECK-LLVM-DAG: %[[CAST5]] = bitcast %class._ZTS1A.A* %agg-temp5 to i8* + %78 = call i8* @llvm.ptr.annotation.p0i8(i8* %77, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 125) + %79 = bitcast i8* %78 to %class._ZTS1A.A* + %80 = bitcast %class._ZTS1A.A* %cb to i8* + %81 = bitcast %class._ZTS1A.A* %79 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %80, i8* align 4 %81, i64 8, i1 false) + %82 = bitcast i32 addrspace(4)** %ap to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %82) #4 + %83 = addrspacecast i32* %a to i32 addrspace(4)* + store i32 addrspace(4)* %83, i32 addrspace(4)** %ap, align 8, !tbaa !5 + %84 = bitcast i32 addrspace(4)** %bp to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %84) #4 + %85 = load i32 addrspace(4)*, i32 addrspace(4)** %ap, align 8, !tbaa !5 + %86 = ptrtoint i32 addrspace(4)* %85 to i64 + ; CHECK-SPIRV: FPGARegINTEL [[TYPE_INT64]] {{[0-9]+}} {{[0-9]+}}{{ *$}} + ; CHECK-LLVM-DAG: %{{[0-9]+}} = call i64 @llvm.annotation.i64(i64 {{[%a-z0-9]+}}, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @[[STR14]] + %87 = call i64 @llvm.annotation.i64(i64 %86, i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.1, i32 0, i32 0), i32 137) + %88 = inttoptr i64 %87 to i32 addrspace(4)* + store i32 addrspace(4)* %88, i32 addrspace(4)** %bp, align 8, !tbaa !5 + %89 = bitcast i32 addrspace(4)** %bp to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %89) #4 + %90 = bitcast i32 addrspace(4)** %ap to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %90) #4 + %91 = bitcast %class._ZTS1A.A* %cb to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %91) #4 + %92 = bitcast %class._ZTS1A.A* %ca to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %92) #4 + %93 = bitcast %union._ZTS2un.un addrspace(4)** %u3 to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %93) #4 + %94 = bitcast %union._ZTS2un.un* %u2 to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %94) #4 + %95 = bitcast %union._ZTS2un.un* %u1 to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %95) #4 + %96 = bitcast %struct._ZTS2st.st addrspace(4)** %iiii to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %96) #4 + %97 = bitcast %struct._ZTS2st.st* %iii to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %97) #4 + %98 = bitcast %struct._ZTS2st.st* %ii to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %98) #4 + %99 = bitcast %struct._ZTS2st.st* %i2 to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %99) #4 + %100 = bitcast %struct._ZTS2st.st* %i to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %100) #4 + %101 = bitcast i32* %f to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %101) #4 + %102 = bitcast i32* %e to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %102) #4 + %103 = bitcast i32* %d to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %103) #4 + %104 = bitcast i32* %c to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %104) #4 + %105 = bitcast i32* %myB to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %105) #4 + %106 = bitcast i32* %b to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %106) #4 + %107 = bitcast i32* %myA to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %107) #4 + %108 = bitcast i32* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %108) #4 + ret void +} + +; Function Attrs: nounwind +declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #4 + +; Function Attrs: argmemonly nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1 immarg) #1 + +; Function Attrs: nounwind +declare i8* @llvm.ptr.annotation.p0i8(i8*, i8*, i8*, i32) #4 + +; Function Attrs: nounwind +declare i64 @llvm.annotation.i64(i64, i8*, i8*, i32) #4 + +; Function Attrs: nounwind +define linkonce_odr spir_func void @_ZN1AC1Ei(%class._ZTS1A.A addrspace(4)* %this, i32 %a) unnamed_addr #3 comdat align 2 { +entry: + %this.addr = alloca %class._ZTS1A.A addrspace(4)*, align 8 + %a.addr = alloca i32, align 4 + store %class._ZTS1A.A addrspace(4)* %this, %class._ZTS1A.A addrspace(4)** %this.addr, align 8, !tbaa !5 + store i32 %a, i32* %a.addr, align 4, !tbaa !9 + %this1 = load %class._ZTS1A.A addrspace(4)*, %class._ZTS1A.A addrspace(4)** %this.addr, align 8 + %0 = load i32, i32* %a.addr, align 4, !tbaa !9 + call spir_func void @_ZN1AC2Ei(%class._ZTS1A.A addrspace(4)* %this1, i32 %0) + ret void +} + +; Function Attrs: nounwind +define linkonce_odr spir_func void @_ZN1AC2Ei(%class._ZTS1A.A addrspace(4)* %this, i32 %a) unnamed_addr #3 comdat align 2 { +entry: + %this.addr = alloca %class._ZTS1A.A addrspace(4)*, align 8 + %a.addr = alloca i32, align 4 + store %class._ZTS1A.A addrspace(4)* %this, %class._ZTS1A.A addrspace(4)** %this.addr, align 8, !tbaa !5 + store i32 %a, i32* %a.addr, align 4, !tbaa !9 + %this1 = load %class._ZTS1A.A addrspace(4)*, %class._ZTS1A.A addrspace(4)** %this.addr, align 8 + %0 = load i32, i32* %a.addr, align 4, !tbaa !9 + %m_val = getelementptr inbounds %class._ZTS1A.A, %class._ZTS1A.A addrspace(4)* %this1, i32 0, i32 0 + store i32 %0, i32 addrspace(4)* %m_val, align 4, !tbaa !17 + ret void +} + +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nounwind } +attributes #2 = { inlinehint nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #4 = { nounwind } + +!llvm.module.flags = !{!0} +!opencl.spir.version = !{!1} +!spirv.Source = !{!2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, i32 2} +!2 = !{i32 4, i32 100000} +!3 = !{!"clang version 9.0.0"} +!4 = !{} +!5 = !{!6, !6, i64 0} +!6 = !{!"any pointer", !7, i64 0} +!7 = !{!"omnipotent char", !8, i64 0} +!8 = !{!"Simple C++ TBAA"} +!9 = !{!10, !10, i64 0} +!10 = !{!"int", !7, i64 0} +!11 = !{i64 0, i64 4, !9, i64 4, i64 4, !12} +!12 = !{!13, !13, i64 0} +!13 = !{!"float", !7, i64 0} +!14 = !{i64 0, i64 4, !9, i64 0, i64 4, !15} +!15 = !{!7, !7, i64 0} +!16 = !{i64 0, i64 4, !9} +!17 = !{!18, !10, i64 0} +!18 = !{!"_ZTS1A", !10, i64 0} diff --git a/llvm-spirv/test/OpSwitch32.ll b/llvm-spirv/test/OpSwitch32.ll index 33a88f2b33ec8..046b1e297eb28 100644 --- a/llvm-spirv/test/OpSwitch32.ll +++ b/llvm-spirv/test/OpSwitch32.ll @@ -30,7 +30,7 @@ target triple = "spir64-unknown-unknown" ;CHECK-LLVM: test_32 ;CHECK-LLVM: entry -;CHECK-LLVM: switch i32 %conv, label %sw.epilog +;CHECK-LLVM: switch i32 %0, label %sw.epilog ;CHECK-LLVM: i32 0, label %sw.bb ;CHECK-LLVM: i32 1, label %sw.bb1 diff --git a/llvm-spirv/test/OpSwitch64.ll b/llvm-spirv/test/OpSwitch64.ll index cc032226c9008..430d576350e93 100644 --- a/llvm-spirv/test/OpSwitch64.ll +++ b/llvm-spirv/test/OpSwitch64.ll @@ -33,7 +33,7 @@ target triple = "spir64-unknown-unknown" ;CHECK-LLVM: test_64 ;CHECK-LLVM: entry -;CHECK-LLVM: switch i64 %call, label %sw.epilog [ +;CHECK-LLVM: switch i64 %0, label %sw.epilog [ ;CHECK-LLVM: i64 0, label %sw.bb ;CHECK-LLVM: i64 1, label %sw.bb1 ;CHECK-LLVM: i64 21474836481, label %sw.bb3 diff --git a/llvm-spirv/test/image-unoptimized.ll b/llvm-spirv/test/image-unoptimized.ll deleted file mode 100644 index 77ebf5e199cc7..0000000000000 --- a/llvm-spirv/test/image-unoptimized.ll +++ /dev/null @@ -1,77 +0,0 @@ -; RUN: llvm-as %s -o %t.bc -; RUN: llvm-spirv %t.bc -spirv-text -o %t -; RUN: FileCheck < %t %s -; RUN: llvm-spirv %t.bc -o %t.spv -; RUN: spirv-val %t.spv -target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" -target triple = "spir-unknown-unknown" - -%opencl.image2d_t = type opaque - -; Function Attrs: nounwind -; CHECK: {{[0-9]*}} Store -; CHECK-NEXT: 1 Return -define spir_kernel void @test_fn(%opencl.image2d_t addrspace(1)* %srcimg, i32 %sampler, <4 x float> addrspace(1)* %results) #0 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 { -entry: - %srcimg.addr = alloca %opencl.image2d_t addrspace(1)*, align 4 - %sampler.addr = alloca i32, align 4 - %results.addr = alloca <4 x float> addrspace(1)*, align 4 - %tid_x = alloca i32, align 4 - %tid_y = alloca i32, align 4 - %.compoundliteral = alloca <2 x i32>, align 8 - store %opencl.image2d_t addrspace(1)* %srcimg, %opencl.image2d_t addrspace(1)** %srcimg.addr, align 4 - store i32 %sampler, i32* %sampler.addr, align 4 - store <4 x float> addrspace(1)* %results, <4 x float> addrspace(1)** %results.addr, align 4 - %call = call spir_func i32 @_Z13get_global_idj(i32 0) #2 - store i32 %call, i32* %tid_x, align 4 - %call1 = call spir_func i32 @_Z13get_global_idj(i32 1) #2 - store i32 %call1, i32* %tid_y, align 4 - %0 = load %opencl.image2d_t addrspace(1)*, %opencl.image2d_t addrspace(1)** %srcimg.addr, align 4 - %1 = load i32, i32* %sampler.addr, align 4 - %2 = load i32, i32* %tid_x, align 4 - %vecinit = insertelement <2 x i32> undef, i32 %2, i32 0 - %3 = load i32, i32* %tid_y, align 4 - %vecinit2 = insertelement <2 x i32> %vecinit, i32 %3, i32 1 - store <2 x i32> %vecinit2, <2 x i32>* %.compoundliteral - %4 = load <2 x i32>, <2 x i32>* %.compoundliteral - %call3 = call spir_func <4 x float> @_Z11read_imagef11ocl_image2d11ocl_samplerDv2_i(%opencl.image2d_t addrspace(1)* %0, i32 %1, <2 x i32> %4) #2 - %5 = load i32, i32* %tid_y, align 4 - %6 = load %opencl.image2d_t addrspace(1)*, %opencl.image2d_t addrspace(1)** %srcimg.addr, align 4 - %call4 = call spir_func i32 @_Z15get_image_width11ocl_image2d(%opencl.image2d_t addrspace(1)* %6) #2 - %mul = mul nsw i32 %5, %call4 - %7 = load i32, i32* %tid_x, align 4 - %add = add nsw i32 %mul, %7 - %8 = load <4 x float> addrspace(1)*, <4 x float> addrspace(1)** %results.addr, align 4 - %arrayidx = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %8, i32 %add - store <4 x float> %call3, <4 x float> addrspace(1)* %arrayidx, align 16 - ret void -} - -; Function Attrs: nounwind readnone -declare spir_func i32 @_Z13get_global_idj(i32) #1 - -; Function Attrs: nounwind readnone -declare spir_func <4 x float> @_Z11read_imagef11ocl_image2d11ocl_samplerDv2_i(%opencl.image2d_t addrspace(1)*, i32, <2 x i32>) #1 - -; Function Attrs: nounwind readnone -declare spir_func i32 @_Z15get_image_width11ocl_image2d(%opencl.image2d_t addrspace(1)*) #1 - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind readnone } - -!opencl.enable.FP_CONTRACT = !{} -!opencl.spir.version = !{!6} -!opencl.ocl.version = !{!6} -!opencl.used.extensions = !{!7} -!opencl.used.optional.core.features = !{!8} -!opencl.compiler.options = !{!7} - -!1 = !{i32 1, i32 0, i32 1} -!2 = !{!"read_only", !"none", !"none"} -!3 = !{!"image2d_t", !"sampler_t", !"float4*"} -!4 = !{!"image2d_t", !"sampler_t", !"float4*"} -!5 = !{!"", !"", !""} -!6 = !{i32 1, i32 2} -!7 = !{} -!8 = !{!"cl_images"}