From a796764a6f3630f0e0aa15820f61298adaae4656 Mon Sep 17 00:00:00 2001 From: Sergey Belyashov Date: Wed, 27 Nov 2019 16:41:54 +0300 Subject: [PATCH 1/2] [Z80] Add feature to enable SLI/SLL instruction --- llvm/lib/Target/Z80/Z80.td | 4 +++- llvm/lib/Target/Z80/Z80InstrInfo.td | 12 +++++++++--- llvm/lib/Target/Z80/Z80Subtarget.cpp | 1 + llvm/lib/Target/Z80/Z80Subtarget.h | 4 ++++ 4 files changed, 17 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Z80/Z80.td b/llvm/lib/Target/Z80/Z80.td index 8e603e997c816..49fc3da2fa1d7 100644 --- a/llvm/lib/Target/Z80/Z80.td +++ b/llvm/lib/Target/Z80/Z80.td @@ -28,6 +28,8 @@ def FeatureEZ80 : SubtargetFeature<"ez80", "HasEZ80Ops", "true", "Support ez80 instructions">; def FeatureIdxHalf : SubtargetFeature<"idxhalf", "HasIdxHalfRegs", "true", "Support index half registers">; +def FeatureSli : SubtargetFeature<"sli", "HasSliOps", "true", + "Support SLI instruction">; //===----------------------------------------------------------------------===// // Z80 Subtarget state @@ -46,7 +48,7 @@ let CompleteModel = 0 in def GenericModel : SchedMachineModel; class Proc Features> : ProcessorModel; def : Proc<"generic", []>; -def : Proc<"z80", [FeatureUndoc, FeatureIdxHalf]>; +def : Proc<"z80", [FeatureUndoc, FeatureIdxHalf, FeatureSli]>; def : Proc<"z180", [FeatureZ180]>; def : Proc<"ez80", [FeatureZ180, FeatureEZ80, FeatureIdxHalf]>; diff --git a/llvm/lib/Target/Z80/Z80InstrInfo.td b/llvm/lib/Target/Z80/Z80InstrInfo.td index 7ecc045471061..a4c8fa0df5e7f 100644 --- a/llvm/lib/Target/Z80/Z80InstrInfo.td +++ b/llvm/lib/Target/Z80/Z80InstrInfo.td @@ -82,6 +82,7 @@ def Z80rl_flag : SDNode<"Z80ISD::RL", SDTUnOpRFF>; def Z80rr_flag : SDNode<"Z80ISD::RR", SDTUnOpRFF>; def Z80sla_flag : SDNode<"Z80ISD::SLA", SDTUnOpRF>; def Z80sra_flag : SDNode<"Z80ISD::SRA", SDTUnOpRF>; +def Z80sli_flag : SDNode<"Z80ISD::SLI", SDTUnOpRF>; def Z80srl_flag : SDNode<"Z80ISD::SRL", SDTUnOpRF>; def Z80bit_flag : SDNode<"Z80ISD::BIT", SDTBitOpF>; def Z80res_flag : SDNode<"Z80ISD::RES", SDTBitOpR>; @@ -132,8 +133,9 @@ def HaveZ180Ops : Predicate<"Subtarget->hasZ180Ops()">, def HaveEZ80Ops : Predicate<"Subtarget->hasEZ80Ops()">, AssemblerPredicate<(all_of FeatureEZ80), "eZ80 ops">; def HaveIdxHalf : Predicate<"Subtarget->hasIndexHalfRegs()">, - AssemblerPredicate<(all_of FeatureIdxHalf), - "index half regs">; + AssemblerPredicate<"FeatureIdxHalf", "index half regs">; +def HaveSliOps : Predicate<"Subtarget->hasSliOps()">, + AssemblerPredicate<"FeatureSli", "sli ops">; //===----------------------------------------------------------------------===// // Z80 Instruction Format Definitions. @@ -805,6 +807,8 @@ defm RL : UnOp8RFF ; defm RR : UnOp8RFF ; defm SLA : UnOp8RF ; defm SRA : UnOp8RF ; +defm SLI : UnOp8RF , + Requires<[HaveSliOps]>; defm SRL : UnOp8RF ; defm BIT : BitOp8F < 1, "bit">; defm RES : BitOp8R < 2, "res">; @@ -820,7 +824,9 @@ defm XOR : BinOp8RF ; defm OR : BinOp8RF ; defm CP : BinOp8F ; defm TST : BinOp8F , - Requires<[HaveEZ80Ops]>; + Requires<[HaveZ180Ops]>; + +def : MnemonicAlias<"sll", "sli">, Requires<[HaveSliOps]>; def : Pat<(fshl G8:$reg, G8:$reg, (i8 1)), (RLC8r G8:$reg)>; def : Pat<(fshl G8:$reg, G8:$reg, (i8 7)), (RRC8r G8:$reg)>; diff --git a/llvm/lib/Target/Z80/Z80Subtarget.cpp b/llvm/lib/Target/Z80/Z80Subtarget.cpp index 5490d37ba567d..befc7c3aa0c92 100644 --- a/llvm/lib/Target/Z80/Z80Subtarget.cpp +++ b/llvm/lib/Target/Z80/Z80Subtarget.cpp @@ -35,6 +35,7 @@ Z80Subtarget &Z80Subtarget::initializeSubtargetDependencies(StringRef CPU, CPU = TargetTriple.getArchName(); ParseSubtargetFeatures(CPU, TuneCPU, FS); HasIdxHalfRegs = HasUndocOps || HasEZ80Ops; + HasSliOps = HasUndocOps; return *this; } diff --git a/llvm/lib/Target/Z80/Z80Subtarget.h b/llvm/lib/Target/Z80/Z80Subtarget.h index 7f9c419f3774c..5bf62d497003a 100644 --- a/llvm/lib/Target/Z80/Z80Subtarget.h +++ b/llvm/lib/Target/Z80/Z80Subtarget.h @@ -52,6 +52,9 @@ class Z80Subtarget final : public Z80GenSubtargetInfo { /// True if target has index half registers (HasUndocOps || HasEZ80Ops). bool HasIdxHalfRegs = false; + /// True if target has SLI (also known SLL) instructions (HasUndocOps) + bool HasSliOps = false; + // Ordering here is important. Z80InstrInfo initializes Z80RegisterInfo which // Z80TargetLowering needs. Z80InstrInfo InstrInfo; @@ -118,6 +121,7 @@ class Z80Subtarget final : public Z80GenSubtargetInfo { bool hasZ180Ops() const { return HasZ180Ops; } bool hasEZ80Ops() const { return HasEZ80Ops; } bool hasIndexHalfRegs() const { return HasIdxHalfRegs; } + bool hasSliOps() const { return HasSliOps; } bool has24BitEZ80Ops() const { return is24Bit() && hasEZ80Ops(); } bool has16BitEZ80Ops() const { return is16Bit() && hasEZ80Ops(); } }; From 32779c33877c35e2ab1eb312f29742e2364485a5 Mon Sep 17 00:00:00 2001 From: Jacob Young Date: Mon, 31 Jan 2022 05:15:37 -0500 Subject: [PATCH 2/2] Fix #2. --- llvm/lib/Target/Z80/Z80.td | 2 +- llvm/lib/Target/Z80/Z80InstrInfo.td | 18 ++++++++++-------- llvm/lib/Target/Z80/Z80Subtarget.cpp | 2 +- llvm/lib/Target/Z80/Z80Subtarget.h | 6 +++--- 4 files changed, 15 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/Z80/Z80.td b/llvm/lib/Target/Z80/Z80.td index 49fc3da2fa1d7..cf77c9798bee6 100644 --- a/llvm/lib/Target/Z80/Z80.td +++ b/llvm/lib/Target/Z80/Z80.td @@ -28,7 +28,7 @@ def FeatureEZ80 : SubtargetFeature<"ez80", "HasEZ80Ops", "true", "Support ez80 instructions">; def FeatureIdxHalf : SubtargetFeature<"idxhalf", "HasIdxHalfRegs", "true", "Support index half registers">; -def FeatureSli : SubtargetFeature<"sli", "HasSliOps", "true", +def FeatureSli : SubtargetFeature<"sli", "HasSliOp", "true", "Support SLI instruction">; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Z80/Z80InstrInfo.td b/llvm/lib/Target/Z80/Z80InstrInfo.td index a4c8fa0df5e7f..d54a371899139 100644 --- a/llvm/lib/Target/Z80/Z80InstrInfo.td +++ b/llvm/lib/Target/Z80/Z80InstrInfo.td @@ -133,9 +133,10 @@ def HaveZ180Ops : Predicate<"Subtarget->hasZ180Ops()">, def HaveEZ80Ops : Predicate<"Subtarget->hasEZ80Ops()">, AssemblerPredicate<(all_of FeatureEZ80), "eZ80 ops">; def HaveIdxHalf : Predicate<"Subtarget->hasIndexHalfRegs()">, - AssemblerPredicate<"FeatureIdxHalf", "index half regs">; -def HaveSliOps : Predicate<"Subtarget->hasSliOps()">, - AssemblerPredicate<"FeatureSli", "sli ops">; + AssemblerPredicate<(all_of FeatureIdxHalf), + "index half regs">; +def HaveSliOp : Predicate<"Subtarget->hasSliOp()">, + AssemblerPredicate<(all_of FeatureSli), "SLI op">; //===----------------------------------------------------------------------===// // Z80 Instruction Format Definitions. @@ -807,8 +808,7 @@ defm RL : UnOp8RFF ; defm RR : UnOp8RFF ; defm SLA : UnOp8RF ; defm SRA : UnOp8RF ; -defm SLI : UnOp8RF , - Requires<[HaveSliOps]>; +defm SLI : UnOp8RF , Requires<[HaveSliOp]>; defm SRL : UnOp8RF ; defm BIT : BitOp8F < 1, "bit">; defm RES : BitOp8R < 2, "res">; @@ -823,15 +823,17 @@ defm AND : BinOp8RF ; defm XOR : BinOp8RF ; defm OR : BinOp8RF ; defm CP : BinOp8F ; -defm TST : BinOp8F , - Requires<[HaveZ180Ops]>; +defm TST : BinOp8F , Requires<[HaveZ180Ops]>; -def : MnemonicAlias<"sll", "sli">, Requires<[HaveSliOps]>; +def : MnemonicAlias<"sll", "sli">, Requires<[HaveSliOp]>; +def : MnemonicAlias<"sl1", "sli">, Requires<[HaveSliOp]>; def : Pat<(fshl G8:$reg, G8:$reg, (i8 1)), (RLC8r G8:$reg)>; def : Pat<(fshl G8:$reg, G8:$reg, (i8 7)), (RRC8r G8:$reg)>; def : Pat<(shl G8:$reg, (i8 1)), (SLA8r G8:$reg)>; def : Pat<(sra G8:$reg, (i8 1)), (SRA8r G8:$reg)>; +def : Pat<(or (shl G8:$reg, (i8 1)), (i8 1)), (SLI8r G8:$reg)>, + Requires<[HaveSliOp]>; def : Pat<(srl G8:$reg, (i8 1)), (SRL8r G8:$reg)>; def : Pat<(add R8:$reg, (i8 1)), (INC8r R8:$reg)>; def : Pat<(add R8:$reg, (i8 -1)), (DEC8r R8:$reg)>; diff --git a/llvm/lib/Target/Z80/Z80Subtarget.cpp b/llvm/lib/Target/Z80/Z80Subtarget.cpp index befc7c3aa0c92..783f30d4a356c 100644 --- a/llvm/lib/Target/Z80/Z80Subtarget.cpp +++ b/llvm/lib/Target/Z80/Z80Subtarget.cpp @@ -35,7 +35,7 @@ Z80Subtarget &Z80Subtarget::initializeSubtargetDependencies(StringRef CPU, CPU = TargetTriple.getArchName(); ParseSubtargetFeatures(CPU, TuneCPU, FS); HasIdxHalfRegs = HasUndocOps || HasEZ80Ops; - HasSliOps = HasUndocOps; + HasSliOp = HasUndocOps; return *this; } diff --git a/llvm/lib/Target/Z80/Z80Subtarget.h b/llvm/lib/Target/Z80/Z80Subtarget.h index 5bf62d497003a..0b2a282fcb427 100644 --- a/llvm/lib/Target/Z80/Z80Subtarget.h +++ b/llvm/lib/Target/Z80/Z80Subtarget.h @@ -52,8 +52,8 @@ class Z80Subtarget final : public Z80GenSubtargetInfo { /// True if target has index half registers (HasUndocOps || HasEZ80Ops). bool HasIdxHalfRegs = false; - /// True if target has SLI (also known SLL) instructions (HasUndocOps) - bool HasSliOps = false; + /// True if target has SLI (also known SLL and SL1) instruction (HasUndocOps) + bool HasSliOp = false; // Ordering here is important. Z80InstrInfo initializes Z80RegisterInfo which // Z80TargetLowering needs. @@ -121,7 +121,7 @@ class Z80Subtarget final : public Z80GenSubtargetInfo { bool hasZ180Ops() const { return HasZ180Ops; } bool hasEZ80Ops() const { return HasEZ80Ops; } bool hasIndexHalfRegs() const { return HasIdxHalfRegs; } - bool hasSliOps() const { return HasSliOps; } + bool hasSliOp() const { return HasSliOp; } bool has24BitEZ80Ops() const { return is24Bit() && hasEZ80Ops(); } bool has16BitEZ80Ops() const { return is16Bit() && hasEZ80Ops(); } };