can't boot up the PS on ZCU102 Rev1.1 board #5
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bwtang
changed the title
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@bwtang
What error did you get? Good luck. |
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Thanks for your reply. Like your advise, I fixed my config file and system-user.dsti (slightly different from the original file) and then rebuild PS kernel with the newest BSP (2019.2) and petalinux (2019.2). But it also reported some errors like that: According the log, the root cause maybe my system-user.dsti file. Its content is: This is my first time to write .dst. I didn't understand its meaning, just copyed from original file and merged it into the default file. I know the riscv-fesvr is related to the dst file. So I want to know its meaning. Do you have some advise? |
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@bwtang Which |
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Were you able to successfully boot on rev1.1? |
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I have Petalinux 2019 installed on my system, and I am using the 2019 BSP file which is placed in my soft_config folder. when I issue Is there something that I need to refactor in order to get BOOT.bin and image.ub to build for rev1.1? |
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@FTGStudio Yes, my board is also a rev1.1 and it works perfectly. However, the scripts are made and tested for 2017.1 Vivado and petalinux. Hence, you need to do some necessary changes in the scripts for newer Vivado and petalinux.
This error seems to say that the hardware definition file Cheers, |
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I was able to export an updated version of the hardware description file via 2019 vivado. I also built the project with 2019 Petalinux. When I generate my BOOT.bin and image.ub file and load it onto an SD card I see the following serial output from the zcu102 rev1.1 board It seems to be hanging out the FSBL. Any advice from this point on? |
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@FTGStudio
The official Xilinx answer sheet for this issue is in here. Cheers |
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I'm attempting to build the fesvr-zynq right now, and it cannot seem to link "fesvr". I am following the instructions from the README. Any advice? /opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/8.2.0/../../../../aarch64-linux-gnu/bin/ld: cannot find -lfesvr |
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Hi @bwtang , have you resolved this problem, I met the same problem as you met. |
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I substitute the fsbl.elf and pmufw.elf with the newer one and generate the BOOT.bin and image.ub, but when i boot with sd card, it will halt on starting kernel and cannot enter into the file system. |
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Hi @FTGStudio , have you boot the arm linux successfully ? |
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@FTGStudio |
This is because when you compile the fesvr you didn't use aarch64 gcc to compile, you can check your fesvr-zynq Makefile to make sure the gcc host is aarch64 while not x86-64 gcc. |
Correct. I was able to build a BOOT.BIN file with the latest zynq_fsbl.elf as well as the pmu.elf and got to linux on the ARM core. @li3tuo4 I was able to build fesvr-lib correctly. The tutorial is what I have been working off of. I am at part 3.2 where I have to build the fesvr and I get the error mentioned above. I see the @botaichang I have the Xilinx SDK added to my path however I receive an error: Any advice? |
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I have attempted the following: I wonder why I keep receving |
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After replacing the |
A simple way is go to Makefile under riscv-fesvr directory and change CC to xilinx SDK aarch64-linux-gnu-gcc and CXX to xilinx SDK aarch64-linux-gnu-g++ and then make libfesvr. |
Which version of petalinux tool do you use? 2019.2 or 2018.3 ? when i create petalinux project i can only pass the compilation through 2017.1 while other versions make some errors. |
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@FTGStudio @li3tuo4 |
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I was able to upgrade the project by opening up in Vivado and selecting "Report Status". When using the make tools I did have to update entries in the Makefile:
Let me know if this helps |
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@botaichang Above all, your @FTGStudio That compiler error seems to be that the |
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@li3tuo4 maybe the petalinux sdk version should be same as vivado version so that it can get the hw description correctly. So I use petalinux 2017.1 to generate the *fsbl and pmu.elf and then substitute this file with files of 2019.2, but this way is not work. So I don't know what should do next. Can you give some advice? |
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I have the design working on rev1.1 now. I can boot up linux on the RISCV core. What version of rocket-chip is this repository using? |
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@FTGStudio @botaichang |
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I am working through each step again to verify, however, at a high level I was able to get it up and running by performing the following actions:
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thanks @li3tuo4 . I try to build with 2018.3 tools. But when i build with 2018.3 petalinux with running the petalinux_bd.sh , i got these errors. Do you have some ideas about this error. It sames as this error: https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2018-1-build-errors-missing-rootfs-files/m-p/1029604#M37135, but it seems haven't resolved. |
I made some changes for soft_config/config file , change some version from 2017.1 to 2018.3, and after compile, now gives this error: there is no fsbl directory so it cannot compile by make. |
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Hi @li3tuo4 , after I made patch for fsbl with 2018.3, I can now start the u-boot but I still cannot mount root-fs successfully. The error information as follows: could you give me a help for this problem? Thanks very much. |
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@botaichang |
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Hi @li3tuo4, thanks for your help, I can boot arm linux after make some patch according to Now I have some questions here:
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@botaichang The current config of physical memory is 256 MB by default for rocket chip. Your riscv-linux probably is not configured to make use of all the memory available? You can first check the riscv-linux config. If you do require physical memory larger than 256 MB, you need to modify the FPGA config in vivado and riscv-linux config. |
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Thank you @FTGStudio for the detailed steps. I am trying to replicate the same steps on my board (Rev 1.1 with Micron MTA4ATF51264HZ-2G6E1). I think maybe there might be some additional steps required in the device tree and/or petalinux configuration apart from what you have mentioned above. This is my petalinux config - https://pastebin.com/WBTTtbPW I would be really thankful if you could guide me on what steps might be missing in our attempt. |
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Hello, aarch64-linux-gnu-g++ -O2 -std=c++11 -Wall -L/home/thaising/rc-fpga-zcu32/common/build -lfesvr -Wl,-rpath,/usr/local/lib -I /home/thaising/rc-fpga-zcu32/common/csrc -I /home/thaising/rc-fpga-zcu32/testchipip/csrc -I /home/thaising/rc-fpga-zcu32/rocket-chip/riscv-tools/riscv-fesvr/ -Wl,-rpath,/usr/local/lib -o /home/thaising/rc-fpga-zcu32/common/build/fesvr-zynq /home/thaising/rc-fpga-zcu32/common/csrc/fesvr_zynq.cc /home/thaising/rc-fpga-zcu32/common/csrc/zynq_driver.cc /home/thaising/rc-fpga-zcu32/testchipip/csrc/blkdev.cc |
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@Thaising-Taing It seems that you did not build and install riscv-fesvr in riscv-tools properly. |
I re-installed riscv-fesvr many times and still facing the same issues when I tried to "make fesvr-zynq". I thought because of this Frontend Issues; likewise, I cannot call the RISCV when I booted them successfully on FPGA. When I typed "LD_LIBRARY_PATH=./ ./fesvr-zynq bbl" as your document told, it is stucking without showing any result, but I am sure that my Spike, pk, bbl are built successfully. The fesvr-zynq that you saw in this picture, I copied from some website that they used to build them and I import directly to my linux. Could you help give some suggestion for both issues that I am facing right now?
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If you have not got fesvr-zynq built right due to this linking error, your fesvr-zynq execution on FPGA would not work. With regard to your error, try to remove content in "common/build" and rebuild from riscv-fesvr. Does executing this fesvr-zynq without arguments show anything (should show help content) on FPGA? If it shows, the error is in pk. |
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The error seems to tell that libfesvr.so is not not compatible. I guess you compiled that .so file for a wrong target architecture. It should target aarch64. You can try again with the FPGA after you have got the right fesvr-zynq. |
Where should I check to make them target to the aarch64? I already added the aarch64 machine to the config.sub file inside the riscv-fesvr directory. Could you help provide me more information to fix this frontend server? I got stuck in here for nearly 3months. |
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You can check using |
This the result that I used the “file libfesvr.so” as what you recommended. And another figure is what I added aarch64 to config.sub file in the riscv-fesvr folder. Could you help check and what is wrong with this that you said it is not target aarch64? |
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Your snapshot shows it's targeting x86, not aarch64. Try to rebuild libfesvr and read the log. |
In your Project, where should I change to make them target the aarch64? I didn't see the instructions that help guide to map them to target aarch64 expect the config.sub inside the riscv-fesvr folder. |
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If everything goes right, it should be aarch64 directly. Something is not correct in build process. |
I already made them target to aarch64 now, but the error message is getting to my First Comment again. The GCC cannot compile the code to build fesvr-zynq. It is so strange. Could you help refer to the images below and gave more specific solution to fix this issues? I fixed and built everything again for riscv-tools. |
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Do you have the full error log? It's either libfesvr.so in common/build not recognized by compiler or libfesvr.so not having those objects. |
This is my log file that I obtained from the build "make fesvr-zynq" and another is the full error message. Could you help check again the screenshot and config.log file that I attached and give me more direction to overcome this issues?
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These missing references are defined in riscv-fesvr (for example |
This is what i obtained from the objdump file. There has alot of things. How could I check them one by one? if it possible can I obtained the file that already built for the riscv-tools or riscv-fesvr from you directly? I spent too long time with Project and now my Professor wished to stop me from this Project if I still have no result to demo. Could you help give more details on this fesvr-zynq? |
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Sorry to hear that your project is not progressing for so long. Usually |
I tried again with your Fesvr-Zynq. It is still stucking without calling the RISCV Core to wake up. It is so strange. My Board is ZCU102. Could you give me the idea why is it stucking? |
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If |
When I build the riscv-tools, I found their has no error, but we have a few warnings. After that, I run make bitstream and create the vivado project. There has no issues and it can working properly when I generated bitstream and program to FPGA. My Project is related to RISCV Soft IP Core, and I saw your Project is gorgeous as it provided the step to call the RISCV Core which run on software stack of ARM. it is so interesting and it is my first time that I run hardware communicate with software, but we encountered so many bugs on your Project. If it is possible, could you help update the whole Project and Guideline. I have a question, the ROCKET CHIP is running in the PL Side of FPGA, right? I saw in your project has two part SYSTEM (maybe ARM Processor PS Part) and another TOP (maybe Rocket Chip). Furthermore, I do not have another Options yet. |
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This repository was used by quite a few people at my old research group and we found it generally works fine. Most people encounter problem due to different Vivado versions or board versions, and these problems are out of the current scope of this project. I am fully employed for other projects at the moment, hence I cannot spend much time in enriching this repo. I feel there is something subtle in your dev environment, which causes this problem. Can you find any experienced ZYNQ-FPGA person to take a look at your problem directly at your dev machine? To answer your questions. Yes, rocket chip is implemented in LUTs etc on PL side and ARM things are hard IPs on PS side. There is a top module instantiates and connects ARM system and PL design, and in this case, PL design is rocket chip. If ZYNQ development is not comfortable to you, you can consider using pure PL FPGA implementations of rocket chip, such as lowrisc, or, chipyard, which includes an on-cloud FPGA-based simulation solution called firesim. If you have further questions or improvement ideas on this repo, I am happy to provide suggestions. Cheers. |
Thank you for your detailed tutorial. It helps me a lot to follow your work. Until now, I have finished the long building process. I successfully built the BOOT.bin & image.ub and load them into my SDcard. But when I powered on my board, it just printed two sentences "Xilinx Zynq MP First Stage Boot Loader \n Release 2017.1 Aug 16 2018 - 17:25:43\n" and then blocked. I used the same version Vivado, SDK, Petalinux and BSP, so I'm confused why it happened.
Then, I found a discussion about the same problem on Xilinx forum. I guess the root cause is the version of my board. My version is "ZCU102 Revision 1.1". It may be newer than your board. The older FSBL or pmu.elf may not work on the new board. So I used the pre-built BOOT.bin & image.ub from Xilinx wiki. This time, it started the PS linux system successfully. So I tried rebuilding with the newest BSP and Petalinux, but it reported some errors during petalinux-build process (I have correct the project config file). So I gave up this solution and tried to repackage the BOOT.bin replacing the original fsbl.elf and pmu.elf with the newest version which downloaded from the above link. This time, the u-boot executed successfully but the kernel failed. Now I have no idead about how to fix it?
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