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[AMDGPU] Add an asm directive to track code_object_version (#76267)
Named '.amdhsa_code_object_version'. This directive sets the e_ident[ABIVERSION] in the ELF header, and should be used as the assumed COV for the rest of the asm file. This commit also weakens the --amdhsa-code-object-version CL flag. Previously, the CL flag took precedence over the IR flag. Now the IR flag/asm directive take precedence over the CL flag. This is implemented by merging a few COV-checking functions in AMDGPUBaseInfo.h.
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+217
-407
lines changed

‎llvm/docs/AMDGPUUsage.rst

+8
Original file line numberDiff line numberDiff line change
@@ -15428,6 +15428,14 @@ command-line options such as ``-triple``, ``-mcpu``, and
1542815428
The target ID syntax used for code object V2 to V3 for this directive differs
1542915429
from that used elsewhere. See :ref:`amdgpu-target-id-v2-v3`.
1543015430

15431+
.. _amdgpu-assembler-directive-amdhsa-code-object-version:
15432+
15433+
.amdhsa_code_object_version <version>
15434+
+++++++++++++++++++++++++++++++++++++
15435+
15436+
Optional directive which declares the code object version to be generated by the
15437+
assembler. If not present, a default value will be used.
15438+
1543115439
.amdhsa_kernel <name>
1543215440
+++++++++++++++++++++
1543315441

‎llvm/include/llvm/MC/MCObjectWriter.h

+3
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,9 @@ class MCObjectWriter {
9292
/// ELF only. Mark that we have seen GNU ABI usage (e.g. SHF_GNU_RETAIN).
9393
virtual void markGnuAbi() {}
9494

95+
/// ELF only, override the default ABIVersion in the ELF header.
96+
virtual void setOverrideABIVersion(uint8_t ABIVersion) {}
97+
9598
/// Tell the object writer to emit an address-significance table during
9699
/// writeObject(). If this function is not called, all symbols are treated as
97100
/// address-significant.

‎llvm/include/llvm/Support/AMDGPUMetadata.h

+2-8
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,6 @@ namespace AMDGPU {
2929
//===----------------------------------------------------------------------===//
3030
namespace HSAMD {
3131

32-
/// HSA metadata major version for code object V2.
33-
constexpr uint32_t VersionMajorV2 = 1;
34-
/// HSA metadata minor version for code object V2.
35-
constexpr uint32_t VersionMinorV2 = 0;
36-
3732
/// HSA metadata major version for code object V3.
3833
constexpr uint32_t VersionMajorV3 = 1;
3934
/// HSA metadata minor version for code object V3.
@@ -49,10 +44,9 @@ constexpr uint32_t VersionMajorV5 = 1;
4944
/// HSA metadata minor version for code object V5.
5045
constexpr uint32_t VersionMinorV5 = 2;
5146

52-
/// HSA metadata beginning assembler directive.
47+
/// Old HSA metadata beginning assembler directive for V2. This is only used for
48+
/// diagnostics now.
5349
constexpr char AssemblerDirectiveBegin[] = ".amd_amdgpu_hsa_metadata";
54-
/// HSA metadata ending assembler directive.
55-
constexpr char AssemblerDirectiveEnd[] = ".end_amd_amdgpu_hsa_metadata";
5650

5751
/// Access qualifiers.
5852
enum class AccessQualifier : uint8_t {

‎llvm/lib/MC/ELFObjectWriter.cpp

+10-1
Original file line numberDiff line numberDiff line change
@@ -226,6 +226,8 @@ class ELFObjectWriter : public MCObjectWriter {
226226

227227
bool SeenGnuAbi = false;
228228

229+
std::optional<uint8_t> OverrideABIVersion;
230+
229231
bool hasRelocationAddend() const;
230232

231233
bool shouldRelocateWithSymbol(const MCAssembler &Asm, const MCValue &Val,
@@ -238,6 +240,7 @@ class ELFObjectWriter : public MCObjectWriter {
238240

239241
void reset() override {
240242
SeenGnuAbi = false;
243+
OverrideABIVersion.reset();
241244
Relocations.clear();
242245
Renames.clear();
243246
MCObjectWriter::reset();
@@ -264,6 +267,10 @@ class ELFObjectWriter : public MCObjectWriter {
264267
void markGnuAbi() override { SeenGnuAbi = true; }
265268
bool seenGnuAbi() const { return SeenGnuAbi; }
266269

270+
bool seenOverrideABIVersion() const { return OverrideABIVersion.has_value(); }
271+
uint8_t getOverrideABIVersion() const { return OverrideABIVersion.value(); }
272+
void setOverrideABIVersion(uint8_t V) override { OverrideABIVersion = V; }
273+
267274
friend struct ELFWriter;
268275
};
269276

@@ -417,7 +424,9 @@ void ELFWriter::writeHeader(const MCAssembler &Asm) {
417424
? int(ELF::ELFOSABI_GNU)
418425
: OSABI);
419426
// e_ident[EI_ABIVERSION]
420-
W.OS << char(OWriter.TargetObjectWriter->getABIVersion());
427+
W.OS << char(OWriter.seenOverrideABIVersion()
428+
? OWriter.getOverrideABIVersion()
429+
: OWriter.TargetObjectWriter->getABIVersion());
421430

422431
W.OS.write_zeros(ELF::EI_NIDENT - ELF::EI_PAD);
423432

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

+8-6
Original file line numberDiff line numberDiff line change
@@ -123,8 +123,11 @@ void AMDGPUAsmPrinter::initTargetStreamer(Module &M) {
123123

124124
getTargetStreamer()->EmitDirectiveAMDGCNTarget();
125125

126-
if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
126+
if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
127+
getTargetStreamer()->EmitDirectiveAMDHSACodeObjectVersion(
128+
CodeObjectVersion);
127129
HSAMetadataStream->begin(M, *getTargetStreamer()->getTargetID());
130+
}
128131

129132
if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
130133
getTargetStreamer()->getPALMetadata()->readFromIR(M);
@@ -230,8 +233,7 @@ void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
230233
IsaInfo::getNumExtraSGPRs(
231234
&STM, CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
232235
getTargetStreamer()->getTargetID()->isXnackOnOrAny()),
233-
CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
234-
CodeObjectVersion);
236+
CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed);
235237

236238
Streamer.popSection();
237239
}
@@ -323,7 +325,7 @@ void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
323325
}
324326

325327
bool AMDGPUAsmPrinter::doInitialization(Module &M) {
326-
CodeObjectVersion = AMDGPU::getCodeObjectVersion(M);
328+
CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(M);
327329

328330
if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
329331
switch (CodeObjectVersion) {
@@ -631,8 +633,8 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
631633
void AMDGPUAsmPrinter::initializeTargetID(const Module &M) {
632634
// In the beginning all features are either 'Any' or 'NotSupported',
633635
// depending on global target features. This will cover empty modules.
634-
getTargetStreamer()->initializeTargetID(
635-
*getGlobalSTI(), getGlobalSTI()->getFeatureString(), CodeObjectVersion);
636+
getTargetStreamer()->initializeTargetID(*getGlobalSTI(),
637+
getGlobalSTI()->getFeatureString());
636638

637639
// If module is empty, we are done.
638640
if (M.empty())

‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ class AMDGPUInformationCache : public InformationCache {
144144
BumpPtrAllocator &Allocator,
145145
SetVector<Function *> *CGSCC, TargetMachine &TM)
146146
: InformationCache(M, AG, Allocator, CGSCC), TM(TM),
147-
CodeObjectVersion(AMDGPU::getCodeObjectVersion(M)) {}
147+
CodeObjectVersion(AMDGPU::getAMDHSACodeObjectVersion(M)) {}
148148

149149
TargetMachine &TM;
150150

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -474,7 +474,7 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
474474

475475
const Module *M = MF.getFunction().getParent();
476476
if (UserSGPRInfo.hasQueuePtr() &&
477-
AMDGPU::getCodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) {
477+
AMDGPU::getAMDHSACodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) {
478478
Register QueuePtrReg = Info.addQueuePtr(TRI);
479479
MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
480480
CCInfo.AllocateReg(QueuePtrReg);

‎llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -532,7 +532,8 @@ void MetadataStreamerMsgPackV4::emitKernel(const MachineFunction &MF,
532532
Func.getCallingConv() != CallingConv::SPIR_KERNEL)
533533
return;
534534

535-
auto CodeObjectVersion = AMDGPU::getCodeObjectVersion(*Func.getParent());
535+
auto CodeObjectVersion =
536+
AMDGPU::getAMDHSACodeObjectVersion(*Func.getParent());
536537
auto Kern = getHSAKernelProps(MF, ProgramInfo, CodeObjectVersion);
537538

538539
auto Kernels =

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -2139,7 +2139,7 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
21392139
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
21402140
// For code object version 5, private_base and shared_base are passed through
21412141
// implicit kernargs.
2142-
if (AMDGPU::getCodeObjectVersion(*MF.getFunction().getParent()) >=
2142+
if (AMDGPU::getAMDHSACodeObjectVersion(*MF.getFunction().getParent()) >=
21432143
AMDGPU::AMDHSA_COV5) {
21442144
AMDGPUTargetLowering::ImplicitParameter Param =
21452145
AS == AMDGPUAS::LOCAL_ADDRESS ? AMDGPUTargetLowering::SHARED_BASE
@@ -6582,7 +6582,7 @@ bool AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(
65826582

65836583
Register SGPR01(AMDGPU::SGPR0_SGPR1);
65846584
// For code object version 5, queue_ptr is passed through implicit kernarg.
6585-
if (AMDGPU::getCodeObjectVersion(*MF.getFunction().getParent()) >=
6585+
if (AMDGPU::getAMDHSACodeObjectVersion(*MF.getFunction().getParent()) >=
65866586
AMDGPU::AMDHSA_COV5) {
65876587
AMDGPUTargetLowering::ImplicitParameter Param =
65886588
AMDGPUTargetLowering::QUEUE_PTR;

‎llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp

+3-2
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,8 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
323323
// TargetPassConfig for subtarget.
324324
bool AMDGPULowerKernelAttributes::runOnModule(Module &M) {
325325
bool MadeChange = false;
326-
bool IsV5OrAbove = AMDGPU::getCodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5;
326+
bool IsV5OrAbove =
327+
AMDGPU::getAMDHSACodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5;
327328
Function *BasePtr = getBasePtrIntrinsic(M, IsV5OrAbove);
328329

329330
if (!BasePtr) // ImplicitArgPtr/DispatchPtr not used.
@@ -356,7 +357,7 @@ ModulePass *llvm::createAMDGPULowerKernelAttributesPass() {
356357
PreservedAnalyses
357358
AMDGPULowerKernelAttributesPass::run(Function &F, FunctionAnalysisManager &AM) {
358359
bool IsV5OrAbove =
359-
AMDGPU::getCodeObjectVersion(*F.getParent()) >= AMDGPU::AMDHSA_COV5;
360+
AMDGPU::getAMDHSACodeObjectVersion(*F.getParent()) >= AMDGPU::AMDHSA_COV5;
360361
Function *BasePtr = getBasePtrIntrinsic(*F.getParent(), IsV5OrAbove);
361362

362363
if (!BasePtr) // ImplicitArgPtr/DispatchPtr not used.

‎llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) {
112112

113113
// By default, for code object v5 and later, track only the minimum scratch
114114
// size
115-
if (AMDGPU::getCodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5 ||
115+
if (AMDGPU::getAMDHSACodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5 ||
116116
STI.getTargetTriple().getOS() == Triple::AMDPAL) {
117117
if (!AssumedStackSizeForDynamicSizeObjects.getNumOccurrences())
118118
AssumedStackSizeForDynamicSizeObjects = 0;

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -571,7 +571,7 @@ unsigned AMDGPUSubtarget::getImplicitArgNumBytes(const Function &F) const {
571571
// Assume all implicit inputs are used by default
572572
const Module *M = F.getParent();
573573
unsigned NBytes =
574-
AMDGPU::getCodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5 ? 256 : 56;
574+
AMDGPU::getAMDHSACodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5 ? 256 : 56;
575575
return F.getFnAttributeAsParsedInteger("amdgpu-implicitarg-num-bytes",
576576
NBytes);
577577
}

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

+13-78
Original file line numberDiff line numberDiff line change
@@ -1303,10 +1303,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
13031303
unsigned NextFreeSGPR, SMRange SGPRRange,
13041304
unsigned &VGPRBlocks, unsigned &SGPRBlocks);
13051305
bool ParseDirectiveAMDGCNTarget();
1306+
bool ParseDirectiveAMDHSACodeObjectVersion();
13061307
bool ParseDirectiveAMDHSAKernel();
1307-
bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
1308-
bool ParseDirectiveHSACodeObjectVersion();
1309-
bool ParseDirectiveHSACodeObjectISA();
13101308
bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
13111309
bool ParseDirectiveAMDKernelCodeT();
13121310
// TODO: Possibly make subtargetHasRegister const.
@@ -5133,20 +5131,6 @@ bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
51335131
return false;
51345132
}
51355133

5136-
bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
5137-
uint32_t &Minor) {
5138-
if (ParseAsAbsoluteExpression(Major))
5139-
return TokError("invalid major version");
5140-
5141-
if (!trySkipToken(AsmToken::Comma))
5142-
return TokError("minor version number required, comma expected");
5143-
5144-
if (ParseAsAbsoluteExpression(Minor))
5145-
return TokError("invalid minor version");
5146-
5147-
return false;
5148-
}
5149-
51505134
bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
51515135
if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
51525136
return TokError("directive only supported for amdgcn architecture");
@@ -5612,63 +5596,18 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
56125596
}
56135597
}
56145598

5615-
getTargetStreamer().EmitAmdhsaKernelDescriptor(
5616-
getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,
5617-
ReserveFlatScr, AMDGPU::getAmdhsaCodeObjectVersion());
5618-
return false;
5619-
}
5620-
5621-
bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
5622-
uint32_t Major;
5623-
uint32_t Minor;
5624-
5625-
if (ParseDirectiveMajorMinor(Major, Minor))
5626-
return true;
5627-
5628-
getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);
5599+
getTargetStreamer().EmitAmdhsaKernelDescriptor(getSTI(), KernelName, KD,
5600+
NextFreeVGPR, NextFreeSGPR,
5601+
ReserveVCC, ReserveFlatScr);
56295602
return false;
56305603
}
56315604

5632-
bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
5633-
uint32_t Major;
5634-
uint32_t Minor;
5635-
uint32_t Stepping;
5636-
StringRef VendorName;
5637-
StringRef ArchName;
5638-
5639-
// If this directive has no arguments, then use the ISA version for the
5640-
// targeted GPU.
5641-
if (isToken(AsmToken::EndOfStatement)) {
5642-
AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
5643-
getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,
5644-
ISA.Stepping,
5645-
"AMD", "AMDGPU");
5646-
return false;
5647-
}
5648-
5649-
if (ParseDirectiveMajorMinor(Major, Minor))
5650-
return true;
5651-
5652-
if (!trySkipToken(AsmToken::Comma))
5653-
return TokError("stepping version number required, comma expected");
5654-
5655-
if (ParseAsAbsoluteExpression(Stepping))
5656-
return TokError("invalid stepping version");
5657-
5658-
if (!trySkipToken(AsmToken::Comma))
5659-
return TokError("vendor name required, comma expected");
5660-
5661-
if (!parseString(VendorName, "invalid vendor name"))
5662-
return true;
5663-
5664-
if (!trySkipToken(AsmToken::Comma))
5665-
return TokError("arch name required, comma expected");
5666-
5667-
if (!parseString(ArchName, "invalid arch name"))
5605+
bool AMDGPUAsmParser::ParseDirectiveAMDHSACodeObjectVersion() {
5606+
uint32_t Version;
5607+
if (ParseAsAbsoluteExpression(Version))
56685608
return true;
56695609

5670-
getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,
5671-
VendorName, ArchName);
5610+
getTargetStreamer().EmitDirectiveAMDHSACodeObjectVersion(Version);
56725611
return false;
56735612
}
56745613

@@ -5955,16 +5894,13 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
59555894
if (IDVal == ".amdhsa_kernel")
59565895
return ParseDirectiveAMDHSAKernel();
59575896

5897+
if (IDVal == ".amdhsa_code_object_version")
5898+
return ParseDirectiveAMDHSACodeObjectVersion();
5899+
59585900
// TODO: Restructure/combine with PAL metadata directive.
59595901
if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)
59605902
return ParseDirectiveHSAMetadata();
59615903
} else {
5962-
if (IDVal == ".hsa_code_object_version")
5963-
return ParseDirectiveHSACodeObjectVersion();
5964-
5965-
if (IDVal == ".hsa_code_object_isa")
5966-
return ParseDirectiveHSACodeObjectISA();
5967-
59685904
if (IDVal == ".amd_kernel_code_t")
59695905
return ParseDirectiveAMDKernelCodeT();
59705906

@@ -8137,9 +8073,8 @@ void AMDGPUAsmParser::onBeginOfFile() {
81378073
return;
81388074

81398075
if (!getTargetStreamer().getTargetID())
8140-
getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString(),
8141-
// TODO: Should try to check code object version from directive???
8142-
AMDGPU::getAmdhsaCodeObjectVersion());
8076+
getTargetStreamer().initializeTargetID(getSTI(),
8077+
getSTI().getFeatureString());
81438078

81448079
if (isHsaAbi(getSTI()))
81458080
getTargetStreamer().EmitDirectiveAMDGCNTarget();

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -2184,7 +2184,8 @@ AMDGPUDisassembler::decodeKernelDescriptorDirective(
21842184
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
21852185
}
21862186

2187-
if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5)
2187+
// FIXME: We should be looking at the ELF header ABI version for this.
2188+
if (AMDGPU::getDefaultAMDHSACodeObjectVersion() >= AMDGPU::AMDHSA_COV5)
21882189
PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack",
21892190
KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
21902191

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

+5-9
Original file line numberDiff line numberDiff line change
@@ -232,13 +232,11 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
232232
bool Is64Bit;
233233
bool HasRelocationAddend;
234234
uint8_t OSABI = ELF::ELFOSABI_NONE;
235-
uint8_t ABIVersion = 0;
236235

237236
public:
238-
ELFAMDGPUAsmBackend(const Target &T, const Triple &TT, uint8_t ABIVersion) :
239-
AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
240-
HasRelocationAddend(TT.getOS() == Triple::AMDHSA),
241-
ABIVersion(ABIVersion) {
237+
ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
238+
: AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
239+
HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
242240
switch (TT.getOS()) {
243241
case Triple::AMDHSA:
244242
OSABI = ELF::ELFOSABI_AMDGPU_HSA;
@@ -256,8 +254,7 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
256254

257255
std::unique_ptr<MCObjectTargetWriter>
258256
createObjectTargetWriter() const override {
259-
return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend,
260-
ABIVersion);
257+
return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend);
261258
}
262259
};
263260

@@ -267,6 +264,5 @@ MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
267264
const MCSubtargetInfo &STI,
268265
const MCRegisterInfo &MRI,
269266
const MCTargetOptions &Options) {
270-
return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(),
271-
getHsaAbiVersion(&STI).value_or(0));
267+
return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
272268
}

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