README.md

Processor Design

Designing and simlating simple 5-stage pipelined RISC-V processor using SystemVelilog and ModelSim

Lab assignment of 2020-2R "Computer Architecture" class

Lab 1: Instruction Design (Score 5/5)

Lab 2: Datapath Element Design (Score 20/20)

Lab 3: Single-cycle Processor Design (Score 30/30)

Lab 4: 5-stage Pipelined Processor Design (Score 45/45)