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Add Verilator lint #9

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Intuity opened this issue Sep 18, 2022 · 0 comments
Open

Add Verilator lint #9

Intuity opened this issue Sep 18, 2022 · 0 comments

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@Intuity
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Intuity commented Sep 18, 2022

Adding a Verilator stage to check the input Verilog to the flow would help to ensure consistency, and avoid issues further down the process when building the full chip. It may be worth waiving some of the more fussy rules, and just keeping the ones which are absolutely essential.

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