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Adding a Verilator stage to check the input Verilog to the flow would help to ensure consistency, and avoid issues further down the process when building the full chip. It may be worth waiving some of the more fussy rules, and just keeping the ones which are absolutely essential.
The text was updated successfully, but these errors were encountered:
Adding a Verilator stage to check the input Verilog to the flow would help to ensure consistency, and avoid issues further down the process when building the full chip. It may be worth waiving some of the more fussy rules, and just keeping the ones which are absolutely essential.
The text was updated successfully, but these errors were encountered: