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Lab6b.flow.rpt
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Flow report for Lab6b
Sat Dec 10 15:21:06 2022
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Sat Dec 10 15:21:06 2022 ;
; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
; Revision Name ; Lab6b ;
; Top-level Entity Name ; motionsynth ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C7G ;
; Timing Models ; Final ;
; Total logic elements ; 6,473 / 49,760 ( 13 % ) ;
; Total combinational functions ; 5,707 / 49,760 ( 11 % ) ;
; Dedicated logic registers ; 3,342 / 49,760 ( 7 % ) ;
; Total registers ; 3411 ;
; Total pins ; 141 / 360 ( 39 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 25,112 / 1,677,312 ( 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/10/2022 15:18:37 ;
; Main task ; Compilation ;
; Revision Name ; Lab6b ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+------------------------------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+------------------------------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 1095757637807.167070711624380 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (SystemVerilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; FLOW_ENABLE_POWER_ANALYZER ; On ; Off ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; lab62soc/synthesis/../lab62soc.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lab62soc/synthesis/../../lab62soc.qsys ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; motionsynth ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; motionsynth ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; motionsynth ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; SLD_FILE ; lab62soc/synthesis/lab62soc.regmap ; -- ; -- ; -- ;
; SLD_FILE ; lab62soc/synthesis/lab62soc.debuginfo ; -- ; -- ; -- ;
; SLD_INFO ; QSYS_NAME lab62soc HAS_SOPCINFO 1 GENERATION_ID 1670471469 ; -- ; lab62soc ; -- ;
; SOPCINFO_FILE ; lab62soc/synthesis/../../lab62soc.sopcinfo ; -- ; -- ; -- ;
; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; motionsynth ; Lab6b ; -- ; -- ;
+-------------------------------------+------------------------------------------------------------+---------------+-------------+----------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:01:09 ; 1.0 ; 5051 MB ; 00:01:26 ;
; Fitter ; 00:00:42 ; 1.7 ; 6340 MB ; 00:01:32 ;
; Assembler ; 00:00:05 ; 1.0 ; 4712 MB ; 00:00:05 ;
; Power Analyzer ; 00:00:08 ; 2.4 ; 5045 MB ; 00:00:17 ;
; Timing Analyzer ; 00:00:09 ; 2.9 ; 5007 MB ; 00:00:17 ;
; EDA Netlist Writer ; 00:00:04 ; 1.0 ; 4760 MB ; 00:00:04 ;
; Total ; 00:02:17 ; -- ; -- ; 00:03:41 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; MattENVYx360 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; MattENVYx360 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; MattENVYx360 ; Windows 10 ; 10.0 ; x86_64 ;
; Power Analyzer ; MattENVYx360 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; MattENVYx360 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; MattENVYx360 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off Lab6b -c Lab6b
quartus_fit --read_settings_files=off --write_settings_files=off Lab6b -c Lab6b
quartus_asm --read_settings_files=off --write_settings_files=off Lab6b -c Lab6b
quartus_pow --read_settings_files=off --write_settings_files=off Lab6b -c Lab6b
quartus_sta Lab6b -c Lab6b
quartus_eda --read_settings_files=off --write_settings_files=off Lab6b -c Lab6b