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Concept for variables that are input and output #10

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chrbertsch opened this issue Feb 6, 2023 · 1 comment
Open

Concept for variables that are input and output #10

chrbertsch opened this issue Feb 6, 2023 · 1 comment
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clarify Issue needs some further clarification. common Issue within the common part of the specification that is not directly related to a specific bus

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@chrbertsch
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citing from: https://github.com/modelica/fmi-design/tree/master/Meetings/2023/2023-01-17-FMI-Design-Webmeeting

Clocked variables: input and output?
Pierre: not possible in FMI 3
Andreas: We need two variables. We need an issue for this.
Christian: is this not a special kind of terminal?
Pierre: might be similar for acausal connections? We could look for a general solution

Currently https://github.com/modelica/fmi-ls-bus/blob/main/docs/2____common_concepts.adoc reads:

If an FMU represents network nodes that are both sender and receiver of a signal, the receiver role will be removed from the FMU interface to allow the signals to have a unique role as output and the reading of such outputs must be handled internally to the FMU.
[The FMI standard requires a variable to be either input or output.]
TODO: is this correct? does that also work for network simulations? how else to solve this unique-variable-name requirement?
@chrbertsch
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Is this problem in the high cut not similar to the Tx / Rx approach in the low cut?
Do we need a duplication of variables (one input and one output, e.g., SignalName_IN, SignalName_OUT, or Signalanme_Tx, SignalName_Rx?)

@bmenne-dspace bmenne-dspace added common Issue within the common part of the specification that is not directly related to a specific bus clarify Issue needs some further clarification. labels Sep 12, 2023
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clarify Issue needs some further clarification. common Issue within the common part of the specification that is not directly related to a specific bus
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