PCIe XDMA demo with various Clocking Wizard tests for the Innova-2 using Vivado 2022.2. The goal is a slow clock that works with AXI peripherals.
Note each AXI GPIO peripheral clocked by a slow clock needs its own Processor System Reset module to generate a clock-domain crossing reset signal based on the XDMA axi_aresetn signal.
Recreate the bitstream. Download slow_clock_tests.tcl and constraints.xdc and source the Tcl script in the Vivado 2022.2 Tcl Console then run Generate Bitstream.
pwd
cd PROJECT_NAME
dir
source slow_clock_tests.tcl
Load the bitstream into your Innova-2. It should work with every variant of the Innova-2. Refer to innova2_flex_xcku15p_notes for system setup.
The Clocking Wizard is set up to generate the slowest clock possible.
The first method is courtesy markg@prosensing from this discussion thread. Using a 250MHz XDMA axi_aclk as input, the slowest possible clock output is about 76kHz.
Clocking Wizard Setup - Clocking Options. Set the Primitive to MMCM and the Source of the Primary Clock to Global Buffer.
Clocking Wizard Setup - MMCM Settings. Set Allow Override Mode and CLKOUT4_CASCADE. Set Divide values for the clk_out? ports to 10, 10, 10, 100, 128, 128, and 128.
Clocking Wizard Setup - Output Clocks. clk_out5 will be qual to (250MHz*10)/DIVCLK_DIVIDE/CLKOUT4_Divide/CLKOUT6_Divide=0.076MHz=76294Hz
Clocking Wizard Setup - Summary:
The second method uses a BUFG Utility Buffer to route a binary counter output onto the global clock network. Slice is used to cut out the most significant bit (MSb). The clock input to the 18-bit counter is 250MHz so the output should be about (250000000/(2^18))=954Hz.
slow_clock_test.c is a simple C program to test the XDMA interface, communicate with AXI peripherals clocked by the slow clocks, and estimate the slow clock periods.
gcc slow_clock_test.c -g -Wall -o slow_clock_test
sudo ./slow_clock_test /dev/xdma0_c2h_0 /dev/xdma0_h2c_0
