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xdma_uart-to-uart

Innova-2 PCIe UART over XDMA Test

Two non-blocking UARTs are connected to each other and through an AXI SmartConnect to XDMA PCIe. This is a test platform for UART over XDMA.

Block Design

PCIe UART over XDMA Block Design

Bitstream

Refer to the innova2_flex_xcku15p_notes project's instructions on installing XDMA drivers and Loading a User Image to load the release bitstream into the Innova-2's FPGA Configuration Memory.

wget https://github.com/mwrnd/innova2_experiments/releases/download/v0.1-alpha/xdma_uart-to-uart_bitstream.zip
unzip -d .  xdma_uart-to-uart_bitstream.zip
md5sum  xdma_uart-to-uart_primary.bin  xdma_uart-to-uart_secondary.bin
echo 4cab44d93b10960a7dd0ce653630d69b should be MD5 Checksum of xdma_uart-to-uart_primary.bin
echo 015c797003f4ddf770c6ea418bd22a18 should be MD5 Checksum of xdma_uart-to-uart_secondary.bin

AXI Addresses

PCIe UART over XDMA Addresses

Testing

xdma_tty_cuse.c bridges the AXI UARTs to the host's TTY subsystem. Compile then run with:

gcc xdma_tty_cuse.c `pkg-config fuse --cflags --libs` --std=gnu17 -g -Wall -latomic -o xdma_tty_cuse

sudo ./xdma_tty_cuse  /dev/xdma0_c2h_0  /dev/xdma0_h2c_0  0x60100000 ttyCUSE0

In a second terminal, connect to the CUSE TTY device:

sudo gtkterm --port /dev/ttyCUSE0

In a third terminal, run a second instance of XDMA TTY CUSE TTY:

sudo ./xdma_tty_cuse  /dev/xdma0_c2h_1  /dev/xdma0_h2c_1  0x60110000 ttyCUSE1

In a fourth terminal, connect to the second CUSE TTY device:

sudo gtkterm --port /dev/ttyCUSE1

XDMA TTY CUSE Loopback Test Commands

Typing in one GTKTerm window should display the characters in the other window.

XDMA TTY CUSE Loopback Test

Sending Files Larger than twice the FIFO Buffer Depth Fails

If you attempt to send a file, the TTY will lock up after sending about twice the number of characters that the RX and TX FIFOs hold.

Send RAW File

001abcdefghijklmnopqrstuvwxyzA is 30 bytes while each FIFO has a 2^4=16-byte depth.

TTY Locks

Basic XDMA UART Testing

uart.c sends as much data as it can to the first AXI UART then reads as much data as it can from the second. Compile then run with:

gcc uart.c `pkg-config fuse --cflags --libs` --std=gnu17 -g -Wall -latomic -o uart

In a seperate terminal, test with:

sudo ./uart /dev/xdma0_c2h_0 /dev/xdma0_h2c_0 0x60100000 /dev/xdma0_c2h_1 /dev/xdma0_h2c_1 0x60110000

The software is able to fill the RX and TX FIFOs with 30 bytes (15 to each FIFO), and successfully read them back.

...
Wrote count = 30 bytes of data to XDMA0 : ABCDEFGHIJKLMNOPQRSTUVWXYZABCD
...
Read count = 30 bytes of data from XDMA1, readstring = ABCDEFGHIJKLMNOPQRSTUVWXYZABCD
...

Similarly with uartlite.c for the UARTlite interfaces:

gcc uartlite.c `pkg-config fuse --cflags --libs` --std=gnu17 -g -Wall -latomic -o uartlite
sudo ./uartlite /dev/xdma0_c2h_0 /dev/xdma0_h2c_0 0x60300000 /dev/xdma0_c2h_1 /dev/xdma0_h2c_1 0x60310000

The UARTlite software needs further debugging. Either delay after each byte sent or wait for the transmit FIFO to empty before sending another byte. Check for the various STATUS register errors.

...
Wrote count = 24 bytes of data to XDMA0 : ABCDEFGHIJKLMNOPQRSTUVWX
...
Read count = 17 bytes of data from XDMA1, readstring = AABCDEFGHIJKLMNOP
...

Integrated Logic Analyzer

The de#cludes an Integrated Logic Analyzer (ILA) for the AXI interface of each UART.

On the computer hosting the Innova-2, enable JTAG Access:

sudo mst start
cd ~/Innova_2_Flex_Open_18_12/driver/
sudo ./make_device
cd ~
sudo insmod /usr/lib/modules/`uname -r`/updates/dkms/mlx5_fpga_tools.ko
sudo ~/Innova_2_Flex_Open_18_12/app/innova2_flex_app -v

Enable JTAG Access

Connect a Xilinx-Compatible 1.8V JTAG Adapter to the Innova-2 and run Vivado Hardware Manager. Add debug_nets.ltx to the Trigger Setup and capture AXI communication.

Capture from Integrated Logic Analyzer

Recreating the De# Vivado

source xdma_uart-to-uart.tcl in Vivado.

Useful References