selector.vhdl.bak

library ieee;
use ieee.std_logic_1164.all;

entity waterControl is
port(
	clk: in std_logic;
	sw_seleccion: in  std_logic;
	led : out std_logic;
	display: out std_logic_vector (6 downto 0)
	
);
end waterControl;


architecture behavior of waterControl is
signal ledInterno : std_logic:='0';

begin 
led<=ledInterno;
process(clk)
	begin
		if rising_edge(clk) then	
			if sw_seleccion='1' then
				ledInterno<='1';
				display<="1111001";		
			else
				ledInterno<='0';
				display <= "1000110";
			end if;
		end if;


end process;



end architecture behavior;