diff --git a/.metrics.json b/.metrics.json index f172cc9df4..2e377e79e3 100644 --- a/.metrics.json +++ b/.metrics.json @@ -10,109 +10,115 @@ "list": [ { "name": "uvmt_cv32e40p", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40p/sim/uvmt; make corev-dv CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40p/sim/uvmt; make corev-dv CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40p_compliance_build", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40p/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40p/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40p SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x_num_mhpmcounter_29", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x_pma_1", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x_pma_2", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x_pma_3", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x_pma_4", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x_pma_5", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40x CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40x_compliance_build", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40x/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40x DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", - "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", - "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", + "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s SIMULATOR=dsim CFG=default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", + "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s SIMULATOR=dsim CFG=default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" + }, + { + "name": "uvmt_cv32e40s_clic", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", + "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=clic_default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s SIMULATOR=dsim CFG=clic_default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", + "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=clic_default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s SIMULATOR=dsim CFG=clic_default DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s_num_mhpmcounter_29", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=num_mhpmcounter_29 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=num_mhpmcounter_29 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=num_mhpmcounter_29 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s_pma_1", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_1 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_1 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_1 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s_pma_2", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_2 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_2 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_2 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s_pma_3", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_3 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_3 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_3 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s_pma_4", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_4 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_4 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_4 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s_pma_5", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_5 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40s/sim/uvmt; make corev-dv CV_CORE=cv32e40s SIMULATOR=dsim CFG=pma_test_cfg_5 DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results; make comp CV_CORE=cv32e40s CFG=pma_test_cfg_5 SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" }, { "name": "uvmt_cv32e40s_compliance_build", - "image": "gcr.io/openhwgroup-metrics-project/cv32-simulation-tools:20211122.7.0-02Feb2022", + "image": "gcr.io/openhwgroup-metrics-project/openhwgroup-toolchain:20220328.14.0-dtc.66", "cmd": "cd cv32e40s/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40s SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results", "wavesCmd": "cd cv32e40s/sim/uvmt; make all_compliance; make comp CV_CORE=cv32e40s SIMULATOR=dsim DSIM_WORK=/mux-flow/build/repo/dsim_work SIM_RESULTS=/mux-flow/build/results WAVES=1" } @@ -307,7 +313,7 @@ "verbose": "true", "tests": { "resultsDir": "/mux-flow/build/results", - "builds": ["uvmt_cv32e40s", "uvmt_cv32e40s_pma_1", "uvmt_cv32e40s_pma_2" ], + "builds": ["uvmt_cv32e40s", "uvmt_cv32e40s_clic", "uvmt_cv32e40s_pma_1", "uvmt_cv32e40s_pma_2" ], "listCmd": "/mux-flow/build/repo/bin/cv_regress --core=cv32e40s --file=cv32e40s_ci_check --metrics --outfile=/mux-flow/build/repo/cv32e40s_ci_check.json", "listFile": "/mux-flow/build/repo/cv32e40s_ci_check.json" } diff --git a/bin/ci_check b/bin/ci_check index 42cf58c127..0281e66954 100755 --- a/bin/ci_check +++ b/bin/ci_check @@ -298,7 +298,7 @@ if (uvm): if (debug): print (json.dumps(list_dict, indent=2, sort_keys=True)) for key in list_dict: - if (key['name'] != 'uvmt_{}'.format(args.core.lower())): + if ('uvmt_{}'.format(args.core.lower()) not in key['name'] ): continue build_cmd_list = (key['cmd']).split() build_cmd = ' '.join(build_cmd_list[0:-1]) @@ -340,61 +340,71 @@ if (uvm): print('Cannot parse listCmd: {}'.format(item['tests']['listCmd'])) exit(1) lists_dict = load_regress_yaml(m.group(1))['tests'] + cfg_dict = load_regress_yaml(m.group(1))['builds'] if (debug): pprint.pprint(lists_dict) num_tests = 0 for key in lists_dict.values(): - run_cmd = key['cmd'] - - if run_cmd == '': - print ('ERROR: cannot find run command in .metrics.json') - exit(1) - try: - if key['num'] > 1: - num = key['num'] - except KeyError: - num = 1 - - # The iss command-line switch takes precedence, - # Otherwise use what is in the regression yaml if defined - # Otherwise set to 1 - if args.iss != None: - iss = int(args.iss) - else: + if (type(key['builds']) is not list): + key['builds'] = [key['builds']] + except: + key['builds'] = ['default'] + for build in key['builds']: + cfg = (load_regress_yaml(m.group(1))['builds'][build]['cfg']) + run_cmd = key['cmd'] + + if run_cmd == '': + print ('ERROR: cannot find run command in .metrics.json') + exit(1) + try: - iss = key['iss'] + if key['num'] > 1: + num = key['num'] except KeyError: - iss = 1 - - for n in range(num): - # Add directory - full_run_cmd = 'cd {}; {}'.format(key['dir'], run_cmd) - # Add SIMULATOR - full_run_cmd += ' SIMULATOR={}'.format(svtool) - # Add indices - full_run_cmd += ' GEN_START_INDEX={} RUN_INDEX={}'.format(n, n) - # Add ISS - full_run_cmd += ' USE_ISS={}'.format('YES' if iss else 'NO') - - # Only DSIM can run corev-dv (riscv-dv) at present - if ( svtool == 'dsim' or svtool == 'xrun' or svtool == 'vsim' or svtool == 'riviera' or svtool == 'vcs'): - num_tests+=1 - if (prcmd or debug): - print(full_run_cmd) - else: - os.system(full_run_cmd) - os.chdir(topdir) # cmd in .metrics.json assumes all cmds start from here + num = 1 + + # The iss command-line switch takes precedence, + # Otherwise use what is in the regression yaml if defined + # Otherwise set to 1 + if args.iss != None: + iss = int(args.iss) else: - num_tests+=1 - if not ( re.search('corev_', full_run_cmd) ): + try: + iss = key['iss'] + except KeyError: + iss = 1 + + for n in range(num): + # Add directory + full_run_cmd = 'cd {}; {}'.format(key['dir'], run_cmd) + # Add cfg + if (cfg is not None): + full_run_cmd += ' CFG={}'.format(cfg) + # Add SIMULATOR + full_run_cmd += ' SIMULATOR={}'.format(svtool) + # Add indices + full_run_cmd += ' GEN_START_INDEX={} RUN_INDEX={}'.format(n, n) + # Add ISS + full_run_cmd += ' USE_ISS={}'.format('YES' if iss else 'NO') + + if ( svtool == 'dsim' or svtool == 'xrun' or svtool == 'vsim' or svtool == 'riviera' or svtool == 'vcs'): + num_tests+=1 if (prcmd or debug): print(full_run_cmd) else: os.system(full_run_cmd) os.chdir(topdir) # cmd in .metrics.json assumes all cmds start from here + else: + num_tests+=1 + if not ( re.search('corev_', full_run_cmd) ): + if (prcmd or debug): + print(full_run_cmd) + else: + os.system(full_run_cmd) + os.chdir(topdir) # cmd in .metrics.json assumes all cmds start from here else: # if(uvm): print ('Not running UVM CI regression') diff --git a/bin/clonetb b/bin/clonetb new file mode 100755 index 0000000000..bc58ca6481 --- /dev/null +++ b/bin/clonetb @@ -0,0 +1,133 @@ +#!/bin/sh + + +# Copyright 2023 Silicon Laboratories Inc. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +# not use this file except in compliance with the License, or, at your option, +# the Apache License version 2.0. +# +# You may obtain a copy of the License at +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. + + +# Description: +# This script is used to clone core-specific verification environments. +# (E.g. "core-v-verif/cv32e40x/".) +# Try running it, and it will assist you with helpful messages. +# +# Examples: +# "$ ./bin/clonetb" +# "$ ./bin/clonetb -x" +# "$ CV_CORE=cv32e40x ./bin/clonetb --unignore" +# +# Environment: +# (Typical usage does not require these to be set.) +# CV_CORE - Name of the core to use. +# VERIF_ENV_REPO - URL to external verif env repo. +# VERIF_ENV_REF - Branch/hash/tag of external verif env repo. + + +usage() { + echo "usage: $0 [-x] [--clone] [--ignore] [--unignore]" + echo " -x clone cv32e40x subtree" + echo " --clone clone subtree based on env vars" + echo " --ignore tell git to ignore the cloned subtree" + echo " --unignore tell git to not ignore the cloned subtree" + + exit 1 +} + +check_env_vars_cvcore() { + if [ -z "${CV_CORE}" ]; then + echo "error: 'CV_CORE' not defined" + exit 1 + fi +} + +check_env_vars() { + check_env_vars_cvcore + + if [ -z "${VERIF_ENV_REPO}" ]; then + echo "error: 'VERIF_ENV_REPO' not defined" + exit 1 + fi + + if [ -z "${VERIF_ENV_REF}" ]; then + echo "error: 'VERIF_ENV_REF' not defined" + exit 1 + fi +} + +clone() { + check_env_vars + + rm -rf ${CV_CORE} + git clone ${VERIF_ENV_REPO} ${CV_CORE} + cd ${CV_CORE} && git checkout ${VERIF_ENV_REF} && cd - + +} + +clone_cv32e40x() { + CV_CORE=cv32e40x + VERIF_ENV_REPO=https://github.com/openhwgroup/cv32e40x-dv.git + VERIF_ENV_REF=443f11c + + clone + + ignore_cloned_directory +} + +ignore_cloned_directory() { + check_env_vars_cvcore + + # Add CV_CORE to git exclude + echo ${CV_CORE} >> .git/info/exclude + + # Set "skip-worktree" git flag + git ls-files ${CV_CORE} | xargs git update-index --skip-worktree +} + +unignore_cloned_directory() { + check_env_vars_cvcore + + # Delete CV_CORE from git exclude + sed -i "/^${CV_CORE}$/d" .git/info/exclude + + # Unset "skip-worktree" git flag + git ls-files -t | # Get git file status "tags" + grep '^S' | # Filter "skip-worktree" files + awk '{print $2}' | # Filter filename + xargs git update-index --no-skip-worktree +} + +main() { + case $1 in + "-x") + clone_cv32e40x + ;; + "--clone") + clone + ;; + "--ignore") + ignore_cloned_directory + ;; + "--unignore") + unignore_cloned_directory + ;; + *) + usage + ;; + esac +} + +main "$@" diff --git a/bin/csv2json b/bin/csv2json new file mode 100755 index 0000000000..883ec5fdce --- /dev/null +++ b/bin/csv2json @@ -0,0 +1,81 @@ +#!/usr/bin/env python3 + + +# Copyright 2023 Silicon Labs, Inc. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +# not use this file except in compliance with the License, or, at your option, +# the Apache License version 2.0. +# +# You may obtain a copy of the License at +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. + + +""" +Description: + Converts ".csv" vplans to ".json". + +Rationale: + It is an alternative to the ".csv" vplans, which in some cases might be + easier to review. + +Usage: + Run it on a ".csv" vplan. +""" + + +import csv +import json +import sys + + +# Check correct usage + +if len(sys.argv) != 2: + message = "usage: {} ".format(sys.argv[0]) + sys.exit(message) + + +# Read ".csv" + +csv_filename = sys.argv[1] +csv_file = open(csv_filename, 'r', encoding='utf-8') +csv_reader = csv.DictReader(csv_file) + + +# Fill empty cells (with value of above cell) + +csv_rows = [] +csv_row_previous = None + +def should_fill_cell(cell_value, previous_row, row_key): + cell_is_empty = not cell_value + previous_row_exists = previous_row + column_should_repeat = row_key in ['Feature', 'Verification Goal'] + return cell_is_empty and previous_row_exists and column_should_repeat + +for row in csv_reader: + for key, value in row.items(): + if should_fill_cell(value, csv_row_previous, key): + row[key] = csv_row_previous[key] + + csv_rows.append(row) + csv_row_previous = row + + +# Write ".json" + +json_string = json.dumps(csv_rows, indent = 4) +json_filename = csv_filename.replace(".csv", ".json") +json_file = open(json_filename, 'w', encoding='utf-8') + +json_file.write(json_string) diff --git a/bin/cv_regress b/bin/cv_regress index a2cd8dd5d1..4ecf7b388f 100755 --- a/bin/cv_regress +++ b/bin/cv_regress @@ -75,8 +75,12 @@ def get_filter_dir(): return os.path.abspath(os.path.join(os.path.dirname(__file__), 'vmgr')) def get_regress_path(project): - '''Fetch regression path using project''' - return os.path.abspath(os.path.join(get_project_path(project), 'regress')) + if args.rlp is None: + '''Fetch regression path using project''' + return os.path.abspath(os.path.join(get_project_path(project), 'regress')) + else: + '''Fetch regression path using override''' + return os.path.abspath(os.path.join(args.rlp)) def get_results_path(project): return os.path.abspath(os.path.join(get_project_path(project), 'sim', 'uvmt')) @@ -147,6 +151,8 @@ def read_file(args, file): test.sub_make(args.make) if args.iss != None: test.iss = args.iss + else: + args.iss = 'YES' if args.cfg: test.cfg = args.cfg if not test.builds and test.build: @@ -185,6 +191,7 @@ logger = logging.getLogger(__name__) parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter) parser.add_argument('-f', '--file', action='append', help='One or more input regression YAML lists to read') parser.add_argument('-p', '--project', '--core', default=DEFAULT_PROJECT, choices=VALID_PROJECTS, help='Select core for regression') +parser.add_argument('--rlp', default=None, help="Override path to regression test list") parser.add_argument('-o', '--outfile', help='Output file') parser.add_argument('-d', '--debug', help='Emit debug messages from logger', action='store_true') parser.add_argument('--results', help='Set a non-standard results directory') @@ -250,7 +257,8 @@ if args.sh: results=args.results, makeargs=' '.join(args.makearg) if args.makearg else '', session=os.path.splitext(os.path.basename(args.outfile))[0], - unique_builds=unique_builds)) + unique_builds=unique_builds, + iss=''.join(args.iss) if args.iss else '')) out_fh.close() os.chmod(args.outfile, 0o775) @@ -264,6 +272,7 @@ if args.metrics: cfg=args.cfg, toolchain=args.toolchain, makeargs=' '.join(args.makearg) if args.makearg else '', + iss=''.join(args.iss) if args.iss else '', unique_builds=unique_builds)) out_fh.close() os.chmod(args.outfile, 0o775) @@ -286,7 +295,8 @@ if args.vsif: toolchain=args.toolchain, simulator=args.simulator, filter_dir=get_filter_dir(), - unique_builds=unique_builds)) + unique_builds=unique_builds, + iss=''.join(args.iss) if args.iss else '')) out_fh.close() # Generate a Vmanager-compatible SVE diff --git a/bin/gen_csr_access_test.py b/bin/gen_csr_access_test.py new file mode 100644 index 0000000000..3601544ae0 --- /dev/null +++ b/bin/gen_csr_access_test.py @@ -0,0 +1,335 @@ +import sys +import os +import argparse +import subprocess +import yaml +import shlex + +if (sys.version_info < (3,5,0)): + print ('Requires python 3.5') + exit(1) + +supported_cores = ["cv32e40s", "cv32e40x"] + +try: + default_core = os.environ['CV_CORE'] +except KeyError: + default_core = 'None' + +topdir = os.path.abspath(os.path.join(os.path.dirname(os.path.realpath(__file__)), '..')) + + +# Parser arguments + +parser = argparse.ArgumentParser() + +parser.add_argument("--dry_run", help="Prints generated yaml to stdout", action="store_true") +parser.add_argument("--core", help="Set the core to generate test for", choices=supported_cores) +parser.add_argument("--output", help="Output path", type=str) +parser.add_argument("--iterations", help="Number of generated tests", type=str, default="1") +parser.add_argument("--m4", help="Use 'm4' for all preprocessing, and the m4 yaml file path unless another path is specified",\ +action="store_true", default=False) +parser.add_argument("--input_yaml_path", help="Optional: input yaml file path. If not specified: the m4 yaml or the default yaml file path is used",\ +type=str) + +parser.add_argument("--pmp_num_regions", help="Set number of Pmp regions", type=str, default="0") +parser.add_argument("--mhpmcounter_num", help="Set number of mhpmcounters", type=str, default="3") +parser.add_argument("--num_triggers", help="Set number of trigger registers", type=str, default="1") +parser.add_argument("--marchid", help="Set number for marchid", type=str, default="0") + +parser.add_argument("--clic_enable", help="Enable clic support", action="store_true", default=False) +parser.add_argument("--clint_enable", help="Enable Basic Interrupts", action="store_true", default=False) +parser.add_argument("--debug_enable", help="Enable Debug Registers", action="store_true", default=False) +parser.add_argument("--umode_enable", help="Enable Certain U-mode fields", action="store_true", default=False) +parser.add_argument("--xsecure_enable", help="Enable Xsecure Registers", action="store_true", default=False) +parser.add_argument("--zc_enable", help="Enable Zc support", action="store_true", default=False) +parser.add_argument("--zicntr_enable", help="Enable Zicntr", action="store_true", default=False) + +parser.add_argument("--a_ext_enable", help="Enable A extension", action="store_true", default=False) +parser.add_argument("--e_base_enable", help="Enable E base", action="store_true", default=False) +parser.add_argument("--e_ext_enable", help="Enable E base", action="store_true", default=False) +parser.add_argument("--f_ext_enable", help="Enable F extension", action="store_true", default=False) +parser.add_argument("--i_base_enable", help="Enable I base", action="store_true", default=False) +parser.add_argument("--i_ext_enable", help="Enable I base", action="store_true", default=False) +parser.add_argument("--m_ext_enable", help="Enable M extension", action="store_true", default=False) +parser.add_argument("--m_none_enable", help="Disable M extension", action="store_true", default=False) +parser.add_argument("--p_ext_enable", help="Enable P extension", action="store_true", default=False) +parser.add_argument("--v_ext_enable", help="Enable V extension", action="store_true", default=False) +parser.add_argument("--x_ext_enable", help="Enable X extension", action="store_true", default=False) + +args = parser.parse_args() + +if (args.core == None or args.core not in supported_cores): + parser.print_help() + print("Error: No supported '--core' specified") + exit(1) +if (args.output == None): + parser.print_help() + print("Error: no '--output' path specified") + exit(1) +if int(args.pmp_num_regions) not in range(65): + print("Error: unsupported number of pmp regions") + exit(1) + +if args.dry_run: + print('{}'.format(args)) + + +script_path = os.path.join(topdir, '{}/vendor_lib/google/riscv-dv/scripts/gen_csr_test.py'.format(args.core.lower())) +template_path = os.path.join(topdir, './bin/templates/csr_access_test_template.S') +output_yaml_path = "" + +if (args.input_yaml_path != None): + yaml_file_path = args.input_yaml_path +elif (args.m4): + yaml_file_path = os.path.join(topdir, 'core-v-cores/{}'.format(args.core.lower()) + '/yaml/csr.yaml.m4') +else: + yaml_file_path = os.path.join(topdir, '{}'.format(args.core.lower()) + '/env/corev-dv/{}'.format(args.core.lower()) + '_csr_template.yaml') + + +def run_riscv_dv_gen_csr_script(output_yaml_path): + try: + print("riscv-dv script path: {}".format(script_path)) + if (not os.path.isfile(script_path)): + print("error: script_path, no such file", file=sys.stderr) + exit(1) + + print("csr description used: {}".format(output_yaml_path)) + if (not os.path.isfile(output_yaml_path)): + print("error: csr description output_yaml_path doesn't exist", file=sys.stderr) + exit(1) + + script_args = { "csr_file" : ' --csr_file {}'.format(output_yaml_path), + "xlen" : ' --xlen 32', + "out" : ' --out ' + args.output, + "iterations" : ' --iterations ' + args.iterations} + subprocess.call(shlex.split("python3 " + script_path + script_args["csr_file"] + script_args["xlen"] + script_args["out"] + script_args["iterations"])) + except Exception as e: + print("error: exception in 'run_riscv_dv_gen_csr_script'") + print(e) + +def preprocess_yaml(): + input_script_path = yaml_file_path + w_enable = True + w_enable_n = w_enable + str_args = "" + enabled_features = { + "clic": False, + "clint": False, + "debug": False, + "e_base": False, + "i_base": False, + "m_ext": False, + "m_none": False, + "readonly": False, + "umode": False, + "a_ext": False, + "f_ext": False, + "p_ext": False, + "v_ext": False, + "x_ext": False, + "xsecure": False, + "zc": False, + "zicntr": False, + "marchid": 0, + "num_mhpmcounters": 0, + "pmp_num_regions": 0, + "dbg_num_triggers": 0, + } + + # CLIC + if (args.clic_enable): + str_args = str_args + "_clic" + enabled_features["clic"] = True + # CLINT + if (args.clint_enable or not args.clic_enable): + str_args = str_args + "_clint" + enabled_features["clint"] = True if not enabled_features["clic"] else False + # DEBUG + if (args.debug_enable): + str_args = str_args + "_debug" + enabled_features["debug"] = True + # I/E + if (args.i_base_enable or args.i_ext_enable): + str_args = str_args + "_i" + enabled_features["i_base"] = True + elif (args.e_base_enable or args.e_ext_enable): + str_args = str_args + "_e" + enabled_features["e_base"] = True + else: + print("error: need '--i_base_enable' or '--e_base_enable'", file=sys.stderr) + exit(1) + if (args.i_ext_enable or args.e_ext_enable): + print("warning: i and e are 'base' modules, not extensions", file=sys.stderr) + # M + if (args.m_ext_enable): + str_args = str_args + "_m" + enabled_features["m_ext"] = True + elif (args.m_none_enable): + str_args = str_args + "_mnone" + enabled_features["m_none"] = True + else: + print("error: need '--m_ext_enable' or '--m_none_enable'", file=sys.stderr) + exit(1) + # A_EXT + if (args.a_ext_enable): + str_args = str_args + "_a" + enabled_features["a_ext"] = True + # F_EXT + if (args.f_ext_enable): + str_args = str_args + "_f" + enabled_features["f_ext"] = True + # P_EXT + if (args.p_ext_enable): + str_args = str_args + "_p" + enabled_features["p_ext"] = True + # V_EXT + if (args.v_ext_enable): + str_args = str_args + "_v" + enabled_features["v_ext"] = True + # X_EXT + if (args.x_ext_enable): + str_args = str_args + "_x" + enabled_features["x_ext"] = True + # XSECURE + if (args.xsecure_enable): + str_args = str_args + "_xsecure" + enabled_features["xsecure"] = True + # UMODE + if (args.umode_enable): + str_args = str_args + "_umode" + enabled_features["umode"] = True + # ZC + if (args.zc_enable): + str_args = str_args + "_zc" + enabled_features["zc"] = True + # ZICNTR + if (args.zicntr_enable): + str_args = str_args + "_zicntr" + enabled_features["zicntr"] = True + # MARCHID + if (int(args.marchid) > 0): + str_args = str_args + "_marchid" + args.marchid + enabled_features["marchid"] = int(args.marchid) + # MHPMCOUNTERS + if (int(args.mhpmcounter_num) > 0): + str_args = str_args + "_mhpmctr" + args.mhpmcounter_num + enabled_features["num_mhpmcounters"] = int(args.mhpmcounter_num) + # PMP + if (int(args.pmp_num_regions) > 0): + str_args = str_args + "_pmp" + args.pmp_num_regions + enabled_features["pmp_num_regions"] = int(args.pmp_num_regions) + # TRIGGERS + if (int(args.num_triggers) > 0): + str_args = str_args + "_triggers" + args.num_triggers + enabled_features["dbg_num_triggers"] = int(args.num_triggers) + # TODO:silabs-robin Any other "enabled_features"? + + print("enabled_features: {}".format(enabled_features)) + + output_script_path = os.path.join(args.output) + "{}_csr_template.yaml".format(args.core.lower() + str_args) + if not args.dry_run: + output_script_handle = open(output_script_path, "w") + + # "m4" - Optionally used for all preprocessing + if (args.m4): + preprocess_yaml_m4(enabled_features, input_script_path, output_script_handle) + return output_script_path + + input_script_handle = open(input_script_path, "r") + input_script_lines = input_script_handle.readlines() + for line in input_script_lines: + input_list = line.split() + # Cond + if len(input_list) == 3 and input_list[0] == "###" and input_list[1].lower() == "cond": + if not enabled_features[input_list[2].lower()]: + w_enable = False + w_enable_n = False + # Cond + elif len(input_list) == 4 and input_list[0] == "###" and input_list[1].lower() == "cond": + if (int(input_list[3].lower()) > int(enabled_features[input_list[2].lower()])): + w_enable = False + w_enable_n = False + else: + w_enable_n = True + w_enable = True + # Endcond + elif len(input_list) == 2 and input_list[0] == "###" and input_list[1].lower() == "endcond": + w_enable_n = True + if w_enable == True: + if args.dry_run: + print(line.strip("\n")) + else: + output_script_handle.write(line) + if w_enable == False: + w_enable = w_enable_n + + if not args.dry_run: + output_script_handle.close() + input_script_handle.close() + return output_script_path + +def gen_riscv_dv_gen_csr_file(iteration = 1): + try: + template_handle = open(template_path, "r") + tlines = template_handle.readlines() + + file_handle = open(os.path.join(args.output) + "riscv_csr_test_{}.S".format(iteration), "r") + lines = file_handle.readlines() + file_handle.close() + + file_handle = open(os.path.join(args.output) + "riscv_csr_test_{}.S".format(iteration), "w") + write_next = 0 + twrite_next = 0 + for line in lines: + if write_next == 1 and line.strip("\n") != "csr_pass:": + file_handle.write(line) + elif line.strip("\n") == "_start:": + for tline in tlines: + if tline.strip("\n") != "_start0:": + file_handle.write(tline) + elif tline.strip("\n") == "_start0:": + file_handle.write(tline) + break + write_next = 1; + elif line.strip("\n") == "csr_pass:": + write_next = 0; + for tline in tlines: + if tline.strip("\n") == "_start0:" and twrite_next == 0: + twrite_next = 1 + elif twrite_next == 1: + file_handle.write(tline) + break + file_handle.close() + template_handle.close() + except Exception as e: + print("error: exception in 'gen_riscv_dv_gen_csr_file'") + print(e) + +def preprocess_yaml_m4(enabled_features, input_script_path, output_script_handle): + args_pre = ['m4', '-G', '-E'] # Turn off GNU extensions, promote warnings to errors + args_post = [input_script_path] + args_mid = [] + + # Set defines for the preprocessing + for key, val in enabled_features.items(): + dname = str(key).upper() + dval = str(int(val)) + args_mid.append('-D') + args_mid.append(dname + '=' + dval) + + # Run the preprocessing + args = args_pre + args_mid + args_post + print('running m4 as: ' + str(args)) # TODO:silabs-robin "if '--verbose'" + proc_results = subprocess.run(args, stdout=output_script_handle) + + if proc_results.returncode != 0: + print("error: m4 preproc returned error status", file=sys.stderr) + exit(1) + +if args.dry_run: + preprocess_yaml() +else: + run_riscv_dv_gen_csr_script(preprocess_yaml()) + for iteration in range(int(args.iterations)): + gen_riscv_dv_gen_csr_file(iteration) diff --git a/bin/merge.sh b/bin/merge.sh new file mode 100755 index 0000000000..7b13e19e4a --- /dev/null +++ b/bin/merge.sh @@ -0,0 +1,182 @@ +#!/bin/bash + +# Copyright 2023 Silicon Laboratories Inc. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +# not use this file except in compliance with the License, or, at your option, +# the Apache License version 2.0. +# +# You may obtain a copy of the License at +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. + + +#TODO: +#List up the PRs these changes are from (so it is easy to see what to include in the cv32e40s/dev to cv32e40x/dev merge) + +#Variables: +date_time=$(date +%Y.%m.%d-%H.%M) + + +usage() { + + echo "usage: $0 --[s_into_x-dv|x-dv_into_s|sdev_into_xdev|xdev_into_sdev]" + echo "--s_into_x-dv Do a merge of core-v-verif cv32e40s/dev cv32e40s directory into cv32e40x-dv main (make sure the clonetb script has run)" + echo "--x-dv_into_s Do a merge of cv32e40x-dv main into core-v-verif cv32e40s/dev cv32e40s (not yet developed)" + echo "--sdev_into_xdev Do a merge of core-v-verif cv32e40s/dev into core-v-verif cv32e40x/dev" + echo "--xdev_into_sdev Do a merge of core-v-verif cv32e40x/dev into core-v-verif cv32e40s/dev" + + exit 1 +} + + +merge_cv32e40s_into_cv32e40x-dv () { + + echo $'\n======= Merge of cv32e40s into cv32e40x-dv: =======\n' + + echo "=== Enter the cv32e40x-dv repo in cv32e40x subdirectory ===" + cd cv32e40x + + echo "=== Make a branch in cv32e40x-dv that contain core-v-verif's cv32e40s folder from the cv32e40s/dev branch ===" + git remote add ohw_cvv git@github.com:openhwgroup/core-v-verif.git + git fetch ohw_cvv + git checkout -b cvv_$date_time ohw_cvv/cv32e40s/dev + git subtree split --prefix cv32e40s -b cv32e40s_$date_time + + echo "=== Make a branch based on the latest cv32e40x-dv content ===" + git remote add ohw_x-dv git@github.com:openhwgroup/cv32e40x-dv.git + git fetch ohw_x-dv + git checkout -b merge_cv32e40s_$date_time ohw_x-dv/main + + echo "=== Merge ===" + git merge -X find-renames --no-ff --no-commit cv32e40s_$date_time + +} + + +move_files_40s_into_40x () { + + echo "=== Exchange 40x/X with 40s/S in file names ===" + + find . -type d | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | xargs -n1 dirname | awk '{gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 mkdir -p + find . -type d | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | awk '{printf $1; printf " "; gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 git mv + find . -type f | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | xargs -n1 dirname | awk '{gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 mkdir -p + find . -type f | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | awk '{printf $1; printf " "; gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 git mv + +} + + +substitute_file_content_40s_into_40x () { + + echo "=== Exchange 40x/X with 40s/S in file content ===" + + find . -type f -exec grep -Il . {} + | egrep -iv '\/\.|40sx|40xs' | xargs -n1 sed -i 's/40s/40x/g' + find . -type f -exec grep -Il . {} + | egrep -iv '\/\.|40sx|40xs' | xargs -n1 sed -i 's/40S/40X/g' + +} + + +merge_sdev_into_xdev () { + + echo $'\n======= Merge of core-v-verif cv32e40s/dev into cv32e40x/dev =======\n' + + echo "=== Download open hardware fork ===" + git remote add ohw_cvv git@github.com:openhwgroup/core-v-verif.git + git fetch ohw_cvv + + echo "=== Make a core-v-verif/cv32e40s/dev branch ===" + git checkout -b cvv_sdev_$date_time ohw_cvv/cv32e40s/dev + + echo "=== Make a core-v-verif/cv32e40x/dev branch ===" + git checkout -b cvv_xdev_$date_time ohw_cvv/cv32e40x/dev + + echo "=== Merge ===" + git merge --no-commit --no-ff cvv_sdev_$date_time + +} + + +merge_xdev_into_sdev () { + + echo $'\n======= Merge of core-v-verif cv32e40x/dev into cv32e40s/dev =======\n' + + echo "=== Download open hardware fork ===" + git remote add ohw_cvv git@github.com:openhwgroup/core-v-verif.git + git fetch ohw_cvv + + echo "=== Make a core-v-verif/cv32e40s/dev branch ===" + git checkout -b cvv_xdev_$date_time ohw_cvv/cv32e40x/dev + + echo "=== Make a core-v-verif/cv32e40s/dev branch ===" + git checkout -b cvv_sdev_$date_time ohw_cvv/cv32e40s/dev + + echo "=== Merge ===" + git merge --no-commit --no-ff cvv_xdev_$date_time + +} + + +check_cv32e40x_repo() { + + echo "=== Check if cv32e40x exist ===" + if [ ! -d "./cv32e40x/" ]; then + echo "Directory cv32e40x does not exists." + echo "Run: ./bin/clonetb -x" + echo "before running: ./bin/merge_script --s_into_x-dv" + exit 1 + fi + printf "OK\n\n" + + echo "=== Check if cv32e40x is the core-v-verif repo ===" + if [ ! -d "./cv32e40x/.git/" ]; then + echo "Directory cv32e40x is a 'core-v-verif' repo and not a 'cv32e40x-dv' repo." + echo "Run: ./bin/clonetb -x" + echo "before running: ./bin/merge_script --s_into_x-dv" + exit 1 + fi + printf "OK\n\n" + +} + + +check_merge_status() { + git status +} + + +main() { + case $1 in + "--s_into_x-dv") + check_cv32e40x_repo + merge_cv32e40s_into_cv32e40x-dv + move_files_40s_into_40x + substitute_file_content_40s_into_40x + check_merge_status + ;; + "--x-dv_into_s") + echo "This merge method is not yet developed" + ;; + "--sdev_into_xdev") + merge_sdev_into_xdev + check_merge_status + ;; + "--xdev_into_sdev") + merge_xdev_into_sdev + check_merge_status + ;; + *) + usage + ;; + esac +} + +main "$@" + diff --git a/bin/run_compliance.sh b/bin/run_compliance.sh index f0fb79ac67..ca9c1fbb8d 100755 --- a/bin/run_compliance.sh +++ b/bin/run_compliance.sh @@ -3,19 +3,19 @@ ############################################################################### # # Copyright 2020 OpenHW Group -# +# # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at -# +# # https://solderpad.org/licenses/ -# +# # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. -# +# # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 # ############################################################################### @@ -24,7 +24,7 @@ # Usage: # run_compliance RISCV_ISA # -# ENV: this script needs the following shell environment variables - +# ENV: this script needs the following shell environment variables - # SIM_DIR : cwd from which to run sims ############################################################################### @@ -32,114 +32,158 @@ cd ${SIM_DIR} # Script starts here if [ "$1" == "" ] ; then - echo "Please specify RISCV_ISA (rv32i|rv32im|rv32imc|rv32Zicsr|rv32Zifencei)" + echo "Please specify RISCV_DEVICE (I|M|C|privilege|Zifencei|Bitmanip)" exit 1 fi -if [ "$1" == "rv32i" ] || [ "$1" == "rv32im" ] || [ "$1" == "rv32imc" ] || [ "$1" == "rv32Zicsr" ] || [ "$1" == "rv32Zifencei" ] ; then - echo "nadda" +if [ "$1" == "I" ] || [ "$1" == "M" ] || [ "$1" == "C" ] || [ "$1" == "privilege" ] || [ "$1" == "Zifencei" ] || [ "$1" == "Bitmanip" ] ; then + echo "Running tests for $1" else - echo "Unknown RISCV_ISA. Please specify one of rv32i|rv32im|rv32imc|rv32Zicsr|rv32Zifencei" + echo "Unknown RISCV_DEVICE setting. Please specify one of I|M|C|privilege|Zifencei" exit 1 fi -if [ "$1" == "rv32Zicsr" ] ; then - make compliance RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRCI-01 - make compliance RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRW-01 - make compliance RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRSI-01 - make compliance RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRC-01 - make compliance RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRWI-01 - make compliance RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRS-01 +if [ "$1" == "Bitmanip" ]; then + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=andn-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bclr-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bclri-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bext-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bexti-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=binv-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=binvi-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bset-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bseti-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=clmul-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=clmulh-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=clmulr-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=clz-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cpop-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=ctz-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=max-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=maxu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=min-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=minu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=orc.b-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=orn-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=rev8-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=rol-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=ror-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=rori-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sext.b-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sext.h-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sh1add-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sh2add-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sh3add-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=xnor-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=zext.h-01 +fi + +if [ "$1" == "Zifencei" ]; then + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=Fencei fi -if [ "$1" == "rv32Zifencei" ]; then - make compliance RISCV_ISA=rv32Zifencei COMPLIANCE_PROG=I-FENCE.I-01 +if [ "$1" == "M" ]; then + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=div-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=divu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=mul-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=mulh-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=mulhsu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=mulhu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=rem-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=remu-01 fi -if [ "$1" == "rv32im" ]; then - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=DIV - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=MULHU - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=REMU - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=MULH - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=MULHSU - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=DIVU - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=REM - make compliance RISCV_ISA=rv32im COMPLIANCE_PROG=MUL +if [ "$1" == "I" ]; then + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=add-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=addi-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=and-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=andi-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=auipc-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=beq-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bge-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bgeu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=blt-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bltu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=bne-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=fence-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=jal-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=jalr-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=lb-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=lbu-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=lh-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=lhu-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=lui-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=lw-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=or-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=ori-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sb-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sh-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sll-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=slli-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=slt-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=slti-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sltiu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sltu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sra-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=srai-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=srl-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=srli-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sub-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=sw-align-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=xor-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=xori-01 fi -if [ "$1" == "rv32i" ]; then - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-LB-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SUB-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRAI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ADDI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-BEQ-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SW-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-RF_size-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-LHU-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLL-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLTU-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-JALR-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SH-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-BNE-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-LW-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-LH-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-BGE-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLTI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-BGEU-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ANDI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRL-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-XORI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ENDIANESS-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLT-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-LBU-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-RF_width-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ORI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-AND-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-LUI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-BLT-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-NOP-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-XOR-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-AUIPC-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-RF_x0-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLTIU-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-IO-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRLI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SB-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLLI-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-BLTU-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRA-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-JAL-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ADD-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-DELAY_SLOTS-01 - make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-OR-01 +if [ "$1" == "C" ]; then + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cadd-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=caddi-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=caddi16sp-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=caddi4spn-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cand-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=candi-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cbeqz-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cbnez-01 + # Waivable - mtvec not fully writable in cv32e40* + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cebreak-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cj-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cjal-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cjalr-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cjr-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cli-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=clui-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=clw-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=clwsp-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cmv-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cnop-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cor-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cslli-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=csrai-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=csrli-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=csub-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=csw-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cswsp-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=cxor-01 fi -if [ "$1" == "rv32imc" ]; then - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SUB - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADD - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SRLI - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-BEQZ - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-J - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-JR - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SWSP - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LW - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADDI4SPN - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-OR - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-BNEZ - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LWSP - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADDI - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADDI16SP - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SW - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-AND - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SRAI - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ANDI - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LI - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-JALR - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LUI - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SLLI - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-XOR - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-MV - make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=C-JAL +if [ "$1" == "privilege" ]; then + # Waivable - mtvec not fully writable in cv32e40* + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=ebreak + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=ecall + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign1-jalr-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign2-jalr-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-beq-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-bge-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-bgeu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-blt-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-bltu-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-bne-01 + make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-jal-01 + # Waiable - below will fail for targets with hardware support for misaligned load/store + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-lh-01 + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-lhu-01 + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-lw-01 + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-sh-01 + #make compliance RISCV_ISA=rv32i_m COMPLIANCE_PROG=misalign-sw-01 fi exit 0 diff --git a/bin/templates/csr_access_test_template.S b/bin/templates/csr_access_test_template.S new file mode 100644 index 0000000000..9834f259c7 --- /dev/null +++ b/bin/templates/csr_access_test_template.S @@ -0,0 +1,92 @@ +# CSR access test +# Generated by gen_csr_test.py (part of riscv-dv) +# Manual edits to fit with BSP and enhance debug + +#include "user_define.h" +.section .text.start +.globl _start +.type _start, @function + +_start: + j _start_main + +.globl _start_main +.section .text +_start_main: + +############################################################################### +# +# Generated code starts... +# +############################################################################### +_start0: +################################################################################ +# +# Generated code ends... +# +################################################################################ +test_done: + lui a0,print_port>>12 + addi a1,zero,'\n' + sw a1,0(a0) + addi a1,zero,'C' + sw a1,0(a0) + addi a1,zero,'V' + sw a1,0(a0) + addi a1,zero,'3' + sw a1,0(a0) + addi a1,zero,'2' + sw a1,0(a0) + addi a1,zero,' ' + sw a1,0(a0) + addi a1,zero,'D' + sw a1,0(a0) + addi a1,zero,'O' + sw a1,0(a0) + addi a1,zero,'N' + sw a1,0(a0) + addi a1,zero,'E' + sw a1,0(a0) + addi a1,zero,'\n' + sw a1,0(a0) + sw a1,0(a0) + +csr_pass: + li x18, 123456789 + li x17, CV_VP_STATUS_FLAGS_BASE + sw x18,0(x17) + wfi + +csr_fail: + lui a0,print_port>>12 + addi a1,zero,'\n' + sw a1,0(a0) + addi a1,zero,'C' + sw a1,0(a0) + addi a1,zero,'V' + sw a1,0(a0) + addi a1,zero,'3' + sw a1,0(a0) + addi a1,zero,'2' + sw a1,0(a0) + addi a1,zero,' ' + sw a1,0(a0) + addi a1,zero,'F' + sw a1,0(a0) + addi a1,zero,'A' + sw a1,0(a0) + addi a1,zero,'I' + sw a1,0(a0) + addi a1,zero,'L' + sw a1,0(a0) + addi a1,zero,'\n' + sw a1,0(a0) + sw a1,0(a0) + + li x18, 1 + li x17, CV_VP_STATUS_FLAGS_BASE + sw x18,0(x17) + wfi +# +# end +# diff --git a/bin/templates/regress_sh.j2 b/bin/templates/regress_sh.j2 index ff23ceaf0b..179ead01f1 100644 --- a/bin/templates/regress_sh.j2 +++ b/bin/templates/regress_sh.j2 @@ -62,7 +62,7 @@ incr_test_counts () { {% for b in unique_builds.values() %} # Build:{{b.name}} {{b.description}} -{% set cmd = b.cmd + ' CV_CORE=' + project + ' CFG=' + b.cfg + ' SIMULATOR=' + b.simulator + ' COV=' + regress_macros.yesorno(b.cov) + ' ' + regress_macros.cv_results(results) + ' ' + makeargs %} +{% set cmd = b.cmd + ' CV_CORE=' + project + ' CFG=' + b.cfg + ' SIMULATOR=' + b.simulator + ' USE_ISS=' + regress_macros.yesorno(iss) + ' COV=' + regress_macros.yesorno(b.cov) + ' ' + regress_macros.cv_results(results) + ' ' + makeargs %} echo "{{session}}: Running build: [cd {{b.abs_dir}} && {{cmd}}]" pushd {{b.abs_dir}} > /dev/null {{cmd}} @@ -80,7 +80,7 @@ popd > /dev/null # --> Test: {{t.name}} : Build: {{build}} : {{t.description}} {% if t.precmd %} # Test (Precommand): {{t.name}} {{t.description}} -{% set cmd = t.precmd + ' CV_CORE=' + project + 'CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1' + ' SIMULATOR=' + t.simulator + ' SEED=random GEN_NUM_TESTS=' + t.num + ' ' + regress_macros.cv_results(results) + ' ' + makeargs + ' ' + t.makearg %} +{% set cmd = t.precmd + ' CV_CORE=' + project + 'CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1' + ' SIMULATOR=' + t.simulator + ' USE_ISS=' + regress_macros.yesorno(t.iss) + ' SEED=random GEN_NUM_TESTS=' + t.num + ' ' + regress_macros.cv_results(results) + ' ' + makeargs + ' ' + t.makearg %} echo "{{session}}: Running precmd: [cd {{t.abs_dir}} && {{cmd}}] pushd {{t.abs_dir}} > /dev/null {{cmd}} >& /dev/null; diff --git a/bin/templates/regress_vsif.j2 b/bin/templates/regress_vsif.j2 index 5dce750ae4..ebccd7fc88 100644 --- a/bin/templates/regress_vsif.j2 +++ b/bin/templates/regress_vsif.j2 @@ -53,7 +53,7 @@ group {{project}} { group {{build.name}} { // Build:{{build.name}} {{build.description}} - pre_group_script: 'cd {{build.abs_dir}} && {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} CV_SIM_PREFIX= {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results)}} {{makeargs}}'; + pre_group_script: 'cd {{build.abs_dir}} && {{build.cmd}} CV_CORE={{project}} CFG={{build.cfg}} CV_SIM_PREFIX= {{toolchain|upper}}=1 SIMULATOR={{build.simulator}} USE_ISS={{regress_macros.yesorno(iss)}} COV={{regress_macros.yesorno(build.cov)}} {{regress_macros.cv_results(results)}} {{makeargs}}'; {% for t in r.get_tests_of_build(build.name) %} {% set indent = ' '%} @@ -64,7 +64,7 @@ group {{project}} { test precmd { sv_seed: gen_random; count: 1; - run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}'; + run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} USE_ISS={{regress_macros.yesorno(t.iss)}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}'; }; {% else %} {% endif %} @@ -73,7 +73,7 @@ group {{project}} { {% if t.precmd %} {{indent}} depends_on: ../precmd; {% endif %} -{{indent}} timeout: 3600; +{{indent}} timeout: 7200; {{indent}} test run { {{indent}} sv_seed: gen_random; {{indent}} count: {{t.num}}; diff --git a/bin/xlsx2csv b/bin/xlsx2csv new file mode 100755 index 0000000000..3a091a4930 --- /dev/null +++ b/bin/xlsx2csv @@ -0,0 +1,74 @@ +#!/usr/bin/env python3 + + +# Copyright 2023 Silicon Labs, Inc. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +# not use this file except in compliance with the License, or, at your option, +# the Apache License version 2.0. +# +# You may obtain a copy of the License at +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. + + +""" +Description: + Converts ".xlsx" to ".csv". + +Rationale: + We have vplans in ".xlsx" but that is a binary format where you can't see + diffs when committing changes. + Because of localization quirks (e.g. system-wide semicolon delimiter, etc), + a script is more reliable than conversion via gui. + +Usage: + Run it on an ".xlsx" vplan. +""" + + +import csv +import os.path +import sys +from openpyxl import load_workbook + + +# Check correct usage + +if len(sys.argv) != 2: + sys.exit("usage: {prog} ".format(prog=sys.argv[0])) + + +# Read ".xlsx" + +xlsx_filename = sys.argv[1] + +if not os.path.isfile(xlsx_filename): + sys.exit("error: file '{filename}' doesn't exist".format(filename=xlsx_filename)) + +xlsx_book = load_workbook(filename = xlsx_filename) +xlsx_sheet = xlsx_book.worksheets[0] + + +# Write ".csv" + +csv_filename = xlsx_filename.replace(".xlsx", ".csv") +csv_file = open(csv_filename, 'w', encoding='utf-8') +csv_writer = csv.writer(csv_file) + +for xlsx_row in xlsx_sheet.values: + csv_row = [] + + for xlsx_cell in xlsx_row: + csv_cell = str(xlsx_cell or '') + csv_row.append(csv_cell) + + csv_writer.writerow(csv_row) diff --git a/cv32e40p/sim/ExternalRepos.mk b/cv32e40p/sim/ExternalRepos.mk index 503bf9135a..3a23ef707d 100644 --- a/cv32e40p/sim/ExternalRepos.mk +++ b/cv32e40p/sim/ExternalRepos.mk @@ -31,10 +31,13 @@ EMBENCH_REPO ?= https://github.com/embench/embench-iot.git EMBENCH_BRANCH ?= master EMBENCH_HASH ?= 6934ddd1ff445245ee032d4258fdeb9828b72af4 -COMPLIANCE_REPO ?= https://github.com/riscv/riscv-compliance -COMPLIANCE_BRANCH ?= master -# 2020-08-19 -COMPLIANCE_HASH ?= c21a2e86afa3f7d4292a2dd26b759f3f29cde497 +# TODO: silabs-hfegran: Temporary fork compliance suite to support bitmanip and +# new repository structure. Revert back to latest mainline when bitmanip PR has +# been approved and local changes upstreamed. +# 2022-02-21 +COMPLIANCE_REPO ?= https://github.com/silabs-hfegran/riscv-arch-test.git +COMPLIANCE_BRANCH ?= dev_hf_riscv_arch_test +COMPLIANCE_HASH ?= 43556e3ae4e98d5e739204f37a11769e14154b7e # This Spike repo is only cloned when the DPI disassembler needs to be rebuilt. # Typically users can simply use the checked-in shared library. diff --git a/cv32e40s/README.md b/cv32e40s/README.md index 3029b8392d..d96ea0a7c1 100644 --- a/cv32e40s/README.md +++ b/cv32e40s/README.md @@ -4,6 +4,7 @@ - **bsp**: the "board support package" for test-programs compiled/assembled/linked for the CV32E40S. This BSP is used by both the `core` testbench and the `uvmt` UVM verification environment. - **env**: the UVM environment class and its associated infrastrucutre. - **sim**: directory where you run the simulations. +- **fv**: directory where you run formal verification. - **tb**: the Testbench module that instanitates the core. - **tests**: this is where all the testcases are. diff --git a/cv32e40s/bsp/Makefile b/cv32e40s/bsp/Makefile index a0e37bb77a..b34ad75cea 100644 --- a/cv32e40s/bsp/Makefile +++ b/cv32e40s/bsp/Makefile @@ -4,11 +4,11 @@ RISCV_EXE_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf- RISCV_CC ?= gcc RISCV_GCC = $(RISCV_EXE_PREFIX)$(RISCV_CC) RISCV_AR = $(RISCV_EXE_PREFIX)ar -RISCV_MARCH ?= rv32imc +RISCV_MARCH ?= rv32im_zca SRC = crt0.S handlers.S syscalls.c vectors.S OBJ = crt0.o handlers.o syscalls.o vectors.o LIBCV-VERIF = libcv-verif.a -CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(RISCV_MARCH) -Wall -pedantic $(RISCV_CFLAGS) +CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(RISCV_MARCH) -Wall -pedantic -mno-relax $(RISCV_CFLAGS) all: $(LIBCV-VERIF) diff --git a/cv32e40s/bsp/bsp.h b/cv32e40s/bsp/bsp.h new file mode 100644 index 0000000000..5014d8dffd --- /dev/null +++ b/cv32e40s/bsp/bsp.h @@ -0,0 +1,55 @@ +// Copyright 2022 Silicon Laboratories Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you +// may not use this file except in compliance with the License, or, at your +// option, the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +enum { + EXC_CAUSE_INSTR_ACC_FAULT = 1, + EXC_CAUSE_ILLEGAL_INSTR = 2, + EXC_CAUSE_BREAKPOINT = 3, + EXC_CAUSE_LOAD_ACC_FAULT = 5, + EXC_CAUSE_STORE_ACC_FAULT = 7, + EXC_CAUSE_ENV_CALL_U = 8, + EXC_CAUSE_ENV_CALL_M = 11, + EXC_CAUSE_INSTR_BUS_FAULT = 24, + EXC_CAUSE_INSTR_INTEGRITY_FAULT = 25, +}; + +typedef union { + struct { + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_5_5 : 1; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t chain : 1; + volatile uint32_t action : 4; + volatile uint32_t size : 4; + volatile uint32_t timing : 1; + volatile uint32_t select : 1; + volatile uint32_t hit : 1; + volatile uint32_t vu : 1; + volatile uint32_t vs : 1; + volatile uint32_t res_26_25: 2; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mcontrol6_t; diff --git a/cv32e40s/bsp/corev_uvmt.h b/cv32e40s/bsp/corev_uvmt.h index 30e460bb5a..d7022b3ca7 100644 --- a/cv32e40s/bsp/corev_uvmt.h +++ b/cv32e40s/bsp/corev_uvmt.h @@ -62,12 +62,13 @@ #define CV_VP_OBI_SLV_RESP_D_EXOKAY_ADDR_MAX ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*4)) #define CV_VP_OBI_SLV_RESP_D_EXOKAY_VALID ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*5)) -// Bitfields for Debug Control VP register +// API for Debug Control VP register #define CV_VP_DEBUG_CONTROL_DBG_REQ(i) ((i) << 31) #define CV_VP_DEBUG_CONTROL_REQ_MODE(i) ((i) << 30) #define CV_VP_DEBUG_CONTROL_RAND_PULSE_DURATION(i) ((i) << 29) #define CV_VP_DEBUG_CONTROL_PULSE_DURATION(i) ((i) << 16) #define CV_VP_DEBUG_CONTROL_RAND_START_DELAY(i) ((i) << 15) #define CV_VP_DEBUG_CONTROL_START_DELAY(i) ((i) << 0) +#define CV_VP_DEBUG_CONTROL *((volatile uint32_t * volatile) (CV_VP_DEBUG_CONTROL_BASE)) #endif diff --git a/cv32e40s/bsp/crt0.S b/cv32e40s/bsp/crt0.S index b0ee48373d..5bb71d449f 100644 --- a/cv32e40s/bsp/crt0.S +++ b/cv32e40s/bsp/crt0.S @@ -1,5 +1,6 @@ /* Copyright (c) 2017 SiFive Inc. All rights reserved. * Copyright (c) 2019 ETH Zürich and University of Bologna + * Copyright (c) 2023 Silicon Laboratories Inc. * This copyrighted material is made available to anyone wishing to use, * modify, copy, or redistribute it subject to the terms and conditions * of the FreeBSD License. This program is distributed in the hope that @@ -23,45 +24,51 @@ _start: /* initialize global pointer */ .option push .option norelax -1: auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) +1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + +/* initialize vector table pointer */ +1:auipc a0, %pcrel_hi(__jvt_base$) + addi a0, a0, %pcrel_lo(1b) + csrw jvt, a0 .option pop /* initialize stack pointer */ - la sp, __stack_end + la sp, __stack_start /* set vector table address */ - la a0, __vector_start - ori a0, a0, 1 /*vector mode = vectored */ - csrw mtvec, a0 + la a0, __vector_start + ori a0, a0, 1 /*vector mode = vectored */ + csrw mtvec, a0 /* clear the bss segment */ - la a0, _edata - la a2, _end - sub a2, a2, a0 - li a1, 0 - call memset + la a0, _edata + la a2, _end + sub a2, a2, a0 + li a1, 0 + call memset /* new-style constructors and destructors */ - la a0, __libc_fini_array - call atexit - call __libc_init_array + la a0, __libc_fini_array + call atexit + call __libc_init_array /* call main */ -// lw a0, 0(sp) /* a0 = argc */ -// addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ -// li a2, 0 /* a2 = envp = NULL */ +// lw a0, 0(sp) /* a0 = argc */ +// addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ +// li a2, 0 /* a2 = envp = NULL */ // Initialize these variables to 0. Cannot use argc or argv // since the stack is not initialized - li a0, 0 - li a1, 0 - li a2, 0 + li a0, 0 + li a1, 0 + li a2, 0 - call main - tail exit + call main + tail exit .size _start, .-_start + .global _init .type _init, @function .global _fini @@ -70,6 +77,6 @@ _init: _fini: /* These don't have to do anything since we use init_array/fini_array. Prevent missing symbol error */ - ret + ret .size _init, .-_init .size _fini, .-_fini diff --git a/cv32e40s/bsp/handlers.S b/cv32e40s/bsp/handlers.S index 99eedafd6b..6a0891542d 100644 --- a/cv32e40s/bsp/handlers.S +++ b/cv32e40s/bsp/handlers.S @@ -21,11 +21,12 @@ #define EXCEPTION_LOAD_ACCESS_FAULT 5 #define EXCEPTION_STORE_ACCESS_FAULT 7 #define EXCEPTION_ECALL_M 11 -#define EXCEPTION_INSN_BUS_FAULT 48 +#define EXCEPTION_ECALL_U 8 +#define EXCEPTION_INSN_BUS_FAULT 24 /* NMI interrupt codes */ -#define INTERRUPT_LOAD_BUS_FAULT (128 | (0x1 << 31)) -#define INTERRUPT_STORE_BUS_FAULT (129 | (0x1 << 31)) +#define INTERRUPT_LOAD_BUS_FAULT (1024 | (0x1 << 31)) +#define INTERRUPT_STORE_BUS_FAULT (1025 | (0x1 << 31)) .section .text.handlers .global __no_irq_handler @@ -49,6 +50,7 @@ .global m_fast13_irq_handler .global m_fast14_irq_handler .global m_fast15_irq_handler +.global end_handler_incr_mepc .global end_handler_ret .weak __no_irq_handler @@ -73,169 +75,191 @@ .weak m_fast14_irq_handler .weak m_fast15_irq_handler +.weak handle_illegal_insn .weak handle_insn_access_fault .weak handle_insn_bus_fault +.weak handle_ecall +.weak handle_ecall_u /* exception handling */ __no_irq_handler: - la a0, no_exception_handler_msg - jal ra, puts - j __no_irq_handler + la a0, no_exception_handler_msg + jal ra, puts + j __no_irq_handler m_software_irq_handler: - j __no_irq_handler + j __no_irq_handler m_timer_irq_handler: - j __no_irq_handler + j __no_irq_handler m_external_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast0_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast1_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast2_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast3_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast4_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast5_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast6_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast7_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast8_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast9_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast10_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast11_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast12_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast13_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast14_irq_handler: - j __no_irq_handler + j __no_irq_handler m_fast15_irq_handler: - j __no_irq_handler + j __no_irq_handler u_sw_irq_handler: - /* While we are still using puts in handlers, save all caller saved - regs. Eventually, some of these saves could be deferred. */ - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr t0, mcause - li t1, EXCEPTION_INSN_ACCESS_FAULT - beq t0, t1, handle_insn_access_fault - li t1, EXCEPTION_ILLEGAL_INSN - beq t0, t1, handle_illegal_insn - li t1, EXCEPTION_ECALL_M - beq t0, t1, handle_ecall - li t1, EXCEPTION_BREAKPOINT - beq t0, t1, handle_ebreak - li t1, EXCEPTION_INSN_BUS_FAULT - beq t0, t1, handle_insn_bus_fault - j handle_unknown + /* While we are still using puts in handlers, save all caller saved + regs. Eventually, some of these saves could be deferred. */ + addi sp,sp,-64 + sw ra, 0(sp) + sw a0, 4(sp) + sw a1, 8(sp) + sw a2, 12(sp) + sw a3, 16(sp) + sw a4, 20(sp) + sw a5, 24(sp) + sw a6, 28(sp) + sw a7, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + csrr t0, mtvec + # Check for clic + andi t0, t0, 0x3 + addi t1, zero, 0x3 + # non-clic jump + bne t0, t1, 1f + # clic section (Filter out upper bits, mpp etc.) + csrr t0, mcause + lui t1, 0x1 + addi t1, t1, -1 + and t0, t1, t0 + j 2f + + 1: csrr t0, mcause + 2: li t1, EXCEPTION_INSN_ACCESS_FAULT + beq t0, t1, handle_insn_access_fault + li t1, EXCEPTION_ILLEGAL_INSN + beq t0, t1, handle_illegal_insn + li t1, EXCEPTION_ECALL_M + beq t0, t1, handle_ecall + li t1, EXCEPTION_ECALL_U + beq t0, t1, handle_ecall_u + li t1, EXCEPTION_BREAKPOINT + beq t0, t1, handle_ebreak + li t1, EXCEPTION_INSN_BUS_FAULT + beq t0, t1, handle_insn_bus_fault + j handle_unknown handle_ecall: - jal ra, handle_syscall - j end_handler_incr_mepc + jal ra, handle_syscall + j end_handler_incr_mepc + +handle_ecall_u: + jal ra, handle_syscall + j end_handler_incr_mepc handle_ebreak: - /* TODO support debug handling requirements. */ - la a0, ebreak_msg - jal ra, puts - j end_handler_incr_mepc + /* TODO support debug handling requirements. */ + la a0, ebreak_msg + jal ra, puts + j end_handler_incr_mepc handle_illegal_insn: - la a0, illegal_insn_msg - jal ra, puts - j end_handler_incr_mepc + la a0, illegal_insn_msg + jal ra, puts + j end_handler_incr_mepc handle_insn_access_fault: - la a0, insn_access_fault_msg - jal ra, puts - j end_handler_incr_mepc + la a0, insn_access_fault_msg + jal ra, puts + j end_handler_incr_mepc handle_insn_bus_fault: - la a0, insn_bus_fault_msg - jal ra, puts - /* Do not advnace the mepc, tests should handle this appropriately */ - j end_handler_ret + la a0, insn_bus_fault_msg + jal ra, puts + /* Do not advnace the mepc, tests should handle this appropriately */ + j end_handler_ret handle_unknown: - la a0, unknown_msg - jal ra, puts - /* We don't know what interrupt/exception is being handled, so don't - increment mepc. */ - j end_handler_ret + la a0, unknown_msg + jal ra, puts + /* We don't know what interrupt/exception is being handled, so don't + increment mepc. */ + j end_handler_ret end_handler_incr_mepc: - csrr t0, mepc - lb t1, 0(t0) - li a0, 0x3 - and t1, t1, a0 - /* Increment mepc by 2 or 4 depending on whether the instruction at mepc - is compressed or not. */ - bne t1, a0, end_handler_incr_mepc2 - addi t0, t0, 2 + csrr t0, mepc + lb t1, 0(t0) + li a0, 0x3 + and t1, t1, a0 + /* Increment mepc by 2 or 4 depending on whether the instruction at mepc + is compressed or not. */ + bne t1, a0, end_handler_incr_mepc2 + addi t0, t0, 2 end_handler_incr_mepc2: - addi t0, t0, 2 - csrw mepc, t0 + addi t0, t0, 2 + csrw mepc, t0 end_handler_ret: - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret + lw ra, 0(sp) + lw a0, 4(sp) + lw a1, 8(sp) + lw a2, 12(sp) + lw a3, 16(sp) + lw a4, 20(sp) + lw a5, 24(sp) + lw a6, 28(sp) + lw a7, 32(sp) + lw t0, 36(sp) + lw t1, 40(sp) + lw t2, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + addi sp,sp,64 + mret .weak handle_data_load_bus_fault .weak handle_data_store_bus_fault @@ -245,77 +269,77 @@ end_handler_ret: .global nmi_end_handler_ret nmi_handler: - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr t0, mcause - li t1, INTERRUPT_LOAD_BUS_FAULT - beq t0, t1, handle_data_load_bus_fault - li t1, INTERRUPT_STORE_BUS_FAULT - beq t0, t1, handle_data_store_bus_fault - - j nmi_end_handler_ret + addi sp,sp,-64 + sw ra, 0(sp) + sw a0, 4(sp) + sw a1, 8(sp) + sw a2, 12(sp) + sw a3, 16(sp) + sw a4, 20(sp) + sw a5, 24(sp) + sw a6, 28(sp) + sw a7, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + csrr t0, mcause + li t1, INTERRUPT_LOAD_BUS_FAULT + beq t0, t1, handle_data_load_bus_fault + li t1, INTERRUPT_STORE_BUS_FAULT + beq t0, t1, handle_data_store_bus_fault + + j nmi_end_handler_ret handle_data_load_bus_fault: - la a0, data_load_bus_fault_msg - jal ra, puts - j nmi_end_handler_ret + la a0, data_load_bus_fault_msg + jal ra, puts + j nmi_end_handler_ret handle_data_store_bus_fault: - la a0, data_store_bus_fault_msg - jal ra, puts - j nmi_end_handler_ret + la a0, data_store_bus_fault_msg + jal ra, puts + j nmi_end_handler_ret nmi_end_handler_ret: - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret + lw ra, 0(sp) + lw a0, 4(sp) + lw a1, 8(sp) + lw a2, 12(sp) + lw a3, 16(sp) + lw a4, 20(sp) + lw a5, 24(sp) + lw a6, 28(sp) + lw a7, 32(sp) + lw t0, 36(sp) + lw t1, 40(sp) + lw t2, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + addi sp,sp,64 + mret .section .rodata data_load_bus_fault_msg: - .string "CV32E40S BSP: data load bus fault exception handler entered\n" + .string "CV32E40S BSP: data load bus fault exception handler entered\n" data_store_bus_fault_msg: - .string "CV32E40S BSP: data store bus fault exception handler entered\n" + .string "CV32E40S BSP: data store bus fault exception handler entered\n" insn_access_fault_msg: - .string "CV32E40S BSP: instruction access fault exception handler entered\n" + .string "CV32E40S BSP: instruction access fault exception handler entered\n" insn_bus_fault_msg: - .string "CV32E40S BSP: instruction bus fault exception handler entered\n" + .string "CV32E40S BSP: instruction bus fault exception handler entered\n" illegal_insn_msg: - .string "CV32E40S BSP: illegal instruction exception handler entered\n" + .string "CV32E40S BSP: illegal instruction exception handler entered\n" ecall_msg: - .string "CV32E40S BSP: ecall exception handler entered\n" + .string "CV32E40S BSP: ecall exception handler entered\n" ebreak_msg: - .string "CV32E40S BSP: ebreak exception handler entered\n" + .string "CV32E40S BSP: ebreak exception handler entered\n" unknown_msg: - .string "CV32E40S BSP: unknown exception handler entered\n" + .string "CV32E40S BSP: unknown exception handler entered\n" no_exception_handler_msg: - .string "CV32E40S BSP: no exception handler installed\n" + .string "CV32E40S BSP: no exception handler installed\n" diff --git a/cv32e40s/bsp/link.ld b/cv32e40s/bsp/link.ld index e765bf77bb..cc1d569470 100644 --- a/cv32e40s/bsp/link.ld +++ b/cv32e40s/bsp/link.ld @@ -11,18 +11,18 @@ */ OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", - "elf32-littleriscv") + "elf32-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) /* CORE-V */ MEMORY { - /* Our testbench is a bit weird in that we initialize the RAM (thus - allowing initialized sections to be placed there). Infact we dump all - sections to ram. */ + /* Our testbench is a bit weird in that we initialize the RAM (thus + allowing initialized sections to be placed there). Infact we dump all + sections to ram. */ - ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 + ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000 } @@ -32,28 +32,20 @@ SECTIONS DM_HaltAddress parameter in the RTL */ .debugger (ORIGIN(dbg)): { + PROVIDE(_debugger_start = .); KEEP(*(.debugger)); } >dbg .debugger_exception (0x1A111000): { + PROVIDE(_debugger_exception = .); KEEP(*(.debugger_exception)); } >dbg /* Debugger Stack*/ .debugger_stack : ALIGN(16) { - PROVIDE(__debugger_stack_start = .); - . = 0x80; + PROVIDE(__debugger_stack_start = ALIGN(ORIGIN(dbg) + LENGTH(dbg) - 15, 16)); } >dbg - - /* NMI interrupt handler fixed entry point */ - PROVIDE(__nmi_address = 0x100000); - - .nmi (__nmi_address): - { - KEEP(*(.nmi)); - } >ram - /* CORE-V: we want a fixed entry point */ PROVIDE(__boot_address = 0x80); @@ -113,6 +105,9 @@ SECTIONS .iplt : { *(.iplt) } .text : { + /* FIXME: the naming for text.tbljal will most likely change and move out of .text */ + . = ALIGN(1024); + *(.text.tbljal) *(.text.unlikely .text.*_unlikely .text.unlikely.*) *(.text.exit .text.exit.*) *(.text.startup .text.startup.*) @@ -151,12 +146,12 @@ SECTIONS .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >ram .exception_ranges : ONLY_IF_RW { *(.exception_ranges*) } >ram /* Thread Local Storage sections */ - .tdata : + .tdata : { PROVIDE_HIDDEN (__tdata_start = .); *(.tdata .tdata.* .gnu.linkonce.td.*) } >ram - .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -252,8 +247,8 @@ SECTIONS . = SEGMENT_START("ldata-segment", .); . = ALIGN(32 / 8); __bss_end = .; - __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, - MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800)); + __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, + MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800)); _end = .; PROVIDE (end = .); . = DATA_SEGMENT_END (.); @@ -263,16 +258,15 @@ SECTIONS PROVIDE(__heap_start = .); /* If end of ram is not 16-byte aligned, align to previous 16-byte boundary */ - PROVIDE(__heap_end = ALIGN(ORIGIN(ram) + LENGTH(ram) - __heap_start - 15, 16)); + PROVIDE(__heap_end = ALIGN(ORIGIN(ram) + LENGTH(ram) - 15, 16)); . = __heap_end; } >ram /* Stack grows downward from end of ram */ - .stack (__heap_start) : ALIGN(16) /* this is a requirement of the ABI(?) */ + .stack (__heap_end) : ALIGN(16) /* this is a requirement of the ABI(?) */ { - PROVIDE(__stack_start = __heap_start); - . = __heap_end; - PROVIDE(__stack_end = .); + PROVIDE(__stack_start = __heap_end); + . = __stack_start; } >ram diff --git a/cv32e40s/bsp/link_corev-dv.ld b/cv32e40s/bsp/link_corev-dv.ld index 55455b8307..e581f98659 100644 --- a/cv32e40s/bsp/link_corev-dv.ld +++ b/cv32e40s/bsp/link_corev-dv.ld @@ -38,7 +38,7 @@ SECTIONS { KEEP (*(SORT_NONE(.init))) KEEP (*(.text.start)) - } >ram + } >rom /* Read-only sections, merged into text segment: */ PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS; @@ -71,11 +71,11 @@ SECTIONS PROVIDE_HIDDEN (__rela_iplt_start = .); *(.rela.iplt) PROVIDE_HIDDEN (__rela_iplt_end = .); - } >ram + } >rom .rela.plt : { *(.rela.plt) - } >ram + } >rom .plt : { *(.plt) } .iplt : { *(.iplt) } @@ -89,11 +89,11 @@ SECTIONS *(.text .stub .text.* .gnu.linkonce.t.*) /* .gnu.warning sections are handled specially by elf.em. */ *(.gnu.warning) - } >ram + } >rom .fini : { KEEP (*(SORT_NONE(.fini))) - } >ram + } >rom PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); @@ -102,7 +102,7 @@ SECTIONS .sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } >ram + } >rom .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >ram .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram @@ -231,16 +231,15 @@ SECTIONS PROVIDE(__heap_start = .); /* If end of ram is not 16-byte aligned, align to previous 16-byte boundary */ - PROVIDE(__heap_end = ALIGN(ORIGIN(ram) + LENGTH(ram) - __heap_start - 15, 16)); + PROVIDE(__heap_end = ALIGN(ORIGIN(ram) + LENGTH(ram) - 15, 16)); . = __heap_end; } >ram /* Stack grows downward from end of ram */ - .stack (__heap_start) : ALIGN(16) /* this is a requirement of the ABI(?) */ + .stack (__heap_end) : ALIGN(16) /* this is a requirement of the ABI(?) */ { - PROVIDE(__stack_start = __heap_start); - . = __heap_end; - PROVIDE(__stack_end = .); + PROVIDE(__stack_start = __heap_end); + . = __stack_start; } >ram /* Stabs debugging sections. */ diff --git a/cv32e40s/bsp/vectors.S b/cv32e40s/bsp/vectors.S index 08af4128ae..947e4c16b1 100644 --- a/cv32e40s/bsp/vectors.S +++ b/cv32e40s/bsp/vectors.S @@ -15,6 +15,7 @@ */ .section .vectors, "ax" +.option push .option norvc .global vector_table @@ -34,7 +35,7 @@ vector_table: j __no_irq_handler j __no_irq_handler j __no_irq_handler - j __no_irq_handler + j nmi_handler j m_fast0_irq_handler j m_fast1_irq_handler j m_fast2_irq_handler @@ -51,4 +52,4 @@ vector_table: j m_fast13_irq_handler j m_fast14_irq_handler j m_fast15_irq_handler - +.option pop diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv new file mode 100644 index 0000000000..5bb219791d --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv @@ -0,0 +1,237 @@ +Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Zc 1.0.1 ace0ee,Zca,c.f*,floating point load stores shall decode as illegal,"Verify that all variations of these instructions decode as illegal +Cross check with instructions used in Zcmp/t",Check against ISS,Constrained-Random,Functional Coverage,"TODO: Should be checked, probably in an illegal instruction test.",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.*,"The remaining instructions in the C extension shall be verified, follow existing C extension verification plan",Verified in C extension ,N/A,N/A,N/A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,"Zcb + + +Note: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.",c.lbu,"Load unsigned byte, 16-bit encoding","Register operands: + +All possible rs1 registers are used. +All possible rd registers are used. +All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Testcase,"No direct coverage, but a lot of variation is output from the debug_test2",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.lhu,"Load unsigned halfword, 16-bit encoding","Register operands: + +All possible rs1 registers are used. +All possible rd registers are used. +All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Testcase,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.lh,"Load signed halfword, 16-bit encoding","Register operands: + +All possible rs1 registers are used. +All possible rd registers are used. +All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.sb,"Store byte, 16-bit encoding","Register operands: + +All possible rs1 registers are used. +All possible rs2 registers are used. +All possible register combinations where rs1 == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.sh,"Store halfword, 16-bit encoding","Register operands: + +All possible rs1 registers are used. +All possible rs2 registers are used. +All possible register combinations where rs1 == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.zext.b,"Zero extend byte, 16-bit encoding","Register operands: + +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.sext.b,"Sign extend byte, 16-bit encoding","Register operands: + +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify illegal if Zbb is not configured,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.zext.h,"Zero extend halfword, 16-bit encoding","Register operands: + +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify illegal if Zbb is not configured,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.sext.h,"Sign extend halfword, 16-bit encoding","Register operands: + +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify illegal if Zbb is not configured,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.not,"Bitwise not, 16-bit encoding","Register operands: + +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,c.mul,"Multiply, 16-bit encoding",M_EXT=M_NONE shall result in c.mul decoding as an illegal instruction,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Register operands: + +All possible rsd registers are used. +All possible rs2 registers are used. +All possible register combinations where rsd == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,Zcmp,cm.push,"Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Testcase,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify instruction with watchpoint triggers on data address ,Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction + +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_push,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. + +Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. (the order might change) + +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.pop,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify instruction with watchpoint triggers on data address ,Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction + +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_pop,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. + +Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. + +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.popret,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction + +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popret,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. + +Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. + +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.popretz,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction + +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popretz,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. + +Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. + +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.mva01s,Move a0-a1 into two registers of s0-s7,"Verify all possible variatons of sreg1, sreg2. Note that sreg1 = sreg2 is illegal",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction + +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mva01s,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. + +Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. + +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.mvsa01,Move two s0-s7 registers into a0-a1,"Verify all possible variatons of sreg1, sreg2.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction + +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mvsa01,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. + +Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. + +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,"Zcmt + + + +Note: Deprioritize as this is furthest from ratification + + + +",cm.jt,jump via table without link,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems,Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.jalt,jump via table and link to ra,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,JVT CSR,Table Jump base vector and control register,"csr stateen bit 2 controls user mode access, if bit is not set, cm.jt and cm.jalt should decode as illegal. +Access also controlled with smstateen, illegal if not enabled.",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,JVT is used as base for jt/jalt,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,JVT can be used to swap jump tables,Check against ISS,Constrained-Random,Code Coverage,N/A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 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+,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json new file mode 100644 index 0000000000..cb0c943680 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json @@ -0,0 +1,1598 @@ +[ + { + "Requirement Location": "Zc 1.0.1 ace0ee", + "Feature": "Zca", + "Sub Feature": "c.f*", + "Feature Description": "floating point load stores shall decode as illegal", + "Verification Goal": "Verify that all variations of these instructions decode as illegal \nCross check with instructions used in Zcmp/t", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Should be checked, probably in an illegal instruction test.", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zca", + "Sub Feature": "c.*", + "Feature Description": "The remaining instructions in the C extension shall be verified, follow existing C extension verification plan", + "Verification Goal": "Verified in C extension ", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lbu", + "Feature Description": "Load unsigned byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "No direct coverage, but a lot of variation is output from the debug_test2", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lhu", + "Feature Description": "Load unsigned halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lh", + "Feature Description": "Load signed halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sb", + "Feature Description": "Store byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rs1 == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sh", + "Feature Description": "Store halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rs1 == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.zext.b", + "Feature Description": "Zero extend byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sext.b", + "Feature Description": "Sign extend byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.zext.h", + "Feature Description": "Zero extend halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sext.h", + "Feature Description": "Sign extend halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.not", + "Feature Description": "Bitwise not, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.mul", + "Feature Description": "Multiply, 16-bit encoding", + "Verification Goal": "M_EXT=M_NONE shall result in c.mul decoding as an illegal instruction", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rsd == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.push", + "Feature Description": "Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify instruction with watchpoint triggers on data address ", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_push", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. (the order might change)\n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.pop", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify instruction with watchpoint triggers on data address ", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_pop", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.popret", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popret", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.popretz", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popretz", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.mva01s", + "Feature Description": "Move a0-a1 into two registers of s0-s7", + "Verification Goal": "Verify all possible variatons of sreg1, sreg2. Note that sreg1 = sreg2 is illegal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mva01s", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.mvsa01", + "Feature Description": "Move two s0-s7 registers into a0-a1", + "Verification Goal": "Verify all possible variatons of sreg1, sreg2.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mvsa01", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "cm.jt", + "Feature Description": "jump via table without link", + "Verification Goal": "Verify all possible variations of index", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "cm.jalt", + "Feature Description": "jump via table and link to ra", + "Verification Goal": "Verify all possible variations of index", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "JVT CSR", + "Feature Description": "Table Jump base vector and control register", + "Verification Goal": "csr stateen bit 2 controls user mode access, if bit is not set, cm.jt and cm.jalt should decode as illegal.\nAccess also controlled with smstateen, illegal if not enabled.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": 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+ "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from 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"Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx new file mode 100644 index 0000000000..6ebd06788c Binary files /dev/null and b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv new file mode 100644 index 0000000000..f69586d0a5 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv @@ -0,0 +1,505 @@ +Reference document,Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,Review (Marton),Review (Robin),Review (Henrik) +"RISC-V ISM vol 1 (unpriv. ISA), 20191213 + +CV32E40P doc rev 46711ac","Section 2.8 + + +Debug chapter",Enter DEBUG mode,EBREAK instruction,"Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1 +cause = 1 + +40S, same is true for ""dcsr.ebreaku"".","Add EBREAK or/and C.EBREAK to arbitrary code +Verify that: +Core switches into debug mode. +Current PC must be saved to DPC +Cause of debug must be saved to DCSR (cause=1) +PC is updated to value on dm_haltaddr_i input +Core starts executing debug code + +Ensure exception routine is not enterred",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mmode_ebreak_executes_debug_code",?,Are Lee's corner cases handled in this vplan?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage," +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_with_ebreakm +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_with_ebreakm +A :uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.dcsr_cause",?,Is Mike's gh issue handled in this vplan?,? +"RISC-V ISM vol 1 (unpriv. ISA), 20191213 + +CV32E40P doc rev 46711ac","Section 2.8 + + +Debug chapter",Enter DEBUG mode,EBREAK instruction,"Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1 +cause = 1 + +40S, same is true for ""dcsr.ebreaku"". +","Add EBREAK or/and C.EBREAK to arbitrary exception code +Verify that: +Core switches into debug mode. +PC of EBREAK instruction must be saved to DPC +Cause of debug must be saved to DCSR (cause=1) +PC is updated to value on dm_haltaddr_i input +Core starts executing debug code +Ensure exception routine is not entered",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: exception_enters_debug_mode",?,Is the PMA overrule handled in this vplan?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"N/A: Hard to detect that we are executing an exception handler. +Covered in debug_test with ISS enabled. +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.dcsr_cause",?,"Note: From OE about counters, ""vi burde også ha assert som sjekker at vi IKKE teller nå countinhibit, sleep, eller stopcount... de assertionene jeg har endre sjekker bare at de teller... vet du om vi har andre sjekker på dette?""",? +"RISC-V ISM vol 1 (unpriv. ISA), 20191213 + +CV32E40P doc rev 46711ac","Section 2.8 + + +Debug chapter",Enter ebreak exception,EBREAK instruction,"Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0. + +40S, same is true for ""dcsr.ebreaku"".","Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0. + +Verify that: +Core does not switch to debug mode, but exception routine is entered as normal.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: ebreak_behavior_m_mode",?,?,"""[ebreakm=1?]""" +,,,,,,Check against ISS,Constrained-Random,Functional Coverage," +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_regular_nodebug) +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_regular_nodebug) +A: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception +A: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception",?,?,"""[ebreakm=1?]""" +"RISC-V ISM vol 1 (unpriv. ISA), 20191213 + +CV32E40P doc rev 46711ac","Section 2.8 + + +Debug chapter",Enter ebreak exception during single stepping,EBREAK instruction,"Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0. + +40S, same is true for ""dcsr.ebreaku"".","Add EBREAK or/and C.EBREAK to arbitrary single stepping code + +Verify that: +Core switches into debug mode. +DPC set to handler. +Debug cause must be step (unless something else happened simultaneously). +PC is updated to value on dm_haltaddr_i input +Core starts executing debug code +Ensure exception routine is not entered",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_known_miscompares""",?,?,"""[ebreakm=1?]""" +,,,,,,Check against ISS,Constrained-Random,Functional Coverage," +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_step_nodebug) +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_step_nodebug) + +A: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception +A: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception",?,?,"""[ebreakm=1?]""" +CV32E40P doc rev 46711ac,Debug chapter,Enter DEBUG mode,External debug event,"Debug mode can be entered by asserting the external signal debug_req_i +cause is set to = 3 (also see verification goal)","Assert debug_req_i while executing arbitrary code +Verify that: +Core switches into debug mode. +Current PC must be saved to DPC +Cause of debug must be saved to DCSR (cause=debugger(0x3)) +PC is updated to value on dm_haltaddr_i input +Core starts executing debug code",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: request_hw_debugger",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause +A: uvmt_cv32_tb.u_debug_assert.a_debug_mode_pc +A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_haltreq +A: uvmt_cv32_tb.u_debug_assert.a_debug_req_taken",,, +"CV32E40P doc rev 46711ac + +RISCV-V External Debug Support Version 0.13.2","Debug chapter + + + +Chapter 5",Trigger module,Trigger module match event,"The core contains a trigger module with a configurable number of trigger register capable of triggering on i.a. instruction address match. +Select mcontrol6 for a trigger and enable instruction matching +Write breakpoint addr to tdata2 register +cause = 2","Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored. + +Enter debug mode by any of the above methods. +Write (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2] +Exit debug mode (dret instruction) +Verify that core enters debug mode on breakpoint addr +Current PC is saved to DPC +Cause of debug must be saved to DCSR (cause=2) +PC is updated to value on dm_haltaddr_i input +Core starts executing debug code",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause +A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug A:a_dt_instr_trigger_hit_*",?,?,? +"CV32E40P doc rev 46711ac + +RISCV-V External Debug Support Version 0.13.2","Debug chapter + + + +Chapter 5",Trigger module,Trigger module match event,"When trigger module is disabled, no trigger should fire even though the PC matches the address in tdata2.","Enter debug mode by any of the above methods. +Write (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1 +Exit debug mode (dret instruction) +Verify that core does not enter debug mode on breakpoint addr +",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",,"Why is the ""Trigger module"" Feature in red text?", +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: cg_trigger_match_disabled +A: uvmt_cv32_tb.u_debug_assert.a_trigger_match_disabled +",,, +40S User Manual 0.8.0,Debug & Trigger,Trigger module,Number of triggers,"The number of triggers is determined by DBG_NUM_TRIGGERS. +When num triggers is 0, accessing the trigger registers causes illegal instruction exception. +Triggers never fire. +""tselect"" is 0.","Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that ""tselect"" is 0.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,"""[40x? Also below.]""" +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A:a_dt_0_triggers_tdata1_access, a_dt_0_triggers_no_triggering",?,?,? +,,,,"The number of triggers is determined by DBG_NUM_TRIGGERS. +DBG_NUM_TRIGGERS can be any value within 0-4. +""tselect"" is WARL (0x0 - (DBG_NUM_TRIGGERS-1)). +All selectable triggers are functional. +All trigger registers are accessible except for ""mcontext"", ""mscontext"", ""hcontext"", and ""scontext"" (those four trap upon access).","For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher ""tselect"" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.",Self Checking Test,Directed Self-Checking,Testcase,,"There are a lot of things to check in a single point here. Nothing is wrong with this point as I see it, so there is no need to change, but ideally this point should be split up.",?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_access_context, a_dt_tselect_higher_than_dbg_num_triggers, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason. COV: c_trigger_i_has_type_mcontrol, c_trigger_i_has_type_etrigger, c_trigger_i_has_type_mcontrol6, c_trigger_i_has_type_disable",?,?,? +User Manual v0.9.0.,Control and Status Registers,Trigger module,tcontrol,"""tcontrol"" doesn't exist.","Check that attempts to access ""tcontrol"" raise an illegal instruction exception, always. (Unless overruled by a higher priority.)",Self Checking Test,Directed Self-Checking,Testcase,,,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,A: a_dt_tcontrol_not_implemented,,, +,,,"""mcontrol6"" compare values"," +Instr execute matching uses only one ""compare value"" (the PC itself). +Load/Store matching uses compare values depending on the size of the access {A, A+1, etc}.","Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_enter_dbg_reason, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*",?,?,? +"User Manual v0.9.0. + +Debug 1.0-STABLE fb7025",,,Mcontrol6Hit,"When a trigger fires, it's ""mcontrol6.hit"" field gets set to 1. +(This is also true when multiple triggers fire at once.)","Induce firing of a trigger. +Check that the corresponding ""hit"" field gets set. +Do the same for variations of multiple triggers firing at once. +Check that the field is WARL 0x0, 0x1.",Self Checking Test,Directed Self-Checking,Testcase,,,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_m6_hit_bit +a_dt_warl_tdata1_m6",,, +,,,Mcontrol6Match,"Supported match conditions in ""mcontrol6.match"" are {0 (eq), 2 (geq), 3 (less)}.","Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the ""match types"" item above.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_enter_dbg_reason, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*",?,?,? +,,,Mcontrol6UM,"Triggers can be en/disabled in M-mode, ""mcontrol6.m"", default is 0. +40S, triggers can be en/disabled in U-mode, ""mcontrol6.u"", default is 0. +40X, triggers cannot be enabled in U-mode, ""mcontrol6.u"", WARL (0x0). +The trigger action is always to enter D-mode, so ""mcontrol6.action"" is always 1.","Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A:a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_tie_offs_*",?,?,? +,,,Mcontrol6LoadStoreExecute,"The ""load"" and ""store"" bits are supported (so load/store addr matching is supported). +The ""execute"" bit is also supported. +The only supported match types are ""address match"" for {instr execution, load, store}, all using ""before"" timing. +Data matching is not supported (only addr matching), so ""mcontrol6.select"" is always 0.","Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. All of these configurations must be crossed, also against match conditions.",Self Checking Test,Directed Self-Checking,Testcase,,?,"""tdata3"" and ""tcontrol"" should be removed.",? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*. ",?,?,? +User Manual v0.9.0.,,,trigger csrs,Some fields in the trigger csrs are hardwired.,Check that the tied fields are tied.,Self Checking Test,Directed Self-Checking,Testcase,TODO csr access test? ,,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_tie_offs_tselect, a_dt_tie_offs_tdata1_mcontrol, a_dt_tie_offs_tdata1_etrigger, a_dt_tie_offs_tdata1_mcontrol6, a_dt_tie_offs_tdata1_disabled, a_dt_tie_offs_tdata2_etrigger. a_dt_tie_offs_tinfo.",,, +,,,"""mcontrol6"" atomics","40X, ""mcontrol6"" trigger behavior has specific descriptions for ""A"" extension.","40X, TODO this section must be filled out when the time comes for planning atomics verification.",,,,,?,?,? +"40S User Manual + +Debug 1.0.0","Control and Status Registers + +Trigger Data 1",Trigger module,"""tdata1.type""","The only supported types are ""2 = address match legacy"", ""5 = Exception trigger"", ""6 = Address match"", and ""15 = Disabled"".","Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is ""15"".",Self Checking Test,Directed Self-Checking,Testcase,,?,?,"""[type 2]""" +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,A: a_dt_tdata1_types,?,?,"""[type 2]""" +,,,"""tdata1.dmode""","This bit is WARL (0x1), so only D-mode can write tdata registers. And this bit is still WARL (0x1) regardless of ""type"" (2, 5, 6, 15).","Try to write tdata registers outside of debug mode, check that they are not writable. Try changing ""tdata1.dmode"" and check that it is WARL (0x1). Cross the above checks with all supported types.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_not_access_tdata1_dbg_mode, a_dt_not_access_tdata2_dbg_mode, a_dt_dmode",?,?,? +"40S User Manual + +Debug 1.0.0","Control and Status Registers + +Trigger Info",Trigger module,"""tinfo""","""tinfo.info"" holds the supported types {2, 5, 6, 15}, +""tinfo.version"" holds the ""Sdtrig"" spec version, +and the register is otherwise WARL (0x0)."," +When num triggers is more than 0, check that ""tinfo.info"" is ""1"" for the three supported types, +""tinfo.version"" is 0x1, +and that the remaining bits are 0.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,"""[type 2]""" +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,A: a_dt_triggers_tinfo,?,?,"""[type 2]""" +"40S User Manual + +Debug 1.0.0","Control and Status Registers + +Exception Trigger",Trigger module,"""etrigger""","A trigger (""tdata1"") can be configured as an exception trigger (""etrigger""). Where ""tdata2"" configures the exceptions to fire upon.","Configure ""tdata1"" and ""tdata2"" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_glitch_dt_exception_trigger_hit_*",?,?,? +,,,,"The bits {""hit"", ""vs"", ""vu"", ""s""} are not supported (WARL 0). +""nmi"" does not exist (mentioned because it briefly did). +""m"" is fully supported. +40S, ""u"" is fully supported. +40X, ""u"" is not supported (WARL0). +The triggers always enter D-mode, so ""etrigger.action"" is WARL 1.","Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.",Self Checking Test,Directed Self-Checking,Testcase,,?,"""tdata3"" and ""tcontrol"" should be removed.",? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_warl_tselect, a_dt_warl_tdata1_general, a_dt_warl_tdata1_m2, a_dt_warl_tdata1_etrigger, a_dt_warl_tdata1_m6, a_dt_warl_tdata1_disabled, a_dt_warl_tdata2_etrigger, a_dt_warl_tinfo. ",?,?,? +40s User Manual 0.8.0,Debug Chapter,debug_pc_o,,"Signal ""debug_pc_o"" is the PC of the last retired instruction The signal is only valid when ""debug_pc_valid_o"" is equal to 1",Verify that the signal can be matched with related rvfi signals,Assertion Check,Assertion Check,Assertion Coverage,"A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o +A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o_inv",,, +40S User Manual 0.8.0,Debug chapter,Debug exception addr,,"If an exception occurs during debug mode, the PC should be set to the dm_exception_addr_i input without changing the status registers","Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers +According to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: illegal_csr_in_dmode +tc: ecall_in_dmode +tc: mret_in_dmode +tc: single_step","Point mentions the exceptions supported by the e40p, need to match 40s/x capabilities and update text","""0.8.0""", +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_exception +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ecall +A: uvmt_cv32_tb.u_debug_assert.a_debug_mode_exception",,, +40S User Manual 0.8.0,Debug chapter,Core debug registers,Illegal access,"Accessing the core debug registers - DCSR, DPC and DSCRATCH0/1 while NOT in debug mode causes an illegal instruction",Access all debug registers in M-mode and observe that illegal instruction exception is triggered.,Self Checking Test,Directed Non-Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: debug_csr_rw",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_regs_m_mode +A: uvmt_cv32_tb.u_debug_assert.a_debug_regs_mmode",,, +Debug 1.0.0,Debug Control and Status,"""dcsr"" writability",,"All fields of ""dcsr"" (except some) are only writable by the external debugger. Exceptions are {""v"", ""prv"", ""cause"", ""nmip""}.","Keep track of whether an external debug request has happened, check that if there is a change in ""dcsr"" (except some) then there must have been an external debug request.",Assertion Check,Constrained-Random,Functional Coverage,,?,?,? +40S User Manual 0.8.0,Debug chapter,Trigger module registers,Access from M-mode,"Accessing the tdata1/2 registers are readable from M-mode, but not writeable. (And is not accessible at all from U-mode.)","Access all tdata registers in M-mode and observe writes have no effects and reads should reflect register content. + +Access registers from D-mode and observe full R/W access. + +Access from U-mode and observe no access at all.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test"".",Should we also check r/w in U-mode?,"""tdata3"" should be removed.",? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_regs. A: a_dt_no_write_access_to_tdata_in_mmode, +a_dt_read_access_to_tdata1_in_mmode, +a_dt_read_access_to_tdata2_in_mmode, +a_dt_write_access_to_tdata1_in_dmode, +a_dt_write_access_to_tdata2_in_dmode, +a_dt_read_access_to_tdata1_in_dmode, +a_dt_read_access_to_tdata2_in_dmode, +a_dt_no_access_to_tdata_in_umode. +COV: c_dt_write_tdata1_in_mmode, +c_dt_write_tdata2_in_mmode. + +",?,?,? +Debug 1.0.0,Trigger Registers,Trigger module registers,"""tdata1"", writing zero","""it is guaranteed that writing 0 to tdata1 disables the trigger, and leaves it in a state where tdata2 and tdata3 can be written with any value that makes sense for any trigger type supported by this trigger."" + +More generally, ""When a selected trigger is disabled [type 15], tdata2 and tdata3 can be written with any value supported by any of the types this trigger supports"".","Write 0 to ""tdata1"", ensure that its state becomes disabled (type 15). Write values to ""tdata2"" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_write_0_to_tdata1, +a_dt_enter_dbg_reason",?,?,? +"Debug 1.0.0 +UserManual v0.9.0.",,,tdata2,"""tdata2"" should always be RW (any) for type 2/6/15.","Change the type to 2/6/15 and write any data to ""tdata2"", read it back and check that it always gets set.",Self Checking Test,Directed Self-Checking,Testcase,,?,"""tdata3"" should be removed.",? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_write_tdata2_random_in_dmode_type_2_6_15. COV: c_dt_w_csrrw_tdata2_m2_m6_disabled, +c_dt_w_csrrs_tdata2_m2_m6_disabled, +c_dt_w_csrrc_tdata2_m2_m6_disabled, +c_dt_w_csrrwi_tdata2_m2_m6_disabled, +c_dt_w_csrrsi_tdata2_m2_m6_disabled, +c_dt_w_csrrci_tdata2_m2_m6_disabled",?,Type 2,? +User Manual v0.9.0.,,,tdata3,"""tdata3"" doesn't exist.","Check that attempts to access ""tdata3"" raise an illegal instruction exception, always. (Unless overruled by a higher priority.) +Verify that tdata3 is illegal for all tdata2 types.",Self Checking Test,Directed Self-Checking,Testcase,,,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_tdata3_not_implemented. COV: c_dt_access_tdata3_m2, c_dt_access_tdata3_etrigger, c_dt_access_tdata3_m6, c_dt_access_tdata3_disabled.",,, +Debug 1.0.0,,,Other tdata registers,"Writing one ""tdata*"" register must not modify other ""tdata*"" registers, and must not modify other triggers than the currently selected.","Read the state of all triggers, write to tdata1/2 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one ""tdata*"" register that was written.",Self Checking Test,Directed Self-Checking,Testcase,,?,"""tdata3"" should be removed.",? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: a_dt_write_only_tdata1, +a_dt_write_only_tdata2.",?,?,? +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt2,Program Buffer,Interrupts,"While in debug mode and executing from the program buffer, all interrupts are masked.","Enable interrupts (setting mstatus.mie field and mie register). +Bring core into debug mode and start executing from program buffer. +Generate interrupts while in debug mode and ensure they are masked.",Self Checking Test,Directed Self-Checking,Testcase,,,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_in_debug +A: uvmt_cv32_tb.u_debug_assert.a_irq_in_debug",,, +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt3,Program Buffer,Exceptions,"While in debug mode and executing from the program buffer, exceptions don’t update any registers but they DO end execution of PB (TBD: goes back to M-mode or restarts in debug(?)) [PZ] this is redundnant with dm_exception_addr_i (on line 10 & 11)","Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn’t update any registers, and jumps out of debug mode into M-mode",Self Checking Test,,,N/A,,, +,,,,,,Check against ISS,,,N/A,,, +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt4,Program Buffer,Triggers,"While in debug mode and executing from the program buffer, no action is taken on any trigger match.","Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test"". ",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match_disabled (d_match_with_en) A:a_dt_no_actions_on_trigger_matches_in_debug_dcsr +a_dt_no_actions_on_trigger_matches_in_debug_dpc",,, +Debug 1.0.0,dcsr,Counters,,"Spec:Counters may be stopped, depending on stopcount in dscr","""dcsr.stopcount"" is WARL and we must test the counter bevaior for both values of stopcount.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: test_stopcnt_bits",?,"Is wrong, need update.",? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_counters_enabled +A: uvmt_cv32_tb.u_debug_assert.a_minstret_count +A: uvmt_cv32_tb.u_debug_assert.a_mcycle_count",?,"Any other ""40p"" outdateds here? Marked them all.",? +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt6,Program Buffer,Timers,"Timers may be stopped, depending on stoptime in dcsr","(See ""Counters"" above.)",,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt7,Program Buffer,WFI instruction,"In debug, the WFI instruction acts as a NOP instruction","Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_in_debug +A: uvmt_cv32_tb.u_debug_assert.a_wfi_in_debug",,, +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt8,Program Buffer,Priv. lvl changes,An ebreak instruction during debug shall result in relaunching the debugger entry code by setting the PC to the halt_addr_i and will not change any CSR in doing this.,"Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: request_ebreak_3x",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_with_ebreakm (.ebreak_in_debug) +CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_with_ebreakm (.ebreak_in_debug) +A: uvmt_cv32_tb.u_debug_assert.a_ebreak_during_debug_mode",,, +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt9,Program Buffer,Fence instructions,Completing program buffer execution is considered output for the purpose of the fence instruction.,"TBD - need to understand the fence instruction in cv32e40s. Is ""completing program buffer execution"" the same as executing dret? [PZ] waiting for more clarity from RISCV Foundation debug task group (see https://lists.riscv.org/g/tech-debug/topic/clarification_request/75725318?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,75725318 ) + +Nothing to do. That sentence was retracted here https://github.com/riscv/riscv-debug-spec/pull/601/files . Now it seems they just recommend debug software to do a fence when completing abstract commands.",,,,N/A,What are we doing here?,Added N/A disclaimer. Striking it., +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt10,Program Buffer,Ctrl. Transfer instr.,"All control transfer instructions may act as illegal instructions if destination is within program buffer. If one does, all must.",N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt11,Program Buffer,Ctrl. Transfer instr.,"All control transfer instructions may as illegal instructions if destination is outside the program buffer. If one does, all must.",N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt12,Program Buffer,Instr. Dependent of PC,Instructions that depend on the PC may act as illegal instructions,N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt13,Program Buffer,Effective XLEN,Effective XLEN = DXLEN,"CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode +Mike: what exactly would a testcase actually do to check this? +ØK: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.",,,,N/A,,, +,,,,,,,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.2 Load-Reserved/Store-Conditional,,,,"N/A for CV32E40s (requires A-extention) : need Arjan/Davide to sign-off on this. [PZ] This is not a test but a warning or assumption that debug entry should not occur between a lr and sc instruction pair. Moreover, CV32E40s does not support A-extension",,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.3 Wait for interrupt,Debug mode,WFI instruction,"If debug_req_i is asserted while waiting for interrupt (core_sleep_o = 1), WFI instruction must complete (core_sleep_o -> 0) and hart enters debug mode.","Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: wfi_before_dmode","Update reference document, applies to several following points",, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_debug_req +A: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req_wu +A: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"By setting step in dcsr[2] before resuming execution, a debugger can cause the hart to execute a single instructin before re-entering debug mode.",Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.,Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step) +A: uvmt_cv32_tb.u_debug_assert.a_single_step +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the instruction being fetched or executed in a single step casues an exception, debug mode is entered immediately after the PC is changed to the exception handler and registers tval and cause are updated. + +Note: CV32E40S does not support tval (this might be supported in future cores)","Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode. + +Check tval==0",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step","Update to reflect that we are now checking ""future cores""",, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_illegal) +A: uvmt_cv32_tb.u_debug_assert.a_single_step_exception",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the instruction being fetched or executed in a single step causes a trigger, debug mode is entered immediately after the trigger fired. Cause is set to 2 instead of 4","Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_trigger_match) +A: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the intruction executed in the single step results in a PC that will cause an exception, the exception will not execute until the next time the hart resumes.","Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)",Self Checking Test,,,N/A,,, +,,,,,,Check against ISS,,,N/A,,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the intruction executed in the single step results in a PC that will cause a trigger event, the trigger event will not take place until the instruction is executed.","This can be verified in the same steps as marked with (#1). +Mike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_next_pc_will_match) +A: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the single step instruction is WFI, it must be treated as a nop instead of stalling and waiting for interrupt. [PZ] #pz_ref2","Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_wfi) +A: uvmt_cv32_tb.u_debug_assert.a_single_step_wfi",,, +RISC-V External Debug Support Version 0.13.2,4.5 Reset,Debug mode,Reset,"When the hart comes out of reset, it must immediately enter debug mode without executing any instructions if the halt signal or debug_req_i is asserted.","Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_reset""",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_at_reset +A: uvmt_cv32_tb.u_debug_assert.a_debug_at_reset",,, +RISC-V External Debug Support Version 0.13.2,4.6 dret instruction,Debug mode,dret instruction,Executing dret while NOT in debug mode will cause an illegal instruction exception.,"Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown. +Can be tested in the same test as for debug entry",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: dret_in_mmode",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret +A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret",,, +RISC-V External Debug Support Version 0.13.2,4.6 dret instruction,Debug mode,dret instruction,Executing dret while in debug mode will restore PC to the value in dpc and exit debug mode.,"Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. +Can be tested in the same test as for debug entry.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: all testcases that enter and exit debug mode (most)","remove note, this is covered or 40s (U-Mode) in the next point",, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret +A: uvmt_cv32_tb.u_debug_assert.a_dmode_dret",,, +Debug 1.0.0,Execution Based,Debug mode,dret instruction,"40S, ""When dret is executed, […] normal execution resumes at the privilege set by prv""","Be in debug mode, note the value in ""dcsr.prv"", exit debug mode with a ""dret"", check that the mode being executed in is the one indicated by ""dcsr.prv"". (Note overlap with user mode vplan.)",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mprv_dret_to_umode",?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,? +Debug 1.0.0,Resume,Debug mode,dret instruction,"40S, ""If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.""","Be in debug mode, set ""dcsr.prv"" to U-mode, let ""mstatus.MPRV"" be set and clear (different runs), exit debug mode with a ""dret"", check that ""mstatus.MPRV"" ends up cleared. (Note overlap with user mode vplan.)",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mprv_dret_to_umode",?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,? +Debug 1.0.0,Debug Control and Status,Debug mode,dret instruction,"""Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in""","40S, enter debug mode from different modes, check that ""dcsr.prv"" represents the previous mode. (Note overlap with user mode vplan.) + +40X, check that ""dcsr.prv"" is always M-mode.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mprv_dret_to_umode",?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,? +"RISC-V ISM vol 1 (unpriv. ISA), 20191213","Section 2.8 + + +Debug chapter",Semihosting,,"To enable semihosting, a special instruction sequence is needed as there is only a single EBREAK instruction available. + +slli x0, x0, 0x1f # Entry NOP +ebreak # Break to debugger +srai x0, x0, 7 # NOP encoding the semihosting call number 7 + +[PZ] This is a software convention and need not be tested in verification. As long as the above instructions work in general, then no need for dedicated semihosting testing.","If all points above passes, there should be nothing to verify here. Semihosting will be handled from SW.",,,,N/A,,, +,,Trigger,Exception handling,"If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.","Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.",Self Checking Test,Directed Self-Checking,Testcase,"With ""before timing"" the core will not attempt to execute instruction at trigger address",,"""link to coverage"": Is this merely claimed? Can we either test it or change the relevant vplan items?", +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"With ""before timing"" the core will not attempt to execute instruction at trigger address + +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause +A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger",,, +,,"Trigger, single step",Exception handling,"If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.","Set up the trigger to match on an address containing an illegal instruction. +Set up single stepping such that the match address will be executed in the next step. +When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.",Self Checking Test,Directed Self-Checking,Testcase,"With ""before timing"" the core will not attempt to execute instruction at trigger address",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"With ""before timing"" the core will not attempt to execute instruction at trigger address + +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause +A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger",,, +"40S User Manual 0.8.0 + +OBI-v1.4","Core Integration + +dbg",OBI,,"OBI bus accesses shall indicate whether the core is in D-mode or not, signaled via ""instr_dbg_o"" and ""data_dbg_o"".","Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have ""dbg"" set correspondingly.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr +A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr_inv +A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data +A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data_inv",?,?,? +"40S User Manual 0.8.0 + +Debug 1.0.0","Control and Status Registers + +Debug Control and Status",NMI,,"The ""dcsr.nmip"" bit is supported. +When a non-maskable interrupt is pending, then this bit must be high.","Cause an NMI to occur, read ""dcsr.nmip"", check that it is high as expected. Have no NMI pending, read ""dsr.nmip"", check that it is low.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,? +"40X/S user manual + +Debug 1.0.0 + +Privspec 1.12","Control and Status Registers + +Debug Control and Status + +Machine Status Registers",MPRV,,"""dcsr.mprven"" is WARL 1. +Since ""mprven"" is 1, then ""mstatus.MPRV"" always takes effect in D-mode.","Read ""dcsr.mprven"", check that it is always 1. + +40S, be in debug mode, have ""mstatus.MPRV"" disabled, check that all instructions are treated as M-mode. Be in debug mode, have ""mstatus.MPRV"" enabled, have ""mstatus.MPP"" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,? +Silabs Internal,,Instruction boundaries,Haltreq and stepping,"External debug requests and single stepping can only cause debug entry on ""instruction boundaries"", so a multi-step instruction cannot be interrupted by this.","While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,? +Debug 1.0.0,,Instruction boundaries,Synchronous entry,"Trigger matching can cause synchronous debug entry, and can interrupt ""within"" and instruction.","Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted ""midway"" and that debug mode is entered correctly.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,? +"RISC-V External Debug Support Version 0.13.2 +CV32E40P doc rev 46711ac","4.8.1 DCSR + +Control and Status Registers",Single step,Interrupts,"While single stepping, interrupts (maskable and non-maskable) may be enabled or disabled using the dcsr.stepie bit. ","Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (mmode_step_stepie) +A: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis",?,?,? +,,,,,"Set up single stepping. Ensure NMI is asserted while performing a step. Ensure that the NMI is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0. +",Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvmt_cv32_tb.u_debug_assert.cov_step_stepie_nmi +A: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis",?,?,? +,,Interrupts,Simultaneous Interrupt,,Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address),Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq + +""NOTE: not tested specifically, but is covered in formal verification of: +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause"" + + +","What feature is this? Several points in this region lack context, or a merging of left hand cells",, +,,,Simultaneous NMI,,Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address),Self Checking Test,Directed Self-Checking,Testcase,,?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",?,?,? +,,RISCV compliance,,All RISCV code should run in debug mode as well as M mode,[PZ] Run RISCV compliance tests all in debug mode,Self Checking Test,Directed Self-Checking,Testcase,Waived,,, +,,Corner Cases,Corner Cases,,[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh),Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",,, +,,,,,,Check against ISS,Constrained-Random,Functional coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq + (.irq_dreq_trig_ill/cebreak/ebreak/branch/multicycle) +",,, +,,,,,[PZ] Add coverage to ensure debug_req asserted on every FSM state,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext +",,, +,,,,,[PZ] Have trigger address match an instruction that has an illegal instruction (both in normal and single step mode). Ensure debug is enterred with cause set to trigger and PC is set to exception handler prior to debug entry,,,,"Not possible with ""before timing"", core will not execute instruction at match address before entering debug mode.",,, +,,,,"If a debug_req_i is asserted when an illegal instructions is being executed, the address of the trap handler must be stored to dpc instead of the address of the illegal instruction","Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction",Self Checking Test,Directed Self-Checking,Testcase,Covered in DTC debug_test_known_miscompares,Lacks verification goal,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,A: uvmt_cv32_tb.u_debug_assert.a_illegal_insn_debug_req,,, +,,,,"Several causes exist for entering debug, the priority is specified in a table in the ""dcsr"" section of the debug spec. + +Note: This changed going to v1.0.0","Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.",Self Checking Test,Directed Self-Checking,Testcase,"Partly covered in DTC ""debug_test"" and ""debug_test_trigger"", the rest will be covered by corev_rand_debug_ebreak and corev_rand_debug_single_step",?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.debug_causes + (.trig_vs_ebreak, trig_vs_cebreak, trig_vs_dbg_req, trig_vs_step + ebreak_vs_req, cebreak_vs_req, ebreak_vs_step, cebreak_vs_step, dbg_req_vs_step)",?,?,? +,,,3-way Corners,"* Haltreq, then single-step ebreak +* Single-step ebreak, then haltreq +* Single-step ebreak with trigger +* Single-step ebreak, then trigger on next instr +* Haltreq, then ebreak with trigger +* Haltreq, then ebreak, then trigger on next instr +* Haltreq during ebreak with trigger +* Haltreq during ebreak, then tirgger on next instr +(More 3-way corners could be possible, see ""Generated Corners"" below.)","Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.",Self Checking Test,Directed Self-Checking,Testcase,,,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,, +,,,4-way Corners,"* Haltreq, then single-step ebreak with trigger +* Haltreq, then single-step ebreak, then trigger on next instr +* Single-step ebreak with trigger, then haltreq +* Single-step ebreak, then haltreq and trigger on next instr +(More 4-way corners could be possible, see ""Generated Corners"" below.)","Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.",Self Checking Test,Directed Self-Checking,Testcase,,,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,, +,,,Generated Corners,There are many corners,"Write a covergroup with all events that can cause debug entry {haltreq, step, etc…} and include timing aspects of first/then (""e.g. haltreq right after step"", etc…). Then, create a cross of all of these, as that should in principle generate all possible corners if written comprehensively. Finally, review if all of these corners are covered by the assertion set.",Assertion Check,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,, +,,,Dret,https://github.com/openhwgroup/core-v-verif/issues/1476,"Execute ""dret"" in M-mode, followed by a haltreq (as early as possible), so D-mode is entered before the exception handler. Ensure the rest of debug modelling has predictions on all csr and rvfi signals needed for checking this outcome.",Assertion Check,Constrained-Random,Functional Coverage,A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret,,, +,,External debug request,Startup / clock gating,"When the reset signal is deasserted, but before the fetch_enable_i signal is active, the internal clock of the core is gated. The cv32e40p would not miss this request, but on the 40s haltreq is no longer sticky and so it should not cause debug entry.","Assert short (1 cycle) debug_req_i randomly after reset, before the core starts executing. Observe that the core does not enter debug mode but instead starts executing instructions.",Self Checking Test,Directed Self-Checking,Testcase,Covered in DTC debug_test_boot_set,Deprecated as debug_req is now non-sticky,"Fix ""40p""",? +RISC-V Debug Support Version 1.0.0-STABLE 86e748abed738f8878707dc31fe2713f41868f2c,A.2 Execution Based,Program Buffer,PMP,"""the PMP must not disallow fetches, loads, or stores in the address range associated with the Debug Module when the hart is in Debug Mode, regardless of how the PMP is configured""","Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.",Self Checking Test,Directed Self-Checking,Testcase,,Any verdict on this now?,?,? +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,---- END ----,,,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json new file mode 100644 index 0000000000..a9ef9f1b7c --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json @@ -0,0 +1,2706 @@ +[ + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1\ncause = 1\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug cod\n\nEnsure exception routine is not enterred", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "Are Lee's corner cases handled in this vplan?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug cod\n\nEnsure exception routine is not enterred", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_with_ebreakm\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_with_ebreakm\nA :uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "Is Mike's gh issue handled in this vplan?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1\ncause = 1\n\n40S, same is true for \"dcsr.ebreaku\".\n", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary exception code\nVerify that:\nCore switches into debug mode.\nPC of EBREAK instruction must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "Is the PMA overrule handled in this vplan?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary exception code\nVerify that:\nCore switches into debug mode.\nPC of EBREAK instruction must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "N/A: Hard to detect that we are executing an exception handler.\nCovered in debug_test with ISS enabled.\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "Note: From OE about counters, \"vi burde ogs\u00e5 ha assert som sjekker at vi IKKE teller n\u00e5 countinhibit, sleep, eller stopcount... de assertionene jeg har endre sjekker bare at de teller... vet du om vi har andre sjekker p\u00e5 dette?\"", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter ebreak exception", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0.\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0.\n\nVerify that:\nCore does not switch to debug mode, but exception routine is entered as normal.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter ebreak exception", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0.\n\nVerify that:\nCore does not switch to debug mode, but exception routine is entered as normal.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_regular_nodebug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_regular_nodebug)\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception\nA: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter ebreak exception during single stepping", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0.\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary single stepping code\n\nVerify that:\nCore switches into debug mode.\nDPC set to handler.\nDebug cause must be step (unless something else happened simultaneously).\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_known_miscompares\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter ebreak exception during single stepping", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary single stepping code\n\nVerify that:\nCore switches into debug mode.\nDPC set to handler.\nDebug cause must be step (unless something else happened simultaneously).\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_step_nodebug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_step_nodebug)\n\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception\nA: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"", + "": "" + }, + { + "Reference document": "CV32E40P doc rev 46711ac", + "Requirement Location": "Debug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "External debug event", + "Feature Description": "Debug mode can be entered by asserting the external signal debug_req_i\ncause is set to = 3 (also see verification goal)", + "Verification Goal": "Assert debug_req_i while executing arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=debugger(0x3))\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert debug_req_i while executing arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=debugger(0x3))\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_debug_mode_pc\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_haltreq\nA: uvmt_cv32_tb.u_debug_assert.a_debug_req_taken", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "CV32E40P doc rev 46711ac\n\nRISCV-V External Debug Support Version 0.13.2", + "Requirement Location": "Debug chapter \n\n\n\nChapter 5", + "Feature": "Trigger module", + "Sub Feature": "Trigger module match event", + "Feature Description": "The core contains a trigger module with a configurable number of trigger register capable of triggering on i.a. instruction address match.\nSelect mcontrol6 for a trigger and enable instruction matching\nWrite breakpoint addr to tdata2 register\ncause = 2", + "Verification Goal": "Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored.\n\nEnter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2]\nExit debug mode (dret instruction)\nVerify that core enters debug mode on breakpoint addr\nCurrent PC is saved to DPC\nCause of debug must be saved to DCSR (cause=2)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored.\n\nEnter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2]\nExit debug mode (dret instruction)\nVerify that core enters debug mode on breakpoint addr\nCurrent PC is saved to DPC\nCause of debug must be saved to DCSR (cause=2)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "CV32E40P doc rev 46711ac\n\nRISCV-V External Debug Support Version 0.13.2", + "Requirement Location": "Debug chapter \n\n\n\nChapter 5", + "Feature": "Trigger module", + "Sub Feature": "Trigger module match event", + "Feature Description": "When trigger module is disabled, no trigger should fire even though the PC matches the address in tdata2.", + "Verification Goal": "Enter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1\nExit debug mode (dret instruction)\nVerify that core does not enter debug mode on breakpoint addr\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Enter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1\nExit debug mode (dret instruction)\nVerify that core does not enter debug mode on breakpoint addr\n", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: cg_trigger_match_disabled\nA: uvmt_cv32_tb.u_debug_assert.a_trigger_match_disabled\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug & Trigger", + "Feature": "Trigger module", + "Sub Feature": "Number of triggers", + "Feature Description": "The number of triggers is determined by DBG_NUM_TRIGGERS.\nWhen num triggers is 0, accessing the trigger registers causes illegal instruction exception.\nTriggers never fire.\n\"tselect\" is 0.", + "Verification Goal": "Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that \"tselect\" is 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[40x? Also below.]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that \"tselect\" is 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "The number of triggers is determined by DBG_NUM_TRIGGERS.\nDBG_NUM_TRIGGERS can be any value within 0-4.\n\"tselect\" is WARL (0x0 - (DBG_NUM_TRIGGERS-1)).\n\"tcontrol\" is WARL (0x0).\nAll selectable triggers are functional.\nAll trigger registers are accessible except for \"mcontext\", \"mscontext\", \"hcontext\", and \"scontext\" (those four trap upon access).", + "Verification Goal": "For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher \"tselect\" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "There are a lot of things to check in a single point here. Nothing is wrong with this point as I see it, so there is no need to change, but ideally this point should be split up.", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher \"tselect\" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nMatch Control Type 6", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" match types", + "Feature Description": "The \"load\" and \"store\" bits are supported (so load/store addr matching is supported).\nThe \"execute\" bit is also supported.\nThe only supported match types are \"address match\" for {instr execution, load, store}, all using \"before\" timing so \"mcontrol6.timing\" is always 0.\nData matching is not supported (only addr matching), so \"mcontrol6.select\" is always 0.", + "Verification Goal": "Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. Also check that the tied fields are tied. All of these configurations must be crossed, also against match conditions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. Also check that the tied fields are tied. All of these configurations must be crossed, also against match conditions.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" match conditions", + "Feature Description": "Supported match conditions in \"mcontrol6.match\" are {0 (eq), 2 (geq), 3 (less)}.", + "Verification Goal": "Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the \"match types\" item above.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the \"match types\" item above.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" compare values", + "Feature Description": "\nInstr execute matching uses only one \"compare value\" (the PC itself).\nLoad/Store matching uses compare values depending on the size of the access {A, A+1, etc}.", + "Verification Goal": "Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" enable", + "Feature Description": "Triggers can be en/disabled in M-mode, \"mcontrol6.m\", default is 0.\n40S, triggers can be en/disabled in U-mode, \"mcontrol6.u\", default is 0.\n40X, triggers cannot be enabled in U-mode, \"mcontrol6.u\", WARL (0x0).\nThe trigger action is always to enter D-mode, so \"mcontrol6.action\" is always 1.", + "Verification Goal": "Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" atomics", + "Feature Description": "40X, \"mcontrol6\" trigger behavior has specific descriptions for \"A\" extension.", + "Verification Goal": "40X, this section must be filled out when the time comes for planning atomics verification.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nTrigger Data 1", + "Feature": "Trigger module", + "Sub Feature": "\"tdata1.type\"", + "Feature Description": "The only supported types are \"2 = address match legacy\", \"5 = Exception trigger\", \"6 = Address match\", and \"15 = Disabled\".", + "Verification Goal": "Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is \"15\".", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is \"15\".", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"tdata1.dmode\"", + "Feature Description": "This bit is WARL (0x1), so only D-mode can write tdata registers. And this bit is still WARL (0x1) regardless of \"type\" (2, 5, 6, 15).", + "Verification Goal": "Try to write tdata registers outside of debug mode, check that it traps. Try changing \"tdata1.dmode\" and check that it is WARL (0x1). Cross the above checks with all supported types.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try to write tdata registers outside of debug mode, check that it traps. Try changing \"tdata1.dmode\" and check that it is WARL (0x1). Cross the above checks with all supported types.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nTrigger Info", + "Feature": "Trigger module", + "Sub Feature": "\"tinfo\"", + "Feature Description": "\"tinfo.info\" holds the supported types {2, 5, 6, 15}, and the register is otherwise WARL (0x0).", + "Verification Goal": "When num triggers is 0, check that \"tinfo\" is 0.\nFor any other num triggers, check that \"tinfo.info\" is \"1\" for the three supported types, and that the remaining bits are 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "When num triggers is 0, check that \"tinfo\" is 0.\nFor any other num triggers, check that \"tinfo.info\" is \"1\" for the three supported types, and that the remaining bits are 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"", + "": "" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nException Trigger", + "Feature": "Trigger module", + "Sub Feature": "\"etrigger\"", + "Feature Description": "A trigger (\"tdata1\") can be configured as an exception trigger (\"etrigger\"). Where \"tdata2\" configures the exceptions to fire upon.", + "Verification Goal": "Configure \"tdata1\" and \"tdata2\" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure \"tdata1\" and \"tdata2\" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "The bits {\"hit\", \"vs\", \"vu\", \"s\"} are not supported (WARL 0).\n\"nmi\" does not exist (mentioned because it briefly did).\n\"m\" is fully supported.\n40S, \"u\" is fully supported.\n40X, \"u\" is not supported (WARL0).\nThe triggers always enter D-mode, so \"etrigger.action\" is WARL 1.", + "Verification Goal": "Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40s User Manual 0.8.0", + "Requirement Location": "Debug Chapter", + "Feature": "debug_pc_o", + "Sub Feature": "", + "Feature Description": "Signal \"debug_pc_o\" is the PC of the last retired instruction The signal is only valid when \"debug_pc_valid_o\" is equal to 1", + "Verification Goal": "Verify that the signal can be matched with related rvfi signals", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Assertion Check", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o\nA: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o_inv", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Debug exception addr", + "Sub Feature": "", + "Feature Description": "If an exception occurs during debug mode, the PC should be set to the dm_exception_addr_i input without changing the status registers", + "Verification Goal": "Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers\nAccording to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Point mentions the exceptions supported by the e40p, need to match 40s/x capabilities and update text", + "Review (Robin)": "\"0.8.0\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug exception addr", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers\nAccording to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_exception\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ecall\nA: uvmt_cv32_tb.u_debug_assert.a_debug_mode_exception", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Core debug registers", + "Sub Feature": "Illegal access", + "Feature Description": "Accessing the core debug registers - DCSR, DPC and DSCRATCH0/1 while NOT in debug mode causes an illegal instruction", + "Verification Goal": "Access all debug registers in M-mode and observe that illegal instruction exception is triggered.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Core debug registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Access all debug registers in M-mode and observe that illegal instruction exception is triggered.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_regs_m_mode\nA: uvmt_cv32_tb.u_debug_assert.a_debug_regs_mmode", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Debug Control and Status", + "Feature": "\"dcsr\" writability", + "Sub Feature": "", + "Feature Description": "All fields of \"dcsr\" (except some) are only writable by the external debugger. Exceptions are {\"v\", \"prv\", \"cause\", \"nmip\"}.", + "Verification Goal": "Keep track of whether an external debug request has happened, check that if there is a change in \"dcsr\" (except some) then there must have been an external debug request.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Trigger module registers", + "Sub Feature": "Access from M-mode", + "Feature Description": "Accessing the trigger module registers - tselect, tdata1/2/3, tinfo, tcontrol are readable from M-mode, but not writeable. (And is not accessible at all from U-mode.)", + "Verification Goal": "Access all trigger module registers in M-mode and observe writes have no effects and reads should reflect register content.\n\nAccess registers from D-mode and observe full R/W access.\n\nAccess from U-mode and observe no access at all.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Should we also check r/w in U-mode?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Access all trigger module registers in M-mode and observe writes have no effects and reads should reflect register content.\n\nAccess registers from D-mode and observe full R/W access.\n\nAccess from U-mode and observe no access at all.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_regs\n", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Trigger Registers", + "Feature": "Trigger module registers", + "Sub Feature": "\"tdata1\", writing zero", + "Feature Description": "\"it is guaranteed that writing 0 to tdata1 disables the trigger, and leaves it in a state where tdata2 and tdata3 can be written with any value that makes sense for any trigger type supported by this trigger.\"\n\nMore generally, \"When a selected trigger is disabled [type 15], tdata2 and tdata3 can be written with any value supported by any of the types this trigger supports\".", + "Verification Goal": "Write 0 to \"tdata1\", ensure that its state becomes disabled (type 15). Write values to \"tdata2\" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Write 0 to \"tdata1\", ensure that its state becomes disabled (type 15). Write values to \"tdata2\" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "\"tdata2\" and \"tdata3\"", + "Feature Description": "\"tdata2\" should always be RW (any), and \"tdata3\" is always WARL (0x0).", + "Verification Goal": "Change the type to 2/5/6/15 and write any data to \"tdata2\", read it back and check that it always gets set. Do the same for \"tdata3\" and check that it always reads back 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "Type 2", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Change the type to 2/5/6/15 and write any data to \"tdata2\", read it back and check that it always gets set. Do the same for \"tdata3\" and check that it always reads back 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "Type 2", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "Other tdata registers", + "Feature Description": "Writing one \"tdata*\" register must not modify other \"tdata*\" registers, and must not modify other triggers than the currently selected.", + "Verification Goal": "Read the state of all triggers, write to tdata1/2/3 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one \"tdata*\" register that was written.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Read the state of all triggers, write to tdata1/2/3 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one \"tdata*\" register that was written.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt2", + "Feature": "Program Buffer", + "Sub Feature": "Interrupts", + "Feature Description": "While in debug mode and executing from the program buffer, all interrupts are masked.", + "Verification Goal": "Enable interrupts (setting mstatus.mie field and mie register).\nBring core into debug mode and start executing from program buffer.\nGenerate interrupts while in debug mode and ensure they are masked.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Enable interrupts (setting mstatus.mie field and mie register).\nBring core into debug mode and start executing from program buffer.\nGenerate interrupts while in debug mode and ensure they are masked.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_in_debug\nA: uvmt_cv32_tb.u_debug_assert.a_irq_in_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt3", + "Feature": "Program Buffer", + "Sub Feature": "Exceptions", + "Feature Description": "While in debug mode and executing from the program buffer, exceptions don\u2019t update any registers but they DO end execution of PB (TBD: goes back to M-mode or restarts in debug(?)) [PZ] this is redundnant with dm_exception_addr_i (on line 10 & 11)", + "Verification Goal": "Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn\u2019t update any registers, and jumps out of debug mode into M-mode", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn\u2019t update any registers, and jumps out of debug mode into M-mode", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt4", + "Feature": "Program Buffer", + "Sub Feature": "Triggers", + "Feature Description": "While in debug mode and executing from the program buffer, no action is taken on any trigger match.", + "Verification Goal": "Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match_disabled (d_match_with_en)", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "dcsr", + "Feature": "Counters", + "Sub Feature": "", + "Feature Description": "Spec:Counters may be stopped, depending on stopcount in dscr", + "Verification Goal": "\"dcsr.stopcount\" is WARL and we must test the counter bevaior for both values of stopcount.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "Is wrong, need update.", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Counters", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "\"dcsr.stopcount\" is WARL and we must test the counter bevaior for both values of stopcount.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_counters_enabled\nA: uvmt_cv32_tb.u_debug_assert.a_minstret_count\nA: uvmt_cv32_tb.u_debug_assert.a_mcycle_count", + "Review (Marton)": "?", + "Review (Robin)": "Any other \"40p\" outdateds here? Marked them all.", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt6", + "Feature": "Program Buffer", + "Sub Feature": "Timers", + "Feature Description": "Timers may be stopped, depending on stoptime in dcsr", + "Verification Goal": "(See \"Counters\" above.)", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt7", + "Feature": "Program Buffer", + "Sub Feature": "WFI instruction", + "Feature Description": "In debug, the WFI instruction acts as a NOP instruction", + "Verification Goal": "Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_in_debug\nA: uvmt_cv32_tb.u_debug_assert.a_wfi_in_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt8", + "Feature": "Program Buffer", + "Sub Feature": "Priv. lvl changes", + "Feature Description": "An ebreak instruction during debug shall result in relaunching the debugger entry code by setting the PC to the halt_addr_i and will not change any CSR in doing this.", + "Verification Goal": "Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_with_ebreakm (.ebreak_in_debug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_with_ebreakm (.ebreak_in_debug)\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_during_debug_mode", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt9", + "Feature": "Program Buffer", + "Sub Feature": "Fence instructions", + "Feature Description": "Completing program buffer execution is considered output for the purpose of the fence instruction.", + "Verification Goal": "TBD - need to understand the fence instruction in cv32e40s. Is \"completing program buffer execution\" the same as executing dret? [PZ] waiting for more clarity from RISCV Foundation debug task group (see https://lists.riscv.org/g/tech-debug/topic/clarification_request/75725318?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,75725318 )\n\nNothing to do. That sentence was retracted here https://github.com/riscv/riscv-debug-spec/pull/601/files . Now it seems they just recommend debug software to do a fence when completing abstract commands.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "What are we doing here?", + "Review (Robin)": "Added N/A disclaimer. Striking it.", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt10", + "Feature": "Program Buffer", + "Sub Feature": "Ctrl. Transfer instr.", + "Feature Description": "All control transfer instructions may act as illegal instructions if destination is within program buffer. If one does, all must.", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt11", + "Feature": "Program Buffer", + "Sub Feature": "Ctrl. Transfer instr.", + "Feature Description": "All control transfer instructions may as illegal instructions if destination is outside the program buffer. If one does, all must.", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt12", + "Feature": "Program Buffer", + "Sub Feature": "Instr. Dependent of PC", + "Feature Description": "Instructions that depend on the PC may act as illegal instructions", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt13", + "Feature": "Program Buffer", + "Sub Feature": "Effective XLEN", + "Feature Description": "Effective XLEN = DXLEN", + "Verification Goal": "CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode\nMike: what exactly would a testcase actually do to check this?\n\u00d8K: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode\nMike: what exactly would a testcase actually do to check this?\n\u00d8K: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.2 Load-Reserved/Store-Conditional", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "N/A for CV32E40s (requires A-extention) : need Arjan/Davide to sign-off on this. [PZ] This is not a test but a warning or assumption that debug entry should not occur between a lr and sc instruction pair. Moreover, CV32E40s does not support A-extension", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.3 Wait for interrupt", + "Feature": "Debug mode", + "Sub Feature": "WFI instruction", + "Feature Description": "If debug_req_i is asserted while waiting for interrupt (core_sleep_o = 1), WFI instruction must complete (core_sleep_o -> 0) and hart enters debug mode.", + "Verification Goal": "Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Update reference document, applies to several following points", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_debug_req\nA: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req_wu\nA: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "By setting step in dcsr[2] before resuming execution, a debugger can cause the hart to execute a single instructin before re-entering debug mode.", + "Verification Goal": "Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the instruction being fetched or executed in a single step casues an exception, debug mode is entered immediately after the PC is changed to the exception handler and registers tval and cause are updated.\n\nNote: CV32E40S does not support tval (this might be supported in future cores)", + "Verification Goal": "Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode.\n\nCheck tval==0", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "Update to reflect that we are now checking \"future cores\"", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode.\n\nCheck tval==0", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_illegal)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_exception", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the instruction being fetched or executed in a single step causes a trigger, debug mode is entered immediately after the trigger fired. Cause is set to 2 instead of 4", + "Verification Goal": "Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_trigger_match)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the intruction executed in the single step results in a PC that will cause an exception, the exception will not execute until the next time the hart resumes.", + "Verification Goal": "Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the intruction executed in the single step results in a PC that will cause a trigger event, the trigger event will not take place until the instruction is executed.", + "Verification Goal": "This can be verified in the same steps as marked with (#1).\nMike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "This can be verified in the same steps as marked with (#1).\nMike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_next_pc_will_match)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the single step instruction is WFI, it must be treated as a nop instead of stalling and waiting for interrupt. [PZ] #pz_ref2", + "Verification Goal": "Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_wfi)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_wfi", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.5 Reset", + "Feature": "Debug mode", + "Sub Feature": "Reset", + "Feature Description": "When the hart comes out of reset, it must immediately enter debug mode without executing any instructions if the halt signal or debug_req_i is asserted.", + "Verification Goal": "Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_reset\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_at_reset\nA: uvmt_cv32_tb.u_debug_assert.a_debug_at_reset", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.6 dret instruction", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "Executing dret while NOT in debug mode will cause an illegal instruction exception.", + "Verification Goal": "Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown.\nCan be tested in the same test as for debug entry", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown.\nCan be tested in the same test as for debug entry", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret\nA: uvmt_cv32_tb.u_debug_assert.a_mumode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.6 dret instruction", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "Executing dret while in debug mode will restore PC to the value in dpc and exit debug mode.", + "Verification Goal": "Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. \nCan be tested in the same test as for debug entry.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "remove note, this is covered or 40s (U-Mode) in the next point", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. \nCan be tested in the same test as for debug entry.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret\nA: uvmt_cv32_tb.u_debug_assert.a_dmode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Execution Based", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "40S, \"When dret is executed, [\u2026] normal execution resumes at the privilege set by prv\"", + "Verification Goal": "Be in debug mode, note the value in \"dcsr.prv\", exit debug mode with a \"dret\", check that the mode being executed in is the one indicated by \"dcsr.prv\". (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode, note the value in \"dcsr.prv\", exit debug mode with a \"dret\", check that the mode being executed in is the one indicated by \"dcsr.prv\". (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Resume", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "40S, \"If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.\"", + "Verification Goal": "Be in debug mode, set \"dcsr.prv\" to U-mode, let \"mstatus.MPRV\" be set and clear (different runs), exit debug mode with a \"dret\", check that \"mstatus.MPRV\" ends up cleared. (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode, set \"dcsr.prv\" to U-mode, let \"mstatus.MPRV\" be set and clear (different runs), exit debug mode with a \"dret\", check that \"mstatus.MPRV\" ends up cleared. (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Debug Control and Status", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "\"Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in\"", + "Verification Goal": "40S, enter debug mode from different modes, check that \"dcsr.prv\" represents the previous mode. (Note overlap with user mode vplan.)\n\n40X, check that \"dcsr.prv\" is always M-mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "40S, enter debug mode from different modes, check that \"dcsr.prv\" represents the previous mode. (Note overlap with user mode vplan.)\n\n40X, check that \"dcsr.prv\" is always M-mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Semihosting", + "Sub Feature": "", + "Feature Description": "To enable semihosting, a special instruction sequence is needed as there is only a single EBREAK instruction available.\n\nslli x0, x0, 0x1f # Entry NOP\nebreak # Break to debugger\nsrai x0, x0, 7 # NOP encoding the semihosting call number 7\n\n[PZ] This is a software convention and need not be tested in verification. As long as the above instructions work in general, then no need for dedicated semihosting testing.", + "Verification Goal": "If all points above passes, there should be nothing to verify here. Semihosting will be handled from SW.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger", + "Sub Feature": "Exception handling", + "Feature Description": "If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address\n\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger, single step", + "Sub Feature": "Exception handling", + "Feature Description": "If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. \nSet up single stepping such that the match address will be executed in the next step.\nWhen the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger, single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. \nSet up single stepping such that the match address will be executed in the next step.\nWhen the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "With timing=0 the core will not attempt to execute instruction at trigger address\n\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0\n\nOBI-v1.4", + "Requirement Location": "Core Integration\n\ndbg", + "Feature": "OBI", + "Sub Feature": "", + "Feature Description": "OBI bus accesses shall indicate whether the core is in D-mode or not, signaled via \"instr_dbg_o\" and \"data_dbg_o\".", + "Verification Goal": "Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have \"dbg\" set correspondingly.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "OBI", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have \"dbg\" set correspondingly.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr_inv\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data_inv", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40S User Manual 0.8.0\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nDebug Control and Status", + "Feature": "NMI", + "Sub Feature": "", + "Feature Description": "The \"dcsr.nmip\" bit is supported.\nWhen a non-maskable interrupt is pending, then this bit must be high.", + "Verification Goal": "Cause an NMI to occur, read \"dcsr.nmip\", check that it is high as expected. Have no NMI pending, read \"dsr.nmip\", check that it is low.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "NMI", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Cause an NMI to occur, read \"dcsr.nmip\", check that it is high as expected. Have no NMI pending, read \"dsr.nmip\", check that it is low.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "40X/S user manual\n\nDebug 1.0.0\n\nPrivspec 1.12", + "Requirement Location": "Control and Status Registers\n\nDebug Control and Status\n\nMachine Status Registers", + "Feature": "MPRV", + "Sub Feature": "", + "Feature Description": "\"dcsr.mprven\" is WARL 1.\nSince \"mprven\" is 1, then \"mstatus.MPRV\" always takes effect in D-mode.", + "Verification Goal": "Read \"dcsr.mprven\", check that it is always 1.\n\n40S, be in debug mode, have \"mstatus.MPRV\" disabled, check that all instructions are treated as M-mode. Be in debug mode, have \"mstatus.MPRV\" enabled, have \"mstatus.MPP\" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "MPRV", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Read \"dcsr.mprven\", check that it is always 1.\n\n40S, be in debug mode, have \"mstatus.MPRV\" disabled, check that all instructions are treated as M-mode. Be in debug mode, have \"mstatus.MPRV\" enabled, have \"mstatus.MPP\" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Silabs Internal", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "Haltreq and stepping", + "Feature Description": "External debug requests and single stepping can only cause debug entry on \"instruction boundaries\", so a multi-step instruction cannot be interrupted by this.", + "Verification Goal": "While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "Synchronous entry", + "Feature Description": "Trigger matching can cause synchronous debug entry, and can interrupt \"within\" and instruction.", + "Verification Goal": "Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted \"midway\" and that debug mode is entered correctly.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted \"midway\" and that debug mode is entered correctly.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2\nCV32E40P doc rev 46711ac", + "Requirement Location": "4.8.1 DCSR\n\nControl and Status Registers", + "Feature": "Single step", + "Sub Feature": "Interrupts", + "Feature Description": "While single stepping, interrupts (maskable and non-maskable) may be enabled or disabled using the dcsr.stepie bit. ", + "Verification Goal": "Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (mmode_step_stepie)\nA: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure NMI is asserted while performing a step. Ensure that the NMI is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure NMI is asserted while performing a step. Ensure that the NMI is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.\n", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvmt_cv32_tb.u_debug_assert.cov_step_stepie_nmi\nA: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "Simultaneous Interrupt", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq\n\n\"NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\"\n\n\n", + "Review (Marton)": "What feature is this? Several points in this region lack context, or a merging of left hand cells", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "Simultaneous NMI", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "RISCV compliance", + "Sub Feature": "", + "Feature Description": "All RISCV code should run in debug mode as well as M mode", + "Verification Goal": "[PZ] Run RISCV compliance tests all in debug mode", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Waived", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Corner Cases", + "Feature Description": "", + "Verification Goal": "[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq\n (.irq_dreq_trig_ill/cebreak/ebreak/branch/multicycle)\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] Add coverage to ensure debug_req asserted on every FSM state", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] Have trigger address match an instruction that has an illegal instruction (both in normal and single step mode). Ensure debug is enterred with cause set to trigger and PC is set to exception handler prior to debug entry", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "Not possible with timing=0, core will not execute instruction at match address before entering debug mode.", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "If a debug_req_i is asserted when an illegal instructions is being executed, the address of the trap handler must be stored to dpc instead of the address of the illegal instruction", + "Verification Goal": "Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC debug_test_known_miscompares", + "Review (Marton)": "Lacks verification goal", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_illegal_insn_debug_req", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "Several causes exist for entering debug, the priority is specified in a table in the \"dcsr\" section of the debug spec.\n\nNote: This changed going to v1.0.0", + "Verification Goal": "Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Partly covered in DTC \"debug_test\" and \"debug_test_trigger\", the rest will be covered by corev_rand_debug_ebreak and corev_rand_debug_single_step", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.debug_causes\n (.trig_vs_ebreak, trig_vs_cebreak, trig_vs_dbg_req, trig_vs_step\n ebreak_vs_req, cebreak_vs_req, ebreak_vs_step, cebreak_vs_step, dbg_req_vs_step)", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "3-way Corners", + "Feature Description": "* Haltreq, then single-step ebreak\n* Single-step ebreak, then haltreq\n* Single-step ebreak with trigger\n* Single-step ebreak, then trigger on next instr\n* Haltreq, then ebreak with trigger\n* Haltreq, then ebreak, then trigger on next instr\n* Haltreq during ebreak with trigger\n* Haltreq during ebreak, then tirgger on next instr\n(More 3-way corners could be possible, see \"Generated Corners\" below.)", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "4-way Corners", + "Feature Description": "* Haltreq, then single-step ebreak with trigger\n* Haltreq, then single-step ebreak, then trigger on next instr\n* Single-step ebreak with trigger, then haltreq\n* Single-step ebreak, then haltreq and trigger on next instr\n(More 4-way corners could be possible, see \"Generated Corners\" below.)", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Generated Corners", + "Feature Description": "There are many corners", + "Verification Goal": "Write a covergroup with all events that can cause debug entry {haltreq, step, etc\u2026} and include timing aspects of first/then (\"e.g. haltreq right after step\", etc\u2026). Then, create a cross of all of these, as that should in principle generate all possible corners if written comprehensively. Finally, review if all of these corners are covered by the assertion set.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Dret", + "Feature Description": "https://github.com/openhwgroup/core-v-verif/issues/1476", + "Verification Goal": "Execute \"dret\" in M-mode, followed by a haltreq (as early as possible), so D-mode is entered before the exception handler. Ensure the rest of debug modelling has predictions on all csr and rvfi signals needed for checking this outcome.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "External debug request", + "Sub Feature": "Startup / clock gating", + "Feature Description": "When the reset signal is deasserted, but before the fetch_enable_i signal is active, the internal clock of the core is gated. The cv32e40p would not miss this request, but on the 40s haltreq is no longer sticky and so it should not cause debug entry.", + "Verification Goal": "Assert short (1 cycle) debug_req_i randomly after reset, before the core starts executing. Observe that the core does not enter debug mode but instead starts executing instructions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC debug_test_boot_set", + "Review (Marton)": "Deprecated as debug_req is now non-sticky", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "RISC-V Debug Support Version 1.0.0-STABLE 86e748abed738f8878707dc31fe2713f41868f2c", + "Requirement Location": "A.2 Execution Based", + "Feature": "Program Buffer", + "Sub Feature": "PMP", + "Feature Description": "\"the PMP must not disallow fetches, loads, or stores in the address range associated with the Debug Module when the hart is in Debug Mode, regardless of how the PMP is configured\"", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "Any verdict on this now?", + "Review (Robin)": "?", + "Review (Henrik)": "?", + "": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "", + "": "" + }, + { + "Reference document": "", + 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a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.xlsx b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.xlsx new file mode 100644 index 0000000000..8d884bdf1e Binary files /dev/null and b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv new file mode 100644 index 0000000000..5c5522108c --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv @@ -0,0 +1,414 @@ +Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage +CLIC 8675ec,Reset behavior,CSR reset value,mintstatus.mil resets to 0,"CSR value check after reset + +Do not implement in initial-block to include formal checking",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Reset behavior,CSR reset value,"mstatus.mie resets to 0 +","CSR value check after reset + +Do not implement in initial-block to include formal checking",Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Reset behavior,CSR reset value,"mtvec resets to {mtvec_addr_i[31:7]. 5'b0_0000, 2'b11}",Assert that mtvec resets to the correct initialization value,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Risc-V Priv. 1.12,Reset behavior,Interrupts never enabled out of reset,mstatus.mie resets to 0,Assert that interrupts are disabled and never taken immediately after deasserting reset,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Constraints,Privilege Modes,CLIC interrupts only support machine mode,"Assert that clic_irq_priv_i[1:0] is always 2'b11 +Assume on input for formal",Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Constraints,NMI,"NMI address is located at the 15th entry in the machine trap vector table, located at mtvec. In other words, nmi_addr = { mtvec[31:7], 5'b0_1111, 2'b00 }","Assert that nmi addr = { mtvec[31:7], 5'b0_1111, 2'b00 }",Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Constraints,Interrupts,Support up to a maximum of 1024 CLIC interrupts,Assert that SMCLIC_ID_WIDTH is inside { 1 .. 10 },Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Constraints,Interrupts,"Interrupt levels inside { 0, 2 .. 255 }",Correct functionality of interrupts of all valid levels,Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Constraints,Input ports,irq_i[31:0] tied to zero,Assert that non-clic irq[31:0] signals are tied to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Eventually taken,Interrupt taken,"An interrupt that is both pending and enabled shall be taken, unless if the core is in debug mode or is blocked by external interfaces (rvalid, fence_flush_ack, etc), and the taking happens within a fixed number of cycles","Check that when conditions are right, then the interrupt gets taken within expected time",Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Interrupt interface,Level sensitive,All interrupt lines are level-sensitive,All assertions and modeling of interrupts for checking assume no edges required to qualify an interrupt,Any/All,"ENV capability, not specific test",N/A, +Silabs Internal,Interrupt interface,Interrupt ack pulse,Interrupt acknowledge is always a pulse,Assert that irq_ack is always a pulse,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Interrupt interface,Interrupt ack valid,Interrupt acknowledge is only asserted when a valid interrupt has been taken by the core,irq_ack never asserted unless core has taken an interrupt,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Interrupt interface,NMI,NMI not reported on irq_ack,"Check that after an NMI is triggered, if there is no other interrupt occuring, then there should be no irq_ack",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Interrupt Interface,Interrupt ID is valid,Interrupt valid ID matches the active interrupt during the cycle where interrupt acknowledge is asserted,Ensure that irq_id is the active interrupt when irq_ack is asserted,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Interrupt Interface,Interrupt ID is never reserved,"Interrupt valid ID during interrupt acknowledge is never a reserved interrupt [15,14,13,12,10,9,8,6,5,4,2,1,0]",Assert irq_id is not a reserved valid when irq_ack is asserted,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Interrupt Interface,Single interrupt ack per ISR,Interrupt acknowledge only asserted once per interrupt,irq_ack only asserts once for an interrupt service period,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs internal,Interrupt interface,RVFI,Every irq_ack must be followed by a corresponding rvfi_intr,"Check that whenever and irq_ack occurs, then the next rvfi retired instruction must have rvfi interrupt set correctly",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Interrupt CSR,mclicbase,12 least significant bits hardwired to zero,"Assert mclicbase[11:0] = 0 + +Note: This register will possibly be removed in the future",Assertion Check,"ENV capability, not specific test",functional Coverage, +CLIC 8675ec,Interrupt CSR,mstatus.mpp,mstatus.mpp accessible through mcause.mpp,Read/Write mpp to mcause.mpp and read back through mstatus.mpp,Self Checking Test,Directed Self-Checking,Testcase, +CLIC 8675ec,Interrupt CSR,mcause.mpp,mcause.mpp accessible through mstatus.mpp,Read/Write mpp to mstatus.mpp and read back through mcause.mpp,Self Checking Test,Directed Self-Checking,Testcase, +CLIC 8675ec,Interrupt CSR,mstatus.mpie,mstatus.mpie accessible through mcause.mpie,Read/Write mpp to mcause.mpie and read back through mstatus.mpie,Self Checking Test,Directed Self-Checking,Testcase, +CLIC 8675ec,Interrupt CSR,mcause.mpie,mcause.mpie accessible through mstatus.mpie,Read/Write mpp to mstatus.mpie and read back through mcause.mpie,Self Checking Test,Directed Self-Checking,Testcase, +CLIC 8675ec,Interrupt CSR,mie,mie not used and hardwired to zero,Assert that mie always appears as hardwired 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mie,Writes to mie should not trap,Attempt writes to mie and ensure that 0 is read back,Self Checking Test,Directed Self-Checking,Testcase, +CLIC 8675ec,Interrupt CSR,mip,mip not used and hardwired to zero,Assert that mip always appears as hardwired 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mip,Writes should not trap,Attempt writes to mip and ensure that 0 is read back,Self Checking Test,Directed Self-Checking,Testcase, +UM v0.3.0 Common,Interrupt CSR,mtvec,Always aligned to 128 bytes,Assert that mtvec[6:2] always zero,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Interrupt CSR,mtvec,Always in CLIC mode (I.e. model can not switch between interrupt modes),Assert that mtvec.mode is always 2'b11 when CLIC is enabled,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Silabs Internal,Interrupt CSR,mtvt,Memory writes to the vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.,Verify that a fence.i instruction after writes to the vector table guarantees that the new vector table pointer taken matches the latest pointer written to the vector table.,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mtvt,"Function ptr reads treated as instruction fetch, adhering to configured PMA settings +(CV32E40S): PMP settings apply as for any other instruction fetch","Assert that interrupts accessing the vector table pointers do so through the instruction interface, and that a lack of PMP execute and PMA main-memory settings causes the instruction fetch to fail. + +Note, instruction fetch is treated as an implicit read, thus do not require PMP read permissions, but execute permission is required. + +Both the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ",Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Interrupt CSR,mtvt,"Always aligned to 2^(max(6, 2+SMCLIC_ID_WIDTH)","Assert that mtvt [max(6, 2+SMCLIC_ID_WIDTH)-1:0] = 0",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mtvt,"Determine alignment by software access, +Write ones to lower order bits and read back",Test that correct alignment can be inferred by writing to these fields and read back.,Self Checking Test,Directed Self-Checking,Testcase, +CLIC 8675ec,Interrupt CSR,mepc,The CSR mepc is set to the PC of the interrupted application code or preempted interrupt handler,"Ensure that MEPC in ISR is value of saved PC. +",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Risc-V Priv. 1.12,Interrupt CSR,mcause,mcause.interrupt flag always set during ISR regardless of the active interrupt,mcause[31] is set when an interrupt is taken,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mcause,mcause.exccode is set to the active interrupt code,mcause.exccode reflects the taken interrupt,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mcause,mcause.mpil: Previous interrupt level,mpil reflects the previous privilege level,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mcause,mcause.mpp: Previous privilege mode,Ensure that mcause.mpp reflects mstatus.mpp previous privilege mode after taking a trap,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mcause,mcause.mpie: Previous interrupt enable,Ensure that mcause.mpie reflects mstatus.mpie previous interrupt enable value after taking a trap,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: + +Case 1: +""The II is still the ranking interrupt (no change). In this case, as the level of the II will still be higher than pil from the OIC, xil and exccode will be rewritten with the same value that they already had (effectively unchanged), and xnxti will return the table entry for the II."" + +(II: Initital interrupt, +OIC: Original interrupted context)",Assert that mnxti returns the table entry for the initial interrupt when the current interrupt is still being signalled to the core as the highest enabled and pending interrupt.,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: + +Case 2: +""The II has been superceded by a higher-level non-SHV interrupt. In this case, xil will be set to the new higher interrupt level, exccode will be updated to the new interrupt id, and xnxti will return the vector table entry for the new higher-level interrupt. The OIC is not disturbed, retaining the original epc and the original pil. This case reduces latency to service a more-important interrupt that arrives after the state-save sequence was begun for the less-important II. The II, if still pending-enabled, will be serviced sometime after the higher-level interrupt as described below.""","Assert that mnxti returns the table entry for the new higher-level interrupt when the current interrupt is being interrupted by a higher level, non-shv interrupt",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: + +Case 3: +""The II has been superceded by a higher-priority non-SHV interrupt at the same level. This operates similarly to the previous case, with exccode updated to the new interrupt id. Because the lower-priority interrupt had not begun to run its service routine, this optimization preserves the property that interrupt handlers at the same interrupt level but different priorities execute atomically with respect to each other (i.e., they do not preempt each other).""","Only machine mode interrupts are supported, an interrupt of the same level but higher priority cannot occur +",N/A,N/A,N/A, +CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: + +Case 4: +""The II has disappeared and a lower-ranked non-SHV interrupt, which has interrupt level greater than the OIC’s pil is present in CLIC. In this case, the xil of the handler will be reduced to the lower-ranked interrupt’s level, exccode will be updated with the new interrupt id, and xnxti will return a pointer to the appropriate handler in table. In this case, the new lower-ranked interrupt would still have caused the original context to have been interrupted to run the handler, and the disappearing II has simply caused the lower-ranked interrupt’s entry and state-save sequence to begin earlier.""","Assert that mnxti returns the table entry for the new lower-level interrupt when the current interrupt is no longer present in the CLIC, and replaced by a new lower-leveled interrupt, with a greater interrupt level than the original interrupted context's pil",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: + +Case 5: +""The II has disappeared and either there is no current interrupt from the CLIC, or the current ranking interrupt is a non-SHV interrupt with level lower than xpil. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. The following trampoline code will then not fetch a vector from the table, and instead just restore the OIC context and mret back to it. This preserves the property that the OIC completes execution before servicing any new interrupt with a lower or equal interrupt level.""","Ensure that mnxti returns 0 in case the initial interrupt is no longer signalled, nor replaced by a new interrupt from the CLIC",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: + +Case 6: +""The II has been superceded by a higher-level SHV interrupt. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. Once interrupts are reenabled for the following instruction, the hart will preempt the current handler and execute the vectored interrupt at a higher interrupt level using the function pointer stored in the vector table.""",Assert that mnxti will return 0 in case of a higher-leveled SHV interrupt pending,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.9.0 Common,Interrupt CSR,mintstatus,"R/O CSR, Holds active interrupt level for each supported privilege mode","Assert that the mil field gets updated with the current interrupt level when an interrupt is taken, and that sil and uil-fields are hard-coded zero. + +Note: NMIs explicitly leave ""mintstatus"" unchanged.",Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,CSR,CSR access,CSR registers should be accessible as defined in UM,"Add new CLIC-specific registers to CSR access tests and ensure that the registers and their fields can be read/written according to specification + +mtvt +mnxti +mintstatus +mintthresh +mscratchcsw +mscratchcswl + +Note: ""mclicbase"" was removed. +Note: ""mintstatus"" got moved.",Self Checking Test,Directed Self-Checking,Testcase, +CLIC 8675ec,Interrupt CSR,Hardware vectoring,mcause.minhv: Set at start of hw vectoring,Assert that mcause.minhv is set when a hw-vectored interrupt is taken,Assertion Check,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt CSR,Hardware vectoring,mcause.minhv: Cleared at end of hw vectoring,Assert that mcause.minhv is cleared when pointer fetch of hw-vectored interrupt is taken successfully,Assertion Check,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt Vector,Hardware vectoring,"Exception on fetch: +mepc : set to faulting address (pointer, rather than address for an instruction) +mcause: exception type","Write invalid (not pointing to a valid instruction or a region with pmp restricted execute access) pointer to the mtvt table, and trigger this handler. +",Check against RM,Directed Non-Self-Checking,Testcase, +Silabs Internal,Interrupt Vector,Hardware vectoring,Prefetcher: no prefetches between pointer fetch and fetch of final vectored target,Assert that no new instructions get fetched that does not match the final vectored target after a pointer fetch is attempted,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt Vector,Hardware vectoring,Interrupt executes trap handler function pointer located at the address specified in mtvt when shv = 1,"Assert that first pc after a taken, shv interrupt always matches address fetched from mtvt +",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt Vector,Hardware vectoring,Interrupt jumps to common code at mtvec when shv = 0,Assert that first pc after a taken non-shv interrupt matches ,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Interrupt Vector,PC,"non-shv: taken trap handler always has address[6:0] = 0; +implied by mtvec alignment restriction","Assert that first pc after a taken, non-shv interrupt always has bits [6:0] = 0 +",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Interrupt arbitration,Interrupts ignored,"Interrupts ignored when +new privilege mode (nP) lower than current privilege mode (P)","Not allowed, assuming clic_irq_priv_i always = 2'b11 +Covered by assertion that asserts that clic_irq_priv_i is always 2'b11 in sim and assumed in formal",N/A,N/A,N/A, +CLIC 8675ec,Interrupt arbitration,Interrupts ignored,"Interrupts ignored when +new privilege mode (nP) = current privilege mode(P) and new interrupt level (nL) != 0 and nL < current interrupt level (L)","During constrained random testing, the following should be true + +Current privilege mode: M-mode +Inside interrupt handler (Nested) + +clic_irq_i = 1 +clic_irq_id_i = random 0 .. max_index +clic_irq_lvl > 0 and < current level +clic_irq_priv_i = 2'b11 assumed always true +clic_irq_shv_i = random 0 .. 1 + +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt arbitration,Interupts disabled,"Interrupts disabled when +mtatus.mie and clicintie[i] = 0","mstatus.mie = 0 should disallow any pending and enabled interrupts from being taken as we only have one level where interrupts can be taken (M-mode), so no other higher modes exist + +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt arbitration,No interrupt,"No interrupt when +new privilege mode (nP) = current privilege mode (P) +clic.level = 0 + +P, nP in M, U","During constrained random testing, the following should be true + +Current privilege mode: M-mode (Cannot signal U-mode) +Test in both nested and non-nested cases + +clic_irq_i = 1 +clic_irq_id_i = random 0 .. max index +clic_irq_lvl = 0 +clic_irq_priv_i = 2'b11 assumed always true +clic_irq_shv_i = random 0 .. 1 + +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt arbitration,No interrupt,"No interrupt when +new privilege mode (nP) > current privilege mode (P) +clic.level = 0 + +nP = M, P = U, clic.level = 0 +(CV32E40S)","During constrained random testing, the following should be true + +Current privilege mode: U-mode +Test for both nested and non-nested cases + +clic_irq_i = 1 +clic_irq_id_i = random 0 .. max_index +clic_irq_lvl = 0 +clic_irq_priv_i = 2'b11 assumed always true +clic_irq_shv_i = random 0 .. 1 + +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt arbitration,"Horizontal interrupt taken +(Nested)","Horizontal interrupt taken when +mtatus.mie and clicintie[i] = 1 +new privilege mode (nP) = current privilege mode (P) +new privilege level (nL) > current privilege level (L) + +Only applicable for M-mode (P, nP = M) as horizontal user mode traps are not supported (N-extension) in neither CV32E40X nor S","During constrained random testing, the following should be true + +Current privilege mode: M-mode (Cannot signal U-mode) + +clic_irq_i = 1 +clic_irq_id_i = random 0 .. max_index +clic_lvl > current_lvl +clic_irq_priv_i = 2'b11 assumed always true +clic_irq_shv_i = random 0 .. 1 + +Check that an interrupt that should be taken under the given circumstances always get taken +Check that system behaves correctly when a pending and enabled interrupt gets taken",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt arbitration,Vertical interrupt taken,"Vertical interrupt taken when +new privilege mode (nP) > current privilege mode (P) +new privilege level (nL) > 0 + +nP = M, P = U + +(CV32E40S)","During constrained random testing, the following should be true + +Current privilege mode: U-mode + +clic_irq_i = 1 +clic_irq_id_i = random 0 .. max_index +clic_lvl > 0 +clic_irq_priv_i = 2'b11 assumed always true +clic_irq_shv_i = random 0 .. 1 + +Check that an interrupt that should be taken under the given circumstances always gets taken +Check that the system behaves correctly when a pending and enabled interrupt gets taken",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,Interrupt arbitration,Interrupt taken,"mstatus.mie = 1 +nP = P = M +nL > L + +or + +nP > P (i.e. nP = M, P = U) +nL > 0",Assert that an interrupt is taken if and only if any of the two conditions are true,Assertion Check,"ENV capability, not specific test",Assertion Coverage, +CLIC 8675ec,Interrupt preemption,mintthresh,Higher level interrupts than mintthresh.th can preempt execution,Assert that interrupts with the same privilege mode and higher privilege level than the running ISR can interrupt the currently running ISR,Assertion Check,"ENV capability, not specific test",Assertion Coverage, +CLIC 8675ec,Interrupt preemption,mintthresh,Lower level interrupts than mintthresh.th cannot preempt execution,Assert that interrupts with the same privilege mode and lower privilege level than the running ISR cannot interrupt the currently running ISR,Assertion Check,"ENV capability, not specific test",Assertion Coverage, +CLIC 8675ec,WFI resume,Resumes,"when +nP > P +interrupt is highest among pending-and-enabled interrupts +i.level != 0 + +nP = M, P = U + +(CV32E40S)","clic_irq_i = 1 +clic_irq_lvl > 0 +P = U +nP = M",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,WFI resume,Resumes,"when +nP = P +interrupt is highest among pending-and-enabled interrupts +i.level > max(xintstatus.xil, xintthresh.th) + +(xintthresh only applies to current privilege mode) +nP, P = M","clic_irq_i = 1 +clic_irq_lvl > max(mintstatus.mil, mintthresh.th) +P, nP = M + +Test that only interrupts with a sufficiently high interrupt level are able to preempt execution with both true or temporarily risen interrupt level",Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,WFI resume,Resumes,"nP < P +interrupt is highest among pending-and-enabled interrupts +i.level != 0 + +Can not occur 40S/40X as new privilege mode signalled on the CLIC interface can never be less than current privilege mode","nP < P cannot occur as we assume clic_irq_lvl = 2'b11 + +No test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs",N/A,N/A,N/A, +CLIC 8675ec,WFI resume,Ignores,Everything not covered above,Core does not resume operation unless any of the above resume conditions are true,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Interrupt instruction,Killed instructions have no side-effects,"When an instruction is interrupted, it is killed, meaning that it has no side-effects: 1) load/store instructions don't reach the bus, 2) control transfer instructions don't jump, 3) CSRs don't get updated, 4) GPRs don't get updated","Check that bus, jumps, and registers are unaffected by killed instructions",Check against RM,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Return from handler,mret,"Execution continues at +Privilege mode = mcause.mpp +pc = mepc +interrupt level = mcause.mpil +global interrupt enable mie = mcause.mpie + +mcause.mpil unchanged +mcause.mpp = least privileged mode +mcause.mpie = 1",Correct update of CSR values when core returns from an ISR,Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,Return from handler,mret,"Execution continues at +P = mcause.mpp +pc = mepc +L = mcause.mpil +ie = mcause.mpie + +mcause.mpil unchanged +mcause.mpp = least privileged mode +mcause.mpie = 1","Correct update of CSR values when core returns from an ISR +Added assertion for formal coverage",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 0.9-draft 4/11/2023,Return from handler,mret,"""If the hart is currently running at some privilege mode x, an MRET or SRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.""","Use ""mret"" to enter U-mode. +Check that ""mintthresh"" is written to zero upon executing the mret.",Assertion Check,"ENV capability, not specific test",Assertion Coverage, +CLIC 0.9-draft 4/11/2023,Return from debug mode,dret,"""Likewise, if the RISC-V debug specification is implemented and the hart is currently running at some privilege mode x, a DRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.""","Use ""dret"" to enter U-mode. +Check that ""mintthresh"" is written to zero upon executing the dret.",Assertion Check,"ENV capability, not specific test",Assertion Coverage, +CLIC 8675ec,WFI,Wakeup conditions,"A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i +• has a higher privilege mode than the current privilege mode and +• the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled +interrupts and +• the interrupt i level is not equal to 0.",Test that interrupts of higher privilege modes than the current privilege mode can wakeup the core from wfi,Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,WFI,Wakeup conditions,"A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i + • has the same privilege mode as the current privilege mode and + • the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and + • the interrupt i level is greater than max(xintstatus.xil, xintthresh.th )",Test that interrupts of higher privilege level than the current privilege level can wake the core from WFI,Check against RM,Constrained-Random,Functional Coverage, +CLIC 8675ec,WFI,Wakeup conditions,"A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i +• has a lower privilege mode than the current privilege mode and +• the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and +• the interrupt i level is not equal to 0.","nP < P cannot occur as we assume clic_irq_lvl = 2'b11 + +No test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs",N/A,N/A,N/A, +CLIC 8675ec,WFI,Wakeup conditions,Core only wakes up if any of the conditions mentioned above is true,Assert that core remains in WFI mode unless correct wakeup conditions occur,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,WFI ,Entry,Execution of WFI causes the core to stop,In normal execution the core stop within a certain time period after execution.,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,WFI ,Clock gating,WFI entry causes the clock to be gated,The core is not clocked during WFI,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,WFI ,Output signal,core_sleep_o output signal is only asserted during active WFI,Assert the proper operation of core_sleep_o,Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Synchronous exception handling,Horizontal synchronous exception traps,Serviced at same privilege mode with same interrupt level as instruction that raised exception ,"Assert that interrupt level is not changed when entering the exception handler +(Can only occur in machine mode)",Assertion Check,"ENV capability, not specific test",Functional Coverage, +CLIC 8675ec,Synchronous exception handling,Vertical synchronous exception traps,"Serviced at higher privilege mode at interrupt level 0 in the higher privilege mode + +(CV32E40S)",Assert that user mode traps are taken in machine mode with interrupt level 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + WFI,Proper interactions between interrupts and WFI,"Corner case + +Test random combinations of streams containing WFI-instructions with random interrupt requests",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Back to back WFI,Correct interactions between interrupts and back-to-back WFI instructions,"Corner case + +In embedded context WFI is used often, ensure that WFI can be re-entered ASAP after servicing a ISR for a previous WFI",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Debug,Correct interaction between interrupts and debug,"Corner case +Test random streams of instructions interrupted by debug and random interrupt requests. +Goal is to verify that interrupts are never taken in debug mode, and that interrupt- and debug transitions are handled correctly + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Exceptions,Correct interaction between interrupts and exceptions,"Corner case +Test random streams of instructions interrupted by exceptions and random interrupt requests. +Generated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten) + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Bus Error,Correct interaction between interrupts and bus errors,"Corner case +Test random streams of instructions interrupted by random interrupt requests and random bus errors. Aims to verify that interrupts and bus errors are correctly prioritized by the system. + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Debug + Bus Error,"Correct interaction between interrupts, debug and bus errors +","Corner case +Test random streams of instructions, + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Debug + WFI,"Correct interaction between interrupts, debug and WFI +","Test random instruction streams containing WFI, where control flow changes occur due to random debug requests and random interrupts + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Debug + WFI + Bus Error,"Correct interaction between interrupts, debug, wfi and bus errors","Test random instruction streams containing WFI instructions, where control flow changes occur due to random debug requests, random bus errors, random interrupts + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Interrupt + Debug + WFI + Bus Error + Exceptions,Correct interaction between all trap sources,"Trap priority stress test +Test random streams containing all trap sources to verify correct behavior + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Nested Interrupts,Correct interactions between nested interrupts,"Verify potential corner case + +Implement nested ISR. Randomly modify mintthresh.th to mask out certain interrupts and randomly trigger new interrupts with higher or lower priority to verify that interrupts with a higher privilege level are allowed to preempt + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Nested Interrupts + exceptions,Correct interactions between nested interrupts and exceptions,"Verify potential corner case +Same as nested interrupts, but random streams include randomly inserted exception-causing instructions +Generated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten) + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Nested interrupts + Debug,Correct interactions between nested interrupts and debug,"Verify potential corner case +Same as nested interrupts, but random streams also gets control flow modified by random debug requests. + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Nested Interrupts + Debug + Bus Error," +Correct interactions between nested inteerrupts, debug and bus-errors","Verify potential corner case +Same as nested interrupts with debug, but also includes random bus errors + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Nested interrupts + Debug + WFI,"Correct interactions between nested interrupts, debug and WFI","Verify potential corner case +Same as nested interrupts with debug, but the instruction stream should also include WFI instructions. + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +UM v0.3.0 Common,Trap priority,Nested interrupts + Debug + WFI + Bus Error + Exceptions,Correct interactions between nested interrupts and all other trap types,"Verify potential corner case +Test nested interrupts with randomly traps (all types) +Generated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten) + +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Load instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Store instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Shift instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit logical instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit compare instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit jump instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit FENCE instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit system instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BEQ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken BEQ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BNE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken BNE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BLT instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken BLT instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BGE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken BGE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BLTU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken BLTU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BGEU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken BGEU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit load instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit store instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit arithmetic instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit shift instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit jump instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit system instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken C.BEQZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken C.BEQZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Nontaken C.BNEZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Taken C.BNEZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 M instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zba instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbb instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbc instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbs instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zicsr instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zifencei instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zc instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zca instructions interrupted +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zcb instructions interrupted +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zcmb instructions interrupted +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zcmt instructions interrupted +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zcmp instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,Illegal instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32 A instructions interrupted +(CV32E40X)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All X interface instructions interrupted +(CV32E40X)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32F instructions interrupted +(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32 P instructions interrupted +(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Risc-V Priv. 1.12,Interrupt instruction,"All RV32V instructions interrupted +(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +,,,,,,,, +,,,,,,,, +,,,,,,,, +,,,,,,,, + ---- END ----,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json new file mode 100644 index 0000000000..4b8759ad3c --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json @@ -0,0 +1,1663 @@ +[ + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mintstatus.mil resets to 0", + "Verification Goal": "CSR value check after reset\n\nDo not implement in initial-block to include formal checking", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mstatus.mie resets to 0\n", + "Verification Goal": "CSR value check after reset\n\nDo not implement in initial-block to include formal checking", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mtvec resets to {mtvec_addr_i[31:7]. 5'b0_0000, 2'b11}", + "Verification Goal": "Assert that mtvec resets to the correct initialization value", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Reset behavior", + "Sub Feature": "Interrupts never enabled out of reset", + "Feature Description": "mstatus.mie resets to 0", + "Verification Goal": "Assert that interrupts are disabled and never taken immediately after deasserting reset", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Privilege Modes", + "Feature Description": "CLIC interrupts only support machine mode", + "Verification Goal": "Assert that clic_irq_priv_i[1:0] is always 2'b11\nAssume on input for formal", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "NMI", + "Feature Description": "NMI address is located at the 15th entry in the machine trap vector table, located at mtvec. In other words, nmi_addr = { mtvec[31:7], 5'b0_1111, 2'b00 }", + "Verification Goal": "Assert that nmi addr = { mtvec[31:7], 5'b0_1111, 2'b00 }", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Interrupts", + "Feature Description": "Support up to a maximum of 1024 CLIC interrupts", + "Verification Goal": "Assert that SMCLIC_ID_WIDTH is inside { 1 .. 10 }", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Interrupts", + "Feature Description": "Interrupt levels inside { 0, 2 .. 255 }", + "Verification Goal": "Correct functionality of interrupts of all valid levels", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Input ports", + "Feature Description": "irq_i[31:0] tied to zero", + "Verification Goal": "Assert that non-clic irq[31:0] signals are tied to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Eventually taken", + "Sub Feature": "Interrupt taken", + "Feature Description": "An interrupt that is both pending and enabled shall be taken, unless if the core is in debug mode or is blocked by external interfaces (rvalid, fence_flush_ack, etc), and the taking happens within a fixed number of cycles", + "Verification Goal": "Check that when conditions are right, then the interrupt gets taken within expected time", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt interface", + "Sub Feature": "Level sensitive", + "Feature Description": "All interrupt lines are level-sensitive", + "Verification Goal": "All assertions and modeling of interrupts for checking assume no edges required to qualify an interrupt", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "Interrupt ack pulse", + "Feature Description": "Interrupt acknowledge is always a pulse", + "Verification Goal": "Assert that irq_ack is always a pulse", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "Interrupt ack valid", + "Feature Description": "Interrupt acknowledge is only asserted when a valid interrupt has been taken by the core", + "Verification Goal": "irq_ack never asserted unless core has taken an interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "NMI", + "Feature Description": "NMI not reported on irq_ack", + "Verification Goal": "Check that after an NMI is triggered, if there is no other interrupt occuring, then there should be no irq_ack", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Interrupt ID is valid", + "Feature Description": "Interrupt valid ID matches the active interrupt during the cycle where interrupt acknowledge is asserted", + "Verification Goal": "Ensure that irq_id is the active interrupt when irq_ack is asserted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Interrupt ID is never reserved", + "Feature Description": "Interrupt valid ID during interrupt acknowledge is never a reserved interrupt [15,14,13,12,10,9,8,6,5,4,2,1,0]", + "Verification Goal": "Assert irq_id is not a reserved valid when irq_ack is asserted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Single interrupt ack per ISR", + "Feature Description": "Interrupt acknowledge only asserted once per interrupt", + "Verification Goal": "irq_ack only asserts once for an interrupt service period", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs internal", + "Feature": "Interrupt interface", + "Sub Feature": "RVFI", + "Feature Description": "Every irq_ack must be followed by a corresponding rvfi_intr", + "Verification Goal": "Check that whenever and irq_ack occurs, then the next rvfi retired instruction must have rvfi interrupt set correctly", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt CSR", + "Sub Feature": "mclicbase", + "Feature Description": "12 least significant bits hardwired to zero", + "Verification Goal": "Assert mclicbase[11:0] = 0 \n\nNote: This register will possibly be removed in the future", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mstatus.mpp", + "Feature Description": "mstatus.mpp accessible through mcause.mpp", + "Verification Goal": "Read/Write mpp to mcause.mpp and read back through mstatus.mpp", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause.mpp", + "Feature Description": "mcause.mpp accessible through mstatus.mpp", + "Verification Goal": "Read/Write mpp to mstatus.mpp and read back through mcause.mpp", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mstatus.mpie", + "Feature Description": "mstatus.mpie accessible through mcause.mpie", + "Verification Goal": "Read/Write mpp to mcause.mpie and read back through mstatus.mpie", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause.mpie", + "Feature Description": "mcause.mpie accessible through mstatus.mpie", + "Verification Goal": "Read/Write mpp to mstatus.mpie and read back through mcause.mpie", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mie", + "Feature Description": "mie not used and hardwired to zero", + "Verification Goal": "Assert that mie always appears as hardwired 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mie", + "Feature Description": "Writes to mie should not trap", + "Verification Goal": "Attempt writes to mie and ensure that 0 is read back", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mip", + "Feature Description": "mip not used and hardwired to zero", + "Verification Goal": "Assert that mip always appears as hardwired 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mip", + "Feature Description": "Writes should not trap", + "Verification Goal": "Attempt writes to mip and ensure that 0 is read back", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvec", + "Feature Description": "Always aligned to 128 bytes", + "Verification Goal": "Assert that mtvec[6:2] always zero", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvec", + "Feature Description": "Always in CLIC mode (I.e. model can not switch between interrupt modes)", + "Verification Goal": "Assert that mtvec.mode is always 2'b11 when CLIC is enabled", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Memory writes to the vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.", + "Verification Goal": "Verify that a fence.i instruction after writes to the vector table guarantees that the new vector table pointer taken matches the latest pointer written to the vector table.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Function ptr reads treated as instruction fetch, adhering to configured PMA settings \n(CV32E40S): PMP settings apply as for any other instruction fetch", + "Verification Goal": "Assert that interrupts accessing the vector table pointers do so through the instruction interface, and that a lack of PMP execute and PMA main-memory settings causes the instruction fetch to fail.\n\nNote, instruction fetch is treated as an implicit read, thus do not require PMP read permissions, but execute permission is required.\n\nBoth the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Always aligned to 2^(max(6, 2+SMCLIC_ID_WIDTH)", + "Verification Goal": "Assert that mtvt [max(6, 2+SMCLIC_ID_WIDTH)-1:0] = 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Determine alignment by software access,\nWrite ones to lower order bits and read back", + "Verification Goal": "Test that correct alignment can be inferred by writing to these fields and read back.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mepc", + "Feature Description": "The CSR\u00a0mepc\u00a0is set to the PC of the interrupted application code or preempted interrupt handler", + "Verification Goal": "Ensure that MEPC in ISR is value of saved PC.\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.interrupt flag always set during ISR regardless of the active interrupt", + "Verification Goal": "mcause[31] is set when an interrupt is taken", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.exccode is set to the active interrupt code", + "Verification Goal": "mcause.exccode reflects the taken interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpil: Previous interrupt level", + "Verification Goal": "mpil reflects the previous privilege level", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpp: Previous privilege mode", + "Verification Goal": "Ensure that mcause.mpp reflects mstatus.mpp previous privilege mode after taking a trap", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpie: Previous interrupt enable", + "Verification Goal": "Ensure that mcause.mpie reflects mstatus.mpie previous interrupt enable value after taking a trap", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 1:\n\"The II is still the ranking interrupt (no change). In this case, as the level of the II will still be higher than pil from the OIC, xil and exccode will be rewritten with the same value that they already had (effectively unchanged), and xnxti will return the table entry for the II.\"\n\n(II: Initital interrupt,\nOIC: Original interrupted context)", + "Verification Goal": "Assert that mnxti returns the table entry for the initial interrupt when the current interrupt is still being signalled to the core as the highest enabled and pending interrupt.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 2:\n\"The II has been superceded by a higher-level non-SHV interrupt. In this case, xil will be set to the new higher interrupt level, exccode will be updated to the new interrupt id, and xnxti will return the vector table entry for the new higher-level interrupt. The OIC is not disturbed, retaining the original epc and the original pil. This case reduces latency to service a more-important interrupt that arrives after the state-save sequence was begun for the less-important II. The II, if still pending-enabled, will be serviced sometime after the higher-level interrupt as described below.\"", + "Verification Goal": "Assert that mnxti returns the table entry for the new higher-level interrupt when the current interrupt is being interrupted by a higher level, non-shv interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 3: \n\"The II has been superceded by a higher-priority non-SHV interrupt at the same level. This operates similarly to the previous case, with exccode updated to the new interrupt id. Because the lower-priority interrupt had not begun to run its service routine, this optimization preserves the property that interrupt handlers at the same interrupt level but different priorities execute atomically with respect to each other (i.e., they do not preempt each other).\"", + "Verification Goal": "Only machine mode interrupts are supported, an interrupt of the same level but higher priority cannot occur\n", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 4:\n\"The II has disappeared and a lower-ranked non-SHV interrupt, which has interrupt level greater than the OIC\u2019s pil is present in CLIC. In this case, the xil of the handler will be reduced to the lower-ranked interrupt\u2019s level, exccode will be updated with the new interrupt id, and xnxti will return a pointer to the appropriate handler in table. In this case, the new lower-ranked interrupt would still have caused the original context to have been interrupted to run the handler, and the disappearing II has simply caused the lower-ranked interrupt\u2019s entry and state-save sequence to begin earlier.\"", + "Verification Goal": "Assert that mnxti returns the table entry for the new lower-level interrupt when the current interrupt is no longer present in the CLIC, and replaced by a new lower-leveled interrupt, with a greater interrupt level than the original interrupted context's pil", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 5:\n\"The II has disappeared and either there is no current interrupt from the CLIC, or the current ranking interrupt is a non-SHV interrupt with level lower than xpil. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. The following trampoline code will then not fetch a vector from the table, and instead just restore the OIC context and mret back to it. This preserves the property that the OIC completes execution before servicing any new interrupt with a lower or equal interrupt level.\"", + "Verification Goal": "Ensure that mnxti returns 0 in case the initial interrupt is no longer signalled, nor replaced by a new interrupt from the CLIC", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 6:\n\"The II has been superceded by a higher-level SHV interrupt. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. Once interrupts are reenabled for the following instruction, the hart will preempt the current handler and execute the vectored interrupt at a higher interrupt level using the function pointer stored in the vector table.\"", + "Verification Goal": "Assert that mnxti will return 0 in case of a higher-leveled SHV interrupt pending", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.9.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mintstatus", + "Feature Description": "R/O CSR, Holds active interrupt level for each supported privilege mode", + "Verification Goal": "Assert that the mil field gets updated with the current interrupt level when an interrupt is taken, and that sil and uil-fields are hard-coded zero.\n\nNote: NMIs explicitly leave \"mintstatus\" unchanged.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "CSR", + "Sub Feature": "CSR access", + "Feature Description": "CSR registers should be accessible as defined in UM", + "Verification Goal": "Add new CLIC-specific registers to CSR access tests and ensure that the registers and their fields can be read/written according to specification\n\nmtvt\nmnxti\nmintstatus\nmintthresh\nmscratchcsw\nmscratchcswl\n\nNote: \"mclicbase\" was removed.\nNote: \"mintstatus\" got moved.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "Hardware vectoring", + "Feature Description": "mcause.minhv: Set at start of hw vectoring", + "Verification Goal": "Assert that mcause.minhv is set when a hw-vectored interrupt is taken", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "Hardware vectoring", + "Feature Description": "mcause.minhv: Cleared at end of hw vectoring", + "Verification Goal": "Assert that mcause.minhv is cleared when pointer fetch of hw-vectored interrupt is taken successfully", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Exception on fetch:\nmepc : set to faulting address (pointer, rather than address for an instruction)\nmcause: exception type", + "Verification Goal": "Write invalid (not pointing to a valid instruction or a region with pmp restricted execute access) pointer to the mtvt table, and trigger this handler. \n", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Prefetcher: no prefetches between pointer fetch and fetch of final vectored target", + "Verification Goal": "Assert that no new instructions get fetched that does not match the final vectored target after a pointer fetch is attempted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Interrupt executes trap handler function pointer located at the address specified in mtvt when shv = 1", + "Verification Goal": "Assert that first pc after a taken, shv interrupt always matches address fetched from mtvt\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Interrupt jumps to common code at mtvec when shv = 0", + "Verification Goal": "Assert that first pc after a taken non-shv interrupt matches ", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt Vector", + "Sub Feature": "PC", + "Feature Description": "non-shv: taken trap handler always has address[6:0] = 0;\nimplied by mtvec alignment restriction", + "Verification Goal": "Assert that first pc after a taken, non-shv interrupt always has bits [6:0] = 0\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupts ignored", + "Feature Description": "Interrupts ignored when \nnew privilege mode (nP) lower than current privilege mode (P)", + "Verification Goal": "Not allowed, assuming clic_irq_priv_i always = 2'b11\nCovered by assertion that asserts that clic_irq_priv_i is always 2'b11 in sim and assumed in formal", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupts ignored", + "Feature Description": "Interrupts ignored when \nnew privilege mode (nP) = current privilege mode(P) and new interrupt level (nL) != 0 and nL < current interrupt level (L)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode\nInside interrupt handler (Nested)\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_irq_lvl > 0 and < current level\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interupts disabled", + "Feature Description": "Interrupts disabled when\nmtatus.mie and clicintie[i] = 0", + "Verification Goal": "mstatus.mie = 0 should disallow any pending and enabled interrupts from being taken as we only have one level where interrupts can be taken (M-mode), so no other higher modes exist\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "No interrupt", + "Feature Description": "No interrupt when \nnew privilege mode (nP) = current privilege mode (P) \nclic.level = 0\n\nP, nP in M, U", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode (Cannot signal U-mode)\nTest in both nested and non-nested cases\n\nclic_irq_i = 1 \nclic_irq_id_i = random 0 .. max index\nclic_irq_lvl = 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "No interrupt", + "Feature Description": "No interrupt when \nnew privilege mode (nP) > current privilege mode (P)\nclic.level = 0\n\nnP = M, P = U, clic.level = 0\n(CV32E40S)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: U-mode\nTest for both nested and non-nested cases\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_irq_lvl = 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Horizontal interrupt taken\n(Nested)", + "Feature Description": "Horizontal interrupt taken when\nmtatus.mie and clicintie[i] = 1\nnew privilege mode (nP) = current privilege mode (P)\nnew privilege level (nL) > current privilege level (L)\n\nOnly applicable for M-mode (P, nP = M) as horizontal user mode traps are not supported (N-extension) in neither CV32E40X nor S", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode (Cannot signal U-mode)\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_lvl > current_lvl\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that an interrupt that should be taken under the given circumstances always get taken\nCheck that system behaves correctly when a pending and enabled interrupt gets taken", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Vertical interrupt taken", + "Feature Description": "Vertical interrupt taken when\nnew privilege mode (nP) > current privilege mode (P)\nnew privilege level (nL) > 0\n\nnP = M, P = U\n\n(CV32E40S)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: U-mode\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_lvl > 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that an interrupt that should be taken under the given circumstances always gets taken\nCheck that the system behaves correctly when a pending and enabled interrupt gets taken", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupt taken", + "Feature Description": "mstatus.mie = 1\nnP = P = M\nnL > L\n\nor\n\nnP > P (i.e. nP = M, P = U)\nnL > 0", + "Verification Goal": "Assert that an interrupt is taken if and only if any of the two conditions are true", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt preemption", + "Sub Feature": "mintthresh", + "Feature Description": "Higher level interrupts than mintthresh.th can preempt execution", + "Verification Goal": "Assert that interrupts with the same privilege mode and higher privilege level than the running ISR can interrupt the currently running ISR", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt preemption", + "Sub Feature": "mintthresh", + "Feature Description": "Lower level interrupts than mintthresh.th cannot preempt execution", + "Verification Goal": "Assert that interrupts with the same privilege mode and lower privilege level than the running ISR cannot interrupt the currently running ISR", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "when \nnP > P\ninterrupt is highest among pending-and-enabled interrupts\ni.level != 0\n\nnP = M, P = U\n\n(CV32E40S)", + "Verification Goal": "clic_irq_i = 1\nclic_irq_lvl > 0\nP = U\nnP = M", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "when\nnP = P\ninterrupt is highest among pending-and-enabled interrupts\ni.level > max(xintstatus.xil, xintthresh.th)\n\n(xintthresh only applies to current privilege mode)\nnP, P = M", + "Verification Goal": "clic_irq_i = 1\nclic_irq_lvl > max(mintstatus.mil, mintthresh.th)\nP, nP = M\n\nTest that only interrupts with a sufficiently high interrupt level are able to preempt execution with both true or temporarily risen interrupt level", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "nP < P\ninterrupt is highest among pending-and-enabled interrupts\ni.level != 0\n\nCan not occur 40S/40X as new privilege mode signalled on the CLIC interface can never be less than current privilege mode", + "Verification Goal": "nP < P cannot occur as we assume clic_irq_lvl = 2'b11\n\nNo test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Ignores", + "Feature Description": "Everything not covered above", + "Verification Goal": "Core does not resume operation unless any of the above resume conditions are true", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt instruction", + "Sub Feature": "Killed instructions have no side-effects", + "Feature Description": "When an instruction is interrupted, it is killed, meaning that it has no side-effects: 1) load/store instructions don't reach the bus, 2) control transfer instructions don't jump, 3) CSRs don't get updated, 4) GPRs don't get updated", + "Verification Goal": "Check that bus, jumps, and registers are unaffected by killed instructions", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "Execution continues at \nPrivilege mode = mcause.mpp\npc = mepc\ninterrupt level = mcause.mpil\nglobal interrupt enable mie = mcause.mpie\n\nmcause.mpil unchanged\nmcause.mpp = least privileged mode\nmcause.mpie = 1", + "Verification Goal": "Correct update of CSR values when core returns from an ISR", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "Execution continues at \nP = mcause.mpp\npc = mepc\nL = mcause.mpil\nie = mcause.mpie\n\nmcause.mpil unchanged\nmcause.mpp = least privileged mode\nmcause.mpie = 1", + "Verification Goal": "Correct update of CSR values when core returns from an ISR\nAdded assertion for formal coverage", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 0.9-draft 4/11/2023", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "\"If the hart is currently running at some privilege mode x, an MRET or SRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.\"", + "Verification Goal": "Use \"mret\" to enter U-mode.\nCheck that \"mintthresh\" is written to zero upon executing the mret.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 0.9-draft 4/11/2023", + "Feature": "Return from debug mode", + "Sub Feature": "dret", + "Feature Description": "\"Likewise, if the RISC-V debug specification is implemented and the hart is currently running at some privilege mode x, a DRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.\"", + "Verification Goal": "Use \"dret\" to enter U-mode.\nCheck that \"mintthresh\" is written to zero upon executing the dret.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i\n\u2022 has a higher privilege mode than the current privilege mode and\n\u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled\ninterrupts and\n\u2022 the interrupt i level is not equal to 0.", + "Verification Goal": "Test that interrupts of higher privilege modes than the current privilege mode can wakeup the core from wfi", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i\n \u2022 has the same privilege mode as the current privilege mode and\n \u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and\n \u2022 the interrupt i level is greater than max(xintstatus.xil, xintthresh.th )", + "Verification Goal": "Test that interrupts of higher privilege level than the current privilege level can wake the core from WFI", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i \n\u2022 has a lower privilege mode than the current privilege mode and \n\u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and \n\u2022 the interrupt i level is not equal to 0.", + "Verification Goal": "nP < P cannot occur as we assume clic_irq_lvl = 2'b11\n\nNo test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "Core only wakes up if any of the conditions mentioned above is true", + "Verification Goal": "Assert that core remains in WFI mode unless correct wakeup conditions occur", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Entry", + "Feature Description": "Execution of WFI causes the core to stop", + "Verification Goal": "In normal execution the core stop within a certain time period after execution.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Clock gating", + "Feature Description": "WFI entry causes the clock to be gated", + "Verification Goal": "The core is not clocked during WFI", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Output signal", + "Feature Description": "core_sleep_o output signal is only asserted during active WFI", + "Verification Goal": "Assert the proper operation of core_sleep_o", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Synchronous exception handling", + "Sub Feature": "Horizontal synchronous exception traps", + "Feature Description": "Serviced at same privilege mode with same interrupt level as instruction that raised exception ", + "Verification Goal": "Assert that interrupt level is not changed when entering the exception handler\n(Can only occur in machine mode)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Synchronous exception handling", + "Sub Feature": "Vertical synchronous exception traps", + "Feature Description": "Serviced at higher privilege mode at interrupt level 0 in the higher privilege mode\n\n(CV32E40S)", + "Verification Goal": "Assert that user mode traps are taken in machine mode with interrupt level 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + WFI", + "Feature Description": "Proper interactions between interrupts and WFI", + "Verification Goal": "Corner case\n\nTest random combinations of streams containing WFI-instructions with random interrupt requests", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Back to back WFI", + "Feature Description": "Correct interactions between interrupts and back-to-back WFI instructions", + "Verification Goal": "Corner case\n\nIn embedded context WFI is used often, ensure that WFI can be re-entered ASAP after servicing a ISR for a previous WFI", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug", + "Feature Description": "Correct interaction between interrupts and debug", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by debug and random interrupt requests.\nGoal is to verify that interrupts are never taken in debug mode, and that interrupt- and debug transitions are handled correctly\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Exceptions", + "Feature Description": "Correct interaction between interrupts and exceptions", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by exceptions and random interrupt requests.\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Bus Error", + "Feature Description": "Correct interaction between interrupts and bus errors", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by random interrupt requests and random bus errors. Aims to verify that interrupts and bus errors are correctly prioritized by the system.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + Bus Error", + "Feature Description": "Correct interaction between interrupts, debug and bus errors\n", + "Verification Goal": "Corner case\nTest random streams of instructions, \n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI", + "Feature Description": "Correct interaction between interrupts, debug and WFI\n", + "Verification Goal": "Test random instruction streams containing WFI, where control flow changes occur due to random debug requests and random interrupts\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI + Bus Error", + "Feature Description": "Correct interaction between interrupts, debug, wfi and bus errors", + "Verification Goal": "Test random instruction streams containing WFI instructions, where control flow changes occur due to random debug requests, random bus errors, random interrupts\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI + Bus Error + Exceptions", + "Feature Description": "Correct interaction between all trap sources", + "Verification Goal": "Trap priority stress test\nTest random streams containing all trap sources to verify correct behavior\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts", + "Feature Description": "Correct interactions between nested interrupts", + "Verification Goal": "Verify potential corner case\n\nImplement nested ISR. Randomly modify mintthresh.th to mask out certain interrupts and randomly trigger new interrupts with higher or lower priority to verify that interrupts with a higher privilege level are allowed to preempt\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts + exceptions", + "Feature Description": "Correct interactions between nested interrupts and exceptions", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts, but random streams include randomly inserted exception-causing instructions\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug", + "Feature Description": "Correct interactions between nested interrupts and debug", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts, but random streams also gets control flow modified by random debug requests.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts + Debug + Bus Error", + "Feature Description": "\nCorrect interactions between nested inteerrupts, debug and bus-errors", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts with debug, but also includes random bus errors\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug + WFI", + "Feature Description": "Correct interactions between nested interrupts, debug and WFI", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts with debug, but the instruction stream should also include WFI instructions.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug + WFI + Bus Error + Exceptions", + "Feature Description": "Correct interactions between nested interrupts and all other trap types", + "Verification Goal": "Verify potential corner case\nTest nested interrupts with randomly traps (all types)\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Load instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Store instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Shift instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit logical instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit compare instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit jump instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit FENCE instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit system instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BEQ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BEQ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BNE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BNE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BLT instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BLT instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BGE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BGE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BLTU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BLTU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BGEU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BGEU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit load instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit store instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit arithmetic instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit shift instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit jump instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit system instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken C.BEQZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken C.BEQZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken C.BNEZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken C.BNEZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 M instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zba instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbb instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbc instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbs instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zicsr instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zifencei instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zc instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zca instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcb instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmb instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmt instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmp instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Illegal instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 A instructions interrupted\n(CV32E40X)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All X interface instructions interrupted\n(CV32E40X)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32F instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 P instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32V instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": " ---- END ----", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx new file mode 100755 index 0000000000..46b4f09d99 Binary files /dev/null and b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.csv b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.csv new file mode 100644 index 0000000000..8e80af5236 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.csv @@ -0,0 +1,58 @@ +Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,Comment +Riscv spec,StoresVisible,StoresVisible,"After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.","Do a fencei, but right before the fencei do a store to the instruction following the fencei, then see that the newly stored value is executed instead of the old instruction (e.g. change addi to use a different immediate)",Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/ + +COV: ???",TODO must be added to regression lists +,,,,"Do a fencei followed by any instruction, but let the environment detect when the fencei is being executed and change the memory holding the next instruction, then see that the old instruction is not executed",Check against RM,Directed Non-Self-Checking,Functional Coverage,"DTC: cv32e40s/tests/programs/custom/fencei/ + +COV: ???",TODO missing cover +,,,,"Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference)",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/fencei/, +,,,,"Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal)",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: ???,TODO missing assert. (Note was ignored because of the difficulty of writing this as an assert for fv.) +User manual,ExternalHandshake,ReqHigh,"When executing a fence.i instruction, fencei_flush_req_o shall rise sometime before executing the next instruction",Check that when executing a fence.i instruction there will be a rising req before has retired,Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_rise_before_retire, +,,ReqWaitLsu,"When executing a fence.i instruction, if there is an ongoing store instruction (not limited to rv32i) that has not completed (data_rvalid_i clocked in as 1), then fencei_flush_req_o shall be low","Make sure a store instruction is run right before a fence.i, and (possibly using obi stalls) ensure that the fence.i is pending retirement but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o was low until this point where it now goes high",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_bus + +COV: ???",TODO missing cover +,,ReqWaitWritebuffer,"When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1",Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied,Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_buffer + +COV: ???",TODO missing cover +,,ReqWaitXinterface,"When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done",Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high,Assertion Check,Constrained-Random,Functional Coverage,(Not relevant for the 40s), +,,ReqWaitObi,fencei_flush_req_o shall not go high while there are outstanding stores on the obi bus,Check vs the OBI monitors that there are no outstanding stores at the time fencei_flush_req_o goes high,Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_outstanding + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_c_req_wait_outstanding_1.cov_req_wait_outstanding_1", +,,ReqLow,"When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o and fencei_flush_ack_i has been sampled high simultaneously, and then then it shall go low","Check that when fencei_flush_req_o is high, then it behaves correctly with regards to fencei_flush_ack_i",Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_stay_high + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_drop_lo", +,,AckChange,"fencei_flush_ack_i is allowed to change freely on any clock cycle: It can be permanently high, go high without fence.i and retract, go high at the same cycle as the req, it can delay arbitrarily after req and then go high, etc","Drive ack to test all permutations of rising/falling before/after/on req, acking without req, retracting an early ack, delaying ack after req, etc.",Any/All,"ENV capability, not specific test",Functional Coverage,COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reqack_cg, +,,AckWithold,"If req is high, but ack never comes, then the core keeps on stalling and the fence.i is blocked from completing","Upon a req, try witholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]})",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_stall_until_ack + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_ack_delayed[*].cov_ack_delayed", +,,BranchInitiated,"After req and ack has been sampled simultaneously high and when req is low again, then the core takes a branch to the instruction after the fence.i instruction",Check that the branch is taken at the point after req and ack has been simultaneously high,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_branch_after_retire + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_branch_after_retire", +,,ShadowingBranch,"If the fence.i ends up not retiring because it was preceeded by a taken branch or a jump, then the fencei_flush_req_o shall not go high","Take a branch or do a jump to skip a fence.i, and ensure that fencei_flush_req_o doesn't go high",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_must_retire + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_retire_without_req + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_no_retire", +User manual,Fetching,Fetching,Instruction data for the next PC must be fetched after the fence.i instruction has executed (because only then can data-side stores have completed and caches have been updated),Check that after a fence.i instruction retires then instr-side obi fetches the next instruction to be executed,Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_fetch_after_retire, +User manual,MultiCycle,MultiCycle,"Given zero stalls on neither instr-side and data-side obi nor on fencei_flush_ack_i, then the execution of fence.i takes a fixed number of cycles.","Check that, given ideal conditions, the cycle count of fence.i is as expected",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_cycle_count_minimum, +User manual,StoresComplete,StoresComplete,"Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted)","Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/fencei/, +,,,,,Check against RM,Constrained-Random,Testcase,RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/, +User manual,Flush,Flush,"When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed","Check that a fence.i will cause flushing of the pipeline, prefetcher, write buffer, and data_req_o",Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_supress_datareq + +A: ???",TODO missing assert. (Have not checked/covered that the pipeline/writebuffer content is actually purged. Or that any memory change WILL be the next instr word.) +Riscv spec,UnusedFields,UnusedFields,"imm[11:0], rs1, rd are reserved for future extensions, and implementations shall ignore them",Try giving random values in those fields and see that all else works as expected,Check against RM,Constrained-Random,Functional Coverage,COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reserved_cg, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json new file mode 100644 index 0000000000..b9a5f7953c --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json @@ -0,0 +1,422 @@ +[ + { + "Requirement Location": "Riscv spec", + "Feature": "StoresVisible", + "Sub Feature": "StoresVisible", + "Feature Description": "After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.", + "Verification Goal": "Do a fencei, but right before the fencei do a store to the instruction following the fencei, then see that the newly stored value is executed instead of the old instruction (e.g. change addi to use a different immediate)", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/\n\nCOV: ???", + "Comment": "TODO must be added to regression lists" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Do a fencei followed by any instruction, but let the environment detect when the fencei is being executed and change the memory holding the next instruction, then see that the old instruction is not executed", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert. (Note was ignored because of the difficulty of writing this as an assert for fv.)" + }, + { + "Requirement Location": "User manual", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqHigh", + "Feature Description": "When executing a fence.i instruction, fencei_flush_req_o shall rise sometime before executing the next instruction", + "Verification Goal": "Check that when executing a fence.i instruction there will be a rising req before has retired", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_rise_before_retire", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitLsu", + "Feature Description": "When executing a fence.i instruction, if there is an ongoing store instruction (not limited to rv32i) that has not completed (data_rvalid_i clocked in as 1), then fencei_flush_req_o shall be low", + "Verification Goal": "Make sure a store instruction is run right before a fence.i, and (possibly using obi stalls) ensure that the fence.i is pending retirement but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o was low until this point where it now goes high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_bus\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitWritebuffer", + "Feature Description": "When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1", + "Verification Goal": "Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_buffer\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitXinterface", + "Feature Description": "When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done", + "Verification Goal": "Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "(Not relevant for the 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitObi", + "Feature Description": "fencei_flush_req_o shall not go high while there are outstanding stores on the obi bus", + "Verification Goal": "Check vs the OBI monitors that there are no outstanding stores at the time fencei_flush_req_o goes high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_outstanding\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_c_req_wait_outstanding_1.cov_req_wait_outstanding_1", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqLow", + "Feature Description": "When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o and fencei_flush_ack_i has been sampled high simultaneously, and then then it shall go low", + "Verification Goal": "Check that when fencei_flush_req_o is high, then it behaves correctly with regards to fencei_flush_ack_i", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_stay_high\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_drop_lo", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "AckChange", + "Feature Description": "fencei_flush_ack_i is allowed to change freely on any clock cycle: It can be permanently high, go high without fence.i and retract, go high at the same cycle as the req, it can delay arbitrarily after req and then go high, etc", + "Verification Goal": "Drive ack to test all permutations of rising/falling before/after/on req, acking without req, retracting an early ack, delaying ack after req, etc.", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reqack_cg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "AckWithold", + "Feature Description": "If req is high, but ack never comes, then the core keeps on stalling and the fence.i is blocked from completing", + "Verification Goal": "Upon a req, try witholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]})", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_stall_until_ack\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_ack_delayed[*].cov_ack_delayed", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "BranchInitiated", + "Feature Description": "After req and ack has been sampled simultaneously high and when req is low again, then the core takes a branch to the instruction after the fence.i instruction", + "Verification Goal": "Check that the branch is taken at the point after req and ack has been simultaneously high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_branch_after_retire\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_branch_after_retire", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ShadowingBranch", + "Feature Description": "If the fence.i ends up not retiring because it was preceeded by a taken branch or a jump, then the fencei_flush_req_o shall not go high", + "Verification Goal": "Take a branch or do a jump to skip a fence.i, and ensure that fencei_flush_req_o doesn't go high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_must_retire\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_retire_without_req\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_no_retire", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "Fetching", + "Sub Feature": "Fetching", + "Feature Description": "Instruction data for the next PC must be fetched after the fence.i instruction has executed (because only then can data-side stores have completed and caches have been updated)", + "Verification Goal": "Check that after a fence.i instruction retires then instr-side obi fetches the next instruction to be executed", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_fetch_after_retire", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "MultiCycle", + "Sub Feature": "MultiCycle", + "Feature Description": "Given zero stalls on neither instr-side and data-side obi nor on fencei_flush_ack_i, then the execution of fence.i takes a fixed number of cycles.", + "Verification Goal": "Check that, given ideal conditions, the cycle count of fence.i is as expected", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_cycle_count_minimum", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "StoresComplete", + "Sub Feature": "StoresComplete", + "Feature Description": "Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted)", + "Verification Goal": "Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "StoresComplete", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "Flush", + "Sub Feature": "Flush", + "Feature Description": "When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed", + "Verification Goal": "Check that a fence.i will cause flushing of the pipeline, prefetcher, write buffer, and data_req_o", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_supress_datareq\n\nA: ???", + "Comment": "TODO missing assert. (Have not checked/covered that the pipeline/writebuffer content is actually purged. Or that any memory change WILL be the next instr word.)" + }, + { + "Requirement Location": "Riscv spec", + "Feature": "UnusedFields", + "Sub Feature": "UnusedFields", + "Feature Description": "imm[11:0], rs1, rd are reserved for future extensions, and implementations shall ignore them", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reserved_cg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.xlsx b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.xlsx new file mode 100755 index 0000000000..f232835cea Binary files /dev/null and b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv new file mode 100644 index 0000000000..b4fae49113 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv @@ -0,0 +1,350 @@ +Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,Comment +UM 0e447ac,Regions,Valid number of regions,There shall be between 0 and 16 PMA regions configured.,"Assert that highest numbered PMA region < 16 (assuming 0-indexed) + +Cover: Having 0 regions, having maximum num regions, and having something in between.",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_valid_num_regions + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_valid_num_regions + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_index + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_index + +COV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_cov_instr_i.cg_inst.cp_numregions","TODO tests must be added to regression lists. + +TODO directed tests has parts to uncomment if RTL is ready. + +TODO everything ""atomics"" must be changed to ""integrity"" for 40s." +,,Configuration to be tested,0 Regions - Deconfigured,"Test configuration 1, aims to verify the following: +1. Default parameters for entire memory range",Any/All,"ENV capability, not specific test",N/A,N/A,"No cover, but fascilitates other covers below. + +TODO these regions are out of date vs testbench. + +TODO must be used in formal regressions too." +,,,"1 Region: +R[0]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111) + +MBCA = M(ain memory) + B(ufferable) + C(acheable) + A(tomic operations allowed) + +","Test configuration 2, aims to verify the following: +1. System configured with 1 PMA region only +2. Full address range of maximum size +3. Upper/Lower bounds for first region set to min/max values",Any/All,"ENV capability, not specific test",N/A,N/A, +,,,"1 Region: +R[0]: 0x0000_0000-0x7FFF_FFFF (MBCA = 1111)","Test configuration 3, aims to verify the following: +1. Correct functionality for 1 defined region +2. Correct behavior for undefined regions when a region is defined",Any/All,"ENV capability, not specific test",N/A,N/A, +,,,"7 Regions: +R[0]: 0x0000_0000-0x1FFF_FFFF (MBCA = 1111) +R[1]: 0x2000_0000-0x3FFF_FFFF (MBCA = 1101) +R[2]: 0x4000_0000-0x5FFF_FFFF (MBCA = 0101) +R[3]: 0x6000_0000-0x9FFF_FFFF (MBCA = 1001) +R[4]: 0xA000_0000-0xDFFF_FFFF (MBCA = 0101) +R[5]: 0xE000_0000-0xE00F_FFFF (MBCA = 0000) +R[6]: 0xE010_0000-0xFFFF_FFFF (MBCA = 0101)","Test configuration 4, aims to verify the following: +1. A standard memory map (Based on ARM Cortex) +2. A fully defined, contiguous memory map with no undefined regions +3. Multiple, non-overlapping regions",Any/All,"ENV capability, not specific test",N/A,N/A, +,,,"16 Regions: +R[0]: 0x4800_0000-0x49FF_FFFF (MBCA = 1011) +R[1]: 0x4400_0000-0x4BFF_FFFF (MBCA = 0001) +R[2]: 0x3ACE_0000-0x4ABC_FFFF (MBCA = 0100) +R[3]: 0x3600_A000-0x4F99_FFFF (MBCA = 1111) +R[4]: 0x3420_C854-0x5000_ABFF (MBCA = 1101) +R[5]: 0x3100_FCAB-0x5000_BCCA (MBCA = 1001) +R[6]: 0x3000_1353-0x5140_FFFF (MBCA = 0000) +R[7]: 0x2C5A_3200-0x52FF_FFFF (MBCA = 0101) +R[8]: 0x2A00_0000-0x56FF_FFFF (MBCA = 1111) +R[9]: 0x2340_000A-0x600F_FFFF (MBCA = 0001) +R[10]: 0x2000_0000-0x63FF_FFFF (MBCA = 0101) +R[11]: 0x13AC_AA55-0x7FFF_FFFF (MBCA = 1011) +R[12]: 0x1000_000F1-0x82FF_FFFF (MBCA = 1101) +R[13]: 0x0500_0000-0x8459_FFFF (MBCA = 0100) +R[14]: 0x0200_0000-0xEFFF_FFFF (MBCA = 0000) +R[15]: 0x0000_A000-0xFFFE_FFFF (MBCA = 1111)","Test configuration 5, aims to verify the following: +1. Region match priority +2. Maximum number of separate areas in memory (33) + +Address may be modified to better suit implementation and verification enviornment, but the following criteria must be met: +1. Each defined region must be enclosed by the adjacent region of lower priority +2. No region boundaries must overlap +3. There shall be undefined space prior to and aft of largest, highest numbered region +",Any/All,"ENV capability, not specific test",N/A,N/A, +,,,"16 Regions: +R[0]: 0x0001_0000-0x001F_FFFF (MBCA = 1001) +R[1]: 0x0030_0000-0x04FF_FFFF (MBCA = 1111) +R[2]: 0x1000_0000-0x1001_0000 (MBCA = 0100) +R[3]: 0x1800_1234-0x18FF_AB21 (MBCA = 0000) +R[4]: 0x2020_0010-0x2FFF_0000 (MBCA = 0001) +R[5]: 0x3100_A000-0x32FF_FFFF (MBCA = 1111) +R[6]: 0x3440_0000-0x3800_FFFF (MBCA = 0100) +R[7]: 0x4AAA_F000-0x4C00_FFFF (MBCA = 1101) +R[8]: 0x4D00_5555-0x4FFF_ABCD (MBCA = 1011) +R[9]: 0x5100_0000-0x52FF_FFFF (MBCA = 0000) +R[10]: 0x5400_0000-0x5FFF_FFFF (MBCA = 1111) +R[11]: 0x6300_0000-0x6700_FFFF (MBCA = 0101) +R[12]: 0xA000_0000-0xAFFF_FFFF (MBCA = 1001) +R[13]: 0xBC00_0000-0xBCFF_FFFF (MBCA = 1101) +R[14]: 0xC000_0000-0xDFFF_FFFF (MBCA = 0001) +R[15]: 0xE700_EF00-0xE9FF_FFFF (MBCA = 0101)","Test configuration 6, aims to verify designs with the following characteristic: +1. Non-contiguously defined maximum number of memory regions +2. Maximum number of separate areas In memory (33) +3. No overlap, single matching regions +4. Non-defined areas prior and aft of each defined region + +Address map may be modified to better suit actual implemetations, but the above criteria must be adhered to.",Any/All,"ENV capability, not specific test",N/A,N/A, +,,,"16 Regions: +Note: Zero length regions are intentional +R[0]: 0x0000_0000-0x0000_0000 (MBCA = 0000) +R[1]: 0x5555_5555-0x5555_5555 (MBCA = 0000) +R[2]: 0x0000_0000-0x0000_0000 (MBCA = 0000) +R[3]: 0xAAAA_AAAA-0xAAAA_AAAA (MBCA = 0000) +R[4]: 0xCCCC_CCCC-0xCCCC_CCCC (MBCA = 0000) +R[5]: 0x0000_0000-0x0000_0000 (MBCA = 0000) +R[6]: 0xE38E_E38E-0xE38E_E38E (MBCA = 0000) +R[7]: 0x0000_0000-0x0000_0000 (MBCA = 0000) +R[8]: 0xFFFF_FFFF-0xFFFF_FFFF (MBCA = 0000) +R[9]: 0x0000_0000-0x0000_0000 (MBCA = 0000) +R[10]: 0x9249_2492-0x9249_2492 (MBCA = 0000) +R[11]: 0x0000_0000-0x0000_0000 (MBCA = 0000) +R[12]: 0xDB6D_B6DB-0xDB6D_B6DB (MBCA = 0000) +R[13]: 0x0000_0000-0x0000_0000 (MBCA = 0000) +R[14]: 0x1249_2492-0x1249_2492 (MBCA = 0000) +Only one non-zero region: +R[15]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111)","Test configuration 7, aims to verify the following: +1. Zero length regions does not match any accesses +2. Upper/Lower bound of outlier (last) region set to min/max of address range + +Address map may be modified to better suit actual implementations, but R[15] must be defined to min/max possible address range. Remaining regions shall have 0 length. +",Any/All,"ENV capability, not specific test",N/A,N/A, +,,Coverpoints,Instruction fetch coverpoint,Region index or default IO unmapped region crossed with passing instruction fetch,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*,"Note: These could also have used RVFI instead. + +Note: Not very feasible to match on every single cfg index, because some are overshadowed by overlapping regions and to model this is expensive." +,,,Load instruction coverpoint,Region index or default IO unmapped region crossed with passing load instruction,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, +,,,Store instruction coverpoint,Region index or default IO unmapped region crossed with passing store instruction,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, +,,,Atomic instruction coverpoint,Region index or default IO unmapped region crossed with atomic operation,N/A,N/A,N/A,, +,,,Load alignment error coverpoint,Region index or default IO unmapped region crossed with load alignment error,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, +,,,Store alignment error coverpoint,Region index or default IO unmapped region crossed with store alignment error,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, +,,,Atomic load-reserved unallowed error coverpoint,Region index or default IO unmapped region crossed with atomic load-reserved unallowed error,N/A,N/A,N/A,, +,,,Atomic store-conditional unallowed error coverpoint,Region index or default IO unmapped region crossed with atomic store-conditional unallowed error,N/A,N/A,N/A,, +Risc-V Priv. spec,PMA Readability,PMA readable by SW,Design must support SW readback of attributes,"N/A. Can be SW-readable via a C-header, or is otherwise the responsibility of integration- or system-level testing.",N/A,N/A,N/A,, +UM 0e447ac,Code Execution,Code Execution only from main memory,"Code execution is not allowed from IO region, any attempts to do so should result in an instruction access fault (exception code 1)","Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification + +The following CSRs must be verified: Verify mcause, mepc, mtval + +E.g. execute a JMP instruction to an area defined as IO (and/or unconfigured PMA region) and verify that an instruction access fault is triggered",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/, +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg.cross_pma", +,,Instruction fetch violation coverpoints,Instruction group type for failing instruction fetch violations,Instruction group type cover from ISACOV for each violated PMA instruction fetch,Other,"ENV capability, not specific test",Functional Coverage,COV: TODO,TODO missing cover. (Problem: Depends on ISACOV updates.) +UM 0e447ac,Access match,Non-Overlapping PMA Regions,"A match should always be inside its matching region, +Lower_bound[region] <= addr[addr_max:2] < Upper_bound[region]","Assert that match[region] always implies that the following holds: +lower[region] & 2'b00 <= addr[31:0] < upper[region] 2'b00",Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_bounds + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_bounds", +,,,,Perform arbitrary accesses: Verify that accesses are matched to their respective memory regions,Assertion Check,"ENV capability, not specific test","ENV capability, not specific test","A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch* + +COV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_matchregion*", +,,Overlapping PMA Regions,Any access matching multiple regions should attain the attributes of the lowest numbered matching region,"Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region. + +Coverage: Multiple regions matching at once.",Check against RM,Directed Non-Self-Checking,Testcase,DTC: TODO,TODO missing directed test? +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch*", +,,,,,Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", +,,Non-Matching Accesses,"PMA_NUM_REGIONS==0: +Accesses not matching attribute regions should be treated as: +Memory +Non-Bufferable +Non-Cacheable +Atomic operations not allowed","Arbitrary accesses to non-configured PMA-areas. +Self checking test should attempt the following: +- Non-aligned load/store accesses: should pass +- Atomic lr/sc operations (if supported by core): should fail +- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply) +- Instruction fetch and execute: should pass",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma_0reg/, +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: TODO + +COV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*",TODO is the random stream run without pma regions? +,,,"PMA_NUM_REGIONS>0 +Accesses not matching attribute regions should be treated as: +IO +Non-Bufferable +Non-Cacheable +Atomic operations not allowed","Arbitrary accesses to non-configured PMA-areas. +Self checking test should attempt the following: +- Non-aligned load/store accesses: should fail +- Atomic lr/sc operations (if supported by core): should fail +- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply) +- Instruction fetch and execute: should fail",Self Checking Test,Directed Self-Checking,Testcase,DTC: TODO,TODO missing directed test? +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", +UM 0e447ac,OBI transfer flags,InstructionFetches,"Bufferable flag effects - For any instruction fetch marked bufferable, the corresponding OBI transfer instr_memtype[0] signal should be set to match the bufferable flag.","Ensure that instr_memtype[0] is set to 1 when an instruction fetch attempt is performed with the bufferable flag set to 1. (Which is never, because ""Accesses to regions marked as bufferable (bufferable=1) will result in the OBI mem_type[0] bit being set, except if the access was an instruction fetch [...]"".)",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,,Ensure that instr_memtype[0] is set to 0 when an instruction fetch attempt is performed with the bufferable flag set to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,"Cacheable flag effects - For any instruction fetch marked cacheable, the corresponding OBI transfer instr_memtype[1] signal should be set to match the cacheable flag.",Ensure that instr_memtype[1] is set to 1 when an instruction fetch attempt is performed with the cacheable flag set to 1,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk5.a_pma_obi_cacheon + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,,Ensure that instr_memtype[1] is set to 0 when an instruction fetch attempt is performed with the cacheable flag set to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_cacheoff + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,Instruction fetch attempts to PMA restricted regions should cause instr_req_o to be deasserted.,"Ensure that PMA-violating instruction fetch attempts does not assert the instr_req_o signal by attempting execution of instructions from allowed and restricted areas of memory, checking that instr_req_o remains deasserted when restricted areas are accessed",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_req_prohibited + +COV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", +,,DataFetches,Bufferable flag effects - data_memtype[0] should match the bufferable flag.,Ensure that data_memtype[0] is set to 1 when a data fetch attempt is performed with the bufferable flag set to 1,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk4.a_pma_obi_bufon + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,,Ensure that data_memtype[0] is set to 0 when a data fetch attempt is performed with the bufferable flag set to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_bufoff + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,Cacheable flag effects - data_memtype[1] should match the cacheable flag,Ensure that data_memtype[1] is set to 1 when an data fetch attempt is performed with the cacheable flag set to 1,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk5.a_pma_obi_cacheon + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,,Ensure that data_memtype[1] is set to 0 when an data fetch attempt is performed with the cacheable flag set to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_cacheoff + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,Data fetch attempts to PMA restricted regions should cause data_req_o to be deasserted.,Ensure that PMA violating data fetch attempts does not assert the data_req_o signal,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_req_prohibited + +COV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", +UM 0e447ac,Non-Naturally Aligned Accesses,Non-naturally aligned data accesses shall only occur for Main memory accesses.,"Non-naturally aligned load access attempts to I/O shall + cause a precise load access fault (exception code 5).","Attempt arbitrary non-naturally aligned load accesses to I/O regions specified by PMA and ensure that these accesses triggers precise load access fault exceptions (code 5). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions. + +The following CSRs must be verified: Verify mcause, mepc, mtval + +Test possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: +ld from addresses in IO space with or_reduce(addr_lsb[2:0]) = 1 +lw from addresses in IO space with or_reduce(addr_lsb[1:0]) = 1 +lh from addresses in IO space with and_reduce(addr_lsb[1:0]) = 1 +",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/,TODO test is commented out +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*","TODO missing ""ld/lw/lh"" specific covers." +,,,"Non-naturally aligned store access attempts to I/O shall + cause a precise store access fault (exception code 7).","Attempt arbitrary non-naturally aligned store accesses to I/O regions specified by PMA and ensure that these accesses triggers precise store access fault exceptions (code 7). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions + +The following CSRs must be verified: Verify mcause, mepc, mtval + +Test possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: +sd to addresses in IO space with or_reduce(addr_lsb[2:0]) = 1 +sw to addresses in IO space with or_reduce(addr_lsb[1:0]) = 1 +sh to addresses in IO space with and_reduce(addr_lsb[1:0]) = 1",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/, +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*","TODO missing ""sd/sw/sh"" specific covers." +,,Multi-memory operation instructions,"When the first memory access of a non-naturally aligned load operation fails due to PMA checks, the second memory access shall also be supressed. ","Attempt non-naturally aligned load instructions to: +- IO +- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. + +In both cases, data_req_o should remain low for both operations.",Self Checking Test,Directed Self-Checking,Testcase,DTC: TODO,TODO missing directed test? +,,,,,Assertion Check,Constrained-Random,Functional Coverage,"A :uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_failure_denies_subsequents + +RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_* + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", +,,,"If a PMA access fault occurs for any of the memory accesses in a non-naturally aligned load, the register file shall not be updated","Attempt non-naturally aligned load instructions to: +- IO +- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. +- Boundary between IO region and memory region s.t. first access will be in memory and second access will be in IO. + +In both cases, the register file should remain unchanged.",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/, +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_* + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", +,,,"When the first memory access of a non-naturally aligned store operation fails due to PMA checks, the second memory access shall also be supressed. ","Attempt non-naturally aligned load instructions to: +- IO +- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. + + +In both cases, data_req_o should remain low for both operations.",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/,TODO test is commented out +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_* + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", +UM 0e447ac,Zce Extension,Push instructions,"push, push.e, c.push, c.push.e instructions shall only occur for main memory regions, any such *push* attempts to I/O shall cause a precise load access fault (exception code 5)","Attempt *push* operations to main memory and IO, verify that all *push* attempts to IO causes a precise store access fault (code 5) and that this does not occur for main memory.",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/,TODO test is commented out +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: TODO + +COV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*","TODO missing random test? + +Note: Cover doesn't check that it goes through WB." +,,Pop instructions,"pop, popret, pop.e, popret.e, c.pop, c.popret, c.pop.e, c.popret.e shall only occur for main memory regions, any such *pop* attempts from I/O shall cause a precise load access fault (exception code 7)","Attempt *pop* operations to main memory and IO, verify that all *pop* attempts to IO causes a precise loac access fault (code 7) and that this does not occur for main memory.",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/,TODO test is commented out. +,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: TODO + +COV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*","TODO missing random test? + +Note: Cover doesn't check that it goes through WB." +,,Table Jump,"Both jumps from a Zce table jump should be checked by PMA and handled as instruction fetches. + +PMA failure in the first table jump should suppress the second jump - instr_fetch_o should be suppressed and no jump to the restricted address shall be performed","First jump: Testing a violating first jump (jump to the jump table) requires a custom linker script that deliberatly places the jump table in a non-executable (IO) region. A test must verify that instructions attempting to jump to the jump table location causes an instruction access fault (exception code 1) and that instr_req_o is suppressed + +The second instruction fetch should be suppressed.",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/,TODO test is commented out +,,,,"Second jump: Test should verify that a PMA access fault on the second jump (jump to the actual instruction address in IO region) should cause an instruction access fault (exception code 1), suppressing instr_req_o. ",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma/,TODO test is commented out +,,,,Coverpoint - Table jumps passing PMA checks crossed with region index or default unmapped memory region,Check against RM,Constrained-Random,Functional Coverage,"RTC: TODO + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_pmafault_tablejump_* + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_firstfail_tablejump:_* + +COV: *.pma_cov_instr_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_allow_jvt_*","TODO missing random test? + +Note: This is not maximally comprehensive, but the modelling that would otherwise be required is disproportionately complex." +Zce spec. proposal,,,"Instruction fetch exceptions occurring when executing an address in the jump table should lead to mepc being set to the C.TBLJ* instruction, and mtval to the address in the jump table entry",Verify that an instruction fetch exception resulting from a jump table entry leads to mepc being set to the C.TBLJ* instruction and mtval to the address in the jump table entry.,Self Checking Test,Directed Self-Checking,Testcase,DTC: TODO,TODO missing directed test? +Risc-V Debug spec.,Debug mode,Single step PMA exceptions,"Any instruction fetch exception that occurs while single stepping, causes debug mode to be re-entered after PC is changed to the exception handler and the appropriate tval and cause registers are updated","Verify that instruction fetches to PMA IO regions fails, the appropriate CSRs and PC is updated to the appropriate values and debug mode is reentered. ",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma_debug/, +,,Program buffer PMA exceptions,Exceptions in the program buffer should cause the program buffer code to end and cmderr set to 3 (exception error),"Verify that program buffer code attempting to fetch instructions from PMA IO region fails, PC is set to dm_exception_addr_i and cmderr is set to 3 (exception error). No other registers should be changed due to this exception.",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma_debug/, +40s UM 0.8.0,DebugRange,DebugRange,"""CV32E40S overrules the PMA and PMP settings for the Debug Module region when it is in debug mode""","Attempt access within/outside the dm region, in both dmode/not, check that the combo within/dmode never gets blocked and that the other combos follow the ordinary rules.",Assertion Check,Constrained-Random,Code Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_dm_region + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_dm_region + +A: (The other cases are covered by all other testing.) + +COV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_dmregion_dmode_*", +UM 0e447ac,Atomic operations,Atomic operations shall only occur for regions in which Atomic operations are allowed. (Only applies for cores with A-extension),Load-Reserved attempts to a region where atomic operations are not permitted shall cause a precise load access fault (exception code 5),"Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions. + +The following CSRs must be verified: Verify mcause, mepc, mtval",Self Checking Test,Directed Self-Checking,Testcase,(N/A for 40s), +,,,,,Check against RM,Constrained-Random,Functional Coverage,(N/A for 40s), +,,,Store-Conditional or Atomic Memory Operation (AMO) attempts to a region where Atomic operations are not allowed shall cause a precise store/AMO access fault (exception code 7).,"Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions. + +The following CSRs must be verified: Verify mcause, mepc, mtval",Self Checking Test,Directed Self-Checking,Testcase,(N/A for 40s), +,,,,,Check against RM,Constrained-Random,Functional Coverage,(N/A for 40s), +UM 0e447ac,Fence* instructions,Fence instructions disregards distinction between memory and IO,Fence instruction shall not be impacted by PMA memory/IO attribute and execute as a conservative fence on all operations ,"Coverpoint - Fence instructions (Fence, fence.i) should not be impacted by PMA.",Check against RM,Constrained-Random,Functional Coverage,"RTC: TODO + +COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_waspmafault_wasmain_wasloadstore_fence_*",TODO missing random test? +UM 0e447ac,WriteBuffer,Bufferable operations,Only bufferable store accesses should use the internal write buffer,Assert that write buffer remains unchanged unless store accesses carry the bufferable flag,Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.a_writebuf_bufferable + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.gen_noregions_nobuf.a_writebuf_noregions + +COV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, +,,,,,,,,, + -------END---------,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json new file mode 100644 index 0000000000..9d66eba2aa --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json @@ -0,0 +1,866 @@ +[ + { + "Requirement Location": "UM 0e447ac", + "Feature": "Regions", + "Sub Feature": "Valid number of regions", + "Feature Description": "There shall be between 0 and 16 PMA regions configured.", + "Verification Goal": "Assert that highest numbered PMA region < 16 (assuming 0-indexed)\n\nCover: Having 0 regions, having maximum num regions, and having something in between.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_valid_num_regions\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_valid_num_regions\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_index\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_index\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_cov_instr_i.cg_inst.cp_numregions", + "Comment": "TODO tests must be added to regression lists.\n\nTODO directed tests has parts to uncomment if RTL is ready.\n\nTODO everything \"atomics\" must be changed to \"integrity\" for 40s." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "Configuration to be tested", + "Feature Description": "0 Regions - Deconfigured", + "Verification Goal": "Test configuration 1, aims to verify the following:\n1. Default parameters for entire memory range", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "No cover, but fascilitates other covers below.\n\nTODO these regions are out of date vs testbench.\n\nTODO must be used in formal regressions too." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "1 Region: \nR[0]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111)\n\nMBCA = M(ain memory)\n B(ufferable)\n C(acheable)\n A(tomic operations allowed)\n\n", + "Verification Goal": "Test configuration 2, aims to verify the following:\n1. System configured with 1 PMA region only\n2. Full address range of maximum size\n3. Upper/Lower bounds for first region set to min/max values", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "1 Region: \nR[0]: 0x0000_0000-0x7FFF_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 3, aims to verify the following:\n1. Correct functionality for 1 defined region\n2. Correct behavior for undefined regions when a region is defined", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "7 Regions:\nR[0]: 0x0000_0000-0x1FFF_FFFF (MBCA = 1111)\nR[1]: 0x2000_0000-0x3FFF_FFFF (MBCA = 1101)\nR[2]: 0x4000_0000-0x5FFF_FFFF (MBCA = 0101)\nR[3]: 0x6000_0000-0x9FFF_FFFF (MBCA = 1001)\nR[4]: 0xA000_0000-0xDFFF_FFFF (MBCA = 0101)\nR[5]: 0xE000_0000-0xE00F_FFFF (MBCA = 0000)\nR[6]: 0xE010_0000-0xFFFF_FFFF (MBCA = 0101)", + "Verification Goal": "Test configuration 4, aims to verify the following:\n1. A standard memory map (Based on ARM Cortex)\n2. A fully defined, contiguous memory map with no undefined regions\n3. Multiple, non-overlapping regions", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nR[0]: 0x4800_0000-0x49FF_FFFF (MBCA = 1011)\nR[1]: 0x4400_0000-0x4BFF_FFFF (MBCA = 0001)\nR[2]: 0x3ACE_0000-0x4ABC_FFFF (MBCA = 0100)\nR[3]: 0x3600_A000-0x4F99_FFFF (MBCA = 1111)\nR[4]: 0x3420_C854-0x5000_ABFF (MBCA = 1101)\nR[5]: 0x3100_FCAB-0x5000_BCCA (MBCA = 1001)\nR[6]: 0x3000_1353-0x5140_FFFF (MBCA = 0000)\nR[7]: 0x2C5A_3200-0x52FF_FFFF (MBCA = 0101)\nR[8]: 0x2A00_0000-0x56FF_FFFF (MBCA = 1111)\nR[9]: 0x2340_000A-0x600F_FFFF (MBCA = 0001)\nR[10]: 0x2000_0000-0x63FF_FFFF (MBCA = 0101)\nR[11]: 0x13AC_AA55-0x7FFF_FFFF (MBCA = 1011)\nR[12]: 0x1000_000F1-0x82FF_FFFF (MBCA = 1101)\nR[13]: 0x0500_0000-0x8459_FFFF (MBCA = 0100)\nR[14]: 0x0200_0000-0xEFFF_FFFF (MBCA = 0000)\nR[15]: 0x0000_A000-0xFFFE_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 5, aims to verify the following:\n1. Region match priority\n2. Maximum number of separate areas in memory (33)\n\nAddress may be modified to better suit implementation and verification enviornment, but the following criteria must be met:\n1. Each defined region must be enclosed by the adjacent region of lower priority\n2. No region boundaries must overlap\n3. There shall be undefined space prior to and aft of largest, highest numbered region\n", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nR[0]: 0x0001_0000-0x001F_FFFF (MBCA = 1001)\nR[1]: 0x0030_0000-0x04FF_FFFF (MBCA = 1111)\nR[2]: 0x1000_0000-0x1001_0000 (MBCA = 0100)\nR[3]: 0x1800_1234-0x18FF_AB21 (MBCA = 0000)\nR[4]: 0x2020_0010-0x2FFF_0000 (MBCA = 0001)\nR[5]: 0x3100_A000-0x32FF_FFFF (MBCA = 1111)\nR[6]: 0x3440_0000-0x3800_FFFF (MBCA = 0100)\nR[7]: 0x4AAA_F000-0x4C00_FFFF (MBCA = 1101)\nR[8]: 0x4D00_5555-0x4FFF_ABCD (MBCA = 1011)\nR[9]: 0x5100_0000-0x52FF_FFFF (MBCA = 0000)\nR[10]: 0x5400_0000-0x5FFF_FFFF (MBCA = 1111)\nR[11]: 0x6300_0000-0x6700_FFFF (MBCA = 0101)\nR[12]: 0xA000_0000-0xAFFF_FFFF (MBCA = 1001)\nR[13]: 0xBC00_0000-0xBCFF_FFFF (MBCA = 1101)\nR[14]: 0xC000_0000-0xDFFF_FFFF (MBCA = 0001)\nR[15]: 0xE700_EF00-0xE9FF_FFFF (MBCA = 0101)", + "Verification Goal": "Test configuration 6, aims to verify designs with the following characteristic:\n1. Non-contiguously defined maximum number of memory regions\n2. Maximum number of separate areas In memory (33)\n3. No overlap, single matching regions\n4. Non-defined areas prior and aft of each defined region\n\nAddress map may be modified to better suit actual implemetations, but the above criteria must be adhered to.", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nNote: Zero length regions are intentional\nR[0]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[1]: 0x5555_5555-0x5555_5555 (MBCA = 0000)\nR[2]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[3]: 0xAAAA_AAAA-0xAAAA_AAAA (MBCA = 0000)\nR[4]: 0xCCCC_CCCC-0xCCCC_CCCC (MBCA = 0000)\nR[5]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[6]: 0xE38E_E38E-0xE38E_E38E (MBCA = 0000)\nR[7]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[8]: 0xFFFF_FFFF-0xFFFF_FFFF (MBCA = 0000)\nR[9]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[10]: 0x9249_2492-0x9249_2492 (MBCA = 0000)\nR[11]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[12]: 0xDB6D_B6DB-0xDB6D_B6DB (MBCA = 0000)\nR[13]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[14]: 0x1249_2492-0x1249_2492 (MBCA = 0000)\nOnly one non-zero region:\nR[15]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 7, aims to verify the following:\n1. Zero length regions does not match any accesses\n2. Upper/Lower bound of outlier (last) region set to min/max of address range\n\nAddress map may be modified to better suit actual implementations, but R[15] must be defined to min/max possible address range. Remaining regions shall have 0 length.\n", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "Coverpoints", + "Feature Description": "Instruction fetch coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing instruction fetch", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "Note: These could also have used RVFI instead.\n\nNote: Not very feasible to match on every single cfg index, because some are overshadowed by overlapping regions and to model this is expensive." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Load instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing load instruction", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Store instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing store instruction", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Atomic instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic operation", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Load alignment error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with load alignment error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Store alignment error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with store alignment error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Atomic load-reserved unallowed error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic load-reserved unallowed error", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Atomic store-conditional unallowed error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic store-conditional unallowed error", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "Risc-V Priv. spec", + "Feature": "PMA Readability", + "Sub Feature": "PMA readable by SW", + "Feature Description": "Design must support SW readback of attributes", + "Verification Goal": "N/A. Can be SW-readable via a C-header, or is otherwise the responsibility of integration- or system-level testing.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Code Execution", + "Sub Feature": "Code Execution only from main memory", + "Feature Description": "Code execution is not allowed from IO region, any attempts to do so should result in an instruction access fault (exception code 1)", + "Verification Goal": "Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nE.g. execute a JMP instruction to an area defined as IO (and/or unconfigured PMA region) and verify that an instruction access fault is triggered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Code Execution", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nE.g. execute a JMP instruction to an area defined as IO (and/or unconfigured PMA region) and verify that an instruction access fault is triggered", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg.cross_pma", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Code Execution", + "Sub Feature": "Instruction fetch violation coverpoints", + "Feature Description": "Instruction group type for failing instruction fetch violations", + "Verification Goal": "Instruction group type cover from ISACOV for each violated PMA instruction fetch", + "Pass/Fail Criteria": "Other", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: TODO", + "Comment": "TODO missing cover. (Problem: Depends on ISACOV updates.)" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Access match", + "Sub Feature": "Non-Overlapping PMA Regions", + "Feature Description": "A match should always be inside its matching region, \nLower_bound[region] <= addr[addr_max:2] < Upper_bound[region]", + "Verification Goal": "Assert that match[region] always implies that the following holds: \nlower[region] & 2'b00 <= addr[31:0] < upper[region] 2'b00", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_bounds\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_bounds", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses: Verify that accesses are matched to their respective memory regions", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "ENV capability, not specific test", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses: Verify that accesses are matched to their respective memory regions", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch*\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_matchregion*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "Overlapping PMA Regions", + "Feature Description": "Any access matching multiple regions should attain the attributes of the lowest numbered matching region", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "Non-Matching Accesses", + "Feature Description": "PMA_NUM_REGIONS==0: \nAccesses not matching attribute regions should be treated as: \nMemory\nNon-Bufferable\nNon-Cacheable\nAtomic operations not allowed", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should pass\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should pass", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_0reg/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should pass\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should pass", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", + "Comment": "TODO is the random stream run without pma regions?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "PMA_NUM_REGIONS>0\nAccesses not matching attribute regions should be treated as: \nIO\nNon-Bufferable\nNon-Cacheable\nAtomic operations not allowed", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should fail\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should fail", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should fail\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should fail", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "OBI transfer flags", + "Sub Feature": "InstructionFetches", + "Feature Description": "Bufferable flag effects - For any instruction fetch marked bufferable, the corresponding OBI transfer instr_memtype[0] signal should be set to match the bufferable flag.", + "Verification Goal": "Ensure that instr_memtype[0] is set to 1 when an instruction fetch attempt is performed with the bufferable flag set to 1. (Which is never, because \"Accesses to regions marked as bufferable (bufferable=1) will result in the OBI mem_type[0] bit being set, except if the access was an instruction fetch [...]\".)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that instr_memtype[0] is set to 0 when an instruction fetch attempt is performed with the bufferable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Cacheable flag effects - For any instruction fetch marked cacheable, the corresponding OBI transfer instr_memtype[1] signal should be set to match the cacheable flag.", + "Verification Goal": "Ensure that instr_memtype[1] is set to 1 when an instruction fetch attempt is performed with the cacheable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk5.a_pma_obi_cacheon\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that instr_memtype[1] is set to 0 when an instruction fetch attempt is performed with the cacheable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_cacheoff\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Instruction fetch attempts to PMA restricted regions should cause instr_req_o to be deasserted.", + "Verification Goal": "Ensure that PMA-violating instruction fetch attempts does not assert the instr_req_o signal by attempting execution of instructions from allowed and restricted areas of memory, checking that instr_req_o remains deasserted when restricted areas are accessed", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_req_prohibited\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "DataFetches", + "Feature Description": "Bufferable flag effects - data_memtype[0] should match the bufferable flag.", + "Verification Goal": "Ensure that data_memtype[0] is set to 1 when a data fetch attempt is performed with the bufferable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk4.a_pma_obi_bufon\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that data_memtype[0] is set to 0 when a data fetch attempt is performed with the bufferable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Cacheable flag effects - data_memtype[1] should match the cacheable flag", + "Verification Goal": "Ensure that data_memtype[1] is set to 1 when an data fetch attempt is performed with the cacheable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk5.a_pma_obi_cacheon\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that data_memtype[1] is set to 0 when an data fetch attempt is performed with the cacheable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_cacheoff\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Data fetch attempts to PMA restricted regions should cause data_req_o to be deasserted.", + "Verification Goal": "Ensure that PMA violating data fetch attempts does not assert the data_req_o signal", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_req_prohibited\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "Non-naturally aligned data accesses shall only occur for Main memory accesses.", + "Feature Description": "Non-naturally aligned load access attempts to I/O shall\n cause a precise load access fault (exception code 5).", + "Verification Goal": "Attempt arbitrary non-naturally aligned load accesses to I/O regions specified by PMA and ensure that these accesses triggers precise load access fault exceptions (code 5). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions. \n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nld from addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nlw from addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nlh from addresses in IO space with and_reduce(addr_lsb[1:0]) = 1\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary non-naturally aligned load accesses to I/O regions specified by PMA and ensure that these accesses triggers precise load access fault exceptions (code 5). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions. \n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nld from addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nlw from addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nlh from addresses in IO space with and_reduce(addr_lsb[1:0]) = 1\n", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*", + "Comment": "TODO missing \"ld/lw/lh\" specific covers." + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "Non-naturally aligned store access attempts to I/O shall\n cause a precise store access fault (exception code 7).", + "Verification Goal": "Attempt arbitrary non-naturally aligned store accesses to I/O regions specified by PMA and ensure that these accesses triggers precise store access fault exceptions (code 7). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nsd to addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nsw to addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nsh to addresses in IO space with and_reduce(addr_lsb[1:0]) = 1", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary non-naturally aligned store accesses to I/O regions specified by PMA and ensure that these accesses triggers precise store access fault exceptions (code 7). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nsd to addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nsw to addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nsh to addresses in IO space with and_reduce(addr_lsb[1:0]) = 1", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*", + "Comment": "TODO missing \"sd/sw/sh\" specific covers." + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "Multi-memory operation instructions", + "Feature Description": "When the first memory access of a non-naturally aligned load operation fails due to PMA checks, the second memory access shall also be supressed. ", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A :uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_failure_denies_subsequents\n\nRTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "If a PMA access fault occurs for any of the memory accesses in a non-naturally aligned load, the register file shall not be updated", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n- Boundary between IO region and memory region s.t. first access will be in memory and second access will be in IO.\n\nIn both cases, the register file should remain unchanged.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n- Boundary between IO region and memory region s.t. first access will be in memory and second access will be in IO.\n\nIn both cases, the register file should remain unchanged.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "When the first memory access of a non-naturally aligned store operation fails due to PMA checks, the second memory access shall also be supressed. ", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Zce Extension", + "Sub Feature": "Push instructions", + "Feature Description": "push, push.e, c.push, c.push.e instructions shall only occur for main memory regions, any such *push* attempts to I/O shall cause a precise load access fault (exception code 5)", + "Verification Goal": "Attempt *push* operations to main memory and IO, verify that all *push* attempts to IO causes a precise store access fault (code 5) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt *push* operations to main memory and IO, verify that all *push* attempts to IO causes a precise store access fault (code 5) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*", + "Comment": "TODO missing random test?\n\nNote: Cover doesn't check that it goes through WB." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "Pop instructions", + "Feature Description": "pop, popret, pop.e, popret.e, c.pop, c.popret, c.pop.e, c.popret.e shall only occur for main memory regions, any such *pop* attempts from I/O shall cause a precise load access fault (exception code 7)", + "Verification Goal": "Attempt *pop* operations to main memory and IO, verify that all *pop* attempts to IO causes a precise loac access fault (code 7) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt *pop* operations to main memory and IO, verify that all *pop* attempts to IO causes a precise loac access fault (code 7) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*", + "Comment": "TODO missing random test?\n\nNote: Cover doesn't check that it goes through WB." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "Table Jump", + "Feature Description": "Both jumps from a Zce table jump should be checked by PMA and handled as instruction fetches. \n\nPMA failure in the first table jump should suppress the second jump - instr_fetch_o should be suppressed and no jump to the restricted address shall be performed", + "Verification Goal": "First jump: Testing a violating first jump (jump to the jump table) requires a custom linker script that deliberatly places the jump table in a non-executable (IO) region. A test must verify that instructions attempting to jump to the jump table location causes an instruction access fault (exception code 1) and that instr_req_o is suppressed\n\nThe second instruction fetch should be suppressed.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Second jump: Test should verify that a PMA access fault on the second jump (jump to the actual instruction address in IO region) should cause an instruction access fault (exception code 1), suppressing instr_req_o. ", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Coverpoint - Table jumps passing PMA checks crossed with region index or default unmapped memory region", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_pmafault_tablejump_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_firstfail_tablejump:_*\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_allow_jvt_*", + "Comment": "TODO missing random test?\n\nNote: This is not maximally comprehensive, but the modelling that would otherwise be required is disproportionately complex." + }, + { + "Requirement Location": "Zce spec. proposal", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "Instruction fetch exceptions occurring when executing an address in the jump table should lead to mepc being set to the C.TBLJ* instruction, and mtval to the address in the jump table entry", + "Verification Goal": "Verify that an instruction fetch exception resulting from a jump table entry leads to mepc being set to the C.TBLJ* instruction and mtval to the address in the jump table entry.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "Risc-V Debug spec.", + "Feature": "Debug mode", + "Sub Feature": "Single step PMA exceptions", + "Feature Description": "Any instruction fetch exception that occurs while single stepping, causes debug mode to be re-entered after PC is changed to the exception handler and the appropriate tval and cause registers are updated", + "Verification Goal": "Verify that instruction fetches to PMA IO regions fails, the appropriate CSRs and PC is updated to the appropriate values and debug mode is reentered. ", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_debug/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "Program buffer PMA exceptions", + "Feature Description": "Exceptions in the program buffer should cause the program buffer code to end and cmderr set to 3 (exception error)", + "Verification Goal": "Verify that program buffer code attempting to fetch instructions from PMA IO region fails, PC is set to dm_exception_addr_i and cmderr is set to 3 (exception error). No other registers should be changed due to this exception.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_debug/", + "Comment": "" + }, + { + "Requirement Location": "40s UM 0.8.0", + "Feature": "DebugRange", + "Sub Feature": "DebugRange", + "Feature Description": "\"CV32E40S overrules the PMA and PMP settings for the Debug Module region when it is in debug mode\"", + "Verification Goal": "Attempt access within/outside the dm region, in both dmode/not, check that the combo within/dmode never gets blocked and that the other combos follow the ordinary rules.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Code Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_dm_region\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_dm_region\n\nA: (The other cases are covered by all other testing.)\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_dmregion_dmode_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Atomic operations", + "Sub Feature": "Atomic operations shall only occur for regions in which Atomic operations are allowed. (Only applies for cores with A-extension)", + "Feature Description": "Load-Reserved attempts to a region where atomic operations are not permitted shall cause a precise load access fault (exception code 5)", + "Verification Goal": "Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Atomic operations", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Atomic operations", + "Sub Feature": "", + "Feature Description": "Store-Conditional or Atomic Memory Operation (AMO) attempts to a region where Atomic operations are not allowed shall cause a precise store/AMO access fault (exception code 7).", + "Verification Goal": "Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Atomic operations", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "(N/A for 40s)", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Fence* instructions", + "Sub Feature": "Fence instructions disregards distinction between memory and IO", + "Feature Description": "Fence instruction shall not be impacted by PMA memory/IO attribute and execute as a conservative fence on all operations ", + "Verification Goal": "Coverpoint - Fence instructions (Fence, fence.i) should not be impacted by PMA.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_waspmafault_wasmain_wasloadstore_fence_*", + "Comment": "TODO missing random test?" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "WriteBuffer", + "Sub Feature": "Bufferable operations", + "Feature Description": "Only bufferable store accesses should use the internal write buffer", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.a_writebuf_bufferable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.gen_noregions_nobuf.a_writebuf_noregions\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------END---------", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx new file mode 100755 index 0000000000..6e5553c3a0 Binary files /dev/null and b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.csv b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.csv new file mode 100644 index 0000000000..a5ddbacddd --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.csv @@ -0,0 +1,542 @@ +Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,High Priority?,Link to Coverage,Comment +,Comments,SmepmpOverrule,"The ""smepmp"" spec features can overrule the ""privspec"" (e.g. for locking). Both specs are included here, so be mindful that checking of certain vplan items could be conditional.",N/A,N/A,N/A,N/A,,N/A, +,,FunctionalCoverage,"Functional coverage is encouraged to be creative in capturing a broad set of possible state, and evaluate it towards the checkers, to catch aspects of pmp functionality that this vplan might have overlooked.",N/A,N/A,N/A,N/A,,N/A, +,,ImplementationChanges,"If test implementation reveals new knowledge that contradicts or augments this vplan, then the vplan should be updated.",N/A,N/A,N/A,N/A,,N/A, +,,TimeAllowance,"Some verification goals in this plan has a ""base level"" of checking plus some optional tweaks that might be tried. It is up to the testing implementation how to prioritize and potentially skip the extras, according to what time allows.",N/A,N/A,N/A,N/A,,N/A, +privspec,General,Configs,"The pmp must be tested in a wide range of configurations. That includes testing on both instruction-side and data-side, and it includes testing overlapping regions, non-overlaping, no regions, differing settings for overlapping regions, M-mode only, U-mode only, both M-mode and U-mode, etc, etc. Use functional coverage with plenty of crosses.","Run with different configs to test parameters in low/mid/high ranges and in combination with the other parameters, instantiate checking on both instruction-side and data-side, write coverage to see all relevant region overlap combinations and to see an exhaustive combination of block-level input combinations and functional-level states.",Other,"ENV capability, not specific test",Functional Coverage,,COV: ???,TODO missing cover +,,Smepmp,"Given 1) backwards-compatible reset values, and 2) no change in ""mseccfg"", then C) the PMP should be fully compatible with the privspec.","For all privspec-derived PMP assertions, check that they must hold as long as the two preconditions hold (i.e. must not be excusable/overridable by smepmp features).",Other,Other,N/A,,N/A, +,,UmodeAlways,"""PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches in S and U mode, data accesses in S and U mode when the MPRV bit in the mstatus register is clear, and data accesses in any mode when the MPRV bit in mstatus is set and the MPP field in mstatus contains S or U."" + +Note: None of those scenarios should let an access bypass the pmp.","Set up the system to match each point in the listing, ensure that the pmp's decision matches all modelled expectations. + +Note: Also cover when none of the listed preconditions are active and the pmp's decision can disagree with the modelled expectations.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_* + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_* + +COV: ???","(Same as for ""MmodeDeny"")" +,,DefaultNone,"""PMP can grant permissions to S and U modes, which by default have none""","Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then U-mode has no access permissions.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,,"A: ??? + +DTC: cv32e40s/tests/programs/custom/pmp/",TODO missing assert +,,DefaultFull,"""can revoke permissions from M-mode, which +by default has full permissions""","Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then M-mode has full access permissions.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,,"A: ??? + +DTC: cv32e40s/tests/programs/custom/pmp/",TODO missing assert +,Csrs,ResetRegisters,"""Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers’ A and L fields.""","Read the A and L values right after reset, ensure that the default reset values are 0. + +Note: Should also be visible on rvfi without specifically using csr instructions.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,,"A: ??? + +DTC: cv32e40s/tests/programs/custom/pmp/",TODO missing assert +,,Warl,"""All PMP CSR fields are WARL and may be hardwired to zero"". + +Note: A field shall also not change its value when an attempt is made to write an illegal value to it. (XWR is one field.)","Try writing any values to the registers and read values out of them, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected and that illegally written fields don't change.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected + +COV: ???",TODO missing cover +,,MmodeOnly,"""PMP CSRs are only accessible to M-mode.""","Try to access any of the pmp CSRs from U-mode, ensure that it always gives ""illegal instruction exception"" and that the CSRs are not updated. + +Note: M-mode accesses are covered by AlwaysAccessible below.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_csrs_mmode_only + +COV: ??? + +DTC: cv32e40s/tests/programs/custom/pmp/","TODO missing cover (combine with ""Warl"" above)" +,,Addr34bit,"""Each PMP address register encodes bits 33–2 of a 34-bit physical address for RV32""","Ensure that when the pmpaddr MSBs are set, then no NAPOT accesses matches. Cover that all bits have been matched against (""toggle cross""). Ensure that there are no attempted accesses to MSBs that the core should not be able to use.",Assertion Check,Constrained-Random,Functional Coverage,,"A: ??? + +COV: ???","TODO missing assert + +TODO missing cover" +,,AddrImplemented,"""Not all physical address bits may be implemented, and so the pmpaddr registers are WARL.""",Cover (toggle) that all bits can be both written and set. (UnusedZero below covers the WARL(0x0) case.),Other,Constrained-Random,Functional Coverage,High Priority,COV: ???,TODO missing cover +,AddressMatching,MatchDisabled,"""When A=0, this PMP entry is disabled and matches no addresses"" +When a cfg is set to off but its address(es) (interpreted as napot/tor) is the only rule that matches an attempted access, then it still does not count as a match.","Have a region's address(es) set up as tor and napot (separate runs), have all other regions not include the target address, have the target region's rule be OFF, make an access within that range, ensure that the outcome is the same as for when an access is outside of all address ranges. + +Note: For this and several other items, functional coverage is necessary because the checking doesn't necessarily have the above scenario in its antecedent. + +Coverage: Capture the above scenario, minus the checking.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???",TODO missing cover +,,NapotMatching,"""NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range [""yyyy...yy01"" etc]"" + +Note: The napot address matching modes match on addresses that are equal to the requested access when masked to the granularity size.","Configure napot rules of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated sizes. + +Note: Includes NAPOT and NA4. + +Note: Try also max and min.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4is4byte.a_na4_is_4byte + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_bin_auto[*] +dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_disallowed_bin_auto[*] + +COV: ???",TODO missing coverage +,,TorMatching,"""If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range. If PMP entry i’s A field is set to TOR, the entry matches any address y such that pmpaddri−1 ≤ y < pmpaddri (irrespective of the value of pmpcfgi−1)""","Configure tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_ismatch_tor_bin_auto[*] + +COV: ???",TODO missing coverage +,,TorZero,"""If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr0.""","Configure entry 0 as tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ??? + +DTC: cv32e40s/tests/programs/custom/pmp/",TODO missing cover +,,TorNomatch,"""If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses.""","Set up tor regions where the addresses are not in increasing order, try accesses on or within the designated ""reverse"" regions, ensure that they are treated as if there is no match.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ??? + +DTC: cv32e40s/tests/programs/custom/pmp/",TODO missing cover +,,SameGrain,"""In general, the PMP grain [...] must be the same across all PMP regions.""","Do the same as for the basic case of GranularityDetermination below, ensure that all read values are the same across all the pmp csrs.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,,A: ???,TODO missing assert +,,Na4Unselectable,"""When G ≥ 1, the NA4 mode is not selectable.""","Have the G parameter set to at least 1, ensure that NA4 never gets selected (even when writing to non-locked cfg). + +Note: Formal should easily check this.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_only_g0 +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_only_g0 + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_not_when_g uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_not_when_g", +,,NapotImplied,"""When G ≥ 2 and pmpcfgi.A[1] is set, i.e. the mode is NAPOT"".",(Covered by Na4Unselectable above),Other,Other,N/A,,N/A, +,,NapotOnes,"""When G ≥ 2 and pmpcfgi.A[1] is set, [...] then bits pmpaddri[G-2:0] read as all ones.""","Have the G parameter set to at least 2, have A set, read pmpaddri, ensure the LSBs are all ones as specified.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_napot_ones_g2.gen_napot_ones_i[*].a_napot_ones, +,,AllZeros,"""When G ≥ 1 and pmpcfgi.A[1] is clear, i.e. the mode is OFF or TOR, then bits pmpaddri[G-1:0] read as all zeros.""","Create the listed preconditions, ensure that the read value contains zeroes as specified. + +Note: Check both OFF/TOR, and for all configs fields (checking of all configs don't need 100% coverage in simulation).",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_all_zeros_g1.gen_all_zeros_i[*].a_all_zeros + +COV: ???",TODO missing cover +,,TorUnaffected,"""Bits pmpaddri[G-1:0] do not affect the TOR address-matching logic.""","Write different values to ""pmpaddri[G-1:0]"", ensure TOR mode matches the same either way.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,StorageUnaffected,"""Although changing pmpcfgi.A[1] affects the value read from pmpaddri, it does not affect the underlying value stored in that register"" +""in particular, pmpaddri[G-1] retains its original value when pmpcfgi.A is changed from NAPOT to TOR/OFF then back to NAPOT.""","Change in and out of (OFF || TOR) and !(OFF || TOR), ensure that different values can be read without having written anything new to the register.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_storage_unaffected[*].a_storage_unaffected + +COV: ???",TODO missing cover +,,GranularityDetermination,"""Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading back pmpaddr0. If G is the index of the least-significant bit set, the PMP granularity is 2 G+2 bytes.""","Write zero to pmpicfg, write ones to pmpaddri, read pmpaddri, ensure that the LSB index matches to granularity parameter. + +Note: Formal can maybe check this for all i. + +Note: If time allows, can write something else than zero and ensure that the rest follows as expected.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_granularity_determination, +,,XlenMatching,"""If the current XLEN is greater than MXLEN, the PMP address registers are zero-extended from MXLEN to XLEN bits for the purposes of address matching.""",N/A,N/A,N/A,N/A,,N/A, +,LockingAndPrivmode,UntilReset,"""Locked PMP entries remain locked until the hart is reset.""","Lock entry i (for all i, if feasible), ensure that the lock bit is never lifted before reset. (Unless if RLB interferes.) + +Note: Sim might do a second reset, formal most likely won't and shouldn't need to.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_until_reset[*].a_until_reset, +,,IgnoreWrites,"""If PMP entry i is locked, writes to pmpicfg and pmpaddri are ignored.""","Lock entry i (for all i, if feasible), ensure that their value can't change, both when written to and otherwise. (Unless if RLB interferes.)",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_notrap[*].a_ignore_writes_notrap + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_nochange[*].a_ignore_writes_nochange + +COV: ???",TODO missing cover +,,IgnoreTor,"""Additionally, if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored.""","Lock entry i (…), have A set and the mode be TOR, ensure that pmpaddri-1 can't change, both for explicit writes and otherwise. (Unless RLB.)",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_stable + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_wdata + +COV: ???",TODO missing cover +,,NotIgnore,"When neither cfg i is locked, nor is cfg i+1 a locked TOR region, then writes to cfg and addr i are not ignored.","Have cfg i unlocked, write to cfg and addr csr i, check that it changes.",Assertion Check,Constrained-Random,Assertion Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_writes[*].a_addr_nonlocked + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_tor[*].a_addr_nonlocked_tor", +,,LockOff,"""Setting the L bit locks the PMP entry even when the A field is set to OFF.""","Lock entry i while the mode is OFF, ensure that it gets locked in this case too. + +Note: Ensure that checking and coverage handles locking for all possible modes.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: (Same checking as for ""IgnoreWrites"" and ""IgnoreTor"" above.) + +COV: ???",TODO missing cover +,,RwxPrivmode,"""In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are enforced on M-mode accesses. When the L bit is set, these permissions are enforced for all privilege modes.""","Be in M-mode and U-mode (separate runs), access a region where L is set and where RWX {grant, deny R, deny W, deny X}, ensure that the access is correspondingly granted/denied.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???",TODO missing cover +,,MmodeSucceed,"""When the L bit is clear, any M-mode access matching the PMP entry will succeed""","Be in M-mode, access a region where L is clear, ensure that access is granted in all cases. + +(Note, see ""Smepmp"" above.)",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,RwxUmode,"""When the L bit is clear […] the R/W/X permissions apply only to S and U modes.""","Be in U-mode, access a region where L is clear, ensure that access is granted/denied based on RWX.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_uorl_onlyif_rwx +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_uorl_onlyif_rwx + +COV: ???",TODO missing cover +,PriorityAndMatching,LowestDetermines,"""PMP entries are statically prioritized. The lowest-numbered PMP entry that matches any byte of an access determines whether that access succeeds or fails."" + +Note: ""any"" byte.","Access a region that is covered by multiple rules, ensure that the lowest indexed match determines the outcome. + +Note: Requires that the rules would disagree on the outcome.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???",TODO missing cover +,,MatchAll,"""The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits.""",(Only relevant for 64-bit architectures.),N/A,N/A,N/A,,N/A, +,,LrwxDetermines,"""If a PMP entry matches all bytes of an access, then the L, R, W,and X bits determine whether the access succeeds or fails. [...] if the L bit is set or the privilege mode of the access is S or U, then the access succeeds only if the R, W,or X bit corresponding to the access type is set.""","Access a pmp region where L and the privmode etc is such that nothing else would deny the access, ensure that each of (or a combination of) RWX can either grant or deny the access.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_lrwx_aftermatch + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_lrwx_aftermatch + +COV: ???",TODO missing cover +,,MmodeSucceed2,"""If the L bit is clear and the privilege mode of the access is M, the access succeeds.""","(Same as ""MmodeSucceed"" above)",Other,Other,N/A,,N/A, +,,MmodeNomatch,"""If no PMP entry matches an M-mode access, the access succeeds.""","Be in M-mode, access a region where no rule matches, ensure that the access is granted (where MMWP is off). + +(Note, see ""Smepmp"" above.)",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal + +COV: ???",TODO missing cover +,,UmodeNomatch,"""If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails."" + +Note: ""All PMP CSRs are always implemented"".","Be in U-mode, do an access that doesn't match any region, ensure that the access fails.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_umode_fails + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_umode_fails + +COV: ???",TODO missing cover +,,UmodeOff,"""If at least one PMP entry is implemented, but all PMP entries’ A fields are set to OFF, then all S-mode and U-mode memory accesses will fail.""","Be in U-mode, have all entries OFF, make an access, ensure that the access fails (for all variations of accesses).",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???",TODO missing cover +,,FailException,"""Failed accesses generate an instruction, load, or store access-fault exception.""","Cause failed accesses on instructions/loads/stores, ensure that an exception occurs and that it is the right one.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_* + +A: ::uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_* + +COV: ???",TODO missing cover +,,MultiAccess,"""Note that a single instruction may generate multiple accesses, which may not be mutually atomic. An access-fault exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects."" + +""On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an access-fault exception occurs. In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check.""","Induce misaligned word instruction-fetch, load, and store, where the lower and upper (separate runs) parts are either accessible or blocked by pmp, ensure that exceptions occur while parts of the access might reach the bus. + +Also check Zc's push/pop and table jump. + +Note: It is up to other vplans to check what happens upon the exception. It is up to this PMP vplan to check that the PMP will cause the exceptions.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap + +A: ??? + +COV: ???","TODO missing assert (on split that errs on first) + +TODO missing cover" +smepmp,MsecCfg,MmodeOnly,"""Machine Security Configuration (mseccfg) is [...] only accessible to Machine mode."" + +Note: Includes ""mseccfgh"".","Access (read/write) mseccfg (and mseccfgh) from M-mode, access mseccfg from U-mode, ensure that the first always works (WARL) and the second never works (exception). + +Note: Cover with MPRV too.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,A: ???,TODO missing assert +,,FieldsWarl,"""All mseccfg fields defined on this proposal are WARL""","Try writing any values to the fields (the defined ones, but also other bits) and read values out of the fields, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected. + +Note: This relates to the ""stickiness"" of those fields. Regardless of their values and current stickiness, the fields are WARL. + +Note: It might be difficult, when trying to write a checker for traps, to filter out all other causes for traps that can occur simultaneously. (Either reduce the scope of checking, or write re-usable helper signals for ""trap causality"" info.) + +Note: ""WPRI"" on some bits.",Assertion Check,Constrained-Random,Functional Coverage,,"A: ??? + +COV: ???","TODO missing assert + +TODO missing cover" +,,ReservedZero,"""the remaining bits are reserved for future standard use and should always read zero."" +(This spec can't dictate that about other specs, but the user manual agrees on the hardwiring.)","Read mseccfg, ensure the non-smepmp-field bits are always zero.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,A: ???,TODO missing assert +,,ResetValue,"""The reset value of mseccfg is implementation-specific, otherwise if backwards compatibility is a requirement it should reset to zero on hard reset.""","Read the value of mseccfg right after reset, ensure that the default reset value is zero. + +Note: Should also be visible on rvfi without specifically using csr instructions.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mseccfg_reset_val + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mseccfg_reset_val", +,LockingBypass,ModifiableEntries,"""When mseccfg.RLB is 1 locked PMP rules may be removed/modified and locked PMP entries may be edited."" + +Note: Both ""cfg"" and ""addr"" registers, limited to fields within ""cfg"" reg, also TOR affects lower ""addr"" reg.","Have a locked pmp entry i, set RLB to 1, try modifying any(!) field within {pmpicfg, pmpaddri, pmpaddri-1(tor)}, ensure that values are updated succesfully (while respecting other rules like legal values and reserved bits).",Assertion Check,Constrained-Random,Functional Coverage,,"A: ??? + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_addr + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_exec + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_lock + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_mode + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_read + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_write + +COV: ???",TODO missing assert +,,RemainZero,"""When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset"" + +Note: ""any"" entry.","Have RLB=0 and at least one L=1, ensure that RLB is 0 forever (until reset). + +Note: No exception occurs on attempted access, but one should try overwriting the value to stimulate the checking.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_rlb_never_fall_while_locked + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_rlb_never_fall_while_locked", +,,UntilReset,"The sticky zero and update-ignores last until reset, and do not hold after reset.",Ensure that RLB is modifiable after reset. (Unless if reset values are set to activate the RemainZero condition.),Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_until_reset_notbefore + +COV: ???",TODO missing cover +,,HardwireZero,"""Vendors who don’t need this functionality may hardwire this field to 0.""","(40s has not hardwired this to 0, it is RW.)",N/A,N/A,N/A,,N/A, +,WhiteList,StickyUntilReset,"""[mseccfg.MMWP] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.""","Have MMWP set, ensure that it remains high forever (til reset).",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mmwp_never_fall_until_reset + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mmwp_never_fall_until_reset", +,,Denied,"""When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching PMP rule, to denied instead of ignored.""","Have MMWP set, be in (effective mode) M-mode, access regions that don't match any rule (including OFF, ""reversed"" TOR, >32bit NAPOT, etc), ensure that the access is denied.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_mmode_mmwp_fails + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_mmode_mmwp_fails + +COV: ???",TODO missing cover +,LockdownGeneral,StickyUntilReset,"""[mseccfg.MML] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.""","Cover: Trying to clear the bit. + +Check: Have MML set, ensure that it remains high forever (til reset).",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mml_never_fall_until_reset + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mml_never_fall_until_reset + +COV: ???",TODO missing cover +,,ExecIgnored,"""[When mseccfg.MML is set.] Adding an M-mode-only or a locked Shared-Region rule with executable privileges is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged."" + +Note: ""pmpcfg"" refers to a field, so the write to the CSR itself should still update other fields.","Have MML set, try adding an ""M-mode-only"" rule and a ""locked Shared-Region"" rule with X privileges, ensure that the relevant pmpcfg field is not updated but is left unchanged, ensure also that other fields can still get updated.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore + +COV: ???",TODO missing cover +,,ExecRlb,"""[The above] restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB.""","Have RLB and MML set, try adding an ""M-mode-only"" rule and a ""locked Shared-Region"" rule with X privileges, ensure that the relevant pmpcfg field is in fact updated.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rlblifts_lockedexec[*].a_rlblifts_lockedexec, +,,MmodeExec,"""Executing code with Machine mode privileges is only possible from memory regions with a matching M-mode-only rule or a locked Shared-Region rule with executable privileges. Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied.""","Execute from ""M-mode-only"" and ""locked Shared-Region"" regions, attempt execution without matching and from ""U-mode-only"" regions, ensure corresponding grant or deny.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???",TODO missing cover +,,RwReserved,"""If mseccfg.MML is not set, the combination of pmpcfg.RW=01 remains reserved for future standard use.""","Whitelist the conditions that allow RW=01 (including MML conditions), ensure that it is adhered to.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rwx_mml[*].a_rwx_mml + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rwfuture[*].a_rw_futureuse +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rwfuture[*].a_rw_futureuse", +,LockdownA,MmodeEnforce,"""[When mseccfg.MML is set.] An M-mode-only rule is enforced on Machine mode""","Be in M-mode, have MML set, access an ""M-mode-only"" region, ensure that the grant/deny is always in accordance to the rule. (E.g. it is not denied execute despite the execute bit being set.) + +Note: Exclude cases of interference from e.g. PMA.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,UmodeDeny,"""[When mseccfg.MML is set.] An M-mode-only rule is [...] denied in Supervisor or User mode.""","Be in U-mode, have MML set, access an ""M-mode-only"" region, ensure that the access is always denied.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,RemainLocked,"""It also remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset"" + +Certain rules under MML are sticky. They cannot be modified again.","Configure rules for {""M-mode-only"", ""U-mode-only, ""Shared-Region rule where pmpcfg.L is set""(both kinds)}, have MML=1 (and RLB=0), ensure that the configs never change again (until reset).",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: ??? + +COV: ???",TODO missing assert +,,RlbUnlocks,"""It also remains locked [...] unless mseccfg.RLB is set.""","Have the same setup as in RemainLocked, but let RLB=1, try changing the configs, ensure that they are indeed changed. + +Note: ""Assertion check"" includes cover properties.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: ??? + +COV: ???",TODO missing assert +,,UmodeEnforce,"""[When mseccfg.MML is set.] An S/U-mode-only rule is enforced on Supervisor and User modes ""","Be in U-mode, have MML=1, access a ""U-mode-only"" region, ensure that the grant/deny is in accordance with the rule (apart from PMA etc).",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cg_data + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cg_instr + +COV: ???","(Same as for ""MmodeDeny"")" +,,MmodeDeny,"""An S/U-mode-only rule is [...] denied on Machine mode.""","Be in M-mode, have MML=1, access a ""U-mode-only"" region, ensure that the access is always denied.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???",TODO missing coverage. (Just do a cg with crosses of all of these variables.) +,,SharedEnforced,"""A Shared-Region rule is enforced on all modes""","Be in M-mode and U-mode (separate runs), access a ""Shared-Region"", ensure that the grant/deny is in accordance with the rule.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,SharedNoexec,"""A Shared-Region rule where pmpcfg.L is not set can be used for sharing data between M-mode and S/U-mode, so is not executable.""","Be in M-mode and U-mode, try to execute from ""A Shared-Region rule where pmpcfg.L is not set"", ensure that it does not work (exception).",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,MmodeReadwrite,"""[Shared-Region rule where pmpcfg.L is not set.] M-mode has read/write access to that region""","Be in M-mode, perform reads and writes to such a region, ensure that the intended effects happen and that the accesses do not cause exceptions.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,UmodeRead,"""[For a Shared-Region rule where pmpcfg.L is not set] S/U-mode has read access if pmpcfg.X is not set, or read/write access if pmpcfg.X is set.""","Be in U-mode, perform reads and writes to such a region, ensure that the reads always work and that the writes depend on X.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,SharedNowrite,"""A Shared-Region rule where pmpcfg.L is set can be used for sharing code between M-mode and S/U-mode, so is not writeable."" + +Note: The spec is unclear here, but ""A Shared-Region rule where pmpcfg.L is set"" must refer to ""LRWX=101X"", because ""The encoding pmpcfg.LRWX=1111"" is a separate point. (This holds for the subsequent items below too.)","Be in M-mode and U-mode, write to such a region, ensure that the writes do not reach the bus and that an exception occurs.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,BothExecute,"""Both M-mode and S/U-mode have execute access on the [Shared-Region rule where pmpcfg.L is set]""","Be in M-mode and U-mode, attempt to execute from such a region, ensure that the code is executed and that the attempt does not cause an exception.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,MmodeRead,"""M-mode also has read access [to Shared-Region rule where pmpcfg.L is set] if pmpcfg.X is set.""","Be in M-mode, attempt to read from such a region, ensure that the success depends accordingly on X.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: ???","(Same as for ""MmodeDeny"")" +,,IgnoreUntilReset,"""The [Shared-Region rule where pmpcfg.L is set] remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.""",(Covered by RemainLocked above.),Other,Other,N/A,,N/A, +,,BothReadonly,"""The encoding pmpcfg.LRWX=1111 can be used for sharing data between M-mode and S/U mode, where both modes only have read-only access to the region.""","Be in M-mode and U-mode, access such a region, ensure that only the reads work and that the rest (write/execute) excepts.",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal +uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal + +COV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cover_item_covergroup_cg_internals_instr_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx + +COV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx + +COV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_umode_mml_lrwx + +COV: ???","TODO technically missing the ""the rest … excepts"" cover" +,,ReadonlyLocked,"""The [pmpcfg.LRWX=1111] rule remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.""",(Covered by RemainLocked above.),Other,Other,N/A,,N/A, +,LegalRwx,,"Depending on the mseccfg control bits and L, some RWX combinations are reserved. + +Note: Use the table from the spec.",Ensure that illegal/reserved mseccfg/L/RWX combinations are unreachable.,Assertion Check,"ENV capability, not specific test",Assertion Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected", +,Reachable,,"All legal states in the table are reachable. It could theoretically be that platform-specific constraints made certain states unreachable (particularily related to locking), but we should be able to reach all legal and supported combinations of settings.",Ensure that all legal states are reachable.,Other,Constrained-Random,Functional Coverage,,COV: ???,TODO missing cover +manual,Parameters,MinimumGranularity,"""The PMP_GRANULARITY parameter is used to configure the minimum granularity of PMP address matching. The minimum granularity is [2^(PMP_GRANULARITY+2)] bytes, so at least 4 bytes.""","Have runs with max granularity, minimum granularity, and something in between. Make sure all checkers/covers are active for each relevant run configuration, so tor/napot/na4 is tested with different granularities. Cover cases where a match would otherwise occur but the granularity made the access not match. + +Note: Ensure TorMatching etc above heed this parameter.",Other,Constrained-Random,Functional Coverage,,COV: ???,TODO missing cover +,,NumRegions,"""The PMP_NUM_REGIONS parameter is used to configure the number of PMP regions, starting from the lowest numbered region."" + +Note: Including 0 regions.","Have runs with max number, minimum number, and something in between.",Other,Constrained-Random,Functional Coverage,,COV: ???,TODO missing cover +,,ResetValues,"""The reset value of the PMP CSR registers can be set through the top level parameters PMP_PMPNCFG_RV[], PMP_PMPADDR_RV[] and PMP_MSECCFG_RV.""","Have runs with different reset values. Ensure that after reset then the reset values are effectuated. + +Note: Try also, reset values with locked configs.",Assertion Check,"ENV capability, not specific test",Functional Coverage,High Priority,"A: ??? + +COV: ???","TODO missing assert + +TODO missing cover" +,,DefaultValues,The reset value defaults should amount to a safe config. (Including no violation of reserved bits.),(Covered by all the checks that handles the various legalities.),Other,Other,N/A,,N/A, +,CSRs,AlwaysAccessible,"""All PMP CSRs are always implemented"". ""MRW"". The CSRs are M-mode accessible, and their existence does not depend on PMP_NUM_REGIONS. + +Note: ""All"" pmp registers, and all fields within them.","Be in M-mode, access (reads/writes) all the pmp csrs, ensure that it always works without excepting (because the csrs exist and the mode is appropriate). + +Note: Potential overlap with CSR vplan.",Assertion Check,Directed Non-Self-Checking,Assertion Coverage,High Priority,A: ???,TODO missing assert +,,ReservedLegal,"Reserved bits/fields have legal values, matching the platform-specified defaults.","(Overlaps with LegalRwx and RwReservedabove.) Read all fields of all pmp-related csrs, ensure there are no unsupported values anywhere (at all times).",Assertion Check,Constrained-Random,Assertion Coverage,,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected, +,,MseccfghZero,"""Hardwired to 0""","Read mseccfgh, ensure it is always 0.",Assertion Check,Constrained-Random,Assertion Coverage,High Priority,A: ???,TODO missing assert +,,UnusedZero,"""CSRs (or bitfields of CSRs) related to PMP entries with number PMP_NUM_REGIONS and above are hardwired to zero."" + +Note: Including upper parts of pmpcfgn and also pmpaddr.","Read pmpcfg and pmpaddr csrs, ensure the values are zero as specified. Cover that the other values can be non-zero.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: ??? + +COV: ???","TODO missing assert + +TODO missing cover" +,,Hardening,"Certain CSRs related to the PMP shall be ""hardened"" as per Xsecure.","(CSR hardening is the responsibility of the security features vplan, even the pmp-specific part of it.)",N/A,N/A,N/A,,N/A, +,MicroArchitecture,WaitUpdate,"Updates to pmp configs should NOT have an effect on earlier instructions (nor on the instruction itself). + +Note: Potential security hole.","The pmp grant/deny checking must be compared vs ""rvfi_csr__rdata"". +(This will detect whether the actual pmp decision differs from what the rvfi csr data would incidate.) + +Note: Compare ""pc_rdata"" for execute, and ""mem_"" signals for read/write. (Might need additional decoding of ""rvfi_insn"".)",Assertion Check,"ENV capability, not specific test",Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_musttrap + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_musttrap + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap + +COV: ???",TODO missing cover +,,,,"Inject pmp csr write instructions in random testing, intermingled with all other kinds of instructions. This should include random interrupts, bus faults, random bus stalls, etc.",Check against RM,Constrained-Random,Functional Coverage,,COV: ???,TODO missing cover +,,AffectSuccessors,"Updates to pmp configs MUST have an effect on later instructions. + +Note: Potential security hole. + +Note: There was a known rtl bug here before (cv32e40s/issues/168).","The ""rvfi_csr__wdata"" (masked) for pmp csrs on one instruction, must match the ""_rdata"" value of the next instruction. +(Combined with checking grant/deny on ""_rdata"", this should ensure that the subsequent instruction has been affected by any pmp csr update.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,High Priority,"(Shares asserts with ""WaitUpdate"" above.) + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_cfg_writes + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_addr_writes", +,,,,(Same random testing as WaitUpdate above.),Other,Other,N/A,,N/A, +,,ImplementationDetails,"Details about pipeline/prefetcher/bus flushing etc are not part of this vplan. Only black-box observable functional behavior is checked. (Such requirements exists in specs, but are deliberately not addressed here.)",N/A,N/A,N/A,N/A,,N/A, +,,Performance,Requirements about performance and stalls etc are not covered here (unless review calls for the opposite).,N/A,N/A,N/A,N/A,,N/A, +,,WriteBuffer,Changes to the pmp config should not impact the write buffer such that a transaction can get its grant/deny status altered.,"Cover cases of the write buffer being full while the pmp cfg changes. Checking of accidental grants is handled by SuppressReq below. Checking of guaranteed writes is not part of this vplan. + +Note: The Write buffer is situated between the pmp and the bus.",Other,Other,Functional Coverage,High Priority,COV: ???,TODO missing cover +,Violations,SuppressReq,"When an access is denied by the pmp, the effect is that the attempted obi transaction is suppressed and does not reach the bus. + +Note: Both ""instr_req_o"" and ""data_req_o"".","Observe a transaction request coming in to the pmp module, observe the pmp denying the access, ensure that the obi bus is shielded from the transaction request.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_supress_req_data.a_suppress_req_data + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_supress_req_instr.a_suppress_req_instr", +,,InternalBuses,(The transaction request feeding into the mpu and its response signaling is not covered by this vplan.),N/A,N/A,N/A,N/A,,N/A, +,,ExceptionExecute,"""mcause [...] Instruction access fault [...] Execution attempt with address failing PMP check.""","Attempt execution of a region that pmp denies execution of, ensure that an ""instruction access fault"" exception occurs (read mcause and rvfi signals). + +Note: Since ISS can check most of this, one could deprioritize this checking if it is not feasible to check within reasonable efforts. (Same for the next 2 items.)",Assertion Check,Constrained-Random,Assertion Coverage,,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause, +,,ExceptionLoad,"""mcause [...] Load access fault [...] Load attempt with address failing PMP check."" + +Note: Holds for load-reserved too.","Attempt loads (and load-reserveds) of a region that pmp denies reading from, ensure that a ""load access fault"" exception occurs (read mcause and rvfi signals).",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load + +COV: ???",TODO missing cover +,,ExceptionStore,"""mcause [...] Store/AMO access fault [...] Store attempt with address failing PMP check."" + +Note: Holds for store-conditional and amo too.","Attempt stores (and store-conditionals and amo) to a region that pmp denies writing to, ensure that a ""store/amo access fault"" exception occurs (read mcause and rvfi signals).",Assertion Check,Constrained-Random,Functional Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store + +COV: ???",TODO missing cover +,,TrapPrecisely,"""All exceptions are precise"". +Meaning mepc will point to the offending instruction, and exactly previous instructions have their side effects fully visible. + +Note: Applies to loads, stores, and executes.","Observe that the pmp causes an exception, ensure that mepc points to the offending instruction. + +Note: Let the Exceptions vplan deal with visibility of side effects for earlier instructions. (Zc push/pop does not follow this, but that is mostly the responsibility of the Zc vplan.) + +Note: If satisfactory mepc checking already exist then it is acceptable to just add covers for the pmp scenarios.",Assertion Check,Constrained-Random,Functional Coverage,,"A: ??? + +COV: ???","TODO missing assert + +TODO missing cover" +,,AlertMinor,"""The following issues result in a minor security alert: [...] Instruction access fault [...] Load access fault [...] Store/AMO access fault""",(Responsibility of the xsecure vplan. But link to coverage here too.),N/A,N/A,N/A,,"A: ??? + +COV: ???",Waiting for xsecure vplan +,,AlertNothing,"The manual lists which pmp-related events can cause an alert minor, but the pmp should in no other cases be the cause for an alert (major/minor). + +Note: Example, ""attempt to reprogram a locked PMP""","Observe an alert signal going high while there is no pmp error that should have caused it, ensure that another viable reason for the alert was present. + +Note: This is slightly out of scope for this vplan, so if it is not very easy to hook on to existing xsecure (helper-)signals then this can be skipped.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,SplitLoadRegfile,"Even if parts of a split load can reach the bus, the instruction itself has failed and so the regfile should not get updated.","(Handled by ""SplitLoadException"" below, because: One only needs to show that an exception is caused, and the exceptions vplan is responsible for checking what that means for the regfile. (But link to coverage here too.))",N/A,N/A,N/A,,A: ???,Waiting for exceptions vplan +,,SplitLoadException,"For split loads, regardless of which of the access that fails, the instruction should still cause an exception.","Perform a misaligned load that translates to multiple accesses, let any of the accesses be denied by pmp, ensure an exception occurs. + +Coverage: See rvfi retire with exception cause from pmp, while the ""low addr"" model checking gave access granted.",Assertion Check,Constrained-Random,Functional Coverage,,"A: ??? + +COV: ???","TODO missing assert + +TODO missing cover" +,,FirstFail,"If a split load/store fails on its first transaction it should get an exception immediately, so it should not allow the second transaction reach the bus and mcause shall reflect the failing transactions.","Attempt such an instruction, ensure that the denied access does not reach the bus, ensure that following accesses also do not reach the bus.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,PushPop,"If a push/pop fails on a transaction it should get an exception immediately, so the remaining transactions should not reach the bus and mcause shall reflect the failing transaction.","(Responsibility of the zc vplan. But link to coverage here too.) + +Note: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.",N/A,N/A,N/A,,"A: ??? + +COV: ???",Waiting for zc vplan +,,TableJump,PMP applies to table jumps and Zc instructions in general.,"(Responsibility of the zc vplan. But link to coverage here too.) + +Note: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.",N/A,N/A,N/A,,"A: ??? + +COV: ???",Waiting for zc vplan +,,ClicVector,"Similarly to TableJump above, CLIC vector fetch needs execute permission.",(Analogous to TableJump above.),N/A,N/A,N/A,,"A: ??? + +COV: ???",Waiting for clic vplan +,,Priority,"Exceptions priority apply to the PMP as well. Particularily, PMP exception (instruction access fault) gets priority over bus errors (instruction bus fault) if an instruction is the result of two fetches were both of these occurred. + +Note: Both could be present in an attempted executed instruction at the same time, because no exception occurs before the point of execution so there is enough time for both to be captured and travel through the pipeline.","Keep track of words fetched with bus error and with pmp execute denied, check retired instructions for a pc that overlaps two such fetches (cover both orders), ensure that ""instruction access fault"" is the taken exception.",Assertion Check,Constrained-Random,Functional Coverage,,"A: ??? + +COV: ???","TODO missing assert + +TODO missing cover" +,Pma,RevokeExecutable,"Even if the pma should allow for execution, the pmp can overrule it and deny access.","Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for execution, let the pmp deny it, attempt execution, ensure that execution is indeed denied.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,RemainNonexecutable,"If the pma disallows execution, the pmp cannot change this fact and execution remains disallowed.","Set up pma and pmp regions such that both have rules covering the same addresses, let the pma disallow execution, let the pmp allow and deny execution (separate runs), attempt execution, ensure that execution is denied.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,RevokePermissible,"Even if the pma allows for data access, the pmp can overrule it and deny access.","Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for read and write (separate or same runs), let pmp deny read/write, attempt read/write, ensure that the pmp can overrule the pma.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +,,RemainNonpermissible,"If the pma disallows data access, the pmp cannot change this fact and data access remains disallowed.","Set up pma and pmp regions such that both have rules covering the same addresses, let the pma deny read and write, let pmp allow or deny it, attempt read/write, ensure that the access is always denied.",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +misc,Misc,DisallowDebug,The PMP can deny usage of debug mode by setting up regions for dm_halt_addr and dm_exception_addr.,"Set up pmp rules so all D-mode entries are blocked from execution, attempt to enter debug mode, ensure that nohing is executed in debug mode.",Assertion Check,Directed Non-Self-Checking,Assertion Coverage,,A: ???,Waiting for ongoing spec changes to be resolved +,,40x,The 40x does not have PMP.,N/A,N/A,N/A,N/A,,N/A, +,,Xif,"The X-interface can do memory operations, but the 40x does not have PMP and the 40s does not have XIF.",N/A,N/A,N/A,N/A,,N/A, +,,RvfiReliable,"Rvfi is used for checking some pmp functionality, so the link between rvfi and pmp must be checked.","If feasible to model within reasonable effort, check that 1) the PMPs' privmode inputs and 2) CSRs and 3) wdata/wmask is for csr write instrs, are properly correlated between access attempts and rvfi reportings. +Otherwise, leave this to general ISS checking.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_* + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_* + +(Indirectly checked by those asserts)", +,,RvfiTrap,"The ""rvfi_trap"" table has PMP-specific fields.","Augment the exception checkers above with checking of ""rvfi_trap.cause_type"" to ensure that specifically PMP is reported as the cause.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,,A: ???,TODO missing assert +,,UntilReset,"Everything that can get locked ""until reset"" must be possible to change after a reset. It should not be possible that these settings lock up so even resets cannot unlock them. + +Note: Formal's reset analysis should in principle be able to find every state that is possible to be in after a reset.","(Covered by ResetValues above. As long as those always take effect out of reset, then a permanent lock up should be either impossible or intentional.)",N/A,N/A,N/A,,N/A, +,,Xsecure,(Will be covered by its own vplan.),N/A,N/A,N/A,N/A,,N/A, +,,Reset,The PMP module is never reset without the whole core being reset. (As this could lift all the locks and stickies and grant privilege escalation.),Check that the core's reset is always equal to the pmp module's reset.,Assertion Check,"ENV capability, not specific test",Assertion Coverage,,A: ???,TODO missing assert +,,UmodeZeroRegions,"If the parameters are set to have 0 pmp regions, then all rules are OFF and U-mode matches nothing and defaults to not have any access.","Be in U-mode, have PMP_NUM_REGIONS=0, ensure all accesses fail (read/write/execute).",Assertion Check,Constrained-Random,Assertion Coverage,,A: ???,TODO missing assert +debug,Mmode,,"""All operations are executed with machine mode privilege"". +It is mostly the responsibility of other vplans to check D-mode relationship to M-mode and U-mode, but the pmp inputs should be checked against debug mode. + +Note: Refer to user-mode vplan and debug vplan if necessary. + +Note: It is assumed that once 1) dmode is shown to be interpreted as mmode by pmp, and 2) all mmode features are verified, then C) the mmode features will work in dmode. But one alternative is to duplicate all the mmode-related checking with dmode variants.","Ensure that the PMP inputs receive the correct mode while in D-mode. + +Note: Test w/wo MPRV too.",Assertion Check,Constrained-Random,Functional Coverage,High Priority,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_* + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_* + +(Indirectly checked by those asserts, together with effective priv mode and umode asserts for dmode/mmode.) + +COV: ???",TODO missing cover +,,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, +,,,,,,,,,, + -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------,,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json new file mode 100644 index 0000000000..43080652d0 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json @@ -0,0 +1,1718 @@ +[ + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "SmepmpOverrule", + "Feature Description": "The \"smepmp\" spec features can overrule the \"privspec\" (e.g. for locking). Both specs are included here, so be mindful that checking of certain vplan items could be conditional.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "FunctionalCoverage", + "Feature Description": "Functional coverage is encouraged to be creative in capturing a broad set of possible state, and evaluate it towards the checkers, to catch aspects of pmp functionality that this vplan might have overlooked.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "ImplementationChanges", + "Feature Description": "If test implementation reveals new knowledge that contradicts or augments this vplan, then the vplan should be updated.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "TimeAllowance", + "Feature Description": "Some verification goals in this plan has a \"base level\" of checking plus some optional tweaks that might be tried. It is up to the testing implementation how to prioritize and potentially skip the extras, according to what time allows.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "privspec", + "Feature": "General", + "Sub Feature": "Configs", + "Feature Description": "The pmp must be tested in a wide range of configurations. That includes testing on both instruction-side and data-side, and it includes testing overlapping regions, non-overlaping, no regions, differing settings for overlapping regions, M-mode only, U-mode only, both M-mode and U-mode, etc, etc. Use functional coverage with plenty of crosses.", + "Verification Goal": "Run with different configs to test parameters in low/mid/high ranges and in combination with the other parameters, instantiate checking on both instruction-side and data-side, write coverage to see all relevant region overlap combinations and to see an exhaustive combination of block-level input combinations and functional-level states.", + "Pass/Fail Criteria": "Other", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "Smepmp", + "Feature Description": "Given 1) backwards-compatible reset values, and 2) no change in \"mseccfg\", then C) the PMP should be fully compatible with the privspec.", + "Verification Goal": "For all privspec-derived PMP assertions, check that they must hold as long as the two preconditions hold (i.e. must not be excusable/overridable by smepmp features).", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "UmodeAlways", + "Feature Description": "\"PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches in S and U mode, data accesses in S and U mode when the MPRV bit in the mstatus register is clear, and data accesses in any mode when the MPRV bit in mstatus is set and the MPP field in mstatus contains S or U.\"\n\nNote: None of those scenarios should let an access bypass the pmp.", + "Verification Goal": "Set up the system to match each point in the listing, ensure that the pmp's decision matches all modelled expectations.\n\nNote: Also cover when none of the listed preconditions are active and the pmp's decision can disagree with the modelled expectations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "DefaultNone", + "Feature Description": "\"PMP can grant permissions to S and U modes, which by default have none\"", + "Verification Goal": "Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then U-mode has no access permissions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "DefaultFull", + "Feature Description": "\"can revoke permissions from M-mode, which\nby default has full permissions\"", + "Verification Goal": "Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then M-mode has full access permissions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "ResetRegisters", + "Feature Description": "\"Writable PMP registers\u2019 A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers\u2019 A and L fields.\"", + "Verification Goal": "Read the A and L values right after reset, ensure that the default reset values are 0.\n\nNote: Should also be visible on rvfi without specifically using csr instructions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "Warl", + "Feature Description": "\"All PMP CSR fields are WARL and may be hardwired to zero\".\n\nNote: A field shall also not change its value when an attempt is made to write an illegal value to it. (XWR is one field.)", + "Verification Goal": "Try writing any values to the registers and read values out of them, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected and that illegally written fields don't change.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "MmodeOnly", + "Feature Description": "\"PMP CSRs are only accessible to M-mode.\"", + "Verification Goal": "Try to access any of the pmp CSRs from U-mode, ensure that it always gives \"illegal instruction exception\" and that the CSRs are not updated.\n\nNote: M-mode accesses are covered by AlwaysAccessible below.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_csrs_mmode_only\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover (combine with \"Warl\" above)" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "Addr34bit", + "Feature Description": "\"Each PMP address register encodes bits 33\u20132 of a 34-bit physical address for RV32\"", + "Verification Goal": "Ensure that when the pmpaddr MSBs are set, then no NAPOT accesses matches. Cover that all bits have been matched against (\"toggle cross\"). Ensure that there are no attempted accesses to MSBs that the core should not be able to use.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "AddrImplemented", + "Feature Description": "\"Not all physical address bits may be implemented, and so the pmpaddr registers are WARL.\"", + "Verification Goal": "Cover (toggle) that all bits can be both written and set. (UnusedZero below covers the WARL(0x0) case.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "MatchDisabled", + "Feature Description": "\"When A=0, this PMP entry is disabled and matches no addresses\"\nWhen a cfg is set to off but its address(es) (interpreted as napot/tor) is the only rule that matches an attempted access, then it still does not count as a match.", + "Verification Goal": "Have a region's address(es) set up as tor and napot (separate runs), have all other regions not include the target address, have the target region's rule be OFF, make an access within that range, ensure that the outcome is the same as for when an access is outside of all address ranges.\n\nNote: For this and several other items, functional coverage is necessary because the checking doesn't necessarily have the above scenario in its antecedent.\n\nCoverage: Capture the above scenario, minus the checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotMatching", + "Feature Description": "\"NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range [\"yyyy...yy01\" etc]\"\n\nNote: The napot address matching modes match on addresses that are equal to the requested access when masked to the granularity size.", + "Verification Goal": "Configure napot rules of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated sizes.\n\nNote: Includes NAPOT and NA4.\n\nNote: Try also max and min.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4is4byte.a_na4_is_4byte\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_bin_auto[*]\ndut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_disallowed_bin_auto[*]\n\nCOV: ???", + "Comment": "TODO missing coverage" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorMatching", + "Feature Description": "\"If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range. If PMP entry i\u2019s A field is set to TOR, the entry matches any address y such that pmpaddri\u22121 \u2264 y < pmpaddri (irrespective of the value of pmpcfgi\u22121)\"", + "Verification Goal": "Configure tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_ismatch_tor_bin_auto[*]\n\nCOV: ???", + "Comment": "TODO missing coverage" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorZero", + "Feature Description": "\"If PMP entry 0\u2019s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr0.\"", + "Verification Goal": "Configure entry 0 as tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorNomatch", + "Feature Description": "\"If pmpaddri\u22121 \u2265 pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses.\"", + "Verification Goal": "Set up tor regions where the addresses are not in increasing order, try accesses on or within the designated \"reverse\" regions, ensure that they are treated as if there is no match.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "SameGrain", + "Feature Description": "\"In general, the PMP grain [...] must be the same across all PMP regions.\"", + "Verification Goal": "Do the same as for the basic case of GranularityDetermination below, ensure that all read values are the same across all the pmp csrs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "Na4Unselectable", + "Feature Description": "\"When G \u2265 1, the NA4 mode is not selectable.\"", + "Verification Goal": "Have the G parameter set to at least 1, ensure that NA4 never gets selected (even when writing to non-locked cfg).\n\nNote: Formal should easily check this.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_only_g0\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_only_g0\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_not_when_g uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_not_when_g", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotImplied", + "Feature Description": "\"When G \u2265 2 and pmpcfgi.A[1] is set, i.e. the mode is NAPOT\".", + "Verification Goal": "(Covered by Na4Unselectable above)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotOnes", + "Feature Description": "\"When G \u2265 2 and pmpcfgi.A[1] is set, [...] then bits pmpaddri[G-2:0] read as all ones.\"", + "Verification Goal": "Have the G parameter set to at least 2, have A set, read pmpaddri, ensure the LSBs are all ones as specified.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_napot_ones_g2.gen_napot_ones_i[*].a_napot_ones", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "AllZeros", + "Feature Description": "\"When G \u2265 1 and pmpcfgi.A[1] is clear, i.e. the mode is OFF or TOR, then bits pmpaddri[G-1:0] read as all zeros.\"", + "Verification Goal": "Create the listed preconditions, ensure that the read value contains zeroes as specified.\n\nNote: Check both OFF/TOR, and for all configs fields (checking of all configs don't need 100% coverage in simulation).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_all_zeros_g1.gen_all_zeros_i[*].a_all_zeros\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorUnaffected", + "Feature Description": "\"Bits pmpaddri[G-1:0] do not affect the TOR address-matching logic.\"", + "Verification Goal": "Write different values to \"pmpaddri[G-1:0]\", ensure TOR mode matches the same either way.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "StorageUnaffected", + "Feature Description": "\"Although changing pmpcfgi.A[1] affects the value read from pmpaddri, it does not affect the underlying value stored in that register\"\n\"in particular, pmpaddri[G-1] retains its original value when pmpcfgi.A is changed from NAPOT to TOR/OFF then back to NAPOT.\"", + "Verification Goal": "Change in and out of (OFF || TOR) and !(OFF || TOR), ensure that different values can be read without having written anything new to the register.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_storage_unaffected[*].a_storage_unaffected\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "GranularityDetermination", + "Feature Description": "\"Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading back pmpaddr0. If G is the index of the least-significant bit set, the PMP granularity is 2 G+2 bytes.\"", + "Verification Goal": "Write zero to pmpicfg, write ones to pmpaddri, read pmpaddri, ensure that the LSB index matches to granularity parameter.\n\nNote: Formal can maybe check this for all i.\n\nNote: If time allows, can write something else than zero and ensure that the rest follows as expected.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_granularity_determination", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "XlenMatching", + "Feature Description": "\"If the current XLEN is greater than MXLEN, the PMP address registers are zero-extended from MXLEN to XLEN bits for the purposes of address matching.\"", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "UntilReset", + "Feature Description": "\"Locked PMP entries remain locked until the hart is reset.\"", + "Verification Goal": "Lock entry i (for all i, if feasible), ensure that the lock bit is never lifted before reset. (Unless if RLB interferes.)\n\nNote: Sim might do a second reset, formal most likely won't and shouldn't need to.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_until_reset[*].a_until_reset", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "IgnoreWrites", + "Feature Description": "\"If PMP entry i is locked, writes to pmpicfg and pmpaddri are ignored.\"", + "Verification Goal": "Lock entry i (for all i, if feasible), ensure that their value can't change, both when written to and otherwise. (Unless if RLB interferes.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_notrap[*].a_ignore_writes_notrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_nochange[*].a_ignore_writes_nochange\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "IgnoreTor", + "Feature Description": "\"Additionally, if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored.\"", + "Verification Goal": "Lock entry i (\u2026), have A set and the mode be TOR, ensure that pmpaddri-1 can't change, both for explicit writes and otherwise. (Unless RLB.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_stable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_wdata\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "NotIgnore", + "Feature Description": "When neither cfg i is locked, nor is cfg i+1 a locked TOR region, then writes to cfg and addr i are not ignored.", + "Verification Goal": "Have cfg i unlocked, write to cfg and addr csr i, check that it changes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_writes[*].a_addr_nonlocked\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_tor[*].a_addr_nonlocked_tor", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "LockOff", + "Feature Description": "\"Setting the L bit locks the PMP entry even when the A field is set to OFF.\"", + "Verification Goal": "Lock entry i while the mode is OFF, ensure that it gets locked in this case too.\n\nNote: Ensure that checking and coverage handles locking for all possible modes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: (Same checking as for \"IgnoreWrites\" and \"IgnoreTor\" above.)\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "RwxPrivmode", + "Feature Description": "\"In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are enforced on M-mode accesses. When the L bit is set, these permissions are enforced for all privilege modes.\"", + "Verification Goal": "Be in M-mode and U-mode (separate runs), access a region where L is set and where RWX {grant, deny R, deny W, deny X}, ensure that the access is correspondingly granted/denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "MmodeSucceed", + "Feature Description": "\"When the L bit is clear, any M-mode access matching the PMP entry will succeed\"", + "Verification Goal": "Be in M-mode, access a region where L is clear, ensure that access is granted in all cases.\n\n(Note, see \"Smepmp\" above.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "RwxUmode", + "Feature Description": "\"When the L bit is clear [\u2026] the R/W/X permissions apply only to S and U modes.\"", + "Verification Goal": "Be in U-mode, access a region where L is clear, ensure that access is granted/denied based on RWX.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_uorl_onlyif_rwx\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_uorl_onlyif_rwx\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "LowestDetermines", + "Feature Description": "\"PMP entries are statically prioritized. The lowest-numbered PMP entry that matches any byte of an access determines whether that access succeeds or fails.\"\n\nNote: \"any\" byte.", + "Verification Goal": "Access a region that is covered by multiple rules, ensure that the lowest indexed match determines the outcome.\n\nNote: Requires that the rules would disagree on the outcome.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MatchAll", + "Feature Description": "\"The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits.\"", + "Verification Goal": "(Only relevant for 64-bit architectures.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "LrwxDetermines", + "Feature Description": "\"If a PMP entry matches all bytes of an access, then the L, R, W,and X bits determine whether the access succeeds or fails. [...] if the L bit is set or the privilege mode of the access is S or U, then the access succeeds only if the R, W,or X bit corresponding to the access type is set.\"", + "Verification Goal": "Access a pmp region where L and the privmode etc is such that nothing else would deny the access, ensure that each of (or a combination of) RWX can either grant or deny the access.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_lrwx_aftermatch\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_lrwx_aftermatch\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MmodeSucceed2", + "Feature Description": "\"If the L bit is clear and the privilege mode of the access is M, the access succeeds.\"", + "Verification Goal": "(Same as \"MmodeSucceed\" above)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MmodeNomatch", + "Feature Description": "\"If no PMP entry matches an M-mode access, the access succeeds.\"", + "Verification Goal": "Be in M-mode, access a region where no rule matches, ensure that the access is granted (where MMWP is off).\n\n(Note, see \"Smepmp\" above.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "UmodeNomatch", + "Feature Description": "\"If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.\"\n\nNote: \"All PMP CSRs are always implemented\".", + "Verification Goal": "Be in U-mode, do an access that doesn't match any region, ensure that the access fails.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_umode_fails\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_umode_fails\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "UmodeOff", + "Feature Description": "\"If at least one PMP entry is implemented, but all PMP entries\u2019 A fields are set to OFF, then all S-mode and U-mode memory accesses will fail.\"", + "Verification Goal": "Be in U-mode, have all entries OFF, make an access, ensure that the access fails (for all variations of accesses).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "FailException", + "Feature Description": "\"Failed accesses generate an instruction, load, or store access-fault exception.\"", + "Verification Goal": "Cause failed accesses on instructions/loads/stores, ensure that an exception occurs and that it is the right one.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: ::uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MultiAccess", + "Feature Description": "\"Note that a single instruction may generate multiple accesses, which may not be mutually atomic. An access-fault exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects.\"\n\n\"On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an access-fault exception occurs. In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check.\"", + "Verification Goal": "Induce misaligned word instruction-fetch, load, and store, where the lower and upper (separate runs) parts are either accessible or blocked by pmp, ensure that exceptions occur while parts of the access might reach the bus.\n\nAlso check Zc's push/pop and table jump.\n\nNote: It is up to other vplans to check what happens upon the exception. It is up to this PMP vplan to check that the PMP will cause the exceptions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap\n\nA: ???\n\nCOV: ???", + "Comment": "TODO missing assert (on split that errs on first)\n\nTODO missing cover" + }, + { + "Requirement Location": "smepmp", + "Feature": "MsecCfg", + "Sub Feature": "MmodeOnly", + "Feature Description": "\"Machine Security Configuration (mseccfg) is [...] only accessible to Machine mode.\"\n\nNote: Includes \"mseccfgh\".", + "Verification Goal": "Access (read/write) mseccfg (and mseccfgh) from M-mode, access mseccfg from U-mode, ensure that the first always works (WARL) and the second never works (exception).\n\nNote: Cover with MPRV too.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "FieldsWarl", + "Feature Description": "\"All mseccfg fields defined on this proposal are WARL\"", + "Verification Goal": "Try writing any values to the fields (the defined ones, but also other bits) and read values out of the fields, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected.\n\nNote: This relates to the \"stickiness\" of those fields. Regardless of their values and current stickiness, the fields are WARL.\n\nNote: It might be difficult, when trying to write a checker for traps, to filter out all other causes for traps that can occur simultaneously. (Either reduce the scope of checking, or write re-usable helper signals for \"trap causality\" info.)\n\nNote: \"WPRI\" on some bits.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "ReservedZero", + "Feature Description": "\"the remaining bits are reserved for future standard use and should always read zero.\"\n(This spec can't dictate that about other specs, but the user manual agrees on the hardwiring.)", + "Verification Goal": "Read mseccfg, ensure the non-smepmp-field bits are always zero.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "ResetValue", + "Feature Description": "\"The reset value of mseccfg is implementation-specific, otherwise if backwards compatibility is a requirement it should reset to zero on hard reset.\"", + "Verification Goal": "Read the value of mseccfg right after reset, ensure that the default reset value is zero.\n\nNote: Should also be visible on rvfi without specifically using csr instructions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mseccfg_reset_val\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mseccfg_reset_val", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "ModifiableEntries", + "Feature Description": "\"When mseccfg.RLB is 1 locked PMP rules may be removed/modified and locked PMP entries may be edited.\"\n\nNote: Both \"cfg\" and \"addr\" registers, limited to fields within \"cfg\" reg, also TOR affects lower \"addr\" reg.", + "Verification Goal": "Have a locked pmp entry i, set RLB to 1, try modifying any(!) field within {pmpicfg, pmpaddri, pmpaddri-1(tor)}, ensure that values are updated succesfully (while respecting other rules like legal values and reserved bits).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_addr\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_exec\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_lock\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_mode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_read\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_write\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "RemainZero", + "Feature Description": "\"When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset\"\n\nNote: \"any\" entry.", + "Verification Goal": "Have RLB=0 and at least one L=1, ensure that RLB is 0 forever (until reset).\n\nNote: No exception occurs on attempted access, but one should try overwriting the value to stimulate the checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_rlb_never_fall_while_locked\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_rlb_never_fall_while_locked", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "UntilReset", + "Feature Description": "The sticky zero and update-ignores last until reset, and do not hold after reset.", + "Verification Goal": "Ensure that RLB is modifiable after reset. (Unless if reset values are set to activate the RemainZero condition.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_until_reset_notbefore\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "HardwireZero", + "Feature Description": "\"Vendors who don\u2019t need this functionality may hardwire this field to 0.\"", + "Verification Goal": "(40s has not hardwired this to 0, it is RW.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WhiteList", + "Sub Feature": "StickyUntilReset", + "Feature Description": "\"[mseccfg.MMWP] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.\"", + "Verification Goal": "Have MMWP set, ensure that it remains high forever (til reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mmwp_never_fall_until_reset\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mmwp_never_fall_until_reset", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WhiteList", + "Sub Feature": "Denied", + "Feature Description": "\"When set it changes the default PMP policy for M-mode when accessing memory regions that don\u2019t have a matching PMP rule, to denied instead of ignored.\"", + "Verification Goal": "Have MMWP set, be in (effective mode) M-mode, access regions that don't match any rule (including OFF, \"reversed\" TOR, >32bit NAPOT, etc), ensure that the access is denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_mmode_mmwp_fails\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_mmode_mmwp_fails\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "StickyUntilReset", + "Feature Description": "\"[mseccfg.MML] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.\"", + "Verification Goal": "Cover: Trying to clear the bit.\n\nCheck: Have MML set, ensure that it remains high forever (til reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mml_never_fall_until_reset\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mml_never_fall_until_reset\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "ExecIgnored", + "Feature Description": "\"[When mseccfg.MML is set.] Adding an M-mode-only or a locked Shared-Region rule with executable privileges is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged.\"\n\nNote: \"pmpcfg\" refers to a field, so the write to the CSR itself should still update other fields.", + "Verification Goal": "Have MML set, try adding an \"M-mode-only\" rule and a \"locked Shared-Region\" rule with X privileges, ensure that the relevant pmpcfg field is not updated but is left unchanged, ensure also that other fields can still get updated.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "ExecRlb", + "Feature Description": "\"[The above] restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB.\"", + "Verification Goal": "Have RLB and MML set, try adding an \"M-mode-only\" rule and a \"locked Shared-Region\" rule with X privileges, ensure that the relevant pmpcfg field is in fact updated.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rlblifts_lockedexec[*].a_rlblifts_lockedexec", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "MmodeExec", + "Feature Description": "\"Executing code with Machine mode privileges is only possible from memory regions with a matching M-mode-only rule or a locked Shared-Region rule with executable privileges. Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied.\"", + "Verification Goal": "Execute from \"M-mode-only\" and \"locked Shared-Region\" regions, attempt execution without matching and from \"U-mode-only\" regions, ensure corresponding grant or deny.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "RwReserved", + "Feature Description": "\"If mseccfg.MML is not set, the combination of pmpcfg.RW=01 remains reserved for future standard use.\"", + "Verification Goal": "Whitelist the conditions that allow RW=01 (including MML conditions), ensure that it is adhered to.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rwx_mml[*].a_rwx_mml\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rwfuture[*].a_rw_futureuse\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rwfuture[*].a_rw_futureuse", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeEnforce", + "Feature Description": "\"[When mseccfg.MML is set.] An M-mode-only rule is enforced on Machine mode\"", + "Verification Goal": "Be in M-mode, have MML set, access an \"M-mode-only\" region, ensure that the grant/deny is always in accordance to the rule. (E.g. it is not denied execute despite the execute bit being set.)\n\nNote: Exclude cases of interference from e.g. PMA.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeDeny", + "Feature Description": "\"[When mseccfg.MML is set.] An M-mode-only rule is [...] denied in Supervisor or User mode.\"", + "Verification Goal": "Be in U-mode, have MML set, access an \"M-mode-only\" region, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "RemainLocked", + "Feature Description": "\"It also remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset\"\n\nCertain rules under MML are sticky. They cannot be modified again.", + "Verification Goal": "Configure rules for {\"M-mode-only\", \"U-mode-only, \"Shared-Region rule where pmpcfg.L is set\"(both kinds)}, have MML=1 (and RLB=0), ensure that the configs never change again (until reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "RlbUnlocks", + "Feature Description": "\"It also remains locked [...] unless mseccfg.RLB is set.\"", + "Verification Goal": "Have the same setup as in RemainLocked, but let RLB=1, try changing the configs, ensure that they are indeed changed.\n\nNote: \"Assertion check\" includes cover properties.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeEnforce", + "Feature Description": "\"[When mseccfg.MML is set.] An S/U-mode-only rule is enforced on Supervisor and User modes \"", + "Verification Goal": "Be in U-mode, have MML=1, access a \"U-mode-only\" region, ensure that the grant/deny is in accordance with the rule (apart from PMA etc).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cg_data\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cg_instr\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeDeny", + "Feature Description": "\"An S/U-mode-only rule is [...] denied on Machine mode.\"", + "Verification Goal": "Be in M-mode, have MML=1, access a \"U-mode-only\" region, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing coverage. (Just do a cg with crosses of all of these variables.)" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedEnforced", + "Feature Description": "\"A Shared-Region rule is enforced on all modes\"", + "Verification Goal": "Be in M-mode and U-mode (separate runs), access a \"Shared-Region\", ensure that the grant/deny is in accordance with the rule.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedNoexec", + "Feature Description": "\"A Shared-Region rule where pmpcfg.L is not set can be used for sharing data between M-mode and S/U-mode, so is not executable.\"", + "Verification Goal": "Be in M-mode and U-mode, try to execute from \"A Shared-Region rule where pmpcfg.L is not set\", ensure that it does not work (exception).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeReadwrite", + "Feature Description": "\"[Shared-Region rule where pmpcfg.L is not set.] M-mode has read/write access to that region\"", + "Verification Goal": "Be in M-mode, perform reads and writes to such a region, ensure that the intended effects happen and that the accesses do not cause exceptions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeRead", + "Feature Description": "\"[For a Shared-Region rule where pmpcfg.L is not set] S/U-mode has read access if pmpcfg.X is not set, or read/write access if pmpcfg.X is set.\"", + "Verification Goal": "Be in U-mode, perform reads and writes to such a region, ensure that the reads always work and that the writes depend on X.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedNowrite", + "Feature Description": "\"A Shared-Region rule where pmpcfg.L is set can be used for sharing code between M-mode and S/U-mode, so is not writeable.\"\n\nNote: The spec is unclear here, but \"A Shared-Region rule where pmpcfg.L is set\" must refer to \"LRWX=101X\", because \"The encoding pmpcfg.LRWX=1111\" is a separate point. (This holds for the subsequent items below too.)", + "Verification Goal": "Be in M-mode and U-mode, write to such a region, ensure that the writes do not reach the bus and that an exception occurs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "BothExecute", + "Feature Description": "\"Both M-mode and S/U-mode have execute access on the [Shared-Region rule where pmpcfg.L is set]\"", + "Verification Goal": "Be in M-mode and U-mode, attempt to execute from such a region, ensure that the code is executed and that the attempt does not cause an exception.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeRead", + "Feature Description": "\"M-mode also has read access [to Shared-Region rule where pmpcfg.L is set] if pmpcfg.X is set.\"", + "Verification Goal": "Be in M-mode, attempt to read from such a region, ensure that the success depends accordingly on X.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "IgnoreUntilReset", + "Feature Description": "\"The [Shared-Region rule where pmpcfg.L is set] remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.\"", + "Verification Goal": "(Covered by RemainLocked above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "BothReadonly", + "Feature Description": "\"The encoding pmpcfg.LRWX=1111 can be used for sharing data between M-mode and S/U mode, where both modes only have read-only access to the region.\"", + "Verification Goal": "Be in M-mode and U-mode, access such a region, ensure that only the reads work and that the rest (write/execute) excepts.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cover_item_covergroup_cg_internals_instr_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_umode_mml_lrwx\n\nCOV: ???", + "Comment": "TODO technically missing the \"the rest \u2026 excepts\" cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "ReadonlyLocked", + "Feature Description": "\"The [pmpcfg.LRWX=1111] rule remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.\"", + "Verification Goal": "(Covered by RemainLocked above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LegalRwx", + "Sub Feature": "", + "Feature Description": "Depending on the mseccfg control bits and L, some RWX combinations are reserved.\n\nNote: Use the table from the spec.", + "Verification Goal": "Ensure that illegal/reserved mseccfg/L/RWX combinations are unreachable.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Reachable", + "Sub Feature": "", + "Feature Description": "All legal states in the table are reachable. It could theoretically be that platform-specific constraints made certain states unreachable (particularily related to locking), but we should be able to reach all legal and supported combinations of settings.", + "Verification Goal": "Ensure that all legal states are reachable.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "manual", + "Feature": "Parameters", + "Sub Feature": "MinimumGranularity", + "Feature Description": "\"The PMP_GRANULARITY parameter is used to configure the minimum granularity of PMP address matching. The minimum granularity is [2^(PMP_GRANULARITY+2)] bytes, so at least 4 bytes.\"", + "Verification Goal": "Have runs with max granularity, minimum granularity, and something in between. Make sure all checkers/covers are active for each relevant run configuration, so tor/napot/na4 is tested with different granularities. Cover cases where a match would otherwise occur but the granularity made the access not match.\n\nNote: Ensure TorMatching etc above heed this parameter.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "NumRegions", + "Feature Description": "\"The PMP_NUM_REGIONS parameter is used to configure the number of PMP regions, starting from the lowest numbered region.\"\n\nNote: Including 0 regions.", + "Verification Goal": "Have runs with max number, minimum number, and something in between.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "ResetValues", + "Feature Description": "\"The reset value of the PMP CSR registers can be set through the top level parameters PMP_PMPNCFG_RV[], PMP_PMPADDR_RV[] and PMP_MSECCFG_RV.\"", + "Verification Goal": "Have runs with different reset values. Ensure that after reset then the reset values are effectuated.\n\nNote: Try also, reset values with locked configs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "DefaultValues", + "Feature Description": "The reset value defaults should amount to a safe config. (Including no violation of reserved bits.)", + "Verification Goal": "(Covered by all the checks that handles the various legalities.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "AlwaysAccessible", + "Feature Description": "\"All PMP CSRs are always implemented\". \"MRW\". The CSRs are M-mode accessible, and their existence does not depend on PMP_NUM_REGIONS.\n\nNote: \"All\" pmp registers, and all fields within them.", + "Verification Goal": "Be in M-mode, access (reads/writes) all the pmp csrs, ensure that it always works without excepting (because the csrs exist and the mode is appropriate).\n\nNote: Potential overlap with CSR vplan.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "ReservedLegal", + "Feature Description": "Reserved bits/fields have legal values, matching the platform-specified defaults.", + "Verification Goal": "(Overlaps with LegalRwx and RwReservedabove.) Read all fields of all pmp-related csrs, ensure there are no unsupported values anywhere (at all times).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MseccfghZero", + "Feature Description": "\"Hardwired to 0\"", + "Verification Goal": "Read mseccfgh, ensure it is always 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "UnusedZero", + "Feature Description": "\"CSRs (or bitfields of CSRs) related to PMP entries with number PMP_NUM_REGIONS and above are hardwired to zero.\"\n\nNote: Including upper parts of pmpcfgn and also pmpaddr.", + "Verification Goal": "Read pmpcfg and pmpaddr csrs, ensure the values are zero as specified. Cover that the other values can be non-zero.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Hardening", + "Feature Description": "Certain CSRs related to the PMP shall be \"hardened\" as per Xsecure.", + "Verification Goal": "(CSR hardening is the responsibility of the security features vplan, even the pmp-specific part of it.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "WaitUpdate", + "Feature Description": "Updates to pmp configs should NOT have an effect on earlier instructions (nor on the instruction itself).\n\nNote: Potential security hole.", + "Verification Goal": "The pmp grant/deny checking must be compared vs \"rvfi_csr__rdata\".\n(This will detect whether the actual pmp decision differs from what the rvfi csr data would incidate.)\n\nNote: Compare \"pc_rdata\" for execute, and \"mem_\" signals for read/write. (Might need additional decoding of \"rvfi_insn\".)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_musttrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_musttrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Inject pmp csr write instructions in random testing, intermingled with all other kinds of instructions. This should include random interrupts, bus faults, random bus stalls, etc.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "AffectSuccessors", + "Feature Description": "Updates to pmp configs MUST have an effect on later instructions.\n\nNote: Potential security hole.\n\nNote: There was a known rtl bug here before (cv32e40s/issues/168).", + "Verification Goal": "The \"rvfi_csr__wdata\" (masked) for pmp csrs on one instruction, must match the \"_rdata\" value of the next instruction.\n(Combined with checking grant/deny on \"_rdata\", this should ensure that the subsequent instruction has been affected by any pmp csr update.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "(Shares asserts with \"WaitUpdate\" above.)\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_cfg_writes\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_addr_writes", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "(Same random testing as WaitUpdate above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "ImplementationDetails", + "Feature Description": "Details about pipeline/prefetcher/bus flushing etc are not part of this vplan. Only black-box observable functional behavior is checked. (Such requirements exists in specs, but are deliberately not addressed here.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "Performance", + "Feature Description": "Requirements about performance and stalls etc are not covered here (unless review calls for the opposite).", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "WriteBuffer", + "Feature Description": "Changes to the pmp config should not impact the write buffer such that a transaction can get its grant/deny status altered.", + "Verification Goal": "Cover cases of the write buffer being full while the pmp cfg changes. Checking of accidental grants is handled by SuppressReq below. Checking of guaranteed writes is not part of this vplan.\n\nNote: The Write buffer is situated between the pmp and the bus.", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SuppressReq", + "Feature Description": "When an access is denied by the pmp, the effect is that the attempted obi transaction is suppressed and does not reach the bus.\n\nNote: Both \"instr_req_o\" and \"data_req_o\".", + "Verification Goal": "Observe a transaction request coming in to the pmp module, observe the pmp denying the access, ensure that the obi bus is shielded from the transaction request.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_supress_req_data.a_suppress_req_data\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_supress_req_instr.a_suppress_req_instr", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "InternalBuses", + "Feature Description": "(The transaction request feeding into the mpu and its response signaling is not covered by this vplan.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionExecute", + "Feature Description": "\"mcause [...] Instruction access fault [...] Execution attempt with address failing PMP check.\"", + "Verification Goal": "Attempt execution of a region that pmp denies execution of, ensure that an \"instruction access fault\" exception occurs (read mcause and rvfi signals).\n\nNote: Since ISS can check most of this, one could deprioritize this checking if it is not feasible to check within reasonable efforts. (Same for the next 2 items.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionLoad", + "Feature Description": "\"mcause [...] Load access fault [...] Load attempt with address failing PMP check.\"\n\nNote: Holds for load-reserved too.", + "Verification Goal": "Attempt loads (and load-reserveds) of a region that pmp denies reading from, ensure that a \"load access fault\" exception occurs (read mcause and rvfi signals).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionStore", + "Feature Description": "\"mcause [...] Store/AMO access fault [...] Store attempt with address failing PMP check.\"\n\nNote: Holds for store-conditional and amo too.", + "Verification Goal": "Attempt stores (and store-conditionals and amo) to a region that pmp denies writing to, ensure that a \"store/amo access fault\" exception occurs (read mcause and rvfi signals).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "TrapPrecisely", + "Feature Description": "\"All exceptions are precise\".\nMeaning mepc will point to the offending instruction, and exactly previous instructions have their side effects fully visible.\n\nNote: Applies to loads, stores, and executes.", + "Verification Goal": "Observe that the pmp causes an exception, ensure that mepc points to the offending instruction.\n\nNote: Let the Exceptions vplan deal with visibility of side effects for earlier instructions. (Zc push/pop does not follow this, but that is mostly the responsibility of the Zc vplan.)\n\nNote: If satisfactory mepc checking already exist then it is acceptable to just add covers for the pmp scenarios.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "AlertMinor", + "Feature Description": "\"The following issues result in a minor security alert: [...] Instruction access fault [...] Load access fault [...] Store/AMO access fault\"", + "Verification Goal": "(Responsibility of the xsecure vplan. But link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for xsecure vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "AlertNothing", + "Feature Description": "The manual lists which pmp-related events can cause an alert minor, but the pmp should in no other cases be the cause for an alert (major/minor).\n\nNote: Example, \"attempt to reprogram a locked PMP\"", + "Verification Goal": "Observe an alert signal going high while there is no pmp error that should have caused it, ensure that another viable reason for the alert was present.\n\nNote: This is slightly out of scope for this vplan, so if it is not very easy to hook on to existing xsecure (helper-)signals then this can be skipped.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SplitLoadRegfile", + "Feature Description": "Even if parts of a split load can reach the bus, the instruction itself has failed and so the regfile should not get updated.", + "Verification Goal": "(Handled by \"SplitLoadException\" below, because: One only needs to show that an exception is caused, and the exceptions vplan is responsible for checking what that means for the regfile. (But link to coverage here too.))", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "Waiting for exceptions vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SplitLoadException", + "Feature Description": "For split loads, regardless of which of the access that fails, the instruction should still cause an exception.", + "Verification Goal": "Perform a misaligned load that translates to multiple accesses, let any of the accesses be denied by pmp, ensure an exception occurs.\n\nCoverage: See rvfi retire with exception cause from pmp, while the \"low addr\" model checking gave access granted.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "FirstFail", + "Feature Description": "If a split load/store fails on its first transaction it should get an exception immediately, so it should not allow the second transaction reach the bus and mcause shall reflect the failing transactions.", + "Verification Goal": "Attempt such an instruction, ensure that the denied access does not reach the bus, ensure that following accesses also do not reach the bus.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "PushPop", + "Feature Description": "If a push/pop fails on a transaction it should get an exception immediately, so the remaining transactions should not reach the bus and mcause shall reflect the failing transaction.", + "Verification Goal": "(Responsibility of the zc vplan. But link to coverage here too.)\n\nNote: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for zc vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "TableJump", + "Feature Description": "PMP applies to table jumps and Zc instructions in general.", + "Verification Goal": "(Responsibility of the zc vplan. But link to coverage here too.)\n\nNote: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for zc vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ClicVector", + "Feature Description": "Similarly to TableJump above, CLIC vector fetch needs execute permission.", + "Verification Goal": "(Analogous to TableJump above.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for clic vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "Priority", + "Feature Description": "Exceptions priority apply to the PMP as well. Particularily, PMP exception (instruction access fault) gets priority over bus errors (instruction bus fault) if an instruction is the result of two fetches were both of these occurred.\n\nNote: Both could be present in an attempted executed instruction at the same time, because no exception occurs before the point of execution so there is enough time for both to be captured and travel through the pipeline.", + "Verification Goal": "Keep track of words fetched with bus error and with pmp execute denied, check retired instructions for a pc that overlaps two such fetches (cover both orders), ensure that \"instruction access fault\" is the taken exception.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RevokeExecutable", + "Feature Description": "Even if the pma should allow for execution, the pmp can overrule it and deny access.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for execution, let the pmp deny it, attempt execution, ensure that execution is indeed denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RemainNonexecutable", + "Feature Description": "If the pma disallows execution, the pmp cannot change this fact and execution remains disallowed.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma disallow execution, let the pmp allow and deny execution (separate runs), attempt execution, ensure that execution is denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RevokePermissible", + "Feature Description": "Even if the pma allows for data access, the pmp can overrule it and deny access.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for read and write (separate or same runs), let pmp deny read/write, attempt read/write, ensure that the pmp can overrule the pma.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RemainNonpermissible", + "Feature Description": "If the pma disallows data access, the pmp cannot change this fact and data access remains disallowed.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma deny read and write, let pmp allow or deny it, attempt read/write, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "misc", + "Feature": "Misc", + "Sub Feature": "DisallowDebug", + "Feature Description": "The PMP can deny usage of debug mode by setting up regions for dm_halt_addr and dm_exception_addr.", + "Verification Goal": "Set up pmp rules so all D-mode entries are blocked from execution, attempt to enter debug mode, ensure that nohing is executed in debug mode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "Waiting for ongoing spec changes to be resolved" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "40x", + "Feature Description": "The 40x does not have PMP.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Xif", + "Feature Description": "The X-interface can do memory operations, but the 40x does not have PMP and the 40s does not have XIF.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "RvfiReliable", + "Feature Description": "Rvfi is used for checking some pmp functionality, so the link between rvfi and pmp must be checked.", + "Verification Goal": "If feasible to model within reasonable effort, check that 1) the PMPs' privmode inputs and 2) CSRs and 3) wdata/wmask is for csr write instrs, are properly correlated between access attempts and rvfi reportings.\nOtherwise, leave this to general ISS checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\n(Indirectly checked by those asserts)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "RvfiTrap", + "Feature Description": "The \"rvfi_trap\" table has PMP-specific fields.", + "Verification Goal": "Augment the exception checkers above with checking of \"rvfi_trap.cause_type\" to ensure that specifically PMP is reported as the cause.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "UntilReset", + "Feature Description": "Everything that can get locked \"until reset\" must be possible to change after a reset. It should not be possible that these settings lock up so even resets cannot unlock them.\n\nNote: Formal's reset analysis should in principle be able to find every state that is possible to be in after a reset.", + "Verification Goal": "(Covered by ResetValues above. As long as those always take effect out of reset, then a permanent lock up should be either impossible or intentional.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Xsecure", + "Feature Description": "(Will be covered by its own vplan.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Reset", + "Feature Description": "The PMP module is never reset without the whole core being reset. (As this could lift all the locks and stickies and grant privilege escalation.)", + "Verification Goal": "Check that the core's reset is always equal to the pmp module's reset.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "UmodeZeroRegions", + "Feature Description": "If the parameters are set to have 0 pmp regions, then all rules are OFF and U-mode matches nothing and defaults to not have any access.", + "Verification Goal": "Be in U-mode, have PMP_NUM_REGIONS=0, ensure all accesses fail (read/write/execute).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "debug", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "\"All operations are executed with machine mode privilege\".\nIt is mostly the responsibility of other vplans to check D-mode relationship to M-mode and U-mode, but the pmp inputs should be checked against debug mode.\n\nNote: Refer to user-mode vplan and debug vplan if necessary.\n\nNote: It is assumed that once 1) dmode is shown to be interpreted as mmode by pmp, and 2) all mmode features are verified, then C) the mmode features will work in dmode. But one alternative is to duplicate all the mmode-related checking with dmode variants.", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\n(Indirectly checked by those asserts, together with effective priv mode and umode asserts for dmode/mmode.)\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.xlsx b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.xlsx new file mode 100755 index 0000000000..a24e24418a Binary files /dev/null and b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.csv b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.csv new file mode 100644 index 0000000000..05ab44153d --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.csv @@ -0,0 +1,379 @@ +Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,Comment +privspec,Misc,SupportedLevels,"""At any time, a RISC-V hardware thread (hart) is running at some privilege level encoded as a mode +in one or more CSRs [User, Supervisor, (Reserved), Machine]""","Run all supported levels (U-mode, M-mode); ensure no unsupported levels can be run (S-mode, reserved). + +Coverage: Attempts to set various modes.",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_no_unsupported_modes + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_umode + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mmode + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,ResetMode,"""M-mode [...] is the first mode entered at reset.""","Wait for reset to end, ensure that the core is in M-mode.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_initial_mode + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,Refetch,"Before a mode change, instructions can have been prefetched and exist in the pipeline but the fetching was done in a different mode than what is changed to. This should not allow for privilege escalation so the instructions must be refetched.","Checking: Handled by ""InstrProt"" below. + +Coverage: Instr fetched twice (same pc, different prot).",N/A,N/A,Functional Coverage,"COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_umode_notrap + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_mmode_notrap + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_umode_trap + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_mmode_trap", +obi,,InstrProt,"""prot[2:1] +User/Application (2’b00), Supervisor (2’b01), Reserved (2’b10), Machine (2’b11) +This matches the privilege levels from [RISC-V-PRIV].""","Track prot[2:1] on instruction fetches on obi, observe retirements on rvfi, ensure the privilege mode of the instruction's execution matches what it was fetched as on obi. + +Coverage: Explicitly observe U/M both.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot_legal + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_iside_legal + +COV: ???", +,,DataProt,"""prot[2:1] +User/Application (2’b00), Supervisor (2’b01), Reserved (2’b10), Machine (2’b11) +This matches the privilege levels from [RISC-V-PRIV].""","Track prot[2:1] on data loads/stores, observe retirements on rvfi, ensure the effective privilege mode of the retirement matches what was used on obi. + +Coverage: Explicitly observe U/M both.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_legal + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_dside_legal + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_equal + +COV: ???", +,,DbgProt,"Since dmode execs as mmode, and obi has corresponding signals, the relationship should be visible on obi.","When obi has a transaction with `dbg` high, check that `prot[2:1]` is M-mode on I-side, and ""effective"" mode on D-side. + +Note: Consider checking before MPU. + +Coverage: Observe U-/M-mode on D-side.",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_iside + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_dside + +COV: ???", +privspec,CSRs,IllegalAccess,"""Attempts to access a CSR without appropriate privilege level […] also raise illegal instruction exceptions""","Try all kinds of accesses (R, W, RW, S, C, …) to all M-level CSRs while in U-level; ensure illegal instruction exception happens. + +(Hint: Assert RVFI vs csr[9:8]) + +Functional coverage can do a full cross of modes vs all CSRs.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_illegal_csr_access + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr + +DTC: cv32e40s/tests/programs/custom/csr_priv_gen_test/", +,,AccessLevel,"""The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR.""","Try all kinds of accesses to all implemented M-level and U-level CSRs while in M-mode and U-mode (cross), ensure appropriate access grant/deny.",Check against RM,Constrained-Random,Functional Coverage,COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr, +,,Warl,U-level CSRs may have WARL fields.,"(There is only JVT, and must be handled by the Zc vplan. Link to cov here still.)",Other,N/A,N/A,"A: ??? +COV: ???",Waiting for Zc vplan linkage +,,MisaU,"""The “U” and “S” bits will be set if there is support for user and supervisor modes respectively.""","Read misa and see that ""U"" is always on. + +Coverage: Ensure actual csr read instruction read misa.",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_misa_bits + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,MisaN,"""N Tentatively reserved for User-Level Interrupts extension""","Read misa and see that ""N"" is always off. + +Coverage: Ensure actual csr read instruction read misa.",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_misa_bits + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,UserExtensions,"""If both XS and FS are hardwired to zero, then SD is also always zero."" + +""In systems without additional user extensions requiring new state, the XS field is hardwired to zero."" + +""If neither the F extension nor S-mode is implemented, then FS is hardwired to zero."" + +None of those 3 are implemented, so they should all be zero.","Check that mstatus {XS, FS, SD} are all 0.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_umode_extensions + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,MscratchReliable,"""the OS can rely on holding a value in the mscratch register while the user context +is running.""","Check that mscratch never changes in U-mode. + +(CLIC vplan must handle ""mscratchcsw"" and ""mscratchcswl"", but link to coverage of that here too.) + +Coverage: See that mscratch is attempted written from umode.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mscratch_reliable + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mscratch_changing + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,Mcsratchcsw,"The clic spec introduces ""conditional swapping"" of mscratch.",(Relevant user-mode related functionality must be handled by the CLIC vplan. Link to cov here still),N/A,N/A,N/A,"A: ??? +COV: ???",Waiting for CLIC vplan linkage. +,,MppValues,"""xPP fields are WARL fields that can hold only privilege mode x and any implemented privilege +mode lower than x"" + +""M-mode software can determine whether a privilege mode is implemented by writing that mode to MPP then reading it back.""","Checking: Check that MPP can hold ""M"" and ""U"" and that it can hold nothing else. + +Coverage: Write and read instrs with each 2-bit permutation.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mpp_mode + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mpp_umode + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mpp_mmode + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.gen_try_goto_mode[*].cov_try_goto_mode + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.gen_try_goto_mode[*].cov_write_mpp", +,,SppValues,"""If privilege mode x is not implemented, then xPP must be hardwired to 0.""",Check that SPP is always 0.,Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_spp_zero, +,,MedelegMideleg,"""In systems without S-mode, the medeleg and mideleg registers should not exist.""","Attempt access to these CSRs. + +Coverage: Instrs attempt (R/W) access.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_medeleg_mideleg + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,Mcounteren,"""In systems with U-mode, the mcounteren must be implemented""","Attempt access to this CSR. (See Counters section below too.) + +Coverage: Instrs attempt (R/W) access.",Assertion Check,Constrained-Random,Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mcounteren_access + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +n-ext,,NExt,N-extension CSRs used to be supported earlier in the legacy of the core's source code.,"Check that the old N-ext CSRs are not accessible (ustatus, uie, utvec, uscratch, uepc, ucause, utval, uip), and traps upon access attempts.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_next_csrs + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +manual,,Jvt,"The vector table jump CSR is accessible and effective in U-mode. ""Smstateen"" applies. Both CSR access and instruction execution is affected.","(Zc vplan should be responsible, but link to coverage here too.)",N/A,N/A,N/A,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_jvt_access + +COV: ???",Waiting for Zc vplan linkage +privspec,Traps,SoftwareInterrupts,U-mode software interrupts are not supported.,"Check that the zero-bits in `mie` and `mip` are always zero, and mcause is never S/U-mode software interrupt.",Assertion Check,Constrained-Random,Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromie + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromip + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_mcausemode + +DTC: cv32e40s/tests/programs/custom/privilege_test/", +,,TrapMpp,"""When a trap is taken from privilege mode y into privilege mode x, […] xPP is set to y.""","Checking: Be in mode y, observe exception and interrupt, check MPP is mode y. + +Cover: Cross U/M with Exc/Int.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_exception + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_general + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_debug + +COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mpp_excint", +,,HigherEnabled,"""Interrupts for higher-privilege modes, y>x ,are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.""",(Responsibility of Interrupts and Clic vplans. Link to coverage here too.),N/A,N/A,N/A,"A: ??? +COV: ???",Waiting for interrupts vplans +,,HigherDisable,"""Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.""",(Responsibility of Interrupts and Clic vplans. Link to coverage here too.),N/A,N/A,N/A,"A: ??? +COV: ???",Waiting for interrupts vplans +,,HigherNone,"""A higher-privilege mode y could disable all of its interrupts before ceding control to a lower-privilege mode""",(Responsibility of Interrupts and Clic vplans. Link to coverage here too.),N/A,N/A,N/A,"A: ??? + +COV: ???",Waiting for interrupts vplans +,,LowerLevel,"""Interrupts for lower-privilege modes, wx ,are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherDisable", + "Feature Description": "\"Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherNone", + "Feature Description": "\"A higher-privilege mode y could disable all of its interrupts before ceding control to a lower-privilege mode\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "LowerLevel", + "Feature Description": "\"Interrupts for lower-privilege modes, w> 2)", cfg.gpr[1]), + $sformatf("beq x%0d, x%1d, nmi_handler", cfg.gpr[0], cfg.gpr[1]) + }; + end + interrupt_handler_instr = { interrupt_handler_instr, $sformatf("csrr x%0d, 0x%0x # %0s;", cfg.gpr[0], status, status.name()), @@ -413,13 +562,17 @@ class cv32e40s_asm_program_gen extends corev_asm_program_gen; // generate NMI handler. // will be placed at a fixed address in memory, set in linker file - //TODO: verify correct functionality when NMI test capability is ready virtual function void gen_nmi_handler_section(int hart); string nmi_handler_instr[$]; // Insert section info so linker can place // debug code at the correct adress - instr_stream.push_back(".section .nmi, \"ax\""); + // We do not want a specific region for the handler code + // in case of direct mode interrupts, as its location is + // dynamically allocated + if (cfg.mtvec_mode == DIRECT) begin + instr_stream.push_back(".section .nmi, \"ax\""); + end // read relevant csr's nmi_handler_instr.push_back($sformatf("csrr x%0d, mepc", cfg.gpr[0])); @@ -434,4 +587,27 @@ class cv32e40s_asm_program_gen extends corev_asm_program_gen; nmi_handler_instr); endfunction : gen_nmi_handler_section + virtual function void gen_section(string label, string instr[$]); + string str; + if(label == "mtvec_handler" && cfg.mtvec_mode == VECTORED) begin + str = ".section .mtvec_handler, \"ax\""; + instr_stream.push_back(str); + str = format_string($sformatf("%0s:", label), LABEL_STR_LEN); + instr_stream.push_back(str); + end else if(label != "") begin + str = format_string($sformatf("%0s:", label), LABEL_STR_LEN); + instr_stream.push_back(str); + end + foreach(instr[i]) begin + str = {indent, instr[i]}; + instr_stream.push_back(str); + if (i == instr.size() - 1) begin + str = ".section .text"; + instr_stream.push_back(""); + instr_stream.push_back(str); + end + end + instr_stream.push_back(""); + endfunction : gen_section + endclass : cv32e40s_asm_program_gen diff --git a/cv32e40s/env/corev-dv/cv32e40s_csr_template.yaml b/cv32e40s/env/corev-dv/cv32e40s_csr_template.yaml deleted file mode 100644 index 14fea831f6..0000000000 --- a/cv32e40s/env/corev-dv/cv32e40s_csr_template.yaml +++ /dev/null @@ -1,1016 +0,0 @@ -# Copyright 2020 OpenHW Group -# Copyright 2019 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -################################################################################ -# -# CSR definitions for the CV32E40S CORE-V proessor core (an RV32IMCZ machine). -# -# This file can be used as input to "gen_csr_test.py" delivered as part of -# Google's riscv-dv project. Assuming you are running this from -# core-v-verif/vendor_lib/google/corev-dv and you've cloned riscv-dv, then the -# following command-line should work for you: -# -# python3 ../riscv-dv/scripts/gen_csr_test.py \ -# --csr_file cv32e40s_csr_template.yaml \ -# --xlen 32 -# -# Source document is the CV32E40S user Manual: -# https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40s_um/en/latest/index.html -# Revision 62f0d86b -# -# Assumptions: -# 1. Configuration core input mtvec_addr_i == 32'h0000_0000 -# 2. Configuration core input mhartid_i == 32'h0000_0000 -# 3. Configuration core input mimpid_i == 32'h0000_0000 -# 4. Core RTL parameters set as per User Manual defaults. -################################################################################ -#- csr: CSR_NAME -# description: > -# BRIEF_DESCRIPTION -# address: 0x### -# privilege_mode: MODE (D/M/S/H/U) -# rv32: -# - MSB_FIELD_NAME: -# - description: > -# BRIEF_DESCRIPTION -# - type: TYPE (WPRI/WLRL/WARL/R) -# - reset_val: RESET_VAL -# - msb: MSB_POS -# - lsb: LSB_POS -# - ... -# - ... -# - LSB_FIELD_NAME: -# - description: ... -# - type: ... -# - ... -# rv64: -# - MSB_FIELD_NAME: -# - description: > -# BRIEF_DESCRIPTION -# - type: TYPE (WPRI/WLRL/WARL/R) -# - reset_val: RESET_VAL -# - msb: MSB_POS -# - lsb: LSB_POS -# - ... -# - ... -# - LSB_FIELD_NAME: -# - description: ... -# - type: ... -# - ... - -# User CSRs not implemented for first release of CV32E40S -#- csr: cycle -# description: > -# (HPM) Cycle Counter -# address: 0xC00 -# privilege_mode: M -# rv32: -# - field_name: cycle -# description: > -# Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode cycle counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: instret -# description: > -# (HPM) Instruction-Retired Counter -# address: 0xC02 -# privilege_mode: M -# rv32: -# - field_name: instret -# description: > -# Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode instruction retired counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: hpmcounter3 -# description: > -# (HPM) Performance-Monitoring Counter3 -# address: 0xC03 -# privilege_mode: M -# rv32: -# - field_name: counter3 -# description: > -# Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine performance counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: cycleh -# description: > -# (HPM) Upper 32 Cycle Counter -# address: 0xC80 -# privilege_mode: M -# rv32: -# - field_name: cycleh -# description: > -# Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode cycle counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: instreth -# description: > -# (HPM) Upper 32 Instruction-Retired Counter -# address: 0xC82 -# privilege_mode: M -# rv32: -# - field_name: instreth -# description: > -# Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode instruction retired counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: hpmcounter3h -# description: > -# (HPM) Upper 32 Performance-Monitoring Counter3 -# address: 0xC83 -# privilege_mode: M -# rv32: -# - field_name: counter3h -# description: > -# Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine performance counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 - -# User Custom CSRs not verified for first release of CV32E40S - -# Machine CSRs - -# mcycle(h) and minstret(h) are done here because out of reset mcountinhibit -# will disable cycle and instruction retirement counts. These access tests -# will not work if this counting is enabled. -- csr: mcycle - description: > - Lower 32 Machine Cycle Counter - address: 0xB00 - privilege_mode: M - rv32: - - field_name: Count - description: > - Lower 32-bits of 64-bit machine cycle counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mcycleh - description: > - Upper 32 Machine Cycle Counter - address: 0xB80 - privilege_mode: M - rv32: - - field_name: Count - description: > - Upper 32-bits of 64-bit machine cycle counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: minstret - description: > - Lower 32 Machine Instructions-Retired Counter - address: 0xB02 - privilege_mode: M - rv32: - - field_name: Count - description: > - Lower 32-bits of 64-bit machine instructions retired counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: minstreth - description: > - Upper 32 Machine Instructions-Retired Counter - address: 0xB82 - privilege_mode: M - rv32: - - field_name: Count - description: > - Upper 32-bits of 64-bit machine instructions retired counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter3 - description: > - Lower 32-bit Machine Performance Monitoring Counter - address: 0xB03 - privilege_mode: M - rv32: - - field_name: Count - description: > - Lower 32-bits of 64-bit machine performance-monitoring counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter3h - description: > - Upper 32-bit Machine Performance Monitoring Counter - address: 0xB83 - privilege_mode: M - rv32: - - field_name: Count - description: > - Upper 32-bits of 64-bit machine performance-monitoring counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mstatus - description: > - Machine ISA Register - address: 0x300 - privilege_mode: M - rv32: - - field_name: MPP - description: > - Machine Previous Privilege mode, hardwired to 3'b11 when User mode not enabled - type: R - reset_val: 3 - msb: 12 - lsb: 11 - - field_name: PMIE - description: > - Previous Machine Interrupt Enable - type: WARL - reset_val: 0 - msb: 7 - lsb: 7 - - field_name: PUIE - description: > - Previous User Interrupt Enable - type: R - reset_val: 0 - msb: 4 - lsb: 4 - - field_name: MIE - description: > - Machine Interrupt Enable - type: WARL - reset_val: 0 - msb: 3 - lsb: 3 - - field_name: UIE - description: > - User Interrupt Enable - type: R - reset_val: 0 - msb: 0 - lsb: 0 -- csr: misa - description: > - Machine ISA Register - address: 0x301 - privilege_mode: M - rv32: - - field_name: MXL - description: > - Encodes native base ISA width - type: R - reset_val: 1 - msb: 31 - lsb: 30 - - field_name: Extensions - description: > - Encodes all supported ISA extensions - type: R - reset_val: 0x101104 - msb: 25 - lsb: 0 -- csr: mie - description: > - Machine Interrupt Enable - address: 0x304 - privilege_mode: M - rv32: - - field_name: MFIE - description: > - Machine Fast Interrupt Enables - type: WARL - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: MEIE - description: > - Machine External Interrupt Enable - type: WARL - reset_val: 0 - msb: 11 - lsb: 11 - - field_name: MTIE - description: > - Machine Timer Interrupt Enable - type: WARL - reset_val: 0 - msb: 7 - lsb: 7 - - field_name: MSIE - description: > - Machine Software Interrupt Enable - type: WARL - reset_val: 0 - msb: 3 - lsb: 3 -- csr: mtvec - description: > - Machine Trap-Vector Base Address - address: 0x305 - privilege_mode: M - rv32: - - field_name: BASE[31:8] - description: > - Trap-handler base address, always aligned to 256 bytes - type: WARL - reset_val: 0 # assumes mtvec_i == 0 - msb: 31 - lsb: 8 - - field_name: BASE[7:2] - description: > - Trap-handler base address, always aligned to 256 bytes - type: R - reset_val: 0 - msb: 7 - lsb: 2 - - field_name: MODE[1] - description: > - Always 0 - type: R - reset_val: 0 - msb: 1 - lsb: 1 - - field_name: MODE[0] - description: > - 0 = Direct mode, 1 = vectored mode - type: WARL - reset_val: 1 - msb: 0 - lsb: 0 - -### Not supported in CV32E40S ### -#- csr: menvcfg -# description: > -# Machine Environment Configuration Register -# address: 0x30A -# privilege_mode: M -# rv32: -# - field_name: FIOM -# description: > -# Fence of IO Implies Memory -# type: RW -# reset_val: 0 -# msb: 0 -# lsb: 0 -# - field_name: CBIE -# description: > -# Cache Block Invalidate Instruction Enable -# type: RW -# reset_val: 0 -# msb: 5 -# lsb: 4 -# - field_name: CBCFE -# description: > -# Cache Block Clean and Flush Instruction Enable -# type: RW -# reset_val: 0 -# msb: 6 -# lsb: 6 -# - field_name: CBZE -# description: > -# Cache Block Zero Instruction Enable -# type: RW -# reset_val: 0 -# msb: 7 -# lsb: 7 - -- csr: mstatush - description: > - Machine ISA register - address: 0x310 - privilege_mode: M - rv32: - - field_name: SBE - description: > - Supervisor Big Endian Memory Access (Always zero) - type: R - reset_val: 0 - msb: 4 - lsb: 4 - - field_name: MBE - description: > - Machine Mode Big Endian Memory Access (Always zero) - type: R - reset_val: 0 - msb: 5 - lsb: 5 - -### Not supported in CV32E40s ### -#- csr: menvcfgh -# description: > -# Machine Environment Configuration (h) -# address: 0x31A -# privilege_mode: M -# rv32: -# - field_name: STCE -# description: > -# STimecmp Enable -# type: RW -# reset_val: 0 -# msb: 31 -# lsb: 31 - -- csr: mcountinhibit - description: > - Machine Counter-Inhibit - address: 0x320 - privilege_mode: M - rv32: - - field_name: Selectors 31..4 - description: > - Selectors for mhpmcounter31..4 inhibit (assuming NUM_MHPMCOUNTER set to 1) - type: R - reset_val: 0 - msb: 31 - lsb: 4 - - field_name: Selectors 3 - description: > - Selectors for mhpmcounter3 inhibit (assuming NUM_MHPMCOUNTER set to 1) - type: WARL - reset_val: 1 - msb: 3 - lsb: 3 - - field_name: minstret inhibit - description: > - Inhibit minstret counting - type: WARL - reset_val: 1 - msb: 2 - lsb: 2 - - field_name: zero - description: > - Zero - type: R - reset_val: 0 - msb: 1 - lsb: 1 - - field_name: mcycle inhibit - description: > - Inhibit mcycle counting - type: WARL - reset_val: 1 - msb: 0 - lsb: 0 -# MHPMEVENT4..31 not full modeled by RM -- csr: mhpmevent3 - description: > - (HPM) Machine Performance-Monitoring Event Selector 3 - address: 0x323 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mscratch - description: > - Machine Scratch-pad Register - address: 0x340 - privilege_mode: M - rv32: - - field_name: MXL - description: > - Scratch-pad - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mepc - description: > - Machine Exception Program Counter - address: 0x341 - privilege_mode: M - rv32: - - field_name: EPC - description: > - Exception PC[31:1] - type: WARL - reset_val: 0 - msb: 31 - lsb: 1 - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 0 - lsb: 0 -- csr: mcause - description: > - Machine Exception Cause - address: 0x342 - privilege_mode: M - rv32: - - field_name: Interrupt - description: > - Set when exception triggered by interrupt - type: WARL - reset_val: 0 - msb: 31 - lsb: 31 - - field_name: zero - description: > - Always zero - type: R - reset_val: 0 - msb: 30 - lsb: 8 - - field_name: ecode - description: > - Exception Code - type: WARL - reset_val: 0 - msb: 7 - lsb: 0 -- csr: mtval - description: > - Machine Trap Value - address: 0x343 - privilege_mode: M - rv32: - - field_name: Trap value - description: > - Machine Trap Value - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mip - description: > - Machine Interrupt Pending - address: 0x344 - privilege_mode: M - rv32: - - field_name: Fast - description: > - Fast Interrupts Pending - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: zero - description: > - Always zero - type: R - reset_val: 0 - msb: 15 - lsb: 12 - - field_name: External - description: > - Machine External Interrupt Pending - type: R - reset_val: 0 - msb: 11 - lsb: 11 - - field_name: Timer - description: > - Machine Timer Interrupt Pending - type: R - reset_val: 0 - msb: 7 - lsb: 7 - - field_name: Software - description: > - Machine Software Interrupt Pending - type: R - reset_val: 0 - msb: 3 - lsb: 3 - -### Not Supported in CV32E40S ### -#- csr: henvcfg -# description: > -# Hypervisor Environment Configuration Register -# address: 0x61A -# privilege_mode: M -# rv32: -# - field_name: FIOM -# description: > -# Fence of IO Implies Memory -# type: R -# reset_val: 0 -# msb: 0 -# lsb: 0 -# - field_name: CBIE -# description: > -# Cache Block Invalidate Instruction Enable -# type: R -# reset_val: 0 -# msb: 5 -# lsb: 4 -# - field_name: CBCFE -# description: > -# Cache Block Clean and Flush Instruction Enable -# type: R -# reset_val: 0 -# msb: 6 -# lsb: 6 -# - field_name: CBZE -# description: > -# Cache Block Zero Instruction Enable -# type: R -# reset_val: 0 -# msb: 7 -# lsb: 7 - -### Not Supported in CV32E40S ### -#- csr: henvcfgh -# description: > -# Hypervisor Environment Configuration (h) -# address: 0x31A -# privilege_mode: M -# rv32: -# - field_name: STCE -# description: > -# STimecmp Enable -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 31 - -### Not Supported in CV32E40S ### -#- csr: mseccfg -# description: > -# Machine Security Configuration -# address: 0x747 -# privilege_mode: M -# rv32: -# - field_name: MML -# description: > -# Machine Mode Lockdown -# type: RW -# reset_val: 0 -# msb: 0 -# lsb: 0 -# - field_name: MMWP -# description: > -# Machine Mode Whitelist Policy -# type: RW -# reset_val: 0 -# msb: 1 -# lsb: 1 -# - field_name: RLB -# description: > -# Rule Locking Bypass -# type: RW -# reset_val: 0 -# msb: 2 -# lsb: 2 -# - field_name: USEED -# description: > -# User Mode Seed Access (Always Zero on cv32e40s) -# type: R -# reset_val: 0 -# msb: 8 -# lsb: 8 -# - field_name: SSEED -# description: > -# Supervisor Mode Seed Access (Always zero on cv32e40s) -# type: R -# reset_val: 0 -# msb: 9 -# lsb: 9 - -### Not supported in CV32E40S ### -#- csr: mseccfgh -# description: > -# Machine Security Configuration (h) -# address: 0x757 -# privilege_mode: M -# rv32: -# - field_name: Zero -# description: > -# Always zero -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 - -- csr: tselect - description: > - Trigger Select Register - address: 0x7A0 - privilege_mode: M - rv32: - - field_name: Trigger - description: > - Trigger select field - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: tdata1 - description: > - Trigger Data Register 1 - address: 0x7A1 - privilege_mode: M - rv32: - - field_name: Type - description: > - Address/data match trigger type - type: R - reset_val: 2 - msb: 31 - lsb: 28 - - field_name: dmode - description: > - Only debug mode can write tdata registers - type: R - reset_val: 1 - msb: 27 - lsb: 27 - - field_name: MaskMax - description: > - Only exact matching supported - type: R - reset_val: 0 - msb: 26 - lsb: 21 - - field_name: Hit - description: > - Hit indication not supported - type: R - reset_val: 0 - msb: 20 - lsb: 20 - - field_name: Select - description: > - Only address matching is supported - type: R - reset_val: 0 - msb: 19 - lsb: 19 - - field_name: Timing - description: > - Break before the instruction at the specified address - type: R - reset_val: 0 - msb: 18 - lsb: 18 - - field_name: Sizelo - description: > - Match accesses of any size - type: R - reset_val: 0 - msb: 17 - lsb: 16 - - field_name: Action - description: > - Enter debug mode on match - type: R - reset_val: 1 - msb: 15 - lsb: 12 - - field_name: Chain - description: > - Chaining not supported - type: R - reset_val: 0 - msb: 11 - lsb: 11 - - field_name: Match - description: > - Match the whole address - type: R - reset_val: 0 - msb: 10 - lsb: 7 - - field_name: m - description: > - Match in M-mode - type: R - reset_val: 1 - msb: 6 - lsb: 6 - - field_name: zero - description: > - Always zero - type: R - reset_val: 0 - msb: 5 - lsb: 5 - - field_name: s - description: > - S-mode not supported - type: R - reset_val: 0 - msb: 4 - lsb: 4 - - field_name: u - description: > - U-mode not supported - type: R - reset_val: 0 - msb: 3 - lsb: 3 - - field_name: execute - description: > - Enable matching on instruction address. Only writeable in Debug mode. - type: R - reset_val: 0 - msb: 2 - lsb: 2 - - field_name: store - description: > - Store address/data matching not supported - type: R - reset_val: 0 - msb: 1 - lsb: 1 - - field_name: load - description: > - Load address/data matching not supported - type: R - reset_val: 0 - msb: 0 - lsb: 0 -- csr: tdata2 - description: > - Trigger Data Register 2 - address: 0x7A2 - privilege_mode: M - rv32: - - field_name: Data - description: > - Native triggers are not supported, so writes to this register from M-Mode will be ignored. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: tdata3 - description: > - Trigger Data Register 3 - address: 0x7A3 - privilege_mode: M - rv32: - - field_name: Zero - description: > - CV32E40S does not support the features requiring this register. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: tinfo - description: > - Trigger Info - address: 0x7A4 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Info - description: > - Only type 2 supported - type: R - reset_val: 4 - msb: 15 - lsb: 0 -- csr: mcontext - description: > - Machine Context Register - address: 0x7A8 - privilege_mode: M - rv32: - - field_name: Zero - description: > - CV32E40S does not support the features requiring this register. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mscontext - description: > - Supervisor Context Register - address: 0x7AA - privilege_mode: M - rv32: - - field_name: Zero - description: > - CV32E40S does not support the features requiring this register. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -############################################################################### -# mvendorid, marchid, mimpid, mhartid and mconfigptr are temporarily -# excluded from auto-generation of access testing as all bits in these CSRs are -# RO, so any attempt to write them causes an illegal instruction exception. -# Access modes to these CSRs is tested in a separate, manually written test- -# program. -# -#- csr: mvendorid -# description: > -# Machine Vendor ID -# address: 0xF11 -# privilege_mode: M -# rv32: -# - field_name: Bank -# description: > -# Number of continuation codes in JEDEC manufacturer ID -# type: R -# reset_val: 12 -# msb: 31 -# lsb: 7 -# - field_name: ID -# description: > -# Final byte of JEDEC manufacturer ID, discarding the parity bit. -# type: R -# reset_val: 2 -# msb: 6 -# lsb: 0 -#- csr: marchid -# description: > -# Machine Architecture ID -# address: 0xF12 -# privilege_mode: M -# rv32: -# - field_name: ID -# description: > -# Machine Architecture ID of CV32E40S is 4 -# type: R -# reset_val: 4 -# msb: 31 -# lsb: 0 -#- csr: mimpid -# description: > -# Machine Implementation ID -# address: 0xF13 -# privilege_mode: M -# rv32: -# - field_name: ID -# description: > -# Machine Implementation ID -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: mhartid -# description: > -# Machine Hart ID -# address: 0xF14 -# privilege_mode: M -# rv32: -# - field_name: Hart -# description: > -# mhartid_i -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: mconfigptr -# description: > -# Machine configuration pointer -# address: 0xF15 -# privilege_mode: M -# rv32: -# -field_name: zero (reserved) -# description: > -# Always return zero -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 diff --git a/cv32e40s/env/corev-dv/cv32e40s_fencei_instr_lib.sv b/cv32e40s/env/corev-dv/cv32e40s_fencei_instr_lib.sv index 37d5dbb571..ec182699e0 100644 --- a/cv32e40s/env/corev-dv/cv32e40s_fencei_instr_lib.sv +++ b/cv32e40s/env/corev-dv/cv32e40s_fencei_instr_lib.sv @@ -184,7 +184,7 @@ class corev_store_fencei_exec_instr_stream extends riscv_load_store_rand_instr_s instr_list.push_back(directive); // Exec - instr = riscv_instr::get_rand_instr(.exclude_instr({NOP}), .exclude_group({RV32C})); + instr = riscv_instr::get_rand_instr(.exclude_instr({NOP}), .exclude_group({RV32C, RV32ZCA, RV32ZCB, RV32ZCBB, RV32ZCBM, RV32ZCMP, RV32ZCMT})); instr.imm.rand_mode(0); `DV_CHECK_RANDOMIZE_FATAL(instr, "failed to randomize exec instruction" ) @@ -204,7 +204,7 @@ class corev_store_fencei_exec_instr_stream extends riscv_load_store_rand_instr_s // Dummy, for replacing exec instr = riscv_instr::get_rand_instr( .include_category({LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}), - .exclude_group({RV32C})); + .exclude_group({RV32C, RV32ZCA, RV32ZCB, RV32ZCBB, RV32ZCBM, RV32ZCMP, RV32ZCMT})); `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, (category inside {LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}); // Note: Several of the constraints could be relaxed, but it turns really complicated @@ -303,17 +303,20 @@ class corev_vp_fencei_exec_instr_stream extends riscv_load_store_rand_instr_stre instr_list.insert(idx_fencei, instr); // Add norvc/rvc guards around the instr after fencei directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option norvc"; + directive.directive = ".option push"; instr_list.insert(idx_fencei + 1, directive); directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option rvc"; - instr_list.insert(idx_fencei + 3, directive); + directive.directive = ".option norvc"; + instr_list.insert(idx_fencei + 2, directive); + directive = corev_directive_instr::type_id::create("corev_directive_instr"); + directive.directive = ".option pop"; + instr_list.insert(idx_fencei + 4, directive); // Add a dummy instr at the top instr = riscv_instr::get_rand_instr( .exclude_instr({NOP}), .include_category({LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}), - .exclude_group({RV32C})); + .exclude_group({RV32C, RV32ZCA, RV32ZCB, RV32ZCBB, RV32ZCBM, RV32ZCMP, RV32ZCMT})); `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, (category inside {LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}); // Note: Several of the constraints could be relaxed, but it turns really complicated @@ -324,16 +327,20 @@ class corev_vp_fencei_exec_instr_stream extends riscv_load_store_rand_instr_stre ) instr.comment = "vp_fencei_exec: dummy"; instr.label = label_dummy; - // Add rvc (nb, reverse order, 3/3) + // Add pop (nb, reverse order, 4/4) (on by default if supported, this will otherwise fail if c is not supported) directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option rvc"; + directive.directive = ".option pop"; instr_list.push_front(directive); - // Add instr (nb, reverse order, 2/3) + // Add instr (nb, reverse order, 3/4) instr_list.push_front(instr); - // Add norvc (nb, reverse order, 1/3) + // Add norvc (nb, reverse order, 2/4) directive = corev_directive_instr::type_id::create("corev_directive_instr"); directive.directive = ".option norvc"; instr_list.push_front(directive); + // Add push (nb, reverse order, 1/4) + directive = corev_directive_instr::type_id::create("corev_directive_instr"); + directive.directive = ".option push"; + instr_list.push_front(directive); // Configure the vp addr register @@ -515,7 +522,7 @@ class corev_vp_fencei_exec_instr_stream extends riscv_load_store_rand_instr_stre function logic is_ok_target(riscv_instr instr); // Note: Could allow 16bit instrs, but that requires more accommodations return ( - (instr.group != RV32C) + (!(instr.group inside {RV32C, RV32ZCA, RV32ZCB, RV32ZCBB, RV32ZCBM, RV32ZCMP, RV32ZCMT})) && (instr.instr_name != NOP) && !((instr.rd == ZERO) && (instr.instr_name inside {ADDI, C_ADDI})) && !(instr.rd inside {cfg.reserved_regs, reserved_rd}) diff --git a/cv32e40s/env/corev-dv/cv32e40s_instr_base_test.sv b/cv32e40s/env/corev-dv/cv32e40s_instr_base_test.sv index cfb54b1ac2..e7b2db44c2 100644 --- a/cv32e40s/env/corev-dv/cv32e40s_instr_base_test.sv +++ b/cv32e40s/env/corev-dv/cv32e40s_instr_base_test.sv @@ -41,6 +41,7 @@ class cv32e40s_instr_base_test extends corev_instr_base_test; override_privil_reg(); override_privil_common_seq(); override_debug_rom_gen(); + override_instr_sequence(); super.build_phase(phase); linker_generator = new(); linker_generator.gen_pma_linker_scripts(); @@ -76,6 +77,11 @@ class cv32e40s_instr_base_test extends corev_instr_base_test; cv32e40s_debug_rom_gen::get_type()); endfunction + virtual function void override_instr_sequence(); + uvm_factory::get().set_type_override_by_type(riscv_instr_sequence::get_type(), + cv32e40s_instr_sequence::get_type()); + endfunction : override_instr_sequence + virtual function void apply_directed_instr(); endfunction diff --git a/cv32e40s/env/corev-dv/cv32e40s_instr_gen_config.sv b/cv32e40s/env/corev-dv/cv32e40s_instr_gen_config.sv index c62e7ca223..096ebdabe7 100644 --- a/cv32e40s/env/corev-dv/cv32e40s_instr_gen_config.sv +++ b/cv32e40s/env/corev-dv/cv32e40s_instr_gen_config.sv @@ -27,6 +27,10 @@ class cv32e40s_instr_gen_config extends riscv_instr_gen_config; // External config control (plusarg) to enable/disable fast_interrupt handlers bit enable_fast_interrupt_handler; bit enable_pma; + bit enable_dummy; + bit enable_hint; + bit disable_pc_hardening; + bit disable_data_independent_timing; bit exit_on_debug_exception; cv32e40s_pma_cfg pma_cfg; @@ -85,14 +89,18 @@ class cv32e40s_instr_gen_config extends riscv_instr_gen_config; } `uvm_object_utils_begin(cv32e40s_instr_gen_config) - `uvm_field_enum(mtvec_mode_t, mtvec_mode, UVM_DEFAULT) - `uvm_field_enum(riscv_reg_t, dp, UVM_DEFAULT) - `uvm_field_enum(riscv_reg_t, scratch_reg, UVM_DEFAULT) - `uvm_field_int(knob_zero_fast_intr_handlers, UVM_DEFAULT) - `uvm_field_int(enable_fast_interrupt_handler, UVM_DEFAULT) - `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT) - `uvm_field_int(enable_pma, UVM_DEFAULT) - `uvm_field_int(exit_on_debug_exception, UVM_DEFAULT) + `uvm_field_enum(mtvec_mode_t, mtvec_mode, UVM_DEFAULT) + `uvm_field_enum(riscv_reg_t, dp, UVM_DEFAULT) + `uvm_field_enum(riscv_reg_t, scratch_reg, UVM_DEFAULT) + `uvm_field_int(knob_zero_fast_intr_handlers, UVM_DEFAULT) + `uvm_field_int(enable_fast_interrupt_handler, UVM_DEFAULT) + `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT) + `uvm_field_int(enable_pma, UVM_DEFAULT) + `uvm_field_int(exit_on_debug_exception, UVM_DEFAULT) + `uvm_field_int(enable_dummy, UVM_DEFAULT) + `uvm_field_int(enable_hint, UVM_DEFAULT) + `uvm_field_int(disable_pc_hardening, UVM_DEFAULT) + `uvm_field_int(disable_data_independent_timing, UVM_DEFAULT) `uvm_object_utils_end function new(string name=""); @@ -101,6 +109,10 @@ class cv32e40s_instr_gen_config extends riscv_instr_gen_config; get_bool_arg_value("+enable_fast_interrupt_handler=", enable_fast_interrupt_handler); get_bool_arg_value("+enable_pma=", enable_pma); get_bool_arg_value("+exit_on_debug_exception=", exit_on_debug_exception); + get_bool_arg_value("+enable_dummy=", enable_dummy); + get_bool_arg_value("+enable_hint=", enable_hint); + get_bool_arg_value("+disable_pc_hardening=", disable_pc_hardening); + get_bool_arg_value("+disable_data_independent_timing=", disable_data_independent_timing); if (enable_pma) begin pma_cfg = cv32e40s_pma_cfg::type_id::create("pma_cfg"); diff --git a/cv32e40s/env/corev-dv/cv32e40s_instr_sequence.sv b/cv32e40s/env/corev-dv/cv32e40s_instr_sequence.sv new file mode 100644 index 0000000000..370acc9695 --- /dev/null +++ b/cv32e40s/env/corev-dv/cv32e40s_instr_sequence.sv @@ -0,0 +1,121 @@ +/* + * Copyright 2022 Silicon Laboratories Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------------------- +// +// CV32E40S instruction sequence, this override prevents hint/illegal instructions from +// overwriting atomic instruction sequences. +// +// TODO: Ideally we would like to only do this for the important instructions in the zcmt +// sequences, but as these instuctions are inserted into the instruction list the +// necessary information to identify these instructions are lost. +// +//----------------------------------------------------------------------------------------- +class cv32e40s_instr_sequence extends riscv_instr_sequence; + `uvm_object_utils(cv32e40s_instr_sequence) + + function new (string name = ""); + super.new(name); + endfunction : new + + virtual function void generate_instr_stream(bit no_label = 1'b0); + string prefix, str; + int i; + insert_illegal_hint_instr(); + instr_string_list = {}; + for(i = 0; i < instr_stream.instr_list.size(); i++) begin + if(i == 0) begin + if (no_label) begin + prefix = format_string(" ", LABEL_STR_LEN); + end else begin + prefix = format_string($sformatf("%0s:", label_name), LABEL_STR_LEN); + end + instr_stream.instr_list[i].has_label = 1'b1; + end else begin + if(instr_stream.instr_list[i].has_label) begin + prefix = format_string($sformatf("%0s:", instr_stream.instr_list[i].label), + LABEL_STR_LEN); + end else begin + prefix = format_string(" ", LABEL_STR_LEN); + end + end + str = {prefix, instr_stream.instr_list[i].convert2asm()}; + instr_string_list.push_back(str); + end + // If PMP is supported, need to align
to a 4-byte boundary. + // TODO(udi) - this might interfere with multi-hart programs, + // may need to specifically match hart0. + if (riscv_instr_pkg::support_pmp && !uvm_re_match(uvm_glob_to_re("*main*"), label_name)) begin + instr_string_list.push_front(".align 2"); + end + prefix = format_string($sformatf("%0d:", i), LABEL_STR_LEN); + if(!is_main_program) begin + generate_return_routine(prefix); + end + endfunction + + function void insert_illegal_hint_instr(); + int bin_instr_cnt; + int idx; + string str; + corev_directive_instr raw_instr; + illegal_instr.init(cfg); + bin_instr_cnt = instr_cnt * cfg.illegal_instr_ratio / 1000; + raw_instr = corev_directive_instr::type_id::create("instr"); + + if (bin_instr_cnt >= 0) begin + `uvm_info(`gfn, $sformatf("Injecting %0d illegal instructions, ratio %0d/100", + bin_instr_cnt, cfg.illegal_instr_ratio), UVM_LOW) + repeat (bin_instr_cnt) begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(illegal_instr, + exception != kHintInstr;) + raw_instr.directive = $sformatf(".4byte 0x%s # %0s", + illegal_instr.get_bin_str(), illegal_instr.comment); + raw_instr.has_label = 1'b0; + idx = $urandom_range(0, instr_stream.instr_list.size() - 1); + // Inserting instructions within atomic sequences causes + // issues with things such as jump tables etc. that depend + // on absolute addressing. + while (instr_stream.instr_list[idx].atomic) begin + idx = $urandom_range(0, instr_stream.instr_list.size() - 1); + end + //instr_stream.insert(idx, str); + instr_stream.insert_instr(raw_instr, idx); + end + end + bin_instr_cnt = instr_cnt * cfg.hint_instr_ratio / 1000; + if (bin_instr_cnt >= 0) begin + `uvm_info(`gfn, $sformatf("Injecting %0d HINT instructions, ratio %0d/100", + bin_instr_cnt, cfg.illegal_instr_ratio), UVM_LOW) + repeat (bin_instr_cnt) begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(illegal_instr, + exception == kHintInstr;) + raw_instr.directive = $sformatf(".2byte 0x%s # %0s", + illegal_instr.get_bin_str(), illegal_instr.comment); + raw_instr.has_label = 1'b0; + idx = $urandom_range(0, instr_stream.instr_list.size() - 1); + // Inserting instructions within atomic sequences causes + // issues with things such as jump tables etc. that depend + // on absolute addressing + while (instr_stream.instr_list[idx].atomic) begin + idx = $urandom_range(0, instr_stream.instr_list.size() - 1); + end + instr_stream.insert_instr(raw_instr, idx); + end + end + endfunction + +endclass : cv32e40s_instr_sequence diff --git a/cv32e40s/env/corev-dv/cv32e40s_instr_test_pkg.sv b/cv32e40s/env/corev-dv/cv32e40s_instr_test_pkg.sv index 39a8af85fc..ba4b2751cf 100644 --- a/cv32e40s/env/corev-dv/cv32e40s_instr_test_pkg.sv +++ b/cv32e40s/env/corev-dv/cv32e40s_instr_test_pkg.sv @@ -14,23 +14,27 @@ * limitations under the License. */ +`include "uvmt_cv32e40s_base_test_pkg.sv" + package cv32e40s_instr_test_pkg; import uvm_pkg::*; import riscv_instr_pkg::*; + import riscv_instr_pkg::XLEN; // This is needed to avoid conflict with uvmt_cv32e40s_base_test_pkg import riscv_instr_test_pkg::*; import riscv_signature_pkg::*; import corev_instr_test_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; - import cv32e40s_pkg::pma_region_t; + import cv32e40s_pkg::pma_cfg_t; - `include "uvmt_cv32e40s_constants.sv" `include "pma_adapted_mem_region_gen.sv" `include "cv32e40s_ldgen.sv" // Instruction streams specific to CV32E40S // RISCV-DV class override definitions + `include "cv32e40s_instr_sequence.sv" `include "cv32e40s_pma_cfg.sv" `include "cv32e40s_compressed_instr.sv" `include "cv32e40s_privil_reg.sv" @@ -41,6 +45,8 @@ package cv32e40s_instr_test_pkg; `include "cv32e40s_instr_base_test.sv" `include "cv32e40s_pma_instr_lib.sv" `include "cv32e40s_fencei_instr_lib.sv" + `include "cv32e40s_zcmp_instr_lib.sv" + `include "cv32e40s_zcmt_instr_lib.sv" // Push general purpose register to the debugger stack function automatic void push_gpr_to_debugger_stack(cv32e40s_instr_gen_config cfg_corev, diff --git a/cv32e40s/env/corev-dv/cv32e40s_jvt_table.sv b/cv32e40s/env/corev-dv/cv32e40s_jvt_table.sv new file mode 100644 index 0000000000..8a06e04dba --- /dev/null +++ b/cv32e40s/env/corev-dv/cv32e40s_jvt_table.sv @@ -0,0 +1,13 @@ +virtual class corev_zcmt_jvt_table; + rand riscv_reg_t jvt_addr; + rand bit [7:0] jvt_size; + riscv_instr jvt_contents[$]; + + function new(); + // Create empty table of correct size + for (int i = 0; i < jvt_size; i++) begin + jvt_contents.push_back('0); + end + endfunction : new + +endclass : corev_zcmt_jvt_table diff --git a/cv32e40s/env/corev-dv/cv32e40s_pma_cfg.sv b/cv32e40s/env/corev-dv/cv32e40s_pma_cfg.sv index f17fd4ddc1..e7736de804 100644 --- a/cv32e40s/env/corev-dv/cv32e40s_pma_cfg.sv +++ b/cv32e40s/env/corev-dv/cv32e40s_pma_cfg.sv @@ -17,7 +17,7 @@ // class cv32e40s_pma_cfg extends uvm_object; - pma_region_t regions[$]; + pma_cfg_t regions[$]; constraint attr_comb_c { foreach (regions[i]) { diff --git a/cv32e40s/env/corev-dv/cv32e40s_pma_instr_lib.sv b/cv32e40s/env/corev-dv/cv32e40s_pma_instr_lib.sv index 3cb841d98b..9126df5de7 100644 --- a/cv32e40s/env/corev-dv/cv32e40s_pma_instr_lib.sv +++ b/cv32e40s/env/corev-dv/cv32e40s_pma_instr_lib.sv @@ -43,6 +43,7 @@ virtual class corev_load_store_pma_base_stream extends riscv_load_store_rand_ins constraint valid_addr_reg_c { use_compressed -> (addr_reg inside {[S0:A5]}); !use_compressed -> (addr_reg inside {[T0:T6]}); + addr_reg inside {cfg.gpr}; } constraint valid_index_c { @@ -95,6 +96,8 @@ class corev_load_pma_instr_stream extends corev_load_store_pma_base_stream; use_compressed -> (dest_reg inside {[S0:A5]}); !use_compressed -> (dest_reg inside {[T0:T6]}); dest_reg != addr_reg; + dest_reg inside {cfg.gpr}; + addr_reg inside {cfg.gpr}; } `uvm_object_utils(corev_load_pma_instr_stream) @@ -247,6 +250,8 @@ class corev_load_store_pma_mixed_instr_stream extends corev_load_store_pma_base_ use_compressed -> (dest_reg inside {[S0:A5]}); !use_compressed -> (dest_reg inside {[T0:T6]}); dest_reg != addr_reg; + dest_reg inside {cfg.gpr}; + addr_reg inside {cfg.gpr}; } `uvm_object_utils(corev_load_store_pma_mixed_instr_stream) diff --git a/cv32e40s/env/corev-dv/cv32e40s_zcmp_instr_lib.sv b/cv32e40s/env/corev-dv/cv32e40s_zcmp_instr_lib.sv new file mode 100644 index 0000000000..49de928e46 --- /dev/null +++ b/cv32e40s/env/corev-dv/cv32e40s_zcmp_instr_lib.sv @@ -0,0 +1,343 @@ +/* + * Copyright 2022 Silicon Laboratories Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------------------- +// +// CV32E40S random zcmp instruction stream +// +//----------------------------------------------------------------------------------------- +class corev_zcmp_pushpop_base_stream extends riscv_directed_instr_stream; + + `uvm_object_utils(corev_zcmp_pushpop_base_stream) + + rand int num_mixed_instr; + + constraint num_mixed_c { + num_mixed_instr inside {[1:50]}; + } + + function new(string name = ""); + super.new(name); + endfunction : new + + extern function void generate_pushpop_instr(); + extern function void generate_pushpopret_instr(); + extern function void generate_pushpopretz_instr(); + extern function void generate_mvsa01_instr(); + extern function void generate_mva01s_instr(); + extern function void post_randomize(); + extern function void add_mixed_instr(int instr_cnt); + +endclass : corev_zcmp_pushpop_base_stream + +// ----------------------------------------------------------------------------- + +function void corev_zcmp_pushpop_base_stream::generate_pushpop_instr(); + riscv_compressed_instr instr; + bit [1:0] saved_spimm; + bit [3:0] saved_rlist; + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_PUSH}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_PUSH; + , "Failed randomizing CM.PUSH" + ) + + saved_spimm = instr.spimm; + saved_rlist = instr.rlist; + + instr.comment = $sformatf("start zcmp push pop instr sequence"); + insert_instr(instr, 0); + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_POP}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_POP; + spimm == local::saved_spimm; + rlist == local::saved_rlist; + , "Failed randomizing CM.PUSH" + ) + + instr.comment = $sformatf("end zcmp push pop instr sequence"); + insert_instr(instr, 1); + +endfunction : generate_pushpop_instr + +// ----------------------------------------------------------------------------- + +function void corev_zcmp_pushpop_base_stream::generate_pushpopret_instr(); + riscv_compressed_instr instr; + riscv_pseudo_instr la_instr; + + bit [1:0] saved_spimm; + bit [3:0] saved_rlist; + + // Backup ra, we might as well use push here + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_PUSH}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_PUSH; + spimm == 2'h0; // No additional stack adjust + rlist == 4'h4; // RA only + , "Failed randomizing CM.PUSH" + ) + instr.comment = $sformatf("start zcmp push popret instr sequence"); + insert_instr(instr, 0); + + la_instr = riscv_pseudo_instr::type_id::create("la_instr"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(la_instr, + pseudo_instr_name == LA; + rd == RA; + , "Failed randomizing LA" + ) + la_instr.imm_str = $sformatf("popret_%0d", get_inst_id()); + insert_instr(riscv_instr'(la_instr), 1); + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_PUSH}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_PUSH; + , "Failed randomizing CM.PUSH" + ) + + saved_spimm = instr.spimm; + saved_rlist = instr.rlist; + + instr.atomic = 1'b1; + insert_instr(instr, 2); + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_POPRET}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_POPRET; + spimm == local::saved_spimm; + rlist == local::saved_rlist; + , "Failed randomizing CM.PUSH" + ) + instr.atomic = 1'b0; + insert_instr(instr, 3); + + // restore ra after return + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_POP}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_POP; + spimm == 2'h0; + rlist == 4'h4; + , "Failed randomizing CM.PUSH" + ) + + instr.comment = $sformatf("end zcmp push popret instr sequence"); + insert_instr(instr, 4); + +endfunction : generate_pushpopret_instr + +// ----------------------------------------------------------------------------- + +function void corev_zcmp_pushpop_base_stream::generate_pushpopretz_instr(); + riscv_compressed_instr instr; + riscv_pseudo_instr la_instr; + + bit [1:0] saved_spimm; + bit [3:0] saved_rlist; + + // Backup ra, we might as well use push here + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_PUSH}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_PUSH; + spimm == 2'h0; // No additional stack adjust + rlist == 4'h4; // RA only + , "Failed randomizing CM.PUSH" + ) + instr.comment = $sformatf("start zcmp push popretz instr sequence"); + insert_instr(instr, 0); + + la_instr = riscv_pseudo_instr::type_id::create("la_instr"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(la_instr, + pseudo_instr_name == LA; + rd == RA; + , "Failed randomizing LA" + ) + la_instr.imm_str = $sformatf("popretz_%0d", get_inst_id()); + insert_instr(riscv_instr'(la_instr), 1); + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_PUSH}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_PUSH; + , "Failed randomizing CM.PUSH" + ) + + saved_spimm = instr.spimm; + saved_rlist = instr.rlist; + + instr.atomic = 1'b1; + insert_instr(instr, 2); + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_POPRETZ}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_POPRETZ; + spimm == local::saved_spimm; + rlist == local::saved_rlist; + , "Failed randomizing CM.PUSH" + ) + instr.atomic = 1'b0; + insert_instr(instr, 3); + + // restore ra after return + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_POP}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_POP; + spimm == 2'h0; + rlist == 4'h4; + , "Failed randomizing CM.PUSH" + ) + + instr.comment = $sformatf("end zcmp push popretz instr sequence"); + insert_instr(instr, 4); + +endfunction : generate_pushpopretz_instr + +// ----------------------------------------------------------------------------- + +function void corev_zcmp_pushpop_base_stream::generate_mvsa01_instr(); + riscv_compressed_instr instr; + riscv_reg_t saved_rs1; + riscv_reg_t saved_rs2; + + if (!(cfg.tp inside {A0, A1})) begin + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_MVSA01}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_MVSA01; + !(sreg1 inside {cfg.reserved_regs}); + !(sreg2 inside {cfg.reserved_regs}); + , "Failed randomizing CM.MVSA01" + ) + instr.comment = $sformatf("start zcmp mvsa01/mva01s instr sequence"); + saved_rs1 = instr.sreg1; + saved_rs2 = instr.sreg2; + + insert_instr(instr, 0); + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_MVA01S}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_MVA01S; + sreg1 == saved_rs1; + sreg2 == saved_rs2; + , "Failed randomizing CM.MVA01S" + ) + instr.comment = $sformatf("end zcmp mvsa01/mva01s instr sequence"); + insert_instr(instr, 1); + end else begin + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({C_NOP}))); + instr.comment = $sformatf("Registers reserved, skipping mvsa01-mva01s sequence"); + insert_instr(instr, 0); + end + +endfunction : generate_mvsa01_instr + +// ----------------------------------------------------------------------------- + +function void corev_zcmp_pushpop_base_stream::generate_mva01s_instr(); + riscv_compressed_instr instr; + riscv_reg_t saved_rs1; + riscv_reg_t saved_rs2; + + if (!(cfg.tp inside {A0, A1})) begin + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_MVA01S}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_MVA01S; + !(sreg1 inside {cfg.reserved_regs}); + !(sreg2 inside {cfg.reserved_regs}); + , "Failed randomizing CM.MVA01S" + ) + instr.comment = $sformatf("start zcmp mva01s/mvsa01 instr sequence"); + saved_rs1 = instr.sreg1; + saved_rs2 = instr.sreg2; + + insert_instr(instr, 0); + + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_MVSA01}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == CM_MVSA01; + sreg1 == saved_rs1; + sreg2 == saved_rs2; + , "Failed randomizing CM.MVSA01" + ) + instr.comment = $sformatf("end zcmp mva01s/mvsa01 instr sequence"); + insert_instr(instr, 1); + end else begin + instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({C_NOP}))); + instr.comment = $sformatf("Registers reserved, skipping mva01s-mvsa01 sequence"); + insert_instr(instr, 0); + end + +endfunction : generate_mva01s_instr + +// ----------------------------------------------------------------------------- + +function void corev_zcmp_pushpop_base_stream::post_randomize(); + + randsequence(main) + main: pop | popret | popretz | mvsa01 | mva01s; + pop: { + generate_pushpop_instr(); + instr_list[$].has_label = 1'b0; + }; + popret: { + generate_pushpopret_instr(); + instr_list[$].label = $sformatf("popret_%0d", get_inst_id()); + }; + popretz: { + generate_pushpopretz_instr(); + instr_list[$].label = $sformatf("popretz_%0d", get_inst_id()); + }; + mva01s: { + generate_mva01s_instr(); + instr_list[$].has_label = 1'b0; + }; + mvsa01: { + generate_mvsa01_instr(); + instr_list[$].has_label = 1'b0; + }; + endsequence + add_mixed_instr(num_mixed_instr); + + foreach(instr_list[i]) begin + if (i < instr_list.size()-1) begin + instr_list[i].has_label = 1'b0; + end + instr_list[i].atomic = 1'b1; + end + + instr_list[0].comment = $sformatf("Start %0s", get_name()); + instr_list[$].comment = $sformatf("End %0s", get_name()); + + if(label != "") begin + instr_list[0].label = label; + instr_list[0].has_label = 1'b1; + end +endfunction : post_randomize + +function void corev_zcmp_pushpop_base_stream::add_mixed_instr(int instr_cnt); + riscv_instr instr; + setup_allowed_instr(.no_branch(1), .no_load_store(1)); + for (int i = 0; i < instr_cnt; i++) begin + instr = riscv_instr::type_id::create("instr"); + randomize_instr(instr); + // Don't want to tamper with RA/SP as that breaks the + // intended sequence flow as there are dependencies on theses + // TODO constrain somehow rather than rerandomize + while (instr.rd == RA || instr.rd == SP || instr.rd == cfg.tp) begin + randomize_instr(instr); + end + insert_instr(instr); + end +endfunction : add_mixed_instr diff --git a/cv32e40s/env/corev-dv/cv32e40s_zcmt_instr_lib.sv b/cv32e40s/env/corev-dv/cv32e40s_zcmt_instr_lib.sv new file mode 100644 index 0000000000..9b02537030 --- /dev/null +++ b/cv32e40s/env/corev-dv/cv32e40s_zcmt_instr_lib.sv @@ -0,0 +1,217 @@ +/* + * Copyright 2022 Silicon Laboratories Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------------------- +// +// CV32E40S random table jump instruction stream +// +//----------------------------------------------------------------------------------------- +class corev_zcmt_base_stream extends riscv_directed_instr_stream; + + const int unsigned JVT_ALIGNMENT_BITS_CONST = 6; + + `uvm_object_utils(corev_zcmt_base_stream) + + rand int num_table_entries; + rand int num_mixed_instr; + + function new(string name = ""); + super.new(name); + endfunction : new + + extern function void generate_jump_table_instr(int entries); + extern function void add_mixed_instr(int instr_cnt); + extern function void post_randomize(); + + constraint num_table_entries_cnstr { + num_table_entries inside {[1:255]}; + } + + constraint num_mixed_c { + num_mixed_instr inside {[1:50]}; + } + +endclass : corev_zcmt_base_stream + +// ----------------------------------------------------------------------------- + +function void corev_zcmt_base_stream::generate_jump_table_instr(int entries); + riscv_instr instr; + riscv_compressed_instr compr_instr; + riscv_csr_instr csr_instr; + riscv_pseudo_instr pseudo_instr; + corev_directive_instr raw_instr; + riscv_reg_t saved_rdrs1; + automatic int unsigned instr_loc = 0; + + // Backup RA to preserve state + compr_instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_PUSH}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(compr_instr, + instr_name == CM_PUSH; + spimm == 2'h0; // No additional stack adjust + rlist == 4'h4; // RA only + , "Failed randomizing CM.PUSH" + ) + insert_instr(compr_instr, instr_loc++); + + // Load address of jump-table (jvt) + pseudo_instr = riscv_pseudo_instr::type_id::create("la_instr"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo_instr, + pseudo_instr_name == LA; + !(rd inside {cfg.reserved_regs, ZERO}); + , "Failed randomizing LA" + ) + pseudo_instr.atomic = 1'b1; + pseudo_instr.imm_str = $sformatf("jt_%0d", get_inst_id()); + saved_rdrs1 = pseudo_instr.rd; + insert_instr(riscv_instr'(pseudo_instr), instr_loc++); + + // Store table address to jvt + csr_instr = riscv_csr_instr::type_id::create("csr_instr"); + // TODO randomize possible? + csr_instr.instr_name = CSRRW; + csr_instr.format = R_FORMAT; + csr_instr.rd = ZERO; + csr_instr.csr = 12'h17; + csr_instr.rs1 = saved_rdrs1; + csr_instr.atomic = 1'b1; + csr_instr.write_csr = 1'b1; + insert_instr(riscv_instr'(csr_instr), instr_loc++); + + // Create random table jump instruction + instr = riscv_instr::get_rand_instr(.include_instr({CM_JT, CM_JALT})); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name inside {CM_JT, CM_JALT}; + , "Failed generating return instruction" + ) + insert_instr(instr, instr_loc++); + + // Create unique table label & alignment as required + raw_instr = corev_directive_instr::type_id::create("instr"); + raw_instr.directive = $sformatf(".global jt_%0d", get_inst_id()); + raw_instr.atomic = 1'b1; + raw_instr.has_label = 1'b0; + insert_instr(raw_instr, instr_loc++); + raw_instr = corev_directive_instr::type_id::create("instr"); + raw_instr.directive = $sformatf(".align %0d", JVT_ALIGNMENT_BITS_CONST); + raw_instr.atomic = 1'b1; + raw_instr.has_label = 1'b0; + insert_instr(raw_instr, instr_loc++); + + // Create pointers to the final target instruction and label + // the first table entry with the global symbol defined above + for (int i = 0; i < entries; i++) begin + raw_instr = corev_directive_instr::type_id::create("instr"); + raw_instr.directive = $sformatf(".long . + %0d", (entries - i)*4); + raw_instr.has_label = 1'b1; + raw_instr.label = i == 0 ? $sformatf("jt_%0d", get_inst_id()) : ""; + raw_instr.atomic = 1'b1; + insert_instr(raw_instr, instr_loc++); + end + + // Point RA to the last instruction in the sequence to + // control instruction sequence completion + pseudo_instr = riscv_pseudo_instr::type_id::create("la_instr"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo_instr, + pseudo_instr_name == LA; + rd == RA; + , "Failed randomizing LA" + ) + pseudo_instr.atomic = 1'b1; + pseudo_instr.imm_str = $sformatf("end_jvt_%0d", get_inst_id()); + insert_instr(riscv_instr'(pseudo_instr), instr_loc++); + + // Return to regular flow + instr = riscv_instr::get_rand_instr(.include_instr({JALR})); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + instr_name == JALR; + rd == ZERO; + rs1 == RA; + imm == 0; + , "Failed generating return instruction" + ) + insert_instr(instr, instr_loc++); + + // Insert random end of sequence target instruction (no flow change) as it is + // unsafe to return to the instruction after the last in sequence + instr = riscv_instr::get_rand_instr(.include_category({SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH})); + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, + (category inside {SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}); + // Note: Several of the constraints could be relaxed, but it turns really complicated + has_rd == 1 -> !(rd inside {cfg.reserved_regs}); + has_rd == 0 && has_rs1 -> !(rs1 inside {cfg.reserved_regs}); + , "failed to randomize dummy instruction" + ) + instr.has_label = 1'b1; + instr.label = $sformatf("end_jvt_%0d", get_inst_id()); + insert_instr(instr, instr_loc++); + + // restore ra after return + compr_instr = riscv_compressed_instr'(riscv_instr::get_rand_instr(.include_instr({CM_POP}))); + `DV_CHECK_RANDOMIZE_WITH_FATAL(compr_instr, + instr_name == CM_POP; + spimm == 2'h0; + rlist == 4'h4; + , "Failed randomizing CM.PUSH" + ) + + insert_instr(compr_instr, instr_loc++); + +endfunction : generate_jump_table_instr + +// ----------------------------------------------------------------------------- + +function void corev_zcmt_base_stream::post_randomize(); + + generate_jump_table_instr(256); + + // Add random instructions into the instruction stream, + // but not into sequences of instructions defined as atomic. + add_mixed_instr(num_mixed_instr); + + // Clear empty labels; prevents asm compilation failure with + // lines starting with : without a preceding label. + foreach(instr_list[i]) begin + if (instr_list[i].label == "") begin + instr_list[i].has_label = 1'b0; + end + instr_list[i].atomic = 1'b1; + end + + instr_list[0].comment = $sformatf("Start %0s", get_name()); + instr_list[$].comment = $sformatf("End %0s", get_name()); + +endfunction : post_randomize + +// ----------------------------------------------------------------------------- + +function void corev_zcmt_base_stream::add_mixed_instr(int instr_cnt); + riscv_instr instr; + setup_allowed_instr(.no_branch(1), .no_load_store(1)); + for (int i = 0; i < instr_cnt; i++) begin + instr = riscv_instr::type_id::create("instr"); + randomize_instr(instr); + // Don't want to tamper with RA as that breaks the + // intended sequence flow + // TODO constrain somehow rather than rerandomize + while (instr.rd == RA) begin + randomize_instr(instr); + end + insert_instr(instr); + end +endfunction : add_mixed_instr + +// ----------------------------------------------------------------------------- diff --git a/cv32e40s/env/corev-dv/ldgen/cv32e40s_ldgen.sv b/cv32e40s/env/corev-dv/ldgen/cv32e40s_ldgen.sv index cdd8c29e99..05b70b4188 100644 --- a/cv32e40s/env/corev-dv/ldgen/cv32e40s_ldgen.sv +++ b/cv32e40s/env/corev-dv/ldgen/cv32e40s_ldgen.sv @@ -20,7 +20,7 @@ /* * provide UVM environment entry and exit points. */ -import cv32e40s_pkg::pma_region_t; +import cv32e40s_pkg::pma_cfg_t; class cv32e40s_ldgen_c; @@ -47,8 +47,8 @@ import cv32e40s_pkg::pma_region_t; parameter RAM_ORIGIN = 32'h0000_0000; parameter RAM_LENGTH = 32'h40_0000; parameter BOOT_ADDR = 32'h80; - parameter NMI_ADDR = 32'h0010_0000; parameter MTVEC_ADDR = 32'h0000_0000; + parameter NMI_ADDR = 32'h0010_0000; parameter DEBUG_ORIGIN = 32'h1A11_0800; parameter DEBUG_EXCEPTION_ADDR = 32'h1A11_1000; parameter DEBUG_STACK_OFFSET = 32'h80; @@ -64,11 +64,17 @@ import cv32e40s_pkg::pma_region_t; // Path handles string ldfiles_path; + bit standalone_generate; + bit disable_default_ram_region; bit disable_default_dbg_region; bit enable_large_mem_support; + bit enable_rom_exec_writable_region; + bit enable_explicit_writable_region; bit nmi_separate_region; + int writable_region_idx; + int disable_section_write_boot = 0; int disable_section_write_nmi = 0; int region_length; @@ -96,8 +102,8 @@ import cv32e40s_pkg::pma_region_t; int fhandle_dbg; int fhandle_fix; - pma_region_t regions[PMA_NUM_REGIONS][$]; - pma_region_t temp_region; + pma_cfg_t regions[PMA_NUM_REGIONS][$]; + pma_cfg_t temp_region; int temp_region_ctr; pma_adapted_memory_regions_c pma_adapted_memory; @@ -118,12 +124,12 @@ import cv32e40s_pkg::pma_region_t; if (!($value$plusargs("boot_addr=0x%x", boot_addr))) begin boot_addr = BOOT_ADDR; end - if (!($value$plusargs("nmi_addr=0x%x", nmi_addr))) begin - nmi_addr = NMI_ADDR; - end if (!($value$plusargs("mtvec_addr=0x%x", mtvec_addr))) begin mtvec_addr = MTVEC_ADDR; end + if (!($value$plusargs("nmi_addr=0x%x", nmi_addr))) begin + nmi_addr = mtvec_addr + 4*15; + end if (!($value$plusargs("dm_halt_addr=0x%x", dbg_origin_addr))) begin dbg_origin_addr = DEBUG_ORIGIN; end @@ -142,6 +148,19 @@ import cv32e40s_pkg::pma_region_t; if (!($value$plusargs("enable_large_mem_support=%d", enable_large_mem_support))) begin enable_large_mem_support = LARGE_MEMORY_SUPPORT; end + if(!($value$plusargs("rom_exec_writable_region=%d", enable_rom_exec_writable_region))) begin + enable_rom_exec_writable_region = 0; + end + if(!($value$plusargs("writable_region_idx=%d", writable_region_idx))) begin + enable_explicit_writable_region = 0; + end + if(!($value$plusargs("standalone_generate=%d", standalone_generate))) begin + standalone_generate = 0; + end + + if (writable_region_idx != -1) begin + enable_explicit_writable_region = 1; + end if ($value$plusargs("ldgen_cp_test_path=%s", ldfiles_path)) begin if ($value$plusargs("start_idx=%d", start_idx)) begin @@ -230,6 +249,7 @@ endfunction : indent function void cv32e40s_ldgen_c::create_memory_layout_file(string filepath); automatic int nmi_region = -1; automatic int boot_region = -1; + automatic string w_string; fhandle_mem = $fopen(filepath, "w"); if (!fhandle_mem) begin @@ -239,6 +259,13 @@ function void cv32e40s_ldgen_c::create_memory_layout_file(string filepath); $fdisplay(fhandle_mem, "MEMORY"); $fdisplay(fhandle_mem, "{"); + if (enable_rom_exec_writable_region) begin + // Main executable region is not writable + w_string = ""; + end else begin + w_string = "w"; + end + // Optionally disable default ram region definition if (!disable_default_ram_region) begin $fdisplay(fhandle_mem, { indent(L1), $sformatf("ram (rwxai) : ORIGIN = 0x%08x, LENGTH = 0x%6x", RAM_ORIGIN, RAM_LENGTH) }); @@ -280,7 +307,11 @@ function void cv32e40s_ldgen_c::create_memory_layout_file(string filepath); if (!(pma_adapted_memory.region[i].cfg.main)) begin region_attributes = "(!i)"; end else begin - region_attributes = default_attributes; + if (i == boot_region) begin + region_attributes = $sformatf("(r%sxai)", w_string); + end else begin + region_attributes = default_attributes; + end end // Allow large memory regions if enabled, otherwise restrict to max SMALL_MEM_LIMIT @@ -311,8 +342,14 @@ function void cv32e40s_ldgen_c::create_memory_layout_file(string filepath); $fdisplay(fhandle_mem, "}"); // if the default ram region is enabled, we alias the lowest numbered executable pma region to ram (boot address needs to be set accordingly) - if (disable_default_ram_region) begin + + if (disable_default_ram_region && !enable_rom_exec_writable_region && !enable_explicit_writable_region) begin $fdisplay(fhandle_mem, { "REGION_ALIAS(\"ram\", region_", $sformatf("%0d", boot_region), ");" }); + end else if(CORE_PARAM_PMA_NUM_REGIONS > 0) begin + $fdisplay(fhandle_mem, { "REGION_ALIAS(\"rom\", region_", $sformatf("%0d", boot_region), ");" }); + $fdisplay(fhandle_mem, { "REGION_ALIAS(\"ram\", region_", $sformatf("%0d", writable_region_idx >= 0 ? writable_region_idx : 0), ");" }); + end else begin + $fdisplay(fhandle_mem, { "REGION_ALIAS(\"rom\", ram);" }); end $fclose(fhandle_mem); @@ -348,7 +385,7 @@ function void cv32e40s_ldgen_c::create_pma_section_file(string filepath); $fdisplay(fhandle_pma, { indent(L1), ".region_", $sformatf("%0d %0s", i, section_location), ":" }); $fdisplay(fhandle_pma, { indent(L1), "{" }); $fdisplay(fhandle_pma, { indent(L2), "KEEP(*(.region_", $sformatf("%0d", i), "));" }); - $fdisplay(fhandle_pma, { indent(L1), "}"}); + $fdisplay(fhandle_pma, { indent(L1), "} > region_", $sformatf("%0d", i) }); end end $fdisplay(fhandle_pma, "}"); @@ -434,7 +471,7 @@ function void cv32e40s_ldgen_c::create_fixed_addr_section_file(string filepath); display_fatal($sformatf("Unable to open %s", filepath)); end if (pma_adapted_memory.region.size == 0) begin - nmi_separate_region = 1; + nmi_separate_region = 0; end foreach (pma_adapted_memory.region[i]) begin @@ -476,23 +513,43 @@ function void cv32e40s_ldgen_c::create_fixed_addr_section_file(string filepath); nmi_memory_area = ""; end - $fdisplay(fhandle_fix, "SECTIONS"); - $fdisplay(fhandle_fix, "{"); - $fdisplay(fhandle_fix, { indent(L1), "/* CORE-V: interrupt vectors */" }); - $fdisplay(fhandle_fix, { indent(L1), "PROVIDE(__vector_start = ", $sformatf("0x%08x", mtvec_addr), ");" }); - $fdisplay(fhandle_fix, { indent(L1), ".mtvec_bootstrap (__vector_start) :" }); - $fdisplay(fhandle_fix, { indent(L1), "{" }); - $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.mtvec_bootstrap));" }); - $fdisplay(fhandle_fix, { indent(L1), "}", mtvec_memory_area, "\n" }); - $fdisplay(fhandle_fix, { indent(L1), "/* CORE-V: we want a fixed entry point */" }); - $fdisplay(fhandle_fix, { indent(L1), "PROVIDE(__boot_address = ", $sformatf("0x%08x", boot_addr), ");\n" }); - $fdisplay(fhandle_fix, { indent(L1), "/* NMI interrupt handler fixed entry point */" }); - $fdisplay(fhandle_fix, { indent(L1), "nmi_handler = ABSOLUTE(", $sformatf("0x%08x", nmi_addr), ");" }); - $fdisplay(fhandle_fix, { indent(L1), ".nmi (", $sformatf("0x%08x", nmi_addr), ") :" }); - $fdisplay(fhandle_fix, { indent(L1), "{" }); - $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.nmi));" }); - $fdisplay(fhandle_fix, { indent(L1), "}", nmi_memory_area }); - $fdisplay(fhandle_fix, "}"); + if (!standalone_generate) begin + $fdisplay(fhandle_fix, "SECTIONS"); + $fdisplay(fhandle_fix, "{"); + $fdisplay(fhandle_fix, { indent(L1), "/* CORE-V: interrupt vectors */" }); + $fdisplay(fhandle_fix, { indent(L1), "PROVIDE(__vector_start = ", $sformatf("0x%08x", mtvec_addr), ");" }); + $fdisplay(fhandle_fix, { indent(L1), "mtvec_handler = DEFINED(vectored_mode) ? ABSOLUTE(", $sformatf("0x%08x", mtvec_addr), ") : mtvec_handler;"}); + $fdisplay(fhandle_fix, { indent(L1), ".mtvec_bootstrap (__vector_start) :" }); + $fdisplay(fhandle_fix, { indent(L1), "{" }); + $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.mtvec_bootstrap));" }); + $fdisplay(fhandle_fix, { indent(L1), "}", mtvec_memory_area, "\n" }); + + $fdisplay(fhandle_fix, { indent(L1), ".mtvec_handler (__vector_start) :" }); + $fdisplay(fhandle_fix, { indent(L1), "{" }); + $fdisplay(fhandle_fix, { indent(L2), "*(.mtvec*);" }); + $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.mtvec_handler));" }); + $fdisplay(fhandle_fix, { indent(L1), "}", mtvec_memory_area, "\n" }); + + $fdisplay(fhandle_fix, { indent(L1), "/* CORE-V: we want a fixed entry point */" }); + $fdisplay(fhandle_fix, { indent(L1), "PROVIDE(__boot_address = ", $sformatf("0x%08x", boot_addr), ");\n" }); + $fdisplay(fhandle_fix, { indent(L1), "/* NMI interrupt handler fixed entry point */" }); + $fdisplay(fhandle_fix, { indent(L1), $sformatf(".nmi_bootstrap ABSOLUTE(0x%08x) ", nmi_addr), " :"}); + $fdisplay(fhandle_fix, { indent(L1), "{" }); + $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.nmi_bootstrap));" }); + $fdisplay(fhandle_fix, { indent(L1), "}", nmi_memory_area, "\n" }); + $fdisplay(fhandle_fix, "}"); + end else begin + $fdisplay(fhandle_fix, "SECTIONS"); + $fdisplay(fhandle_fix, "{"); + $fdisplay(fhandle_fix, { indent(L1), "PROVIDE(__boot_address = ", $sformatf("0x%08x", boot_addr), ");\n" }); + $fdisplay(fhandle_fix, { indent(L2), "PROVIDE(__vector_start = ", $sformatf("0x%08x", mtvec_addr), ");\n" }); + $fdisplay(fhandle_fix, { indent(L1), ".vectors (__vector_start):" }); + $fdisplay(fhandle_fix, { indent(L1), "{" }); + $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.vectors));" }); + $fdisplay(fhandle_fix, { indent(L1), "}", mtvec_memory_area, "\n"}); + + $fdisplay(fhandle_fix, "}"); + end $fclose(fhandle_fix); display_message({ filepath, " generated" }); diff --git a/cv32e40s/env/corev-dv/target/cv32e40s/riscv_core_setting.sv b/cv32e40s/env/corev-dv/target/cv32e40s/riscv_core_setting.sv index 0688f60d32..e2c652d2b2 100644 --- a/cv32e40s/env/corev-dv/target/cv32e40s/riscv_core_setting.sv +++ b/cv32e40s/env/corev-dv/target/cv32e40s/riscv_core_setting.sv @@ -24,16 +24,17 @@ parameter int XLEN = 32; parameter satp_mode_t SATP_MODE = BARE; // Supported Privileged mode -privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE}; +privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE/*, TODO: USER_MODE*/}; // Unsupported instructions riscv_instr_name_t unsupported_instr[]; // ISA supported by the processor -riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32ZBA, RV32ZBB, RV32ZBC, RV32ZBS}; +// Note: zcbb and zcbm are the zbb and m/zmmul-dependent instructions in zcb +riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32ZBA, RV32ZBB, RV32ZBC, RV32ZBS, RV32ZCA, RV32ZCB, RV32ZCBB, RV32ZCBM, RV32ZCMP, RV32ZCMT}; // Interrupt mode support -mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; +mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED, CLIC}; // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is // supported @@ -45,6 +46,9 @@ bit [31:0] valid_interrupt_mask = 32'hffff_0888; // Physical memory protection support bit support_pmp = 0; +// Enhanced physical memory protection support +bit support_epmp = 0; + // Debug mode support bit support_debug_mode = 1; diff --git a/cv32e40s/env/uvme/cov/uvme_debug_covg.sv b/cv32e40s/env/uvme/cov/uvme_debug_covg.sv index 0382aecee4..7d4af3748c 100644 --- a/cv32e40s/env/uvme/cov/uvme_debug_covg.sv +++ b/cv32e40s/env/uvme/cov/uvme_debug_covg.sv @@ -205,8 +205,8 @@ class uvme_debug_covg extends uvm_component; // Cover that we get a debug_req while in wfi covergroup cg_wfi_debug_req; `per_instance_fcov - inwfi : coverpoint cntxt.debug_cov_vif.mon_cb.in_wfi { - bins hit = {1}; + inwfi : coverpoint cntxt.debug_cov_vif.mon_cb.ctrl_fsm_cs { + bins hit = {SLEEP}; } dreq: coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { bins hit = {1}; @@ -294,19 +294,20 @@ class uvme_debug_covg extends uvm_component; covergroup cg_debug_regs_d_mode; `per_instance_fcov mode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins M = {1}; + bins M = {1}; } access : coverpoint (cntxt.debug_cov_vif.mon_cb.csr_access && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; + bins hit = {1}; } op : coverpoint cntxt.debug_cov_vif.mon_cb.csr_op { - bins read = {'h0}; - bins write = {'h1}; - // TODO:ropeders also SET and CLEAR? + bins read = {cv32e40s_pkg::CSR_OP_READ}; + bins write = {cv32e40s_pkg::CSR_OP_WRITE}; + bins set = {cv32e40s_pkg::CSR_OP_SET}; + bins clear = {cv32e40s_pkg::CSR_OP_CLEAR}; } addr : coverpoint cntxt.debug_cov_vif.mon_cb.wb_stage_instr_rdata_i[31:20] { // csr addr not updated if illegal access - bins dcsr = {'h7B0}; - bins dpc = {'h7B1}; + bins dcsr = {'h7B0}; + bins dpc = {'h7B1}; bins dscratch0 = {'h7B2}; bins dscratch1 = {'h7B3}; } @@ -317,19 +318,20 @@ class uvme_debug_covg extends uvm_component; covergroup cg_debug_regs_m_mode; `per_instance_fcov mode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins M = {0}; + bins M = {0}; } access : coverpoint (cntxt.debug_cov_vif.mon_cb.csr_access && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; + bins hit = {1}; } op : coverpoint cntxt.debug_cov_vif.mon_cb.csr_op { - bins read = {1'h0}; - bins write = {1'h1}; - // TODO:ropeders also SET and CLEAR? + bins read = {cv32e40s_pkg::CSR_OP_READ}; + bins write = {cv32e40s_pkg::CSR_OP_WRITE}; + bins set = {cv32e40s_pkg::CSR_OP_SET}; + bins clear = {cv32e40s_pkg::CSR_OP_CLEAR}; } addr : coverpoint cntxt.debug_cov_vif.mon_cb.wb_stage_instr_rdata_i[31:20] { // csr addr not updated if illegal access - bins dcsr = {'h7B0}; - bins dpc = {'h7B1}; + bins dcsr = {'h7B0}; + bins dpc = {'h7B1}; bins dscratch0 = {'h7B2}; bins dscratch1 = {'h7B3}; } @@ -342,17 +344,18 @@ class uvme_debug_covg extends uvm_component; `per_instance_fcov mode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q; // Only M and D supported access : coverpoint (cntxt.debug_cov_vif.mon_cb.csr_access && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; + bins hit = {1}; } op : coverpoint cntxt.debug_cov_vif.mon_cb.csr_op { - bins read = {'h0}; - bins write = {'h1}; + bins read = {cv32e40s_pkg::CSR_OP_READ}; + bins write = {cv32e40s_pkg::CSR_OP_WRITE}; + bins set = {cv32e40s_pkg::CSR_OP_SET}; + bins clear = {cv32e40s_pkg::CSR_OP_CLEAR}; } addr : coverpoint cntxt.debug_cov_vif.mon_cb.wb_stage_instr_rdata_i[31:20] { // csr addr not updated if illegal access - bins tsel = {'h7A0}; + bins tsel = {'h7A0}; bins tdata1 = {'h7A1}; bins tdata2 = {'h7A2}; - bins tdata3 = {'h7A3}; bins tinfo = {'h7A4}; } tregs_access : cross mode, access, op, addr; diff --git a/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_agent.sv b/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_agent.sv index ebd7cfb5aa..6e2f85c453 100644 --- a/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_agent.sv +++ b/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_agent.sv @@ -25,7 +25,6 @@ */ class uvma_cv32e40s_core_cntrl_agent_c extends uvma_core_cntrl_agent_c; - string log_tag = "CV32E40SCORECTRLAGT"; `uvm_component_utils_begin(uvma_cv32e40s_core_cntrl_agent_c) @@ -57,6 +56,18 @@ class uvma_cv32e40s_core_cntrl_agent_c extends uvma_core_cntrl_agent_c; */ extern virtual task start_fetch_toggle_seq(); + /** + * End of elaboration phase + * Emit ovpsim.ic control file + */ + extern function void end_of_elaboration_phase(uvm_phase phase); + + /** + * Configure core specific ISS overrides + */ + extern function void configure_iss(); + + endclass : uvma_cv32e40s_core_cntrl_agent_c function uvma_cv32e40s_core_cntrl_agent_c::new(string name="uvma_cv32e40s_core_cntrl_agent", uvm_component parent=null); @@ -74,7 +85,7 @@ function void uvma_cv32e40s_core_cntrl_agent_c::retrieve_vif(); $cast(e40s_cntxt, cntxt); // Core control interface - if (!uvm_config_db#(virtual uvme_cv32e40s_core_cntrl_if)::get(this, "", $sformatf("core_cntrl_vif"), e40s_cntxt.core_cntrl_vif)) begin + if (!uvm_config_db#(virtual uvme_cv32e40s_core_cntrl_if_t)::get(this, "", $sformatf("core_cntrl_vif"), e40s_cntxt.core_cntrl_vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(e40s_cntxt.core_cntrl_vif))) end @@ -114,4 +125,139 @@ task uvma_cv32e40s_core_cntrl_agent_c::start_fetch_toggle_seq(); endtask : start_fetch_toggle_seq +function void uvma_cv32e40s_core_cntrl_agent_c::end_of_elaboration_phase(uvm_phase phase); + super.end_of_elaboration_phase(phase); + + if (cfg.use_iss) begin + configure_iss(); + end + +endfunction : end_of_elaboration_phase + +function void uvma_cv32e40s_core_cntrl_agent_c::configure_iss(); + int fh; // file handle ISS control file (typically ovpsim.ic). + string refpath = "cpu" ; // root of config path in ISS control file. + + fh = $fopen(cfg.iss_control_file, "a"); + + // ------------------------------------------------------------------------------------- + // Parameters + // ------------------------------------------------------------------------------------- + + // Suppress unwanted log messages + if (cfg.iss_suppress_invalid_msg) begin + $fwrite(fh, $sformatf("--excludem RISCV_CSR_UNIMP\n")); + $fwrite(fh, $sformatf("--excludem RISCV_UDEC\n")); + $fwrite(fh, $sformatf("--excludem RISCV_NFP128\n")); + $fwrite(fh, $sformatf("--excludem RISCV_NFP16\n")); + $fwrite(fh, $sformatf("--excludem RISCV_ILL\n")); + end + + $fwrite(fh, $sformatf("--override %s/misa_Extensions=0x%06x\n", refpath, cfg.get_misa())); + $fwrite(fh, $sformatf("--override %s/noinhibit_mask=0x%08x\n", refpath, cfg.get_noinhibit_mask())); + $fwrite(fh, $sformatf("--override %s/Smstateen=T\n", refpath)); + + // ------------------------------------------------------------------------------------- + // Boot strap pins + // ------------------------------------------------------------------------------------- + $fwrite(fh, $sformatf("--override %s/mhartid=%0d\n", refpath, cfg.mhartid)); + $fwrite(fh, $sformatf("--override %s/mimpid=%0d\n", refpath, cfg.mimpid)); + $fwrite(fh, $sformatf("--override %s/startaddress=0x%08x\n", refpath, cfg.boot_addr)); + $fwrite(fh, $sformatf("--override %s/reset_address=0x%08x\n", refpath, cfg.boot_addr)); + // Specification forces mtvec[0] high at reset regardless of bootstrap pin state of mtvec_addr_i]0] + $fwrite(fh, $sformatf("--override %s/mtvec_mask=0xffffff8%1d\n", refpath, (cfg.clic_interrupt_enable ? 0 : 1))); + $fwrite(fh, $sformatf("--override %s/mtvec=0x%08x\n", refpath, cfg.mtvec_addr | (cfg.clic_interrupt_enable ? 32'b11 : 32'b1))); + $fwrite(fh, $sformatf("--override %s/nmi_address=0x%08x\n", refpath, cfg.nmi_addr)); + $fwrite(fh, $sformatf("--override %s/debug_address=0x%08x\n", refpath, cfg.dm_halt_addr)); + $fwrite(fh, $sformatf("--override %s/dexc_address=0x%08x\n", refpath, cfg.dm_exception_addr)); + $fwrite(fh, $sformatf("--override %s/extension_*/tdata1_reset=0x%08x\n", refpath, 'h28001000)); + + if (cfg.ext_zca_supported) begin + $fwrite(fh, $sformatf("--override %s/Zca=1\n", refpath)); + end else begin + $fwrite(fh, $sformatf("--override %s/Zca=0\n", refpath)); + end + + if (cfg.ext_zcb_supported) begin + $fwrite(fh, $sformatf("--override %s/Zcb=1\n", refpath)); + end else begin + $fwrite(fh, $sformatf("--override %s/Zcb=0\n", refpath)); + end + + if (cfg.ext_zcmp_supported) begin + $fwrite(fh, $sformatf("--override %s/Zcmp=1\n", refpath)); + end else begin + $fwrite(fh, $sformatf("--override %s/Zcmp=0\n", refpath)); + end + + if (cfg.ext_zcmt_supported) begin + $fwrite(fh, $sformatf("--override %s/Zcmt=1\n", refpath)); + end else begin + $fwrite(fh, $sformatf("--override %s/Zcmt=0\n", refpath)); + end + + if (cfg.is_ext_b_supported()) begin + // Bitmanip version + case (cfg.bitmanip_version) + BITMANIP_VERSION_0P90: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.90\n", refpath)); + BITMANIP_VERSION_0P91: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.91\n", refpath)); + BITMANIP_VERSION_0P92: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.92\n", refpath)); + BITMANIP_VERSION_0P93: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.93\n", refpath)); + BITMANIP_VERSION_0P93_DRAFT: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.93-draft\n", refpath)); + BITMANIP_VERSION_0P94: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.94\n", refpath)); + BITMANIP_VERSION_1P00: $fwrite(fh, $sformatf("--override %s/bitmanip_version=1.0.0\n", refpath)); + endcase + + // Bitmanip extensions + $fwrite(fh, $sformatf("--override %s/Zba=%0d\n", refpath, cfg.ext_zba_supported)); + $fwrite(fh, $sformatf("--override %s/Zbb=%0d\n", refpath, cfg.ext_zbb_supported)); + $fwrite(fh, $sformatf("--override %s/Zbc=%0d\n", refpath, cfg.ext_zbc_supported)); + $fwrite(fh, $sformatf("--override %s/Zbe=%0d\n", refpath, cfg.ext_zbe_supported)); + $fwrite(fh, $sformatf("--override %s/Zbf=%0d\n", refpath, cfg.ext_zbf_supported)); + $fwrite(fh, $sformatf("--override %s/Zbm=%0d\n", refpath, cfg.ext_zbm_supported)); + $fwrite(fh, $sformatf("--override %s/Zbp=%0d\n", refpath, cfg.ext_zbp_supported)); + $fwrite(fh, $sformatf("--override %s/Zbr=%0d\n", refpath, cfg.ext_zbr_supported)); + $fwrite(fh, $sformatf("--override %s/Zbs=%0d\n", refpath, cfg.ext_zbs_supported)); + $fwrite(fh, $sformatf("--override %s/Zbt=%0d\n", refpath, cfg.ext_zbt_supported)); + end + + case(cfg.debug_spec_version) + DEBUG_VERSION_0_13_2: $fwrite(fh, $sformatf("--override %s/debug_version=0.13.2-DRAFT\n", refpath)); + DEBUG_VERSION_0_14_0: $fwrite(fh, $sformatf("--override %s/debug_version=0.14.0-DRAFT\n", refpath)); + DEBUG_VERSION_1_0_0: begin + $fwrite(fh, $sformatf("--override %s/debug_version=1.0.0-STABLE\n", refpath)); + end + endcase + + case(cfg.priv_spec_version) + PRIV_VERSION_MASTER: $fwrite(fh, $sformatf("--override %s/priv_version=master\n", refpath)); + PRIV_VERSION_1_10: $fwrite(fh, $sformatf("--override %s/priv_version=1.10\n", refpath)); + PRIV_VERSION_1_11: $fwrite(fh, $sformatf("--override %s/priv_version=1.11\n", refpath)); + PRIV_VERSION_1_12: $fwrite(fh, $sformatf("--override %s/priv_version=1.12\n", refpath)); + PRIV_VERSION_20190405: $fwrite(fh, $sformatf("--override %s/priv_version=20190405\n", refpath)); + endcase + + if (cfg.priv_spec_version == PRIV_VERSION_1_12) begin + case(cfg.endianness) + ENDIAN_LITTLE, ENDIAN_BIG: $fwrite(fh, $sformatf("--override %s/endianFixed=1\n", refpath)); + ENDIAN_MIXED: $fwrite(fh, $sformatf("--override %s/endianFixed=0\n", refpath)); + endcase + end + + // PMA Regions + $fwrite(fh, $sformatf("--override %s/extension_*/PMA_NUM_REGIONS=%0d\n", refpath, cfg.pma_regions.size())); + foreach (cfg.pma_regions[i]) begin + $fwrite(fh, $sformatf("--override %s/extension_*/word_addr_low%0d=0x%08x\n", refpath, i, cfg.pma_regions[i].word_addr_low)); + $fwrite(fh, $sformatf("--override %s/extension_*/word_addr_high%0d=0x%08x\n", refpath, i, cfg.pma_regions[i].word_addr_high)); + $fwrite(fh, $sformatf("--override %s/extension_*/main%0d=%0d\n", refpath, i, cfg.pma_regions[i].main)); + $fwrite(fh, $sformatf("--override %s/extension_*/bufferable%0d=%0d\n", refpath, i, cfg.pma_regions[i].bufferable)); + $fwrite(fh, $sformatf("--override %s/extension_*/cacheable%0d=%0d\n", refpath, i, cfg.pma_regions[i].cacheable)); + $fwrite(fh, $sformatf("--override %s/extension_*/atomic%0d=%0d\n", refpath, i, 1)); + end + + // Enable use of hw reg names instead of abi + $fwrite(fh, $sformatf("--override %s/use_hw_reg_names=T\n", refpath)); + $fclose(fh); +endfunction : configure_iss + `endif // __UVMA_CV32E40S_CORE_CNTRL_AGENT_SV__ diff --git a/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_cntxt.sv b/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_cntxt.sv index 0deadfb663..11c207ae65 100644 --- a/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_cntxt.sv +++ b/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_cntxt.sv @@ -25,7 +25,7 @@ */ class uvma_cv32e40s_core_cntrl_cntxt_c extends uvma_core_cntrl_cntxt_c; - virtual uvme_cv32e40s_core_cntrl_if core_cntrl_vif; + virtual uvme_cv32e40s_core_cntrl_if_t core_cntrl_vif; `uvm_object_utils_begin(uvma_cv32e40s_core_cntrl_cntxt_c) `uvm_object_utils_end diff --git a/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_drv.sv b/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_drv.sv index 9ddc80eab8..c5eb4f32cb 100644 --- a/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_drv.sv +++ b/cv32e40s/env/uvme/uvma_cv32e40s_core_cntrl_drv.sv @@ -54,7 +54,7 @@ task uvma_cv32e40s_core_cntrl_drv_c::drive_bootstrap(); e40s_cntxt.core_cntrl_vif.dm_halt_addr = cfg.dm_halt_addr; e40s_cntxt.core_cntrl_vif.dm_exception_addr = cfg.dm_exception_addr; e40s_cntxt.core_cntrl_vif.mhartid = cfg.mhartid; - e40s_cntxt.core_cntrl_vif.mimpid = cfg.mimpid; + e40s_cntxt.core_cntrl_vif.mimpid_patch = cfg.mimpid_patch; e40s_cntxt.core_cntrl_vif.fetch_en = 1'b0; e40s_cntxt.core_cntrl_vif.scan_cg_en = 1'b0; diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_buserr_sb.sv b/cv32e40s/env/uvme/uvme_cv32e40s_buserr_sb.sv index 6de7a3479b..85ce1f8653 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_buserr_sb.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_buserr_sb.sv @@ -59,6 +59,7 @@ class uvme_cv32e40s_buserr_sb_c extends uvm_scoreboard; bit pending_nmi; // Whether nmi happened and handler is expected int late_retires; // Number of non-debug/step/handler retires since "pending_nmi" uvma_obi_memory_mon_trn_c obii_err_queue[$]; // All I-side OBI trns last seen with "err" + uvma_obi_memory_addr_l_t obii_ok_addrs[$]; // Latest non-"err" obi transaction addresses `uvm_component_utils(uvme_cv32e40s_buserr_sb_c) @@ -108,6 +109,11 @@ function void uvme_cv32e40s_buserr_sb_c::write_obii(uvma_obi_memory_mon_trn_c tr end else begin // Acquit this address, as it was (re)fetched wo/ err remove_from_err_queue(trn); + + // Store the 3 latest non-"err" addresses as they could be in the pipeline + // after the same address has been added to the "err" queue + if (obii_ok_addrs.size() == 3) void'(obii_ok_addrs.pop_back()); + obii_ok_addrs.push_front(trn.address); end endfunction : write_obii @@ -126,20 +132,21 @@ function void uvme_cv32e40s_buserr_sb_c::write_rvfi(uvma_rvfi_instr_seq_item_c#( if (should_instr_err(trn)) begin cnt_rvfi_errmatch++; - //TODO:mateilga remove this separate counter when RVFI is updated with an intr cause field - if (trn.dbg_mode) begin - cnt_rvfi_errmatch_debug++; - end - - assert (trn.trap) + assert (trn.trap.trap) else `uvm_error(info_tag, $sformatf("retire at 0x%08x (expected 'err') lacks 'rvfi_trap'", trn.pc_rdata)); - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) - cnt_rvfi_ifaulthandl <= 1) + assert (cnt_rvfi_errmatch - cnt_rvfi_ifaulthandl <= 1) else `uvm_error(info_tag, "too many err retires without ifault handling"); + end else begin + foreach(obii_ok_addrs[i]) begin + if (obii_ok_addrs[i] == trn.pc_rdata) begin + obii_ok_addrs.delete(i); + break; + end + end end // D-side NMI handler - //TODO:mateilga update this to check the new intr cause field when RVFI is updated - if (trn.intr && mcause[31] && (mcause[30:0] inside {128, 129})) begin + if (trn.intr.intr && (trn.intr.cause inside {1024, 1025, 1026, 1027})) begin cnt_rvfi_nmihandl++; assert (pending_nmi) @@ -151,12 +158,12 @@ function void uvme_cv32e40s_buserr_sb_c::write_rvfi(uvma_rvfi_instr_seq_item_c#( end // I-side exception handler - //TODO:mateilga update this to check the new intr cause field when RVFI is updated. This will allow for counting handler entries during debug - if (trn.intr && !mcause[31] && (mcause[31:0] == 48)) begin + if (trn.intr.exception && (trn.intr.cause == 24)) begin cnt_rvfi_ifaulthandl++; - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) == cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, "ifault handler entered without matching an ifault retirement"); + // TODO: silabs-hfegran: This assertion needs a complete rewrite + //assert (cnt_rvfi_errmatch == cnt_rvfi_ifaulthandl) + // else `uvm_error(info_tag, "ifault handler entered without matching an ifault retirement"); end // Retires after D-side "first err" @@ -188,12 +195,12 @@ function void uvme_cv32e40s_buserr_sb_c::check_phase(uvm_phase phase); super.check_phase(phase); // Check OBI D-side - assert (cnt_obid_trn > 0) - else `uvm_warning(info_tag, "zero D-side OBI transactions received"); + if (cnt_obid_trn == 0) + `uvm_warning(info_tag, "zero D-side OBI transactions received"); assert (cnt_obid_trn >= cnt_obid_err) else `uvm_error(info_tag, "obid 'err' transactions counted wrong"); - assert (cnt_obid_trn != cnt_obid_err) - else `uvm_warning(info_tag, "all the D-side OBI transactions were errs"); + if (cnt_obid_trn == cnt_obid_err) + `uvm_warning(info_tag, "all the D-side OBI transactions were errs"); assert (cnt_obid_err >= cnt_obid_firsterr) else `uvm_error(info_tag, "obid 'first' transactions counted wrong"); assert (!(cnt_obid_err && !cnt_obid_firsterr)) @@ -210,49 +217,56 @@ function void uvme_cv32e40s_buserr_sb_c::check_phase(uvm_phase phase); else `uvm_error(info_tag, $sformatf("more/less 'err' (%0d) than nmi handling (%0d)", cnt_obid_firsterr, cnt_rvfi_nmihandl)); // Check OBI I-side - assert (cnt_obii_trn > 0) - else `uvm_warning(info_tag, "zero I-side OBI transactions received"); + if (cnt_obii_trn == 0) + `uvm_warning(info_tag, "zero I-side OBI transactions received"); assert (cnt_obii_trn >= cnt_obii_err) else `uvm_error(info_tag, "obii 'err' transactions counted wrong"); - assert (cnt_obii_trn != cnt_obii_err) - else `uvm_warning(info_tag, "all the I-side OBI transactions were errs"); + if (cnt_obii_trn == cnt_obii_err) + `uvm_warning(info_tag, "all the I-side OBI transactions were errs"); // Check RVFI I-side - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) >= cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, "more instr fault handler than actual err retirements"); - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) == cnt_rvfi_ifaulthandl) - else `uvm_warning(info_tag, $sformatf("err retires (%0d) != handler entries (%0d)", (cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug), cnt_rvfi_ifaulthandl)); - - // Check OBI I-side vs RVFI - assert (cnt_obii_err >= cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, $sformatf("less I-side err (%0d) than exception handling (%0d)", cnt_obii_err, cnt_rvfi_ifaulthandl)); - assert (cnt_obii_err >= cnt_rvfi_errmatch) - else `uvm_warning(info_tag, "more retired errs than fetches"); - - // Check RVFI (just a sanity check) - assert (cnt_rvfi_trn > 0) - else `uvm_warning(info_tag, "zero rvfi transactions received"); - - // Inform about the end state - `uvm_info(info_tag, $sformatf("received %0d D-side 'err' transactions", cnt_obid_err), UVM_NONE) - `uvm_info(info_tag, $sformatf("received %0d D-side 'first err' transactions", cnt_obid_firsterr), UVM_NONE) - `uvm_info(info_tag, $sformatf("observed %0d rvfi nmi handler entries", cnt_rvfi_nmihandl), UVM_NONE) - `uvm_info(info_tag, $sformatf("received %0d I-side 'err' transactions", cnt_obii_err), UVM_NONE) - `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions", cnt_rvfi_errmatch), UVM_NONE) - `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions during debug", cnt_rvfi_errmatch_debug), UVM_NONE) - `uvm_info(info_tag, $sformatf("observed %0d rvfi ifault handler entries", cnt_rvfi_ifaulthandl), UVM_NONE) - -endfunction : check_phase - - -function bit uvme_cv32e40s_buserr_sb_c::should_instr_err(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_trn); - - uvma_obi_memory_addr_l_t err_addrs[$]; + // TODO: silabs-hfegran needs rewrite - currently gives frequent false positives + //assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) >= cnt_rvfi_ifaulthandl) + // else `uvm_error(info_tag, "more instr fault handler than actual err retirements"); + if ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) != cnt_rvfi_ifaulthandl) + `uvm_warning(info_tag, $sformatf("err retires (%0d) != handler entries (%0d)", (cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug), cnt_rvfi_ifaulthandl)); + + // Check OBI I-side vs RVFI + assert (cnt_obii_err >= cnt_rvfi_ifaulthandl) + else `uvm_error(info_tag, $sformatf("less I-side err (%0d) than exception handling (%0d)", cnt_obii_err, cnt_rvfi_ifaulthandl)); + if (cnt_obii_err < cnt_rvfi_errmatch) + `uvm_warning(info_tag, "more retired errs than fetches"); + + // Check RVFI (just a sanity check) + if (cnt_rvfi_trn == 0) + `uvm_warning(info_tag, "zero rvfi transactions received"); + + // Inform about the end state + `uvm_info(info_tag, $sformatf("received %0d D-side 'err' transactions", cnt_obid_err), UVM_NONE) + `uvm_info(info_tag, $sformatf("received %0d D-side 'first err' transactions", cnt_obid_firsterr), UVM_NONE) + `uvm_info(info_tag, $sformatf("observed %0d rvfi nmi handler entries", cnt_rvfi_nmihandl), UVM_NONE) + `uvm_info(info_tag, $sformatf("received %0d I-side 'err' transactions", cnt_obii_err), UVM_NONE) + `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions", cnt_rvfi_errmatch), UVM_NONE) + `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions during debug", cnt_rvfi_errmatch_debug), UVM_NONE) + `uvm_info(info_tag, $sformatf("observed %0d rvfi ifault handler entries", cnt_rvfi_ifaulthandl), UVM_NONE) + + endfunction : check_phase + + + function bit uvme_cv32e40s_buserr_sb_c::should_instr_err(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_trn); + // This function may have corners that will incorrectly trigger errors when + // an error transaction is followed by a non-error transaction to the same address. + // To avoid this the scoreboard needs to be re-written to not rely on the addresses to identify transactions + + uvma_obi_memory_addr_l_t err_addrs[$]; bit [31:0] rvfi_addr = rvfi_trn.pc_rdata; // Extract all addrs from queue of I-side OBI "err" transactions + // but ignore addresses of the 3 latest non-"err" obi transactions. foreach (obii_err_queue[i]) begin - err_addrs[i] = obii_err_queue[i].address; + if (!({obii_err_queue[i].address} inside {obii_ok_addrs})) begin + err_addrs[i] = obii_err_queue[i].address; + end end foreach (err_addrs[i]) begin diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv b/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv index a26287b92f..47348aa9db 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv @@ -28,74 +28,105 @@ class uvme_cv32e40s_cfg_c extends uvma_core_cntrl_cfg_c; // Integrals rand int unsigned sys_clk_period; cv32e40s_pkg::b_ext_e b_ext; - bit obi_memory_instr_random_err_enabled = 0; - bit obi_memory_instr_one_shot_err_enabled = 0; - bit obi_memory_data_random_err_enabled = 0; - bit obi_memory_data_one_shot_err_enabled = 0; - rand bit buserr_scoreboarding_enabled = 1; + bit obi_memory_instr_random_err_enabled = 0; + bit obi_memory_instr_one_shot_err_enabled = 0; + bit obi_memory_data_random_err_enabled = 0; + bit obi_memory_data_one_shot_err_enabled = 0; + bit iss_suppress_invalid_msg = 0; + bit nmi_timeout_instr_plusarg_valid = 0; + bit irq_min_limit_plusarg_valid = 0; + bit single_step_min_limit_plusarg_valid = 0; + bit irq_single_step_threshold_plusarg_valid = 0; + bit clic_irq_clear_on_ack_plusarg_valid = 0; + rand bit clic_irq_clear_on_ack; + rand bit buserr_scoreboarding_enabled = 1; + rand int unsigned fetch_toggle_initial_delay; + rand int unsigned nmi_timeout_instr; + rand int unsigned single_step_min_limit; + rand int unsigned irq_min_limit; + rand int unsigned irq_single_step_threshold; // Agent cfg handles rand uvma_isacov_cfg_c isacov_cfg; rand uvma_clknrst_cfg_c clknrst_cfg; rand uvma_interrupt_cfg_c interrupt_cfg; + rand uvma_clic_cfg_c clic_cfg; rand uvma_debug_cfg_c debug_cfg; + rand uvma_wfe_wu_cfg_c wfe_wu_cfg; rand uvma_obi_memory_cfg_c obi_memory_instr_cfg; rand uvma_obi_memory_cfg_c obi_memory_data_cfg; rand uvma_fencei_cfg_c fencei_cfg; rand uvma_rvfi_cfg_c#(ILEN,XLEN) rvfi_cfg; - rand uvma_rvvi_cfg_c#(ILEN,XLEN) rvvi_cfg; rand uvma_pma_cfg_c#(ILEN,XLEN) pma_cfg; `uvm_object_utils_begin(uvme_cv32e40s_cfg_c) - `uvm_field_int ( enabled , UVM_DEFAULT ) - `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT ) - `uvm_field_int ( cov_model_enabled , UVM_DEFAULT ) - `uvm_field_int ( trn_log_enabled , UVM_DEFAULT ) - `uvm_field_int ( buserr_scoreboarding_enabled, UVM_DEFAULT ) - `uvm_field_int ( sys_clk_period , UVM_DEFAULT | UVM_DEC) - `uvm_field_enum (cv32e40s_pkg::b_ext_e, b_ext , UVM_DEFAULT ) - `uvm_field_int ( obi_memory_instr_random_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_instr_one_shot_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_data_random_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_data_one_shot_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( enabled, UVM_DEFAULT ) + `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT ) + `uvm_field_int ( cov_model_enabled, UVM_DEFAULT ) + `uvm_field_int ( trn_log_enabled, UVM_DEFAULT ) + `uvm_field_int ( buserr_scoreboarding_enabled, UVM_DEFAULT ) + `uvm_field_int ( sys_clk_period, UVM_DEFAULT | UVM_DEC ) + `uvm_field_enum (b_ext_e, b_ext, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_instr_random_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_instr_one_shot_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_data_random_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( obi_memory_data_one_shot_err_enabled, UVM_DEFAULT ) + `uvm_field_int ( iss_suppress_invalid_msg, UVM_DEFAULT ) + `uvm_field_int ( fetch_toggle_initial_delay, UVM_DEFAULT ) + `uvm_field_int ( nmi_timeout_instr, UVM_DEFAULT | UVM_DEC ) + `uvm_field_int ( single_step_min_limit, UVM_DEFAULT | UVM_DEC ) + `uvm_field_int ( irq_min_limit, UVM_DEFAULT | UVM_DEC ) + `uvm_field_int ( irq_single_step_threshold, UVM_DEFAULT | UVM_DEC ) `uvm_field_object(isacov_cfg , UVM_DEFAULT) `uvm_field_object(clknrst_cfg , UVM_DEFAULT) `uvm_field_object(interrupt_cfg , UVM_DEFAULT) + `uvm_field_object(clic_cfg , UVM_DEFAULT) `uvm_field_object(debug_cfg , UVM_DEFAULT) + `uvm_field_object(wfe_wu_cfg , UVM_DEFAULT) `uvm_field_object(obi_memory_instr_cfg , UVM_DEFAULT) `uvm_field_object(obi_memory_data_cfg , UVM_DEFAULT) `uvm_field_object(rvfi_cfg , UVM_DEFAULT) - `uvm_field_object(rvvi_cfg , UVM_DEFAULT) `uvm_field_object(fencei_cfg , UVM_DEFAULT) `uvm_field_object(pma_cfg , UVM_DEFAULT) `uvm_object_utils_end constraint defaults_cons { - soft enabled == 0; - soft is_active == UVM_PASSIVE; - soft scoreboarding_enabled == 1; - soft cov_model_enabled == 1; - soft trn_log_enabled == 1; - soft sys_clk_period == uvme_cv32e40s_sys_default_clk_period; // see uvme_cv32e40s_constants.sv - soft buserr_scoreboarding_enabled == 1; + soft enabled == 0; + soft is_active == UVM_PASSIVE; + soft scoreboarding_enabled == 1; + soft cov_model_enabled == 1; + soft trn_log_enabled == 1; + soft sys_clk_period == uvme_cv32e40s_sys_default_clk_period; // see uvme_cv32e40s_constants.sv + soft buserr_scoreboarding_enabled == 1; + soft fetch_toggle_initial_delay inside {[50:200]}; + soft nmi_timeout_instr == 0; // no timeout + soft irq_min_limit == 0; // no timeout + soft single_step_min_limit == 0; // no timeout + soft irq_single_step_threshold == 0; // no timeout + soft clic_irq_clear_on_ack == 1; } constraint cv32e40s_riscv_cons { xlen == uvma_core_cntrl_pkg::MXL_32; ilen == 32; - ext_i_supported == 1; - ext_c_supported == 1; - ext_m_supported == 1; - ext_zifencei_supported == 1; - ext_zicsr_supported == 1; - ext_a_supported == 0; - ext_p_supported == 0; - ext_v_supported == 0; - ext_f_supported == 0; - ext_d_supported == 0; + ext_i_supported == 1; + ext_c_supported == 1; + ext_m_supported == 1; + ext_zifencei_supported == 1; + ext_zicsr_supported == 1; + ext_a_supported == 0; + ext_p_supported == 0; + ext_v_supported == 0; + ext_f_supported == 0; + ext_d_supported == 0; + ext_zca_supported == 1; + ext_zcb_supported == 1; + ext_zcmb_supported == 0; + ext_zcmp_supported == 1; + ext_zcmt_supported == 1; if (b_ext == cv32e40s_pkg::B_NONE) { ext_zba_supported == 0; @@ -113,15 +144,16 @@ class uvme_cv32e40s_cfg_c extends uvma_core_cntrl_cfg_c; ext_zbc_supported == 1; ext_zbs_supported == 1; } - ext_zbe_supported == 0; - ext_zbf_supported == 0; - ext_zbm_supported == 0; - ext_zbp_supported == 0; - ext_zbr_supported == 0; - ext_zbt_supported == 0; + ext_zbe_supported == 0; + ext_zbf_supported == 0; + ext_zbm_supported == 0; + ext_zbp_supported == 0; + ext_zbr_supported == 0; + ext_zbt_supported == 0; + ext_nonstd_supported == 1; mode_s_supported == 0; - mode_u_supported == 0; + mode_u_supported == 1; pmp_supported == 0; debug_supported == 1; @@ -129,7 +161,8 @@ class uvme_cv32e40s_cfg_c extends uvma_core_cntrl_cfg_c; unaligned_access_amo_supported == 1; bitmanip_version == BITMANIP_VERSION_1P00; - priv_spec_version == PRIV_VERSION_MASTER; + priv_spec_version == PRIV_VERSION_1_12; + debug_spec_version == DEBUG_VERSION_1_0_0; endianness == ENDIAN_LITTLE; boot_addr_valid == 1; @@ -140,48 +173,66 @@ class uvme_cv32e40s_cfg_c extends uvma_core_cntrl_cfg_c; } constraint default_cv32e40s_boot_cons { - (!mhartid_plusarg_valid) -> (mhartid == 'h0000_0000); - (!mimpid_plusarg_valid) -> (mimpid == 'h0000_0000); - (!boot_addr_plusarg_valid) -> (boot_addr == 'h0000_0080); - (!mtvec_addr_plusarg_valid) -> (mtvec_addr == 'h0000_0000); - (!nmi_addr_plusarg_valid) -> (nmi_addr == 'h0010_0000); - (!dm_halt_addr_plusarg_valid) -> (dm_halt_addr == 'h1a11_0800); - (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h1a11_1000); + (!mhartid_plusarg_valid) -> (mhartid == 'h0000_0000); + (!mimpid_patch_plusarg_valid) -> (mimpid_patch == 'h0 ); + (!mimpid_plusarg_valid) -> (mimpid == {12'b0, MIMPID_MAJOR, 4'b0, MIMPID_MINOR, 4'b0, mimpid_patch[3:0]}); + (!boot_addr_plusarg_valid) -> (boot_addr == 'h0000_0080); + (!mtvec_addr_plusarg_valid) -> (mtvec_addr == 'h0000_0000); + (!nmi_addr_plusarg_valid) -> (nmi_addr == 'h0010_0000); + (!dm_halt_addr_plusarg_valid) -> (dm_halt_addr == 'h1a11_0800); + (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h1a11_1000); + (!clic_irq_clear_on_ack_plusarg_valid) -> (clic_irq_clear_on_ack == 1'b1); + solve mimpid_patch before mimpid; } constraint agent_cfg_cons { if (enabled) { clknrst_cfg.enabled == 1; - interrupt_cfg.enabled == 1; + interrupt_cfg.enabled == basic_interrupt_enable; + clic_cfg.enabled == clic_interrupt_enable; debug_cfg.enabled == 1; + wfe_wu_cfg.enabled == 1; rvfi_cfg.enabled == 1; - rvvi_cfg.enabled == use_iss; obi_memory_instr_cfg.enabled == 1; obi_memory_data_cfg.enabled == 1; fencei_cfg.enabled == 1; } - obi_memory_instr_cfg.version == UVMA_OBI_MEMORY_VERSION_1P2; + clic_cfg.is_mmode_irq_only == 1; + clic_cfg.clear_irq_on_ack == clic_irq_clear_on_ack; + + obi_memory_data_cfg.clic_interrupts_enabled == clic_interrupt_enable; + obi_memory_instr_cfg.clic_interrupts_enabled == clic_interrupt_enable; + obi_memory_data_cfg.basic_interrupts_enabled == basic_interrupt_enable; + obi_memory_instr_cfg.basic_interrupts_enabled == basic_interrupt_enable; + + obi_memory_instr_cfg.version == UVMA_OBI_MEMORY_VERSION_1P3; obi_memory_instr_cfg.drv_mode == UVMA_OBI_MEMORY_MODE_SLV; + obi_memory_instr_cfg.chk_scheme == UVMA_OBI_MEMORY_CHK_CV32E40S; obi_memory_instr_cfg.write_enabled == 0; obi_memory_instr_cfg.addr_width == XLEN; obi_memory_instr_cfg.data_width == XLEN; obi_memory_instr_cfg.id_width == 0; - obi_memory_instr_cfg.achk_width == 0; - obi_memory_instr_cfg.rchk_width == 0; + obi_memory_instr_cfg.achk_width == 12; + obi_memory_instr_cfg.rchk_width == 5; + //obi_memory_instr_cfg.achk_width == ENV_PARAM_INSTR_ACHK_WIDTH; + //obi_memory_instr_cfg.rchk_width == ENV_PARAM_INSTR_RCHK_WIDTH; obi_memory_instr_cfg.auser_width == 0; obi_memory_instr_cfg.ruser_width == 0; obi_memory_instr_cfg.wuser_width == 0; soft obi_memory_instr_cfg.drv_slv_gnt_random_latency_max <= 3; soft obi_memory_instr_cfg.drv_slv_rvalid_random_latency_max <= 6; - obi_memory_data_cfg.version == UVMA_OBI_MEMORY_VERSION_1P2; + obi_memory_data_cfg.version == UVMA_OBI_MEMORY_VERSION_1P3; obi_memory_data_cfg.drv_mode == UVMA_OBI_MEMORY_MODE_SLV; + obi_memory_data_cfg.chk_scheme == UVMA_OBI_MEMORY_CHK_CV32E40S; obi_memory_data_cfg.addr_width == XLEN; obi_memory_data_cfg.data_width == XLEN; obi_memory_data_cfg.id_width == 0; - obi_memory_data_cfg.achk_width == 0; - obi_memory_data_cfg.rchk_width == 0; + obi_memory_data_cfg.achk_width == 12; + obi_memory_data_cfg.rchk_width == 5; + //obi_memory_data_cfg.achk_width == ENV_PARAM_DATA_ACHK_WIDTH; + //obi_memory_data_cfg.rchk_width == ENV_PARAM_DATA_ACHK_WIDTH; obi_memory_data_cfg.auser_width == 0; obi_memory_data_cfg.ruser_width == 0; obi_memory_data_cfg.wuser_width == 0; @@ -195,24 +246,27 @@ class uvme_cv32e40s_cfg_c extends uvma_core_cntrl_cfg_c; isacov_cfg.seq_instr_x2_enabled == 1; isacov_cfg.reg_crosses_enabled == 0; isacov_cfg.reg_hazards_enabled == 1; + isacov_cfg.decoder == ISA_SUPPORT; + - rvfi_cfg.nret == uvme_cv32e40s_pkg::RVFI_NRET; - rvfi_cfg.nmi_load_fault_enabled == 1; - rvfi_cfg.nmi_load_fault_cause == cv32e40s_pkg::INT_CAUSE_LSU_LOAD_FAULT; - rvfi_cfg.nmi_store_fault_enabled == 1; - rvfi_cfg.nmi_store_fault_cause == cv32e40s_pkg::INT_CAUSE_LSU_STORE_FAULT; - rvfi_cfg.insn_bus_fault_enabled == 1; - rvfi_cfg.insn_bus_fault_cause == cv32e40s_pkg::EXC_CAUSE_INSTR_BUS_FAULT; + rvfi_cfg.nret == RVFI_NRET; + rvfi_cfg.nmi_load_fault_enabled == 1; + rvfi_cfg.nmi_load_fault_cause == cv32e40s_pkg::INT_CAUSE_LSU_LOAD_FAULT; + rvfi_cfg.nmi_store_fault_enabled == 1; + rvfi_cfg.nmi_store_fault_cause == cv32e40s_pkg::INT_CAUSE_LSU_STORE_FAULT; + rvfi_cfg.insn_bus_fault_enabled == 1; + rvfi_cfg.insn_bus_fault_cause == cv32e40s_pkg::EXC_CAUSE_INSTR_BUS_FAULT; if (is_active == UVM_ACTIVE) { isacov_cfg.is_active == UVM_PASSIVE; clknrst_cfg.is_active == UVM_ACTIVE; interrupt_cfg.is_active == UVM_ACTIVE; + clic_cfg.is_active == UVM_ACTIVE; + wfe_wu_cfg.is_active == UVM_ACTIVE; debug_cfg.is_active == UVM_ACTIVE; obi_memory_instr_cfg.is_active == UVM_ACTIVE; obi_memory_data_cfg.is_active == UVM_ACTIVE; rvfi_cfg.is_active == UVM_PASSIVE; - rvvi_cfg.is_active == UVM_ACTIVE; fencei_cfg.is_active == UVM_ACTIVE; } @@ -221,20 +275,22 @@ class uvme_cv32e40s_cfg_c extends uvma_core_cntrl_cfg_c; clknrst_cfg.trn_log_enabled == 0; debug_cfg.trn_log_enabled == 0; interrupt_cfg.trn_log_enabled == 0; + clic_cfg.trn_log_enabled == 0; + wfe_wu_cfg.trn_log_enabled == 0; isacov_cfg.trn_log_enabled == 0; obi_memory_data_cfg.trn_log_enabled == 1; obi_memory_instr_cfg.trn_log_enabled == 1; rvfi_cfg.trn_log_enabled == 1; - rvvi_cfg.trn_log_enabled == 1; } else { clknrst_cfg.trn_log_enabled == 0; debug_cfg.trn_log_enabled == 0; interrupt_cfg.trn_log_enabled == 0; + clic_cfg.trn_log_enabled == 0; + wfe_wu_cfg.trn_log_enabled == 0; isacov_cfg.trn_log_enabled == 0; obi_memory_data_cfg.trn_log_enabled == 0; obi_memory_instr_cfg.trn_log_enabled == 0; rvfi_cfg.trn_log_enabled == 0; - rvvi_cfg.trn_log_enabled == 0; } if (cov_model_enabled) { @@ -318,8 +374,9 @@ function uvme_cv32e40s_cfg_c::new(string name="uvme_cv32e40s_cfg"); core_name = "CV32E40S"; - if ($test$plusargs("USE_ISS")) + if ($test$plusargs("USE_ISS")) begin use_iss = 1; + end if ($test$plusargs("trn_log_disabled")) begin trn_log_enabled = 0; trn_log_enabled.rand_mode(0); @@ -329,32 +386,64 @@ function uvme_cv32e40s_cfg_c::new(string name="uvme_cv32e40s_cfg"); buserr_scoreboarding_enabled.rand_mode(0); end - if ($test$plusargs("obi_memory_instr_random_err")) + if ($test$plusargs("obi_memory_instr_random_err")) begin obi_memory_instr_random_err_enabled = 1; - if ($test$plusargs("obi_memory_instr_one_shot_err")) + end + if ($test$plusargs("obi_memory_instr_one_shot_err")) begin obi_memory_instr_one_shot_err_enabled = 1; - if ($test$plusargs("obi_memory_data_random_err")) + end + if ($test$plusargs("obi_memory_data_random_err")) begin obi_memory_data_random_err_enabled = 1; - if ($test$plusargs("obi_memory_data_one_shot_err")) + end + if ($test$plusargs("obi_memory_data_one_shot_err")) begin obi_memory_data_one_shot_err_enabled = 1; + end + if ($value$plusargs("nmi_timeout_instr=%d", nmi_timeout_instr)) begin + nmi_timeout_instr_plusarg_valid = 1; + nmi_timeout_instr.rand_mode(0); + end + if ($value$plusargs("irq_single_step_threshold=%0d", irq_single_step_threshold)) begin + irq_single_step_threshold_plusarg_valid = 1; + irq_single_step_threshold.rand_mode(0); + end + if ($value$plusargs("irq_min_limit=%0d", irq_min_limit)) begin + irq_min_limit_plusarg_valid = 1; + irq_min_limit.rand_mode(0); + end + if ($value$plusargs("single_step_min_limit=%0d", single_step_min_limit)) begin + single_step_min_limit_plusarg_valid = 1; + single_step_min_limit.rand_mode(0); + end + + if ($test$plusargs("enable_clic")) begin + clic_interrupt_enable = 1; + basic_interrupt_enable = 0; + end + + if ($value$plusargs("clic_irq_clear_on_ack=%0d", clic_irq_clear_on_ack)) begin + clic_irq_clear_on_ack_plusarg_valid = 1; + clic_irq_clear_on_ack.rand_mode(0); + end - isacov_cfg = uvma_isacov_cfg_c::type_id::create("isacov_cfg"); - clknrst_cfg = uvma_clknrst_cfg_c::type_id::create("clknrst_cfg"); - interrupt_cfg = uvma_interrupt_cfg_c::type_id::create("interrupt_cfg"); - debug_cfg = uvma_debug_cfg_c ::type_id::create("debug_cfg"); + + isacov_cfg = uvma_isacov_cfg_c::type_id::create("isacov_cfg"); + clknrst_cfg = uvma_clknrst_cfg_c::type_id::create("clknrst_cfg"); + interrupt_cfg = uvma_interrupt_cfg_c::type_id::create("interrupt_cfg"); + clic_cfg = uvma_clic_cfg_c::type_id::create("clic_cfg"); + debug_cfg = uvma_debug_cfg_c::type_id::create("debug_cfg"); + wfe_wu_cfg = uvma_wfe_wu_cfg_c::type_id::create("wfe_wu_cfg"); obi_memory_instr_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_instr_cfg"); obi_memory_data_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_data_cfg" ); - rvfi_cfg = uvma_rvfi_cfg_c#(ILEN,XLEN)::type_id::create("rvfi_cfg"); - rvvi_cfg = uvma_rvvi_ovpsim_cfg_c#(ILEN,XLEN)::type_id::create("rvvi_cfg"); - fencei_cfg = uvma_fencei_cfg_c::type_id::create("fencei_cfg"); - pma_cfg = uvma_pma_cfg_c#(ILEN,XLEN)::type_id::create("pma_cfg"); + rvfi_cfg = uvma_rvfi_cfg_c#(ILEN,XLEN)::type_id::create("rvfi_cfg"); + fencei_cfg = uvma_fencei_cfg_c::type_id::create("fencei_cfg"); + pma_cfg = uvma_pma_cfg_c#(ILEN,XLEN)::type_id::create("pma_cfg"); + obi_memory_instr_cfg.mon_logger_name = "OBII"; obi_memory_data_cfg.mon_logger_name = "OBID"; isacov_cfg.core_cfg = this; rvfi_cfg.core_cfg = this; - rvvi_cfg.core_cfg = this; endfunction : new @@ -370,9 +459,6 @@ function void uvme_cv32e40s_cfg_c::post_randomize(); rvfi_cfg.instr_name[0] = "INSTR"; - // Set volatile locations for virtual peripherals - rvvi_cfg.add_volatile_mem_addr_range(CV_VP_REGISTER_BASE, CV_VP_REGISTER_BASE + CV_VP_REGISTER_SIZE - 1); - // Disable some CSR checks from all tests configure_disable_csr_checks(); @@ -397,6 +483,7 @@ function void uvme_cv32e40s_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cnt pma_regions[i].main = e40s_cntxt.core_cntrl_vif.pma_cfg[i].main; pma_regions[i].bufferable = e40s_cntxt.core_cntrl_vif.pma_cfg[i].bufferable; pma_regions[i].cacheable = e40s_cntxt.core_cntrl_vif.pma_cfg[i].cacheable; + pma_regions[i].integrity = e40s_cntxt.core_cntrl_vif.pma_cfg[i].integrity; end // Copy to the pma_configuration @@ -404,7 +491,17 @@ function void uvme_cv32e40s_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cnt foreach (pma_cfg.regions[i]) pma_cfg.regions[i] = pma_regions[i]; -endfunction : sample_parameters + // Debug region overrides + pma_cfg.region_override_condition = uvma_pma_cfg_c#(ILEN,XLEN)::PMA_OVERRIDE_DEBUG; + pma_cfg.region_overrides = new[1]; + pma_cfg.region_overrides[0] = uvma_core_cntrl_pma_region_c::type_id::create("debug_pma_region_override"); + pma_cfg.region_overrides[0].word_addr_low = CORE_PARAM_DM_REGION_START >> 2; + pma_cfg.region_overrides[0].word_addr_high = CORE_PARAM_DM_REGION_END >> 2; + pma_cfg.region_overrides[0].main = 1; + pma_cfg.region_overrides[0].bufferable = 0; + pma_cfg.region_overrides[0].cacheable = 0; + pma_cfg.region_overrides[0].integrity = 0; +endfunction: sample_parameters function bit uvme_cv32e40s_cfg_c::is_csr_check_disabled(string name); @@ -419,6 +516,9 @@ endfunction : is_csr_check_disabled function void uvme_cv32e40s_cfg_c::configure_disable_csr_checks(); + // TODO: remove when fixed in ISS + disable_csr_check("misa"); + // Need to check disable_csr_check("mcountinhibit"); @@ -460,9 +560,12 @@ function void uvme_cv32e40s_cfg_c::set_unsupported_csr_mask(); unsupported_csr_mask[uvma_core_cntrl_pkg::INSTRETH] = 1; unsupported_csr_mask[uvma_core_cntrl_pkg::SCOUNTEREN] = 1; - // TODO:ropeders re-evaluate this when 40s is more stable + unsupported_csr_mask[uvma_core_cntrl_pkg::TDATA3] = 1; unsupported_csr_mask[uvma_core_cntrl_pkg::TCONTROL] = 1; + unsupported_csr_mask[uvma_core_cntrl_pkg::MCONTEXT] = 1; + unsupported_csr_mask[uvma_core_cntrl_pkg::SCONTEXT] = 1; + for (int i = 0; i < MAX_NUM_HPMCOUNTERS; i++) begin unsupported_csr_mask[uvma_core_cntrl_pkg::HPMCOUNTER3+i] = 1; unsupported_csr_mask[uvma_core_cntrl_pkg::HPMCOUNTER3H+i] = 1; diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_cntxt.sv b/cv32e40s/env/uvme/uvme_cv32e40s_cntxt.sv index 9bd962b9ac..0a0c490efc 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_cntxt.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_cntxt.sv @@ -26,20 +26,41 @@ class uvme_cv32e40s_cntxt_c extends uvm_object; // Virtual interface for Debug coverage - virtual uvmt_cv32e40s_debug_cov_assert_if debug_cov_vif; - virtual uvmt_cv32e40s_vp_status_if vp_status_vif; ///< Virtual interface for Virtual Peripherals - virtual uvma_interrupt_if intr_vif ; ///< Virtual interface for interrupts - virtual uvma_debug_if debug_vif ; ///< Virtual interface for debug + virtual uvmt_cv32e40s_debug_cov_assert_if_t debug_cov_vif; + virtual uvmt_cv32e40s_vp_status_if_t vp_status_vif; ///< Virtual interface for Virtual Peripherals + virtual uvma_interrupt_if_t intr_vif; ///< Virtual interface for interrupts + virtual uvma_clic_if_t#(CORE_PARAM_CLIC_ID_WIDTH) clic_vif; ///< Virtual interface for clic interrupts + virtual uvma_wfe_wu_if_t wfe_wu_vif; + virtual uvma_debug_if_t debug_vif; ///< Virtual interface for debug // Agent context handles - uvma_cv32e40s_core_cntrl_cntxt_c core_cntrl_cntxt; - uvma_clknrst_cntxt_c clknrst_cntxt; - uvma_interrupt_cntxt_c interrupt_cntxt; - uvma_debug_cntxt_c debug_cntxt; - uvma_obi_memory_cntxt_c obi_memory_instr_cntxt; - uvma_obi_memory_cntxt_c obi_memory_data_cntxt; + uvma_cv32e40s_core_cntrl_cntxt_c core_cntrl_cntxt; + uvma_clknrst_cntxt_c clknrst_cntxt; + uvma_interrupt_cntxt_c interrupt_cntxt; + uvma_clic_cntxt_c#(CORE_PARAM_CLIC_ID_WIDTH) clic_cntxt; + uvma_wfe_wu_cntxt_c wfe_wu_cntxt; + uvma_debug_cntxt_c debug_cntxt; + uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + ) obi_memory_instr_cntxt; + uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) obi_memory_data_cntxt; uvma_rvfi_cntxt_c#(ILEN,XLEN) rvfi_cntxt; - uvma_rvvi_cntxt_c#(ILEN,XLEN) rvvi_cntxt; uvma_fencei_cntxt_c fencei_cntxt; // Memory modelling @@ -53,11 +74,12 @@ class uvme_cv32e40s_cntxt_c extends uvm_object; `uvm_field_object(core_cntrl_cntxt, UVM_DEFAULT) `uvm_field_object(clknrst_cntxt, UVM_DEFAULT) `uvm_field_object(interrupt_cntxt, UVM_DEFAULT) + `uvm_field_object(clic_cntxt, UVM_DEFAULT) `uvm_field_object(debug_cntxt , UVM_DEFAULT) + `uvm_field_object(wfe_wu_cntxt , UVM_DEFAULT) `uvm_field_object(obi_memory_instr_cntxt, UVM_DEFAULT) `uvm_field_object(obi_memory_data_cntxt , UVM_DEFAULT) `uvm_field_object(rvfi_cntxt, UVM_DEFAULT) - `uvm_field_object(rvvi_cntxt, UVM_DEFAULT) `uvm_field_object(mem, UVM_DEFAULT) `uvm_field_event(sample_cfg_e , UVM_DEFAULT) @@ -85,10 +107,29 @@ function uvme_cv32e40s_cntxt_c::new(string name="uvme_cv32e40s_cntxt"); debug_cntxt = uvma_debug_cntxt_c::type_id::create("debug_cntxt"); fencei_cntxt = uvma_fencei_cntxt_c::type_id::create("fencei_cntxt"); interrupt_cntxt = uvma_interrupt_cntxt_c::type_id::create("interrupt_cntxt"); - obi_memory_data_cntxt = uvma_obi_memory_cntxt_c::type_id::create("obi_memory_data_cntxt" ); - obi_memory_instr_cntxt = uvma_obi_memory_cntxt_c::type_id::create("obi_memory_instr_cntxt"); + clic_cntxt = uvma_clic_cntxt_c#(CORE_PARAM_CLIC_ID_WIDTH)::type_id::create("clic_cntxt"); + wfe_wu_cntxt = uvma_wfe_wu_cntxt_c::type_id::create("wfe_wu_cntxt"); + obi_memory_data_cntxt = uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + )::type_id::create("obi_memory_data_cntxt" ); + obi_memory_instr_cntxt = uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + )::type_id::create("obi_memory_instr_cntxt"); rvfi_cntxt = uvma_rvfi_cntxt_c#(ILEN,XLEN)::type_id::create("rvfi_cntxt"); - rvvi_cntxt = uvma_rvvi_ovpsim_cntxt_c#(ILEN,XLEN)::type_id::create("rvvi_cntxt"); mem = uvml_mem_c#(XLEN)::type_id::create("mem"); diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_constants.sv b/cv32e40s/env/uvme/uvme_cv32e40s_constants.sv index f092026bfa..570f0a85b7 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_constants.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_constants.sv @@ -17,42 +17,6 @@ `ifndef __UVME_CV32E40S_CONSTANTS_SV__ `define __UVME_CV32E40S_CONSTANTS_SV__ - -parameter uvme_cv32e40s_sys_default_clk_period = 1_500; // 10ns -parameter uvme_cv32e40s_debug_default_clk_period = 10_000; // 10ns - -// For RVFI/RVVI -parameter ILEN = 32; -parameter XLEN = 32; -parameter RVFI_NRET = 1; - -// Control how often to print core scoreboard checked heartbeat messages -parameter PC_CHECKED_HEARTBEAT = 10_000; - -// Map the virtual peripheral registers -parameter CV_VP_REGISTER_BASE = 32'h0080_0000; -parameter CV_VP_REGISTER_SIZE = 32'h0000_1000; - -parameter CV_VP_VIRTUAL_PRINTER_OFFSET = 32'h0000_0000; -parameter CV_VP_RANDOM_NUM_OFFSET = 32'h0000_0040; -parameter CV_VP_CYCLE_COUNTER_OFFSET = 32'h0000_0080; -parameter CV_VP_STATUS_FLAGS_OFFSET = 32'h0000_00c0; -parameter CV_VP_FENCEI_TAMPER_OFFSET = 32'h0000_0100; -parameter CV_VP_INTR_TIMER_OFFSET = 32'h0000_0140; -parameter CV_VP_DEBUG_CONTROL_OFFSET = 32'h0000_0180; -parameter CV_VP_OBI_SLV_RESP_OFFSET = 32'h0000_01c0; -parameter CV_VP_SIG_WRITER_OFFSET = 32'h0000_0200; - -parameter CV_VP_VIRTUAL_PRINTER_BASE = CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET; -parameter CV_VP_RANDOM_NUM_BASE = CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET; -parameter CV_VP_CYCLE_COUNTER_BASE = CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET; -parameter CV_VP_STATUS_FLAGS_BASE = CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET; -parameter CV_VP_INTR_TIMER_BASE = CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET; -parameter CV_VP_DEBUG_CONTROL_BASE = CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET; -parameter CV_VP_OBI_SLV_RESP_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET; -parameter CV_VP_SIG_WRITER_BASE = CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET; -parameter CV_VP_FENCEI_TAMPER_BASE = CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET; - `endif // __UVME_CV32E40S_CONSTANTS_SV__ diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_core_cntrl_if.sv b/cv32e40s/env/uvme/uvme_cv32e40s_core_cntrl_if.sv index 6a94f9f479..6839c9116b 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_core_cntrl_if.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_core_cntrl_if.sv @@ -1,13 +1,14 @@ /** * Quasi-static core control signals. */ -interface uvme_cv32e40s_core_cntrl_if +interface uvme_cv32e40s_core_cntrl_if_t import uvm_pkg::*; import cv32e40s_pkg::*; (); logic clk; logic fetch_en; + logic wu_wfe; logic scan_cg_en; logic [31:0] boot_addr; @@ -16,10 +17,14 @@ interface uvme_cv32e40s_core_cntrl_if logic [31:0] dm_exception_addr; logic [31:0] nmi_addr; logic [31:0] mhartid; - logic [31:0] mimpid; + logic [3:0] mimpid_patch; logic [31:0] num_mhpmcounters; - pma_region_t pma_cfg[]; + `ifndef FORMAL + pma_cfg_t pma_cfg[]; + `else + pma_cfg_t pma_cfg[16]; + `endif cv32e40s_pkg::b_ext_e b_ext; // Testcase asserts this to load memory (not really a core control signal) @@ -27,6 +32,7 @@ interface uvme_cv32e40s_core_cntrl_if clocking drv_cb @(posedge clk); output fetch_en; + output wu_wfe; endclocking : drv_cb -endinterface : uvme_cv32e40s_core_cntrl_if +endinterface : uvme_cv32e40s_core_cntrl_if_t diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_core_sb.sv b/cv32e40s/env/uvme/uvme_cv32e40s_core_sb.sv index 5582aac524..9d9674f423 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_core_sb.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_core_sb.sv @@ -49,7 +49,7 @@ class uvme_cv32e40s_core_sb_c extends uvm_scoreboard; int unsigned csr_checked_cnt; // Analysis exports - uvm_analysis_imp_core_sb_rvfi_instr#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN), uvme_cv32e40s_core_sb_c) rvfi_instr_export; + uvm_analysis_imp_core_sb_rvfi_instr#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN), uvme_cv32e40s_core_sb_c) rvfi_instr_imp; uvm_analysis_imp_core_sb_rvvi_state#(uvma_rvvi_state_seq_item_c#(ILEN,XLEN), uvme_cv32e40s_core_sb_c) rvvi_state_export; `uvm_component_utils_begin(uvme_cv32e40s_core_sb_c) @@ -129,7 +129,7 @@ function uvme_cv32e40s_core_sb_c::new(string name="uvme_cv32e40s_core_sb", uvm_c super.new(name, parent); - rvfi_instr_export = new("rvfi_instr_export", this); + rvfi_instr_imp = new("rvfi_instr_imp", this); rvvi_state_export = new("rvvi_state_export", this); endfunction : new @@ -187,9 +187,19 @@ function void uvme_cv32e40s_core_sb_c::pre_abort(); endfunction : pre_abort function void uvme_cv32e40s_core_sb_c::print_instr_checked_stats(); - `uvm_info("CORESB", $sformatf("checked %0d instruction retirements", pc_checked_cnt), UVM_NONE); - `uvm_info("CORESB", $sformatf("checked %0d GPR updates", gpr_checked_cnt), UVM_NONE); - `uvm_info("CORESB", $sformatf("checked %0d CSRs", csr_checked_cnt), UVM_NONE); + if ($test$plusargs("USE_ISS")) begin + if ((pc_checked_cnt > 0) && cfg.scoreboarding_enabled) begin + `uvm_info("CORESB", $sformatf("checked %0d instruction retirements", pc_checked_cnt), UVM_NONE) + `uvm_info("CORESB", $sformatf("checked %0d GPR updates", gpr_checked_cnt), UVM_NONE) + `uvm_info("CORESB", $sformatf("checked %0d CSRs", csr_checked_cnt), UVM_NONE) + end + else begin + `uvm_error("CORESB", "No Instructions checked!") + end + end + else begin + `uvm_info("CORESB", "ISS scoreboard disabled for this test.", UVM_NONE) + end endfunction : print_instr_checked_stats function void uvme_cv32e40s_core_sb_c::write_core_sb_rvfi_instr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr); @@ -306,7 +316,7 @@ function void uvme_cv32e40s_core_sb_c::check_instr(uvma_rvfi_instr_seq_item_c#(I end // CHECK: insn - if (!rvfi_instr.trap) begin + if (!rvfi_instr.trap.trap) begin if (rvfi_instr.insn != rvvi_state.insn) begin `uvm_error("CORESB", $sformatf("INSN Mismatch, order: %0d, rvfi.pc = 0x%08x, rvfi.insn = 0x%08x, rvvi.insn = 0x%08x", rvfi_instr.order, rvfi_instr.pc_rdata, rvfi_instr.insn, rvvi_state.insn)); @@ -323,15 +333,16 @@ endfunction : check_instr function void uvme_cv32e40s_core_sb_c::check_gpr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - // gpt_checked_cnt represents the GPR "updates" checked, so skip writes to x0 - if (rvfi_instr.rd1_addr !=0 || rvfi_instr.rd2_addr != 0) + + if (rvfi_instr.gpr_wmask[31:1] != 0) begin gpr_checked_cnt++; + end - // Update the local register map - if (rvfi_instr.rd1_addr != 0) - x[rvfi_instr.rd1_addr] = rvfi_instr.rd1_wdata; - if (rvfi_instr.rd2_addr != 0) - x[rvfi_instr.rd2_addr] = rvfi_instr.rd2_wdata; + for (int i = 1; i < 32; i++) begin + if (rvfi_instr.gpr_wmask[i]) begin + x[i] = rvfi_instr.get_gpr_wdata(i); + end + end for (int i = 0; i < 32; i++) begin if (x[i] != rvvi_state.x[i]) begin @@ -343,6 +354,7 @@ function void uvme_cv32e40s_core_sb_c::check_gpr(uvma_rvfi_instr_seq_item_c#(ILE end end + endfunction : check_gpr function void uvme_cv32e40s_core_sb_c::check_csr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_env.sv b/cv32e40s/env/uvme/uvme_cv32e40s_env.sv index dd8136e744..c164d9ac74 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_env.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_env.sv @@ -33,20 +33,38 @@ class uvme_cv32e40s_env_c extends uvm_env; uvme_cv32e40s_cov_model_c cov_model; uvme_cv32e40s_prd_c predictor; uvme_cv32e40s_sb_c sb; - uvme_cv32e40s_core_sb_c core_sb; uvme_cv32e40s_buserr_sb_c buserr_sb; uvme_cv32e40s_vsqr_c vsequencer; // Agents - uvma_cv32e40s_core_cntrl_agent_c core_cntrl_agent; - uvma_isacov_agent_c#(ILEN,XLEN) isacov_agent; - uvma_clknrst_agent_c clknrst_agent; - uvma_interrupt_agent_c interrupt_agent; - uvma_debug_agent_c debug_agent; - uvma_obi_memory_agent_c obi_memory_instr_agent; - uvma_obi_memory_agent_c obi_memory_data_agent ; + uvma_cv32e40s_core_cntrl_agent_c core_cntrl_agent; + uvma_isacov_agent_c#(ILEN,XLEN) isacov_agent; + uvma_clknrst_agent_c clknrst_agent; + uvma_interrupt_agent_c interrupt_agent; + uvma_clic_agent_c#(CORE_PARAM_CLIC_ID_WIDTH) clic_agent; + uvma_wfe_wu_agent_c wfe_wu_agent; + uvma_debug_agent_c debug_agent; + uvma_obi_memory_agent_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + ) obi_memory_instr_agent; + uvma_obi_memory_agent_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) obi_memory_data_agent; uvma_rvfi_agent_c#(ILEN,XLEN) rvfi_agent; - uvma_rvvi_agent_c#(ILEN,XLEN) rvvi_agent; uvma_fencei_agent_c fencei_agent; uvma_pma_agent_c#(ILEN,XLEN) pma_agent; @@ -125,11 +143,6 @@ class uvme_cv32e40s_env_c extends uvm_env; */ extern virtual function void connect_predictor(); - /** - * Connects the RVFI to the RVVI for step and compare feedback - */ - extern virtual function void connect_rvfi_rvvi(); - /** * Connects scoreboards components to agents/predictor. */ @@ -148,7 +161,16 @@ class uvme_cv32e40s_env_c extends uvm_env; /** * Install virtual peripheral sequences to the OBI data slave sequence */ - extern virtual function void install_vp_register_seqs(uvma_obi_memory_slv_seq_c data_slv_seq); + extern virtual function void install_vp_register_seqs(uvma_obi_memory_slv_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )data_slv_seq); endclass : uvme_cv32e40s_env_c @@ -204,15 +226,6 @@ function void uvme_cv32e40s_env_c::connect_phase(uvm_phase phase); super.connect_phase(phase); if (cfg.enabled) begin - if (cfg.rvvi_cfg.is_active == UVM_ACTIVE) begin - uvma_rvvi_ovpsim_agent_c rvvi_ovpsim_agent; - - connect_rvfi_rvvi(); - if (!$cast(rvvi_ovpsim_agent, rvvi_agent)) begin - `uvm_fatal("UVMECV32E40SENV", "Could not cast agent to rvvi_ovpsim_agent"); - end - rvvi_ovpsim_agent.set_clknrst_sequencer(clknrst_agent.sequencer); - end if (cfg.scoreboarding_enabled) begin connect_predictor (); @@ -239,26 +252,80 @@ endfunction : end_of_elaboration_phase task uvme_cv32e40s_env_c::run_phase(uvm_phase phase); - uvma_obi_memory_fw_preload_seq_c fw_preload_seq; - uvma_obi_memory_slv_seq_c instr_slv_seq; - uvma_obi_memory_slv_seq_c data_slv_seq; + uvma_obi_memory_fw_preload_seq_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + ) fw_preload_seq; + uvma_obi_memory_slv_seq_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + ) instr_slv_seq; + uvma_obi_memory_slv_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) data_slv_seq; if (cfg.is_active) begin fork begin : spawn_obi_instr_fw_preload_thread - fw_preload_seq = uvma_obi_memory_fw_preload_seq_c::type_id::create("fw_preload_seq"); + fw_preload_seq = uvma_obi_memory_fw_preload_seq_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + )::type_id::create("fw_preload_seq"); void'(fw_preload_seq.randomize()); fw_preload_seq.start(obi_memory_instr_agent.sequencer); end begin : obi_instr_slv_thread - instr_slv_seq = uvma_obi_memory_slv_seq_c::type_id::create("instr_slv_seq"); + instr_slv_seq = uvma_obi_memory_slv_seq_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + )::type_id::create("instr_slv_seq"); void'(instr_slv_seq.randomize()); instr_slv_seq.start(obi_memory_instr_agent.sequencer); end begin : obi_data_slv_thread - data_slv_seq = uvma_obi_memory_slv_seq_c::type_id::create("data_slv_seq"); + data_slv_seq = uvma_obi_memory_slv_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::type_id::create("data_slv_seq"); install_vp_register_seqs(data_slv_seq); @@ -273,30 +340,44 @@ endtask : run_phase function void uvme_cv32e40s_env_c::retrieve_vifs(); - if (!uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if)::get(this, "", "vp_status_vif", cntxt.vp_status_vif)) begin + if (!uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if_t)::get(this, "", "vp_status_vif", cntxt.vp_status_vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vp_status_vif handle of type %s in uvm_config_db", $typename(cntxt.vp_status_vif))) end else begin `uvm_info("VIF", $sformatf("Found vp_status_vif handle of type %s in uvm_config_db", $typename(cntxt.vp_status_vif)), UVM_DEBUG) end - if (!uvm_config_db#(virtual uvma_interrupt_if)::get(this, "", "intr_vif", cntxt.intr_vif)) begin + if (!uvm_config_db#(virtual uvma_interrupt_if_t)::get(this, "", "intr_vif", cntxt.intr_vif)) begin `uvm_fatal("VIF", $sformatf("Could not find intr_vif handle of type %s in uvm_config_db", $typename(cntxt.intr_vif))) end else begin `uvm_info("VIF", $sformatf("Found intr_vif handle of type %s in uvm_config_db", $typename(cntxt.intr_vif)), UVM_DEBUG) end - if (!uvm_config_db#(virtual uvma_debug_if)::get(this, "", "debug_vif", cntxt.debug_vif)) begin + if (!uvm_config_db#(virtual uvma_clic_if_t#(.CLIC_ID_WIDTH(uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH)))::get(this, "", "clic_vif", cntxt.clic_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find clic_vif handle of type %s in uvm_config_db", $typename(cntxt.clic_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found clic_vif handle of type %s in uvm_config_db", $typename(cntxt.clic_vif)), UVM_DEBUG) + end + + if (!uvm_config_db#(virtual uvma_wfe_wu_if_t)::get(this, "", "wfe_wu_vif", cntxt.wfe_wu_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find wfe_wu_vif handle of type %s in uvm_config_db", $typename(cntxt.wfe_wu_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found wfe_wu_vif handle of type %s in uvm_config_db", $typename(cntxt.wfe_wu_vif)), UVM_DEBUG) + end + + if (!uvm_config_db#(virtual uvma_debug_if_t)::get(this, "", "debug_vif", cntxt.debug_vif)) begin `uvm_fatal("VIF", $sformatf("Could not find debug_vif handle of type %s in uvm_config_db", $typename(cntxt.debug_vif))) end else begin `uvm_info("VIF", $sformatf("Found debug_vif handle of type %s in uvm_config_db", $typename(cntxt.debug_vif)), UVM_DEBUG) end - void'(uvm_config_db#(virtual uvmt_cv32e40s_debug_cov_assert_if)::get(this, "", "debug_cov_vif", cntxt.debug_cov_vif)); + void'(uvm_config_db#(virtual uvmt_cv32e40s_debug_cov_assert_if_t)::get(this, "", "debug_cov_vif", cntxt.debug_cov_vif)); if (cntxt.debug_cov_vif == null) begin - `uvm_fatal("CNTXT", $sformatf("No uvmt_cv32e40s_debug_cov_assert_if found in config database")) + `uvm_fatal("CNTXT", $sformatf("No uvmt_cv32e40s_debug_cov_assert_if_t found in config database")) end endfunction: retrieve_vifs @@ -310,12 +391,13 @@ function void uvme_cv32e40s_env_c::assign_cfg(); uvm_config_db#(uvma_debug_cfg_c)::set(this, "debug_agent", "cfg", cfg.debug_cfg); uvm_config_db#(uvma_fencei_cfg_c)::set(this, "fencei_agent", "cfg", cfg.fencei_cfg); uvm_config_db#(uvma_interrupt_cfg_c)::set(this, "*interrupt_agent", "cfg", cfg.interrupt_cfg); + uvm_config_db#(uvma_clic_cfg_c)::set(this, "*clic_agent", "cfg", cfg.clic_cfg); + uvm_config_db#(uvma_wfe_wu_cfg_c)::set(this, "*wfe_wu_agent", "cfg", cfg.wfe_wu_cfg); uvm_config_db#(uvma_isacov_cfg_c)::set(this, "*isacov_agent", "cfg", cfg.isacov_cfg); uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "obi_memory_data_agent", "cfg", cfg.obi_memory_data_cfg); uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "obi_memory_instr_agent", "cfg", cfg.obi_memory_instr_cfg); uvm_config_db#(uvma_pma_cfg_c)::set(this, "pma_agent", "cfg", cfg.pma_cfg); uvm_config_db#(uvma_rvfi_cfg_c#(ILEN,XLEN))::set(this, "rvfi_agent", "cfg", cfg.rvfi_cfg); - uvm_config_db#(uvma_rvvi_cfg_c#(ILEN,XLEN))::set(this, "rvvi_agent", "cfg", cfg.rvvi_cfg); endfunction: assign_cfg @@ -329,27 +411,65 @@ function void uvme_cv32e40s_env_c::assign_cntxt(); uvm_config_db#(uvma_debug_cntxt_c)::set(this, "debug_agent", "cntxt", cntxt.debug_cntxt); uvm_config_db#(uvma_fencei_cntxt_c)::set(this, "fencei_agent", "cntxt", cntxt.fencei_cntxt); uvm_config_db#(uvma_interrupt_cntxt_c)::set(this, "interrupt_agent", "cntxt", cntxt.interrupt_cntxt); - uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "obi_memory_data_agent", "cntxt", cntxt.obi_memory_data_cntxt); - uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "obi_memory_instr_agent", "cntxt", cntxt.obi_memory_instr_cntxt); + uvm_config_db#(uvma_clic_cntxt_c#(CORE_PARAM_CLIC_ID_WIDTH))::set(this, "clic_agent", "cntxt", cntxt.clic_cntxt); + uvm_config_db#(uvma_wfe_wu_cntxt_c)::set(this, "wfe_wu_agent", "cntxt", cntxt.wfe_wu_cntxt); + uvm_config_db#(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ))::set(this, "obi_memory_data_agent", "cntxt", cntxt.obi_memory_data_cntxt); + uvm_config_db#(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + ))::set(this, "obi_memory_instr_agent", "cntxt", cntxt.obi_memory_instr_cntxt); uvm_config_db#(uvma_rvfi_cntxt_c#(ILEN,XLEN))::set(this, "rvfi_agent", "cntxt", cntxt.rvfi_cntxt); - uvm_config_db#(uvma_rvvi_cntxt_c#(ILEN,XLEN))::set(this, "rvvi_agent", "cntxt", cntxt.rvvi_cntxt); endfunction: assign_cntxt function void uvme_cv32e40s_env_c::create_agents(); - core_cntrl_agent = uvma_cv32e40s_core_cntrl_agent_c::type_id::create("core_cntrl_agent", this); - isacov_agent = uvma_isacov_agent_c#(ILEN,XLEN)::type_id::create("isacov_agent", this); - clknrst_agent = uvma_clknrst_agent_c::type_id::create("clknrst_agent", this); - interrupt_agent = uvma_interrupt_agent_c::type_id::create("interrupt_agent", this); - debug_agent = uvma_debug_agent_c::type_id::create("debug_agent", this); - obi_memory_instr_agent = uvma_obi_memory_agent_c::type_id::create("obi_memory_instr_agent", this); - obi_memory_data_agent = uvma_obi_memory_agent_c::type_id::create("obi_memory_data_agent", this); - rvfi_agent = uvma_rvfi_agent_c#(ILEN,XLEN)::type_id::create("rvfi_agent", this); - rvvi_agent = uvma_rvvi_ovpsim_agent_c#(ILEN,XLEN)::type_id::create("rvvi_agent", this); - fencei_agent = uvma_fencei_agent_c::type_id::create("fencei_agent", this); - pma_agent = uvma_pma_agent_c#(ILEN,XLEN)::type_id::create("pma_agent", this); + core_cntrl_agent = uvma_cv32e40s_core_cntrl_agent_c::type_id::create("core_cntrl_agent", this); + isacov_agent = uvma_isacov_agent_c#(ILEN,XLEN)::type_id::create("isacov_agent", this); + clknrst_agent = uvma_clknrst_agent_c::type_id::create("clknrst_agent", this); + interrupt_agent = uvma_interrupt_agent_c::type_id::create("interrupt_agent", this); + clic_agent = uvma_clic_agent_c#(CORE_PARAM_CLIC_ID_WIDTH)::type_id::create("clic_agent", this); + wfe_wu_agent = uvma_wfe_wu_agent_c::type_id::create("wfe_wu_agent", this); + debug_agent = uvma_debug_agent_c::type_id::create("debug_agent", this); + obi_memory_instr_agent = uvma_obi_memory_agent_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + )::type_id::create("obi_memory_instr_agent", this); + obi_memory_data_agent = uvma_obi_memory_agent_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::type_id::create("obi_memory_data_agent", this); + rvfi_agent = uvma_rvfi_agent_c#(ILEN,XLEN)::type_id::create("rvfi_agent", this); + fencei_agent = uvma_fencei_agent_c::type_id::create("fencei_agent", this); + pma_agent = uvma_pma_agent_c#(ILEN,XLEN)::type_id::create("pma_agent", this); endfunction: create_agents @@ -359,7 +479,6 @@ function void uvme_cv32e40s_env_c::create_env_components(); if (cfg.scoreboarding_enabled) begin predictor = uvme_cv32e40s_prd_c::type_id::create("predictor", this); sb = uvme_cv32e40s_sb_c::type_id::create("sb" , this); - core_sb = uvme_cv32e40s_core_sb_c::type_id::create("core_sb", this); end if (cfg.buserr_scoreboarding_enabled) begin @@ -386,24 +505,8 @@ function void uvme_cv32e40s_env_c::connect_predictor(); endfunction: connect_predictor -function void uvme_cv32e40s_env_c::connect_rvfi_rvvi(); - - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(rvvi_agent.sequencer.rvfi_instr_export); - end - -endfunction : connect_rvfi_rvvi - function void uvme_cv32e40s_env_c::connect_scoreboard(); - // Connect the CORE Scoreboard (but only if the ISS is running) - if (cfg.use_iss) begin - rvvi_agent.state_mon_ap.connect(core_sb.rvvi_state_export); - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(core_sb.rvfi_instr_export); - end - end - // Connect the bus error scoreboard if (cfg.buserr_scoreboarding_enabled) begin obi_memory_data_agent.mon_ap.connect(buserr_sb.obid); @@ -430,8 +533,9 @@ function void uvme_cv32e40s_env_c::connect_coverage_model(); obi_memory_data_agent.mon_ap.connect(pma_agent.monitor.obi_d_export); foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(isacov_agent.monitor.rvfi_instr_export); + rvfi_agent.instr_mon_ap[i].connect(isacov_agent.monitor.rvfi_instr_imp); rvfi_agent.instr_mon_ap[i].connect(cov_model.interrupt_covg.interrupt_mon_export); + //rvfi_agent.instr_mon_ap[i].connect(cov_model.clic_covg.clic_mon_export); // TODO: silabs-hfegran rvfi_agent.instr_mon_ap[i].connect(pma_agent.monitor.rvfi_instr_export); end @@ -440,26 +544,84 @@ endfunction: connect_coverage_model function void uvme_cv32e40s_env_c::assemble_vsequencer(); - vsequencer.clknrst_sequencer = clknrst_agent.sequencer; - vsequencer.interrupt_sequencer = interrupt_agent.sequencer; - vsequencer.debug_sequencer = debug_agent.sequencer; + vsequencer.clknrst_sequencer = clknrst_agent.sequencer; + vsequencer.interrupt_sequencer = interrupt_agent.sequencer; + vsequencer.clic_sequencer = clic_agent.sequencer; + vsequencer.wfe_wu_sequencer = wfe_wu_agent.sequencer; + vsequencer.debug_sequencer = debug_agent.sequencer; vsequencer.obi_memory_instr_sequencer = obi_memory_instr_agent.sequencer; - vsequencer.obi_memory_data_sequencer = obi_memory_data_agent .sequencer; + vsequencer.obi_memory_data_sequencer = obi_memory_data_agent.sequencer; endfunction: assemble_vsequencer -function void uvme_cv32e40s_env_c::install_vp_register_seqs(uvma_obi_memory_slv_seq_c data_slv_seq); - - void'(data_slv_seq.register_vp_vseq("vp_virtual_printer", CV_VP_VIRTUAL_PRINTER_BASE, uvma_obi_memory_vp_virtual_printer_seq_c::get_type())); - - void'(data_slv_seq.register_vp_vseq("vp_rand_num", CV_VP_RANDOM_NUM_BASE, uvma_obi_memory_vp_rand_num_seq_c::get_type())); - - void'(data_slv_seq.register_vp_vseq("vp_cycle_counter", CV_VP_CYCLE_COUNTER_BASE, uvma_obi_memory_vp_cycle_counter_seq_c::get_type())); +function void uvme_cv32e40s_env_c::install_vp_register_seqs(uvma_obi_memory_slv_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) +) data_slv_seq); + + void'(data_slv_seq.register_vp_vseq("vp_virtual_printer", CV_VP_VIRTUAL_PRINTER_BASE, uvma_obi_memory_vp_virtual_printer_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::get_type())); + + void'(data_slv_seq.register_vp_vseq("vp_rand_num", CV_VP_RANDOM_NUM_BASE, uvma_obi_memory_vp_rand_num_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) ::get_type())); + + void'(data_slv_seq.register_vp_vseq("vp_cycle_counter", CV_VP_CYCLE_COUNTER_BASE, uvma_obi_memory_vp_cycle_counter_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) ::get_type())); begin - uvma_obi_memory_vp_directed_slv_resp_seq_c#(2) vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_directed_slv_resp", CV_VP_OBI_SLV_RESP_BASE, uvma_obi_memory_vp_directed_slv_resp_seq_c#(2)::get_type()))) begin + uvma_obi_memory_vp_directed_slv_resp_seq_c#( + .OBI_PERIPHS(2), + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) vp_seq; + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_directed_slv_resp", CV_VP_OBI_SLV_RESP_BASE, uvma_obi_memory_vp_directed_slv_resp_seq_c#( + .OBI_PERIPHS(2), + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::get_type()))) begin `uvm_fatal("CV32E40SVPSEQ", $sformatf("Could not cast vp_directed_slv_resp correctly")); end vp_seq.obi_cfg[0] = cfg.obi_memory_instr_cfg; @@ -467,40 +629,130 @@ function void uvme_cv32e40s_env_c::install_vp_register_seqs(uvma_obi_memory_slv_ end begin - uvme_cv32e40s_vp_sig_writer_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_sig_writer", CV_VP_SIG_WRITER_BASE, uvme_cv32e40s_vp_sig_writer_seq_c::get_type()))) begin + uvme_cv32e40s_vp_sig_writer_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) vp_seq; + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_sig_writer", CV_VP_SIG_WRITER_BASE, uvme_cv32e40s_vp_sig_writer_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::get_type()))) begin `uvm_fatal("CV32E40SVPSEQ", $sformatf("Could not cast vp_sig_writes correctly")); end vp_seq.cv32e40s_cntxt = cntxt; end begin - uvme_cv32e40s_vp_status_flags_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", CV_VP_STATUS_FLAGS_BASE, uvme_cv32e40s_vp_status_flags_seq_c::get_type()))) begin + uvme_cv32e40s_vp_status_flags_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) vp_seq; + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", CV_VP_STATUS_FLAGS_BASE, uvme_cv32e40s_vp_status_flags_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::get_type()))) begin `uvm_fatal("CV32E40SVPSEQ", $sformatf("Could not cast vp_status_flags correctly")); end vp_seq.cv32e40s_cntxt = cntxt; end begin - uvme_cv32e40s_vp_interrupt_timer_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_interrupt_timer", CV_VP_INTR_TIMER_BASE, uvme_cv32e40s_vp_interrupt_timer_seq_c::get_type()))) begin + uvme_cv32e40s_vp_interrupt_timer_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )vp_seq; + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_interrupt_timer", CV_VP_INTR_TIMER_BASE, uvme_cv32e40s_vp_interrupt_timer_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::get_type()))) begin `uvm_fatal("CV32E40SVPSEQ", $sformatf("Could not cast vp_interrupt_timer correctly")); end vp_seq.cv32e40s_cntxt = cntxt; end begin - uvme_cv32e40s_vp_debug_control_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_debug_control", CV_VP_DEBUG_CONTROL_BASE, uvme_cv32e40s_vp_debug_control_seq_c::get_type()))) begin + uvme_cv32e40s_vp_debug_control_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )vp_seq; + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_debug_control", CV_VP_DEBUG_CONTROL_BASE, uvme_cv32e40s_vp_debug_control_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::get_type()))) begin `uvm_fatal("CV32E40SVPSEQ", $sformatf("Could not cast vp_debug_control correctly")); end vp_seq.cv32e40s_cntxt = cntxt; end begin - uvme_cv32e40s_vp_fencei_tamper_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_fencei_tamper", CV_VP_FENCEI_TAMPER_BASE, uvme_cv32e40s_vp_fencei_tamper_seq_c::get_type()))) begin + uvme_cv32e40s_vp_fencei_tamper_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) vp_seq; + if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_fencei_tamper", CV_VP_FENCEI_TAMPER_BASE, uvme_cv32e40s_vp_fencei_tamper_seq_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + )::get_type()))) begin `uvm_fatal("CV32E40SVPSEQ", $sformatf("Could not cast vp_fencei_tamper correctly")); end vp_seq.cv32e40s_cntxt = cntxt; diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv b/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv index ac3ada1858..bbe32f5ff2 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv @@ -34,20 +34,22 @@ */ package uvme_cv32e40s_pkg; - import uvm_pkg ::*; - import uvml_hrtbt_pkg ::*; - import uvml_sb_pkg ::*; - import uvml_trn_pkg ::*; - import uvml_mem_pkg ::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import uvm_pkg::*; + import uvml_hrtbt_pkg::*; + import uvml_sb_pkg::*; + import uvml_trn_pkg::*; + import uvml_mem_pkg::*; import uvma_core_cntrl_pkg::*; import uvma_isacov_pkg::*; import uvma_clknrst_pkg::*; + import uvma_clic_pkg::*; + import uvma_wfe_wu_pkg::*; import uvma_interrupt_pkg::*; import uvma_debug_pkg::*; import uvma_obi_memory_pkg::*; import uvma_rvfi_pkg::*; - import uvma_rvvi_pkg::*; - import uvma_rvvi_ovpsim_pkg::*; import uvma_fencei_pkg::*; import uvma_pma_pkg::*; @@ -69,15 +71,19 @@ package uvme_cv32e40s_pkg; // Virtual sequences `include "uvme_cv32e40s_base_vseq.sv" `include "uvme_cv32e40s_reset_vseq.sv" + `include "uvme_cv32e40s_nmi_timeout_vseq.sv" + `include "uvme_cv32e40s_irq_ss_timeout_vseq.sv" `include "uvme_cv32e40s_vp_debug_control_seq.sv" `include "uvme_cv32e40s_vp_interrupt_timer_seq.sv" `include "uvme_cv32e40s_vp_sig_writer_seq.sv" `include "uvme_cv32e40s_vp_status_flags_seq.sv" `include "uvme_cv32e40s_vp_fencei_tamper_seq.sv" `include "uvme_cv32e40s_interrupt_noise_vseq.sv" + `include "uvme_cv32e40s_clic_noise_vseq.sv" `include "uvme_cv32e40s_vseq_lib.sv" `include "uvme_cv32e40s_core_cntrl_base_seq.sv" `include "uvme_cv32e40s_core_cntrl_fetch_toggle_seq.sv" + `include "uvme_cv32e40s_wu_wfe_noise_vseq.sv" `include "uvme_cv32e40s_random_debug_vseq.sv" `include "uvme_cv32e40s_random_debug_reset_vseq.sv" `include "uvme_cv32e40s_random_debug_bootset_vseq.sv" @@ -91,7 +97,6 @@ package uvme_cv32e40s_pkg; `include "uvme_counters_covg.sv" `include "uvme_cv32e40s_cov_model.sv" `include "uvme_cv32e40s_sb.sv" - `include "uvme_cv32e40s_core_sb.sv" `include "uvme_cv32e40s_buserr_sb.sv" `include "uvme_cv32e40s_vsqr.sv" `include "uvme_cv32e40s_env.sv" diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_tdefs.sv b/cv32e40s/env/uvme/uvme_cv32e40s_tdefs.sv index 577f058ecd..e6c20b2ba0 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_tdefs.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_tdefs.sv @@ -21,10 +21,4 @@ `define __UVME_CV32E40S_TDEFS_SV__ -typedef enum { - FETCH_CONSTANT, - FETCH_INITIAL_DELAY_CONSTANT, - FETCH_RANDOM_TOGGLE -} fetch_toggle_t; - `endif // __UVME_CV32E40S_TDEFS_SV__ diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_vsqr.sv b/cv32e40s/env/uvme/uvme_cv32e40s_vsqr.sv index 786b56c766..a78473555e 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_vsqr.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_vsqr.sv @@ -32,11 +32,31 @@ class uvme_cv32e40s_vsqr_c extends uvm_sequencer#( uvme_cv32e40s_cntxt_c cntxt; // Sequencer handles - uvma_clknrst_sqr_c clknrst_sequencer; - uvma_interrupt_sqr_c interrupt_sequencer; - uvma_debug_sqr_c debug_sequencer; - uvma_obi_memory_sqr_c obi_memory_instr_sequencer; - uvma_obi_memory_sqr_c obi_memory_data_sequencer ; + uvma_clknrst_sqr_c clknrst_sequencer; + uvma_interrupt_sqr_c interrupt_sequencer; + uvma_clic_sqr_c#(CORE_PARAM_CLIC_ID_WIDTH) clic_sequencer; + uvma_wfe_wu_sqr_c wfe_wu_sequencer; + uvma_debug_sqr_c debug_sequencer; + uvma_obi_memory_sqr_c#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + ) obi_memory_instr_sequencer; + uvma_obi_memory_sqr_c#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ) obi_memory_data_sequencer ; `uvm_component_utils_begin(uvme_cv32e40s_vsqr_c) `uvm_field_object(cfg , UVM_DEFAULT) diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_interrupt_noise_vseq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_clic_noise_vseq.sv similarity index 60% rename from cv32e40x/env/uvme/vseq/uvme_cv32e40x_interrupt_noise_vseq.sv rename to cv32e40s/env/uvme/vseq/uvme_cv32e40s_clic_noise_vseq.sv index f6370e357a..3fdb8737cc 100644 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_interrupt_noise_vseq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_clic_noise_vseq.sv @@ -14,14 +14,14 @@ // limitations under the License. -`ifndef __UVME_CV32E40X_INTERRUPT_NOISE_SV__ -`define __UVME_CV32E40X_INTERRUPT_NOISE_SV__ +`ifndef __UVME_CV32E40S_CLIC_NOISE_SV__ +`define __UVME_CV32E40S_CLIC_NOISE_SV__ /** * Virtual sequence responsible for starting the system clock and issuing * the initial reset pulse to the DUT. */ -class uvme_cv32e40x_interrupt_noise_c extends uvme_cv32e40x_base_vseq_c; +class uvme_cv32e40s_clic_noise_c extends uvme_cv32e40s_base_vseq_c; rand int unsigned short_delay_wgt; rand int unsigned med_delay_wgt; @@ -32,7 +32,7 @@ class uvme_cv32e40x_interrupt_noise_c extends uvme_cv32e40x_base_vseq_c; rand bit [31:0] reserved_irq_mask; - `uvm_object_utils_begin(uvme_cv32e40x_interrupt_noise_c) + `uvm_object_utils_begin(uvme_cv32e40s_clic_noise_c) `uvm_object_utils_end constraint default_delay_c { @@ -66,47 +66,45 @@ class uvme_cv32e40x_interrupt_noise_c extends uvme_cv32e40x_base_vseq_c; /** * Default constructor. */ - extern function new(string name="uvme_cv32e40x_interrupt_noise"); + extern function new(string name="uvme_cv32e40s_clic_noise"); /** * Starts the clock, waits, then resets the DUT. */ extern virtual task body(); extern virtual task rand_delay(); -endclass : uvme_cv32e40x_interrupt_noise_c +endclass : uvme_cv32e40s_clic_noise_c -function uvme_cv32e40x_interrupt_noise_c::new(string name="uvme_cv32e40x_interrupt_noise"); +function uvme_cv32e40s_clic_noise_c::new(string name="uvme_cv32e40s_clic_noise"); super.new(name); endfunction : new -task uvme_cv32e40x_interrupt_noise_c::rand_delay(); +task uvme_cv32e40s_clic_noise_c::rand_delay(); randcase - short_delay_wgt: repeat($urandom_range(100,1)) @(cntxt.interrupt_cntxt.vif.drv_cb); - med_delay_wgt: repeat($urandom_range(500,100)) @(cntxt.interrupt_cntxt.vif.drv_cb); - long_delay_wgt: repeat($urandom_range(10_000,5_000)) @(cntxt.interrupt_cntxt.vif.drv_cb); + short_delay_wgt: repeat($urandom_range(100,1)) @(cntxt.clic_cntxt.vif.drv_cb); + med_delay_wgt: repeat($urandom_range(500,100)) @(cntxt.clic_cntxt.vif.drv_cb); + long_delay_wgt: repeat($urandom_range(10_000,5_000)) @(cntxt.clic_cntxt.vif.drv_cb); endcase endtask : rand_delay -task uvme_cv32e40x_interrupt_noise_c::body(); +task uvme_cv32e40s_clic_noise_c::body(); fork begin : gen_assert_until_ack - repeat (initial_delay_assert_until_ack) @(cntxt.interrupt_cntxt.vif.drv_cb); + repeat (initial_delay_assert_until_ack) @(cntxt.clic_cntxt.vif.drv_cb); - while(1) begin - uvma_interrupt_seq_item_c irq_req; + forever begin + uvma_clic_seq_item_c irq_req; - `uvm_create_on(irq_req, p_sequencer.interrupt_sequencer); + `uvm_create_on(irq_req, p_sequencer.clic_sequencer); start_item(irq_req); - irq_req.default_repeat_count_c.constraint_mode(0); assert(irq_req.randomize() with { - action == UVMA_INTERRUPT_SEQ_ITEM_ACTION_ASSERT_UNTIL_ACK; + action == UVMA_CLIC_SEQ_ITEM_ACTION_ASSERT; repeat_count dist { 1 :/ 9, [2:3] :/ 1 }; - (irq_mask & local::reserved_irq_mask) == 0; }); finish_item(irq_req); @@ -117,14 +115,13 @@ task uvme_cv32e40x_interrupt_noise_c::body(); begin : gen_assert - repeat (initial_delay_assert) @(cntxt.interrupt_cntxt.vif.drv_cb); + repeat (initial_delay_assert) @(cntxt.clic_cntxt.vif.drv_cb); - while(1) begin - uvma_interrupt_seq_item_c irq_req; + forever begin + uvma_clic_seq_item_c irq_req; - `uvm_do_on_with(irq_req, p_sequencer.interrupt_sequencer, { - action == UVMA_INTERRUPT_SEQ_ITEM_ACTION_DEASSERT; - (irq_mask & local::reserved_irq_mask) == 0; + `uvm_do_on_with(irq_req, p_sequencer.clic_sequencer, { + action == UVMA_CLIC_SEQ_ITEM_ACTION_ASSERT; }) rand_delay(); @@ -134,14 +131,13 @@ task uvme_cv32e40x_interrupt_noise_c::body(); begin : gen_deassert - repeat (initial_delay_deassert) @(cntxt.interrupt_cntxt.vif.drv_cb); + repeat (initial_delay_deassert) @(cntxt.clic_cntxt.vif.drv_cb); - while(1) begin - uvma_interrupt_seq_item_c irq_req; + forever begin + uvma_clic_seq_item_c irq_req; - `uvm_do_on_with(irq_req, p_sequencer.interrupt_sequencer, { - action == UVMA_INTERRUPT_SEQ_ITEM_ACTION_ASSERT; - (irq_mask & local::reserved_irq_mask) == 0; + `uvm_do_on_with(irq_req, p_sequencer.clic_sequencer, { + action == UVMA_CLIC_SEQ_ITEM_ACTION_DEASSERT; }) rand_delay(); @@ -151,4 +147,4 @@ task uvme_cv32e40x_interrupt_noise_c::body(); join endtask : body -`endif // __UVME_CV32E40X_INTERRUPT_NOISE_SV__ +`endif // __UVME_CV32E40X_CLIC_NOISE_SV__ diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_core_cntrl_fetch_toggle_seq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_core_cntrl_fetch_toggle_seq.sv index 45906fbdfa..8eeb264cea 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_core_cntrl_fetch_toggle_seq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_core_cntrl_fetch_toggle_seq.sv @@ -24,22 +24,14 @@ class uvme_cv32e40s_fetch_toggle_seq_c extends uvme_cv32e40s_core_cntrl_base_seq rand fetch_toggle_t fetch_toggle_mode; - rand int unsigned initial_delay; - `uvm_object_utils_begin(uvme_cv32e40s_fetch_toggle_seq_c); `uvm_field_enum(fetch_toggle_t, fetch_toggle_mode, UVM_DEFAULT) - `uvm_field_int(initial_delay, UVM_DEFAULT) `uvm_object_utils_end constraint default_mode_cons { soft fetch_toggle_mode inside { FETCH_CONSTANT, FETCH_INITIAL_DELAY_CONSTANT }; } - constraint default_initial_delay { - // Wait a bit before starting - initial_delay inside {[50:200]}; - } - extern function new(string name = ""); extern virtual task body(); @@ -95,7 +87,7 @@ endtask : fetch_constant task uvme_cv32e40s_fetch_toggle_seq_c::fetch_initial_delay(); - repeat (initial_delay) @(cntxt.core_cntrl_vif.drv_cb); + repeat (cfg.fetch_toggle_initial_delay) @(cntxt.core_cntrl_vif.drv_cb); cntxt.core_cntrl_vif.drv_cb.fetch_en <= 1'b1; endtask : fetch_initial_delay diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_irq_ss_timeout_vseq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_irq_ss_timeout_vseq.sv new file mode 100644 index 0000000000..ea27e73603 --- /dev/null +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_irq_ss_timeout_vseq.sv @@ -0,0 +1,93 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +//////////////////////////////////////////////////////////////////////////////// +// Author: Henrik Fegran - henrik.fegran@silabs.com // +// // +// Virtual sequence to ensure that random tests encountering // +// a configured number of irq&single steps terminates correctly after a set // +// timeout // +// // +//////////////////////////////////////////////////////////////////////////////// +`ifndef __UVME_CV32E40S_IRQ_SS_TIMEOUT_VSEQ_SV__ +`define __UVME_CV32E40S_IRQ_SS_TIMEOUT_VSEQ_SV__ + + +/** + * Virtual sequence responsible for terminating test n cycles after an nmi + */ +class uvme_cv32e40s_irq_ss_timeout_vseq_c extends uvme_cv32e40s_base_vseq_c; + + uvme_cv32e40s_cntxt_c cv32e40s_cntxt; + + + `uvm_object_utils(uvme_cv32e40s_irq_ss_timeout_vseq_c) + + /** + * Default constructor. + */ + extern function new(string name="uvme_cv32e40s_irq_ss_timeout_vseq"); + + /** + * Waits for a configured number of instructions after an nmi. + */ + extern virtual task body(); + +endclass : uvme_cv32e40s_irq_ss_timeout_vseq_c + + +function uvme_cv32e40s_irq_ss_timeout_vseq_c::new(string name="uvme_cv32e40s_irq_ss_timeout_vseq"); + + super.new(name); + +endfunction : new + + +task uvme_cv32e40s_irq_ss_timeout_vseq_c::body(); + + let single_step_cnt = cntxt.rvfi_cntxt.instr_vif[0].single_step_cnt; + let irq_cnt = cntxt.rvfi_cntxt.instr_vif[0].irq_cnt; + let rvfi_valid = cntxt.rvfi_cntxt.instr_vif[0].rvfi_valid; + let clk = cntxt.rvfi_cntxt.instr_vif[0].clk; + + if (cntxt == null) begin + `uvm_fatal("E40SVPSTATUS", "Must initialize cntxt in virtual sequence") + end + + // terminate = ss > ss.min && irq > irq.min && ss + irq > threshold + if (cfg.irq_single_step_threshold > 0) begin + fork + forever begin + @(posedge clk) begin + if (rvfi_valid) begin + // Threshold exceeded + if (irq_cnt > cfg.irq_min_limit && + single_step_cnt > cfg.single_step_min_limit && + (single_step_cnt + irq_cnt) >= cfg.irq_single_step_threshold) + begin + `uvm_info("IRQ_SS_TIMEOUT_WATCHDOG", $sformatf("IRQ/SINGLE STEP timeout: single step count: %0d, irq count: %0d, threshold: %0d", single_step_cnt, irq_cnt, cfg.irq_single_step_threshold), UVM_LOW); + cntxt.vp_status_vif.exit_valid = 1; + cntxt.vp_status_vif.exit_value = 32'h0; + end + end + end + end + join + end + +endtask : body + + +`endif // __UVME_CV32E40S_IRQ_SS_TIMEOUT_VSEQ_SV__ diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_nmi_timeout_vseq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_nmi_timeout_vseq.sv new file mode 100644 index 0000000000..d7ed7cb4c6 --- /dev/null +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_nmi_timeout_vseq.sv @@ -0,0 +1,84 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +//////////////////////////////////////////////////////////////////////////////// +// Author: Henrik Fegran - henrik.fegran@silabs.com // +// // +// Virtual sequence to ensure that random tests encountering // +// nmi terminates correctly after a set timeout // +// // +// Usage: Set nmi_timeout_instr plusarg to non-zero value // +// // +//////////////////////////////////////////////////////////////////////////////// +`ifndef __UVME_CV32E40S_NMI_TIMEOUT_VSEQ_SV__ +`define __UVME_CV32E40S_NMI_TIMEOUT_VSEQ_SV__ + + +/** + * Virtual sequence responsible for terminating test n cycles after an nmi + */ +class uvme_cv32e40s_nmi_timeout_vseq_c extends uvme_cv32e40s_base_vseq_c; + + uvme_cv32e40s_cntxt_c cv32e40s_cntxt; + + + `uvm_object_utils(uvme_cv32e40s_nmi_timeout_vseq_c) + + /** + * Default constructor. + */ + extern function new(string name="uvme_cv32e40s_nmi_timeout_vseq"); + + /** + * Waits for a configured number of instructions after an nmi. + */ + extern virtual task body(); + +endclass : uvme_cv32e40s_nmi_timeout_vseq_c + + +function uvme_cv32e40s_nmi_timeout_vseq_c::new(string name="uvme_cv32e40s_nmi_timeout_vseq"); + + super.new(name); + +endfunction : new + + +task uvme_cv32e40s_nmi_timeout_vseq_c::body(); + + if (cntxt == null) begin + `uvm_fatal("E40SVPSTATUS", "Must initialize cntxt in virtual sequence") + end + + if (cfg.nmi_timeout_instr > 0) begin + fork + forever begin + @(posedge cntxt.rvfi_cntxt.instr_vif[0].clk) begin + if (cntxt.rvfi_cntxt.instr_vif[0].rvfi_valid) begin + if (cntxt.rvfi_cntxt.instr_vif[0].nmi_instr_cnt >= cfg.nmi_timeout_instr) begin + `uvm_info("NMI_TIMEOUT_WATCHDOG", $sformatf("NMI timeout: %0d", cntxt.rvfi_cntxt.instr_vif[0].nmi_instr_cnt), UVM_LOW); + cntxt.vp_status_vif.exit_valid = 1; + cntxt.vp_status_vif.exit_value = 32'h0; + end + end + end + end + join + end + +endtask : body + + +`endif // __UVME_CV32E40S_NMI_TIMEOUT_VSEQ_SV__ diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_bootset_vseq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_bootset_vseq.sv index a4a8eee8d2..c1cd92bfa7 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_bootset_vseq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_bootset_vseq.sv @@ -38,7 +38,7 @@ task uvme_cv32e40s_random_debug_bootset_c::body(); fork uvma_debug_seq_item_c debug_req; `uvm_do_on_with(debug_req, p_sequencer.debug_sequencer, { - active_cycles == 1; + active_cycles == cfg.fetch_toggle_initial_delay; }); join endtask : body diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_reset_vseq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_reset_vseq.sv index 38ee198e84..eae4751255 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_reset_vseq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_random_debug_reset_vseq.sv @@ -38,7 +38,7 @@ task uvme_cv32e40s_random_debug_reset_c::body(); fork uvma_debug_seq_item_c debug_req; `uvm_do_on_with(debug_req, p_sequencer.debug_sequencer, { - active_cycles == 50; + active_cycles == cfg.fetch_toggle_initial_delay + 50; }); join endtask : body diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_debug_control_seq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_debug_control_seq.sv index bb28012909..a70b1b1b2b 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_debug_control_seq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_debug_control_seq.sv @@ -22,11 +22,38 @@ /** * Sequence implementing the virtual status flags decoding */ -class uvme_cv32e40s_vp_debug_control_seq_c extends uvma_obi_memory_vp_debug_control_seq_c; +class uvme_cv32e40s_vp_debug_control_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_debug_control_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +) ; uvme_cv32e40s_cntxt_c cv32e40s_cntxt; - `uvm_object_utils_begin(uvme_cv32e40s_vp_debug_control_seq_c) + `uvm_object_utils_begin(uvme_cv32e40s_vp_debug_control_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end /** diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_fencei_tamper_seq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_fencei_tamper_seq.sv index 78f27ea0e1..24c00186e1 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_fencei_tamper_seq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_fencei_tamper_seq.sv @@ -18,17 +18,44 @@ `ifndef __UVME_CV32E40S_VP_FENCEI_TAMPER_SEQ_SV__ `define __UVME_CV32E40S_VP_FENCEI_TAMPER_SEQ_SV__ - -class uvme_cv32e40s_vp_fencei_tamper_seq_c extends uvma_obi_memory_vp_base_seq_c; +import rvviApiPkg::*; + +class uvme_cv32e40s_vp_fencei_tamper_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); uvme_cv32e40s_cntxt_c cv32e40s_cntxt; - uvma_rvvi_ovpsim_cntxt_c rvvi_ovpsim_cntxt; bit enabled = 0; bit [31:0] addr; bit [31:0] data; - `uvm_object_utils(uvme_cv32e40s_vp_fencei_tamper_seq_c) + `uvm_object_utils(uvme_cv32e40s_vp_fencei_tamper_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) extern function new(string name="uvme_cv32e40s_vp_fencei_tamper_seq_c"); extern virtual task vp_body(uvma_obi_memory_mon_trn_c mon_trn); @@ -88,12 +115,6 @@ task uvme_cv32e40s_vp_fencei_tamper_seq_c::body(); if (cv32e40s_cntxt.fencei_cntxt.fencei_vif == null) begin `uvm_fatal("E40SVPSTATUS", "Must initialize fencei_vif in virtual peripheral"); end - if (cv32e40s_cntxt.rvvi_cntxt == null) begin - `uvm_fatal("E40SVPSTATUS", "Must initialize rvvi_cntxt in virtual peripheral"); - end - if (!$cast(rvvi_ovpsim_cntxt, cv32e40s_cntxt.rvvi_cntxt)) begin - `uvm_fatal("E40SVPSTATUS", "Could not cast rvvi_cntxt to rvvi_ovpsim_cntxt"); - end fork while (1) begin @@ -119,45 +140,11 @@ function void uvme_cv32e40s_vp_fencei_tamper_seq_c::write_rtl_mem(); endfunction : write_rtl_mem - function void uvme_cv32e40s_vp_fencei_tamper_seq_c::write_iss_mem(); - logic [31:0] addr_lo; - logic [31:0] addr_hi; - int shamt_lo; - int shamt_hi; - logic [31:0] shdata_lo; - logic [31:0] shdata_hi; - logic [31:0] issmask_lo; - logic [31:0] issmask_hi; - logic [31:0] issdata_lo; - logic [31:0] issdata_hi; - logic [31:0] data_lo; - logic [31:0] data_hi; - - // Calculate iss ram addresses - addr_lo = addr >> 2; - addr_hi = (addr + 4) >> 2; - - // Shift the data to be written - shamt_lo = addr[1:0] * 8; - shamt_hi = (4 * 8) - shamt_lo; - shdata_lo = data << shamt_lo; - shdata_hi = data >> shamt_hi; - - // Mask the existing data - issmask_lo = 32'h FFFF_FFFF >> shamt_hi; - issmask_hi = 32'h FFFF_FFFF << shamt_lo; - issdata_lo = rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_lo] & issmask_lo; - issdata_hi = rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_hi] & issmask_hi; - - // Calculate iss ram data - data_lo = shdata_lo | issdata_lo; - data_hi = shdata_hi | issdata_hi; - - // Write to iss ram - rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_lo] = data_lo; - rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_hi] = data_hi; + if ($test$plusargs("USE_ISS")) begin + rvviRefMemoryWrite(0, addr, data, 4); + end endfunction : write_iss_mem diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_interrupt_timer_seq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_interrupt_timer_seq.sv index 6bf148f620..82cc6cd374 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_interrupt_timer_seq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_interrupt_timer_seq.sv @@ -22,11 +22,38 @@ /** * Sequence implementing the virtual status flags decoding */ -class uvme_cv32e40s_vp_interrupt_timer_seq_c extends uvma_obi_memory_vp_interrupt_timer_seq_c; +class uvme_cv32e40s_vp_interrupt_timer_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_interrupt_timer_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); uvme_cv32e40s_cntxt_c cv32e40s_cntxt; - `uvm_object_utils_begin(uvme_cv32e40s_vp_interrupt_timer_seq_c) + `uvm_object_utils_begin(uvme_cv32e40s_vp_interrupt_timer_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end /** @@ -49,7 +76,16 @@ endfunction : new task uvme_cv32e40s_vp_interrupt_timer_seq_c::set_interrupt(); - cv32e40s_cntxt.interrupt_cntxt.vif.drv_cb.irq_drv <= interrupt_value; + if (cfg.clic_interrupts_enabled) begin + cv32e40s_cntxt.clic_cntxt.vif.drv_cb.clic_irq_drv <= clic_value.irq; + cv32e40s_cntxt.clic_cntxt.vif.drv_cb.clic_irq_id_drv <= clic_value.id; + cv32e40s_cntxt.clic_cntxt.vif.drv_cb.clic_irq_level_drv <= clic_value.level; + cv32e40s_cntxt.clic_cntxt.vif.drv_cb.clic_irq_priv_drv <= clic_value.priv; + cv32e40s_cntxt.clic_cntxt.vif.drv_cb.clic_irq_shv_drv <= clic_value.shv; + end + else if (cfg.basic_interrupts_enabled) begin + cv32e40s_cntxt.interrupt_cntxt.vif.drv_cb.irq_drv <= interrupt_value; + end endtask : set_interrupt diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_sig_writer_seq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_sig_writer_seq.sv index 5a48311d64..99b4956b5b 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_sig_writer_seq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_sig_writer_seq.sv @@ -23,11 +23,38 @@ /** * Sequence implementing the virtual status flags decoding */ -class uvme_cv32e40s_vp_sig_writer_seq_c extends uvma_obi_memory_vp_sig_writer_seq_c; +class uvme_cv32e40s_vp_sig_writer_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_sig_writer_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); uvme_cv32e40s_cntxt_c cv32e40s_cntxt; - `uvm_object_utils_begin(uvme_cv32e40s_vp_sig_writer_seq_c) + `uvm_object_utils_begin(uvme_cv32e40s_vp_sig_writer_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end /** diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_status_flags_seq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_status_flags_seq.sv index fb5c9191db..0cb2addf51 100644 --- a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_status_flags_seq.sv +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_vp_status_flags_seq.sv @@ -23,13 +23,40 @@ /** * Sequence implementing the virtual status flags decoding */ -class uvme_cv32e40s_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c; +class uvme_cv32e40s_vp_status_flags_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); localparam NUM_WORDS = 2; uvme_cv32e40s_cntxt_c cv32e40s_cntxt; - `uvm_object_utils_begin(uvme_cv32e40s_vp_status_flags_seq_c) + `uvm_object_utils_begin(uvme_cv32e40s_vp_status_flags_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end /** @@ -112,6 +139,7 @@ task uvme_cv32e40s_vp_status_flags_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_ slv_rsp.rdata = 0; end + add_r_fields(mon_trn, slv_rsp); slv_rsp.set_sequencer(p_sequencer); `uvm_send(slv_rsp) diff --git a/cv32e40s/env/uvme/vseq/uvme_cv32e40s_wu_wfe_noise_vseq.sv b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_wu_wfe_noise_vseq.sv new file mode 100644 index 0000000000..fa38f45a06 --- /dev/null +++ b/cv32e40s/env/uvme/vseq/uvme_cv32e40s_wu_wfe_noise_vseq.sv @@ -0,0 +1,120 @@ +// Copyright 2023 Silicon Labs. Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVME_CV32E40S_WU_WFE_NOISE_VSEQ_C__ +`define __UVME_CV32E40S_WU_WFE_NOISE_VSEQ_C__ + +/** + * + */ +class uvme_cv32e40s_wu_wfe_noise_vseq_c extends uvme_cv32e40s_base_vseq_c; + + rand int unsigned initial_delay_assert; + rand int unsigned initial_delay_deassert; + + rand int unsigned short_delay_wgt; + rand int unsigned medium_delay_wgt; + rand int unsigned long_delay_wgt; + + semaphore asserted_wu; + semaphore deasserted_wu; + `uvm_object_utils_begin(uvme_cv32e40s_wu_wfe_noise_vseq_c); + `uvm_object_utils_end + + constraint default_delay_c { + soft short_delay_wgt == 2; + soft medium_delay_wgt == 5; + soft long_delay_wgt == 3; + } + + constraint valid_initial_delay_assert_c { + initial_delay_assert dist { 0 :/ 2, + [10:500] :/ 4, + [500:1000] :/ 3}; + } + + constraint valid_initial_delay_deassert_c { + initial_delay_deassert dist { 0 :/ 2, + [10:500] :/ 4, + [500:1000] :/ 3}; + } + + extern function new(string name = ""); + + extern virtual task body(); + + extern virtual task rand_delay(); + +endclass : uvme_cv32e40s_wu_wfe_noise_vseq_c + +function uvme_cv32e40s_wu_wfe_noise_vseq_c::new(string name = ""); + super.new(name); +endfunction : new + +task uvme_cv32e40s_wu_wfe_noise_vseq_c::rand_delay(); + randcase + short_delay_wgt: repeat($urandom_range(100, 1)) @(cntxt.wfe_wu_cntxt.vif.drv_cb); + medium_delay_wgt: repeat($urandom_range(500, 100)) @(cntxt.wfe_wu_cntxt.vif.drv_cb); + long_delay_wgt: repeat($urandom_range(10_000, 5000)) @(cntxt.wfe_wu_cntxt.vif.drv_cb); + endcase +endtask : rand_delay + +task uvme_cv32e40s_wu_wfe_noise_vseq_c::body(); + asserted_wu = new(1); + deasserted_wu = new(1); + + // start with deasserted + void'(asserted_wu.put(1)); + + fork + begin : gen_assert + repeat (initial_delay_assert) @(cntxt.wfe_wu_cntxt.vif.drv_cb); + + forever begin + @(cntxt.wfe_wu_cntxt.vif.drv_cb) + if (deasserted_wu.try_get(1)) begin + uvma_wfe_wu_seq_item_c wfe_req; + + `uvm_do_on_with(wfe_req, p_sequencer.wfe_wu_sequencer, { + action == UVMA_WFE_WU_SEQ_ITEM_ACTION_ASSERT; + }) + rand_delay(); + asserted_wu.put(1); + end + end + end + + begin : gen_deassert + repeat (initial_delay_deassert) @(cntxt.wfe_wu_cntxt.vif.drv_cb); + + forever begin + @(cntxt.wfe_wu_cntxt.vif.drv_cb) + if (asserted_wu.try_get(1)) begin + uvma_wfe_wu_seq_item_c wfe_req; + + `uvm_do_on_with(wfe_req, p_sequencer.wfe_wu_sequencer, { + action == UVMA_WFE_WU_SEQ_ITEM_ACTION_DEASSERT; + }) + rand_delay(); + deasserted_wu.put(1); + end + end + end + join + +endtask : body + +`endif // __UVME_CV32E40S_WU_WFE_NOISE_VSEQ_C__ + diff --git a/cv32e40s/fv/.gitignore b/cv32e40s/fv/.gitignore new file mode 100644 index 0000000000..114ddb4830 --- /dev/null +++ b/cv32e40s/fv/.gitignore @@ -0,0 +1,7 @@ +jgproject/ +.qverify/ +qverify_ui* +.visualizer/ +ZinUIStateFile +formal_*.rpt +propcheck.db/ diff --git a/cv32e40s/fv/Makefile b/cv32e40s/fv/Makefile new file mode 100644 index 0000000000..7ed3560d40 --- /dev/null +++ b/cv32e40s/fv/Makefile @@ -0,0 +1,56 @@ +# Copyright 2022 Silicon Labs, Inc. +# Copyright 2022 OpenHW Group +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + + +# Defines and Includes + +CORE_V_VERIF ?= $(realpath ../..) +CV_CORE ?= cv32e40s + +include $(CORE_V_VERIF)/$(CV_CORE)/sim/ExternalRepos.mk +include $(CORE_V_VERIF)/mk/fv/fv.mk + + +# Options + +JG_EXTRAS = -bg dimgray -fg lightgray + +export FV_DEFINES = ${USER_DEFINES} +export FV_INCDIRS = ${USER_INCDIRS} +#TODO:silabs-robin This defines system is not perfect. + + +# Safety Check + +ifndef CV_SIM_PREFIX + $(warning CV_SIM_PREFIX undefined) +endif + + +# Make Targets + +jaspergold: jg +jasper: jg +jg: $(CV_CORE_PKG) + $(CV_SIM_PREFIX) jaspergold $(JG_EXTRAS) jaspergold.tcl + # TODO:silabs-robin Move to "mk/fv/jg.mk"? + +qverify: q +questa: q +q: $(CV_CORE_PKG) + $(CV_SIM_PREFIX) qverify -do qverify.tcl + # TODO:silabs-robin Move to "mk/fv/jg.mk"? diff --git a/cv32e40s/fv/README.md b/cv32e40s/fv/README.md new file mode 100644 index 0000000000..87470a6e15 --- /dev/null +++ b/cv32e40s/fv/README.md @@ -0,0 +1,21 @@ +# Formal Verification + +This directory is for running formal property checking. + +Read the Makefile for more info. + + +## Usage Examples + +Simple example: +``` +make jg +``` + +Advanced examples: +``` +make jg USER_DEFINES=+define+MYDEFINE USER_INCDIRS=+incdir+MYINCDIR +make jg JG_EXTRAS="" +make jg USER_DEFINES=+define+COREV_ASSERT_OFF +make jg USER_DEFINES=+define+DEFONE+DEFTWO+DEFTHREE +``` diff --git a/cv32e40s/fv/defines.sv b/cv32e40s/fv/defines.sv new file mode 100644 index 0000000000..9836ac7cd3 --- /dev/null +++ b/cv32e40s/fv/defines.sv @@ -0,0 +1 @@ +`define FORMAL 1 diff --git a/cv32e40s/fv/dummy_pkg.sv b/cv32e40s/fv/dummy_pkg.sv new file mode 100644 index 0000000000..761f565dc7 --- /dev/null +++ b/cv32e40s/fv/dummy_pkg.sv @@ -0,0 +1,60 @@ +// TODO:silabs-robin Delete this file, make core-v-verif files fv compatible. + + +// Copyright 2022 Silicon Labs, Inc. +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + + +// Defines + +`include "uvma_obi_memory_macros.sv" + + +// Packages + +package uvmt_cv32e40s_pkg; + `include "uvmt_cv32e40s_constants.sv" + `include "uvmt_cv32e40s_tdefs.sv" + + import cv32e40s_pkg::*; +endpackage + +package uvme_cv32e40s_pkg; + `include "uvme_cv32e40s_constants.sv" +endpackage + +package uvma_rvfi_pkg; + `include "uvma_rvfi_constants.sv" + `include "uvma_rvfi_tdefs.sv" +endpackage + +package uvma_fencei_pkg; +endpackage + + +// Interfaces + +interface uvma_clknrst_if_t; + logic clk; + logic reset_n; +endinterface : uvma_clknrst_if_t + + +// Modules + + +// Fin diff --git a/cv32e40s/fv/fv.flist b/cv32e40s/fv/fv.flist new file mode 100644 index 0000000000..ad12befeaf --- /dev/null +++ b/cv32e40s/fv/fv.flist @@ -0,0 +1,57 @@ +# Copyright 2022 Silicon Labs, Inc. +# Copyright 2022 OpenHW Group +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +# not use this file except in compliance with the License, or, at your option, +# the Apache License version 2.0. +# +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. + + ++incdir+${DV_UVMT_PATH} ++incdir+${DV_UVME_PATH} ++incdir+${DV_UVMA_PATH}/uvma_rvfi ++incdir+${DV_UVMA_PATH}/uvma_fencei ++incdir+${DV_UVMA_PATH}/uvma_clic ++incdir+${DV_UVMA_PATH}/uvma_obi_memory/src + +./uvm_pkg.sv +./defines.sv +${FV_DEFINES} +${FV_INCDIRS} + +-f ${CV_CORE_PKG}/cv32e40s_manifest.flist +-f ${DV_ISA_DECODER_PATH}/isa_decoder_pkg.flist +-f ${DV_SUPPORT_PATH}/support_pkg.flist +${DV_UVM_TESTCASE_PATH}/base-tests/uvmt_cv32e40s_base_test_pkg.sv +${DV_UVMA_PATH}/uvma_obi_memory/src/uvma_obi_memory_assert.sv +${DV_UVMA_PATH}/uvma_obi_memory/src/uvma_obi_memory_1p2_assert.sv + +./dummy_pkg.sv + +#TODO: change the file names too? + +${DV_UVMA_PATH}/uvma_clic/uvma_clic_if.sv +${DV_UVMA_PATH}/uvma_debug/uvma_debug_if.sv +${DV_UVMA_PATH}/uvma_fencei/uvma_fencei_if.sv +${DV_UVMA_PATH}/uvma_interrupt/uvma_interrupt_if.sv +${DV_UVMA_PATH}/uvma_obi_memory/src/uvma_obi_memory_assert_if_wrp.sv +${DV_UVMA_PATH}/uvma_obi_memory/src/uvma_obi_memory_if.sv +${DV_UVMA_PATH}/uvma_rvfi/uvma_rvfi_csr_if.sv +${DV_UVMA_PATH}/uvma_rvfi/uvma_rvfi_instr_if.sv +${DV_UVMA_PATH}/uvma_wfe_wu/uvma_wfe_wu_if.sv +${DV_UVME_PATH}/uvme_cv32e40s_core_cntrl_if.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_tb_ifs.sv + +-f ${DV_UVMT_PATH}/uvmt_cv32e40s_tb_files.flist diff --git a/cv32e40s/fv/jaspergold.tcl b/cv32e40s/fv/jaspergold.tcl new file mode 100644 index 0000000000..74f6827e21 --- /dev/null +++ b/cv32e40s/fv/jaspergold.tcl @@ -0,0 +1,53 @@ +# Copyright 2022 Silicon Labs, Inc. +# Copyright 2022 OpenHW Group +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + + +# TODO:silabs-robin No hardcoded paths, integrate with `mk/` definitions. + + +proc cvfv_rerun {} { + clear -all + + # Message Severities + ## Error on file not found + set_message -error WNL074 + ## Allow omitted param defaults + set_message -info VERI-1818 + ## Allow parameter treated as localparam + set_message -info VERI-2418 + ## Allow empty port in module declaration + set_message -info VERI-8026 + ## Allow multiplier blackboxing + set_message -info WNL018 + + # Analyze & Elaborate + analyze -sv12 -f fv.flist + elaborate -top uvmt_cv32e40s_tb -extract_covergroup + + # Clock & Reset + clock clknrst_if.clk + reset ~clknrst_if.reset_n + + # Assumes + assume -from_assert {*_memory_assert_i.u_assert.a_r_after_a} + assume -from_assert {*.obi_*_memory_assert_i.*.a_*par} + assume -from_assert {*integration_assert_i.a_stable_*} + assume -from_assert {*integration_assert_i.a_aligned_*} + assume -from_assert {*integration_assert_i.a_no_scan_cg} +} + +cvfv_rerun diff --git a/cv32e40s/fv/qverify.tcl b/cv32e40s/fv/qverify.tcl new file mode 100644 index 0000000000..74e09d554d --- /dev/null +++ b/cv32e40s/fv/qverify.tcl @@ -0,0 +1,70 @@ +# Copyright 2022 Silicon Labs, Inc. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +# not use this file except in compliance with the License, or, at your option, +# the Apache License version 2.0. +# +# You may obtain a copy of the License at +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. + + +proc cvfv_rerun {} { + onerror {exit 1} + + puts "cvfv: compiling verilog" + vlog -mfcu -f fv.flist + + puts "cvfv: cutpointing general 'control points'" + netlist cutpoint {uvmt_cv32e40s_tb.clknrst_if.reset_n} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.debug_if.debug_req} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.interrupt_if.irq} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.core_cntrl_if.boot_addr} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.core_cntrl_if.mtvec_addr} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.core_cntrl_if.dm_halt_addr} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.core_cntrl_if.dm_exception_addr} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.core_cntrl_if.mhartid} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.core_cntrl_if.mimpid_patch} -module uvmt_cv32e40s_tb + #cutpoints needed to subdue "Design Checks" errors that lead to bonkers CEXes + + puts "cvfv: cutpointing obi 'control points'" + netlist cutpoint {uvmt_cv32e40s_tb.obi_instr_if.err} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_instr_if.gntpar} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_instr_if.gnt} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_instr_if.rchk} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_instr_if.rdata} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_instr_if.rvalidpar} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_instr_if.rvalid} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_data_if.err} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_data_if.gntpar} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_data_if.gnt} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_data_if.rchk} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_data_if.rdata} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_data_if.rvalidpar} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.obi_data_if.rvalid} -module uvmt_cv32e40s_tb + netlist cutpoint {uvmt_cv32e40s_tb.fencei_if.flush_ack} -module uvmt_cv32e40s_tb + + puts "cvfv: setting constants" + netlist constant {uvmt_cv32e40s_tb.core_cntrl_if.scan_cg_en} {0} -module uvmt_cv32e40s_tb + netlist constant {uvmt_cv32e40s_tb.core_cntrl_if.fetch_en} {1} -module uvmt_cv32e40s_tb + + puts "cvfv: initializing clock/reset" + netlist clock {uvmt_cv32e40s_tb.clknrst_if.clk} -module uvmt_cv32e40s_tb + netlist reset {uvmt_cv32e40s_tb.clknrst_if.reset_n} -active_low -module uvmt_cv32e40s_tb + formal init -inferred + + puts "cvfv: compiling formal model" + formal compile -d uvmt_cv32e40s_tb -work work + + puts "cvfv: see the visualizer log for compilation warnings" +} + +cvfv_rerun diff --git a/cv32e40s/fv/uvm_pkg.sv b/cv32e40s/fv/uvm_pkg.sv new file mode 100644 index 0000000000..9c555230f2 --- /dev/null +++ b/cv32e40s/fv/uvm_pkg.sv @@ -0,0 +1,5 @@ +package uvm_pkg; +endpackage + +`define uvm_error(ID, MSG) ; +`define uvm_info(ID, MSG, VERBOSITY) ; diff --git a/cv32e40s/regress/cv32e40s_ci_check.yaml b/cv32e40s/regress/cv32e40s_ci_check.yaml index 95948aa0da..d59600ed74 100644 --- a/cv32e40s/regress/cv32e40s_ci_check.yaml +++ b/cv32e40s/regress/cv32e40s_ci_check.yaml @@ -5,18 +5,27 @@ description: Commit sanity for the cv32e40s builds: clone_riscv-dv: cmd: make clone_riscv-dv + cfg: default dir: cv32e40s/sim/uvmt clone_svlib: cmd: make clone_svlib + cfg: default dir: cv32e40s/sim/uvmt clone_cv_core_rtl: cmd: make clone_cv_core_rtl + cfg: default dir: cv32e40s/sim/uvmt uvmt_cv32e40s: cmd: make comp_corev-dv comp + cfg: default + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_clic: + cmd: make comp_corev-dv comp + cfg: clic_default dir: cv32e40s/sim/uvmt uvmt_cv32e40s_pma_1: @@ -31,70 +40,64 @@ builds: tests: hello-world: - build: uvmt_cv32e40s + builds: [ uvmt_cv32e40s ] description: UVM Hello World Test dir: cv32e40s/sim/uvmt cmd: make test TEST=hello-world - interrupt_test: - build: uvmt_cv32e40s - description: Interrupt directed test + clic: + builds: [ uvmt_cv32e40s_clic ] + description: CLIC interrupt test dir: cv32e40s/sim/uvmt - cmd: make test TEST=interrupt_test + cmd: make test TEST=clic corev_rand_interrupt: - build: uvmt_cv32e40s + builds: [ uvmt_cv32e40s ] description: Interrupt random test dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt num: 2 illegal: - build: uvmt_cv32e40s + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=illegal -# FIXME: temporarily remove this test from ci_check: see issue #1031. -# debug_test: -# build: uvmt_cv32e40s -# dir: cv32e40s/sim/uvmt -# cmd: make test TEST=debug_test -# makearg: USER_RUN_FLAGS=+rand_stall_obi_disable + debug_test2: + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] + description: Debug directed test + dir: cv32e40s/sim/uvmt + cmd: make test TEST=debug_test2 + makearg: USER_RUN_FLAGS=+rand_stall_obi_disable csr_instructions: - build: uvmt_cv32e40s + builds: [ uvmt_cv32e40s ] description: CSR Instruction Test dir: cv32e40s/sim/uvmt cmd: make test TEST=csr_instructions riscv_arithmetic_basic_test_0: - build: uvmt_cv32e40s + builds: [ uvmt_cv32e40s ] description: Static riscv-dv arithmetic test 0 dir: cv32e40s/sim/uvmt cmd: make test TEST=riscv_arithmetic_basic_test_0 corev_rand_arithmetic_base_test: - builds: - - uvmt_cv32e40s - - uvmt_cv32e40s_pma_1 - - uvmt_cv32e40s_pma_2 + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2 ] description: Generated corev-dv random arithmetic test dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test num: 1 corev_rand_instr_test: - builds: - - uvmt_cv32e40s - - uvmt_cv32e40s_pma_1 - - uvmt_cv32e40s_pma_2 + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2 ] description: Generated corev-dv random instruction test dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_test num: 1 corev_rand_jump_stress_test: - build: uvmt_cv32e40s + builds: [ uvmt_cv32e40s ] description: Generated corev-dv jump stress test dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test diff --git a/cv32e40s/regress/cv32e40s_compliance.yaml b/cv32e40s/regress/cv32e40s_compliance.yaml index ba90fcd83a..b0320d9a6b 100644 --- a/cv32e40s/regress/cv32e40s_compliance.yaml +++ b/cv32e40s/regress/cv32e40s_compliance.yaml @@ -1,7 +1,7 @@ # YAML file to specify a regression testlist --- # Header -name: cv32_compliance +name: cv32e40s_compliance description: Runs all RISCV compliance tests on the CV32E40S # List of builds diff --git a/cv32e40s/regress/cv32e40s_counters_test.yaml b/cv32e40s/regress/cv32e40s_counters_test.yaml index 296f96313f..374d3ac604 100644 --- a/cv32e40s/regress/cv32e40s_counters_test.yaml +++ b/cv32e40s/regress/cv32e40s_counters_test.yaml @@ -3,7 +3,7 @@ # This means you need to have a toolchain at COREV_SW_TOOLCHAIN (see Common.mk) --- # Header -name: cv32_counters +name: cv32e40s_counters_test description: Performance counters test # List of builds @@ -16,35 +16,8 @@ builds: cmd: make bsp comp dir: cv32e40s/sim/uvmt - uvmt_cv32e40s_num_mhpmcounter_29: - cmd: make bsp comp - cfg: num_mhpmcounter_29 - dir: cv32e40s/sim/uvmt - # List of tests tests: - perf_counters_instructions: - build: uvmt_cv32e40s - description: Performance counter test - dir: cv32e40s/sim/uvmt - cmd: make test COREV=YES TEST=perf_counters_instructions - num: 40 - - mhpmcounter29_csr_access_test_1: - build: uvmt_cv32e40s_num_mhpmcounter_29 - description: Hardware performance counter full access coverage test 1 - builds: [ uvmt_cv32e40s_num_mhpmcounter_29] - dir: cv32e40s/sim/uvmt - cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_1 - num: 40 - - mhpmcounter29_csr_access_test_2: - build: uvmt_cv32e40s_num_mhpmcounter_29 - description: Hardware performance counter full access coverage test 2 - builds: [ uvmt_cv32e40s_num_mhpmcounter_29] - dir: cv32e40s/sim/uvmt - cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_2 - num: 40 hpmcounter_basic_test: build: uvmt_cv32e40s diff --git a/cv32e40s/regress/cv32e40s_debug.yaml b/cv32e40s/regress/cv32e40s_debug.yaml index 74b35197df..f4a52e6b93 100644 --- a/cv32e40s/regress/cv32e40s_debug.yaml +++ b/cv32e40s/regress/cv32e40s_debug.yaml @@ -1,7 +1,7 @@ # YAML file to specify a regression testlist --- # Header -name: cv32_debug_regression +name: cv32e40s_debug description: Directed and random debug tests for CV32E40S # List of builds diff --git a/cv32e40s/regress/cv32e40s_full.yaml b/cv32e40s/regress/cv32e40s_full.yaml index 0a7bc61867..4667d6aa4f 100644 --- a/cv32e40s/regress/cv32e40s_full.yaml +++ b/cv32e40s/regress/cv32e40s_full.yaml @@ -3,7 +3,7 @@ # This means you need to have a toolchain at COREV_SW_TOOLCHAIN (see Common.mk) --- # Header -name: cv32_full_covg +name: cv32e40s_full description: Full regression (all tests) for CV32E40S with step-and-compare against RM" # List of builds @@ -24,9 +24,9 @@ builds: cmd: make comp_corev-dv comp dir: cv32e40s/sim/uvmt - uvmt_cv32e40s_b_ext_abs: + uvmt_cv32e40s_clic: cmd: make comp_corev-dv comp - cfg: b_ext_abs + cfg: clic_default dir: cv32e40s/sim/uvmt uvmt_cv32e40s_b_ext_all: @@ -39,9 +39,9 @@ builds: cfg: pma dir: cv32e40s/sim/uvmt - uvmt_cv32e40s_num_mhpmcounter_29: + uvmt_cv32e40s_pma_debug: cmd: make comp_corev-dv comp - cfg: num_mhpmcounter_29 + cfg: pma_debug dir: cv32e40s/sim/uvmt uvmt_cv32e40s_pma_1: @@ -69,363 +69,504 @@ builds: cfg: pma_test_cfg_5 dir: cv32e40s/sim/uvmt - uvmt_cv32e40s_no_bitmanip: + uvmt_cv32e40s_pmp: cmd: make comp_corev-dv comp - cfg: no_bitmanip + cfg: pmp dir: cv32e40s/sim/uvmt + uvmt_cv32e40s_dummy_instr: + cmd: make comp_corev-dv comp + cfg: dummy_instr + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_debug_trigger_cfg0: + cmd: make comp_corev-dv comp + cfg: debug_trigger_cfg0 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_debug_trigger_cfg1: + cmd: make comp_corev-dv comp + cfg: debug_trigger_cfg1 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_debug_trigger_cfg2: + cmd: make comp_corev-dv comp + cfg: debug_trigger_cfg2 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_debug_trigger_cfg3: + cmd: make comp_corev-dv comp + cfg: debug_trigger_cfg3 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_debug_trigger_cfg4: + cmd: make comp_corev-dv comp + cfg: debug_trigger_cfg4 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_xsecure_disable_std: + cmd: make comp_corev-dv comp + cfg: xsecure_disable_std + dir: cv32e40s/sim/uvmt + + # List of tests tests: hello-world: description: uvm_hello_world_test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=hello-world csr_instructions: description: CSR instruction test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=csr_instructions generic_exception_test: description: Generic exception test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=generic_exception_test illegal_instr_test: description: Illegal instruction test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=illegal_instr_test branch_zero: description: Branch test with zero offsets - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=branch_zero cv32e40s_csr_access_test: description: CSR Access Mode Test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=cv32e40s_csr_access_test cv32e40s_readonly_csr_access_test: description: CSR Read-only Access Mode Test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=cv32e40s_readonly_csr_access_test requested_csr_por: description: CSR PoR test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=requested_csr_por modeled_csr_por: description: Modeled CSR PoR test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=modeled_csr_por csr_instr_asm: description: CSR instruction assembly test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=csr_instr_asm - perf_counters_instructions: - description: Performance counter test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] - dir: cv32e40s/sim/uvmt - cmd: make test TEST=perf_counters_instructions - - mhpmcounter29_csr_access_test_1: - description: Hardware performance counter full access coverage test 1 - builds: [ uvmt_cv32e40s_num_mhpmcounter_29 ] - dir: cv32e40s/sim/uvmt - cmd: make test TEST=mhpmcounter29_csr_access_test_1 - - mhpmcounter29_csr_access_test_2: - description: Hardware performance counter full access coverage test 2 - builds: [ uvmt_cv32e40s_num_mhpmcounter_29 ] - dir: cv32e40s/sim/uvmt - cmd: make test TEST=mhpmcounter29_csr_access_test_2 - hpmcounter_basic_test: description: Hardware performance counter basic test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=hpmcounter_basic_test hpmcounter_basic_nostall_test: description: Hardware performance counter basic test with no random stalls - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=hpmcounter_basic_nostall_test hpmcounter_hazard_test: description: Hardware performance counter hazard test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=hpmcounter_hazard_test riscv_ebreak_test_0: description: Static corev-dv ebreak - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=riscv_ebreak_test_0 riscv_arithmetic_basic_test_0: description: Static riscv-dv arithmetic test 0 - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=riscv_arithmetic_basic_test_0 num: 1 riscv_arithmetic_basic_test_1: description: Static riscv-dv arithmetic test 1 - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=riscv_arithmetic_basic_test_1 num: 1 corev_rand_arithmetic_base_test: description: Generated corev-dv arithmetic test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_xsecure_disable_std ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test num: 4 corev_rand_instr_test: description: Generated corev-dv random instruction test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_xsecure_disable_std ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_test num: 5 corev_rand_instr_long_stall: description: Generated corev-dv random instruction test with long stalls - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_long_stall num: 2 corev_rand_illegal_instr_test: description: Generated corev-dv random instruction test with illegal instructions - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_illegal_instr_test num: 5 corev_rand_jump_stress_test: description: Generated corev-dv jump stress test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test num: 5 corev_rand_interrupt: description: Generated corev-dv random interrupt test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt num: 5 corev_rand_debug: description: Generated corev-dv random debug test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_debug num: 5 corev_rand_debug_single_step: description: debug random test with single-stepping - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_debug_single_step num: 5 corev_rand_debug_ebreak: description: debug random test with ebreaks from ROM - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_debug_ebreak num: 5 corev_rand_interrupt_wfi: description: Generated corev-dv random interrupt WFI test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi num: 5 corev_rand_fencei: - description: Generated corev-dv random fence,i test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + description: Generated corev-dv random fence.i test + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fencei num: 2 corev_rand_interrupt_wfi_mem_stress: description: Generated corev-dv random interrupt WFI test with memory stress - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi_mem_stress num: 5 corev_rand_interrupt_debug: description: Generated corev-dv random interrupt WFI test with debug - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_debug num: 5 corev_rand_interrupt_exception: description: Generated corev-dv random interrupt WFI test with exceptions - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_exception num: 5 corev_rand_interrupt_nested: description: Generated corev-dv random interrupt WFI test with random nested interrupts - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_nested num: 5 corev_rand_pma_test: description: Generated corev-dv random PMA test - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5 ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pma_test num: 3 corev_rand_instr_obi_err: description: Random OBI instruction bus error test - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_obi_err num: 6 corev_rand_instr_obi_err_debug: description: Random OBI instruction bus error test with debug - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_obi_err_debug num: 6 corev_rand_data_obi_err: description: Random OBI data bus error test - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err num: 6 corev_rand_data_obi_err_debug: description: Random OBI data bus error test with debug - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err_debug - num: 6 + num: 10 illegal: description: Illegal-riscv-tests - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=illegal fibonacci: description: Fibonacci test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=fibonacci misalign: description: Misalign test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=misalign dhrystone: description: Dhrystone test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=dhrystone - debug_test: - description: Debug Test 1 - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + debug_test2: + description: Debug Test 2 + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt - cmd: make test TEST=debug_test + cmd: make test TEST=debug_test2 debug_test_reset: description: Debug reset test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_test_reset - debug_test_trigger: - description: Debug trigger test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] - dir: cv32e40s/sim/uvmt - cmd: make test TEST=debug_test_trigger - debug_test_boot_set: description: Debug test target debug_req at BOOT_SET - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_test_boot_set num: 10 interrupt_bootstrap: description: Interrupt bootstrap test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=interrupt_bootstrap interrupt_test: description: Interrupt test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=interrupt_test + clic: + description: CLIC interrupt test + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=clic + isa_fcov_holes: description: ISA function coverage test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=isa_fcov_holes + cov_holes_generic: + description: Generic coverage closure test for known coverage holes + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=cov_holes_generic + instr_bus_error: description: Directed instruction bus error test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=instr_bus_error data_bus_error: description: Directed data bus error test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=data_bus_error load_store_rs1_zero: description: Directed rs1 coverage test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_no_bitmanip] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=load_store_rs1_zero + fencei: + description: fence.i directed tests + builds: + - uvmt_cv32e40s + - uvmt_cv32e40s_pma_1 + - uvmt_cv32e40s_pma_2 + - uvmt_cv32e40s_pma_5 + - uvmt_cv32e40s_dummy_instr + dir: cv32e40s/sim/uvmt + cmd: make test TEST=fencei + pma: - description: ISA function coverage test - builds: [ uvmt_cv32e40s_pma] + description: PMA directed tests + builds: [ uvmt_cv32e40s_pma ] dir: cv32e40s/sim/uvmt - cmd: make test TEST=isa_fcov_holes + cmd: make test TEST=pma + + pma_0reg: + description: PMA directed tests with zero registers + builds: [ uvmt_cv32e40s ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=pma_0reg + + pma_debug: + description: PMA directed tests relating to debug + builds: [ uvmt_cv32e40s_pma_debug ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=pma_debug + + pmp: + description: PMP directed tests + builds: [ uvmt_cv32e40s_pmp ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=pmp + + pmp_csr_access_test: + description: Test to write to all bits of all 64 PMP CSRs + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=pmp_csr_access_test b_ext_test: description: Directed Zb extension test - builds: [ uvmt_cv32e40s_b_ext_abs, uvmt_cv32e40s_b_ext_all] + builds: [ uvmt_cv32e40s_b_ext_all ] dir: cv32e40s/sim/uvmt cmd: make test TEST=b_ext_test + csr_priv_gen_test: + description: Generated U-mode CSR access tests + builds: [ uvmt_cv32e40s_pmp ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=csr_priv_gen_test + +# custom_priv_gen_test: +# description: Generated U-mode custom instr tests +# builds: [ uvmt_cv32e40s_pmp ] +# dir: cv32e40s/sim/uvmt +# cmd: make test TEST=custom_priv_gen_test +# TODO:silabs-robin This test times out. + + debug_priv_test: + description: D-mode vs U-mode tests + builds: [ uvmt_cv32e40s_pmp ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=debug_priv_test + + interrupt_priv_test: + description: Interrupts vs U-mode tests + builds: [ uvmt_cv32e40s_pmp ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=interrupt_priv_test + + mcounteren_priv_gen_test: + description: U-mode access and privilege instructions + builds: [ uvmt_cv32e40s_pmp ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=mcounteren_priv_gen_test + + privilege_test: + description: Privilege mode accesses and csr behavior + builds: [ uvmt_cv32e40s_pmp ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=privilege_test + + zc_test: + description: Zc directed test + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1 ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=zc_test + num: 5 + + pushpop_debug_triggers: + description: Zc push/pop vs debug triggers + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=pushpop_debug_triggers + + debug_test_trigger: + description: Test of debug triggers + builds: [ uvmt_cv32e40s_debug_trigger_cfg1, + uvmt_cv32e40s_debug_trigger_cfg2, + uvmt_cv32e40s_debug_trigger_cfg3, + uvmt_cv32e40s_debug_trigger_cfg4 ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=debug_test_trigger + + debug_test_0_triggers: + description: Test of debug triggers + builds: [ uvmt_cv32e40s_debug_trigger_cfg0 ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=debug_test_0_triggers + + wfe_test: + description: Short directed wfe test (needs PMP support) + builds: [ uvmt_cv32e40s_clic, uvmt_cv32e40s ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=wfe_test + + xsecure_test: + description: xsecure test + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=xsecure_test + + xsecure_csrs: + description: xsecure csr test + builds: [ uvmt_cv32e40s_clic, uvmt_cv32e40s ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=xsecure_csrs diff --git a/cv32e40s/regress/cv32e40s_hello_world.yaml b/cv32e40s/regress/cv32e40s_hello_world.yaml index 2a6556f63f..41f0049ce6 100644 --- a/cv32e40s/regress/cv32e40s_hello_world.yaml +++ b/cv32e40s/regress/cv32e40s_hello_world.yaml @@ -1,5 +1,5 @@ -# YAML file to specify the ci_check regression testlist. -name: cv32e40s_ci_check +# YAML file to specify the hello-world regression testlist. +name: cv32e40s_hello_world description: Commit sanity for the cv32e40s builds: diff --git a/cv32e40s/regress/cv32e40s_interrupt.yaml b/cv32e40s/regress/cv32e40s_interrupt.yaml index e7d03426c2..a01860655e 100644 --- a/cv32e40s/regress/cv32e40s_interrupt.yaml +++ b/cv32e40s/regress/cv32e40s_interrupt.yaml @@ -1,7 +1,7 @@ # YAML file to specify a regression testlist --- # Header -name: cv32_interrupt +name: cv32e40s_interrupt description: Directed and random interrupt tests for CV32E40S # List of builds diff --git a/cv32e40s/regress/cv32e40s_pma.yaml b/cv32e40s/regress/cv32e40s_pma.yaml index a6d1014234..0b61e17e95 100644 --- a/cv32e40s/regress/cv32e40s_pma.yaml +++ b/cv32e40s/regress/cv32e40s_pma.yaml @@ -12,20 +12,72 @@ builds: cmd: make clean_bsp clean_test_programs dir: cv32e40s/sim/uvmt + corev-dv_pma_1: + cmd: make comp_corev-dv + cfg: pma_test_cfg_1 + dir: cv32e40s/sim/uvmt + + corev-dv_pma_2: + cmd: make comp_corev-dv + cfg: pma_test_cfg_2 + dir: cv32e40s/sim/uvmt + + corev-dv_pma_3: + cmd: make comp_corev-dv + cfg: pma_test_cfg_3 + dir: cv32e40s/sim/uvmt + + corev-dv_pma_4: + cmd: make comp_corev-dv + cfg: pma_test_cfg_4 + dir: cv32e40s/sim/uvmt + + corev-dv_pma_5: + cmd: make comp_corev-dv + cfg: pma_test_cfg_5 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_pma_1: + cmd: make comp + cfg: pma_test_cfg_1 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_pma_2: + cmd: make comp + cfg: pma_test_cfg_2 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_pma_3: + cmd: make comp + cfg: pma_test_cfg_3 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_pma_4: + cmd: make comp + cfg: pma_test_cfg_4 + dir: cv32e40s/sim/uvmt + + uvmt_cv32e40s_pma_5: + cmd: make comp + cfg: pma_test_cfg_5 + dir: cv32e40s/sim/uvmt + corev-dv: cmd: make clean_riscv-dv comp_corev-dv dir: cv32e40s/sim/uvmt cov: 0 - uvmt_cv32e40s: - cmd: make comp - dir: cv32e40s/sim/uvmt # List of tests tests: corev_rand_pma_test: - build: uvmt_cv32e40s description: Generated corev-dv pma test dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pma_test + builds: + - uvmt_cv32e40s_pma_1 + - uvmt_cv32e40s_pma_2 + - uvmt_cv32e40s_pma_3 + - uvmt_cv32e40s_pma_4 + - uvmt_cv32e40s_pma_5 num: 20 diff --git a/cv32e40s/regress/cv32e40s_rel_check.yaml b/cv32e40s/regress/cv32e40s_rel_check.yaml index 8b855d5f26..019548ab06 100644 --- a/cv32e40s/regress/cv32e40s_rel_check.yaml +++ b/cv32e40s/regress/cv32e40s_rel_check.yaml @@ -1,7 +1,7 @@ # YAML file to specify a regression testlist --- # Header -name: cv32e40s_full +name: cv32e40s_rel_check description: Release regression for CV32E40S # List of builds @@ -91,12 +91,6 @@ tests: dir: cv32e40s/sim/uvmt cmd: make test TEST=csr_instr_asm - perf_counters_instructions: - build: uvmt_cv32e40s - description: Performance counter test - dir: cv32e40s/sim/uvmt - cmd: make test TEST=perf_counters_instructions - hpmcounter_basic_test: build: uvmt_cv32e40s description: Hardware performance counter basic test diff --git a/cv32e40s/sim/ExternalRepos.mk b/cv32e40s/sim/ExternalRepos.mk index d6cc8b06c6..c472caf044 100644 --- a/cv32e40s/sim/ExternalRepos.mk +++ b/cv32e40s/sim/ExternalRepos.mk @@ -15,26 +15,27 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40s CV_CORE_BRANCH ?= master -CV_CORE_HASH ?= 103056f0deeac8e6cc10244c86bff83d3014f66f +CV_CORE_HASH ?= 86b09c6f88bdaec9e28fc192cdbbc6d88bee038a CV_CORE_TAG ?= none -# RISCVDV_REPO ?= https://github.com/google/riscv-dv -# RISCVDV_BRANCH ?= master -# RISCVDV_HASH ?= 96c1ee6f371f2754c45b4831fcab95f6671689d9 - -# TODO: silabs-hfegran, remove this temporary fix when riscv-dv changes get upstreamed -RISCVDV_REPO ?= https://github.com/silabs-hfegran/riscv-dv.git -RISCVDV_BRANCH ?= dev_hf_rvdv_csr_updates -RISCVDV_HASH ?= 87d9ae2d60d928e3c6afcd6ff1aacb5298f2904b +#RISCVDV_REPO ?= https://github.com/google/riscv-dv +RISCVDV_REPO ?= https://github.com/silabs-hfegran/riscv-dv +#RISCVDV_BRANCH ?= master +RISCVDV_BRANCH ?= dev_hf +#RISCVDV_HASH ?= 797aa0762de8e2c8d427b978483b47dd7649954a +RISCVDV_HASH ?= 13e0cdf5d50e882d939e9a0d0afe093ee1c68290 EMBENCH_REPO ?= https://github.com/embench/embench-iot.git EMBENCH_BRANCH ?= master EMBENCH_HASH ?= 6934ddd1ff445245ee032d4258fdeb9828b72af4 -COMPLIANCE_REPO ?= https://github.com/strichmo/riscv-arch-test.git -COMPLIANCE_BRANCH ?= strichmo/pr/cv32e40s_initial_old_compliance -# 2020-08-19 -COMPLIANCE_HASH ?= cf29051b177ba61b8c39de91c33d20d202697423 +# TODO: silabs-hfegran: Temporary fork compliance suite to support bitmanip and +# new repository structure. Revert back to latest mainline when bitmanip PR has +# been approved and local changes upstreamed. +# 2022-02-21 +COMPLIANCE_REPO ?= https://github.com/silabs-hfegran/riscv-arch-test.git +COMPLIANCE_BRANCH ?= dev_hf_riscv_arch_test +COMPLIANCE_HASH ?= 43556e3ae4e98d5e739204f37a11769e14154b7e # This Spike repo is only cloned when the DPI disassembler needs to be rebuilt # Typically users can simply use the checked-in shared library diff --git a/cv32e40s/sim/tools/xrun/README.md b/cv32e40s/sim/tools/xrun/README.md index 3936396de4..d116239f10 100644 --- a/cv32e40s/sim/tools/xrun/README.md +++ b/cv32e40s/sim/tools/xrun/README.md @@ -1,24 +1,28 @@ -## Xcelium tools directory +## Xcelium Tools Directory -Various Xcelium-based utilities and scripts. +Xcelium-based utilities and scripts. -### Simulator control scripts -These TCL scripts can be passed to Xcelium by the core-v-verif Makefiles when using Xcelium. The following scripts are currently supported: +### Simulator Control Scripts -| Script | Usage | -|--------|-------| -| probe.tcl | Generates probes for waveform database viewable with Cadence SimVision. Invoked when WAVES=1 passed to the make test command | -| indago.tcl | Generates probes for waveform database viewable with Cadence Indago. Invokedf when WAVEs=1 ADV_DEBUG=1 passed to the make test command | +These scripts can be passed to Xcelium by the core-v-verif Makefiles. +The following scripts are currently supported: -### Coverage refinement files +| Script | Usage | +|------------|-------| +| probe.tcl | Generates probes for waveform database viewable with Cadence SimVision. Invoked when WAVES=1 passed to the make test command | +| indago.tcl | Generates probes for waveform database viewable with Cadence Indago. Invokedf when WAVES=1 ADV_DEBUG=1 passed to the make test command | -These XML files should be created using coverage tools such as IMC or Vmanager. These are used to generate coverage reports that focus on necessary coverage while removing exceptions that are unhittable or not significant for the design being verified. + +### Coverage Refinement Files + +These refinement files should be created using coverage tools such as IMC or Vmanager. +They are used to generate coverage reports that focus on necessary coverage, while removing exceptions that are unhittable or not significant for the design being verified. *Note that some files are automatically generated and some are manually maintained. This is indicated in the table.* -| File | Maintenance | Description | -|------|-------------|-------------| -| cv32e40s.hierarchy.vRefine | Manual | Removes hierarchies from coverage database that are not to be considered for coverage (e.g. testbench | -| cv32e40s.auto.vRefine | Automatic | Auto-generated refinements based on parameter usage for the CV32E40S without PULP extensions. *Do not manually edit* | -| cv32e40s.manual.vRefine | Manual | Manually added coverage exception based on deesign verification reviews. | +| File | Maintenance | Description | +|-----------------------------------|-------------|-------------| +| cv32e40s.non_dut_code_cov.vRefine | Manual | Removes non-DUT code coverage from coverage database, that are not to be considered for coverage (e.g. testbench) | +| cv32e40s.auto.vRefine | Automatic | Auto-generated refinements based on parameter usage for the CV32E40S without PULP extensions. *Do not manually edit* | +| cv32e40s.manual.vRefine | Manual | Manually added coverage exception based on deesign verification reviews. | diff --git a/cv32e40s/sim/tools/xrun/covfile.tcl b/cv32e40s/sim/tools/xrun/covfile.tcl index cc7f40e83f..7dac801908 100644 --- a/cv32e40s/sim/tools/xrun/covfile.tcl +++ b/cv32e40s/sim/tools/xrun/covfile.tcl @@ -20,6 +20,12 @@ set_optimize -vlog_prune_on # Set glitch strobes set_glitch_strobe 1ps +# Enable coverage for type parameterized modules +set_parameterized_module_coverage -type_parameters_only + +# Enable coverage for expressions containing inside operator +set_expr_scoring -inside + # ---------------------------------------------------------------------------------- # FSM coverage configruation # ---------------------------------------------------------------------------------- @@ -51,4 +57,4 @@ set_covergroup -new_instance_reporting # Instances/modules to remove from coverage # For performance and to avoid spurious warnings, remove these modules from code coverage collection # ---------------------------------------------------------------------------------- -deselect_coverage -all -instance uvmt_cv32e40s_tb.iss_wrap... \ No newline at end of file +deselect_coverage -all -instance uvmt_cv32e40s_tb.imperas_dv... diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.auto.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.auto.vRefine index 2318153d2d..1d95223d59 100644 --- a/cv32e40s/sim/tools/xrun/cv32e40s.auto.vRefine +++ b/cv32e40s/sim/tools/xrun/cv32e40s.auto.vRefine @@ -1,211 +1,1579 @@ - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.hierarchy.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.hierarchy.vRefine deleted file mode 100644 index c203c7ab2d..0000000000 --- a/cv32e40s/sim/tools/xrun/cv32e40s.hierarchy.vRefine +++ /dev/null @@ -1,31 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.manual_expression_cov_todo.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.manual_expression_cov_todo.vRefine new file mode 100644 index 0000000000..1a5d0be46d --- /dev/null +++ b/cv32e40s/sim/tools/xrun/cv32e40s.manual_expression_cov_todo.vRefine @@ -0,0 +1,164 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_assertions.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_assertions.vRefine new file mode 100644 index 0000000000..3cf31c41cc --- /dev/null +++ b/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_assertions.vRefine @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_interfaces.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_interfaces.vRefine new file mode 100644 index 0000000000..741045f769 --- /dev/null +++ b/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_interfaces.vRefine @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_other_modules.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_other_modules.vRefine new file mode 100644 index 0000000000..c93c08142b --- /dev/null +++ b/cv32e40s/sim/tools/xrun/cv32e40s.non_dut_code_cov_other_modules.vRefine @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.xsecure_trigger_express_cov.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.xsecure_trigger_express_cov.vRefine new file mode 100644 index 0000000000..bc1bc137da --- /dev/null +++ b/cv32e40s/sim/tools/xrun/cv32e40s.xsecure_trigger_express_cov.vRefine @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/tb/assertions/README.md b/cv32e40s/tb/assertions/README.md new file mode 100644 index 0000000000..784efd5f66 --- /dev/null +++ b/cv32e40s/tb/assertions/README.md @@ -0,0 +1 @@ +Directory for assertion files and related models and support logic. diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_fencei_assert.sv b/cv32e40s/tb/assertions/uvmt_cv32e40s_fencei_assert.sv similarity index 59% rename from cv32e40s/tb/uvmt/uvmt_cv32e40s_fencei_assert.sv rename to cv32e40s/tb/assertions/uvmt_cv32e40s_fencei_assert.sv index 9d23e2fec1..b1fdc91730 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_fencei_assert.sv +++ b/cv32e40s/tb/assertions/uvmt_cv32e40s_fencei_assert.sv @@ -16,50 +16,71 @@ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +`default_nettype none + + module uvmt_cv32e40s_fencei_assert import cv32e40s_pkg::*; import uvm_pkg::*; #( - parameter int PMA_NUM_REGIONS = 0, - parameter pma_region_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:'Z} + parameter int PMA_NUM_REGIONS = 0, + parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:'Z} )( - input clk_i, - input rst_ni, - - input fencei_flush_req_o, - input fencei_flush_ack_i, - - input wb_valid, - input wb_instr_valid, - input wb_sys_en, - input wb_sys_fencei_insn, - input [31:0] wb_pc, - input [31:0] wb_rdata, - input wb_buffer_state, - - input instr_req_o, - input [31:0] instr_addr_o, - input instr_gnt_i, - - input data_req_o, - input data_gnt_i, - input data_rvalid_i, - - input rvfi_valid, - input rvfi_intr, - input rvfi_dbg_mode + input wire clk_i, + input wire rst_ni, + + input wire fencei_flush_req_o, + input wire fencei_flush_ack_i, + + input wire wb_valid, + input wire wb_instr_valid, + input wire wb_sys_en, + input wire wb_sys_fencei_insn, + input wire [31:0] wb_pc, + input wire [31:0] wb_rdata, + input wire wb_buffer_state, + + input wire instr_req_o, + input wire [31:0] instr_addr_o, + input wire instr_gnt_i, + + input wire data_req_o, + input wire data_gnt_i, + input wire data_rvalid_i, + + uvma_rvfi_instr_if_t rvfi_if ); - localparam int CYCLE_COUNT = 6; + default clocking @(posedge clk_i); endclocking default disable iff !rst_ni; + string info_tag = "CV32E40S_FENCEI_ASSERT"; - logic is_fencei_in_wb; + localparam int CYCLE_COUNT = 6; + localparam int FENCEI_IDATA = 32'b 000000000000_00000_001_00000_0001111; + localparam int FENCEI_IMASK = 32'b 000000000000_00000_111_00000_1111111; + localparam int FENCE_IDATA = 32'b 000000000000_00000_000_00000_0001111; + localparam int FENCE_IMASK = 32'b 000000000000_00000_111_00000_1111111; + + + // Helper Signals/Functions + + logic is_fencei_in_wb; assign is_fencei_in_wb = wb_sys_fencei_insn && wb_sys_en && wb_instr_valid; + logic is_rvfiinstr_fencei; + assign is_rvfiinstr_fencei = ( + ((rvfi_if.rvfi_insn & FENCEI_IMASK) == FENCEI_IDATA) + ); + + logic is_rvfiinstr_fence; + assign is_rvfiinstr_fence = ( + ((rvfi_if.rvfi_insn & FENCE_IMASK) == FENCE_IDATA) + ); + int obi_outstanding; - always @(posedge clk_i, negedge rst_ni) begin + always_ff @(posedge clk_i, negedge rst_ni) begin if (~rst_ni) begin obi_outstanding <= 0; end else if (data_req_o && data_gnt_i && !data_rvalid_i) begin @@ -78,18 +99,27 @@ module uvmt_cv32e40s_fencei_assert end endfunction + + // vplan:ReqLow + a_req_stay_high: assert property ( fencei_flush_req_o && !fencei_flush_ack_i |=> fencei_flush_req_o ) else `uvm_error(info_tag, "req must not drop before ack"); + + // vplan:ReqLow + a_req_drop_lo: assert property ( fencei_flush_req_o && fencei_flush_ack_i |=> !fencei_flush_req_o ) else `uvm_error(info_tag, "req must drop after ack"); + + // vplan:ReqHigh + a_req_rise_before_retire: assert property ( $rose(is_fencei_in_wb) |-> @@ -100,12 +130,51 @@ module uvmt_cv32e40s_fencei_assert ) ) else `uvm_error(info_tag, "fencei shall not retire without seeing a rising flush req"); + + // vplan:ShadowingBranch + a_req_must_retire: assert property ( fencei_flush_req_o |-> - is_fencei_in_wb until_with wb_valid + is_fencei_in_wb until_with wb_valid ) else `uvm_error(info_tag, "if there is no retire then there can't be a req"); + cov_retire_without_req: cover property ( + $rose(is_fencei_in_wb) + ##0 + ( + !fencei_flush_req_o + throughout + ($fell(is_fencei_in_wb) [->1]) + ) + ); + + cov_no_retire: cover property ( + $rose(is_fencei_in_wb) + ##0 (!wb_valid throughout ($fell(is_fencei_in_wb) [->1])) + ); + + + // vplan:ShadowingBranch (TODO:silabs-robin New vplan item instead) + + a_req_must_rvfi_fencei: assert property ( + fencei_flush_req_o + |=> + (rvfi_if.rvfi_valid [->1]) ##0 + is_rvfiinstr_fencei + ) else `uvm_error(info_tag, "A handshake must results in fencei retire"); + + // (Just a helper/sanity assert complementing the above) + a_req_mustnt_rvfi_fence: assert property ( + fencei_flush_req_o + |=> + (rvfi_if.rvfi_valid [->1]) ##0 + !is_rvfiinstr_fence + ) else `uvm_error(info_tag, "A handshake must not results in a fence retire"); + + + // vplan:Fetching + property p_fetch_after_retire; int pc_next; (is_fencei_in_wb && wb_valid, pc_next={wb_pc[31:2],2'b00}+4) @@ -116,70 +185,119 @@ module uvmt_cv32e40s_fencei_assert ##0 (instr_addr_o == pc_next) ) or ( // Exception execution - rvfi_valid [->2:3] // retire: fencei, (optionally "rvfi_trap"), interrupt/debug handler - ##0 (rvfi_intr || rvfi_dbg_mode) + rvfi_if.rvfi_valid [->2:3] // retire: fencei, (optionally "rvfi_trap"), interrupt/debug handler + ##0 (rvfi_if.rvfi_intr || rvfi_if.rvfi_dbg_mode) ); endproperty + a_fetch_after_retire: assert property ( p_fetch_after_retire ) else `uvm_error(info_tag, "after fencei, the next-pc fetching cannot be forgone"); + + // vplan:AckWithold + a_stall_until_ack: assert property ( fencei_flush_req_o && !fencei_flush_ack_i |=> !$changed(wb_pc) ) else `uvm_error(info_tag, "WB stage must remain unchanged until the flush req is acked"); - property p_branch_after_retire; - int pc_next; - (fencei_flush_req_o, pc_next=wb_pc+4) - ##1 !fencei_flush_req_o - |=> - ( - wb_valid [->1:2] - ##0 (wb_pc == pc_next) - ) or ( - rvfi_valid [->2] - ##0 (rvfi_intr || rvfi_dbg_mode) + for (genvar i = 1; i <= 5; i++) begin: gen_ack_delayed + // "5" is an appropriate arbitrary upper limit + cov_ack_delayed: cover property ( + $rose(fencei_flush_req_o) + ##0 (!fencei_flush_ack_i) [*i] + ##1 fencei_flush_ack_i ); + end + + + // vplan:BranchInitiated + + sequence seq_branch_after_retire_ante; + $fell(fencei_flush_req_o) + ##0 + rvfi_if.rvfi_valid [->2] + ; + endsequence + + sequence seq_branch_after_retire_conse (pc_at_fencei); + (rvfi_if.rvfi_pc_rdata == pc_at_fencei + 32'd 4) + || rvfi_if.rvfi_intr + || rvfi_if.rvfi_dbg_mode + ; + endsequence + + property p_branch_after_retire; + logic [31:0] pc_at_fencei; + + (fencei_flush_req_o, pc_at_fencei = wb_pc) + ##1 + seq_branch_after_retire_ante + |-> + seq_branch_after_retire_conse (pc_at_fencei) + ; endproperty + a_branch_after_retire: assert property ( p_branch_after_retire ) else `uvm_error(info_tag, "the pc following fencei did not enter WB"); + cov_branch_after_retire: cover property ( + seq_branch_after_retire_ante + ##0 + ! rvfi_if.rvfi_intr + ##0 + ! rvfi_if.rvfi_dbg_mode + ); + + + // vplan:Flush + a_supress_datareq: assert property ( fencei_flush_req_o |-> !data_req_o ) else `uvm_error(info_tag, "obi data req shall not happen while fencei is flushing"); + + // vplan:MultiCycle + property p_fencei_quick_retire; $rose(is_fencei_in_wb) ##1 (fencei_flush_req_o && fencei_flush_ack_i); endproperty + a_cycle_count_minimum: assert property ( p_fencei_quick_retire implies (##1 !$rose(wb_instr_valid) [*CYCLE_COUNT-1]) - ) else `uvm_error(info_tag, "fencei shan't finish before the expected number of cycles"); - c_cycle_count_minimum: cover property ( + ) else `uvm_error(info_tag, "fencei shall not finish before the expected number of cycles"); + + cov_cycle_count_minimum: cover property ( p_fencei_quick_retire and (s_nexttime [CYCLE_COUNT] $rose(wb_instr_valid)) ); + + // vplan:ReqWaitLsu + property p_req_wait_bus; fencei_flush_req_o |-> - !data_rvalid_i throughout ( + !data_rvalid_i throughout ( $fell(wb_valid) [->1] ##1 (data_req_o && data_gnt_i) [->1] ); endproperty + a_req_wait_bus: assert property (p_req_wait_bus) else `uvm_error(info_tag, "flush req shall not come if rvalid is awaited"); + if (bufferable_in_config()) begin : gen_c_req_wait_bus - c_req_wait_bus: cover property ( + cov_req_wait_bus: cover property ( $rose(is_fencei_in_wb) ##1 ( is_fencei_in_wb throughout ( @@ -190,40 +308,39 @@ module uvmt_cv32e40s_fencei_assert ); end + + // vplan:ReqWaitObi + property p_req_wait_outstanding; fencei_flush_req_o |-> (obi_outstanding == 0); endproperty + a_req_wait_outstanding: assert property (p_req_wait_outstanding) else `uvm_error(info_tag, "flush req shall not come if obi has outstanding transactions"); + if (bufferable_in_config()) begin : gen_c_req_wait_outstanding_1 - c_req_wait_outstanding_1: cover property ( + cov_req_wait_outstanding_1: cover property ( is_fencei_in_wb throughout ((obi_outstanding >= 1) ##0 (fencei_flush_req_o [->1])) ); end - - property p_req_wait_buffer; - is_fencei_in_wb && (wb_buffer_state == WBUF_FULL) |-> - !fencei_flush_req_o throughout( - (data_rvalid_i && (wb_buffer_state == WBUF_EMPTY)) [->1] - ); - endproperty - a_req_wait_buffer: assert property(p_req_wait_buffer) - else `uvm_error(info_tag, "fencei_flush_req_o should be held low until write buffer is empty"); + // vplan:ReqWaitWritebuffer + property p_req_wait_buffer; + is_fencei_in_wb && (wb_buffer_state == WBUF_FULL) + |-> + !fencei_flush_req_o throughout ( + (data_rvalid_i && (wb_buffer_state == WBUF_EMPTY)) [->1] + ); + endproperty - // TODO:ropeders assert fencei flush req explicitly vs X interface queue (not just vs rvalid) + a_req_wait_buffer: assert property( + p_req_wait_buffer + ) else `uvm_error(info_tag, "fencei_flush_req_o should be held low until write buffer is empty"); - for (genvar i = 1; i <= 5; i++) begin: gen_ack_delayed - // "5" is an appropriate arbitrary upper limit - c_ack_delayed: cover property ( - $rose(fencei_flush_req_o) - ##0 (!fencei_flush_ack_i) [*i] - ##1 fencei_flush_ack_i - ); - end + // vplan:AckChange covergroup cg_reqack(string name) @(posedge clk_i); option.per_instance = 1; @@ -245,18 +362,17 @@ module uvmt_cv32e40s_fencei_assert illegal_bins il = binsof(cp_req.fell) && binsof(cp_ack.rose); } endgroup - cg_reqack reqack_cg = new("reqack"); - c_no_retire: cover property ( - $rose(is_fencei_in_wb) - ##0 (!wb_valid throughout ($fell(is_fencei_in_wb) [->1])) - ); + cg_reqack reqack_cg = new("reqack_cg"); + + + // vplan:UnusedFields covergroup cg_reserved(string name) @(posedge clk_i); option.per_instance = 1; option.name = name; - // Just a handfull of different values for reserved to-be-ignored fields + // A handfull of different values for (ignored) reserved fields cp_imm: coverpoint wb_rdata[31:20] iff (is_fencei_in_wb && wb_valid) { bins b[4] = {[0:$]}; } @@ -267,6 +383,11 @@ module uvmt_cv32e40s_fencei_assert bins b[4] = {[0:$]}; } endgroup - cg_reserved reserved_cg = new("reserved"); + + cg_reserved reserved_cg = new("reserved_cg"); + endmodule : uvmt_cv32e40s_fencei_assert + + +`default_nettype wire diff --git a/cv32e40s/tb/assertions/uvmt_cv32e40s_pma_model.sv b/cv32e40s/tb/assertions/uvmt_cv32e40s_pma_model.sv new file mode 100644 index 0000000000..ef45573189 --- /dev/null +++ b/cv32e40s/tb/assertions/uvmt_cv32e40s_pma_model.sv @@ -0,0 +1,136 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +`default_nettype none + + +module uvmt_cv32e40s_pma_model + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; +#( + parameter logic [31:0] DM_REGION_START, + parameter logic [31:0] DM_REGION_END, + parameter bit IS_INSTR_SIDE, + parameter int PMA_NUM_REGIONS, + parameter pma_cfg_t PMA_CFG [PMA_NUM_REGIONS-1:0] +)( + input wire clk, + input wire rst_n, + + input wire core_trans_pushpop_i, + input wire dbg, + input wire load_access, + input wire misaligned_access_i, + input wire [31:0] addr_i, + input wire jvt_t jvt_q, + + output wire pma_status_t pma_status_o +); + + + localparam int MAX_REGIONS = 16; + + localparam pma_cfg_t CFG_DEFAULT = '{ + default : '0, + main : (PMA_NUM_REGIONS == 0) + }; + + localparam pma_cfg_t CFG_DEBUG = '{ + default : '0, + main : 1'b 1 + }; + + var logic [PMA_MAX_REGIONS-1:0] match_list; + function automatic logic is_match_on(int i); + logic [33:0] low = {PMA_CFG[i].word_addr_low, 2'b 00}; + logic [33:0] high = {PMA_CFG[i].word_addr_high, 2'b 00}; + return ((low <= addr_i) && (addr_i < high)); + endfunction + for (genvar i = 0; i < MAX_REGIONS; i++) begin: gen_match_list + always_comb match_list[i] = (i < PMA_NUM_REGIONS) && is_match_on(i); + end + + var pma_cfg_t cfg_matched; + var logic have_match; + var logic[31:0] match_idx; + always_comb begin + have_match = '0; + cfg_matched = 'X; + match_idx = 'X; + for (int i = 0; i < PMA_NUM_REGIONS; i++) begin + if (pma_status_o.match_list[i]) begin + have_match = 1; + cfg_matched = PMA_CFG[i]; + match_idx = i; + break; + end + end + end + + + wire logic accesses_dmregion; + assign accesses_dmregion = + ((DM_REGION_START <= addr_i) && (addr_i <= DM_REGION_END)); + + wire logic override_dm; + assign override_dm = dbg && accesses_dmregion; + + var pma_cfg_t cfg_effective; + always_comb begin + cfg_effective = + override_dm + ? CFG_DEBUG + : (have_match ? cfg_matched : CFG_DEFAULT); + + cfg_effective.bufferable = + cfg_effective.bufferable && !IS_INSTR_SIDE && !load_access; + end + + wire logic allow_instr; + assign allow_instr = cfg_effective.main; + + wire logic allow_data; + assign allow_data = + cfg_effective.main || + (!misaligned_access_i && !core_trans_pushpop_i); + + wire logic accesses_jvt; + assign accesses_jvt = + (jvt_q <= addr_i) && + (addr_i <= (jvt_q + (4 * 8'b 1111_1111))); + + assign pma_status_o.allow = + override_dm || + (IS_INSTR_SIDE ? allow_instr : allow_data); + assign pma_status_o.main = cfg_effective.main; + assign pma_status_o.bufferable = cfg_effective.bufferable; + assign pma_status_o.cacheable = cfg_effective.cacheable; + assign pma_status_o.integrity = cfg_effective.integrity; + assign pma_status_o.override_dm = override_dm; + assign pma_status_o.accesses_dmregion = accesses_dmregion; + assign pma_status_o.accesses_jvt = accesses_jvt; + assign pma_status_o.match_list = match_list; + assign pma_status_o.have_match = have_match; + assign pma_status_o.match_idx = match_idx; + + +endmodule : uvmt_cv32e40s_pma_model + + +`default_nettype wire diff --git a/cv32e40s/tb/assertions/uvmt_cv32e40s_pmp_model.sv b/cv32e40s/tb/assertions/uvmt_cv32e40s_pmp_model.sv new file mode 100644 index 0000000000..02dc240efb --- /dev/null +++ b/cv32e40s/tb/assertions/uvmt_cv32e40s_pmp_model.sv @@ -0,0 +1,451 @@ +// Copyright 2022 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + +`default_nettype none + +module uvmt_cv32e40s_pmp_model + import cv32e40s_pkg::*; + import uvm_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + #( + parameter int PMP_GRANULARITY, + parameter int PMP_NUM_REGIONS, + parameter logic [31:0] DM_REGION_START, + parameter logic [31:0] DM_REGION_END + ) + ( + // Clock and Reset + input wire clk, + input wire rst_n, + + // CSRs + input wire pmp_csr_t csr_pmp_i, + + // Privilege Mode + input wire privlvl_t priv_lvl_i, + + // Access Checking + input wire [33:0] pmp_req_addr_i, + input wire pmp_req_e pmp_req_type_i, + input wire pmp_req_err_o, + + // Debug Mode + input wire debug_mode, + + // Match Status + output match_status_t match_status_o + ); + + + // Defines + + `define max(a,b) ((a) > (b) ? (a) : (b)) + + + // Check legal reasons to accept access + + always_comb begin + match_status_o = {<<{'0}}; + + // Lock Detection + for (int region = 0; region < PMP_NUM_REGIONS; region++) begin + match_status_o.is_any_locked = csr_pmp_i.cfg[region].lock ? 1'b1 : match_status_o.is_any_locked; + end + + // Match Detection + for (int i = 0; i < PMP_NUM_REGIONS; i++) begin + automatic logic [$clog2(PMP_MAX_REGIONS)-1:0] region = i; + + if (is_match_na4(region) || is_match_tor(region) || is_match_napot(region)) begin + match_status_o.val_index = region; + match_status_o.is_matched = 1'b1; + break; + end + end + + // Debug Module Override + match_status_o.is_dm_override = + debug_mode && ((DM_REGION_START <= pmp_req_addr_i) && (pmp_req_addr_i <= DM_REGION_END)); + + // Allowed access whitelist table + if (match_status_o.is_matched) begin + match_status_o.is_locked = csr_pmp_i.cfg[match_status_o.val_index].lock; + if (csr_pmp_i.mseccfg.mml === 1'b1) begin + case (pmp_req_type_i) + PMP_ACC_READ: begin + // ------------------------------------------------------------ + // Read access U-Mode + // ------------------------------------------------------------ + // Read access U-mode - Shared data region, U-mode RO + match_status_o.val_access_allowed_reason.r_umode_mml_w = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Read access U-mode - Shared data region, U-mode RW + match_status_o.val_access_allowed_reason.r_umode_mml_wx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Read access U-mode - Read flag + match_status_o.val_access_allowed_reason.r_umode_mml_r = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Read access U-mode - Read/execute flag + match_status_o.val_access_allowed_reason.r_umode_mml_rx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Read access U-mode - Read/Write flag + match_status_o.val_access_allowed_reason.r_umode_mml_rw = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Read access U-mode - Read/Write/Execute flag + match_status_o.val_access_allowed_reason.r_umode_mml_rwx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Read access U-mode - Locked shared region + match_status_o.val_access_allowed_reason.r_umode_mml_lrwx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + + // ------------------------------------------------------------ + // Read access M-Mode + // ------------------------------------------------------------ + // Read access M-mode - Shared data region, U-mode RO + match_status_o.val_access_allowed_reason.r_mmode_mml_w = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Read access M-mode - Shared data region, U-mode RW + match_status_o.val_access_allowed_reason.r_mmode_mml_wx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Read access M-mode - Shared code region, M-mode RX + match_status_o.val_access_allowed_reason.r_mmode_mml_lwx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Read access M-mode - Locked/Read + match_status_o.val_access_allowed_reason.r_mmode_mml_lr = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Read access M-mode - Locked read/execute region + match_status_o.val_access_allowed_reason.r_mmode_mml_lrx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Read access M-mode - Locked read/write region + match_status_o.val_access_allowed_reason.r_mmode_mml_lrw = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Read access M-mode - Locked shared region + match_status_o.val_access_allowed_reason.r_mmode_mml_lrwx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + end // PMP_ACC_READ + + PMP_ACC_WRITE: begin + // ------------------------------------------------------------ + // Write access U-Mode + // ------------------------------------------------------------ + // Write access U-mode - Shared data region, U-mode RW + match_status_o.val_access_allowed_reason.w_umode_mml_wx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Write access U-mode - Read/write region + match_status_o.val_access_allowed_reason.w_umode_mml_rw = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Write access U-mode - Read/write/execute region + match_status_o.val_access_allowed_reason.w_umode_mml_rwx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + + // ------------------------------------------------------------ + // Write access M-Mode + // ------------------------------------------------------------ + // Write access M-mode - Shared data region, U-mode RO + match_status_o.val_access_allowed_reason.w_mmode_mml_w = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Write access M-mode - Shared data region, U-mode RW + match_status_o.val_access_allowed_reason.w_mmode_mml_wx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Write access M-mode - Locked read/write region + match_status_o.val_access_allowed_reason.w_mmode_mml_lrw = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + end // PMP_ACC_WRITE + + PMP_ACC_EXEC: begin + // ------------------------------------------------------------ + // Execute access U-Mode + // ------------------------------------------------------------ + // Execute access U-mode - Executable region + match_status_o.val_access_allowed_reason.x_umode_mml_x = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Execute access U-mode - Read/execute region + match_status_o.val_access_allowed_reason.x_umode_mml_rx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Execute access U-mode - Read/write/execute region + match_status_o.val_access_allowed_reason.x_umode_mml_rwx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Execute access U-mode - Locked shared code region, X only + match_status_o.val_access_allowed_reason.x_umode_mml_lw = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Execute access U-mode - Locked shared code region, M-mode RX + match_status_o.val_access_allowed_reason.x_umode_mml_lwx = ( + priv_lvl_i == PRIV_LVL_U && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + + // ------------------------------------------------------------ + // Execute access M-Mode + // ------------------------------------------------------------ + // Execute access M-mode - Locked executable region + match_status_o.val_access_allowed_reason.x_mmode_mml_lx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Execute access M-mode - Locked shared code region, X-only + match_status_o.val_access_allowed_reason.x_mmode_mml_lw = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b0 + ); + // Execute access M-mode - Locked shared code region, M-mode RX + match_status_o.val_access_allowed_reason.x_mmode_mml_lwx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + // Execute access M-mode - Locked Read/Execute region + match_status_o.val_access_allowed_reason.x_mmode_mml_lrx = ( + priv_lvl_i == PRIV_LVL_M && + csr_pmp_i.cfg[match_status_o.val_index].lock == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].read == 1'b1 && + csr_pmp_i.cfg[match_status_o.val_index].write == 1'b0 && + csr_pmp_i.cfg[match_status_o.val_index].exec == 1'b1 + ); + end // PMP_ACC_EXEC + endcase // case(pmp_req_type_i) + + end else begin // mmwp low + case ( priv_lvl_i ) + PRIV_LVL_M: + case ( {pmp_req_type_i, match_status_o.is_locked} ) + { PMP_ACC_READ, 1'b1 }: match_status_o.val_access_allowed_reason.r_mmode_lr = csr_pmp_i.cfg[match_status_o.val_index].read; + { PMP_ACC_READ, 1'b0 }: match_status_o.val_access_allowed_reason.r_mmode_r = 1'b1; + { PMP_ACC_WRITE, 1'b1 }: match_status_o.val_access_allowed_reason.w_mmode_lw = csr_pmp_i.cfg[match_status_o.val_index].write; + { PMP_ACC_WRITE, 1'b0 }: match_status_o.val_access_allowed_reason.w_mmode_w = 1'b1; + { PMP_ACC_EXEC, 1'b1 }: match_status_o.val_access_allowed_reason.x_mmode_lx = csr_pmp_i.cfg[match_status_o.val_index].exec; + { PMP_ACC_EXEC, 1'b0 }: match_status_o.val_access_allowed_reason.x_mmode_x = 1'b1; + endcase + PRIV_LVL_U: + case ( pmp_req_type_i ) + PMP_ACC_READ: match_status_o.val_access_allowed_reason.r_umode_r = csr_pmp_i.cfg[match_status_o.val_index].read; + PMP_ACC_WRITE: match_status_o.val_access_allowed_reason.w_umode_w = csr_pmp_i.cfg[match_status_o.val_index].write; + PMP_ACC_EXEC: match_status_o.val_access_allowed_reason.x_umode_x = csr_pmp_i.cfg[match_status_o.val_index].exec; + endcase + endcase // case (priv_lvl_i) + + end + + match_status_o.is_rwx_ok = |match_status_o.val_access_allowed_reason; + end else begin + // ------------------------------------------------------------ + // NO MATCH REGION + // ------------------------------------------------------------ + // No matching region found, allow only M-access, and only if MMWP bit is not set + case ( {pmp_req_type_i, priv_lvl_i} ) + { PMP_ACC_READ, PRIV_LVL_M }: + match_status_o.val_access_allowed_reason.r_mmode_nomatch_nommwp_r = !csr_pmp_i.mseccfg.mmwp; + { PMP_ACC_WRITE, PRIV_LVL_M }: + match_status_o.val_access_allowed_reason.w_mmode_nomatch_nommwp_w = !csr_pmp_i.mseccfg.mmwp; + { PMP_ACC_EXEC, PRIV_LVL_M }: + match_status_o.val_access_allowed_reason.x_mmode_nomatch_nommwp_x = !csr_pmp_i.mseccfg.mmwp && !csr_pmp_i.mseccfg.mml; + endcase + match_status_o.is_access_allowed_no_match = |match_status_o.val_access_allowed_reason; + end + + // Access is allowed if any one of the above conditions matches (or DM override) + match_status_o.is_access_allowed = + |match_status_o.val_access_allowed_reason || match_status_o.is_dm_override; + end + + + // Helper functions + + function automatic int is_match_na4(input logic[$clog2(PMP_MAX_REGIONS)-1:0] region); + is_match_na4 = (csr_pmp_i.cfg[region].mode == PMP_MODE_NA4) && + (csr_pmp_i.addr[region][33:2] == pmp_req_addr_i[33:2]); + endfunction : is_match_na4 + + function automatic logic is_match_tor(input logic[$clog2(PMP_MAX_REGIONS)-1:0] region); + logic [33:2+PMP_GRANULARITY] req, hi, lo; + + req = pmp_req_addr_i[33:2+PMP_GRANULARITY]; + hi = csr_pmp_i.addr[region][33:2+PMP_GRANULARITY]; + lo = (region > 0) ? csr_pmp_i.addr[region - 1'b1][33:2+PMP_GRANULARITY] : '0; + + is_match_tor = (csr_pmp_i.cfg[region].mode == PMP_MODE_TOR) && + (lo <= req) && + (req < hi); + endfunction : is_match_tor + + function automatic int is_match_napot(input logic[$clog2(PMP_MAX_REGIONS)-1:0] region); + logic [31:0] mask = gen_mask(region); + logic [31:0] csr_addr_masked = csr_pmp_i.addr[region][33:2] & mask; + logic [31:0] req_addr_masked = pmp_req_addr_i[33:2] & mask; + + is_match_napot = (csr_pmp_i.cfg[region].mode == PMP_MODE_NAPOT) && + (csr_addr_masked == req_addr_masked); + endfunction : is_match_napot + + function automatic logic[31:0] gen_mask(input logic[$clog2(PMP_MAX_REGIONS)-1:0] i); + logic [31:0] mask; + logic [31:0] csr_addr; + + mask = '1; + if (PMP_GRANULARITY >= 1) begin + mask[`max(PMP_GRANULARITY-1, 0) : 0] = '0; // TODO remove or assume+assert? + end + + csr_addr = csr_pmp_i.addr[i][33:2]; + if (PMP_GRANULARITY >= 2) begin + csr_addr[`max(PMP_GRANULARITY-2, 0) : 0] = '1; // TODO should be assumed+assert? + end + + for (int j = 0; j < 32; j++) begin + mask[j] = 0; + if (csr_addr[j] == 0) begin + break; + end + end + + return mask; + endfunction + +endmodule : uvmt_cv32e40s_pmp_model + +`default_nettype wire diff --git a/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv b/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv index 390b64c41f..3a116df7ca 100644 --- a/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv +++ b/cv32e40s/tb/core/cv32e40s_tb_wrapper.sv @@ -22,9 +22,7 @@ module cv32e40s_tb_wrapper BOOT_ADDR = 'h80, DM_HALTADDRESS = 32'h1A11_0800, HART_ID = 32'h0000_0000, - IMP_ID = 32'h0000_0000, - // Parameters used by DUT - NUM_MHPMCOUNTERS = 1 + IMP_PATCH_ID = 4'h0 ) (input logic clk_i, input logic rst_ni, @@ -72,8 +70,7 @@ module cv32e40s_tb_wrapper // .PULP_XPULP ( PULP_XPULP ), // .PULP_CLUSTER ( PULP_CLUSTER ), // .FPU ( FPU ), -// .PULP_ZFINX ( PULP_ZFINX ), -// .NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS )) +// .PULP_ZFINX ( PULP_ZFINX )) // core_log_i( // .clk_i ( cv32e40s_core_i.id_stage_i.clk ), // .is_decoding_i ( cv32e40s_core_i.id_stage_i.is_decoding_o ), @@ -83,10 +80,7 @@ module cv32e40s_tb_wrapper // ); // instantiate the core - cv32e40s_core #( - .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS) - ) - cv32e40s_core_i + cv32e40s_core cv32e40s_core_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -96,7 +90,7 @@ module cv32e40s_tb_wrapper .boot_addr_i ( BOOT_ADDR ), .dm_halt_addr_i ( DM_HALTADDRESS ), .mhartid_i ( HART_ID ), - .mimpid_i ( IMP_ID ), + .mimpid_patch_i ( IMP_PATCH_ID ), .instr_req_o ( instr_req ), .instr_gnt_i ( instr_gnt ), diff --git a/cv32e40s/tb/core/tb_top_verilator.sv b/cv32e40s/tb/core/tb_top_verilator.sv index 2361e8ec47..b9438579de 100644 --- a/cv32e40s/tb/core/tb_top_verilator.sv +++ b/cv32e40s/tb/core/tb_top_verilator.sv @@ -89,8 +89,7 @@ module tb_top_verilator .RAM_ADDR_WIDTH (RAM_ADDR_WIDTH), .BOOT_ADDR (BOOT_ADDR), .DM_HALTADDRESS (32'h1A11_0800), - .HART_ID (32'h0000_0000), - .NUM_MHPMCOUNTERS (1) + .HART_ID (32'h0000_0000) ) cv32e40s_tb_wrapper_i (.clk_i ( clk_i ), diff --git a/cv32e40s/tb/ldgen/ldgen_tb.sv b/cv32e40s/tb/ldgen/ldgen_tb.sv index 7ff946e50c..d96d078ca4 100644 --- a/cv32e40s/tb/ldgen/ldgen_tb.sv +++ b/cv32e40s/tb/ldgen/ldgen_tb.sv @@ -14,19 +14,25 @@ // limitations under the License. `include "cv32e40s_pkg.sv" +`include "uvmt_cv32e40s_base_test_pkg.sv" -import cv32e40s_pkg::pma_region_t; +import uvm_pkg::*; +import cv32e40s_pkg::pma_cfg_t; +import uvmt_cv32e40s_base_test_pkg::*; -`include "uvmt_cv32e40s_constants.sv" `include "pma_adapted_mem_region_gen.sv" `include "cv32e40s_ldgen.sv" module ldgen_tb; + cv32e40s_ldgen_c linker_generator; initial begin : ldgen_start - cv32e40s_ldgen_c linker_generator; linker_generator = new(); linker_generator.gen_pma_linker_scripts(); end + final begin : ldgen_end + linker_generator.display_message("Linker script generation complete"); + end + endmodule : ldgen_tb diff --git a/cv32e40s/tb/uvmt/imperas_dummy_pkg.flist b/cv32e40s/tb/uvmt/imperas_dummy_pkg.flist new file mode 100644 index 0000000000..0b9a8a58cd --- /dev/null +++ b/cv32e40s/tb/uvmt/imperas_dummy_pkg.flist @@ -0,0 +1 @@ +${DV_UVMT_PATH}/uvmt_cv32e40s_imperas_dummy_pkg.sv diff --git a/cv32e40s/tb/uvmt/imperas_dv.flist b/cv32e40s/tb/uvmt/imperas_dv.flist new file mode 100644 index 0000000000..35206e8395 --- /dev/null +++ b/cv32e40s/tb/uvmt/imperas_dv.flist @@ -0,0 +1,26 @@ +// +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +/////////////////////////////////////// +// ImperasDV +// - The traditional location of the Imperas reference model is under vendor_lib in this repo. +// - The proposed new location of the Imperas reference model is in an installation directory +// that is external to this repo. +// + +// ImperasDV test bench wrapper +${TBSRC_HOME}/uvmt/uvmt_cv32e40s_imperas_dv_wrap.sv + diff --git a/cv32e40s/tb/uvmt/imperas_dv_deps.flist b/cv32e40s/tb/uvmt/imperas_dv_deps.flist new file mode 100644 index 0000000000..71aecb9f53 --- /dev/null +++ b/cv32e40s/tb/uvmt/imperas_dv_deps.flist @@ -0,0 +1,27 @@ +// +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +/////////////////////////////////////// +// ImperasDV +// - The traditional location of the Imperas reference model is under vendor_lib in this repo. +// - The proposed new location of the Imperas reference model is in an installation directory +// that is external to this repo. +// + ++incdir+${IMPERAS_HOME}/ImpProprietary/include/host +-f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f +-f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f + diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_fifo.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_fifo.sv new file mode 100644 index 0000000000..ba0a61bdd8 --- /dev/null +++ b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_fifo.sv @@ -0,0 +1,107 @@ +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +/* + +This is a configurable FIFO. +It inputs item_in when add_item is set. +It always outputs the "oldest" fifo item. +It shifts the fifo on the next clock cycle when shift_fifo is set. + +The figure shows how the FIFO behaves: + +t1: | t2: | t3: | +add_item | add_item | !add_item | +&& !shift_fifo | && !shift_fifo | && !shift_fifo | +_____________ | _____________ | _____________ | +| | | | | | | | | | | | | | | +| | | X | | | i1| | X | | | i1| i2| X | | +|___|___|___| | |___|___|___| | |___|___|___| | + ^ ^ ^ +t4: | t5: | t6: | +!add_item | !add_item | !add_item | +&& shift_fifo | && shift_fifo | && !shift_fifo | +_____________ | _____________ | _____________ | +| | | | | | | | | | | | | | | +| i1| i2| X | | | i2| | X | | | | | X | | +|___|___|___| | |___|___|___| | |___|___|___| | + ^ ^ ^ +t7: | t8: | t9: | +add_item | add_item | !add_item | +&& !shift_fifo | && shift_fifo | && !shift_fifo | +_____________ | _____________ | _____________ | +| | | | | | | | | | | | | | | +| | | X | | | i3| | X | | | i4| | X | | +|___|___|___| | |___|___|___| | |___|___|___| | + ^ ^ ^ +*/ + +module uvmt_cv32e40s_sl_fifo + import cv32e40s_pkg::*; + #( + parameter type FIFO_TYPE_T = obi_inst_req_t, + parameter FIFO_SIZE = 2 + ) + ( + input logic rst_ni, + input logic clk_i, + + input logic add_item, + input logic shift_fifo, + + input FIFO_TYPE_T item_in, + output FIFO_TYPE_T item_out + ); + + // Extend the FIFO with one elemet to make sure the pointer will not underflow + localparam FIFO_PTR_SIZE = $clog2(FIFO_SIZE+1); + + // Extend the FIFO with one elemet to make sure the pointer will not underflow + FIFO_TYPE_T [FIFO_SIZE:0] fifo; + logic [FIFO_PTR_SIZE-1:0] ptr; + FIFO_TYPE_T zero; + + assign item_out = fifo[FIFO_SIZE]; + + always_ff @(posedge clk_i, negedge rst_ni) begin + if(!rst_ni) begin + fifo <= '0; + ptr <= FIFO_SIZE; + zero <= '0; + end else begin + if (add_item && !shift_fifo) begin + fifo[ptr] <= item_in; + ptr <= ptr - 1'b1; + + end else if (!add_item && shift_fifo) begin + ptr <= ptr + 1'b1; + + fifo[FIFO_SIZE:1] <= fifo[FIFO_SIZE-1:0]; + fifo[0] <= zero; + + // If used correctly the fifo should not shift unless there already is an item in the fifo. + // For safety we add this as a requirement for entering this fifo state. + end else if (add_item && shift_fifo && ptr < FIFO_SIZE) begin + fifo[FIFO_SIZE:1] <= fifo[FIFO_SIZE-1:0]; + fifo[0] <= zero; + + fifo[ptr+1'b1] <= item_in; + end + end + end + + +endmodule : uvmt_cv32e40s_sl_fifo diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_obi_phases_monitor.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_obi_phases_monitor.sv new file mode 100644 index 0000000000..14883bacc4 --- /dev/null +++ b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_obi_phases_monitor.sv @@ -0,0 +1,73 @@ + +module uvmt_cv32e40s_sl_obi_phases_monitor + import uvm_pkg::*; + ( + input logic clk_i, + input logic rst_ni, + + input logic obi_req, + input logic obi_gnt, + input logic obi_rvalid, + + + // continued address and respons phase indicators, indicates address and respons phases + // of more than one cycle + output logic addr_ph_cont, + output logic resp_ph_cont, + + // address phase counter, used to verify no response phase preceedes an address phase + output integer v_addr_ph_cnt + ); + + logic addr_ph_valid; + logic rsp_ph_valid; + logic obi_rready; + + assign obi_rready = 1'b1; //This is an assumption + + assign addr_ph_valid = obi_req == 1'b1 && obi_gnt == 1'b1; + assign rsp_ph_valid = obi_rready == 1'b1 && obi_rvalid == 1'b1; + + + always @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + addr_ph_cont <= 1'b0; + end + else begin + if (obi_req == 1'b1 && obi_gnt == 1'b0) begin + addr_ph_cont <= 1'b1; + end + else begin + addr_ph_cont <= 1'b0; + end + end + end + + always @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + resp_ph_cont <= 1'b0; + end + else begin + if (obi_rvalid == 1'b1 && obi_rready == 1'b0) begin + resp_ph_cont <= 1'b1; + end + else begin + resp_ph_cont <= 1'b0; + end + end + end + + always @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + v_addr_ph_cnt <= '0; + end + else begin + if (addr_ph_valid && !rsp_ph_valid) begin + v_addr_ph_cnt <= v_addr_ph_cnt + 1'b1; + end + else if (!addr_ph_valid && rsp_ph_valid && v_addr_ph_cnt > 0) begin + v_addr_ph_cnt <= v_addr_ph_cnt - 1'b1; + end + end + end +endmodule : uvmt_cv32e40s_sl_obi_phases_monitor diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match.sv new file mode 100644 index 0000000000..a009b835b6 --- /dev/null +++ b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match.sv @@ -0,0 +1,172 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_sl_trigger_match + import uvmt_cv32e40s_base_test_pkg::*; + ( + input logic clk_i, + input logic rst_ni, + output logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] trigger_match_mem, + output logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] trigger_match_execute, + output logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] trigger_match_exception, + output logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] is_trigger_match + ); + + localparam TDATA1_RESET = 32'h2800_1000; + localparam TDATA1_ET_M_MODE = 9; + localparam TDATA1_ET_U_MODE = 6; + localparam TDATA1_LSB_TYPE = 28; + localparam TDATA1_MSB_TYPE = 31; + localparam TDATA1_LOAD = 0; + localparam TDATA1_STORE = 1; + localparam TDATA1_EXECUTE = 2; + localparam TDATA1_M2_M6_U_MODE = 3; + localparam TDATA1_M2_M6_M_MODE = 6; + localparam TDATA1_LSB_MATCH = 7; + localparam TDATA1_MSB_MATCH = 10; + localparam TDATA1_MATCH_WHEN_EQUAL = 0; + localparam TDATA1_MATCH_WHEN_GREATER_OR_EQUAL = 2; + localparam TDATA1_MATCH_WHEN_LESSER = 3; + + localparam MAX_MEM_ACCESS = 13; //Push and pop can do 13 memory access. XIF can potentially do more (TODO (xif): check this when merging to cv32e40x) + + + // signals to keep track of the conditions for triggering. + logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] system_conditions; + logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] csr_conditions_m2_m6; + logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] csr_conditions_etrigger; + + // keep track of what obi memory transactions that seems to trigger + logic [MAX_MEM_ACCESS:0][CORE_PARAM_DBG_NUM_TRIGGERS-1:0] trigger_match_mem_op; + + // check if there are execute or exception trigger matches. + logic execute_exception_trigger_match; + + + generate + + assign system_conditions = rvfi.rvfi_valid && !rvfi.rvfi_dbg_mode; + + for (genvar t = 0; t < CORE_PARAM_DBG_NUM_TRIGGERS; t++) begin + + assign csr_conditions_m2_m6[t] = + (in_support_if.tdata1_array[t][TDATA1_MSB_TYPE:TDATA1_LSB_TYPE] == 2 || + in_support_if.tdata1_array[t][TDATA1_MSB_TYPE:TDATA1_LSB_TYPE] == 6) && + ((rvfi.is_mmode && in_support_if.tdata1_array[t][TDATA1_M2_M6_M_MODE]) || + (rvfi.is_umode && in_support_if.tdata1_array[t][TDATA1_M2_M6_U_MODE])); + + + assign csr_conditions_etrigger[t] = + (in_support_if.tdata1_array[t][TDATA1_MSB_TYPE:TDATA1_LSB_TYPE] == 5) && + ((rvfi.is_mmode && in_support_if.tdata1_array[t][TDATA1_ET_M_MODE]) || + (rvfi.is_umode && in_support_if.tdata1_array[t][TDATA1_ET_U_MODE])); + + + // Trigger match instruction: + assign trigger_match_execute[t] = csr_conditions_m2_m6[t] + && in_support_if.tdata1_array[t][TDATA1_EXECUTE] + && system_conditions + && !rvfi.rvfi_trap.clicptr //TODO: KD: burde finne ut hvorfor clicptr er et unntak. + && (((rvfi.rvfi_pc_rdata == in_support_if.tdata2_array[t]) && in_support_if.tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_EQUAL) + || ((rvfi.rvfi_pc_rdata >= in_support_if.tdata2_array[t]) && in_support_if.tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_GREATER_OR_EQUAL) + || ((rvfi.rvfi_pc_rdata < in_support_if.tdata2_array[t]) && in_support_if.tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_LESSER)); + + // Trigger match exception: + assign trigger_match_exception[t] = system_conditions + && !trigger_match_execute + && csr_conditions_etrigger[t] + && rvfi.rvfi_trap.exception + && in_support_if.tdata2_array[t][rvfi.rvfi_trap.exception_cause[$clog2(32)-1:0]]; + + end + endgenerate + + + // Trigger match load and store: + + generate + for (genvar mem_op = 0; mem_op < 13; mem_op++) begin : trigger_match_memory_operation + uvmt_cv32e40s_sl_trigger_match_mem + #( + .MEMORY_OPERATION_NR (mem_op) + ) + sl_trigger_match_mem + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + .csr_conditions_m2_m6 (csr_conditions_m2_m6), + .tdata1_array (in_support_if.tdata1_array), + .tdata2_array (in_support_if.tdata2_array), + .trigger_match_execute (trigger_match_execute), + .trigger_match_mem (trigger_match_mem_op[mem_op]) + ); + end : trigger_match_memory_operation + endgenerate + + + assign execute_exception_trigger_match = (|trigger_match_execute) || (|trigger_match_exception); + + always_comb begin + if (trigger_match_mem_op[0] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[0]; + + end else if (trigger_match_mem_op[1] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[1]; + + end else if (trigger_match_mem_op[2] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[2]; + + end else if (trigger_match_mem_op[3] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[3]; + + end else if (trigger_match_mem_op[4] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[4]; + + end else if (trigger_match_mem_op[5] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[5]; + + end else if (trigger_match_mem_op[6] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[6]; + + end else if (trigger_match_mem_op[7] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[7]; + + end else if (trigger_match_mem_op[8] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[8]; + + end else if (trigger_match_mem_op[9] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[9]; + + end else if (trigger_match_mem_op[10] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[10]; + + end else if (trigger_match_mem_op[11] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[11]; + + end else if (trigger_match_mem_op[12] && !execute_exception_trigger_match) begin + trigger_match_mem = trigger_match_mem_op[12]; + + end else begin + trigger_match_mem = '0; + end + end + + + assign is_trigger_match = trigger_match_mem | trigger_match_execute | trigger_match_exception; + + +endmodule diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match_mem.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match_mem.sv new file mode 100644 index 0000000000..ef5f2cddc3 --- /dev/null +++ b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_trigger_match_mem.sv @@ -0,0 +1,118 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +module uvmt_cv32e40s_sl_trigger_match_mem + import uvmt_cv32e40s_base_test_pkg::*; + #( + parameter int MEMORY_OPERATION_NR = 0 + ) + ( + input logic clk_i, + input logic rst_ni, + input logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] csr_conditions_m2_m6, + input logic [31:0] tdata1_array[CORE_PARAM_DBG_NUM_TRIGGERS+1], + input logic [31:0] tdata2_array[CORE_PARAM_DBG_NUM_TRIGGERS+1], + input logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] trigger_match_execute, + output logic [CORE_PARAM_DBG_NUM_TRIGGERS-1:0] trigger_match_mem + ); + + localparam TDATA1_LOAD = 0; + localparam TDATA1_STORE = 1; + localparam TDATA1_LSB_MATCH = 7; + localparam TDATA1_MSB_MATCH = 10; + localparam TDATA1_MATCH_WHEN_EQUAL = 0; + localparam TDATA1_MATCH_WHEN_GREATER_OR_EQUAL = 2; + localparam TDATA1_MATCH_WHEN_LESSER = 3; + + localparam MAX_MEM_ACCESS = 13; //Push and pop can do 13 memory access. XIF can potentially do more (TODO (xif): check this when merging to cv32e40x) + + + logic [3:0][31:0] byte_addr; + logic [3:0][CORE_PARAM_DBG_NUM_TRIGGERS-1:0] byte_match; + logic [3:0] byte_match_overview; + + generate + for (genvar b = 0; b < 4; b++) begin + + // Calculate the address of each byte + assign byte_addr[b] = rvfi.rvfi_mem_addr[MEMORY_OPERATION_NR*32 +: 32] + b; + + // Check if the bytes trigger + for (genvar t = 0; t < CORE_PARAM_DBG_NUM_TRIGGERS; t++) begin + assign byte_match[b][t] = + !rvfi.rvfi_trap.exception && + !trigger_match_execute && + csr_conditions_m2_m6[t] && + ((tdata1_array[t][TDATA1_LOAD] && rvfi.rvfi_mem_rmask_intended[MEMORY_OPERATION_NR*4+b]) || + (tdata1_array[t][TDATA1_STORE] && rvfi.rvfi_mem_wmask_intended[MEMORY_OPERATION_NR*4+b])) && + (((byte_addr[b] == tdata2_array[t]) && tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_EQUAL) || + ((byte_addr[b] >= tdata2_array[t]) && tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_GREATER_OR_EQUAL) || + ((byte_addr[b] < tdata2_array[t]) && tdata1_array[t][TDATA1_MSB_MATCH:TDATA1_LSB_MATCH] == TDATA1_MATCH_WHEN_LESSER)); + end + end + endgenerate + + + assign byte_match_overview = {|byte_match[3], |byte_match[2], |byte_match[1], |byte_match[0]}; + + always_comb begin + // No byte triggers: + if (byte_match_overview == 0) begin + trigger_match_mem = '0; + + // Only byte zero matches + end else if (!byte_match_overview[3] && !byte_match_overview[2] && !byte_match_overview[1] && byte_match_overview[0]) begin + trigger_match_mem = byte_match[0]; + + // Byte one matches, byte two and three dont match + end else if (!byte_match_overview[3] && !byte_match_overview[2] && byte_match_overview[1]) begin + if(byte_addr[1][31:2] == byte_addr[0][31:2]) begin + trigger_match_mem = byte_match[1] | byte_match[0]; + end else if (byte_match[0]) begin + trigger_match_mem = byte_match[0]; + end else begin + trigger_match_mem = byte_match[1] | byte_match[0]; + end + + // Byte two matches, byte three dont match + end else if (!byte_match_overview[3] && byte_match_overview[2]) begin + if(byte_addr[2][31:2] == byte_addr[0][31:2]) begin + trigger_match_mem = byte_match[2] | byte_match[1] | byte_match[0]; + end else if(byte_addr[1][31:2] == byte_addr[0][31:2] && (|byte_match[1] || |byte_match[0])) begin + trigger_match_mem = byte_match[1] | byte_match[0]; + end else if (byte_match[0]) begin + trigger_match_mem = byte_match[0]; + end else begin + trigger_match_mem = byte_match[2] | byte_match[1] | byte_match[0]; + end + + // Byte three matches + end else begin + if(byte_addr[3][31:2] == byte_addr[0][31:2]) begin + trigger_match_mem = byte_match[3] | byte_match[2] | byte_match[1] | byte_match[0]; + end else if(byte_addr[2][31:2] == byte_addr[0][31:2] && (|byte_match[2] || |byte_match[1] || |byte_match[0])) begin + trigger_match_mem = byte_match[2] | byte_match[1] | byte_match[0]; + end else if(byte_addr[1][31:2] == byte_addr[0][31:2] && (|byte_match[1] || |byte_match[0])) begin + trigger_match_mem = byte_match[1] | byte_match[0]; + end else if (byte_match[0]) begin + trigger_match_mem = byte_match[0]; + end else begin + trigger_match_mem = byte_match[3] | byte_match[2] | byte_match[1] | byte_match[0]; + end + end + end + +endmodule : uvmt_cv32e40s_sl_trigger_match_mem diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_support_logic.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_support_logic.sv new file mode 100644 index 0000000000..bdbfec8f38 --- /dev/null +++ b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_support_logic.sv @@ -0,0 +1,475 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs +// +// Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +module uvmt_cv32e40s_support_logic + import uvm_pkg::*; + import uvma_rvfi_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_pkg::*; + import uvma_rvfi_pkg::*; + import isa_decoder_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + ( + uvma_rvfi_instr_if_t rvfi, + uvmt_cv32e40s_support_logic_module_i_if_t.driver_mp in_support_if, + uvmt_cv32e40s_support_logic_module_o_if_t.master_mp out_support_if, + uvma_obi_memory_if_t data_obi_if, + uvma_obi_memory_if_t instr_obi_if + ); + + + // --------------------------------------------------------------------------- + // Default Resolutions + // --------------------------------------------------------------------------- + + default clocking @(posedge in_support_if.clk); endclocking + default disable iff (!in_support_if.rst_n); + + // --------------------------------------------------------------------------- + // Local parameters + // --------------------------------------------------------------------------- + + localparam MAX_NUM_OUTSTANDING_OBI_REQUESTS = 2; + + // --------------------------------------------------------------------------- + // Local variables + // --------------------------------------------------------------------------- + + // Signal indicates an exception is active for a multiop instruction, + // in other words a subop has triggered an exception. WB stage timing. + logic exception_active; + + // Signal indicates data bus address phase completed last cycle + logic data_bus_gnt_q; + + // flag for signaling first debug instruction + logic first_debug_ins_flag; + // prev rvfi_valid was a dret + logic ins_was_dret; + // flopped value of core control signal fetch_enable + logic fetch_enable_q; + // counter for keeping track of the number of rvfi_valids that have passed since the last observed debug_req + int req_vs_valid_cnt; + + + obi_data_req_t data_obi_req; + assign data_obi_req.addr = data_obi_if.addr; + assign data_obi_req.we = data_obi_if.we; + assign data_obi_req.be = data_obi_if.be; + assign data_obi_req.wdata = data_obi_if.wdata; + assign data_obi_req.memtype = data_obi_if.memtype; + assign data_obi_req.prot = data_obi_if.prot; + assign data_obi_req.dbg = data_obi_if.dbg; + assign data_obi_req.achk = data_obi_if.achk; + assign data_obi_req.integrity = '0; + + obi_inst_req_t instr_obi_req; + assign instr_obi_req.addr = instr_obi_if.addr; + assign instr_obi_req.memtype = instr_obi_if.memtype; + assign instr_obi_req.prot = instr_obi_if.prot; + assign instr_obi_req.dbg = instr_obi_if.dbg; + assign instr_obi_req.achk = instr_obi_if.achk; + assign instr_obi_req.integrity = '0; + + // --------------------------------------------------------------------------- + // Support logic blocks + // --------------------------------------------------------------------------- + + // Decoder: + always_comb begin + out_support_if.asm_if = decode_instr(in_support_if.if_instr); + end + always_comb begin + out_support_if.asm_id = decode_instr(in_support_if.id_instr); + end + always_comb begin + out_support_if.asm_ex = decode_instr(in_support_if.ex_instr); + end + always_comb begin + out_support_if.asm_wb = decode_instr(in_support_if.wb_instr); + end + always_comb begin + out_support_if.asm_rvfi = decode_instr(rvfi.rvfi_insn); + end + + + // Check if a new obi data req arrives after an exception is triggered. + // Used to verify exception timing with multiop instruction + always @(posedge in_support_if.clk or negedge in_support_if.rst_n) begin + if (!in_support_if.rst_n) begin + out_support_if.req_after_exception <= 0; + exception_active <= 0; + data_bus_gnt_q <= 0; + end else begin + // set prev bus gnt + data_bus_gnt_q <= in_support_if.data_bus_gnt; + + // is a trap taken in WB? + if (in_support_if.ctrl_fsm_o.pc_set && (in_support_if.ctrl_fsm_o.pc_mux == PC_TRAP_DBE || in_support_if.ctrl_fsm_o.pc_mux == PC_TRAP_EXC)) begin + if (in_support_if.data_bus_req && data_bus_gnt_q) begin + out_support_if.req_after_exception <= 1; + end + exception_active <= 1; + end else if (rvfi.rvfi_valid) begin + exception_active <= 0; + out_support_if.req_after_exception <= 0; + + end else if (exception_active && data_bus_gnt_q && in_support_if.data_bus_req) begin + out_support_if.req_after_exception <= 1; + end + end + + end //always + + // Detect first instruction of debug code + assign out_support_if.first_debug_ins = rvfi.rvfi_valid && rvfi.rvfi_dbg_mode && !first_debug_ins_flag; + + + always@ (posedge in_support_if.clk or negedge in_support_if.rst_n) begin + if( !in_support_if.rst_n) begin + first_debug_ins_flag <= 0; + ins_was_dret <= 0; + end else begin + if(rvfi.rvfi_valid) begin + if(rvfi.rvfi_dbg_mode) begin + first_debug_ins_flag <= 1; + end else begin + first_debug_ins_flag <= 0; + end + if(rvfi.is_dret && !rvfi.rvfi_trap.trap) begin + ins_was_dret <= 1; + end + end + if(ins_was_dret) begin + first_debug_ins_flag <= 0; + ins_was_dret <= 0; + end + end + end + + + //detect core startup + assign out_support_if.first_fetch = in_support_if.fetch_enable && !fetch_enable_q; + + always@ (posedge in_support_if.clk or negedge in_support_if.rst_n) begin + if( !in_support_if.rst_n) begin + fetch_enable_q <= 0; + end else if (in_support_if.fetch_enable) begin + fetch_enable_q <= 1; + end + end + + //record a debug_req long enough that it could be taken + always@ (posedge in_support_if.clk or negedge in_support_if.rst_n) begin + if( !in_support_if.rst_n) begin + out_support_if.recorded_dbg_req <= 0; + req_vs_valid_cnt <= 4'h0; + end else begin + if(rvfi.rvfi_valid) begin + if(in_support_if.debug_req_i) begin + out_support_if.recorded_dbg_req <= 1; + req_vs_valid_cnt <= 4'h1; + end else if (req_vs_valid_cnt > 0) begin + req_vs_valid_cnt <= req_vs_valid_cnt - 1; + end else begin + out_support_if.recorded_dbg_req <= 0; + end + end else if (in_support_if.debug_req_i) begin + out_support_if.recorded_dbg_req <= 1; + req_vs_valid_cnt <= 4'h2; + end + end + end + +if (CORE_PARAM_DBG_NUM_TRIGGERS == 0) begin + assign trigger_match_mem = '0; + assign trigger_match_execute = '0; + assign trigger_match_exception = '0; + assign is_trigger_match = '0; + +end else begin + + uvmt_cv32e40s_sl_trigger_match + sl_trigger_match + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + .trigger_match_mem (out_support_if.trigger_match_mem[CORE_PARAM_DBG_NUM_TRIGGERS-1:0]), + .trigger_match_execute (out_support_if.trigger_match_execute[CORE_PARAM_DBG_NUM_TRIGGERS-1:0]), + .trigger_match_exception (out_support_if.trigger_match_exception[CORE_PARAM_DBG_NUM_TRIGGERS-1:0]), + .is_trigger_match (out_support_if.is_trigger_match[CORE_PARAM_DBG_NUM_TRIGGERS-1:0]) + ); + + assign out_support_if.trigger_match_mem[CORE_PARAM_DBG_NUM_TRIGGERS] = 1'b0; + assign out_support_if.trigger_match_execute[CORE_PARAM_DBG_NUM_TRIGGERS] = 1'b0; + assign out_support_if.trigger_match_exception[CORE_PARAM_DBG_NUM_TRIGGERS] = 1'b0; + assign out_support_if.is_trigger_match[CORE_PARAM_DBG_NUM_TRIGGERS] = 1'b0; + +end + + + + // Count "irq_ack" + + always_latch begin + if (in_support_if.rst_n == 0) begin + out_support_if.cnt_irq_ack = 0; + end else if (in_support_if.irq_ack) begin + if ($past(out_support_if.cnt_irq_ack) != '1) begin + out_support_if.cnt_irq_ack = $past(out_support_if.cnt_irq_ack) + 1; + end + end + end + + + // Count rvfi reported interrupts + + logic do_count_rvfi_irq; + always_comb begin + do_count_rvfi_irq = + rvfi.rvfi_intr.interrupt && + !(rvfi.rvfi_intr.cause inside {[1024:1027]}) && + rvfi.rvfi_valid && + ($past(out_support_if.cnt_rvfi_irqs) != '1); + end + + always_latch begin + if (in_support_if.rst_n == 0) begin + out_support_if.cnt_rvfi_irqs = 0; + end else if (do_count_rvfi_irq) begin + out_support_if.cnt_rvfi_irqs = $past(out_support_if.cnt_rvfi_irqs) + 1; + end + end + + + + // --------------------------------------------------------------------------- + // Support logic submodules + // --------------------------------------------------------------------------- + + + // Support logic for obi interfaces: + + //obi data bus: + uvmt_cv32e40s_sl_obi_phases_monitor data_bus_obi_phases_monitor ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .obi_req (in_support_if.data_bus_req), + .obi_gnt (in_support_if.data_bus_gnt), + .obi_rvalid (in_support_if.data_bus_rvalid), + + .addr_ph_cont (out_support_if.data_bus_addr_ph_cont), + .resp_ph_cont (out_support_if.data_bus_resp_ph_cont), + .v_addr_ph_cnt (out_support_if.data_bus_v_addr_ph_cnt) + ); + + //obi instr bus: + uvmt_cv32e40s_sl_obi_phases_monitor instr_bus_obi_phases_monitor ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .obi_req (in_support_if.instr_bus_req), + .obi_gnt (in_support_if.instr_bus_gnt), + .obi_rvalid (in_support_if.instr_bus_rvalid), + + .addr_ph_cont (out_support_if.instr_bus_addr_ph_cont), + .resp_ph_cont (out_support_if.instr_bus_resp_ph_cont), + .v_addr_ph_cnt (out_support_if.instr_bus_v_addr_ph_cnt) + ); + + //obi protocol between alignmentbuffer (ab) and instructoin (i) interface (i) mpu (m) (=> abiim) + uvmt_cv32e40s_sl_obi_phases_monitor abiim_bus_obi_phases_monitor ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .obi_req (in_support_if.abiim_bus_req), + .obi_gnt (in_support_if.abiim_bus_gnt), + .obi_rvalid (in_support_if.abiim_bus_rvalid), + + .addr_ph_cont (out_support_if.abiim_bus_addr_ph_cont), + .resp_ph_cont (out_support_if.alignment_buff_resp_ph_cont), + .v_addr_ph_cnt (out_support_if.alignment_buff_addr_ph_cnt) + ); + + //obi protocol between LSU (l) MPU (m) and LSU (l) (=> lml) + uvmt_cv32e40s_sl_obi_phases_monitor lml_bus_obi_phases_monitor ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .obi_req (in_support_if.lml_bus_req), + .obi_gnt (in_support_if.lml_bus_gnt), + .obi_rvalid (in_support_if.lml_bus_rvalid), + + .addr_ph_cont (out_support_if.lml_bus_addr_ph_cont), + .resp_ph_cont (out_support_if.lsu_resp_ph_cont), + .v_addr_ph_cnt (out_support_if.lsu_addr_ph_cnt) + ); + + + //The submodule instances under will tell if the + //the response's request had integrity + + uvmt_cv32e40s_sl_fifo + #( + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) instr_req_had_integrity_i + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .add_item (in_support_if.instr_bus_gnt && in_support_if.instr_bus_req), + .shift_fifo (in_support_if.instr_bus_rvalid), + + .item_in (in_support_if.req_instr_integrity), + .item_out (out_support_if.instr_req_had_integrity) + ); + + uvmt_cv32e40s_sl_fifo + #( + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) data_req_had_integrity_i + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .add_item (in_support_if.data_bus_gnt && in_support_if.data_bus_req), + .shift_fifo (in_support_if.data_bus_rvalid), + + .item_in (in_support_if.req_data_integrity), + .item_out (out_support_if.data_req_had_integrity) + ); + + uvmt_cv32e40s_sl_fifo + #( + .FIFO_TYPE_T (obi_data_req_t), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) fifo_obi_data_req + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .add_item (data_obi_if.gnt && data_obi_if.req), + .shift_fifo (data_obi_if.rvalid), + + .item_in (data_obi_req), + .item_out (out_support_if.obi_data_packet.req) + ); + + assign out_support_if.obi_data_packet.resp.rdata = data_obi_if.rdata; + assign out_support_if.obi_data_packet.resp.err = data_obi_if.err; + assign out_support_if.obi_data_packet.resp.rchk = data_obi_if.rchk; + assign out_support_if.obi_data_packet.resp.integrity_err = '0; + assign out_support_if.obi_data_packet.resp.integrity = '0; + assign out_support_if.obi_data_packet.valid = data_obi_if.rvalid; + + + uvmt_cv32e40s_sl_fifo + #( + .FIFO_TYPE_T (obi_inst_req_t), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) fifo_obi_instr_req + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .add_item (instr_obi_if.gnt && instr_obi_if.req), + .shift_fifo (instr_obi_if.rvalid), + + .item_in (instr_obi_req), + .item_out (out_support_if.obi_instr_packet.req) + ); + + assign out_support_if.obi_instr_packet.resp.rdata = instr_obi_if.rdata; + assign out_support_if.obi_instr_packet.resp.err = instr_obi_if.err; + assign out_support_if.obi_instr_packet.resp.rchk = instr_obi_if.rchk; + assign out_support_if.obi_instr_packet.resp.integrity_err = '0; + assign out_support_if.obi_instr_packet.resp.integrity = '0; + assign out_support_if.obi_instr_packet.valid = instr_obi_if.rvalid; + + + //The submodule instance under will tell if the + //the response's request had a gntpar error + //in the transfere of instructions on the OBI instruction bus. + + logic instr_gntpar_error; + logic instr_prev_gntpar_error; + logic data_gntpar_error; + logic data_prev_gntpar_error; + + assign instr_gntpar_error = ((in_support_if.instr_bus_gnt == in_support_if.instr_bus_gntpar || instr_prev_gntpar_error) && in_support_if.instr_bus_req) && in_support_if.rst_n; + assign data_gntpar_error = ((in_support_if.data_bus_gnt == in_support_if.data_bus_gntpar || data_prev_gntpar_error) && in_support_if.data_bus_req) && in_support_if.rst_n; + + always @(posedge in_support_if.clk, negedge in_support_if.rst_n) begin + if(!in_support_if.rst_n) begin + instr_prev_gntpar_error <= 1'b0; + data_prev_gntpar_error <= 1'b0; + end else begin + + if (in_support_if.instr_bus_req && !in_support_if.instr_bus_gnt) begin + instr_prev_gntpar_error <= instr_gntpar_error; + end else begin + instr_prev_gntpar_error <= 1'b0; + end + + if (in_support_if.data_bus_req && !in_support_if.data_bus_gnt) begin + data_prev_gntpar_error <= data_gntpar_error; + end else begin + data_prev_gntpar_error <= 1'b0; + end + + end + end + + uvmt_cv32e40s_sl_fifo + #( + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) sl_req_gntpar_error_in_resp_instr_i + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .add_item (in_support_if.instr_bus_gnt && in_support_if.instr_bus_req), + .shift_fifo (in_support_if.instr_bus_rvalid), + + .item_in (instr_gntpar_error), + .item_out (out_support_if.gntpar_error_in_response_instr) + ); + + //The submodule instance under will tell if the + //the response's request had a gntpar error + //in the transfere of data on the OBI data bus. + + uvmt_cv32e40s_sl_fifo + #( + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) sl_req_gntpar_error_in_resp_data_i + ( + .clk_i (in_support_if.clk), + .rst_ni (in_support_if.rst_n), + + .add_item (in_support_if.data_bus_gnt && in_support_if.data_bus_req), + .shift_fifo (in_support_if.data_bus_rvalid), + + .item_in (data_gntpar_error), + .item_out (out_support_if.gntpar_error_in_response_data) + ); + +endmodule : uvmt_cv32e40s_support_logic diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s.flist b/cv32e40s/tb/uvmt/uvmt_cv32e40s.flist index 7ef5134a9a..0e9f44dec5 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s.flist +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s.flist @@ -16,6 +16,7 @@ // limitations under the License. // + // Libraries -f ${DV_UVML_HRTBT_PATH}/uvml_hrtbt_pkg.flist -f ${DV_UVML_TRN_PATH}/uvml_trn_pkg.flist @@ -23,47 +24,46 @@ -f ${DV_UVML_SB_PATH}/uvml_sb_pkg.flist -f ${DV_UVML_MEM_PATH}/uvml_mem_pkg.flist -f ${DV_SVLIB_PATH}/svlib_pkg.flist +-f ${DV_ISA_DECODER_PATH}/isa_decoder_pkg.flist +-f ${DV_SUPPORT_PATH}/support_pkg.flist + + +// Imperas dv dependencies (rvvi, idv) or dummy package goes here (later packages depend on this) +${FILE_LIST_IDV_DEPS} // Agents -f ${DV_UVMA_CORE_CNTRL_PATH}/uvma_core_cntrl_pkg.flist -f ${DV_UVMA_OBI_MEMORY_PATH}/src/uvma_obi_memory_pkg.flist -f ${DV_UVMA_RVFI_PATH}/uvma_rvfi_pkg.flist --f ${DV_UVMA_RVVI_PATH}/uvma_rvvi_pkg.flist -f ${DV_UVMA_ISACOV_PATH}/uvma_isacov_pkg.flist -f ${DV_UVMA_PMA_PATH}/src/uvma_pma_pkg.flist -f ${DV_UVMA_CLKNRST_PATH}/uvma_clknrst_pkg.flist -f ${DV_UVMA_INTERRUPT_PATH}/uvma_interrupt_pkg.flist +-f ${DV_UVMA_CLIC_PATH}/uvma_clic_pkg.flist -f ${DV_UVMA_DEBUG_PATH}/uvma_debug_pkg.flist --f ${DV_UVMA_RVVI_OVPSIM_PATH}/uvma_rvvi_ovpsim_pkg.flist -f ${DV_UVMA_FENCEI_PATH}/uvma_fencei_pkg.flist +-f ${DV_UVMA_WFE_WU_PATH}/uvma_wfe_wu_pkg.flist -// Environments --f ${DV_UVME_PATH}/uvme_cv32e40s_pkg.flist // CV32E40S test bench Directories +incdir+${DV_UVMT_PATH} -+incdir+${DV_UVMT_PATH}/../../tests/uvmt -+incdir+${DV_UVMT_PATH}/../../tests/uvmt/base-tests -+incdir+${DV_UVMT_PATH}/../../tests/uvmt/compliance-tests -+incdir+${DV_UVMT_PATH}/../../tests/uvmt/vseq ++incdir+${DV_UVM_TESTCASE_PATH} ++incdir+${DV_UVM_TESTCASE_PATH}/base-tests ++incdir+${DV_UVM_TESTCASE_PATH}/compliance-tests ++incdir+${DV_UVM_TESTCASE_PATH}/vseq + +${DV_UVM_TESTCASE_PATH}/base-tests/uvmt_cv32e40s_base_test_pkg.sv // CV32E40S tests (includes constants/macros/types meant for test bench) +incdir+${TBSRC_HOME} + +// Environments +-f ${DV_UVME_PATH}/uvme_cv32e40s_pkg.flist ${DV_UVMT_PATH}/uvmt_cv32e40s_pkg.sv -// CV32E40S test bench files -${DV_UVMT_PATH}/uvmt_cv32e40s_dut_wrap.sv -${DV_UVMT_PATH}/uvmt_cv32e40s_tb.sv -${TBSRC_HOME}/core/tb_riscv/include/perturbation_defines.sv -${TBSRC_HOME}/uvmt/uvmt_cv32e40s_tb.sv -${TBSRC_HOME}/uvmt/uvmt_cv32e40s_dut_wrap.sv -${TBSRC_HOME}/core/mm_ram.sv -${TBSRC_HOME}/core/dp_ram.sv -${TBSRC_HOME}/core/tb_riscv/riscv_gnt_stall.sv -${TBSRC_HOME}/core/tb_riscv/riscv_rvalid_stall.sv -${TBSRC_HOME}/core/tb_riscv/riscv_random_interrupt_generator.sv +// ImperasDV wrapper files (this env var is not set if not using idv) +// Depends on env +${FILE_LIST_IDV} -${DV_UVMT_PATH}/uvmt_cv32e40s_interrupt_assert.sv -${DV_UVMT_PATH}/uvmt_cv32e40s_debug_assert.sv -${DV_UVMT_PATH}/uvmt_cv32e40s_fencei_assert.sv -${DV_UVMT_PATH}/uvmt_cv32e40s_integration_assert.sv +// CV32E40S test bench files +-f ${DV_UVMT_PATH}/uvmt_cv32e40s_tb_files.flist diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv new file mode 100644 index 0000000000..7a562f529b --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv @@ -0,0 +1,3335 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2022 Silicon Laboratories, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +module uvmt_cv32e40s_clic_interrupt_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvma_rvfi_pkg::*; + #( + parameter int CLIC = 0, + parameter int CLIC_ID_WIDTH = 5, + parameter int NUM_IRQ = 32 + )( + // gated clock + input logic clk, + // global clock + input logic clk_i, + input logic rst_ni, + input logic fetch_enable, + + // interfaces + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if, + uvma_rvfi_instr_if_t rvfi_if, + uvma_rvfi_csr_if_t csr_mepc_if, + uvma_rvfi_csr_if_t csr_mstatus_if, + uvma_rvfi_csr_if_t csr_mcause_if, + uvma_rvfi_csr_if_t csr_mintthresh_if, + uvma_rvfi_csr_if_t csr_mintstatus_if, + uvma_rvfi_csr_if_t csr_dcsr_if, + + + // CSR interface + input logic [31:0] dpc, + input logic [31:0] mintstatus, + input logic [31:0] mintthresh, + input logic [31:0] mstatus, + input logic [31:0] mtvec, + input logic [31:0] mtvt, + input logic [31:0] mepc, + input logic [31:0] mie, + input logic [31:0] mip, + input logic [31:0] mnxti, + input logic [31:0] mscratch, + input logic [31:0] mscratchcsw, + input logic [31:0] mscratchcswl, + input logic [31:0] dcsr, + + //Control signals: + input logic pc_set, + input logic [3:0] pc_mux, + + input logic [31:0] rvfi_mepc_wdata, + input logic [31:0] rvfi_mepc_wmask, + input logic [31:0] rvfi_mepc_rdata, + input logic [31:0] rvfi_mepc_rmask, + input logic [31:0] rvfi_dpc_rdata, + input logic [31:0] rvfi_dpc_rmask, + input logic [31:0] rvfi_mscratch_wdata, + input logic [31:0] rvfi_mscratch_wmask, + input logic [31:0] rvfi_mscratch_rdata, + input logic [31:0] rvfi_mscratch_rmask, + input logic [31:0] rvfi_mcause_wmask, + input logic [31:0] rvfi_mcause_wdata, + + + input logic [31:0] mcause, + + input logic [31:0] mtvec_addr_i, + + input logic [NUM_IRQ-1:0] irq_i, + input logic irq_ack, + input logic [1:0] current_priv_mode, + + uvma_clic_if_t clic_if, + + input logic [CLIC_ID_WIDTH-1:0] irq_id, + input logic [7:0] irq_level, + input logic [1:0] irq_priv, + input logic irq_shv, + + input logic debug_mode, + input logic debug_req, + input logic debug_havereset, + input logic debug_running, + input logic [31:0] debug_halt_addr, + input logic [31:0] debug_exc_addr, + + input logic obi_instr_req, + input logic obi_instr_gnt, + input logic obi_instr_rvalid, + input logic obi_instr_rready, + input logic [31:0] obi_instr_addr, + input logic [31:0] obi_instr_rdata, + input logic obi_instr_err, + + input logic obi_data_req, + input logic obi_data_gnt, + input logic obi_data_we, + input logic [3:0] obi_data_be, + input logic obi_data_rvalid, + input logic obi_data_rready, + input logic [31:0] obi_data_addr, + input logic [31:0] obi_data_wdata, + input logic obi_data_err, + + input logic [1:0] rvfi_mode, + input logic [31:0] rvfi_insn, + input rvfi_intr_t rvfi_intr, + input logic [31:0] rvfi_rs1_rdata, + input logic [31:0] rvfi_rs2_rdata, + input logic [31:0] rvfi_rd_wdata, + input logic rvfi_valid, + input rvfi_trap_t rvfi_trap, + input logic [31:0] rvfi_pc_rdata, + input logic [31:0] rvfi_pc_wdata, + input logic rvfi_dbg_mode, + input logic [2:0] rvfi_dbg, + + input logic wu_wfe, + input logic core_sleep_o + ); + + default clocking + @(posedge clk_i); + endclocking + default disable iff !rst_ni; + + string info_tag = "CLIC_ASSERT"; + + localparam logic [31:0] NMI_OFFSET = 0; + localparam logic [3:0] PC_MUX_MRET = 4'b0001; + localparam logic [3:0] PC_MUX_CLICV = 4'b1101; + + typedef struct packed { + logic irq; + logic [CLIC_ID_WIDTH-1:0] id; + logic [7:0] level; + logic [1:0] priv; + logic shv; + } clic_irq_bundle_t; + + typedef struct packed { + logic [CLIC_ID_WIDTH-1:0] id; + logic [7:0] level; + logic [1:0] priv; + logic shv; + } internal_clic_irq_bundle_t; + + typedef struct packed { + logic [31:24] mil; + logic [23:16] reserved; + logic [15:8] sil; + logic [7:0] uil; + } mintstatus_t; + + typedef struct packed { + logic [31:8] reserved_0; + logic [7:0] th; + } mintthresh_t; + + typedef struct packed { + logic [31:31] sd; + logic [30:23] reserved_3; + logic [22:22] tsr; + logic [21:21] tw; + logic [20:20] tvm; + logic [19:19] mxr; + logic [18:18] sum; + logic [17:17] mprv; + logic [16:15] xs; + logic [14:13] fs; + logic [12:11] mpp; + logic [10:9] vs; + logic [8:8] spp; + logic [7:7] mpie; + logic [6:6] ube; + logic [5:5] spie; + logic [4:4] reserved_2; + logic [3:3] mie; + logic [2:2] reserved_1; + logic [1:1] sie; + logic [0:0] reserved_0; + } mstatus_t; + + typedef struct packed { + logic [31:7] base_31_7; + logic [6:2] base_6_2; + logic [1:0] mode; + } mtvec_clic_t; + + localparam N_MTVT = 2+CLIC_ID_WIDTH > 6 ? 2+CLIC_ID_WIDTH : 6; + + typedef struct packed { + logic [31:N_MTVT] base_31_n; + logic [N_MTVT-1:0] base_n_0; + } mtvt_t; + + typedef struct packed { + logic [31:1] m_exception_pc; + logic [0:0] reserved; + } mepc_t; + + typedef enum logic [10:0] { + INSTR_ACCESS_FAULT = 11'd1, + ILLEGAL_INSTR = 11'd2, + BREAKPOINT = 11'd3, + LOAD_ACCESS_FAULT = 11'd5, + STORE_ACCESS_FAULT = 11'd7, + ECALL_U_MODE = 11'd8, + ECALL_M_MODE = 11'd11, + INSTR_BUS_FAULT = 11'd24, + INSTR_PARITY_FAULT = 11'd25, + NMI_LOAD = 11'd1024, + NMI_STORE = 11'd1025, + NMI_LOAD_PARITY = 11'd1026, + NMI_STORE_PARITY = 11'd1027 + } exccode_t; + + typedef struct packed { + logic [31:31] interrupt; + logic [30:30] minhv; + logic [29:28] mpp; + logic [27:27] mpie; + logic [26:24] reserved_1; + logic [23:16] mpil; + logic [15:12] reserved_0; + logic [11:11] exccode_11; + union packed { + logic [10:0] exccode_10_0; + exccode_t exccode_val; + }n; + } mcause_t; + + typedef struct packed { + logic [31:28] debugver; + logic [27:18] reserved_27_18; + logic [17:17] ebreakvs; + logic [16:16] ebreakvu; + logic [15:15] ebreakm; + logic [14:14] reserved_14; + logic [13:13] ebreaks; + logic [12:12] ebreaku; + logic [11:11] stepie; + logic [10:10] stopcount; + logic [9:9] stoptime; + logic [8:6] cause; + logic [5:5] v; + logic [4:4] mprven; + logic [3:3] nmip; + logic [2:2] step; + logic [1:0] prv; + } dcsr_t; + + typedef enum logic [1:0] { + M_MODE = 2'b11, + I_MODE = 2'b10, // Illegal, reserved + S_MODE = 2'b01, // Not used in 40S/X + U_MODE = 2'b00 + } priv_mode_t; + + typedef enum logic [2:0] { + CSRRW = 3'b001, + CSRRS = 3'b010, + CSRRC = 3'b011, + CSRRWI = 3'b101, + CSRRSI = 3'b110, + CSRRCI = 3'b111 + } csr_minor_opcode_t; + + typedef enum logic [6:0] { + LOAD = 7'b000_0011, LOAD_FP = 7'b000_0111, CUS_0 = 7'b000_1011, MISC_MEM = 7'b000_1111, OP_IMM = 7'b001_0011, AUIPC = 7'b001_0111,OP_IMM_32 = 7'b001_1011, + STORE = 7'b010_0011, STORE_FP = 7'b010_0111, CUS_1 = 7'b010_1011, AMO = 7'b010_1111, OP = 7'b011_0011, LUI = 7'b011_0111,OP_32 = 7'b011_1011, + MADD = 7'b100_0011, MSUB = 7'b100_0111, NMSUB = 7'b100_1011, NMADD = 7'b100_1111, OP_FP = 7'b101_0011, RES_1 = 7'b101_0111,CUS_2 = 7'b101_1011, + BRANCH = 7'b110_0011, JALR = 7'b110_0111, RES_0 = 7'b110_1011, JAL = 7'b110_1111, SYSTEM = 7'b111_0011, RES_2 = 7'b111_0111,CUS_3 = 7'b111_1011 + } major_opcode_t; + + typedef enum logic [2:0] { + FUNCT3_LB = 3'b000, + FUNCT3_LH = 3'b001, + FUNCT3_LW = 3'b010, + FUNCT3_LBU = 3'b100, + FUNCT3_LHU = 3'b101 + } load_size_e; + + typedef enum logic [2:0] { + FUNCT3_SB = 3'b000, + FUNCT3_SH = 3'b001, + FUNCT3_SW = 3'b010 + } store_size_e; + + typedef enum logic [4:0] { + X0 = 5'd0, + X1 = 5'd1, + X2 = 5'd2, + X3 = 5'd3, + X4 = 5'd4, + X5 = 5'd5, + X6 = 5'd6, + X7 = 5'd7, + X8 = 5'd8, + X9 = 5'd9, + X10 = 5'd10, + X11 = 5'd11, + X12 = 5'd12, + X13 = 5'd13, + X14 = 5'd14, + X15 = 5'd15, + X16 = 5'd16, + X17 = 5'd17, + X18 = 5'd18, + X19 = 5'd19, + X20 = 5'd20, + X21 = 5'd21, + X22 = 5'd22, + X23 = 5'd23, + X24 = 5'd24, + X25 = 5'd25, + X26 = 5'd26, + X27 = 5'd27, + X28 = 5'd28, + X29 = 5'd29, + X30 = 5'd30, + X31 = 5'd31 + } gpr_t; + + typedef enum logic [31:20] { + MSTATUS = 12'h300, + MISA = 12'h301, + MIE = 12'h304, + MTVEC = 12'h305, + MTVT = 12'h307, + MSTATUSH = 12'h310, + MCOUNTINHIBIT = 12'h320, + MHPMEVENT3 = 12'h323, + MHPMEVENT31 = 12'h33F, + MSCRATCH = 12'h340, + MEPC = 12'h341, + MCAUSE = 12'h342, + MTVAL = 12'h343, + MIP = 12'h344, + MNXTI = 12'h345, + MINTSTATUS = 12'h346, + MINTTHRESH = 12'h347, + MSCRATCHCSW = 12'h348, + MSCRATCHCSWL = 12'h349, + MCLICBASE = 12'h34A, + TSELECT = 12'h7A0, + TDATA1 = 12'h7A1, + TDATA2 = 12'h7A2, + TDATA3 = 12'h7A3, + TINFO = 12'h7A4, + TCONTROL = 12'h7A5, + DCSR = 12'h7B0, + DPC = 12'h7B1, + DSCRATCH0 = 12'h7B2, + DSCRATCH1 = 12'h7B3 + } csr_name_t; + + typedef struct packed { + csr_name_t csr; + union packed { + gpr_t rs1; + logic [19:15] uimm; + }n; + csr_minor_opcode_t funct3; + gpr_t rd; + major_opcode_t opcode; + } csr_instr_t; + + typedef struct packed { + logic [31:12] imm; + gpr_t rd; + }u_type; + + typedef struct packed { + logic [31:12] imm; + gpr_t rd; + }j_type; + + function logic[20:0] read_j_imm(logic[31:0] instr); + automatic logic [20:0] imm; + imm = instr >> 11; + return { imm[20], imm[10:1], imm[11], imm[18:12], 1'b0 }; + endfunction : read_j_imm + + typedef struct packed { + union packed { + struct packed { + logic [31:25] funct7; + gpr_t rs2; + }m; + logic [31:20] funct12; + }n; + gpr_t rs1; + logic [14:12] funct3; + gpr_t rd; + }r_type; + + typedef struct packed { + gpr_t rs3; + logic [26:25] funct2; + gpr_t rs2; + gpr_t rs1; + logic [14:12] funct3; + gpr_t rd; + }r4_type; + + typedef struct packed { + logic [31:20] imm; + gpr_t rs1; + logic [14:12] funct3; + gpr_t rd; + }i_type; + + typedef struct packed { + logic [31:20] imm; + gpr_t rs1; + load_size_e funct3; + gpr_t rd; + }i_type_load; + + typedef struct packed { + logic [31:25] imm; + gpr_t rs2; + gpr_t rs1; + logic [14:12] funct3; + gpr_t rd; + }b_type; + + function logic[11:0] read_b_imm(logic[31:0] instr); + automatic logic [11:0] imm; + imm = {instr[31], instr[7], instr[30:25], instr[11:8]}; + return imm; + endfunction : read_b_imm + + typedef struct packed { + logic [31:25] imm_h; + gpr_t rs2; + gpr_t rs1; + store_size_e funct3; + logic [11:7] imm_l; + }s_type; + + function logic[11:0] read_s_imm(logic[31:0] instr); + automatic logic [11:0] imm; + imm = {instr[31:25], instr[11:7]}; + return imm; + endfunction : read_s_imm + + typedef struct packed { + union packed { + logic [31:7] raw; + i_type i; + i_type_load i_load; + j_type j; + s_type s; + r_type r; + r4_type r4; + b_type b; + u_type u; + }n; + major_opcode_t opcode; + } uncompressed_instr_t; + + // Instruction name enum, add instructions as needed + typedef enum { + FENCEI, + MRET, + DRET, + ECALL, + EBREAK, + WFI, + WFE, + SB, + SH, + SW, + LB, + LH, + LW, + LBU, + LHU, + // Compressed + CEBREAK, + // Pseudo name, class of instruction + STORE_INSN, + LOAD_INSN + } instr_names_e; + + typedef struct packed { + logic is_mret; + logic is_clicv; + logic [35:32] tag; + logic [31:0] addr; + } obi_tagged_txn_t; + + + + function logic[7:0] max_level(logic[7:0] a, logic[7:0] b); + max_level = a > b ? a : b; + endfunction : max_level + + logic core_not_in_debug; + logic core_in_debug; + logic is_csr_access_instr; + + logic [11:0] s_imm; + logic [11:0] b_imm; + logic [20:0] j_imm; + logic [11:0] i_imm; + + uncompressed_instr_t mapped_instr; + + clic_irq_bundle_t clic; + clic_irq_bundle_t clic_core; + clic_irq_bundle_t clic_oic; + + csr_instr_t csr_instr_raw; + csr_instr_t csr_instr; + mintstatus_t mintstatus_fields; + mstatus_t mstatus_fields; + mtvec_clic_t mtvec_fields; + mtvt_t mtvt_fields; + mepc_t mepc_fields; + mcause_t mcause_fields; + mintthresh_t mintthresh_fields; + dcsr_t dcsr_fields; + + + mstatus_t rvfi_mstatus_fields; + mstatus_t rvfi_mstatus_wdata_fields; + mstatus_t rvfi_mstatus_wmask_fields; + mcause_t rvfi_mcause_fields; + mcause_t rvfi_mcause_wdata_fields; + mcause_t rvfi_mcause_wmask_fields; + mintstatus_t rvfi_mintstatus_fields; + mintstatus_t rvfi_mintstatus_wdata_fields; + mintthresh_t rvfi_mintthresh_fields; + dcsr_t rvfi_dcsr_fields; + + logic is_mepc_access_instr; + logic is_mtvec_access_instr; + logic is_mtvt_access_instr; + logic is_mcause_access_instr; + logic is_mstatus_access_instr; + logic is_mnxti_access_instr; + logic is_mscratchcsw_access_instr; + logic is_mscratchcswl_access_instr; + logic is_csr_write; + logic is_csr_read; + logic is_mret_instr; + logic is_fencei_instr; + logic is_interrupt_allowed; + logic is_dret_instr; + logic is_wfi_instr; + logic is_wfe_instr; + + logic is_load_instr; + logic is_store_instr; + + logic is_valid_mnxti_write; + logic is_valid_mnxti_read; + + logic is_load_bus_fault; + logic is_store_bus_fault; + logic is_load_parity_fault; + logic is_store_parity_fault; + logic is_instr_access_fault; + logic is_instr_clicptr_fault; + + logic is_interrupt_taken; + logic is_invalid_instr_word; + logic is_cause_nmi; + logic is_cause_interrupt; + logic is_cause_instr_access_fault; + logic is_cause_instr_bus_fault; + logic is_trap_exception; + logic is_intr_ecall_ebreak; + logic is_intr_exception; + + logic is_wfe_wakeup_event; + + logic [7:0] effective_clic_level; + + //arbitrary limit, 8 should be OK for now (by some margin) update as needed + localparam MAX_OBI_OUTSTANDING = 8; + logic [31:0] mtvt_write_offset; + logic [31:0] mtvt_read_offset; + logic [31:0] mtvt_table_value[0:(2**(CLIC_ID_WIDTH))-1]; + logic is_mtvt_store_event; + logic no_mtvt_store_event_occurred; + int items_in_obi_instr_fifo; + int items_in_obi_data_wfifo; + logic obi_instr_pop; + logic obi_instr_push; + logic obi_instr_pending; + logic obi_data_pop; + logic obi_data_push; + logic obi_data_pending; + logic [0:8][31:0] obi_instr_addr_fifo; + logic [0:8][31:0] obi_data_addr_fifo; + logic [31:0] obi_instr_resp; + + logic [2:0] obi_instr_service; + logic [2:0] obi_instr_service_n; + logic [2:0] obi_instr_request; + logic [2:0] obi_instr_request_n; + logic [2:0] obi_data_service; + logic [2:0] obi_data_service_n; + logic [2:0] obi_data_request; + logic [2:0] obi_data_request_n; + + logic is_read_mtvt_table_val_obi; + localparam logic [31:0] mtvt_max_offset = ((2**CLIC_ID_WIDTH)*4-1); + logic [31:0] last_mtvt_table_read_addr; + logic is_mtvt_load_event; + + logic [0:7][3:0] obi_instr_fifo_tag; + logic [0:7][3:0] obi_instr_fifo_tag_n; + logic [2:0] obi_instr_fifo_tag_size; + logic [2:0] obi_instr_fifo_tag_size_n; + logic [0:7][3:0] obi_data_fifo_tag; + logic [0:7][3:0] obi_data_fifo_tag_n; + logic [2:0] obi_data_fifo_tag_size; + logic [2:0] obi_data_fifo_tag_size_n; + + logic is_mtvt_table_access; + logic is_read_from_mtvt; + logic [0:7][3:0] obi_instr_tag; + logic [0:7][3:0] obi_instr_tag_n; + logic [0:7][31:0] obi_instr_tag_addr; + logic [0:7][31:0] obi_instr_tag_addr_n; + logic [2:0] obi_instr_tag_size; + logic [2:0] obi_instr_tag_size_n; + + logic obi_instr_fifo_tag_we; + logic obi_instr_fifo_tag_re; + logic obi_instr_fifo_tag_full; + logic obi_instr_fifo_tag_empty; + logic [7:0] obi_instr_fifo_tag_wena; + logic [7:0] obi_instr_fifo_tag_rena; + logic [2:0] obi_instr_fifo_tag_waddr; + logic [2:0] obi_instr_fifo_tag_waddr_ff; + logic [2:0] obi_instr_fifo_tag_raddr; + logic [2:0] obi_instr_fifo_tag_raddr_ff; + obi_tagged_txn_t obi_instr_fifo_tag_ff[8]; + obi_tagged_txn_t obi_instr_fifo_tag_out; + + logic obi_data_fifo_tag_we; + logic obi_data_fifo_tag_re; + logic obi_data_fifo_tag_full; + logic obi_data_fifo_tag_empty; + logic [7:0] obi_data_fifo_tag_wena; + logic [7:0] obi_data_fifo_tag_rena; + logic [2:0] obi_data_fifo_tag_waddr; + logic [2:0] obi_data_fifo_tag_waddr_ff; + logic [2:0] obi_data_fifo_tag_raddr; + logic [2:0] obi_data_fifo_tag_raddr_ff; + obi_tagged_txn_t obi_data_fifo_tag_ff[8]; + obi_tagged_txn_t obi_data_fifo_tag_out; + + logic [31:0] mepc_as_pointer_rdata; + logic [31:0] clicv_pointer_rdata; + logic pc_mux_mret_q; + logic obi_req_is_mret; + logic delayed_mret_req; + logic pc_mux_clicv_q; + logic obi_req_is_clicv; + logic delayed_clicv_req; + logic [31:0] next_pc; + logic irq_ack_occurred_between_valid; + logic [7:0] mintstatus_mil_q; + logic [7:0] expected_mpil; + logic prev_was_valid_mnxti_write; + logic prev_was_mret; + logic intended_mode_u; + logic prev_was_trapped_u; + + assign is_wfe_wakeup_event = wu_wfe; + + assign is_wfi_instr = is_instr(rvfi_insn, WFI); + assign is_wfe_instr = is_instr(rvfi_insn, WFE); + + assign is_load_bus_fault = (rvfi_intr.cause == NMI_LOAD && rvfi_intr.intr == 1 && rvfi_intr.interrupt == 1); + assign is_store_bus_fault = (rvfi_intr.cause == NMI_STORE && rvfi_intr.intr == 1 && rvfi_intr.interrupt == 1); + assign is_load_parity_fault = (rvfi_intr.cause == NMI_LOAD_PARITY && rvfi_intr.intr == 1 && rvfi_intr.interrupt == 1); + assign is_store_parity_fault = (rvfi_intr.cause == NMI_STORE_PARITY && rvfi_intr.intr == 1 && rvfi_intr.interrupt == 1); + assign is_cause_instr_access_fault = (rvfi_intr.cause == INSTR_ACCESS_FAULT && rvfi_intr.intr == 1 && rvfi_intr.exception == 1); + assign is_cause_instr_bus_fault = (rvfi_intr.cause == INSTR_BUS_FAULT && rvfi_intr.intr == 1 && rvfi_intr.exception == 1); + assign is_cause_instr_parity_fault = (rvfi_intr.cause == INSTR_PARITY_FAULT && rvfi_intr.intr == 1 && rvfi_intr.exception == 1); + + assign is_cause_nmi = (rvfi_intr.cause inside { NMI_LOAD, NMI_STORE, NMI_LOAD_PARITY, NMI_STORE_PARITY }) && rvfi_intr.intr && rvfi_intr.interrupt; + assign is_cause_interrupt = !(rvfi_intr.cause inside { NMI_LOAD, NMI_STORE, NMI_LOAD_PARITY, NMI_STORE_PARITY }) && rvfi_intr.intr && rvfi_intr.interrupt; + + assign is_interrupt_taken = (rvfi_intr.intr == 1'b1 && rvfi_intr.interrupt == 1'b1); + + assign is_instr_access_fault = (rvfi_trap.exception_cause == INSTR_ACCESS_FAULT && rvfi_trap.exception == 1 && rvfi_trap.trap == 1); + assign is_invalid_instr_word = (( rvfi_trap.exception_cause == INSTR_ACCESS_FAULT + || rvfi_trap.exception_cause == INSTR_BUS_FAULT + || rvfi_trap.exception_cause == INSTR_PARITY_FAULT) + && rvfi_trap.exception == 1'b1 && rvfi_trap.trap == 1'b1); + + assign is_instr_clicptr_fault = (rvfi_trap.exception_cause inside { INSTR_BUS_FAULT, INSTR_PARITY_FAULT, INSTR_ACCESS_FAULT } + && rvfi_trap.clicptr == 1'b1); + + assign is_trap_exception = rvfi_trap.exception == 1'b1 && rvfi_trap.trap == 1'b1; + assign is_intr_exception = rvfi_intr.exception == 1'b1 && rvfi_intr.intr == 1'b1; + assign is_intr_ecall_ebreak = is_intr_exception + && (rvfi_intr.cause == ECALL_M_MODE + || rvfi_intr.cause == ECALL_U_MODE + || rvfi_intr.cause == BREAKPOINT); + + + assign s_imm = read_s_imm(rvfi_insn); + assign b_imm = read_b_imm(rvfi_insn); + assign j_imm = read_j_imm(rvfi_insn); + assign i_imm = mapped_instr.n.i.imm; + + assign mapped_instr = uncompressed_instr_t'(rvfi_insn); + + // Map csrs to bitfield representations + assign mintstatus_fields = mintstatus_t'(mintstatus); + assign mintthresh_fields = mintthresh_t'(mintthresh); + assign mstatus_fields = mstatus_t'(mstatus); + assign mtvec_fields = mtvec_clic_t'(mtvec); + assign mtvt_fields = mtvt_t'(mtvt); + assign mepc_fields = mepc_t'(mepc); + assign mcause_fields = mcause_t'(mcause); + assign dcsr_fields = dcsr_t'(dcsr); + + assign rvfi_mstatus_fields = mstatus_t'(csr_mstatus_if.rvfi_csr_rdata); + assign rvfi_mstatus_wdata_fields = mstatus_t'(csr_mstatus_if.rvfi_csr_wdata & csr_mstatus_if.rvfi_csr_wmask); + assign rvfi_mcause_fields = mcause_t'(csr_mcause_if.rvfi_csr_rdata); + assign rvfi_mcause_wdata_fields = mcause_t'(csr_mcause_if.rvfi_csr_wdata & csr_mcause_if.rvfi_csr_wmask); + assign rvfi_mcause_wmask_fields = mcause_t'(csr_mcause_if.rvfi_csr_wmask); + assign rvfi_mintstatus_fields = mintstatus_t'(csr_mintstatus_if.rvfi_csr_rdata); + assign rvfi_mintstatus_wdata_fields = mintstatus_t'(csr_mintstatus_if.rvfi_csr_wdata & csr_mintstatus_if.rvfi_csr_wmask); + assign rvfi_mintthresh_fields = mintthresh_t'(csr_mintthresh_if.rvfi_csr_rdata); + assign rvfi_dcsr_fields = dcsr_t'(csr_dcsr_if.rvfi_csr_rdata); + + always_comb begin + clic.irq = clic_if.clic_irq; + clic.id = clic_if.clic_irq_id; + clic.level = clic_if.clic_irq_level; + clic.priv = clic_if.clic_irq_priv; + clic.shv = clic_if.clic_irq_shv; + end + + always_comb begin + if (!rst_ni) begin + clic_core.id = '0; + clic_core.level = '0; + clic_core.priv = '0; + clic_core.shv = '0; + end else begin + clic_core.id = irq_id; + clic_core.level = irq_level; + clic_core.priv = irq_priv; + clic_core.shv = irq_shv; + end + end + + always @(posedge clk_i) begin + if (!rst_ni) begin + clic_core.irq <= 0; + end else begin + clic_core.irq <= clic.irq; + end + end + + + assign core_not_in_debug = debug_running; + assign core_in_debug = !core_not_in_debug; + assign csr_instr_raw = csr_instr_t'(rvfi_insn); + assign is_csr_access_instr = csr_instr_raw.opcode == SYSTEM + && (csr_instr_raw.funct3 inside { CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI }) ; + assign is_mnxti_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MNXTI; + assign is_mepc_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MEPC; + assign is_mtvec_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MTVEC; + assign is_mtvt_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MTVT; + assign is_mcause_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MCAUSE; + assign is_mstatus_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MSTATUS; + assign is_mscratchcsw_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MSCRATCHCSW; + assign is_mscratchcswl_access_instr = is_csr_access_instr && rvfi_valid && csr_instr.csr == MSCRATCHCSWL; + + assign csr_instr = is_csr_access_instr ? csr_instr_raw : 32'h0000_0000; + + assign is_valid_mnxti_write = is_mnxti_access_instr && is_csr_write && rvfi_valid; + assign is_valid_mnxti_read = is_mnxti_access_instr && is_csr_read && rvfi_valid; + + // TODO replace with non-poking signal + assign is_interrupt_allowed = dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.interrupt_allowed; + + function logic fun_is_csr_write(csr_instr_t instr); + if (instr.opcode == SYSTEM + && (instr.funct3 inside { CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI })) begin + + case (instr.funct3) + CSRRW, CSRRWI : fun_is_csr_write = 1'b1; + CSRRS, CSRRC : fun_is_csr_write = instr.n.rs1 ? 1'b1 : 1'b0; + CSRRSI, CSRRCI: fun_is_csr_write = instr.n.uimm ? 1'b1 : 1'b0; + + // Should never be here + default : fun_is_csr_write = 1'b0; + endcase + end else begin + fun_is_csr_write = 1'b0; + end + endfunction : fun_is_csr_write + + function logic fun_is_csr_read(csr_instr_t instr); + if (instr.opcode == SYSTEM + && (instr.funct3 inside { CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI })) begin + case (instr.funct3) + CSRRW, CSRRWI : fun_is_csr_read = instr.rd ? 1'b1 : 1'b0; + CSRRS, CSRRC : fun_is_csr_read = 1'b1; + CSRRSI, CSRRCI: fun_is_csr_read = 1'b1; + + // Should never be here + default : fun_is_csr_read = 1'b0; + endcase + end else begin + fun_is_csr_read = 1'b0; + end + endfunction : fun_is_csr_read + + always_comb begin + if (is_csr_access_instr) begin + is_csr_write = fun_is_csr_write(csr_instr); + is_csr_read = fun_is_csr_read(csr_instr); + end else begin + is_csr_write = 0; + is_csr_read = 0; + end + end + + // Checks if a single bit of a csr is cleared by sw + function bit csr_bit_cleared_by_sw(bit[31:0] index); + case (csr_instr.funct3) + CSRRCI: begin + if (index > 4) begin + return 0; + end else begin + return csr_instr.n.uimm[index]; + end + end + CSRRWI: begin + if (index > 4) begin + return 1; + end else begin + return !csr_instr.n.uimm[index]; + end + end + CSRRC: begin + return rvfi_rs1_rdata[index]; + end + CSRRW: begin + return !rvfi_rs1_rdata[index]; + end + CSRRS, CSRRSI: begin + return 0; + end + endcase + + return 0; + endfunction : csr_bit_cleared_by_sw + + // Checks if a single bit of a csr is set by sw + function bit csr_bit_set_by_sw(bit[31:0] index); + case (csr_instr.funct3) + CSRRCI: begin + return 0; + end + CSRRWI: begin + if (index > 4) begin + return 0; + end else begin + return csr_instr.n.uimm[index]; + end + end + CSRRC: begin + return 0; + end + CSRRW, CSRRS: begin + return rvfi_rs1_rdata[index]; + end + CSRRSI: begin + if (index > 4) begin + return 0; + end else begin + return csr_instr.n.uimm[index]; + end + end + endcase + + return 0; + endfunction : csr_bit_set_by_sw + + bit is_minhv_set_by_sw; + bit is_minhv_cleared_by_sw; + + always_comb begin + is_minhv_set_by_sw = rvfi_valid && is_csr_write && is_mcause_access_instr && csr_bit_set_by_sw(30); + is_minhv_cleared_by_sw = rvfi_valid && is_csr_write && is_mcause_access_instr && csr_bit_cleared_by_sw(30); + end + + function is_instr(uncompressed_instr_t instr, instr_names_e instr_type); + if (is_invalid_instr_word) begin + return 1'b0; + end + + case (instr_type) + FENCEI : return ( (instr.opcode == MISC_MEM) + && (instr.n.i.rd == 5'b0_0000) + && (instr.n.i.funct3 == 3'b001) + && (instr.n.i.rs1 == 5'b0_0000) + && (instr.n.i.imm == 12'h000)); + ECALL : return ( (instr.opcode == SYSTEM) + && (instr.n.i.imm == 12'b0000_0000_0000)); + EBREAK : return ( (instr.opcode == SYSTEM) + && (instr.n.i.imm == 12'b0000_0000_0001)); + CEBREAK: return ( (instr == 32'b0000_0000_1001_0010)); // compressed + MRET : return ( (instr.opcode == SYSTEM) + && (instr.n.r.rd == 5'b0_0000) + && (instr.n.r.n.m.funct7 == 12'b001_1000) + && (instr.n.r.n.m.rs2 == 5'b0_0010) + && (instr.n.r.rs1 == 5'b0_0000) + && (instr.n.r.funct3 == 3'b000)); + DRET : return ( (instr.opcode == SYSTEM) + && (instr.n.r.n.funct12 == 12'b0111_1011_0010)); + WFI : return ( (instr.opcode == SYSTEM) + && (instr.n.r.rd == 5'b0_0000) + && (instr.n.r.funct3 == 3'b000) + && (instr.n.r.rs1 == 5'b0_0000) + && (instr.n.r.n.funct12 == 12'b0001_0000_0101)); + WFE : return ( (instr.opcode == SYSTEM) + && (instr.n.r.rd == 5'b0_0000) + && (instr.n.r.funct3 == 3'b000) + && (instr.n.r.rs1 == 5'b0_0000) + && (instr.n.r.n.funct12 == 12'b1000_1100_0000)); + SB : return ( (instr.opcode == STORE) + && (instr.n.s.funct3 == FUNCT3_SB)); + SH : return ( (instr.opcode == STORE) + && (instr.n.s.funct3 == FUNCT3_SH)); + SW : return ( (instr.opcode == STORE) + && (instr.n.s.funct3 == FUNCT3_SW)); + STORE_INSN : return (instr.opcode == STORE) + && (instr.n.s.funct3 inside { FUNCT3_SB, FUNCT3_SH, FUNCT3_SW }); + LB : return ( (instr.opcode == LOAD) + && (instr.n.i.funct3 == FUNCT3_LB)); + LH : return ( (instr.opcode == LOAD) + && (instr.n.i.funct3 == FUNCT3_LH)); + LW : return ( (instr.opcode == LOAD) + && (instr.n.i.funct3 == FUNCT3_LW)); + LBU : return ( (instr.opcode == LOAD) + && (instr.n.i.funct3 == FUNCT3_LBU)); + LHU : return ( (instr.opcode == LOAD) + && (instr.n.i.funct3 == FUNCT3_LHU)); + LOAD_INSN : return (instr.opcode == LOAD) + && (instr.n.i.funct3 inside { FUNCT3_LB, FUNCT3_LH, FUNCT3_LW, FUNCT3_LBU, FUNCT3_LHU }); + endcase + endfunction : is_instr + + assign is_mret_instr = rvfi_valid && is_instr(rvfi_insn, MRET); + assign is_dret_instr = rvfi_valid && is_instr(rvfi_insn, DRET); + assign is_fencei_instr = rvfi_valid && is_instr(rvfi_insn, FENCEI); + + assign is_store_instr = rvfi_valid && is_instr(rvfi_insn, STORE_INSN); + assign is_load_instr = rvfi_valid && is_instr(rvfi_insn, LOAD_INSN); + + function logic is_store_instr_addr_in_mtvt_region(uncompressed_instr_t instr); + automatic logic [31:0] base = 0; + automatic logic [11:0] offset = 0; + case (is_instr(instr, STORE_INSN)) + 1: offset = s_imm; + 0: return 1'b0; + endcase + base = rvfi_rs1_rdata; + return base + offset inside { [mtvt : mtvt + ((2**CLIC_ID_WIDTH * 4))] } ? 1'b1 : 1'b0; + endfunction : is_store_instr_addr_in_mtvt_region + + function logic is_load_instr_addr_in_mtvt_region(uncompressed_instr_t instr); + automatic logic [31:0] base = 0; + automatic logic [11:0] offset = 0; + case (is_instr(instr, LOAD_INSN)) + 1: offset = i_imm; + 0: return 1'b0; + endcase + base = rvfi_rs1_rdata; + return base + offset inside { [mtvt : mtvt + ((2**CLIC_ID_WIDTH * 4))] } ? 1'b1 : 1'b0; + endfunction : is_load_instr_addr_in_mtvt_region + + generate + if (CLIC) begin : gen_clic_assertions + + // ------------------------------------------------------------------------ + // mintstatus.mil resets to 0 + // ------------------------------------------------------------------------ + + property p_mintstatus_mil_reset_to_zero; + $rose(rst_ni) |-> mintstatus_fields.mil == 8'h0; + endproperty : p_mintstatus_mil_reset_to_zero + + a_mintstatus_mil_reset_to_zero: assert property (p_mintstatus_mil_reset_to_zero) + else + `uvm_error(info_tag, + $sformatf("mintstatus.mil non-zero reset value not allowed")); + + // ------------------------------------------------------------------------ + // mstatus.mie should reset to zero + // ------------------------------------------------------------------------ + + property p_mstatus_mie_reset_to_zero; + $rose(rst_ni) |-> mstatus_fields.mie == 1'b0; + endproperty : p_mstatus_mie_reset_to_zero + + a_mstatus_mie_reset_to_zero: assert property (p_mstatus_mie_reset_to_zero) + else + `uvm_error(info_tag, + $sformatf("mstatus.mie non-zero reset value not allowed")); + + // ------------------------------------------------------------------------ + // mtvec reset value is correct + // ------------------------------------------------------------------------ + + property p_mtvec_reset_value_correct; + $rose(fetch_enable) |=> ##1 + mtvec_fields.base_31_7 == mtvec_addr_i[31:7] && + mtvec_fields.base_6_2 == 5'h00 && + mtvec_fields.mode == 2'b11; + endproperty : p_mtvec_reset_value_correct; + + a_mtvec_reset_value_correct: assert property (p_mtvec_reset_value_correct) + else + `uvm_error(info_tag, + $sformatf("mtvec reset value: 0x%08h, should have been 0x%08h", + mtvec_fields, mtvec_addr_i)); + + // ------------------------------------------------------------------------ + // clic.priv should always be machine mode + // ------------------------------------------------------------------------ + + property p_clic_mode_only; + clic.priv == M_MODE; + endproperty : p_clic_mode_only + + a_clic_mode_only: assert property (p_clic_mode_only) + else + `uvm_error(info_tag, + $sformatf("When clic is enabled, it should be the ONLY mode available")); + + // ------------------------------------------------------------------------ + // NMI address should be at the fifthteenth entry in the mtvec table + // ------------------------------------------------------------------------ + + property p_nmi_to_mtvec_offset; + is_cause_nmi + && rvfi_valid + |-> + rvfi_pc_rdata == ({$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + NMI_OFFSET) + or + rvfi_pc_rdata == ({$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + NMI_OFFSET + 2) + && (mapped_instr.opcode[1:0] != 2'b11) + or + is_dret_instr + ##1 rvfi_valid[->1] + ##0 rvfi_pc_rdata == ({$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + NMI_OFFSET) + && !rvfi_dbg_mode + or + ##0 rvfi_pc_rdata == debug_halt_addr + && rvfi_dbg_mode + ; + endproperty : p_nmi_to_mtvec_offset + + a_nmi_to_mtvec_offset: assert property (p_nmi_to_mtvec_offset) + else + `uvm_error(info_tag, + $sformatf("Taken nmi address wrong")); + + // ------------------------------------------------------------------------ + // CLIC_ID_WIDTH setting should be for 1-1024 interrupts + // ------------------------------------------------------------------------ + + property p_clic_valid_setting; + CLIC_ID_WIDTH inside {[1:10]}; + endproperty : p_clic_valid_setting + + a_clic_valid_setting: assert property (p_clic_valid_setting) + else + `uvm_error(info_tag, + $sformatf("CLIC_ID_WIDTH is invalid, is %0d, should be in range 1 .. 10", + CLIC_ID_WIDTH)); + + // ------------------------------------------------------------------------ + // irq_i[0:31] should be hardcoded zero + // ------------------------------------------------------------------------ + + for (genvar i = 0; i < NUM_IRQ; i++) begin : gen_non_clic_tieoff + + property p_tieoff_zero_irq_i; + irq_i[i] == '0; + endproperty : p_tieoff_zero_irq_i; + + a_tieoff_zero_irq_i : assert property (p_tieoff_zero_irq_i) + else + `uvm_error(info_tag, + $sformatf("irq_i[%0d] should be zero, is %0b", + i, + irq_i[i]) + ); + end + + // ------------------------------------------------------------------------ + // Enabled and pending interrupts should eventually be taken, + // assuming that the request is not retracted + // ------------------------------------------------------------------------ + + localparam MAX_STALL_CYCLES = 20; + + property p_obi_instr_max_load_stalls; + $stable(obi_instr_fifo_tag_waddr) && (obi_instr_fifo_tag_waddr != '0) + |-> + ($stable(obi_instr_fifo_tag_waddr))[*0:MAX_STALL_CYCLES] + ##1 $changed(obi_instr_fifo_tag_waddr); + endproperty : p_obi_instr_max_load_stalls + + property p_obi_instr_max_gnt_stalls; + obi_instr_pending + |-> + obi_instr_pending[*0:MAX_STALL_CYCLES] ##1 obi_instr_push; + endproperty : p_obi_instr_max_gnt_stalls + + property p_obi_data_max_load_stalls; + $stable(obi_data_fifo_tag_waddr) && (obi_data_fifo_tag_waddr != '0) + |-> + ($stable(obi_data_fifo_tag_waddr))[*0:MAX_STALL_CYCLES] + ##1 $changed(obi_data_fifo_tag_waddr); + endproperty : p_obi_data_max_load_stalls + + property p_obi_data_max_gnt_stalls; + obi_data_pending + |-> + obi_data_pending[*0:MAX_STALL_CYCLES] ##1 obi_data_push; + endproperty : p_obi_data_max_gnt_stalls + + localparam MAX_RVFI_VALID_DELAY = 64; + + property p_instr_valid_delay; + !rvfi_valid |-> !rvfi_valid[*0:MAX_RVFI_VALID_DELAY] ##1 rvfi_valid; + endproperty + + + // ------------------------------------------------------------------------ + // irq_ack is always single cycle pulse + // ------------------------------------------------------------------------ + + property p_irq_ack_is_always_single_cycle_pulse; + irq_ack + |=> + !irq_ack; + endproperty : p_irq_ack_is_always_single_cycle_pulse + + a_irq_ack_is_always_single_cycle_pulse: assert property (p_irq_ack_is_always_single_cycle_pulse) + else + `uvm_error(info_tag, + $sformatf("irq_ack not single cycle pulse")); + + // ------------------------------------------------------------------------ + // irq_ack should only be asserted on taken interrupts + // ------------------------------------------------------------------------ + + + + always_comb begin + effective_clic_level = mintthresh_fields.th > mintstatus_fields.mil ? mintthresh_fields.th : mintstatus_fields.mil; + end + + sequence seq_irq_pend(bit ok = 1'b1); + @(posedge clk_i) + + // valid pending + ok ##0 ( + (mstatus_fields.mie + && $past(clic.irq) + && $past(clic.priv) == current_priv_mode + && $past(clic.level) > effective_clic_level) + or + ($past(clic.irq) + && $past(clic.priv) > current_priv_mode + && $past(clic.level) > 0) + ) + or + // no valid pending + !ok ##0 ( + !(mstatus_fields.mie + && $past(clic.irq) + && $past(clic.priv) == current_priv_mode + && $past(clic.level) > effective_clic_level) + and + !($past(clic.irq) + && $past(clic.priv) > current_priv_mode + && $past(clic.level) > 0) + ) + ; + endsequence : seq_irq_pend + + property p_irq_ack_valid; + irq_ack + |-> + seq_irq_pend(1'b1) + ; + endproperty : p_irq_ack_valid + + a_irq_ack_valid: assert property (p_irq_ack_valid) + else + `uvm_error(info_tag, + $sformatf("irq ack prerequisites not met and ack occurred")); + + // ------------------------------------------------------------------------ + // There should be no irq_ack unless there was a pending and enabled irq + // ------------------------------------------------------------------------ + property p_no_irq_no_ack; + // Never irq_ack unless we had a valid and pending interrupt present. + seq_irq_pend(1'b0).triggered + |-> + !irq_ack + ; + endproperty : p_no_irq_no_ack + + a_no_irq_no_ack : assert property (p_no_irq_no_ack) + else + `uvm_error(info_tag, + $sformatf("irq ack prerequisites not met and ack occurred")); + + // ------------------------------------------------------------------------ + // There should be no irq_ack on taken nmi + // + // Ideally would like to have an assertion for this case, but it is not + // possible to separate cases on rvfi where the taken interrupts handler + // is interrupted by nmi, and thus appears to have an ack caused by nmi + // + // The remaining cases will be covered by no irq_ack without valid, + // pending irq, and that ack always occurs together with a valid pending + // interrupt condition. + // ------------------------------------------------------------------------ + + // ------------------------------------------------------------------------ + // Every irq_ack should be followed by an rvfi_intr + // ------------------------------------------------------------------------ + + property p_every_ack_followed_by_rvfi_intr; + irq_ack + ##1 rvfi_valid[->1] + |-> + // all the following are rvfi_intr-based signals. + is_cause_interrupt + or + is_cause_nmi + or + is_cause_instr_access_fault + or + is_cause_instr_bus_fault + or + is_cause_instr_parity_fault + ; + endproperty : p_every_ack_followed_by_rvfi_intr + + a_every_ack_followed_by_rvfi_intr: assert property (p_every_ack_followed_by_rvfi_intr) + else + `uvm_error(info_tag, + $sformatf("Every irq_ack should be followed by the corresponding rvfi_intr")); + + // ------------------------------------------------------------------------ + // mie is unused, and should be hard coded zero + // ------------------------------------------------------------------------ + + property p_mie_unused_hardcode_zero; + mie == 32'h0000_0000; + endproperty : p_mie_unused_hardcode_zero + + a_mie_unused_hardcode_zero: assert property (p_mie_unused_hardcode_zero) + else + `uvm_error(info_tag, + $sformatf("Mie is unused and should always read zero")); + + // ------------------------------------------------------------------------ + // mip is unused, and should be hard coded zero + // ------------------------------------------------------------------------ + + property p_mip_unused_hardcode_zero; + mip == 32'h0000_0000; + endproperty : p_mip_unused_hardcode_zero + + a_mip_unused_hardcode_zero: assert property (p_mip_unused_hardcode_zero) + else + `uvm_error(info_tag, + $sformatf("Mip is unused and should always read zero")); + + // ------------------------------------------------------------------------ + // mtvec should always be aligned to 128 bytes + // ------------------------------------------------------------------------ + + property p_mtvec_aligned_to_128_bytes; + mtvec_fields.base_6_2 == 5'b0_0000; + endproperty : p_mtvec_aligned_to_128_bytes; + + a_mtvec_aligned_to_128_bytes: assert property (p_mtvec_aligned_to_128_bytes) + else + `uvm_error(info_tag, + $sformatf("mtvec[6:2] should have been zero (128 bytes alignment), was %05b", + mtvec_fields.base_6_2)); + + // ------------------------------------------------------------------------ + // mtvec.mode should always be clic mode + // ------------------------------------------------------------------------ + + property p_mtvec_mode_always_clic; + mtvec_fields.mode == 2'b11; + endproperty : p_mtvec_mode_always_clic + + a_mtvec_mode_always_clic: assert property (p_mtvec_mode_always_clic) + else + `uvm_error(info_tag, + $sformatf("mtvec.mode should always be clic in clic mode, is %02b", + mtvec_fields.mode)); + + // ------------------------------------------------------------------------ + // fencei guarantees that updated mtvt table values are fetched + // ------------------------------------------------------------------------ + + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + obi_instr_service <= '0; + obi_instr_request <= '0; + obi_data_service <= '0; + obi_data_request <= '0; + end else begin + obi_instr_request <= obi_instr_request_n; + obi_instr_service <= obi_instr_service_n; + obi_data_request <= obi_data_request_n; + obi_data_service <= obi_data_service_n; + end + end + + always_comb begin + if (obi_instr_push) begin + obi_instr_request_n <= obi_instr_request == 3'd7 ? obi_instr_request + 3'd2 : obi_instr_request + 3'd1; + end else begin + obi_instr_request_n <= obi_instr_request; + end + + if (obi_instr_pop) begin + obi_instr_service_n <= obi_instr_service == 3'd7 ? obi_instr_service + 3'd2 : obi_instr_service + 3'd1; + end else begin + obi_instr_service_n <= obi_instr_service; + end + + if (obi_data_push) begin + obi_data_request_n <= obi_data_request == 3'd7 ? obi_data_request + 3'd2 : obi_data_request + 3'd1; + end else begin + obi_data_request_n <= obi_data_request; + end + + if (obi_data_pop) begin + obi_data_service_n <= obi_data_service == 3'd7 ? obi_data_service + 3'd2 : obi_data_service + 3'd1; + end else begin + obi_data_service_n <= obi_data_service; + end + end + + // New obi_instr read request + assign obi_instr_push = obi_instr_req && obi_instr_gnt; + // New obi_instr read fulfillment + assign obi_instr_pop = obi_instr_rvalid && obi_instr_rready; + + // New obi_data read request + assign obi_data_push = obi_data_req && obi_data_gnt; + // New obi_data read fulfillment + assign obi_data_pop = obi_data_rvalid && obi_data_rready; + + assign obi_instr_pending = obi_instr_req && !obi_instr_gnt; + assign obi_data_pending = obi_data_req && !obi_data_gnt; + + + always_comb begin + if (!rst_ni) begin + is_read_mtvt_table_val_obi <= 1'b0; + end + else begin + is_read_mtvt_table_val_obi <= (obi_instr_addr inside { [mtvt:mtvt+mtvt_max_offset ]}) && obi_instr_req && obi_instr_gnt; + end + end + + logic is_write_mtvt_table_val_obi; + always_comb begin + if (!rst_ni) begin + is_write_mtvt_table_val_obi <= 1'b0; + end + else begin + is_write_mtvt_table_val_obi <= (obi_data_addr inside { [mtvt:mtvt+mtvt_max_offset ]}) && obi_data_req && obi_data_gnt && obi_data_we; + end + end + + + always @(posedge clk_i) begin + if (!rst_ni) begin + last_mtvt_table_read_addr <= 0; + end else begin + if ($fell(is_read_mtvt_table_val_obi)) begin + last_mtvt_table_read_addr <= $past(obi_instr_addr); + end else begin + last_mtvt_table_read_addr <= last_mtvt_table_read_addr; + end + end + end + + + assign is_mtvt_store_event = is_store_instr_addr_in_mtvt_region(rvfi_insn) && !rvfi_trap.exception && rvfi_valid; + assign is_mtvt_load_event = is_read_mtvt_table_val_obi; + + `ifdef FORMAL + always@* begin + if (!rst_ni) begin + no_mtvt_store_event_occurred <= 1'b1; + end + if (is_mtvt_store_event) begin + mtvt_write_offset <= rvfi_rs1_rdata + s_imm - mtvt; + mtvt_table_value[(CLIC_ID_WIDTH)'(mtvt_write_offset/'d4)] <= rvfi_rs2_rdata; + no_mtvt_store_event_occurred <= 0; + end + else if (no_mtvt_store_event_occurred && is_mtvt_load_event) begin + mtvt_read_offset <= rvfi_rs1_rdata + i_imm - mtvt; + mtvt_table_value[(CLIC_ID_WIDTH)'(mtvt_read_offset/'d4)] <= rvfi_rd_wdata; + end + end + `else + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mtvt_table_value <= {<<{'0}}; + end else if (is_read_from_mtvt) begin + mtvt_table_value[(CLIC_ID_WIDTH)'((obi_instr_fifo_tag_out.addr - mtvt)/4)] <= obi_instr_rdata; + end + end + `endif + + sequence s_store_mtvt_value; + @(posedge clk_i) + + is_mtvt_store_event; + endsequence : s_store_mtvt_value + + + assign is_mtvt_table_access = obi_instr_addr inside { [mtvt : mtvt + ((2**CLIC_ID_WIDTH)*4)-1] } && obi_instr_push; + assign is_read_from_mtvt = obi_instr_fifo_tag_out.addr inside { [ mtvt : mtvt + ((2**CLIC_ID_WIDTH)*4)-1 ] } && obi_instr_pop; + + assign obi_instr_fifo_tag_wena = obi_instr_fifo_tag_we ? ( 8'h1 << obi_instr_fifo_tag_waddr ) : 8'h00; + assign obi_instr_fifo_tag_rena = obi_instr_fifo_tag_re ? ( 8'h1 << obi_instr_fifo_tag_raddr ) : 8'h00; + + assign obi_data_fifo_tag_wena = obi_data_fifo_tag_we ? ( 8'h1 << obi_data_fifo_tag_waddr ) : 8'h00; + assign obi_data_fifo_tag_rena = obi_data_fifo_tag_re ? ( 8'h1 << obi_data_fifo_tag_raddr ) : 8'h00; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + obi_instr_fifo_tag_waddr_ff <= 0; + obi_data_fifo_tag_waddr_ff <= 0; + obi_instr_fifo_tag_raddr_ff <= 0; + obi_data_fifo_tag_raddr_ff <= 0; + obi_instr_fifo_tag_waddr <= 0; + obi_data_fifo_tag_waddr <= 0; + obi_instr_fifo_tag_raddr <= 0; + obi_data_fifo_tag_raddr <= 0; + end else begin + + if (obi_instr_fifo_tag_we) begin + obi_instr_fifo_tag_waddr <= obi_instr_fifo_tag_waddr < 3'd7 ? obi_instr_fifo_tag_waddr + 3'd1 : obi_instr_fifo_tag_waddr + 3'd2; + end else begin + obi_instr_fifo_tag_waddr <= obi_instr_fifo_tag_waddr; + end + + if (obi_data_fifo_tag_we) begin + obi_data_fifo_tag_waddr <= obi_data_fifo_tag_waddr < 3'd7 ? obi_data_fifo_tag_waddr + 3'd1 : obi_data_fifo_tag_waddr + 3'd2; + end else begin + obi_data_fifo_tag_waddr <= obi_data_fifo_tag_waddr; + end + + if (obi_instr_fifo_tag_re) begin + obi_instr_fifo_tag_raddr <= obi_instr_fifo_tag_raddr < 3'd7 ? obi_instr_fifo_tag_raddr + 3'd1 : obi_instr_fifo_tag_raddr + 3'd2; + end else begin + obi_instr_fifo_tag_raddr <= obi_instr_fifo_tag_raddr; + end + + if (obi_data_fifo_tag_re) begin + obi_data_fifo_tag_raddr <= obi_data_fifo_tag_raddr < 3'd7 ? obi_data_fifo_tag_raddr + 3'd1 : obi_data_fifo_tag_raddr + 3'd2; + end else begin + obi_data_fifo_tag_raddr <= obi_data_fifo_tag_raddr; + end + + // obi instr fifo write + if (obi_instr_fifo_tag_we) begin + obi_instr_fifo_tag_waddr_ff <= obi_instr_fifo_tag_waddr; + end else begin + obi_instr_fifo_tag_waddr_ff <= obi_instr_fifo_tag_waddr_ff; + end + // obi instr fifo read + if (obi_instr_fifo_tag_re) begin + obi_instr_fifo_tag_raddr_ff <= obi_instr_fifo_tag_raddr; + end else begin + obi_instr_fifo_tag_raddr_ff <= obi_instr_fifo_tag_raddr_ff; + end + + // obi data fifo write + if (obi_data_fifo_tag_we) begin + obi_data_fifo_tag_waddr_ff <= obi_data_fifo_tag_waddr; + end else begin + obi_data_fifo_tag_waddr_ff <= obi_data_fifo_tag_waddr_ff; + end + // obi data fifo read + if (obi_data_fifo_tag_re) begin + obi_data_fifo_tag_raddr_ff <= obi_data_fifo_tag_raddr; + end else begin + obi_data_fifo_tag_raddr_ff <= obi_data_fifo_tag_raddr_ff; + end + end + end + + for (genvar i = 0; i < 8; i++) begin + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + obi_instr_fifo_tag_ff[i] <= '0; + obi_data_fifo_tag_ff[i] <= '0; + end else begin + if (obi_instr_fifo_tag_wena[i]) begin + obi_instr_fifo_tag_ff[i].tag <= obi_instr_request_n; + obi_instr_fifo_tag_ff[i].addr <= obi_instr_addr; + obi_instr_fifo_tag_ff[i].is_mret <= obi_req_is_mret; + obi_instr_fifo_tag_ff[i].is_clicv <= obi_req_is_clicv; + end else begin + obi_instr_fifo_tag_ff[i] <= obi_instr_fifo_tag_ff[i]; + end + + if (obi_data_fifo_tag_wena[i]) begin + obi_data_fifo_tag_ff[i].tag <= obi_data_request_n; + obi_data_fifo_tag_ff[i].addr <= obi_data_addr; + obi_data_fifo_tag_ff[i].is_mret <= 0; // Not used for data fifo + obi_data_fifo_tag_ff[i].is_clicv <= 0; // Not used for data fifo + end else begin + obi_data_fifo_tag_ff[i] <= obi_data_fifo_tag_ff[i]; + end + end + end + end + + always_comb begin + case (obi_instr_fifo_tag_rena) + 8'b1 << 0: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[0]; + 8'b1 << 1: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[1]; + 8'b1 << 2: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[2]; + 8'b1 << 3: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[3]; + 8'b1 << 4: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[4]; + 8'b1 << 5: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[5]; + 8'b1 << 6: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[6]; + 8'b1 << 7: obi_instr_fifo_tag_out <= obi_instr_fifo_tag_ff[7]; + default: obi_instr_fifo_tag_out <= '0; + endcase + + case (obi_data_fifo_tag_rena) + 8'b1 << 0: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[0]; + 8'b1 << 1: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[1]; + 8'b1 << 2: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[2]; + 8'b1 << 3: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[3]; + 8'b1 << 4: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[4]; + 8'b1 << 5: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[5]; + 8'b1 << 6: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[6]; + 8'b1 << 7: obi_data_fifo_tag_out <= obi_data_fifo_tag_ff[7]; + default: obi_data_fifo_tag_out <= '0; + endcase + end + + //this signal remembers the return address from an mret related pointer fetch. + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mepc_as_pointer_rdata <= '0; + //logic is_first_instr; + end else begin + if (obi_instr_fifo_tag_rena && obi_instr_fifo_tag_out.is_mret) begin + mepc_as_pointer_rdata <= {obi_instr_rdata[31:1], 1'b0}; + end + end + end + + + // signal obi_req_is_mret is high if the address phase originates from an mret in the pc_mux + assign obi_req_is_mret = (pc_mux_mret_q && !delayed_mret_req) || (!support_if.instr_bus_addr_ph_cont && (pc_mux == PC_MUX_MRET && pc_set)); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pc_mux_mret_q <= 0; + delayed_mret_req <= 0; + end else begin + // if the pc mux mret-related address phase is delayed, we need to remember it + if (pc_mux == PC_MUX_MRET && pc_set && (!(obi_instr_req && obi_instr_gnt) || support_if.instr_bus_addr_ph_cont)) begin + pc_mux_mret_q <= 1; + // double delay, previous address phase is not gnt'ed + if (support_if.instr_bus_addr_ph_cont && !(obi_instr_req && obi_instr_gnt)) begin + delayed_mret_req <= 1; + end + end else if (delayed_mret_req == 1 && obi_instr_req && obi_instr_gnt) begin + delayed_mret_req <= 0; + end else if (obi_instr_req && obi_instr_gnt) begin + pc_mux_mret_q <= 0; + end + end + end + + //this signal remembers the return address from a clicv related pointer fetch. + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + clicv_pointer_rdata <= '0; + end else begin + if (obi_instr_fifo_tag_rena && obi_instr_fifo_tag_out.is_clicv) begin + clicv_pointer_rdata <= {obi_instr_rdata[31:1], 1'b0}; + end + end + end + + // signal obi_req_is_clicv is high if the address phase originates from a clicv in the pc_mux + assign obi_req_is_clicv = (pc_mux_clicv_q && !delayed_clicv_req) || (!support_if.instr_bus_addr_ph_cont && (pc_mux == PC_MUX_CLICV && pc_set)); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pc_mux_clicv_q <= 0; + delayed_clicv_req <= 0; + end else begin + // if the pc mux clicv-related address phase is delayed, we need to remember it + if (pc_mux == PC_MUX_CLICV && pc_set && (!(obi_instr_req && obi_instr_gnt) || support_if.instr_bus_addr_ph_cont)) begin + pc_mux_clicv_q <= 1; + // double delay, previous address phase is not gnt'ed + if (support_if.instr_bus_addr_ph_cont && !(obi_instr_req && obi_instr_gnt)) begin + delayed_clicv_req <= 1; + end + end else if (delayed_clicv_req == 1 && obi_instr_req && obi_instr_gnt) begin + delayed_clicv_req <= 0; + end else if (obi_instr_req && obi_instr_gnt) begin + pc_mux_clicv_q <= 0; + end + end + end + + + + + assign obi_instr_fifo_tag_we = obi_instr_push; + assign obi_data_fifo_tag_we = obi_data_push; + + assign obi_instr_fifo_tag_re = obi_instr_pop; + assign obi_data_fifo_tag_re = obi_data_pop; + + property p_mtvt_table_read_equals_value_written; + is_read_from_mtvt + |-> + obi_instr_rdata == mtvt_table_value[(CLIC_ID_WIDTH)'((obi_instr_fifo_tag_out.addr - mtvt)/4)]; + + endproperty : p_mtvt_table_read_equals_value_written + + property p_fencei_guarantee_visible_mtvt_write; + accept_on( + // Assume that mtvt is not changed - otherwise complexity of assertion explodes + !$stable(mtvt, @(posedge clk_i)) + ) + s_store_mtvt_value + ##1 (is_fencei_instr && rvfi_valid)[->1] + ##1 (irq_ack && clic_core.shv)[->1] + ##1 rvfi_valid[->1] + |-> + // past because oic.id might have taken a new interrupt here, with cleared lower bit + rvfi_pc_rdata == (($past(mtvt_table_value[clic_oic.id]) >> 1) << 1) + or + // Took debug instead, make sure dpc is correct + rvfi_dbg + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == (($past(mtvt_table_value[clic_oic.id]) >> 1) << 1) + or + is_invalid_instr_word + or + is_cause_nmi + or + is_trap_exception + or + // This should not be necessary, but inconsistent rvfi signaling on shv traps necessitates this check + is_intr_exception + ; + endproperty : p_fencei_guarantee_visible_mtvt_write + + a_fencei_guarantee_visible_mtvt_write: assert property (p_fencei_guarantee_visible_mtvt_write) + else + `uvm_error(info_tag, + $sformatf("Fencei should _always_ make writes to mtvt visible to next taken shv interrupt")); + + // ------------------------------------------------------------------------ + // dpc correct when interrupting clic-interrupts + // ------------------------------------------------------------------------ + property p_dpc_to_mtvt_shv; + irq_ack + && clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ + |-> + // Regular case + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == (($past(mtvt_table_value[clic_oic.id]) >> 1) << 1) + && rvfi_intr.interrupt + or + // NMI + rvfi_intr.interrupt + && rvfi_intr.cause >= 11'h400 + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + or + // Trap + rvfi_trap.exception + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == debug_exc_addr + ; + endproperty : p_dpc_to_mtvt_shv + + a_dpc_to_mtvt_shv : assert property (p_dpc_to_mtvt_shv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_mtvec_nonshv; + irq_ack + && !clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ + |-> + // Regular case && nmi (identical behavior) + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + && rvfi_intr.interrupt + or + // Trap + rvfi_trap.exception + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == debug_exc_addr + ; + endproperty : p_dpc_to_mtvec_nonshv + + a_dpc_to_mtvec_nonshv : assert property (p_dpc_to_mtvec_nonshv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + logic [31:0] past_rvfi_pc_wdata; + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + past_rvfi_pc_wdata <= 0; + end else begin + if ($rose(dut_wrap.cv32e40s_wrapper_i.core_i.fetch_enable)) begin + past_rvfi_pc_wdata <= {dut_wrap.cv32e40s_wrapper_i.core_i.boot_addr_i[31:2] , 2'b00}; + end else if (rvfi_valid) begin + past_rvfi_pc_wdata <= rvfi_pc_wdata; + end + end + end + + property p_dpc_to_pc_halt; + $rose(support_if.first_debug_ins) + ##0 rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ + |-> + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && rvfi_dpc_rdata == past_rvfi_pc_wdata + or + // Interrupt or nmi (checked above) + rvfi_intr.interrupt + or + // Trap + rvfi_trap.exception + ; + endproperty : p_dpc_to_pc_halt + + a_dpc_to_pc_halt : assert property (p_dpc_to_pc_halt) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_pc_step; + $rose(support_if.first_debug_ins) + ##0 rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP + |-> + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && rvfi_dpc_rdata == past_rvfi_pc_wdata + or + // Interrupt or nmi (checked below) + rvfi_intr.interrupt + or + // Trap + rvfi_trap.exception + ; + endproperty : p_dpc_to_pc_step + + a_dpc_to_pc_step : assert property (p_dpc_to_pc_step) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_mtvt_step_irq_shv; + irq_ack + && clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP + |-> + // Regular case + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == (($past(mtvt_table_value[clic_oic.id]) >> 1) << 1) + && rvfi_intr.interrupt + or + // NMI + rvfi_intr.interrupt + && rvfi_intr.cause >= 11'h400 + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + ; + endproperty : p_dpc_to_mtvt_step_irq_shv + + a_dpc_to_mtvt_step_irq_shv : assert property (p_dpc_to_mtvt_step_irq_shv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_mtvec_step_irq_nonshv; + irq_ack + && !clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP + |-> + // Regular case && nmi (identical behavior) + rvfi_dbg + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + && rvfi_intr.interrupt + ; + endproperty : p_dpc_to_mtvec_step_irq_nonshv + + a_dpc_to_mtvec_step_irq_nonshv : assert property (p_dpc_to_mtvec_step_irq_nonshv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + + // ------------------------------------------------------------------------ + // mtvt aligned correctly + // ------------------------------------------------------------------------ + + property p_mtvt_alignment_correct; + disable iff (!rst_ni || N_MTVT <= 6) // Disable if field does not exist + mtvt_fields.base_n_0 == '0; + endproperty : p_mtvt_alignment_correct + + a_mtvt_alignment_correct: assert property (p_mtvt_alignment_correct) + else + `uvm_error(info_tag, + $sformatf("mtvt alignment should have been %d bytes, mtvt: %08x", + (2 ** N_MTVT), + mtvt)); + + // ------------------------------------------------------------------------ + // mepc is always set correctly when taking an interrupt + // ------------------------------------------------------------------------ + + + // Formal tools generate warnings for latch behavior in assign statements, use explicit always_latch here + always_latch begin + next_pc <= !rst_ni ? '0 : rvfi_valid ? rvfi_pc_wdata : next_pc ; + end + + property p_mepc_set_correct_after_irq; + logic [31:0] sampled_next_pc; + // checks both csr_output and rvfi rdata + irq_ack + ##1 (1, sampled_next_pc = rvfi_pc_wdata) + ##0 rvfi_valid[->1] + |-> + // 1. Normal case + sampled_next_pc == $past(next_pc) // should always match) + && rvfi_intr.cause < 'h400 // no nmi + && rvfi_intr.exception == 1'b0 + && rvfi_mepc_rdata == $past(next_pc) // does not match with nmi + or + // 2. Nmi occurred + sampled_next_pc == $past(next_pc) // should always match + && rvfi_intr.cause >= 'h400 + && !(is_mepc_access_instr && is_csr_write) + && rvfi_mepc_rdata == (mtvec_fields & ~32'b11) + or + // 3. Handler rewrites mtvec addr, and nmi occurred on new mtvec + sampled_next_pc == $past(next_pc) + && is_cause_nmi + && is_mtvec_access_instr && is_csr_write + or + // 4. Handler rewrites mepc addr, and nmi occurred on new mepc + sampled_next_pc == $past(next_pc) + && is_cause_nmi + && is_mepc_access_instr && is_csr_write + or + // 5. Hardware vectored interrupt, but with instruction access fault exception on mtvt + sampled_next_pc == $past(next_pc) + && clic_oic.shv == 1'b1 + && rvfi_intr.cause == 'h1 + && rvfi_mepc_rdata == (mtvec_fields & ~32'b11) + or + // 6. Hardware vectored interrupt, but with instruction access fault on mtvt target + sampled_next_pc == $past(next_pc) + && clic_oic.shv == 1'b1 + && rvfi_intr.cause == 'h1 + && rvfi_mepc_rdata == mtvt_fields + (4 * clic_oic.id) + or + // 7. Hardware vectored interrupt without instruction access fault + sampled_next_pc == $past(next_pc) + && clic_oic.shv == 1'b1 + && rvfi_intr.exception == 1'b0 + && rvfi_mepc_rdata == sampled_next_pc + or + // 8. Last instruction prior to irq_ack enables irq, shv-irq and first instruction in handler gets interrupted + // and this traps with instruction access fault + // irq_ack followed by irq ack + sampled_next_pc == $past(next_pc) + && $changed(clic_oic) == 1'b1 + && $past(clic_oic.shv) == 1'b1 + && rvfi_intr.cause == 1'h1 + && rvfi_mepc_rdata == mtvt_fields + (4 * $past(clic_oic.id)) + or + // 9. Nested interrupt, with first being shv, second non-shv + sampled_next_pc == $past(next_pc) + && $changed(clic_oic) == 1'b1 + && $past(clic_oic.shv) == 1'b1 + && clic_oic.shv == 1'b0 + && rvfi_intr.cause == 1'h1 + && rvfi_mepc_rdata == mtvec_fields & ~32'b11 + or + // 10. non-nested, mtvt fail with mtvt write + sampled_next_pc == $past(next_pc) + && $stable(clic_oic) == 1'b1 + && clic_oic.shv == 1'b1 + && rvfi_intr.cause == 1'h1 + && is_mtvt_access_instr && is_csr_write + && rvfi_mepc_rdata == $past(mtvt_fields) + (4 * clic_oic.id) + or + // 11. nested interrupts mtvt fail with mtvt write + sampled_next_pc == $past(next_pc) + && $changed(clic_oic) == 1'b1 + && $past(clic_oic.shv) == 1'b1 + && rvfi_intr.cause == 1'h1 + && is_mtvt_access_instr && is_csr_write + && rvfi_mepc_rdata == $past(mtvt_fields) + (4 * $past(clic_oic.id)) + or + // 12. Nmi occurred with shv first + sampled_next_pc == $past(next_pc) // should always match + && rvfi_intr.cause >= 'h400 + && !(is_mepc_access_instr && is_csr_write) + && $past(clic_oic.shv) == 1'b1 + && rvfi_mepc_rdata == clicv_pointer_rdata + + ; + endproperty : p_mepc_set_correct_after_irq; + + a_mepc_set_correct_after_irq: assert property (p_mepc_set_correct_after_irq) + else + `uvm_error(info_tag, + $sformatf("Wrong mepc (0x%08x)", + mepc_fields)); + + // ------------------------------------------------------------------------ + // mcause.interrupt is always set when taking an interrupt + // ------------------------------------------------------------------------ + + property p_mcause_interrupt_always_set_on_taken_irq; + irq_ack + |=> + mcause_fields.interrupt; + endproperty : p_mcause_interrupt_always_set_on_taken_irq + + a_mcause_interrupt_always_set_on_taken_irq: assert property (p_mcause_interrupt_always_set_on_taken_irq) + else + `uvm_error(info_tag, + $sformatf("mcause.interrupt should be set on taken interrupts")); + + // ------------------------------------------------------------------------ + // mcause.cause is always set correctly after taking an interrupt + // ------------------------------------------------------------------------ + + property p_mcause_exccode_always_set_correctly_on_taken_irq; + irq_ack + |=> + mcause_fields.n.exccode_10_0 == $past(clic_core.id); + endproperty : p_mcause_exccode_always_set_correctly_on_taken_irq + + a_mcause_exccode_always_set_correctly_on_taken_irq: assert property (p_mcause_exccode_always_set_correctly_on_taken_irq) + else + `uvm_error(info_tag, + $sformatf("mcause.exccode should be set on taken interrupts")); + + + // ------------------------------------------------------------------------ + // mcause.mpil should reflect the previous privilege mode after taking + // an interrupt + // ------------------------------------------------------------------------ + + property p_mcause_mpil_reflects_previous_interrupt_lvl; + bit [7:0] il_prev; + (irq_ack, il_prev = mintstatus_fields.mil) |=> mcause_fields.mpil == il_prev; + endproperty : p_mcause_mpil_reflects_previous_interrupt_lvl + + a_mcause_mpil_reflects_previous_interrupt_lvl: assert property (p_mcause_mpil_reflects_previous_interrupt_lvl) + else + `uvm_error(info_tag, + $sformatf("mpil wrong, value: %0d", + mcause_fields.mpil)); + + // ------------------------------------------------------------------------ + // mcause.mpp should reflect the previous privilege mode after taking an + // interrupt + // ------------------------------------------------------------------------ + + property p_mcause_we_cover; + reject_on(rvfi_trap) + is_mcause_access_instr + && csr_instr.n.rs1 != 0 + && csr_instr.rd != 0 + && (~|rvfi_trap) + && rvfi_valid + ##1 + rvfi_valid[=5]; + endproperty : p_mcause_we_cover + + property p_mstatus_we_cover; + reject_on(rvfi_trap) + is_mstatus_access_instr + && csr_instr.n.rs1 != 0 + && csr_instr.rd != 0 + && (~|rvfi_trap) + && rvfi_valid + ##1 + rvfi_valid[=5]; + endproperty : p_mstatus_we_cover + + property p_mnxti_we_cover; + reject_on(rvfi_trap) + is_mnxti_access_instr + && csr_instr.n.rs1 != 0 + && csr_instr.rd != 0 + && (~|rvfi_trap) + && rvfi_valid + ##1 + rvfi_valid[=5]; + endproperty : p_mnxti_we_cover + + property p_mstatus_mpp_neq_mcause_mpp; + mstatus_fields.mpp == mcause_fields.mpp; + endproperty : p_mstatus_mpp_neq_mcause_mpp + + property p_mstatus_mpie_neq_mcause_mpie; + mstatus_fields.mpie == mcause_fields.mpie; + endproperty : p_mstatus_mpie_neq_mcause_mpie + + a_mpp: assert property (p_mstatus_mpp_neq_mcause_mpp) + else + `uvm_error(info_tag, "'mstatus.mpp' must match 'mcause.mpp'"); + a_mpie: assert property (p_mstatus_mpie_neq_mcause_mpie) + else + `uvm_error(info_tag, "'mstatus.mpie' must match 'mcause.mpie'"); + + property p_mcause_mpp_reflects_previous_privilege_mode; + bit [1:0] mode_prev = 2'b11; + irq_ack + |=> + mcause_fields.mpp == $past(current_priv_mode); + endproperty : p_mcause_mpp_reflects_previous_privilege_mode + + a_mcause_mpp_reflects_previous_privilege_mode: assert property (p_mcause_mpp_reflects_previous_privilege_mode) + else + `uvm_error(info_tag, + $sformatf("Previous privilege wrong, mpp value: %02b", + mcause_fields.mpp)); + + // ------------------------------------------------------------------------ + // mcause.mpie should reflect the previous interrupt enable after taking + // an interrupt + // ------------------------------------------------------------------------ + + property p_mcause_mpie_reflects_previous_interrupt_enable; + bit mpie_prev; + (irq_ack, mpie_prev = mstatus_fields.mie) |=> mstatus_fields.mpie == mpie_prev; + endproperty : p_mcause_mpie_reflects_previous_interrupt_enable + + a_mcause_mpie_reflects_previous_interrupt_enable: assert property (p_mcause_mpie_reflects_previous_interrupt_enable) + else + `uvm_error(info_tag, + $sformatf("mpie wrong, value: %0b", + mcause_fields.mpie)); + + // ------------------------------------------------------------------------ + // mnxti should return the value of the currently taken interrupt + // if the pending interrupt in clic is the same as the interrupt id + // in the current context + // ------------------------------------------------------------------------ + + always_latch begin + clic_oic <= !rst_ni ? '0 : irq_ack ? clic_core : clic_oic; + end + + sequence seq_irq_req_unchanged; + @(posedge clk_i) + + clic == clic_oic; + endsequence : seq_irq_req_unchanged + + sequence seq_valid_irq_pending(s_clic); + clic_irq_bundle_t sampled_clic = s_clic; + + @(posedge clk_i) + + sampled_clic.priv == M_MODE + && sampled_clic.level > mcause_fields.mpil + && sampled_clic.level > mintthresh_fields.th + && !sampled_clic.shv + && csr_instr.rd; + endsequence : seq_valid_irq_pending + + property p_mnxti_case_1_irq_req_unchanged; + // Due to simulator issues (xcelium) one cannot sample sampled_clic = clic, must sample individual signals + clic_irq_bundle_t sampled_clic; + (seq_irq_req_unchanged.triggered, + sampled_clic.irq = clic.irq, + sampled_clic.id = clic.id, + sampled_clic.level = clic.level, + sampled_clic.priv = clic.priv, + sampled_clic.shv = clic.shv) + ##2 + is_valid_mnxti_read && !irq_ack + |-> + // Return pointer to current interrupt entry + (rvfi_rd_wdata == mtvt_fields + (clic_oic.id * 4)) + && sampled_clic.irq + && sampled_clic.priv == M_MODE + && sampled_clic.level > mcause_fields.mpil + && sampled_clic.level > mintthresh_fields.th + && !sampled_clic.shv + && csr_instr.rd + or + // Return 0 if no irq, not higher level, or shv, or previous mnxti updated the context such that the previous + // levels are no longer valid or destination register = x0 + rvfi_rd_wdata == 0 + && !(sampled_clic.irq + && sampled_clic.priv == M_MODE + && sampled_clic.level > mcause_fields.mpil + && sampled_clic.level > mintthresh_fields.th + && !sampled_clic.shv) + or + // Destination register is x0 (zero) - no read value + rvfi_rd_wdata == 0 + && csr_instr.rd == X0 + or + rvfi_trap.debug + or + rvfi_trap.exception + ; + endproperty : p_mnxti_case_1_irq_req_unchanged + + a_mnxti_case_1_irq_req_unchanged: assert property (p_mnxti_case_1_irq_req_unchanged) + else + `uvm_error(info_tag, + $sformatf("No change on pending interrupt, mnxti incorrect result")); + + // ------------------------------------------------------------------------ + // mnxti should return the table entry for the new, higher level + // interrupt when this new interrupt has superceeded the initial + // interrupt. + // ------------------------------------------------------------------------ + + sequence seq_higher_lvl_nonshv_clic_taken; + @(posedge clk_i) + + clic.irq + && clic.level > mcause_fields.mpil + && clic.level > mintthresh_fields.th + && clic.priv == clic_oic.priv + && !clic.shv; + endsequence : seq_higher_lvl_nonshv_clic_taken + + property p_mnxti_case_2_replaced_by_higher_level_non_shv_irq; + logic [CLIC_ID_WIDTH-1:0] sampled_clic_id; + (seq_higher_lvl_nonshv_clic_taken.triggered, sampled_clic_id = clic.id) + ##2 + is_valid_mnxti_read + |-> + // Return pointer to current interrupt entry + (rvfi_rd_wdata == mtvt_fields + (sampled_clic_id * 4)) + or + // rvfi masks out reads that are written to x0 + csr_instr.rd == X0 + && rvfi_rd_wdata == 0 + or + rvfi_trap.debug + or + rvfi_trap.exception; + endproperty : p_mnxti_case_2_replaced_by_higher_level_non_shv_irq + + + a_mnxti_case_2_replaced_by_higher_level_non_shv_irq: assert property (p_mnxti_case_2_replaced_by_higher_level_non_shv_irq) + else + `uvm_error(info_tag, + $sformatf("interrupt replaced by higher level non-shv interrupt, mnxti incorrect result")); + + // ------------------------------------------------------------------------ + // mnxti should return the value of the lower leveled interrupt + // when the original interrupt is no longer present and the new + // interrupt has a level higher than the interrupted context + // already in clic + // ------------------------------------------------------------------------ + + sequence seq_lower_oic_no_longer_presesnt_lower_lvl_pending; + @(posedge clk_i) + + clic.irq + && clic.level > mcause_fields.mpil + && clic.level <= clic_oic.level + && clic.level > mintthresh_fields.th + && clic.priv == clic_oic.priv + && !clic.shv; + endsequence : seq_lower_oic_no_longer_presesnt_lower_lvl_pending + + property p_mnxti_case_4_replaced_by_lower_level_irq; + logic [CLIC_ID_WIDTH-1:0] sampled_clic_id; + seq_higher_lvl_nonshv_clic_taken.triggered + ##2 is_valid_mnxti_write + ##1 (seq_lower_oic_no_longer_presesnt_lower_lvl_pending.triggered[->1], sampled_clic_id = clic.id) + ##2 is_valid_mnxti_read + |-> + (rvfi_rd_wdata == mtvt_fields + (sampled_clic_id * 4)) + or + csr_instr.rd == X0 + && rvfi_rd_wdata == 0 + or + rvfi_trap.debug + or + rvfi_trap.exception; + endproperty : p_mnxti_case_4_replaced_by_lower_level_irq + + a_mnxti_case_4_replaced_by_lower_level_irq: assert property (p_mnxti_case_4_replaced_by_lower_level_irq) + else + `uvm_error(info_tag, + $sformatf("interrupt replaced by lower level interrupt, mnxti result incorrect")); + + // ------------------------------------------------------------------------ + // mnxti should read zero if the original interrupt is no longer asserted + // ------------------------------------------------------------------------ + + property p_mnxti_case_5_1_no_current_irq; + !clic.irq + ##2 is_valid_mnxti_read + |-> + rvfi_rd_wdata == 32'h0000_0000; + endproperty : p_mnxti_case_5_1_no_current_irq + + a_mnxti_case_5_1_no_current_irq : assert property (p_mnxti_case_5_1_no_current_irq) + else + `uvm_error(info_tag, + $sformatf("mnxti should read zero when no irq is present")); + + // ------------------------------------------------------------------------ + // mnxti should read zero if the current pending interrupt has a + // level lower than mpil + // ------------------------------------------------------------------------ + + sequence seq_nonshv_lower_lvl_pending; + @(posedge clk_i) + + clic.irq + && !clic.shv + && (clic.level < mcause_fields.mpil); + endsequence : seq_nonshv_lower_lvl_pending + + property p_mnxti_case_5_2_lvl_nonshv_pending; + seq_nonshv_lower_lvl_pending.triggered + ##2 is_valid_mnxti_read + |-> + rvfi_rd_wdata == 32'h0000_0000; + endproperty : p_mnxti_case_5_2_lvl_nonshv_pending + + a_mnxti_case_5_2_lvl_nonshv_pending : assert property (p_mnxti_case_5_2_lvl_nonshv_pending) + else + `uvm_error(info_tag, + $sformatf("mnxti should read zero when irq is lower level and non-shv")); + + // ------------------------------------------------------------------------ + // mnxti should read zero if higher level shv interrupt has succeeded + // the initial interrerupt + // ------------------------------------------------------------------------ + + sequence seq_higher_lvl_shv_irq_pending; + @(posedge clk_i) + + clic.irq + && clic.shv + && clic.level > mintthresh_fields.th + && clic.level > mcause_fields.mpil; + endsequence : seq_higher_lvl_shv_irq_pending + + property p_mnxti_case_6_higher_level_irq_superceed; + seq_higher_lvl_shv_irq_pending.triggered + ##2 is_valid_mnxti_read + |-> + rvfi_rd_wdata == 32'h0000_0000; + endproperty : p_mnxti_case_6_higher_level_irq_superceed + + a_mnxti_case_6_higher_level_irq_superceed: assert property (p_mnxti_case_6_higher_level_irq_superceed) + else + `uvm_error(info_tag, + $sformatf("mnxti should read zero when a higher level shv interrupt is pending")); + + // ------------------------------------------------------------------------ + // mnxti CSR side effects on write + // ------------------------------------------------------------------------ + + sequence seq_pending_nonshv_irq; + @(posedge clk_i) + + clic.irq + && !clic.shv + && clic.level > mintthresh_fields.th + && clic.level > mcause_fields.mpil + && clic.priv == M_MODE; + endsequence : seq_pending_nonshv_irq + + property p_mnxti_side_effects_on_write; + logic [$bits(clic.id)-1:0] sampled_id; + logic [$bits(clic.level)-1:0] sampled_level; + + (seq_pending_nonshv_irq, + // Sampled values + sampled_id = clic.id, + sampled_level = clic.level) + ##2 is_valid_mnxti_write + && !rvfi_trap.exception + && !rvfi_trap.debug + |-> + (mintstatus_fields.mil == sampled_level) + && (mcause_fields.n.exccode_10_0 == sampled_id) + && (mcause_fields.interrupt == 1'b1) + + // NOTE: The code below should work, but fails with xcelium - evaluate if this can + // be reenabled if this issue is fixed (needs changes to sampling code above as well): + + // (mintstatus_fields.mil == sampled_clic.level) + //&& (mcause_fields.n.exccode_10_0 == sampled_clic.id) + //&& (mcause_fields.interrupt == 1'b1) + ; + + endproperty : p_mnxti_side_effects_on_write + + a_mnxti_side_effects_on_write: assert property (p_mnxti_side_effects_on_write) + else + `uvm_error(info_tag, + $sformatf("Side effects on mnxti write wrong")); + + property p_mnxti_no_side_effects_on_no_write; + !is_valid_mnxti_write + && is_mnxti_access_instr + |-> + // no change unless trap (below) + $stable(mintstatus_fields) + && $stable(mcause_fields) + or + // mintstatus static if horizontal trap, + // mcause allowed to change + $stable(mintstatus_fields) + && rvfi_trap.exception + && rvfi_trap.trap + ##1 + rvfi_valid[->1] + ##0 + rvfi_intr.exception + && rvfi_intr.intr + && $stable(rvfi_mode) + or + // Clear mintstatus.mil for vertical traps + // mcause allowed to change + mintstatus_fields.mil == 'h0 + && rvfi_trap.exception + && rvfi_trap.trap + ##1 + rvfi_valid[->1] + ##0 + rvfi_intr.exception + && rvfi_intr.intr + && $changed(rvfi_mode) + or + // NMI + //$stable(mintstatus_fields) // FIXME reintroduce to not overconstrain + ##1 rvfi_valid[->1] + ##0 rvfi_intr.interrupt + && rvfi_intr.cause >= 'h400 + ; + endproperty : p_mnxti_no_side_effects_on_no_write + + a_mnxti_no_side_effects_on_no_write: assert property (p_mnxti_no_side_effects_on_no_write) + else + `uvm_error(info_tag, + $sformatf("Should be no side effects on no mnxti write")); + + // ------------------------------------------------------------------------ + // Mintstatus should be updated on ISR handler entry + // ------------------------------------------------------------------------ + + property p_mintstatus_updated_on_isr_handler_entry; + clic.irq + ##1 irq_ack + |=> + mintstatus_fields.mil == clic_oic.level && + mintstatus_fields.sil == 8'h00 && + mintstatus_fields.uil == 8'h00; + endproperty : p_mintstatus_updated_on_isr_handler_entry + + a_mintstatus_updated_on_isr_handler_entry: assert property(p_mintstatus_updated_on_isr_handler_entry) + else + `uvm_error(info_tag, + $sformatf("Minstatus mismatch, read 0x%08h", + mintstatus_fields)); + + // ------------------------------------------------------------------------ + // Minhv should be set when an shv interrupt is taken but ptr fetch fails + // otherwise it should be cleared on an interrupt + // ------------------------------------------------------------------------ + + property p_mcause_minhv_set_at_failing_ptr_fetch; + + (clic.shv ##1 irq_ack ##1 rvfi_valid[->1]) + within + (1 ##1 rvfi_valid ##1 rvfi_valid[->1]) + |-> + // No minhv without clic ptr exception + // and no clic ptr exception without minhv + rvfi_mcause_wdata_fields.minhv ^~ (rvfi_trap.exception && is_instr_clicptr_fault) + or + is_minhv_set_by_sw + ; + endproperty : p_mcause_minhv_set_at_failing_ptr_fetch + + a_mcause_minhv_set_at_failing_ptr_fetch: assert property (p_mcause_minhv_set_at_failing_ptr_fetch) + else + `uvm_error(info_tag, + $sformatf("mcause.minhv not set/cleared correctly")); + + + // ------------------------------------------------------------------------ + // mcause.minhv set, should only have happened if sw set it + // or we took a trap that with a clicptr fault + // ------------------------------------------------------------------------ + property p_mcause_minhv_set_valid; + + (rvfi_valid && !rvfi_mcause_fields.minhv && !rvfi_mcause_wmask_fields.minhv) + ##1 (!rvfi_valid)[*0:$] + ##1 (rvfi_valid && rvfi_mcause_wdata_fields.minhv && rvfi_mcause_wmask_fields.minhv) + |-> + rvfi_trap.exception && is_instr_clicptr_fault + or + is_minhv_set_by_sw + ; + endproperty : p_mcause_minhv_set_valid + + a_mcause_minhv_set_valid: assert property (p_mcause_minhv_set_valid) + else + `uvm_error(info_tag, + $sformatf("mcause.minhv not set in a valid way")); + + // ------------------------------------------------------------------------ + // mcause.minhv cleared, should only have happened if sw cleared it + // or we took a trap that did not have a clicptr fault + // ------------------------------------------------------------------------ + property p_mcause_minhv_clear_valid; + + (rvfi_valid && rvfi_mcause_fields.minhv && !rvfi_mcause_wmask_fields.minhv) + ##1 (!rvfi_valid)[*0:$] + ##1 (rvfi_valid && !rvfi_mcause_wdata_fields.minhv && rvfi_mcause_wmask_fields.minhv) + |-> + // There should be no clicptr fault + not strong (rvfi_trap.exception && is_instr_clicptr_fault) + and ( + // and sw cleared it + is_minhv_cleared_by_sw + or + // or we encountered a trap that did not have a clicptr fault + (rvfi_trap || rvfi_intr) && !is_instr_clicptr_fault + ) + ; + endproperty : p_mcause_minhv_clear_valid + + a_mcause_minhv_clear_valid: assert property (p_mcause_minhv_clear_valid) + else + `uvm_error(info_tag, + $sformatf("mcause.minhv not cleared in a valid way")); + + // ------------------------------------------------------------------------ + // PC should be set to the address fetched from the mtvt pointer after + // taking an shv interrupt + // ------------------------------------------------------------------------ + + sequence s_shv_irq_no_pending_obi; + 1 ##1 !obi_instr_pending + && clic.irq + && clic.shv + ##1 irq_ack + ; + endsequence : s_shv_irq_no_pending_obi + + sequence s_shv_irq_pending_obi; + 1 ##1 obi_instr_pending + && clic.irq + && clic.shv + ##1 irq_ack + ; + endsequence : s_shv_irq_pending_obi + + property p_pc_to_mtvt_for_taken_shv_interrupt_outstanding_obi; + logic [31:0] pointer_value = '0; + logic [31:0] pointer_addr = '0; + logic [3:0] pointer_req = '0; + + s_shv_irq_pending_obi + // Need to finish outstanding obi txn first then get the correct address + ##0 (obi_instr_push[->2], + // Sample address for pointer fetch + pointer_addr = obi_instr_addr, + pointer_req = obi_instr_request_n) + // Wait for rdata and sample expected pc + ##1 ((pointer_req == obi_instr_service_n)[->1]) + ##0 (1, pointer_value = obi_instr_rdata) + ##0 rvfi_valid[->1] + |-> + rvfi_pc_rdata == (pointer_value & ~1) + // use past here as these may be updated by handler instruction or new interrupt + && $past(mtvt_fields) + ($past(clic_oic.id) * 4) == (pointer_addr) + // minhv should be cleared unless explicitly written to + && ((!mcause_fields.minhv && !(is_mcause_access_instr && is_csr_write && rvfi_mcause_wmask[30] && rvfi_mcause_wdata[30])) + || (mcause_fields.minhv && (is_mcause_access_instr && is_csr_write && rvfi_mcause_wmask[30] && rvfi_mcause_wdata[30]))) + or + is_cause_nmi // nmi-address verified in nmi-related assertions + or + is_invalid_instr_word + && rvfi_pc_rdata == { $past(mtvec[31:7]), 7'h0 } + or + is_cause_instr_access_fault || is_cause_instr_bus_fault || is_cause_instr_parity_fault + or + is_instr_access_fault + or + is_instr_clicptr_fault + or + is_mstatus_access_instr && is_csr_write && mstatus_fields.mie + && irq_ack + or + is_mnxti_access_instr && is_csr_write && mstatus_fields.mie + && irq_ack + or + is_mret_instr && $past(mstatus_fields.mpie) + && irq_ack + or + rvfi_dbg_mode + ; + endproperty : p_pc_to_mtvt_for_taken_shv_interrupt_outstanding_obi + + a_pc_to_mtvt_for_taken_shv_interrupt_outstanding_obi: assert property (p_pc_to_mtvt_for_taken_shv_interrupt_outstanding_obi) + else + `uvm_error(info_tag, + $sformatf("Pc should be at mtvt after taking an shv interrupt")); + + property p_pc_to_mtvt_for_taken_shv_interrupt; + logic [31:0] pointer_value = '0; + logic [31:0] pointer_addr = '0; + logic [3:0] pointer_req = '0; + s_shv_irq_no_pending_obi + ##0 (obi_instr_push[->1], + // Sample address for pointer fetch + pointer_addr = obi_instr_addr, + pointer_req = obi_instr_request_n) + // Wait for rdata and sample expected pc + ##1 ((pointer_req == obi_instr_service_n)[->1]) + ##0 (1, pointer_value = obi_instr_rdata) + ##0 rvfi_valid[->1] + |-> + // Normal case, should end up at mtvt + rvfi_pc_rdata == (pointer_value & ~1) + && $past(mtvt_fields) + ($past(clic_oic.id) * 4) == (pointer_addr) + // minhv should be cleared unless explicitly written to + && ((!mcause_fields.minhv && !(is_mcause_access_instr && is_csr_write && rvfi_mcause_wmask[30] && rvfi_mcause_wdata[30])) + || (mcause_fields.minhv && (is_mcause_access_instr && is_csr_write && rvfi_mcause_wmask[30] && rvfi_mcause_wdata[30]))) + or + is_cause_nmi // nmi-address verified in nmi-related assertions + or + is_invalid_instr_word + && rvfi_pc_rdata == { $past(mtvec[31:7]), 7'h0 } + or + is_cause_instr_access_fault || is_cause_instr_bus_fault || is_cause_instr_parity_fault + or + is_instr_access_fault + or + is_instr_clicptr_fault + or + is_mstatus_access_instr && is_csr_write && mstatus_fields.mie + && irq_ack + or + is_mnxti_access_instr && is_csr_write && mstatus_fields.mie + && irq_ack + or + is_mret_instr && $past(mstatus_fields.mpie) + && irq_ack + or + rvfi_dbg_mode + ; + + endproperty : p_pc_to_mtvt_for_taken_shv_interrupt + + a_pc_to_mtvt_for_taken_shv_interrupt: assert property (p_pc_to_mtvt_for_taken_shv_interrupt) + else + `uvm_error(info_tag, + $sformatf("Pc should be at mtvt after taking an shv interrupt")); + + // ------------------------------------------------------------------------ + // PC should be set to mtvec for taken non-shv interrupt + // ------------------------------------------------------------------------ + + property p_pc_to_mtvec_for_taken_nonshv_interrupt; + clic.irq + && !clic.shv + ##1 irq_ack + ##1 rvfi_valid[->1] + |-> + // Need to use past here to avoid the case where mtvec is updated simultaneously + rvfi_pc_rdata[31:7] == $past(mtvec[31:7]) + or + // Nmi, correct pc covered in a_nmi_to_mtvec_offset + is_cause_nmi + or + is_instr_access_fault + or + rvfi_dbg_mode + ; + endproperty : p_pc_to_mtvec_for_taken_nonshv_interrupt + + a_pc_to_mtvec_for_taken_nonshv_interrupt: assert property (p_pc_to_mtvec_for_taken_nonshv_interrupt) + else + `uvm_error(info_tag, + $sformatf("Pc should be at mtvec after taking a non-shv interrupt")); + + // ------------------------------------------------------------------------ + // Correct alignment of the taken non-shv interrupt address + // ------------------------------------------------------------------------ + + property p_pc_alignment_of_taken_non_shv_interrupt; + irq_ack + && !clic_core.shv + ##1 rvfi_valid[->1] + |-> + // Exceptions/interrupts should jump to base address, + // and base addr. should be aligned + !is_cause_nmi + && rvfi_pc_rdata[6:0] == 7'b000_0000 + or + is_cause_nmi + && rvfi_pc_rdata[6:0] == NMI_OFFSET // == all zeros + NMI_OFFSET in table + or + rvfi_dbg_mode + ; + endproperty : p_pc_alignment_of_taken_non_shv_interrupt + + a_pc_alignment_of_taken_non_shv_interrupt: assert property (p_pc_alignment_of_taken_non_shv_interrupt) + else + `uvm_error(info_tag, + $sformatf("Non-shv interrupt taken should have a PC aligned with bits 6:0 = 0")); + + // ------------------------------------------------------------------------ + // Interrupt taken if, and only if the following matches: + // ------------------------------------------------------------------------ + // ------------------------------------------------------------------------ + // Higher level than mintthresh.th interrupts can preempt + // ------------------------------------------------------------------------ + property p_higher_lvl_than_mintthresh_th_can_preempt; + clic.irq + ##1 ($past(clic.priv) == current_priv_mode) + && ($past(clic.level) > effective_clic_level) + && mstatus_fields.mie + && is_interrupt_allowed == 1'b1 + |-> + irq_ack + or + rvfi_valid[->1:2] + ##0 rvfi_dbg_mode + or + rvfi_valid[->1:2] + ##0 rvfi_intr.exception + or + rvfi_valid[->1:2] + ##0 rvfi_trap.exception + or + rvfi_valid[->1:2] + ##0 is_cause_nmi + ; + endproperty : p_higher_lvl_than_mintthresh_th_can_preempt + + a_higher_lvl_than_mintthresh_th_can_preempt: assert property(p_higher_lvl_than_mintthresh_th_can_preempt) + else + `uvm_error(info_tag, + $sformatf("Higher level than mintthresh should be able to interrupt")); + + // ------------------------------------------------------------------------ + // Lower level than mintthresh.th interrupts cannot preempt + // ------------------------------------------------------------------------ + property p_lower_lvl_than_mintthresh_th_cannot_preempt; + clic.irq + ##1 $past(clic.level) < mintthresh_fields.th + && $past(clic.priv) == current_priv_mode + |-> + !irq_ack; + endproperty : p_lower_lvl_than_mintthresh_th_cannot_preempt + + a_lower_lvl_than_mintthresh_th_cannot_preempt: assert property (p_lower_lvl_than_mintthresh_th_cannot_preempt) + else + `uvm_error(info_tag, + $sformatf("Lower than mintthresh.th level interrupts should not preempt")); + + // ------------------------------------------------------------------------ + // WFI wakeup required + // ------------------------------------------------------------------------ + property p_wfi_wfe_wakeup_condition_valid; + logic sampled_wfe_wakeup_event; + clic_irq_bundle_t sampled_clic; + logic [7:0] sampled_level; + priv_mode_t sampled_priv; + + core_sleep_o ##1 // first cycle $fell will fail out of reset + ($fell(core_sleep_o), + sampled_clic.irq = clic.irq, + sampled_clic.id = clic.id, + sampled_clic.level = clic.level, + sampled_clic.priv = clic.priv, + sampled_clic.shv = clic.shv, + sampled_priv = priv_mode_t'(current_priv_mode), + sampled_level = effective_clic_level, + sampled_wfe_wakeup_event = is_wfe_wakeup_event) + ##1 rvfi_valid[->1] + |-> + // Interrupt triggered wake up *both wfe and wfi* + ##0 sampled_clic.irq + && sampled_clic.priv == sampled_priv + && sampled_clic.level > sampled_level + or + // Interrupt triggered wake up *both wfe and wfi* + ##0 sampled_clic.irq + && sampled_clic.priv > sampled_priv + && sampled_clic.level > 0 + or + // Debug request *both wfe and wfi* + ##1 rvfi_valid[->1] + ##0 rvfi_dbg_mode == 1'b1 + or + // Wakeup from wfe-pin, *wfe only* + is_wfe_instr + ##0 sampled_wfe_wakeup_event + ; + endproperty : p_wfi_wfe_wakeup_condition_valid + + a_wfi_wfe_wakeup_condition_valid: assert property (p_wfi_wfe_wakeup_condition_valid) + else + `uvm_error(info_tag, + $sformatf("core should have woken up")); + + // ------------------------------------------------------------------------ + // WFI wakeup forbidden + // ------------------------------------------------------------------------ + property p_wfi_wfe_wakeup_condition_not_valid; + core_sleep_o + ##1 + !(( clic.irq + && clic.priv == priv_mode_t'(current_priv_mode) + && clic.level > effective_clic_level) + || + ( clic.irq + && clic.priv > priv_mode_t'(current_priv_mode) + && clic.level > 0)) + |-> + // Stay asleep + $stable(core_sleep_o) + or + // We slept due to wfe, pin can wake us up + is_wfe_wakeup_event + ##0 !core_sleep_o + ##0 rvfi_valid[->1] + ##0 is_wfe_instr + + or + // We woke up due to a debug request, first retire wfi, then take debug + !core_sleep_o + ##0 rvfi_valid[->2] + ##0 rvfi_dbg_mode + ; + endproperty : p_wfi_wfe_wakeup_condition_not_valid + + a_wfi_wfe_wakeup_condition_not_valid: assert property (p_wfi_wfe_wakeup_condition_not_valid) + else + `uvm_error(info_tag, + $sformatf("core should not have woken up")); + + // ------------------------------------------------------------------------ + // WFI entry causes core to stop + // ------------------------------------------------------------------------ + property p_wfi_wfe_causes_core_to_stop; + core_sleep_o + |-> + !rvfi_valid + ; + endproperty : p_wfi_wfe_causes_core_to_stop + + a_wfi_wfe_causes_core_to_stop: assert property (p_wfi_wfe_causes_core_to_stop) + else + `uvm_error(info_tag, + $sformatf("core should not execute anything in wfi")); + + // ------------------------------------------------------------------------ + // WFI entry causes core clock to be gated + // ------------------------------------------------------------------------ + property p_wfi_wfe_causes_clock_gating; + core_sleep_o + |-> + $stable(clk) + ; + endproperty : p_wfi_wfe_causes_clock_gating + + a_wfi_wfe_causes_clock_gating: assert property (p_wfi_wfe_causes_clock_gating) + else + `uvm_error(info_tag, + $sformatf("core clk should be gated in wfi")); + + // ------------------------------------------------------------------------ + // WFI: core_sleep_o only asserted during wfi + // ------------------------------------------------------------------------ + property p_core_sleep_o_only_during_wfi_wfe; + core_sleep_o + ##0 rvfi_valid[->1] + |-> + is_wfi_instr + or + is_wfe_instr + ; + endproperty : p_core_sleep_o_only_during_wfi_wfe + + a_core_sleep_o_only_during_wfi_wfe: assert property (p_core_sleep_o_only_during_wfi_wfe) + else + `uvm_error(info_tag, + $sformatf("core_sleep_o should only be asserted during wfi")); + + // ------------------------------------------------------------------------ + // Correct state of core after mret + // Regular execution (excludes debug, exceptions etc...) + // ------------------------------------------------------------------------ + + + always @(posedge clk_i) begin + if (!rst_ni || (rvfi_valid && !irq_ack)) begin + irq_ack_occurred_between_valid <= 1'b0; + end else begin + irq_ack_occurred_between_valid <= irq_ack_occurred_between_valid ? 1'b1 : irq_ack; + end + end + + property p_irq_ack_occurred_zero_out_of_reset; + !fetch_enable |-> irq_ack_occurred_between_valid == 1'b0; + endproperty : p_irq_ack_occurred_zero_out_of_reset + + // mret should continue at mepc, or at the pointer fetched from mepc if minhv + // this checks the intention at retirement of mepc, not that the next instruction is correct. + + property p_mret_pc_intended; + rvfi_if.is_mret + && !rvfi_if.rvfi_trap.trap + |-> + rvfi_if.rvfi_pc_wdata == csr_mepc_if.rvfi_csr_rdata + or + rvfi_mcause_fields.minhv && rvfi_if.rvfi_pc_wdata == mepc_as_pointer_rdata; + endproperty : p_mret_pc_intended + + a_mret_pc_intended: assert property (p_mret_pc_intended) + else + `uvm_error(info_tag, + $sformatf("mret result state incorrect")); + + + // this checks actual next instruction, if not interrupt or debug + property p_mret_pc_not_vectored; + rvfi_if.is_mret + && !rvfi_if.rvfi_trap.trap + && !rvfi_mcause_fields.minhv + + ##1 rvfi_valid[->1] + ##0 !(rvfi_if.rvfi_intr.intr || support_if.first_debug_ins) + |-> + rvfi_if.rvfi_pc_rdata == csr_mepc_if.rvfi_csr_rdata; + endproperty : p_mret_pc_not_vectored + + a_mret_pc_not_vectored: assert property (p_mret_pc_not_vectored) + else + `uvm_error(info_tag, + $sformatf("mret result state incorrect")); + + + //mret to umode clears mintthresh + a_mret_umode_clear_mintthresh: assert property ( + rvfi_if.is_mret + ##1 rvfi_valid[->1] + ##0 rvfi_if.is_umode + |-> + csr_mintthresh_if.rvfi_csr_rdata == 0 + ) + else + `uvm_error(info_tag, + $sformatf("mret to umode does not clear mintthresh")); + + + // this assert verifies that mode is correctly restored on an mret + property p_mret_mode_mpp; + logic [1:0] prev_mpp = '0; + (rvfi_if.is_mret, + prev_mpp = rvfi_mcause_fields.mpp) + ##1 rvfi_valid[->1] + ##0 !(rvfi_if.rvfi_intr.intr || support_if.first_debug_ins) + |-> + rvfi_if.rvfi_mode == prev_mpp; + endproperty : p_mret_mode_mpp + + a_mret_mode_mpp: assert property (p_mret_mode_mpp) + else + `uvm_error(info_tag, + $sformatf("mret does not update mode according to mpp")); + + // this assert verifies that mil is correctly restored on an mret + property p_mret_mil_mpil; + logic [7:0] prev_rvfi_mcause_mpil; + (rvfi_if.is_mret, + prev_rvfi_mcause_mpil = rvfi_mcause_fields.mpil) + ##1 rvfi_valid[->1] + ##0 !(rvfi_if.rvfi_intr.intr || support_if.first_debug_ins) + |-> + rvfi_mintstatus_fields.mil == prev_rvfi_mcause_mpil; + endproperty : p_mret_mil_mpil + + a_mret_mil_mpil: assert property (p_mret_mil_mpil) + else + `uvm_error(info_tag, + $sformatf("mret does not update mil according to mpil")); + + // this assert verifies that mil is correctly restored on an mret + property p_mret_mil_mpil_intended; + rvfi_if.is_mret + && !rvfi_if.rvfi_trap.trap + |-> + rvfi_mintstatus_wdata_fields.mil == rvfi_mcause_fields.mpil; + endproperty : p_mret_mil_mpil_intended + + a_mret_mil_mpil_intended: assert property (p_mret_mil_mpil_intended) + else + `uvm_error(info_tag, + $sformatf("mret does not update mil according to mpil")); + + + + // this assert verifies that mie is correctly restored on an mret + property p_mret_mie_mpie; + logic prev_rvfi_mcause_mpie; + (rvfi_if.is_mret, + prev_rvfi_mcause_mpie = rvfi_mcause_fields.mpie) + ##1 rvfi_valid[->1] + ##0 !(rvfi_if.rvfi_intr.intr || support_if.first_debug_ins) + |-> + rvfi_mstatus_fields.mie == prev_rvfi_mcause_mpie + ; + endproperty : p_mret_mie_mpie + + a_mret_mie_mpie: assert property (p_mret_mie_mpie) + else + `uvm_error(info_tag, + $sformatf("mret does not update mie according to mpie")); + + // this assert verifies that mie is correctly restored on an mret + property p_mret_mie_mpie_intended; + rvfi_if.is_mret + && !rvfi_if.rvfi_trap.trap + |-> + rvfi_mstatus_wdata_fields.mie == rvfi_mcause_fields.mpie; + endproperty : p_mret_mie_mpie_intended + + a_mret_mie_mpie_intended: assert property (p_mret_mie_mpie_intended) + else + `uvm_error(info_tag, + $sformatf("mret does not update mie according to mpie")); + + // this assert verifies that mpie is correctly set on an mret + a_mret_mpie_intended: assert property ( + rvfi_if.is_mret + && !rvfi_if.rvfi_trap.trap + |-> + rvfi_mstatus_wdata_fields.mpie + ) + else + `uvm_error(info_tag, + $sformatf("mret does not set mpie")); + + // this assert verifies that mpil is unchanged on an mret + a_mret_mpil_intended: assert property ( + rvfi_if.is_mret + && !rvfi_if.rvfi_trap.trap + |-> + rvfi_mcause_wmask_fields.mpil == '0 + or + (rvfi_mcause_fields.mpil == rvfi_mcause_wdata_fields.mpil) + ) + else + `uvm_error(info_tag, + $sformatf("mret does change mpil")); + + + // ------------------------------------------------------------------------ + // clic level should be the larger of mintthresh_th and prev. taken irq + // ------------------------------------------------------------------------ + + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mintstatus_mil_q <= 0; + prev_was_valid_mnxti_write <= 0; + prev_was_mret <= 0; + intended_mode_u <= 0; + prev_was_trapped_u <= 0; + expected_mpil <= 0; + end else begin + if (rvfi_valid) begin + mintstatus_mil_q <= rvfi_mintstatus_fields.mil; + prev_was_valid_mnxti_write <= is_valid_mnxti_write; + prev_was_mret <= rvfi_if.is_mret; + intended_mode_u <= !rvfi_if.rvfi_trap.trap && ( + (rvfi_if.is_mret && rvfi_mcause_fields.mpp == U_MODE) || + (rvfi_if.is_dret && rvfi_dcsr_fields.prv == U_MODE) || + rvfi_if.rvfi_mode == U_MODE); + prev_was_trapped_u <= rvfi_if.rvfi_trap.trap && intended_mode_u; + expected_mpil <= rvfi_mcause_wmask_fields.mpil ? (rvfi_mcause_wdata_fields.mpil & rvfi_mcause_wmask_fields.mpil) : rvfi_mcause_fields.mpil; + end + end + end + + a_mintstatus_mil_decrease_intended: assert property( + rvfi_valid && + csr_mintstatus_if.rvfi_csr_wmask && + rvfi_mintstatus_wdata_fields.mil < rvfi_mintstatus_fields.mil + |-> + rvfi_if.is_mret + or + is_valid_mnxti_write && + rvfi_mintstatus_wdata_fields.mil > max_level(rvfi_mintthresh_fields.th, rvfi_mcause_fields.mpil) + or + rvfi_if.rvfi_mode == U_MODE && + rvfi_if.rvfi_trap.exception && + rvfi_mintstatus_wdata_fields.mil == 0 + ) + else + `uvm_error(info_tag, + $sformatf("minstatus.mil decreased wihout mret")); + + a_mintstatus_mil_decreased: assert property( + rvfi_valid && + rvfi_mintstatus_fields.mil < mintstatus_mil_q + |-> + prev_was_mret + or + prev_was_valid_mnxti_write && + rvfi_mintstatus_fields.mil > max_level(rvfi_mintthresh_fields.th, expected_mpil) + or + rvfi_if.rvfi_intr.intr && + (intended_mode_u || prev_was_trapped_u) + ) + else + `uvm_error(info_tag, + $sformatf("minstatus.mil decreased wihout mret")); + + a_mintstatus_mil_increase_intended: assert property( + rvfi_valid && + csr_mintstatus_if.rvfi_csr_wmask && + rvfi_mintstatus_wdata_fields.mil > rvfi_mintstatus_fields.mil + |-> + is_valid_mnxti_write + or + rvfi_if.is_mret + ) + else + `uvm_error(info_tag, + $sformatf("minstatus.mil written illegally")); + + a_mintstatus_mil_increase_intended_th: assert property( + rvfi_valid && + csr_mintstatus_if.rvfi_csr_wmask && // mil is changed + rvfi_mintstatus_fields.mil > 0 && // in an interrupt handler + rvfi_mintstatus_wdata_fields.mil > rvfi_mintstatus_fields.mil + |-> + is_valid_mnxti_write && rvfi_mintstatus_wdata_fields.mil >= rvfi_mintthresh_fields.th + or + rvfi_if.is_mret + ) + else + `uvm_error(info_tag, + $sformatf("minstatus.mil written illegally")); + + a_mintstatus_mil_increased: assert property( + rvfi_valid && + rvfi_mintstatus_fields.mil > mintstatus_mil_q + |-> + prev_was_valid_mnxti_write + or + rvfi_if.rvfi_intr.intr + or + prev_was_mret + ) + else + `uvm_error(info_tag, + $sformatf("minstatus.mil written illegally")); + + + + a_mintstatus_mil_increased_th: assert property( + rvfi_valid && + rvfi_mintstatus_fields.mil > mintstatus_mil_q && + mintstatus_mil_q > 0 + + |-> + prev_was_valid_mnxti_write && rvfi_mintstatus_fields.mil >= rvfi_mintthresh_fields.th + or + rvfi_if.rvfi_intr.intr && ((rvfi_mintstatus_fields.mil >= rvfi_mintthresh_fields.th) || intended_mode_u) + or + prev_was_mret + ) + else + `uvm_error(info_tag, + $sformatf("minstatus.mil written illegally")); + + + // ------------------------------------------------------------------------ + // Horizontal exception handling + // ------------------------------------------------------------------------ + + property p_horizontal_exception_service; + rvfi_mode == M_MODE + && rvfi_valid + && rvfi_trap.exception + |-> + ##0 $stable(current_priv_mode, @(posedge clk_i)) + && $stable(mintstatus_fields.mil, @(posedge clk_i)) + until_with rvfi_valid[->1]; + endproperty : p_horizontal_exception_service + + property p_stable_mode_lvl; + $stable(current_priv_mode) && $stable(mintstatus_fields.mil); + endproperty : p_stable_mode_lvl + + a_horizontal_exception_service: assert property (p_horizontal_exception_service) + else + `uvm_error(info_tag, + $sformatf("Horizontal exception service not handled correctly")); + + // ------------------------------------------------------------------------ + // Vertical exception handling + // ------------------------------------------------------------------------ + + property p_vertical_exception_service; + rvfi_valid + && rvfi_trap.exception + && rvfi_mode == U_MODE + ##1 rvfi_valid[->1] + |-> + // regular case + ##0 mintstatus_fields.mil == 0 + && rvfi_mode == M_MODE + or + // mnxti overwriting expected mil, checked in mnxti assertions + ##0 is_mnxti_access_instr + && rvfi_mode == M_MODE + or + // first handler instruction is mret, should be handled at lvl 0, + // but mpil may cause mil to change after mret retirement + ##0 is_mret_instr + && rvfi_mode == M_MODE + && $past(mintstatus_fields.mil) == 0 + && mintstatus_fields.mil == $past(mcause_fields.mpil) + ; + endproperty : p_vertical_exception_service + + a_vertical_exception_service: assert property (p_vertical_exception_service) + else + `uvm_error(info_tag, + $sformatf("Vertical exception service not handled correctly")); + + // ------------------------------------------------------------------------ + // MEPC lsb should always be 0 + // ------------------------------------------------------------------------ + property p_mepc_lsb_always_zero; + mepc_fields.reserved == 1'b0; + endproperty : p_mepc_lsb_always_zero; + + a_mepc_lsb_always_zero: assert property (p_mepc_lsb_always_zero) + else + `uvm_error(info_tag, + $sformatf("mepc[0] should always be zero")); + + // ------------------------------------------------------------------------ + // Checks correct behavior of accesses to mscratchcsw + // ------------------------------------------------------------------------ + property p_mscratchcsw_value; + is_mscratchcsw_access_instr + |-> + rvfi_rd_wdata == (csr_instr.rd != X0 ? rvfi_mscratch_rdata : 'b0) + && rvfi_mscratch_wdata == rvfi_rs1_rdata + && mstatus_fields.mpp != rvfi_mode + && csr_instr.funct3 == CSRRW + && csr_instr.rd != X0 + && csr_instr.n.rs1 != X0 + or + rvfi_rd_wdata == rvfi_rs1_rdata + && rvfi_mscratch_wmask == 'h0 + && mstatus_fields.mpp == rvfi_mode + && csr_instr.funct3 == CSRRW + && csr_instr.rd != X0 + && csr_instr.n.rs1 != X0 + or + rvfi_trap.exception + or + rvfi_trap.debug + ; + endproperty : p_mscratchcsw_value + + a_mscratchcsw_value: assert property (p_mscratchcsw_value) + else + `uvm_error(info_tag, + $sformatf("mscratchcsw value not as expected")); + + // ------------------------------------------------------------------------ + // Checks correct behavior of accesses to mscratchcswl + // ------------------------------------------------------------------------ + property p_mscratchcswl_value; + is_mscratchcswl_access_instr + |-> + rvfi_rd_wdata == (csr_instr.rd != X0 ? rvfi_mscratch_rdata : 'b0) + && rvfi_mscratch_wdata == rvfi_rs1_rdata + && |mcause_fields.mpil ^ |mintstatus_fields.mil + && csr_instr.funct3 == CSRRW + && csr_instr.rd != X0 + && csr_instr.n.rs1 != X0 + or + rvfi_rd_wdata == rvfi_rs1_rdata + && rvfi_mscratch_wmask == 'h0 + && |mcause_fields.mpil ^~ |mintstatus_fields.mil + && csr_instr.funct3 == CSRRW + && csr_instr.rd != X0 + && csr_instr.n.rs1 != X0 + or + rvfi_trap.exception + or + rvfi_trap.debug + ; + endproperty : p_mscratchcswl_value + + a_mscratchcswl_value: assert property (p_mscratchcswl_value) + else + `uvm_error(info_tag, + $sformatf("mscratchcswl value not as expected")); + + // ------------------------------------------------------------------------ + // Formal verification constraints + // Gated due to some simulators not ignoring restrict keyword + // ------------------------------------------------------------------------ + + `ifdef FORMAL + // Stability assumes + r_fetch_enable_stable: restrict property (fetch_enable |-> $stable(mtvec_addr_i)); + r_clic_mode_assume: restrict property (p_clic_mode_only); + r_irq_i: restrict property (irq_i == 0); + + // prevents undefined latch value out of reset in formal + r_irq_ack_occurred_zero_out_of_of_reset: restrict property (p_irq_ack_occurred_zero_out_of_reset); + + // Sanity cover for mtvt table helper logic + c_mtvt_table_read_equals_value_written: cover property (p_mtvt_table_read_equals_value_written); + r_mtvt_table_read_equals_value_written: restrict property (p_mtvt_table_read_equals_value_written); + + //`define CLIC_DELAY_RESTRICTIONS + `ifdef CLIC_DELAY_RESTRICTIONS // TODO: (silabs-hfegran) temporary fix, implement with tcl script later + // These attempts to restrict the amount of bus-induced delays during formal analysis to help reach + // a bounded proof, as in theory infinte bus stalls are possible. + // Limit data and instr stalls for formal convergence, consider removing when assertion set matures + r_instr_load_stalls: restrict property (p_obi_instr_max_load_stalls); + r_instr_max_gnt_stalls: restrict property (p_obi_instr_max_gnt_stalls); + r_data_load_stalls: restrict property (p_obi_data_max_load_stalls); + r_data_max_gnt_stalls: restrict property (p_obi_data_max_gnt_stalls); + `endif + + `endif + + end + + endgenerate +endmodule : uvmt_cv32e40s_clic_interrupt_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_constants.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_constants.sv index 349621996d..9c3c810a3a 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_constants.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_constants.sv @@ -18,162 +18,4 @@ `ifndef __UVMT_CV32E40S_CONSTANTS_SV__ `define __UVMT_CV32E40S_CONSTANTS_SV__ - `ifdef ZBA_ZBB_ZBS - parameter cv32e40s_pkg::b_ext_e B_EXT = cv32e40s_pkg::ZBA_ZBB_ZBS; - `elsif ZBA_ZBB_ZBC_ZBS - parameter cv32e40s_pkg::b_ext_e B_EXT = cv32e40s_pkg::ZBA_ZBB_ZBC_ZBS; - `else - parameter cv32e40s_pkg::b_ext_e B_EXT = cv32e40s_pkg::B_NONE; - `endif - - `ifdef PMP_ENABLE_2 - parameter int CORE_PARAM_PMP_NUM_REGIONS = 2; - `else - parameter int CORE_PARAM_PMP_NUM_REGIONS = 0; - `endif - - `ifdef PMA_CUSTOM_CFG - const string pma_cfg_name = "pma_custom_cfg"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 3; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - // Overlap "shadow" of main code (.text), for testing overlap priority - cv32e40s_pkg::pma_region_t'{ - word_addr_low : '0, - word_addr_high : ('h 1a11_0800 + 'd 16) >> 2, // should be identical to the prioritized region below - main : 0, // Would stop all execution, but should be overruled - bufferable : 0, - cacheable : 0}, - // Main code (.text) is executable up til into dbg region - cv32e40s_pkg::pma_region_t'{ - word_addr_low : '0, - word_addr_high : ('h 1a11_0800 + 'd 16) >> 2, // "dbg" address plus arbitrary offset to have a known usable area - main : 1, - bufferable : 1, - cacheable : 1}, - // Second portion of dbg up til end is exec - cv32e40s_pkg::pma_region_t'{ - word_addr_low : 'h 1A11_1000 >> 2, // after ".debugger" - word_addr_high : 'h FFFF_FFFF, - main : 1, - bufferable : 0, - cacheable : 0} - }; - `elsif PMA_DEBUG_CFG - const string pma_cfg_name = "pma_debug_cfg"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 2; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - // Everything is initially executable - cv32e40s_pkg::pma_region_t'{ - word_addr_low : '0, - word_addr_high : 'h FFFF_FFFF, - main : 1, - bufferable : 0, - cacheable : 0}, - // A small region below "dbg" is forbidden to facilitate pma exception testing - cv32e40s_pkg::pma_region_t'{ - word_addr_low : ('h 1a11_0800 - 'd 16) >> 2, - word_addr_high : 'h 1a11_0800 >> 2, - main : 0, - bufferable : 0, - cacheable : 0} - }; - `elsif PMA_TEST_CFG_1 - const string pma_cfg_name = "pma_test_cfg_1"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 1; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[0:CORE_PARAM_PMA_NUM_REGIONS-1] = '{ - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h7FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1} - }; - - `elsif PMA_TEST_CFG_2 - const string pma_cfg_name = "pma_test_cfg_2"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 7; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'hE010_0000>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'hE000_0000>>2, word_addr_high : 32'hE00F_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'hA000_0000>>2, word_addr_high : 32'hDFFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h6000_0000>>2, word_addr_high : 32'h9FFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h4000_0000>>2, word_addr_high : 32'h5FFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h2000_0000>>2, word_addr_high : 32'h3FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h1FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1} - }; - `elsif PMA_TEST_CFG_3 - const string pma_cfg_name = "pma_test_cfg_3"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'h0000_A000>>2, word_addr_high : 32'hFFFE_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1}, - '{word_addr_low : 32'h0200_0000>>2, word_addr_high : 32'hEFFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0500_0000>>2, word_addr_high : 32'h8459_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h1000_00F1>>2, word_addr_high : 32'h82FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h13AC_AA55>>2, word_addr_high : 32'h7FFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h2000_0000>>2, word_addr_high : 32'h63FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h2340_000A>>2, word_addr_high : 32'h600F_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h2A00_0000>>2, word_addr_high : 32'h56FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1}, - '{word_addr_low : 32'h2C5A_3200>>2, word_addr_high : 32'h52FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h3000_1353>>2, word_addr_high : 32'h5140_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h3100_FCAB>>2, word_addr_high : 32'h5000_BCCA>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h3420_C854>>2, word_addr_high : 32'h5000_ABFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h3600_A000>>2, word_addr_high : 32'h4F99_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1}, - '{word_addr_low : 32'h3ACE_0000>>2, word_addr_high : 32'h4ABC_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h4400_0000>>2, word_addr_high : 32'h4BFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h4800_0000>>2, word_addr_high : 32'h49FF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1} - }; - `elsif PMA_TEST_CFG_4 - const string pma_cfg_name = "pma_test_cfg_4"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'hE700_EF00>>2, word_addr_high : 32'hE9FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'hC000_0000>>2, word_addr_high : 32'hDFFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'hBC00_0000>>2, word_addr_high : 32'hBCFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'hA000_0000>>2, word_addr_high : 32'hAFFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h6300_0000>>2, word_addr_high : 32'h6700_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h5400_0000>>2, word_addr_high : 32'h5FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1}, - '{word_addr_low : 32'h5100_0000>>2, word_addr_high : 32'h52FF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h4D00_5555>>2, word_addr_high : 32'h4FFF_ABCD>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h4AAA_F000>>2, word_addr_high : 32'h4C00_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h3440_0000>>2, word_addr_high : 32'h3800_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h3100_A000>>2, word_addr_high : 32'h32FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1}, - '{word_addr_low : 32'h2020_0010>>2, word_addr_high : 32'h2FFF_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h1800_1234>>2, word_addr_high : 32'h18FF_AB21>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h1000_0000>>2, word_addr_high : 32'h1001_0000>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0}, - '{word_addr_low : 32'h0030_0000>>2, word_addr_high : 32'h04FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1}, - '{word_addr_low : 32'h0001_0000>>2, word_addr_high : 32'h001F_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0} - }; - `elsif PMA_TEST_CFG_5 - const string pma_cfg_name = "pma_test_cfg_5"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1}, - '{word_addr_low : 32'h1249_2492>>2, word_addr_high : 32'h1249_2492>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'hDB6D_B6DB>>2, word_addr_high : 32'hDB6D_B6DB>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h9249_2492>>2, word_addr_high : 32'h9249_2492>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'hFFFF_FFFF>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'hE38E_E38E>>2, word_addr_high : 32'hE38E_E38E>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'hCCCC_CCCC>>2, word_addr_high : 32'hCCCC_CCCC>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'hAAAA_AAAA>>2, word_addr_high : 32'hAAAA_AAAA>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h5555_5555>>2, word_addr_high : 32'h5555_5555>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0} - }; - `elsif PMA_TEST_CFG_X1 // Used for memory layout generator debug - const string pma_cfg_name = "pma_test_cfg_x1"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 5; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'h00000000>>2, word_addr_high : 32'h20000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h30000000>>2, word_addr_high : 32'h40000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h50000000>>2, word_addr_high : 32'h60000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h70000000>>2, word_addr_high : 32'h80000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1}, - '{word_addr_low : 32'h00000000>>2, word_addr_high : 32'hF0000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1} - }; - `else - const string pma_cfg_name = "pma_noregion"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 0; - parameter cv32e40s_pkg::pma_region_t CORE_PARAM_PMA_CFG[-1:0] = '{default:cv32e40s_pkg::PMA_R_DEFAULT}; - `endif - - `endif // __UVMT_CV32E40S_CONSTANTS_SV__ diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv index 4e73e009ea..23d359ff91 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv @@ -17,41 +17,81 @@ module uvmt_cv32e40s_debug_assert import uvm_pkg::*; + import uvma_rvfi_pkg::*; import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; ( - uvmt_cv32e40s_debug_cov_assert_if cov_assert_if + uvma_rvfi_instr_if_t rvfi, + uvma_rvfi_csr_if_t csr_dcsr, + uvma_rvfi_csr_if_t csr_dpc, + uvma_rvfi_csr_if_t csr_dscratch0, + uvma_rvfi_csr_if_t csr_dscratch1, + uvma_rvfi_csr_if_t csr_mcause, + uvma_rvfi_csr_if_t csr_mepc, + uvma_rvfi_csr_if_t csr_mstatus, + uvma_rvfi_csr_if_t csr_mtvec, + //TODO:MT tdatas should not be necessary when trigger logic is ready + uvma_rvfi_csr_if_t csr_tdata1, + uvma_rvfi_csr_if_t csr_tdata2, + uvma_obi_memory_if_t instr_obi, + uvma_obi_memory_if_t data_obi, + uvmt_cv32e40s_debug_cov_assert_if_t cov_assert_if, + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if ); // --------------------------------------------------------------------------- // Local parameters // --------------------------------------------------------------------------- - localparam WFI_INSTR_MASK = 32'h ffff_ffff; + localparam WFI_INSTR_MASK = 32'h ffff_ffff; localparam WFI_INSTR_OPCODE = 32'h 1050_0073; localparam EBREAK_INSTR_OPCODE = 32'h 0010_0073; localparam CEBREAK_INSTR_OPCODE = 32'h 0000_9002; localparam DRET_INSTR_OPCODE = 32'h 7B20_0073; + localparam int MSTATUS_TW_POS = 21; + localparam int MCAUSE_MINHV_POS = 30; + localparam int DCSR_STEP_POS = 2; + localparam int DCSR_NMIP_POS = 3; + localparam int DCSR_STEPIE_POS = 11; + localparam int DCSR_EBREAKM_POS = 15; + localparam int DCSR_EBREAKU_POS = 12; + + localparam CSR_ADDR_DCSR = 12'h7B0; + localparam CSR_ADDR_DPC = 12'h7B1; + localparam CSR_ADDR_DSCRATCH0 = 12'h7B2; + localparam CSR_ADDR_DSCRATCH1 = 12'h7B3; + localparam CSR_ADDR_MCAUSE = 12'h342; // --------------------------------------------------------------------------- // Local variables // --------------------------------------------------------------------------- - string info_tag = "CV32E40S_DEBUG_ASSERT"; - logic [31:0] pc_at_dbg_req; // Capture PC when debug_req_i or ebreak is active - logic [31:0] pc_at_ebreak; // Capture PC when ebreak - logic [31:0] halt_addr_at_entry; - logic halt_addr_at_entry_flag; - logic [31:0] exception_addr_at_entry; - logic exception_addr_at_entry_flag; - logic [31:0] tdata2_at_entry; + string info_tag = "CV32E40S_DEBUG_ASSERT"; + logic [31:0] pc_at_dbg_req; // Capture PC when debug_req_i or ebreak is active + logic [31:0] dpc_dbg_ebreak; + logic [31:0] dpc_dbg_trg; + logic [31:0] dpc_dbg_step; + logic [31:0] dpc_dbg_step_notrap; + logic [31:0] dpc_dbg_step_irq; + logic [31:0] dpc_dbg_step_nmi; + logic [31:0] dpc_dbg_haltreq; + logic [31:0] dpc_dbg_haltreq_notrap; + logic [31:0] dpc_dbg_haltreq_irq; + logic [31:0] dpc_dbg_haltreq_nmi; + logic [31:0] halt_addr; + logic [31:0] exception_addr_at_entry; + logic exception_addr_at_entry_flag; // Locally track which debug cause should be used - logic [2:0] debug_cause_pri; - logic [31:0] boot_addr_at_entry; - logic [31:0] mtvec_addr; - logic is_trigger_match; + logic [2:0] debug_cause_pri; + logic [31:0] boot_addr; + logic [31:0] mtvec_addr; + + logic ebreak_allowed; + + int stable_req_vs_valid_cnt; + + logic [31:0] dpc_rdata_q; + logic [31:0] dcsr_rdata_q; + logic [31:0] debug_pc_o_q; - // Locally track pc in ID stage to detect first instruction of debug code - logic first_debug_ins_flag; - logic first_debug_ins; - logic started_decoding_in_debug; // --------------------------------------------------------------------------- // Clocking blocks @@ -61,6 +101,7 @@ module uvmt_cv32e40s_debug_assert default clocking @(posedge cov_assert_if.clk_i); endclocking default disable iff !(cov_assert_if.rst_ni); + assign cov_assert_if.is_ebreak = cov_assert_if.wb_valid && (cov_assert_if.wb_stage_instr_rdata_i == EBREAK_INSTR_OPCODE) @@ -79,9 +120,7 @@ module uvmt_cv32e40s_debug_assert && (cov_assert_if.wb_stage_instr_rdata_i[14:12] == 3'b010) && (cov_assert_if.wb_stage_instr_rdata_i[6:0] == 7'h33); - assign is_trigger_match = cov_assert_if.trigger_match_in_wb && cov_assert_if.wb_valid; - - assign mtvec_addr = {cov_assert_if.mtvec[31:2], 2'b00}; + assign mtvec_addr = {csr_mtvec.rvfi_csr_rdata[31:2], 2'b00}; // --------------------------------------- // Assertions @@ -104,10 +143,10 @@ module uvmt_cv32e40s_debug_assert // Check that we enter debug mode when expected. CSR checks are done in other assertions property p_enter_debug; - $changed(debug_cause_pri) && (debug_cause_pri != 0) && !cov_assert_if.debug_mode_q + $changed(debug_cause_pri) && (debug_cause_pri != 0) && !rvfi.rvfi_dbg_mode + ##1 rvfi.rvfi_valid[->1] |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q; + support_if.first_debug_ins; endproperty a_enter_debug: assert property(p_enter_debug) @@ -115,137 +154,236 @@ module uvmt_cv32e40s_debug_assert // Check that dpc gets the correct value when debug mode is entered. - a_debug_mode_pc: assert property( - $rose(first_debug_ins) + $rose(support_if.first_debug_ins) |-> - cov_assert_if.wb_stage_pc == halt_addr_at_entry - ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong pc. pc==%08x", cov_assert_if.wb_stage_pc)); + rvfi.rvfi_pc_rdata == halt_addr + ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong pc. pc==%08x", rvfi.rvfi_pc_rdata)); + + + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_debug_mode_pc_dpc: assert property( + $rose(support_if.first_debug_ins) + |-> + (rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt + ##1 + dpc_rdata_q == pc_at_dbg_req) + or + (csr_dpc.rvfi_csr_rdata == pc_at_dbg_req) + ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong dpc. dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate - a_debug_mode_pc_dpc: assert property( - $rose(first_debug_ins) + // Breaking down the above assert in to debug causes, to improve runtime + property p_dpc_dbg_ebreak; + $rose(support_if.first_debug_ins) && rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_EBREAK |-> - cov_assert_if.depc_q == pc_at_dbg_req - ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong dpc. dpc==%08x", cov_assert_if.depc_q)); + csr_dpc.rvfi_csr_rdata == dpc_dbg_ebreak; + endproperty + + a_dpc_dbg_ebreak: assert property(p_dpc_dbg_ebreak) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on an ebreak, dpc==%08x", csr_dpc.rvfi_csr_rdata)); - a_debug_mode_pc_dmode: assert property( - $rose(first_debug_ins) + property p_dpc_dbg_trigger; + $rose(support_if.first_debug_ins) && rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_TRIGGER |-> - cov_assert_if.debug_mode_q - ) else `uvm_error(info_tag, "First debug mode instruction predicted wrongly"); + csr_dpc.rvfi_csr_rdata == dpc_dbg_trg; + endproperty + a_dpc_dbg_trigger: assert property(p_dpc_dbg_trigger) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a trigger, dpc==%08x", csr_dpc.rvfi_csr_rdata)); - // Check that dcsr.cause is as expected + //TODO:MT Fully covered by those below, remove? + property p_dpc_dbg_step; + $rose(support_if.first_debug_ins) && + rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP + |-> + (csr_dpc.rvfi_csr_rdata == dpc_dbg_step) + or + (rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt + ##1 dpc_rdata_q == dpc_dbg_step); + endproperty - property p_dcsr_cause; - $rose(first_debug_ins) + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_dpc_dbg_step: assert property(p_dpc_dbg_step) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a step, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate + + + property p_dpc_dbg_step_notrap; + $rose(support_if.first_debug_ins) && + !rvfi.rvfi_intr.intr && + rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP |-> - (cov_assert_if.dcsr_q[8:6] == debug_cause_pri); + (csr_dpc.rvfi_csr_rdata == dpc_dbg_step_notrap); endproperty - a_dcsr_cause: assert property(p_dcsr_cause) - else `uvm_error(info_tag, "dcsr.cause was not as expected"); + a_dpc_dbg_step_notrap: assert property(p_dpc_dbg_step_notrap) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a step, dpc==%08x", csr_dpc.rvfi_csr_rdata)); - // Check that debug with cause haltreq is correct - property p_debug_mode_ext_req; - $rose(cov_assert_if.debug_mode_q) && (cov_assert_if.dcsr_q[8:6] == cv32e40s_pkg::DBG_CAUSE_HALTREQ) - |-> debug_cause_pri == cv32e40s_pkg::DBG_CAUSE_HALTREQ; + property p_dpc_dbg_step_nmi; + $rose(support_if.first_debug_ins) && + rvfi.is_nmi && + (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP) + |=> + dpc_rdata_q == dpc_dbg_step_nmi; endproperty - a_debug_mode_ext_req: assert property(p_debug_mode_ext_req) - else `uvm_error(info_tag, $sformatf("Debug cause not correct for haltreq, cause = %d",cov_assert_if.dcsr_q[8:6])); + a_dpc_dbg_step_nmi: assert property(p_dpc_dbg_step_nmi) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a step, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + - // Check that debug with cause ebreak is correct - property p_cebreak_debug_mode; - $rose(cov_assert_if.debug_mode_q) && (cov_assert_if.dcsr_q[8:6] == cv32e40s_pkg::DBG_CAUSE_EBREAK) - |-> debug_cause_pri == cv32e40s_pkg::DBG_CAUSE_EBREAK; + property p_dpc_dbg_step_irq; + $rose(support_if.first_debug_ins) && + rvfi.rvfi_intr.intr && + rvfi.rvfi_intr.interrupt && + !rvfi.is_nmi && + (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP) + |=> + dpc_rdata_q == dpc_dbg_step_irq; endproperty - a_cebreak_debug_mode: assert property(p_cebreak_debug_mode) - else `uvm_error(info_tag,$sformatf("Debug mode with wrong cause after ebreak, case = %d",cov_assert_if.dcsr_q[8:6])); + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_dpc_dbg_step_irq: assert property(p_dpc_dbg_step_irq) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a step, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate + //TODO:MT Fully covered by those below, remove? + property p_dpc_dbg_haltreq; + $rose(support_if.first_debug_ins) && + (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ) + |-> + (csr_dpc.rvfi_csr_rdata == dpc_dbg_haltreq) + or + (rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt + ##1 dpc_rdata_q == dpc_dbg_haltreq); + endproperty - // ebreak / c.ebreak without dcsr.ebreakm results in exception at mtvec - // (Exclude single stepping as the sequence gets very complicated) + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_dpc_dbg_haltreq: assert property(p_dpc_dbg_haltreq) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a haltreq, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate - property p_general_ebreak_exception(ebreak); - $rose(ebreak) - && !cov_assert_if.debug_mode_q - && !cov_assert_if.dcsr_q[2] - && !cov_assert_if.dcsr_q[15] - ##0 ( - (!cov_assert_if.pending_debug && !cov_assert_if.irq_ack_o && !cov_assert_if.pending_nmi) - throughout (##1 cov_assert_if.wb_valid [->1]) - ) + property p_dpc_dbg_haltreq_notrap; + $rose(support_if.first_debug_ins) && + !rvfi.rvfi_intr.intr && + rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ |-> - !cov_assert_if.debug_mode_q - && (cov_assert_if.mcause_q[30:0] === cv32e40s_pkg::EXC_CAUSE_BREAKPOINT) - && (cov_assert_if.mepc_q == pc_at_ebreak) - && (cov_assert_if.wb_stage_pc == mtvec_addr); - // TODO:ropeders need assertions for what happens if cebreak and req/irq? + (csr_dpc.rvfi_csr_rdata == dpc_dbg_haltreq_notrap); endproperty - a_cebreak_exception: assert property( - p_general_ebreak_exception(cov_assert_if.is_cebreak) - ) else `uvm_error(info_tag, $sformatf("Exception not entered correctly after c.ebreak with dcsr.ebreak=0")); + a_dpc_dbg_haltreq_notrap: assert property(p_dpc_dbg_haltreq_notrap) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a haltreq, dpc==%08x", csr_dpc.rvfi_csr_rdata)); - a_ebreak_exception: assert property( - p_general_ebreak_exception(cov_assert_if.is_ebreak) - ) else `uvm_error(info_tag, $sformatf("Exception not entered correctly after ebreak with dcsr.ebreak=0")); + property p_dpc_dbg_haltreq_nmi; + $rose(support_if.first_debug_ins) && + rvfi.is_nmi && + (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ) + |=> + dpc_rdata_q == dpc_dbg_haltreq_nmi; + endproperty + + a_dpc_dbg_haltreq_nmi: assert property(p_dpc_dbg_haltreq_nmi) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a haltreq, dpc==%08x", csr_dpc.rvfi_csr_rdata)); - // c.ebreak during debug mode results in relaunch of debug mode - property p_cebreak_during_debug_mode; - $rose(cov_assert_if.is_cebreak) && cov_assert_if.debug_mode_q + property p_dpc_dbg_haltreq_irq; + $rose(support_if.first_debug_ins) && + rvfi.rvfi_intr.intr && + rvfi.rvfi_intr.interrupt && + !rvfi.is_nmi && + (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ) + |=> + dpc_rdata_q == dpc_dbg_haltreq_irq; + endproperty + + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_dpc_dbg_haltreq_irq: assert property(p_dpc_dbg_haltreq_irq) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a haltreq, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate + + // Check that dcsr.cause is as expected + property p_dcsr_cause; + $rose(support_if.first_debug_ins) |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.wb_stage_pc == halt_addr_at_entry); - // TODO should check no change in dpc and dcsr + (rvfi.rvfi_dbg == debug_cause_pri) + or + (support_if.recorded_dbg_req && (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ)); endproperty - a_cebreak_during_debug_mode: assert property(p_cebreak_during_debug_mode) - else `uvm_error(info_tag,$sformatf("Debug mode not restarted after c.ebreak")); + a_dcsr_cause: assert property(p_dcsr_cause) + else `uvm_error(info_tag, "dcsr.cause was not as expected"); - // ebreak during debug mode results in relaunch - property p_ebreak_during_debug_mode; - $rose(cov_assert_if.is_ebreak) && cov_assert_if.debug_mode_q - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.wb_stage_pc == halt_addr_at_entry); - // TODO should check no change in dpc and dcsr + // check that a stable debug_req is actually taken within reasonable time + a_debug_req_taken: assert property(stable_req_vs_valid_cnt <= 3) + else `uvm_error(info_tag, "External debug request not taken in reasonable time"); + + + // ebreak / c.ebreak without dcsr.ebreak[prv] results in exception at mtvec + property p_ebreak_mmode_exception; + rvfi.is_ebreak && + !rvfi.rvfi_dbg_mode && + rvfi.is_mmode && + !csr_dcsr.rvfi_csr_rdata[DCSR_EBREAKM_POS] + |-> rvfi.rvfi_trap.trap && rvfi.rvfi_trap.exception + or + rvfi.rvfi_trap.trap && rvfi.rvfi_trap.debug && !(rvfi.rvfi_trap.debug_cause == cv32e40s_pkg::DBG_CAUSE_EBREAK); endproperty - a_ebreak_during_debug_mode: assert property(p_ebreak_during_debug_mode) - else `uvm_error(info_tag,$sformatf("Debug mode not restarted after ebreak")); + property p_ebreak_umode_exception; + rvfi.is_ebreak && + !rvfi.rvfi_dbg_mode && + rvfi.is_umode && + !csr_dcsr.rvfi_csr_rdata[DCSR_EBREAKU_POS] + |-> rvfi.rvfi_trap.trap && rvfi.rvfi_trap.exception + or + rvfi.rvfi_trap.trap && rvfi.rvfi_trap.debug && !(rvfi.rvfi_trap.debug_cause == cv32e40s_pkg::DBG_CAUSE_EBREAK); + endproperty + + a_ebreak_mmode_exception: assert property(p_ebreak_mmode_exception) + else `uvm_error(info_tag, $sformatf("Exception not entered correctly after ebreak with dcsr.ebreakm=0 in mmode")); + a_ebreak_umode_exception: assert property(p_ebreak_umode_exception) + else `uvm_error(info_tag, $sformatf("Exception not entered correctly after ebreak with dcsr.ebreaku=0 in umode")); - // Trigger match results in debug mode - property p_trigger_match; - is_trigger_match ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q + // ebreak and cebreak during debug mode results in relaunch + property p_ebreak_during_debug_mode; + rvfi.is_ebreak && + rvfi.rvfi_trap.debug_cause == cv32e40s_pkg::DBG_CAUSE_EBREAK && //The ebreak is actually taken + rvfi.rvfi_dbg_mode + ##1 rvfi.rvfi_valid[->1] |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6] === cv32e40s_pkg::DBG_CAUSE_TRIGGER) - && (cov_assert_if.depc_q == tdata2_at_entry) && (cov_assert_if.wb_stage_pc == halt_addr_at_entry); + rvfi.rvfi_dbg_mode && + ((csr_dcsr.rvfi_csr_rdata | (1 << DCSR_NMIP_POS)) == (dcsr_rdata_q | (1 << DCSR_NMIP_POS))) && + (csr_dpc.rvfi_csr_rdata == dpc_rdata_q) && + (rvfi.rvfi_pc_rdata == halt_addr); endproperty - a_trigger_match: assert property(p_trigger_match) - else `uvm_error(info_tag, - $sformatf("Debug mode not correctly entered after trigger match depc=%08x, tdata2=%08x", - cov_assert_if.depc_q, tdata2_at_entry)); + a_ebreak_during_debug_mode: assert property(p_ebreak_during_debug_mode) + else `uvm_error(info_tag,$sformatf("Debug mode not restarted after ebreak")); - // Address match without trigger enabled should NOT result in debug mode + cov_cebreak_dbg : cover property( + rvfi.is_ebreak_compr && rvfi.rvfi_dbg_mode + ); + cov_ebreak_dbg : cover property( + rvfi.is_ebreak_noncompr && rvfi.rvfi_dbg_mode + ); - property p_trigger_match_disabled; - $rose(cov_assert_if.addr_match) && !cov_assert_if.debug_mode_q |-> ##[1:6] !cov_assert_if.debug_mode_q; - endproperty - a_trigger_match_disabled: assert property(p_trigger_match_disabled) - else `uvm_error(info_tag, "Trigger match with tdata[2]==0 resulted in debug mode"); // Exception in debug mode results in pc->dm_exception_addr_i @@ -286,55 +424,79 @@ module uvmt_cv32e40s_debug_assert `uvm_error(info_tag, $sformatf("IRQ not ignored while in debug mode")); - // WFI in debug mode does not sleep + // WFI/WFE in debug mode does not sleep - property p_wfi_in_debug; - cov_assert_if.debug_mode_q && $rose(cov_assert_if.is_wfi) |-> ##6 !cov_assert_if.core_sleep_o; - // TODO:ropeders should/could the consequent be more specific? + property p_wfi_wfe_in_debug; + cov_assert_if.debug_mode_q |-> !cov_assert_if.core_sleep_o; endproperty - a_wfi_in_debug : assert property(p_wfi_in_debug) - else `uvm_error(info_tag, $sformatf("WFI in debug mode cause core_sleep_o=1")); + a_wfi_wfe_in_debug : assert property(p_wfi_wfe_in_debug) + else `uvm_error(info_tag, $sformatf("WFI or WFE in debug mode cause core_sleep_o=1")); // Debug request while sleeping makes core wake up and enter debug mode with cause=haltreq - property p_sleep_debug_req; - cov_assert_if.in_wfi && cov_assert_if.debug_req_i + property p_sleep_debug_req_wu; + (cov_assert_if.ctrl_fsm_cs == SLEEP) && cov_assert_if.debug_req_i |=> - !cov_assert_if.core_sleep_o - ##0 s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6] == cv32e40s_pkg::DBG_CAUSE_HALTREQ); + !cov_assert_if.core_sleep_o; endproperty - a_sleep_debug_req : assert property(p_sleep_debug_req) + a_sleep_debug_req_wu : assert property(p_sleep_debug_req_wu) else `uvm_error(info_tag, - $sformatf("Did not exit sleep(== %d) after debug_req_i. Debug_mode = %d cause = %d", - cov_assert_if.core_sleep_o, cov_assert_if.debug_mode_q, cov_assert_if.dcsr_q[8:6])); + $sformatf("Did not exit sleep(== %d) after debug_req_i. ", + cov_assert_if.core_sleep_o)); + property p_sleep_debug_req; + (cov_assert_if.ctrl_fsm_cs == SLEEP) && cov_assert_if.debug_req_i + ##0(cov_assert_if.debug_req_i throughout cov_assert_if.debug_halted[->1]) + ##0 rvfi.rvfi_valid[->1] + |-> + rvfi.rvfi_dbg_mode && rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ; + endproperty - // Accessing debug regs in m-mode is illegal + a_sleep_debug_req : assert property(p_sleep_debug_req) + else `uvm_error(info_tag, + $sformatf("Did not enter debug haltreq after debug_req_i during sleep. Debug_mode = %d cause = %d", + rvfi.rvfi_dbg_mode, rvfi.rvfi_dbg)); - property p_debug_regs_mmode; - int tmp; - cov_assert_if.ex_stage_csr_en && cov_assert_if.ex_valid && !cov_assert_if.debug_mode_q - && cov_assert_if.ex_stage_instr_rdata_i[31:20] inside {'h7B0, 'h7B1, 'h7B2, 'h7B3} - ##0 (1, tmp = cov_assert_if.ex_stage_pc) - |=> - (cov_assert_if.wb_stage_pc == tmp) [->1] - ##0 cov_assert_if.illegal_insn_i; + // Accessing debug regs in m-mode is illegal + property p_debug_regs_mumode(csr_addr, csr_wmask); + rvfi.is_csr_instr(csr_addr) && !rvfi.rvfi_dbg_mode + |-> + // instruction traps either as illegal or trigger + rvfi.rvfi_trap.trap && ( + (rvfi.rvfi_trap.exception && (rvfi.rvfi_trap.exception_cause == cv32e40s_pkg::EXC_CAUSE_ILLEGAL_INSN) && (csr_wmask == 0)) + || + (rvfi.rvfi_trap.debug && (rvfi.rvfi_trap.debug_cause == cv32e40s_pkg::DBG_CAUSE_TRIGGER)) + ); endproperty - a_debug_regs_mmode : assert property(p_debug_regs_mmode) - else - `uvm_error(info_tag, "Accessing debug regs in M-mode did not result in illegal instruction"); + a_debug_regs_mumode_dcsr : assert property(p_debug_regs_mumode(CSR_ADDR_DCSR, csr_dcsr.rvfi_csr_wmask)) + else `uvm_error(info_tag, "Accessing debug reg DCSR in M- or U-mode did not result in illegal instruction"); + + a_debug_regs_mumode_dpc : assert property(p_debug_regs_mumode(CSR_ADDR_DPC, csr_dpc.rvfi_csr_wmask)) + else `uvm_error(info_tag, "Accessing debug reg DPC in M- or U-mode did not result in illegal instruction"); + + a_debug_regs_mumode_dscratch0 : assert property(p_debug_regs_mumode(CSR_ADDR_DSCRATCH0, csr_dscratch0.rvfi_csr_wmask)) + else `uvm_error(info_tag, "Accessing debug reg DSCRATCH0 in M- or U-mode did not result in illegal instruction"); + + a_debug_regs_mumode_dscratch1 : assert property(p_debug_regs_mumode(CSR_ADDR_DSCRATCH1, csr_dscratch1.rvfi_csr_wmask)) + else `uvm_error(info_tag, "Accessing debug reg DSCRATCH1 in M- or U-mode did not result in illegal instruction"); // Exception while single step -> PC is set to exception handler before debug property p_single_step_exception; - !cov_assert_if.debug_mode_q && cov_assert_if.dcsr_q[2] - && cov_assert_if.illegal_insn_i && cov_assert_if.wb_valid && !is_trigger_match - |-> ##[1:20] cov_assert_if.debug_mode_q && (cov_assert_if.depc_q == mtvec_addr); + rvfi.rvfi_valid && //valid + !rvfi.rvfi_dbg_mode && //not in dbg + csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] && // step set + !(rvfi.is_dbg_trg) && // not trigger + rvfi.rvfi_trap.exception // exception + ##1 rvfi.rvfi_valid[->1] + |-> + rvfi.rvfi_dbg_mode && + (csr_dpc.rvfi_csr_rdata == mtvec_addr); + endproperty a_single_step_exception : assert property(p_single_step_exception) @@ -343,15 +505,18 @@ module uvmt_cv32e40s_debug_assert // Trigger during single step property p_single_step_trigger; - !cov_assert_if.debug_mode_q && cov_assert_if.dcsr_q[2] - && cov_assert_if.addr_match && cov_assert_if.wb_valid && cov_assert_if.tdata1[2] - |-> ##[1:20] cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6] == cv32e40s_pkg::DBG_CAUSE_TRIGGER) - && (cov_assert_if.depc_q == pc_at_dbg_req); + (rvfi.is_dbg_trg) && + !rvfi.rvfi_dbg_mode && + csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] + ##1 rvfi.rvfi_valid[->1] + |-> + rvfi.rvfi_dbg_mode && ((rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_TRIGGER) || + (support_if.recorded_dbg_req && (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ))); endproperty a_single_step_trigger : assert property (p_single_step_trigger) else `uvm_error(info_tag, - $sformatf("Single step and trigger error: depc = %08x, cause = %d",cov_assert_if.depc_q, cov_assert_if.dcsr_q[8:6])); + $sformatf("Single step and trigger error: dpc = %08x, cause = %d",cov_assert_if.dpc_q, cov_assert_if.dcsr_q[8:6])); // Single step WFI must not result in sleeping @@ -367,111 +532,112 @@ module uvmt_cv32e40s_debug_assert else `uvm_error(info_tag, "Debug mode not entered after single step WFI or core went sleeping"); - // Executing with single step with no irq results in debug mode + // Executing with single step results in debug mode property p_single_step; - !cov_assert_if.debug_mode_q && cov_assert_if.dcsr_q[2] && !cov_assert_if.dcsr_q[11] - && cov_assert_if.wb_stage_instr_valid_i - |=> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q; + rvfi.rvfi_valid && + !rvfi.rvfi_dbg_mode && + csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] + ##1 rvfi.rvfi_valid[->1] + |-> + rvfi.rvfi_dbg_mode; endproperty a_single_step: assert property(p_single_step) else `uvm_error(info_tag, "Debug mode not entered for single step"); - // dret in M-mode will cause illegal instruction - // If pending debug req, illegal insn will not assert until resume - property p_mmode_dret; - !cov_assert_if.debug_mode_q && cov_assert_if.is_dret && !cov_assert_if.pending_debug - |-> cov_assert_if.illegal_insn_i; + property p_mumode_dret; + rvfi.is_dret && !rvfi.rvfi_dbg_mode + |-> rvfi.rvfi_trap; endproperty - a_mmode_dret : assert property(p_mmode_dret) + a_mumode_dret : assert property(p_mumode_dret) else `uvm_error(info_tag, "Executing dret in M-mode did not result in illegal instruction"); // dret in D-mode will restore pc (if no re-entry or interrupt intervenes) property p_dmode_dret_pc; - int dpc; (1, dpc =cov_assert_if.rvfi_csr_dpc_rdata) - ##0(cov_assert_if.rvfi_valid && cov_assert_if.rvfi_dbg_mode && cov_assert_if.rvfi_insn == DRET_INSTR_OPCODE) - - ##1 cov_assert_if.rvfi_valid[->1] - ##0 (!cov_assert_if.rvfi_intr && !cov_assert_if.rvfi_dbg_mode) + int dpc; + (rvfi.is_dret && rvfi.rvfi_dbg_mode, + dpc = csr_dpc.rvfi_csr_rdata) + ##1 + rvfi.rvfi_valid[->1] + ##0 (!rvfi.rvfi_intr && !rvfi.rvfi_dbg_mode) |-> - - cov_assert_if.rvfi_pc_rdata == dpc; + rvfi.rvfi_pc_rdata == dpc; endproperty a_dmode_dret_pc : assert property(p_dmode_dret_pc) else `uvm_error(info_tag, "Dret did not cause correct return from debug mode"); - // dret in D-mode will place dpc in mepc if re-entry is interrupted - /* - //TODO:mateilga reinstate this when the "kill" signal sensitivity in RVFI has been added + // dret in D-mode will place dpc in mepc if re-entry is interrupted (excluding nmi) property p_dmode_dret_pc_int; - int dpc; (1, dpc =cov_assert_if.rvfi_csr_dpc_rdata) - ##0(cov_assert_if.rvfi_valid && cov_assert_if.rvfi_dbg_mode && cov_assert_if.rvfi_insn == DRET_INSTR_OPCODE) - - ##1 cov_assert_if.rvfi_valid[->1] - ##0 (cov_assert_if.rvfi_intr && !cov_assert_if.rvfi_dbg_mode) + int dpc; + (rvfi.is_dret && rvfi.rvfi_dbg_mode, + dpc = csr_dpc.rvfi_csr_rdata) + ##1 + rvfi.rvfi_valid[->1] + ##0 (rvfi.rvfi_intr && !rvfi.rvfi_dbg_mode && !rvfi.is_nmi) |-> - - (cov_assert_if.rvfi_csr_mepc_wdata & cov_assert_if.rvfi_csr_mepc_wmask) == dpc; - + csr_mepc.rvfi_csr_rdata == dpc; endproperty a_dmode_dret_pc_int : assert property(p_dmode_dret_pc_int) else `uvm_error(info_tag, "Dret did not save dpc to mepc when return from debug mode was interrupted"); - */ - // dret in D-mode will exit D-mode + // dret in D-mode can be followed by nmi where "mepc=dpc" - property p_dmode_dret_exit; - cov_assert_if.debug_mode_q && cov_assert_if.is_dret - |=> !cov_assert_if.debug_mode_q; - // TODO:ropeders also assert, stays in mmode until wb_valid if no debug_request + property p_dmode_dret_pc_nmi_eq; + int dpc; + (rvfi.rvfi_valid && rvfi.rvfi_dbg_mode && rvfi.rvfi_insn == DRET_INSTR_OPCODE, + dpc = csr_dpc.rvfi_csr_rdata) + ##1 + rvfi.rvfi_valid[->1] + ##0 (!rvfi.rvfi_dbg_mode && rvfi.is_nmi) + ##0 (csr_mepc.rvfi_csr_rdata == dpc); endproperty - a_dmode_dret_exit : assert property(p_dmode_dret_exit) - else `uvm_error(info_tag, "Dret did not exit debug mode"); + cov_dmode_dret_pc_nmi_eq : cover property(p_dmode_dret_pc_nmi_eq); - // TODO:ropeders what is missing from these dret assertions? + // dret in D-mode can be followed by nmi where "mepc!=dpc" - // Check that trigger regs cannot be written from M-mode - // TSEL, and TDATA3 are tied to zero, hence no register to check - property p_mmode_tdata1_write; - !cov_assert_if.debug_mode_q && cov_assert_if.csr_access && cov_assert_if.csr_op == 'h1 // TODO:ropeders also "set" op? - && cov_assert_if.wb_stage_instr_rdata_i[31:20] == 'h7A1 - |-> - ##0 $stable(cov_assert_if.tdata1) [*4]; + property p_dmode_dret_pc_nmi_neq; + int dpc; + (rvfi.rvfi_valid && rvfi.rvfi_dbg_mode && rvfi.rvfi_insn == DRET_INSTR_OPCODE, + dpc = csr_dpc.rvfi_csr_rdata) + ##1 + rvfi.rvfi_valid[->1] + ##0 (!rvfi.rvfi_dbg_mode && rvfi.is_nmi) + ##0 (csr_mepc.rvfi_csr_rdata != dpc); endproperty - a_mmode_tdata1_write : assert property(p_mmode_tdata1_write) - else `uvm_error(info_tag, "Writing tdata1 from M-mode not allowed to change register value!"); + cov_dmode_dret_pc_nmi_neq : cover property(p_dmode_dret_pc_nmi_neq); - property p_mmode_tdata2_write; - !cov_assert_if.debug_mode_q && cov_assert_if.csr_access && cov_assert_if.csr_op == 'h1 - && cov_assert_if.wb_stage_instr_rdata_i[31:20] == 'h7A2 - |-> - ##0 $stable(cov_assert_if.tdata2) [*4]; + + // dret in D-mode will exit D-mode + + property p_dmode_dret_exit; + cov_assert_if.debug_mode_q && cov_assert_if.is_dret + |=> + !cov_assert_if.debug_mode_q; endproperty - a_mmode_tdata2_write : assert property(p_mmode_tdata2_write) - else `uvm_error(info_tag, "Writing tdata2 from M-mode not allowed to change register value!"); + a_dmode_dret_exit : assert property(p_dmode_dret_exit) + else `uvm_error(info_tag, "Dret did not exit debug mode"); // Check that mcycle works as expected when not sleeping // Counter can be written an arbitrary value, check that // it changed only when not being written to + // Counter should not increment when in debug mode with dcsr.stopcount set property p_mcycle_count; - !cov_assert_if.mcountinhibit_q[0] && !cov_assert_if.core_sleep_o + !cov_assert_if.mcountinhibit_q[0] && !cov_assert_if.core_sleep_o && !((cov_assert_if.debug_mode_q) && cov_assert_if.dcsr_q[10]) && !(cov_assert_if.csr_we_int && (cov_assert_if.csr_addr ==12'hB00 || cov_assert_if.csr_addr == 12'hB80)) |=> $changed(cov_assert_if.mcycle); endproperty @@ -482,9 +648,10 @@ module uvmt_cv32e40s_debug_assert // Check that minstret works as expected when not sleeping // Check only when not written to + // Counter should not increment when in debug mode with dcsr.stopcount set property p_minstret_count; - !cov_assert_if.mcountinhibit_q[2] && cov_assert_if.inst_ret && !cov_assert_if.core_sleep_o + !cov_assert_if.mcountinhibit_q[2] && cov_assert_if.inst_ret && !cov_assert_if.core_sleep_o && !((cov_assert_if.debug_mode_q) && cov_assert_if.dcsr_q[10]) && !(cov_assert_if.csr_we_int && (cov_assert_if.csr_addr == 12'hB02 || cov_assert_if.csr_addr == 12'hB82)) |=> (cov_assert_if.minstret == ($past(cov_assert_if.minstret)+1)); endproperty @@ -493,29 +660,15 @@ module uvmt_cv32e40s_debug_assert else `uvm_error(info_tag, "Minstret not counting when mcountinhibit[2] is cleared!"); - // Check debug_req_i and irq on same cycle. - // Should result in debug mode with regular pc in dpc, not pc from interrupt handler. - // PC is checked in another assertion - property p_debug_req_and_irq; - ((cov_assert_if.debug_req_i || cov_assert_if.debug_req_q) && !cov_assert_if.debug_mode_q) - && (cov_assert_if.pending_enabled_irq != 0) - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q; - // TODO:ropeders should dpc be checked here? - endproperty - - a_debug_req_and_irq : assert property(p_debug_req_and_irq) - else `uvm_error(info_tag, "Debug mode not entered after debug_req_i and irq on same cycle"); - // debug_req at reset should result in debug mode and no instructions executed property p_debug_at_reset; (cov_assert_if.ctrl_fsm_cs == cv32e40s_pkg::RESET) && cov_assert_if.debug_req_i + ##0 (cov_assert_if.debug_req_i throughout !cov_assert_if.debug_havereset[->1]) + ##0 rvfi.rvfi_valid[->1] |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.depc_q == boot_addr_at_entry); + rvfi.rvfi_dbg_mode; endproperty a_debug_at_reset : assert property(p_debug_at_reset) @@ -532,7 +685,7 @@ module uvmt_cv32e40s_debug_assert (cov_assert_if.debug_havereset == 1) && (cov_assert_if.debug_running == 0) && (cov_assert_if.debug_halted == 0) - #=# + ##1 (cov_assert_if.debug_havereset == 0) && (cov_assert_if.debug_running == 1) && (cov_assert_if.debug_halted == 0) @@ -542,19 +695,65 @@ module uvmt_cv32e40s_debug_assert (cov_assert_if.debug_havereset == 1) && (cov_assert_if.debug_running == 0) && (cov_assert_if.debug_halted == 0) - #=# + ##1 (cov_assert_if.debug_havereset == 0) && (cov_assert_if.debug_running == 0) && (cov_assert_if.debug_halted == 1) ); + // step vs nmi + // check that stepie disables nmi + property p_stepie_irq_dis; + rvfi.is_dret && csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] && !csr_dcsr.rvfi_csr_rdata[DCSR_STEPIE_POS] + ##1 rvfi.rvfi_valid[->1] + |-> + !(rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt); + endproperty + + a_stepie_irq_dis : assert property(p_stepie_irq_dis) + else `uvm_error(info_tag, "Single stepping should ignore all interrupts if stepie is set"); + + cov_step_stepie_nmi : cover property ( + rvfi.is_dret + && csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] + && !csr_dcsr.rvfi_csr_rdata[DCSR_STEPIE_POS] + && csr_dcsr.rvfi_csr_rdata[DCSR_NMIP_POS] + ); + + // step trap handler entry, no retire + + // if the next instruction after a single step dret is in debug mode, + // a trap entry has to be the cause. + property p_step_trap_handler_entry; + (rvfi.is_dret && + csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] && + csr_dcsr.rvfi_csr_rdata[DCSR_STEPIE_POS]) + ##1 rvfi.rvfi_valid[->1] + ##0 rvfi.rvfi_dbg_mode && (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP) + |-> + rvfi.rvfi_intr.intr; + endproperty + + a_step_trap_handler_entry : assert property(p_step_trap_handler_entry) + else `uvm_error(info_tag, "single stepping remained in debug mode illegally"); + + property p_step_no_trap; + rvfi.is_dret && csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] && csr_dcsr.rvfi_csr_rdata[DCSR_STEPIE_POS] + ##1 rvfi.rvfi_valid[->1] + ##0 !rvfi.rvfi_dbg_mode + |-> + !rvfi.rvfi_intr.intr || (rvfi.rvfi_intr.intr && rvfi.rvfi_trap.clicptr); + endproperty + + a_step_no_trap : assert property(p_step_no_trap) + else `uvm_error(info_tag, "single stepping should not retire a trap handler entry"); + // Check that we cover the case where a debug_req_i // comes while flushing due to an illegal insn, causing // dpc to be set to the exception handler entry addr - // TODO We have excluded the case where an nmi is taken in the second stage of the antecedent. - // Make sure this is covered in a debug vs nmi assertion when it is written + // Make sure this is covered in a debug vs nmi assertion when it is written sequence s_illegal_insn_debug_req_ante; // Antecedent cov_assert_if.wb_illegal && cov_assert_if.wb_valid && !cov_assert_if.debug_mode_q ##1 cov_assert_if.debug_req_i && !cov_assert_if.debug_mode_q && !cov_assert_if.pending_nmi; @@ -562,16 +761,108 @@ module uvmt_cv32e40s_debug_assert sequence s_illegal_insn_debug_req_conse; // Consequent s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.depc_q == mtvec_addr); + ##0 cov_assert_if.debug_mode_q && (cov_assert_if.dpc_q == mtvec_addr); endsequence // Need to confirm that the assertion can be reached for non-trivial cases cov_illegal_insn_debug_req_nonzero : cover property( - s_illegal_insn_debug_req_ante |-> s_illegal_insn_debug_req_conse ##0 (cov_assert_if.depc_q != 0)); + s_illegal_insn_debug_req_ante ##0 s_illegal_insn_debug_req_conse ##0 (cov_assert_if.dpc_q != 0)); a_illegal_insn_debug_req : assert property(s_illegal_insn_debug_req_ante |-> s_illegal_insn_debug_req_conse) else `uvm_error(info_tag, "Debug mode not entered correctly while handling illegal instruction!"); + // OBI dbg signal needs to correlate to debug mode + + property p_obi_dbg_instr; + (instr_obi.req && !support_if.instr_bus_addr_ph_cont && instr_obi.dbg) + |-> + cov_assert_if.debug_mode_if; + endproperty + + a_obi_dbg_instr : assert property(p_obi_dbg_instr) + else `uvm_error(info_tag, "OBI instruction bus dbg signal high for non-debug transaction"); + + property p_obi_dbg_instr_inv; + (instr_obi.req && !support_if.instr_bus_addr_ph_cont && !instr_obi.dbg) + |-> + !cov_assert_if.debug_mode_if; + endproperty + + a_obi_dbg_instr_inv : assert property(p_obi_dbg_instr_inv) + else `uvm_error(info_tag, "OBI instruction bus dbg signal low for debug transaction"); + + property p_obi_dbg_data; + (data_obi.req && !support_if.data_bus_addr_ph_cont && data_obi.dbg) + |-> + cov_assert_if.debug_mode_q; + endproperty + + a_obi_dbg_data : assert property(p_obi_dbg_data) + else `uvm_error(info_tag, "OBI data bus dbg signal high for non-debug transaction"); + + property p_obi_dbg_data_inv; + (data_obi.req && !support_if.data_bus_addr_ph_cont && !data_obi.dbg) + |-> + !cov_assert_if.debug_mode_q; + endproperty + + a_obi_dbg_data_inv : assert property(p_obi_dbg_data_inv) + else `uvm_error(info_tag, "OBI data bus dbg signal low for debug transaction"); + + // Pending NMI shall be visible in dcsr.nmip + property p_dcsr_nmip; + rvfi.rvfi_dbg_mode && rvfi.is_csr_read(CSR_ADDR_DCSR) && csr_dcsr.rvfi_csr_rdata[DCSR_NMIP_POS] + |-> + rvfi.rvfi_nmip[0]; + endproperty + + a_dcsr_nmip : assert property(p_dcsr_nmip) + else `uvm_error(info_tag, "NMI pending not reflected in dcsr.nmip"); + + // debug_pc_o shall show PC of last retired instruction + property p_debug_pc_o; + (rvfi.rvfi_valid && !rvfi.rvfi_trap.trap) + |-> + rvfi.rvfi_pc_rdata == debug_pc_o_q; + endproperty + + a_debug_pc_o : assert property(p_debug_pc_o) + else `uvm_error(info_tag, "debug_pc_o is not driven correctly") + + property p_debug_pc_o_inv; + int dbg_pc; + (cov_assert_if.debug_pc_valid_o, dbg_pc = cov_assert_if.debug_pc_o) + ##1 rvfi.rvfi_valid[->1] + |-> + rvfi.rvfi_pc_rdata == dbg_pc; + endproperty + + a_debug_pc_o_inv : assert property(p_debug_pc_o_inv) + else `uvm_error(info_tag, "debug_pc_o is not driven correctly") + + + // Exceptions don't update "mcause" + + a_dbg_mcause: assert property ( + rvfi.rvfi_valid && + rvfi.rvfi_dbg_mode && + rvfi.rvfi_trap + |-> + !csr_mstatus.rvfi_csr_wmask + ) else `uvm_error(info_tag, "dmode exceptions shouldn't update mcause") + + + // "mret" causes exceptions + + a_dbg_mret: assert property ( + rvfi.is_mret && + rvfi.rvfi_dbg_mode + |-> + rvfi.rvfi_valid && + rvfi.rvfi_trap.trap && + rvfi.rvfi_trap.exception + ) else `uvm_error(info_tag, "dmode mret should except") + // ------------------------------------------- // Capture internal states for use in checking @@ -580,93 +871,156 @@ module uvmt_cv32e40s_debug_assert always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin if(!cov_assert_if.rst_ni) begin pc_at_dbg_req <= 32'h0; - pc_at_ebreak <= 32'h0; end else begin - // Capture debug pc - if (cov_assert_if.ctrl_fsm_cs == cv32e40s_pkg::BOOT_SET) begin - pc_at_dbg_req <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; - end - if (cov_assert_if.rvfi_valid) begin - pc_at_dbg_req <= cov_assert_if.rvfi_pc_wdata; - if ((debug_cause_pri == 2) && !started_decoding_in_debug) begin // trigger - pc_at_dbg_req <= cov_assert_if.rvfi_pc_rdata; - end - if ((debug_cause_pri == 1) && !started_decoding_in_debug) begin // ebreak - pc_at_dbg_req <= cov_assert_if.rvfi_pc_rdata; + //NMI has highest priority for dpc + if(rvfi.is_nmi && rvfi.rvfi_dbg_mode) begin + if (csr_mtvec.rvfi_csr_rdata[1:0] == 1) begin // vectored CLINT + pc_at_dbg_req <= mtvec_addr+'h3C; + end else begin //unvectored CLINT + pc_at_dbg_req <= mtvec_addr; end - end - if (cov_assert_if.addr_match && !cov_assert_if.tdata1[18] && cov_assert_if.wb_valid) begin // trigger - pc_at_dbg_req <= cov_assert_if.wb_stage_pc; - end - if (cov_assert_if.irq_ack_o) begin // interrupt - if (cov_assert_if.mtvec[1:0] == 0) begin + // if the debug cause is synchronous debug entry IRQ is "taken" first4 + end else if ( rvfi.rvfi_valid && + rvfi.rvfi_dbg_mode && + rvfi.rvfi_intr.intr && + rvfi.rvfi_intr.interrupt) begin + if (csr_mtvec.rvfi_csr_rdata[1:0] == 1) begin //vectored CLINT + pc_at_dbg_req <= mtvec_addr + (rvfi.rvfi_intr.cause << 2); + end else begin //unvectored CLINT pc_at_dbg_req <= mtvec_addr; - end else if (cov_assert_if.mtvec[1:0] == 1) begin - pc_at_dbg_req <= mtvec_addr + (cov_assert_if.irq_id_o << 2); end + // Exception with exception trigger active + end else if (rvfi.is_dbg_trg && rvfi.rvfi_trap.exception) begin + pc_at_dbg_req <= rvfi.rvfi_pc_wdata; + + end else if ((rvfi.is_ebreak && ebreak_allowed)|| rvfi.is_dbg_trg) begin + pc_at_dbg_req <= rvfi.rvfi_pc_rdata; + + end else if (support_if.first_fetch) begin + pc_at_dbg_req <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; + + end else if (rvfi.rvfi_valid) begin + pc_at_dbg_req <= rvfi.rvfi_pc_wdata; end - if(cov_assert_if.pending_nmi && cov_assert_if.nmi_allowed && (cov_assert_if.ctrl_fsm_cs == cv32e40s_pkg::FUNCTIONAL)) - begin - //TODO:ropeders shouldn't "nmi_allowed" be trustable without "ctrl_fsm_cs"? - //TODO:ropeders shouldn't "dcsr.nmip" be usable as a "dpc" pedictor? - //TODO:ropeders shouldn't there be an assert for "dpc" not only on first instr in dmode? - pc_at_dbg_req <= cov_assert_if.nmi_addr_i; - end - if(cov_assert_if.debug_mode_q && started_decoding_in_debug) begin - pc_at_dbg_req <= pc_at_dbg_req; + end + end + + // Breaking down the above structure on debug cause, to improve likelyhood of formal convergence + always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin + if(!cov_assert_if.rst_ni) begin + dpc_dbg_ebreak <= 32'h0; + end else begin + if (rvfi.is_ebreak) begin + dpc_dbg_ebreak <= rvfi.rvfi_pc_rdata; end + end + end - // Capture pc at ebreak - if(cov_assert_if.is_ebreak || cov_assert_if.is_cebreak ) begin - pc_at_ebreak <= cov_assert_if.wb_stage_pc; + always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin + if(!cov_assert_if.rst_ni) begin + dpc_dbg_trg <= 32'h0; + end else begin + if (rvfi.is_dbg_trg && rvfi.rvfi_trap.exception) begin + dpc_dbg_trg <= rvfi.rvfi_pc_wdata; + end else if (rvfi.is_dbg_trg) begin + dpc_dbg_trg <= rvfi.rvfi_pc_rdata; end - end + end end + always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin + if(!cov_assert_if.rst_ni) begin + dpc_dbg_step <= 32'h0; + dpc_dbg_step_notrap <= 32'h0; + dpc_dbg_step_irq <= 32'h0; + dpc_dbg_step_nmi <= 32'h0; + dpc_dbg_haltreq <= 32'h0; + dpc_dbg_haltreq_notrap <= 32'h0; + dpc_dbg_haltreq_irq <= 32'h0; + dpc_dbg_haltreq_nmi <= 32'h0; + end else begin + //NMI has highest priority for dpc + if(rvfi.is_nmi && rvfi.rvfi_dbg_mode) begin + if (csr_mtvec.rvfi_csr_rdata[1:0] == 1) begin // vectored CLINT + dpc_dbg_step <= mtvec_addr+'h3C; + dpc_dbg_step_nmi <= mtvec_addr+'h3C; + dpc_dbg_haltreq <= mtvec_addr+'h3C; + dpc_dbg_haltreq_nmi <= mtvec_addr+'h3C; + end else begin //unvectored CLINT + dpc_dbg_step <= mtvec_addr; + dpc_dbg_step_nmi <= mtvec_addr; + dpc_dbg_haltreq <= mtvec_addr; + dpc_dbg_haltreq_nmi <= mtvec_addr; + end + + // if the debug cause is synchronous debug entry IRQ is "taken" first4 + end else if ( rvfi.rvfi_valid && + rvfi.rvfi_dbg_mode && + rvfi.rvfi_intr.intr && + rvfi.rvfi_intr.interrupt) begin + if (csr_mtvec.rvfi_csr_rdata[1:0] == 1) begin //vectored CLINT + dpc_dbg_step <= mtvec_addr + (rvfi.rvfi_intr.cause << 2); + dpc_dbg_step_irq <= mtvec_addr + (rvfi.rvfi_intr.cause << 2); + dpc_dbg_haltreq <= mtvec_addr + (rvfi.rvfi_intr.cause << 2); + dpc_dbg_haltreq_irq <= mtvec_addr + (rvfi.rvfi_intr.cause << 2); + end else begin //unvectored CLINT + dpc_dbg_step <= mtvec_addr; + dpc_dbg_step_irq <= mtvec_addr; + dpc_dbg_haltreq <= mtvec_addr; + dpc_dbg_haltreq_irq <= mtvec_addr; + end - // Keep track of wfi state + end else if (rvfi.rvfi_valid) begin + dpc_dbg_step <= rvfi.rvfi_pc_wdata; + dpc_dbg_haltreq <= rvfi.rvfi_pc_wdata; - always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin - if (!cov_assert_if.rst_ni) begin - cov_assert_if.in_wfi <= 1'b0; - end else begin - // Enter wfi if we have a valid instruction, and conditions allow it (e.g. no single-step etc) - if (cov_assert_if.is_wfi && cov_assert_if.wb_valid - && !cov_assert_if.pending_debug && !cov_assert_if.debug_mode_q && !cov_assert_if.dcsr_q[2]) - cov_assert_if.in_wfi <= 1'b1; - if (cov_assert_if.pending_enabled_irq || cov_assert_if.debug_req_i) - cov_assert_if.in_wfi <= 1'b0; + end else if (support_if.first_fetch) begin + dpc_dbg_haltreq <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; + end + //keep separate to truly disconnect + if(rvfi.rvfi_valid) begin + dpc_dbg_step_notrap <= rvfi.rvfi_pc_wdata; + dpc_dbg_haltreq_notrap <= rvfi.rvfi_pc_wdata; + end else if (support_if.first_fetch) begin + dpc_dbg_haltreq_notrap <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; + end + + + end end - end - // Capture dm_halt_addr_i value + always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin + if(!cov_assert_if.rst_ni) begin + dpc_rdata_q <= 32'h0; + dcsr_rdata_q <= 32'h0; + debug_pc_o_q <= 32'h0; + end else begin + if(rvfi.rvfi_valid) begin + dpc_rdata_q <= csr_dpc.rvfi_csr_rdata; + dcsr_rdata_q <= csr_dcsr.rvfi_csr_rdata; + end + if(cov_assert_if.debug_pc_valid_o) begin + debug_pc_o_q <= cov_assert_if.debug_pc_o; + end + end + end + + // Capture start values always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin - //TODO:ropeders this should be entirely unnecessary because user manual says it should be stable. Could remove? - if(!cov_assert_if.rst_ni) begin - halt_addr_at_entry_flag <= 1'b0; - end else begin - if(!halt_addr_at_entry_flag) begin - if(cov_assert_if.ctrl_fsm_cs == cv32e40s_pkg::DEBUG_TAKEN) begin - halt_addr_at_entry <= {cov_assert_if.dm_halt_addr_i[31:2], 2'b00}; - tdata2_at_entry <= cov_assert_if.tdata2; - halt_addr_at_entry_flag <= 1'b1; - end - end - - // Clear flag while not in dmode or we see ebreak in debug - if ((!cov_assert_if.debug_mode_q && halt_addr_at_entry_flag) - || (cov_assert_if.debug_mode_q && (cov_assert_if.is_ebreak || cov_assert_if.is_cebreak))) - begin - halt_addr_at_entry_flag <= 1'b0; - end - - // Capture boot addr - if(cov_assert_if.ctrl_fsm_cs == cv32e40s_pkg::BOOT_SET) - boot_addr_at_entry <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; - end + if(!cov_assert_if.rst_ni) begin + halt_addr <= 0; + boot_addr <= 0; + end else begin + if(support_if.first_fetch) begin + halt_addr <= {cov_assert_if.dm_halt_addr_i[31:2], 2'b00}; + boot_addr <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; + end + end end + + always@ (posedge cov_assert_if.clk_i) begin if ((cov_assert_if.illegal_insn_i || (cov_assert_if.sys_ecall_insn_i && cov_assert_if.sys_en_i)) && cov_assert_if.pc_set && cov_assert_if.debug_mode_q && cov_assert_if.wb_valid) @@ -675,12 +1029,12 @@ module uvmt_cv32e40s_debug_assert end end - assign cov_assert_if.addr_match = (cov_assert_if.wb_stage_pc == cov_assert_if.tdata2); - assign cov_assert_if.dpc_will_hit = (cov_assert_if.depc_n == cov_assert_if.tdata2); + assign cov_assert_if.dpc_will_hit = (cov_assert_if.dpc_n == cov_assert_if.tdata2); assign cov_assert_if.pending_enabled_irq = |(cov_assert_if.irq_i & cov_assert_if.mie_q); assign cov_assert_if.is_wfi = cov_assert_if.wb_valid && ((cov_assert_if.wb_stage_instr_rdata_i & WFI_INSTR_MASK) == WFI_INSTR_OPCODE) + && ((rvfi.rvfi_mode == UVMA_RVFI_M_MODE) || (csr_mstatus.rvfi_csr_rdata[MSTATUS_TW_POS] == 1)) //not legal if in user mode with tw == 0 && !cov_assert_if.wb_err && (cov_assert_if.wb_mpu_status == MPU_OK); assign cov_assert_if.is_dret = @@ -689,53 +1043,64 @@ module uvmt_cv32e40s_debug_assert && !cov_assert_if.wb_err && (cov_assert_if.wb_mpu_status == MPU_OK); - // Track which debug cause should be expected - + // cause REQ is treated separately, as it's timing is vaguely defined. always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin if( !cov_assert_if.rst_ni) begin debug_cause_pri <= 3'b000; - end else if(!cov_assert_if.debug_mode_q) begin - if (is_trigger_match) begin - debug_cause_pri <= 3'b010; // Trigger match - end else if(cov_assert_if.dcsr_q[15] && (cov_assert_if.is_ebreak || cov_assert_if.is_cebreak)) begin - debug_cause_pri <= 3'b001; // Ebreak - end else if((cov_assert_if.debug_req_i || cov_assert_if.debug_req_q) - && (cov_assert_if.ctrl_fsm_cs == cv32e40s_pkg::FUNCTIONAL)) begin - debug_cause_pri <= 3'b011; // Haltreq - end else if((cov_assert_if.dcsr_q[2]) && (debug_cause_pri inside {3'b100, 0})) begin // "step" - debug_cause_pri <= 3'b100; // Single step - end else if(cov_assert_if.ctrl_fsm_cs == cv32e40s_pkg::FUNCTIONAL) begin + end else begin + if (rvfi.is_dbg_trg) begin + debug_cause_pri <= cv32e40s_pkg::DBG_CAUSE_TRIGGER; + end else if(rvfi.is_ebreak && ebreak_allowed) begin + debug_cause_pri <= cv32e40s_pkg::DBG_CAUSE_EBREAK; + end else if(rvfi.rvfi_valid && csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS]) begin // "step" + debug_cause_pri <= cv32e40s_pkg::DBG_CAUSE_STEP; + end else if(rvfi.is_dret && !csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS]) begin debug_cause_pri <= 3'b000; // (not a cause) end - // TODO:ropeders should have cause 5 when RTL is ready end end + assign ebreak_allowed = (rvfi.is_mmode && csr_dcsr.rvfi_csr_rdata[DCSR_EBREAKM_POS]) || (rvfi.is_umode && csr_dcsr.rvfi_csr_rdata[DCSR_EBREAKU_POS]); - // Detect first instruction of debug code - - assign first_debug_ins = - cov_assert_if.debug_mode_q && cov_assert_if.wb_valid - && !first_debug_ins_flag && started_decoding_in_debug; + // count the number of rvalids while debug_req is stable always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin if( !cov_assert_if.rst_ni) begin - first_debug_ins_flag <= 0; - started_decoding_in_debug <= 0; + stable_req_vs_valid_cnt <= 4'h0; end else begin - if(cov_assert_if.debug_mode_q) begin - if(cov_assert_if.wb_valid) begin - first_debug_ins_flag <= 1; - end - if(cov_assert_if.id_valid) begin - started_decoding_in_debug <= 1; - end - end else begin - first_debug_ins_flag <= 0; - started_decoding_in_debug <= 0; + if(!cov_assert_if.debug_req_i || (rvfi.rvfi_valid && rvfi.rvfi_dbg_mode)) begin + stable_req_vs_valid_cnt <= 4'h0; + end else if (rvfi.rvfi_valid) begin + stable_req_vs_valid_cnt <= stable_req_vs_valid_cnt + 1; end end end + sequence s_dbg_with_nmi_dret_stepie(bit stepie_value); + rvfi.rvfi_dbg_mode + && rvfi.is_dret + && rvfi.rvfi_nmip[0] + && csr_dcsr.rvfi_csr_rdata[DCSR_STEPIE_POS] == stepie_value + && csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] + && rvfi.rvfi_valid + ##1 + rvfi.rvfi_valid[->1] + ; + endsequence : s_dbg_with_nmi_dret_stepie + + property p_dbg_with_nmi_dret_stepie(bit stepie_value); + reject_on( + csr_mtvec.rvfi_csr_rdata[31:2] == 0 // ignore lower bits + || csr_dpc.rvfi_csr_rdata == 0 + || csr_mtvec.rvfi_csr_rdata == csr_dpc.rvfi_csr_rdata + || rvfi.rvfi_trap.exception) + s_dbg_with_nmi_dret_stepie(stepie_value) + ; + endproperty : p_dbg_with_nmi_dret_stepie + + + cov_dbg_with_nmi_dret_stepie: cover property (p_dbg_with_nmi_dret_stepie(1'b1)); + cov_dbg_with_nmi_dret_stepie_n: cover property (p_dbg_with_nmi_dret_stepie(1'b0)); + endmodule : uvmt_cv32e40s_debug_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_chk.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_chk.sv index e9f3a4d78a..9a8ec2b6eb 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_chk.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_chk.sv @@ -25,7 +25,7 @@ * All ports are SV interfaces. */ module uvmt_cv32e40s_dut_chk( - uvma_debug_if debug_if + uvma_debug_if_t debug_if ); `pragma protect begin diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_wrap.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_wrap.sv index 8ca7b4a3db..9ebae7e2e5 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_wrap.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_dut_wrap.sv @@ -35,117 +35,64 @@ `ifndef __UVMT_CV32E40S_DUT_WRAP_SV__ `define __UVMT_CV32E40S_DUT_WRAP_SV__ +`default_nettype none + /** * Module wrapper for CV32E40S RTL DUT. */ + module uvmt_cv32e40s_dut_wrap - import cv32e40s_pkg::*; - - #(// DUT (riscv_core) parameters. - parameter cv32e40s_pkg::b_ext_e B_EXT = cv32e40s_pkg::B_NONE, - parameter int PMA_NUM_REGIONS = 0, - parameter pma_region_t PMA_CFG[PMA_NUM_REGIONS-1 : 0] = '{default:PMA_R_DEFAULT}, - parameter int PMP_NUM_REGIONS = 0, - // Remaining parameters are used by TB components only - INSTR_ADDR_WIDTH = 32, - INSTR_RDATA_WIDTH = 32, - RAM_ADDR_WIDTH = 20 - ) +#( + parameter INSTR_ADDR_WIDTH = 32, + parameter INSTR_RDATA_WIDTH = 32, + parameter RAM_ADDR_WIDTH = 20 + ) ( - uvma_clknrst_if clknrst_if, - uvma_interrupt_if interrupt_if, - uvmt_cv32e40s_vp_status_if vp_status_if, - uvme_cv32e40s_core_cntrl_if core_cntrl_if, - uvmt_cv32e40s_core_status_if core_status_if, - uvma_obi_memory_if obi_instr_if_i, - uvma_obi_memory_if obi_data_if_i, - uvma_fencei_if fencei_if_i + uvma_clknrst_if_t clknrst_if, + uvma_interrupt_if_t interrupt_if, + uvma_clic_if_t clic_if, + uvma_wfe_wu_if_t wfe_wu_if, + uvmt_cv32e40s_vp_status_if_t vp_status_if, + uvme_cv32e40s_core_cntrl_if_t core_cntrl_if, + uvmt_cv32e40s_core_status_if_t core_status_if, + uvma_obi_memory_if_t obi_instr_if, + uvma_obi_memory_if_t obi_data_if, + uvma_fencei_if_t fencei_if ); - import uvm_pkg::*; // needed for the UVM messaging service (`uvm_info(), etc.) - - // signals connecting core to memory - logic instr_req; - logic instr_gnt; - logic instr_rvalid; - logic [INSTR_ADDR_WIDTH-1 :0] instr_addr; - logic [INSTR_RDATA_WIDTH-1:0] instr_rdata; - - logic data_req; - logic data_gnt; - logic data_rvalid; - logic [31:0] data_addr; - logic data_we; - logic [3:0] data_be; - logic [31:0] data_rdata; - logic [31:0] data_wdata; - - logic [31:0] irq; - - logic debug_havereset; - logic debug_running; - logic debug_halted; - - assign debug_if.clk = clknrst_if.clk; - assign debug_if.reset_n = clknrst_if.reset_n; - - // -------------------------------------------- - // OBI Instruction agent v1.2 signal tie-offs - assign obi_instr_if_i.we = 'b0; - assign obi_instr_if_i.be = 'hf; // Always assumes 32-bit full bus reads on instruction OBI - assign obi_instr_if_i.auser = 'b0; - assign obi_instr_if_i.wuser = 'b0; - assign obi_instr_if_i.aid = 'b0; - assign obi_instr_if_i.wdata = 'b0; - assign obi_instr_if_i.reqpar = ~obi_instr_if_i.req; - assign obi_instr_if_i.achk = 'b0; - assign obi_instr_if_i.rchk = 'b0; - assign obi_instr_if_i.rready = 1'b1; - assign obi_instr_if_i.rreadypar = 1'b0; - - // -------------------------------------------- - // OBI Data agent v12.2 signal tie-offs - assign obi_data_if_i.auser = 'b0; - assign obi_data_if_i.wuser = 'b0; - assign obi_data_if_i.aid = 'b0; - assign obi_data_if_i.reqpar = ~obi_data_if_i.req; - assign obi_data_if_i.achk = 'b0; - assign obi_data_if_i.rchk = 'b0; - assign obi_data_if_i.rready = 1'b1; - assign obi_data_if_i.rreadypar = 1'b0; - - // -------------------------------------------- - // Connect to uvma_interrupt_if - assign interrupt_if.clk = clknrst_if.clk; - assign interrupt_if.reset_n = clknrst_if.reset_n; - assign interrupt_if.irq_id = cv32e40s_wrapper_i.core_i.irq_id; - assign interrupt_if.irq_ack = cv32e40s_wrapper_i.core_i.irq_ack; - - // -------------------------------------------- - // Connect to core_cntrl_if - assign core_cntrl_if.b_ext = B_EXT; - initial begin - core_cntrl_if.pma_cfg = new[PMA_NUM_REGIONS]; - foreach (core_cntrl_if.pma_cfg[i]) begin - core_cntrl_if.pma_cfg[i].word_addr_low = PMA_CFG[i].word_addr_low; - core_cntrl_if.pma_cfg[i].word_addr_high = PMA_CFG[i].word_addr_high; - core_cntrl_if.pma_cfg[i].main = PMA_CFG[i].main; - core_cntrl_if.pma_cfg[i].bufferable = PMA_CFG[i].bufferable; - core_cntrl_if.pma_cfg[i].cacheable = PMA_CFG[i].cacheable; - end - end - - // -------------------------------------------- + logic debug_havereset; + logic debug_running; + logic debug_halted; + logic debug_pc_valid; + logic [31:0] debug_pc; + + logic alert_major; + logic alert_minor; + + // instantiate the core + cv32e40s_wrapper #( - .B_EXT (B_EXT), - .PMA_NUM_REGIONS (PMA_NUM_REGIONS), - .PMA_CFG (PMA_CFG), - .PMP_NUM_REGIONS (PMP_NUM_REGIONS) - ) - cv32e40s_wrapper_i - ( + .B_EXT (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_B_EXT), + .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC), + .CLIC_ID_WIDTH (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH), + .DBG_NUM_TRIGGERS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS), + .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), + .DM_REGION_START (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_START), + .LFSR0_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_LFSR0_CFG), + .LFSR1_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_LFSR1_CFG), + .LFSR2_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_LFSR2_CFG), + .M_EXT (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_M_EXT), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMP_GRANULARITY (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_GRANULARITY), + .PMP_MSECCFG_RV (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_MSECCFG_RV), + .PMP_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_NUM_REGIONS), + .PMP_PMPADDR_RV (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_PMPADDR_RV), + .PMP_PMPNCFG_RV (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_PMPNCFG_RV), + .RV32 (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_RV32) + ) cv32e40s_wrapper_i ( .clk_i ( clknrst_if.clk ), .rst_ni ( clknrst_if.reset_n ), @@ -154,64 +101,63 @@ module uvmt_cv32e40s_dut_wrap .boot_addr_i ( core_cntrl_if.boot_addr ), .mtvec_addr_i ( core_cntrl_if.mtvec_addr ), .dm_halt_addr_i ( core_cntrl_if.dm_halt_addr ), - .nmi_addr_i ( core_cntrl_if.nmi_addr ), .mhartid_i ( core_cntrl_if.mhartid ), - .mimpid_i ( core_cntrl_if.mimpid ), + .mimpid_patch_i ( core_cntrl_if.mimpid_patch ), .dm_exception_addr_i ( core_cntrl_if.dm_exception_addr), - .instr_req_o ( obi_instr_if_i.req ), - .instr_reqpar_o ( /* todo: connect */ ), - .instr_gnt_i ( obi_instr_if_i.gnt ), - .instr_gntpar_i ( 1'b0 /* todo: connect */ ), - .instr_addr_o ( obi_instr_if_i.addr ), - .instr_achk_o ( /* todo: connect */ ), - .instr_prot_o ( obi_instr_if_i.prot ), - .instr_dbg_o ( /* obi_instr_if_i.dbg */ ), // todo: Support OBI 1.3 - .instr_memtype_o ( obi_instr_if_i.memtype ), - .instr_rdata_i ( obi_instr_if_i.rdata ), - .instr_rchk_i ( '0 /* todo: connect */ ), - .instr_rvalid_i ( obi_instr_if_i.rvalid ), - .instr_rvalidpar_i ( 1'b0 /* todo: connect */ ), - .instr_err_i ( obi_instr_if_i.err ), - - .data_req_o ( obi_data_if_i.req ), - .data_reqpar_o ( /* todo: connect */ ), - .data_gnt_i ( obi_data_if_i.gnt ), - .data_gntpar_i ( 1'b0 /* todo: connect */ ), - .data_rvalid_i ( obi_data_if_i.rvalid ), - .data_rvalidpar_i ( 1'b0 /* todo: connect */ ), - .data_we_o ( obi_data_if_i.we ), - .data_be_o ( obi_data_if_i.be ), - .data_addr_o ( obi_data_if_i.addr ), - .data_achk_o ( /* todo: connect */ ), - .data_wdata_o ( obi_data_if_i.wdata ), - .data_prot_o ( obi_data_if_i.prot ), - .data_dbg_o ( /* obi_data_if_i.dbg */ ), // todo: Support OBI 1.3 - .data_memtype_o ( obi_data_if_i.memtype ), - .data_rdata_i ( obi_data_if_i.rdata ), - .data_rchk_i ( '0 /* todo: connect */ ), - .data_err_i ( obi_data_if_i.err ), + .instr_req_o ( obi_instr_if.req ), + .instr_reqpar_o ( obi_instr_if.reqpar ), + .instr_gnt_i ( obi_instr_if.gnt ), + .instr_gntpar_i ( obi_instr_if.gntpar ), + .instr_addr_o ( obi_instr_if.addr ), + .instr_achk_o ( obi_instr_if.achk ), + .instr_prot_o ( obi_instr_if.prot ), + .instr_dbg_o ( obi_instr_if.dbg ), + .instr_memtype_o ( obi_instr_if.memtype ), + .instr_rdata_i ( obi_instr_if.rdata ), + .instr_rchk_i ( obi_instr_if.rchk ), + .instr_rvalid_i ( obi_instr_if.rvalid ), + .instr_rvalidpar_i ( obi_instr_if.rvalidpar ), + .instr_err_i ( obi_instr_if.err ), + + .data_req_o ( obi_data_if.req ), + .data_reqpar_o ( obi_data_if.reqpar ), + .data_gnt_i ( obi_data_if.gnt ), + .data_gntpar_i ( obi_data_if.gntpar ), + .data_rvalid_i ( obi_data_if.rvalid ), + .data_rvalidpar_i ( obi_data_if.rvalidpar ), + .data_we_o ( obi_data_if.we ), + .data_be_o ( obi_data_if.be ), + .data_addr_o ( obi_data_if.addr ), + .data_achk_o ( obi_data_if.achk ), + .data_wdata_o ( obi_data_if.wdata ), + .data_prot_o ( obi_data_if.prot ), + .data_dbg_o ( obi_data_if.dbg ), + .data_memtype_o ( obi_data_if.memtype ), + .data_rdata_i ( obi_data_if.rdata ), + .data_rchk_i ( obi_data_if.rchk ), + .data_err_i ( obi_data_if.err ), .mcycle_o ( /*todo: connect */ ), .irq_i ( interrupt_if.irq ), + .wu_wfe_i ( wfe_wu_if.wfe_wu ), + .clic_irq_i ( clic_if.clic_irq ), + .clic_irq_id_i ( clic_if.clic_irq_id ), + .clic_irq_level_i ( clic_if.clic_irq_level ), + .clic_irq_priv_i ( clic_if.clic_irq_priv ), + .clic_irq_shv_i ( clic_if.clic_irq_shv ), - .clic_irq_i ( '0 /*todo: connect */ ), - .clic_irq_id_i ( '0 /*todo: connect */ ), - .clic_irq_il_i ( '0 /*todo: connect */ ), - .clic_irq_priv_i ( '0 /*todo: connect */ ), - .clic_irq_hv_i ( '0 /*todo: connect */ ), - .clic_irq_id_o ( /*todo: connect */ ), - .clic_irq_mode_o ( /*todo: connect */ ), - .clic_irq_exit_o ( /*todo: connect */ ), - .fencei_flush_req_o ( fencei_if_i.flush_req ), - .fencei_flush_ack_i ( fencei_if_i.flush_ack ), + .fencei_flush_req_o ( fencei_if.flush_req ), + .fencei_flush_ack_i ( fencei_if.flush_ack ), .debug_req_i ( debug_if.debug_req ), .debug_havereset_o ( debug_havereset ), .debug_running_o ( debug_running ), .debug_halted_o ( debug_halted ), + .debug_pc_valid_o ( debug_pc_valid ), + .debug_pc_o ( debug_pc ), .alert_major_o ( alert_major ), .alert_minor_o ( alert_minor ), @@ -222,4 +168,6 @@ module uvmt_cv32e40s_dut_wrap endmodule : uvmt_cv32e40s_dut_wrap +`default_nettype wire + `endif // __UVMT_CV32E40S_DUT_WRAP_SV__ diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_imperas_dummy_pkg.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_imperas_dummy_pkg.sv new file mode 100644 index 0000000000..c4f9ce901b --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_imperas_dummy_pkg.sv @@ -0,0 +1,60 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// + +`ifndef __UVMT_CV32E40S_IMPERAS_DUMMY_PKG_SV__ +`define __UVMT_CV32E40S_IMPERAS_DUMMY_PKG_SV__ +import uvm_pkg::*; + +package rvviApiPkg; + function int rvviRefShutdown(); + `uvm_error("ISS_DUMMY", "USE_ISS=1 set but no ISS installation is available"); + return 0; + endfunction : rvviRefShutdown + + function void rvviRefMemoryWrite( + int hartId, + longint address, + longint data, + int size + ); + `uvm_error("ISS_DUMMY", "USE_ISS=1 set but not ISS installation is available"); + endfunction : rvviRefMemoryWrite +endpackage : rvviApiPkg + +interface rvviTrace + #( + parameter int NHART = 1, + parameter int RETIRE = 1 + ); +endinterface : rvviTrace + +module uvmt_cv32e40s_imperas_dv_wrap + import uvm_pkg::*; + #() + ( + rvviTrace rvvi + ); + +endmodule : uvmt_cv32e40s_imperas_dv_wrap + +interface uvmt_imperas_dv_if_t; + task ref_init; + `uvm_info("ISS_DUMMY", "ref_init called from uvmt_cv32e40s_imperas_dummy_pkg.sv", UVM_LOW); + endtask : ref_init +endinterface : uvmt_imperas_dv_if_t + +`endif // __UVMT_CV32E40S_IMPERAS_DUMMY_PKG_SV__ diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_imperas_dv_wrap.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_imperas_dv_wrap.sv new file mode 100644 index 0000000000..9a567ede5c --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_imperas_dv_wrap.sv @@ -0,0 +1,1019 @@ +// +// Copyright 2022 OpenHW Group +// Copyright 2023 Imperas +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// + + +`ifndef __UVMT_CV32E40S_IMPERAS_DV_WRAP_SV__ +`define __UVMT_CV32E40S_IMPERAS_DV_WRAP_SV__ + +`define DUT_PATH dut_wrap.cv32e40s_wrapper_i +`define RVFI_IF `DUT_PATH.rvfi_instr_if + +`define STRINGIFY(x) `"x`" + +//////////////////////////////////////////////////////////////////////////// +// Assign the rvvi CSR values from RVFI - CSR = (wdata & wmask) | (rdata & ~wmask) +//////////////////////////////////////////////////////////////////////////// +`define RVVI_SET_CSR(CSR_ADDR, CSR_NAME) \ + bit csr_``CSR_NAME``_wb; \ + wire [31:0] csr_``CSR_NAME``_w; \ + wire [31:0] csr_``CSR_NAME``_r; \ + assign csr_``CSR_NAME``_w = `DUT_PATH.rvfi_csr_``CSR_NAME``_if.rvfi_csr_wdata & `DUT_PATH.rvfi_csr_``CSR_NAME``_if.rvfi_csr_wmask; \ + assign csr_``CSR_NAME``_r = `DUT_PATH.rvfi_csr_``CSR_NAME``_if.rvfi_csr_rdata & ~(`DUT_PATH.rvfi_csr_``CSR_NAME``_if.rvfi_csr_wmask); \ + assign rvvi.csr[0][0][``CSR_ADDR] = csr_``CSR_NAME``_w | csr_``CSR_NAME``_r; \ + assign rvvi.csr_wb[0][0][``CSR_ADDR] = csr_``CSR_NAME``_wb; \ + always @(rvvi.csr[0][0][``CSR_ADDR]) begin \ + if ((`DUT_PATH.rvfi_csr_``CSR_NAME``_if.rvfi_csr_rmask || `DUT_PATH.rvfi_csr_``CSR_NAME``_if.rvfi_csr_wmask) && `RVFI_IF.rvfi_valid) begin \ + csr_``CSR_NAME``_wb = 1; \ + end \ + end \ + always @(posedge rvvi.clk) begin \ + if (`RVFI_IF.rvfi_valid && csr_``CSR_NAME``_wb) begin \ + csr_``CSR_NAME``_wb = 0; \ + end \ + end + +//////////////////////////////////////////////////////////////////////////// +// Assign the NET IRQ values from the core irq inputs +//////////////////////////////////////////////////////////////////////////// +`define RVVI_WRITE_IRQ(IRQ_NAME, IRQ_IDX) \ + wire irq_``IRQ_NAME; \ + assign irq_``IRQ_NAME = `DUT_PATH.irq_i[IRQ_IDX]; \ + always @(irq_``IRQ_NAME) begin \ + void'(rvvi.net_push(`STRINGIFY(``IRQ_NAME), irq_``IRQ_NAME)); \ + end + +//////////////////////////////////////////////////////////////////////////// +// CSR definitions +//////////////////////////////////////////////////////////////////////////// +`define CSR_JVT_ADDR 32'h017 +`define CSR_MSTATUS_ADDR 32'h300 +`define CSR_MISA_ADDR 32'h301 +`define CSR_MIE_ADDR 32'h304 +`define CSR_MTVEC_ADDR 32'h305 +`define CSR_MCOUNTEREN_ADDR 32'h306 +`define CSR_MENVCFG_ADDR 32'h30A +`define CSR_MSTATEEN0_ADDR 32'h30C +`define CSR_MSTATEEN1_ADDR 32'h30D +`define CSR_MSTATEEN2_ADDR 32'h30E +`define CSR_MSTATEEN3_ADDR 32'h30F +`define CSR_MTVT_ADDR 32'h307 // only available when CLIC=1 +`define CSR_MSTATUSH_ADDR 32'h310 +`define CSR_MENVCFGH_ADDR 32'h31A +`define CSR_MSTATEEN0H_ADDR 32'h31C +`define CSR_MSTATEEN1H_ADDR 32'h31D +`define CSR_MSTATEEN2H_ADDR 32'h31E +`define CSR_MSTATEEN3H_ADDR 32'h31F +`define CSR_MCOUNTINHIBIT_ADDR 32'h320 + +`define CSR_MHPMEVENT3_ADDR 32'h323 +`define CSR_MHPMEVENT4_ADDR 32'h324 +`define CSR_MHPMEVENT5_ADDR 32'h325 +`define CSR_MHPMEVENT6_ADDR 32'h326 +`define CSR_MHPMEVENT7_ADDR 32'h327 +`define CSR_MHPMEVENT8_ADDR 32'h328 +`define CSR_MHPMEVENT9_ADDR 32'h329 +`define CSR_MHPMEVENT10_ADDR 32'h32A +`define CSR_MHPMEVENT11_ADDR 32'h32B +`define CSR_MHPMEVENT12_ADDR 32'h32C +`define CSR_MHPMEVENT13_ADDR 32'h32D +`define CSR_MHPMEVENT14_ADDR 32'h32E +`define CSR_MHPMEVENT15_ADDR 32'h32F +`define CSR_MHPMEVENT16_ADDR 32'h330 +`define CSR_MHPMEVENT17_ADDR 32'h331 +`define CSR_MHPMEVENT18_ADDR 32'h332 +`define CSR_MHPMEVENT19_ADDR 32'h333 +`define CSR_MHPMEVENT20_ADDR 32'h334 +`define CSR_MHPMEVENT21_ADDR 32'h335 +`define CSR_MHPMEVENT22_ADDR 32'h336 +`define CSR_MHPMEVENT23_ADDR 32'h337 +`define CSR_MHPMEVENT24_ADDR 32'h338 +`define CSR_MHPMEVENT25_ADDR 32'h339 +`define CSR_MHPMEVENT26_ADDR 32'h33A +`define CSR_MHPMEVENT27_ADDR 32'h33B +`define CSR_MHPMEVENT28_ADDR 32'h33C +`define CSR_MHPMEVENT29_ADDR 32'h33D +`define CSR_MHPMEVENT30_ADDR 32'h33E +`define CSR_MHPMEVENT31_ADDR 32'h33F + +`define CSR_MSCRATCH_ADDR 32'h340 +`define CSR_MEPC_ADDR 32'h341 +`define CSR_MCAUSE_ADDR 32'h342 +`define CSR_MTVAL_ADDR 32'h343 +`define CSR_MIP_ADDR 32'h344 +`define CSR_MNXTI_ADDR 32'h345 // only available when CLIC=1 +`define CSR_MINTSTATUS_ADDR 32'hFB1 // only available when CLIC=1 +`define CSR_MINTTHRESH_ADDR 32'h347 // only available when CLIC=1 +`define CSR_MSCRATCHCSW_ADDR 32'h348 // only available when CLIC=1 +`define CSR_MSCRATCHCSWL_ADDR 32'h349 // only available when CLIC=1 +`define CSR_MCLICBASE_ADDR 32'h34A // only available when CLIC=1 + +`define CSR_PMPCFG0_ADDR 32'h3A0 +`define CSR_PMPCFG1_ADDR 32'h3A1 +`define CSR_PMPCFG2_ADDR 32'h3A2 +`define CSR_PMPCFG3_ADDR 32'h3A3 +`define CSR_PMPCFG4_ADDR 32'h3A4 +`define CSR_PMPCFG5_ADDR 32'h3A5 +`define CSR_PMPCFG6_ADDR 32'h3A6 +`define CSR_PMPCFG7_ADDR 32'h3A7 +`define CSR_PMPCFG8_ADDR 32'h3A8 +`define CSR_PMPCFG9_ADDR 32'h3A9 +`define CSR_PMPCFG10_ADDR 32'h3AA +`define CSR_PMPCFG11_ADDR 32'h3AB +`define CSR_PMPCFG12_ADDR 32'h3AC +`define CSR_PMPCFG13_ADDR 32'h3AD +`define CSR_PMPCFG14_ADDR 32'h3AE +`define CSR_PMPCFG15_ADDR 32'h3AF + +`define CSR_PMPADDR0_ADDR 32'h3B0 +`define CSR_PMPADDR1_ADDR 32'h3B1 +`define CSR_PMPADDR2_ADDR 32'h3B2 +`define CSR_PMPADDR3_ADDR 32'h3B3 +`define CSR_PMPADDR4_ADDR 32'h3B4 +`define CSR_PMPADDR5_ADDR 32'h3B5 +`define CSR_PMPADDR6_ADDR 32'h3B6 +`define CSR_PMPADDR7_ADDR 32'h3B7 +`define CSR_PMPADDR8_ADDR 32'h3B8 +`define CSR_PMPADDR9_ADDR 32'h3B9 +`define CSR_PMPADDR10_ADDR 32'h3BA +`define CSR_PMPADDR11_ADDR 32'h3BB +`define CSR_PMPADDR12_ADDR 32'h3BC +`define CSR_PMPADDR13_ADDR 32'h3BD +`define CSR_PMPADDR14_ADDR 32'h3BE +`define CSR_PMPADDR15_ADDR 32'h3BF +`define CSR_PMPADDR16_ADDR 32'h3C0 +`define CSR_PMPADDR17_ADDR 32'h3C1 +`define CSR_PMPADDR18_ADDR 32'h3C2 +`define CSR_PMPADDR19_ADDR 32'h3C3 +`define CSR_PMPADDR20_ADDR 32'h3C4 +`define CSR_PMPADDR21_ADDR 32'h3C5 +`define CSR_PMPADDR22_ADDR 32'h3C6 +`define CSR_PMPADDR23_ADDR 32'h3C7 +`define CSR_PMPADDR24_ADDR 32'h3C8 +`define CSR_PMPADDR25_ADDR 32'h3C9 +`define CSR_PMPADDR26_ADDR 32'h3CA +`define CSR_PMPADDR27_ADDR 32'h3CB +`define CSR_PMPADDR28_ADDR 32'h3CC +`define CSR_PMPADDR29_ADDR 32'h3CD +`define CSR_PMPADDR30_ADDR 32'h3CE +`define CSR_PMPADDR31_ADDR 32'h3CF +`define CSR_PMPADDR32_ADDR 32'h3D0 +`define CSR_PMPADDR33_ADDR 32'h3D1 +`define CSR_PMPADDR34_ADDR 32'h3D2 +`define CSR_PMPADDR35_ADDR 32'h3D3 +`define CSR_PMPADDR36_ADDR 32'h3D4 +`define CSR_PMPADDR37_ADDR 32'h3D5 +`define CSR_PMPADDR38_ADDR 32'h3D6 +`define CSR_PMPADDR39_ADDR 32'h3D7 +`define CSR_PMPADDR40_ADDR 32'h3D8 +`define CSR_PMPADDR41_ADDR 32'h3D9 +`define CSR_PMPADDR42_ADDR 32'h3DA +`define CSR_PMPADDR43_ADDR 32'h3DB +`define CSR_PMPADDR44_ADDR 32'h3DC +`define CSR_PMPADDR45_ADDR 32'h3DD +`define CSR_PMPADDR46_ADDR 32'h3DE +`define CSR_PMPADDR47_ADDR 32'h3DF +`define CSR_PMPADDR48_ADDR 32'h3E0 +`define CSR_PMPADDR49_ADDR 32'h3E1 +`define CSR_PMPADDR50_ADDR 32'h3E2 +`define CSR_PMPADDR51_ADDR 32'h3E3 +`define CSR_PMPADDR52_ADDR 32'h3E4 +`define CSR_PMPADDR53_ADDR 32'h3E5 +`define CSR_PMPADDR54_ADDR 32'h3E6 +`define CSR_PMPADDR55_ADDR 32'h3E7 +`define CSR_PMPADDR56_ADDR 32'h3E8 +`define CSR_PMPADDR57_ADDR 32'h3E9 +`define CSR_PMPADDR58_ADDR 32'h3EA +`define CSR_PMPADDR59_ADDR 32'h3EB +`define CSR_PMPADDR60_ADDR 32'h3EC +`define CSR_PMPADDR61_ADDR 32'h3ED +`define CSR_PMPADDR62_ADDR 32'h3EE +`define CSR_PMPADDR63_ADDR 32'h3EF + +`define CSR_MSECCFG_ADDR 32'h747 +`define CSR_MSECCFGH_ADDR 32'h757 + +`define CSR_TSELECT_ADDR 32'h7A0 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TDATA1_ADDR 32'h7A1 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TDATA2_ADDR 32'h7A2 // only when DBG_NUM_TRIGGERS > 0 +`define CSR_TINFO_ADDR 32'h7A4 // only when DBG_NUM_TRIGGERS > 0 + +`define CSR_DCSR_ADDR 32'h7B0 +`define CSR_DPC_ADDR 32'h7B1 +`define CSR_DSCRATCH0_ADDR 32'h7B2 +`define CSR_DSCRATCH1_ADDR 32'h7B3 + +`define CSR_MCYCLE_ADDR 32'hB00 +`define CSR_MINSTRET_ADDR 32'hB02 + +`define CSR_MHPMCOUNTER3_ADDR 32'hB03 +`define CSR_MHPMCOUNTER4_ADDR 32'hB04 +`define CSR_MHPMCOUNTER5_ADDR 32'hB05 +`define CSR_MHPMCOUNTER6_ADDR 32'hB06 +`define CSR_MHPMCOUNTER7_ADDR 32'hB07 +`define CSR_MHPMCOUNTER8_ADDR 32'hB08 +`define CSR_MHPMCOUNTER9_ADDR 32'hB09 +`define CSR_MHPMCOUNTER10_ADDR 32'hB0A +`define CSR_MHPMCOUNTER11_ADDR 32'hB0B +`define CSR_MHPMCOUNTER12_ADDR 32'hB0C +`define CSR_MHPMCOUNTER13_ADDR 32'hB0D +`define CSR_MHPMCOUNTER14_ADDR 32'hB0E +`define CSR_MHPMCOUNTER15_ADDR 32'hB0F +`define CSR_MHPMCOUNTER16_ADDR 32'hB10 +`define CSR_MHPMCOUNTER17_ADDR 32'hB11 +`define CSR_MHPMCOUNTER18_ADDR 32'hB12 +`define CSR_MHPMCOUNTER19_ADDR 32'hB13 +`define CSR_MHPMCOUNTER20_ADDR 32'hB14 +`define CSR_MHPMCOUNTER21_ADDR 32'hB15 +`define CSR_MHPMCOUNTER22_ADDR 32'hB16 +`define CSR_MHPMCOUNTER23_ADDR 32'hB17 +`define CSR_MHPMCOUNTER24_ADDR 32'hB18 +`define CSR_MHPMCOUNTER25_ADDR 32'hB19 +`define CSR_MHPMCOUNTER26_ADDR 32'hB1A +`define CSR_MHPMCOUNTER27_ADDR 32'hB1B +`define CSR_MHPMCOUNTER28_ADDR 32'hB1C +`define CSR_MHPMCOUNTER29_ADDR 32'hB1D +`define CSR_MHPMCOUNTER30_ADDR 32'hB1E +`define CSR_MHPMCOUNTER31_ADDR 32'hB1F + +`define CSR_MCYCLEH_ADDR 32'hB80 +`define CSR_MINSTRETH_ADDR 32'hB82 + +`define CSR_MHPMCOUNTER3H_ADDR 32'hB83 +`define CSR_MHPMCOUNTER4H_ADDR 32'hB84 +`define CSR_MHPMCOUNTER5H_ADDR 32'hB85 +`define CSR_MHPMCOUNTER6H_ADDR 32'hB86 +`define CSR_MHPMCOUNTER7H_ADDR 32'hB87 +`define CSR_MHPMCOUNTER8H_ADDR 32'hB88 +`define CSR_MHPMCOUNTER9H_ADDR 32'hB89 +`define CSR_MHPMCOUNTER10H_ADDR 32'hB8A +`define CSR_MHPMCOUNTER11H_ADDR 32'hB8B +`define CSR_MHPMCOUNTER12H_ADDR 32'hB8C +`define CSR_MHPMCOUNTER13H_ADDR 32'hB8D +`define CSR_MHPMCOUNTER14H_ADDR 32'hB8E +`define CSR_MHPMCOUNTER15H_ADDR 32'hB8F +`define CSR_MHPMCOUNTER16H_ADDR 32'hB90 +`define CSR_MHPMCOUNTER17H_ADDR 32'hB91 +`define CSR_MHPMCOUNTER18H_ADDR 32'hB92 +`define CSR_MHPMCOUNTER19H_ADDR 32'hB93 +`define CSR_MHPMCOUNTER20H_ADDR 32'hB94 +`define CSR_MHPMCOUNTER21H_ADDR 32'hB95 +`define CSR_MHPMCOUNTER22H_ADDR 32'hB96 +`define CSR_MHPMCOUNTER23H_ADDR 32'hB97 +`define CSR_MHPMCOUNTER24H_ADDR 32'hB98 +`define CSR_MHPMCOUNTER25H_ADDR 32'hB99 +`define CSR_MHPMCOUNTER26H_ADDR 32'hB9A +`define CSR_MHPMCOUNTER27H_ADDR 32'hB9B +`define CSR_MHPMCOUNTER28H_ADDR 32'hB9C +`define CSR_MHPMCOUNTER29H_ADDR 32'hB9D +`define CSR_MHPMCOUNTER30H_ADDR 32'hB9E +`define CSR_MHPMCOUNTER31H_ADDR 32'hB9F + +`define CSR_CPUCTRL_ADDR 32'hBF0 +`define CSR_SECURESEED0_ADDR 32'hBF9 +`define CSR_SECURESEED1_ADDR 32'hBFA +`define CSR_SECURESEED2_ADDR 32'hBFC + +`define CSR_MVENDORID_ADDR 32'hF11 +`define CSR_MARCHID_ADDR 32'hF12 +`define CSR_MIMPID_ADDR 32'hF13 +`define CSR_MHARTID_ADDR 32'hF14 +`define CSR_MCONFIGPTR_ADDR 32'hF15 + +/////////////////////////////////////////////////////////////////////////////// +// Module wrapper for Imperas DV. +//////////////////////////////////////////////////////////////////////////// +`ifdef USE_IMPERASDV + +`include "idv/idv.svh" // located in $IMPERAS_HOME/ImpProprietary/include/host + +module uvmt_cv32e40s_imperas_dv_wrap + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import uvme_cv32e40s_pkg::*; + import rvviApiPkg::*; + #( + ) + + ( + rvviTrace rvvi // RVVI SystemVerilog Interface + ); + + trace2api #(.CMP_PC (1), + .CMP_INS (1), + .CMP_GPR (1), + .CMP_FPR (0), + .CMP_VR (0), + .CMP_CSR (1) + ) + idv_trace2api(rvvi); + + trace2log idv_trace2log(rvvi); + + trace2cov idv_trace2cov(rvvi); + + string info_tag = "ImperasDV_wrap"; + + // Make the UVM environment configuration available to the Reference Model as needed. + uvme_cv32e40s_cfg_c uvm_env_cfg; + + initial begin + @(rvvi.clk); + void'(uvm_config_db#(uvme_cv32e40s_cfg_c)::get(null, "uvm_test_top.env", "cfg", uvm_env_cfg)); + if (!uvm_env_cfg) begin + `uvm_fatal(info_tag, "Configuration handle is null") + end + else begin + `uvm_info(info_tag, $sformatf("Found UVM environment configuration handle:\n%s", uvm_env_cfg.sprint()), UVM_DEBUG) + end + end + + //////////////////////////////////////////////////////////////////////////// + // Adopted from: + // ImperasDV/examples/openhwgroup_cv32e40s/systemverilog/cv32e40s_testbench.sv + // + // InstrunctionBusFault(48) is in fact a TRAP which is derived externally + // This is strange as other program TRAPS are derived by the model, for now + // We have to ensure we do not step the REF model for this TRAP as it will + // Step too far. So instead we block it as being VALID, but pass on the + // signals. + // maybe we need a different way to communicate this to the model, for + // instance the ability to register a callback on fetch, in order to assert + // this signal. + //////////////////////////////////////////////////////////////////////////// + assign rvvi.clk = `RVFI_IF.clk; + assign rvvi.valid[0][0] = `RVFI_IF.rvfi_valid; + assign rvvi.order[0][0] = `RVFI_IF.rvfi_order; + assign rvvi.insn[0][0] = `RVFI_IF.rvfi_insn; + assign rvvi.trap[0][0] = (`RVFI_IF.rvfi_trap.trap && `RVFI_IF.rvfi_trap.exception == 1'b1) || // Exceptions never retire + (`RVFI_IF.rvfi_trap.trap && `RVFI_IF.rvfi_trap.debug == 1'b1 && `RVFI_IF.rvfi_trap.debug_cause == 'h1) || // Ebreak never retires + (`RVFI_IF.rvfi_trap.trap && `RVFI_IF.rvfi_trap.debug == 1'b1 && `RVFI_IF.rvfi_trap.debug_cause == 'h2); // Trigger match never retires + assign rvvi.intr[0][0] = `RVFI_IF.rvfi_intr; + assign rvvi.mode[0][0] = `RVFI_IF.rvfi_mode; + assign rvvi.ixl[0][0] = `RVFI_IF.rvfi_ixl; + assign rvvi.pc_rdata[0][0] = `RVFI_IF.rvfi_pc_rdata; + assign rvvi.pc_wdata[0][0] = `RVFI_IF.rvfi_pc_wdata; + + `RVVI_SET_CSR( `CSR_JVT_ADDR, jvt ) + `RVVI_SET_CSR( `CSR_MSTATUS_ADDR, mstatus ) + `RVVI_SET_CSR( `CSR_MISA_ADDR, misa ) + `RVVI_SET_CSR( `CSR_MIE_ADDR, mie ) + `RVVI_SET_CSR( `CSR_MTVEC_ADDR, mtvec ) + `RVVI_SET_CSR( `CSR_MCOUNTEREN_ADDR, mcounteren ) + `RVVI_SET_CSR( `CSR_MENVCFG_ADDR, menvcfg ) + `RVVI_SET_CSR( `CSR_MSTATEEN0_ADDR, mstateen0 ) + `RVVI_SET_CSR( `CSR_MSTATEEN1_ADDR, mstateen1 ) + `RVVI_SET_CSR( `CSR_MSTATEEN2_ADDR, mstateen2 ) + `RVVI_SET_CSR( `CSR_MSTATEEN3_ADDR, mstateen3 ) + + `RVVI_SET_CSR( `CSR_MSTATUSH_ADDR, mstatush ) + `RVVI_SET_CSR( `CSR_MENVCFGH_ADDR, menvcfgh ) + `RVVI_SET_CSR( `CSR_MSTATEEN0H_ADDR, mstateen0h ) + `RVVI_SET_CSR( `CSR_MSTATEEN1H_ADDR, mstateen1h ) + `RVVI_SET_CSR( `CSR_MSTATEEN2H_ADDR, mstateen2h ) + `RVVI_SET_CSR( `CSR_MSTATEEN3H_ADDR, mstateen3h ) + `RVVI_SET_CSR( `CSR_MCOUNTINHIBIT_ADDR, mcountinhibit ) + + `RVVI_SET_CSR( `CSR_MHPMEVENT3_ADDR, mhpmevent3 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT4_ADDR, mhpmevent4 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT5_ADDR, mhpmevent5 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT6_ADDR, mhpmevent6 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT7_ADDR, mhpmevent7 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT8_ADDR, mhpmevent8 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT9_ADDR, mhpmevent9 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT10_ADDR, mhpmevent10 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT11_ADDR, mhpmevent11 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT12_ADDR, mhpmevent12 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT13_ADDR, mhpmevent13 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT14_ADDR, mhpmevent14 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT15_ADDR, mhpmevent15 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT16_ADDR, mhpmevent16 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT17_ADDR, mhpmevent17 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT18_ADDR, mhpmevent18 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT19_ADDR, mhpmevent19 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT20_ADDR, mhpmevent20 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT21_ADDR, mhpmevent21 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT22_ADDR, mhpmevent22 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT23_ADDR, mhpmevent23 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT24_ADDR, mhpmevent24 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT25_ADDR, mhpmevent25 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT26_ADDR, mhpmevent26 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT27_ADDR, mhpmevent27 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT28_ADDR, mhpmevent28 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT29_ADDR, mhpmevent29 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT30_ADDR, mhpmevent30 ) + `RVVI_SET_CSR( `CSR_MHPMEVENT31_ADDR, mhpmevent31 ) + + `RVVI_SET_CSR( `CSR_MSCRATCH_ADDR, mscratch ) + `RVVI_SET_CSR( `CSR_MEPC_ADDR, mepc ) + `RVVI_SET_CSR( `CSR_MCAUSE_ADDR, mcause ) + `RVVI_SET_CSR( `CSR_MTVAL_ADDR, mtval ) + `RVVI_SET_CSR( `CSR_MIP_ADDR, mip ) + + `RVVI_SET_CSR( `CSR_PMPCFG0_ADDR, pmpcfg0 ) + `RVVI_SET_CSR( `CSR_PMPCFG1_ADDR, pmpcfg1 ) + `RVVI_SET_CSR( `CSR_PMPCFG2_ADDR, pmpcfg2 ) + `RVVI_SET_CSR( `CSR_PMPCFG3_ADDR, pmpcfg3 ) + `RVVI_SET_CSR( `CSR_PMPCFG4_ADDR, pmpcfg4 ) + `RVVI_SET_CSR( `CSR_PMPCFG5_ADDR, pmpcfg5 ) + `RVVI_SET_CSR( `CSR_PMPCFG6_ADDR, pmpcfg6 ) + `RVVI_SET_CSR( `CSR_PMPCFG7_ADDR, pmpcfg7 ) + `RVVI_SET_CSR( `CSR_PMPCFG8_ADDR, pmpcfg8 ) + `RVVI_SET_CSR( `CSR_PMPCFG9_ADDR, pmpcfg9 ) + `RVVI_SET_CSR( `CSR_PMPCFG10_ADDR, pmpcfg10 ) + `RVVI_SET_CSR( `CSR_PMPCFG11_ADDR, pmpcfg11 ) + `RVVI_SET_CSR( `CSR_PMPCFG12_ADDR, pmpcfg12 ) + `RVVI_SET_CSR( `CSR_PMPCFG13_ADDR, pmpcfg13 ) + `RVVI_SET_CSR( `CSR_PMPCFG14_ADDR, pmpcfg14 ) + `RVVI_SET_CSR( `CSR_PMPCFG15_ADDR, pmpcfg15 ) + + `RVVI_SET_CSR( `CSR_PMPADDR0_ADDR, pmpaddr0 ) + `RVVI_SET_CSR( `CSR_PMPADDR1_ADDR, pmpaddr1 ) + `RVVI_SET_CSR( `CSR_PMPADDR2_ADDR, pmpaddr2 ) + `RVVI_SET_CSR( `CSR_PMPADDR3_ADDR, pmpaddr3 ) + `RVVI_SET_CSR( `CSR_PMPADDR4_ADDR, pmpaddr4 ) + `RVVI_SET_CSR( `CSR_PMPADDR5_ADDR, pmpaddr5 ) + `RVVI_SET_CSR( `CSR_PMPADDR6_ADDR, pmpaddr6 ) + `RVVI_SET_CSR( `CSR_PMPADDR7_ADDR, pmpaddr7 ) + `RVVI_SET_CSR( `CSR_PMPADDR8_ADDR, pmpaddr8 ) + `RVVI_SET_CSR( `CSR_PMPADDR9_ADDR, pmpaddr9 ) + `RVVI_SET_CSR( `CSR_PMPADDR10_ADDR, pmpaddr10 ) + `RVVI_SET_CSR( `CSR_PMPADDR11_ADDR, pmpaddr11 ) + `RVVI_SET_CSR( `CSR_PMPADDR12_ADDR, pmpaddr12 ) + `RVVI_SET_CSR( `CSR_PMPADDR13_ADDR, pmpaddr13 ) + `RVVI_SET_CSR( `CSR_PMPADDR14_ADDR, pmpaddr14 ) + `RVVI_SET_CSR( `CSR_PMPADDR15_ADDR, pmpaddr15 ) + `RVVI_SET_CSR( `CSR_PMPADDR16_ADDR, pmpaddr16 ) + `RVVI_SET_CSR( `CSR_PMPADDR17_ADDR, pmpaddr17 ) + `RVVI_SET_CSR( `CSR_PMPADDR18_ADDR, pmpaddr18 ) + `RVVI_SET_CSR( `CSR_PMPADDR19_ADDR, pmpaddr19 ) + `RVVI_SET_CSR( `CSR_PMPADDR20_ADDR, pmpaddr20 ) + `RVVI_SET_CSR( `CSR_PMPADDR21_ADDR, pmpaddr21 ) + `RVVI_SET_CSR( `CSR_PMPADDR22_ADDR, pmpaddr22 ) + `RVVI_SET_CSR( `CSR_PMPADDR23_ADDR, pmpaddr23 ) + `RVVI_SET_CSR( `CSR_PMPADDR24_ADDR, pmpaddr24 ) + `RVVI_SET_CSR( `CSR_PMPADDR25_ADDR, pmpaddr25 ) + `RVVI_SET_CSR( `CSR_PMPADDR26_ADDR, pmpaddr26 ) + `RVVI_SET_CSR( `CSR_PMPADDR27_ADDR, pmpaddr27 ) + `RVVI_SET_CSR( `CSR_PMPADDR28_ADDR, pmpaddr28 ) + `RVVI_SET_CSR( `CSR_PMPADDR29_ADDR, pmpaddr29 ) + `RVVI_SET_CSR( `CSR_PMPADDR30_ADDR, pmpaddr30 ) + `RVVI_SET_CSR( `CSR_PMPADDR31_ADDR, pmpaddr31 ) + `RVVI_SET_CSR( `CSR_PMPADDR32_ADDR, pmpaddr32 ) + `RVVI_SET_CSR( `CSR_PMPADDR33_ADDR, pmpaddr33 ) + `RVVI_SET_CSR( `CSR_PMPADDR34_ADDR, pmpaddr34 ) + `RVVI_SET_CSR( `CSR_PMPADDR35_ADDR, pmpaddr35 ) + `RVVI_SET_CSR( `CSR_PMPADDR36_ADDR, pmpaddr36 ) + `RVVI_SET_CSR( `CSR_PMPADDR37_ADDR, pmpaddr37 ) + `RVVI_SET_CSR( `CSR_PMPADDR38_ADDR, pmpaddr38 ) + `RVVI_SET_CSR( `CSR_PMPADDR39_ADDR, pmpaddr39 ) + `RVVI_SET_CSR( `CSR_PMPADDR40_ADDR, pmpaddr40 ) + `RVVI_SET_CSR( `CSR_PMPADDR41_ADDR, pmpaddr41 ) + `RVVI_SET_CSR( `CSR_PMPADDR42_ADDR, pmpaddr42 ) + `RVVI_SET_CSR( `CSR_PMPADDR43_ADDR, pmpaddr43 ) + `RVVI_SET_CSR( `CSR_PMPADDR44_ADDR, pmpaddr44 ) + `RVVI_SET_CSR( `CSR_PMPADDR45_ADDR, pmpaddr45 ) + `RVVI_SET_CSR( `CSR_PMPADDR46_ADDR, pmpaddr46 ) + `RVVI_SET_CSR( `CSR_PMPADDR47_ADDR, pmpaddr47 ) + `RVVI_SET_CSR( `CSR_PMPADDR48_ADDR, pmpaddr48 ) + `RVVI_SET_CSR( `CSR_PMPADDR49_ADDR, pmpaddr49 ) + `RVVI_SET_CSR( `CSR_PMPADDR50_ADDR, pmpaddr50 ) + `RVVI_SET_CSR( `CSR_PMPADDR51_ADDR, pmpaddr51 ) + `RVVI_SET_CSR( `CSR_PMPADDR52_ADDR, pmpaddr52 ) + `RVVI_SET_CSR( `CSR_PMPADDR53_ADDR, pmpaddr53 ) + `RVVI_SET_CSR( `CSR_PMPADDR54_ADDR, pmpaddr54 ) + `RVVI_SET_CSR( `CSR_PMPADDR55_ADDR, pmpaddr55 ) + `RVVI_SET_CSR( `CSR_PMPADDR56_ADDR, pmpaddr56 ) + `RVVI_SET_CSR( `CSR_PMPADDR57_ADDR, pmpaddr57 ) + `RVVI_SET_CSR( `CSR_PMPADDR58_ADDR, pmpaddr58 ) + `RVVI_SET_CSR( `CSR_PMPADDR59_ADDR, pmpaddr59 ) + `RVVI_SET_CSR( `CSR_PMPADDR60_ADDR, pmpaddr60 ) + `RVVI_SET_CSR( `CSR_PMPADDR61_ADDR, pmpaddr61 ) + `RVVI_SET_CSR( `CSR_PMPADDR62_ADDR, pmpaddr62 ) + `RVVI_SET_CSR( `CSR_PMPADDR63_ADDR, pmpaddr63 ) + + `RVVI_SET_CSR( `CSR_MSECCFG_ADDR, mseccfg ) + `RVVI_SET_CSR( `CSR_MSECCFGH_ADDR, mseccfgh ) + + if (CORE_PARAM_DBG_NUM_TRIGGERS > 0) begin + `RVVI_SET_CSR( `CSR_TSELECT_ADDR, tselect ) + `RVVI_SET_CSR( `CSR_TDATA1_ADDR, tdata1 ) + `RVVI_SET_CSR( `CSR_TDATA2_ADDR, tdata2 ) + `RVVI_SET_CSR( `CSR_TINFO_ADDR, tinfo ) + end + + `RVVI_SET_CSR( `CSR_DCSR_ADDR, dcsr ) + `RVVI_SET_CSR( `CSR_DPC_ADDR, dpc ) + `RVVI_SET_CSR( `CSR_DSCRATCH0_ADDR, dscratch0 ) + `RVVI_SET_CSR( `CSR_DSCRATCH1_ADDR, dscratch1 ) + + `RVVI_SET_CSR( `CSR_MHPMCOUNTER3_ADDR, mhpmcounter3 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER4_ADDR, mhpmcounter4 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER5_ADDR, mhpmcounter5 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER6_ADDR, mhpmcounter6 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER7_ADDR, mhpmcounter7 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER8_ADDR, mhpmcounter8 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER9_ADDR, mhpmcounter9 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER10_ADDR, mhpmcounter10 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER11_ADDR, mhpmcounter11 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER12_ADDR, mhpmcounter12 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER13_ADDR, mhpmcounter13 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER14_ADDR, mhpmcounter14 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER15_ADDR, mhpmcounter15 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER16_ADDR, mhpmcounter16 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER17_ADDR, mhpmcounter17 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER18_ADDR, mhpmcounter18 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER19_ADDR, mhpmcounter19 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER20_ADDR, mhpmcounter20 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER21_ADDR, mhpmcounter21 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER22_ADDR, mhpmcounter22 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER23_ADDR, mhpmcounter23 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER24_ADDR, mhpmcounter24 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER25_ADDR, mhpmcounter25 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER26_ADDR, mhpmcounter26 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER27_ADDR, mhpmcounter27 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER28_ADDR, mhpmcounter28 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER29_ADDR, mhpmcounter29 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER30_ADDR, mhpmcounter30 ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER31_ADDR, mhpmcounter31 ) + + `RVVI_SET_CSR( `CSR_MCYCLE_ADDR, mcycle ) + `RVVI_SET_CSR( `CSR_MINSTRET_ADDR, minstret ) + + `RVVI_SET_CSR( `CSR_MHPMCOUNTER3H_ADDR, mhpmcounter3h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER4H_ADDR, mhpmcounter4h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER5H_ADDR, mhpmcounter5h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER6H_ADDR, mhpmcounter6h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER7H_ADDR, mhpmcounter7h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER8H_ADDR, mhpmcounter8h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER9H_ADDR, mhpmcounter9h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER10H_ADDR,mhpmcounter10h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER11H_ADDR,mhpmcounter11h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER12H_ADDR,mhpmcounter12h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER13H_ADDR,mhpmcounter13h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER14H_ADDR,mhpmcounter14h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER15H_ADDR,mhpmcounter15h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER16H_ADDR,mhpmcounter16h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER17H_ADDR,mhpmcounter17h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER18H_ADDR,mhpmcounter18h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER19H_ADDR,mhpmcounter19h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER20H_ADDR,mhpmcounter20h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER21H_ADDR,mhpmcounter21h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER22H_ADDR,mhpmcounter22h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER23H_ADDR,mhpmcounter23h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER24H_ADDR,mhpmcounter24h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER25H_ADDR,mhpmcounter25h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER26H_ADDR,mhpmcounter26h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER27H_ADDR,mhpmcounter27h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER28H_ADDR,mhpmcounter28h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER29H_ADDR,mhpmcounter29h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER30H_ADDR,mhpmcounter30h ) + `RVVI_SET_CSR( `CSR_MHPMCOUNTER31H_ADDR,mhpmcounter31h ) + + `RVVI_SET_CSR( `CSR_CPUCTRL_ADDR, cpuctrl ) + `RVVI_SET_CSR( `CSR_SECURESEED0_ADDR, secureseed0 ) + `RVVI_SET_CSR( `CSR_SECURESEED1_ADDR, secureseed1 ) + `RVVI_SET_CSR( `CSR_SECURESEED2_ADDR, secureseed2 ) + + `RVVI_SET_CSR( `CSR_MVENDORID_ADDR, mvendorid ) + `RVVI_SET_CSR( `CSR_MARCHID_ADDR, marchid ) + `RVVI_SET_CSR( `CSR_MIMPID_ADDR, mimpid ) + `RVVI_SET_CSR( `CSR_MHARTID_ADDR, mhartid ) + `RVVI_SET_CSR( `CSR_MCONFIGPTR_ADDR, mconfigptr ) + + `RVVI_SET_CSR( `CSR_MCYCLEH_ADDR, mcycleh ) + `RVVI_SET_CSR( `CSR_MINSTRETH_ADDR, minstreth ) + + if (CORE_PARAM_CLIC == 1) begin + `RVVI_SET_CSR( `CSR_MTVT_ADDR, mtvt ) + `RVVI_SET_CSR( `CSR_MNXTI_ADDR, mnxti ) + `RVVI_SET_CSR( `CSR_MINTSTATUS_ADDR, mintstatus ) + `RVVI_SET_CSR( `CSR_MINTTHRESH_ADDR, mintthresh ) + `RVVI_SET_CSR( `CSR_MSCRATCHCSW_ADDR, mscratchcsw ) + `RVVI_SET_CSR( `CSR_MSCRATCHCSWL_ADDR,mscratchcswl ) + end + + + //////////////////////////////////////////////////////////////////////////// + // Assign the RVVI GPR registers + //////////////////////////////////////////////////////////////////////////// + bit [31:0] XREG[32]; + genvar gi; + generate + for(gi=0; gi<32; gi++) + assign rvvi.x_wdata[0][0][gi] = XREG[gi]; + endgenerate + + always_comb begin + int i; + if (|`RVFI_IF.rvfi_gpr_wmask[31:1] && `RVFI_IF.rvfi_valid) begin + for (i=1; i<32; i++) begin + if (`RVFI_IF.rvfi_gpr_wmask[i]) begin + XREG[i] = `RVFI_IF.rvfi_gpr_wdata[i*XLEN+:XLEN]; + end + else begin + XREG[i] = 32'h0; + end + end + end + end + + assign rvvi.x_wb[0][0] = `RVFI_IF.rvfi_gpr_wmask; + + //////////////////////////////////////////////////////////////////////////// + // RESET + //////////////////////////////////////////////////////////////////////////// + always @`DUT_PATH.rst_ni begin + void'(rvvi.net_push("reset", !`DUT_PATH.rst_ni)); + end + + //////////////////////////////////////////////////////////////////////////// + // DEBUG REQUESTS, + //////////////////////////////////////////////////////////////////////////// + logic debug_req_i; + assign debug_req_i = `DUT_PATH.debug_req_i; + always @(debug_req_i) begin + void'(rvvi.net_push("haltreq", debug_req_i)); + end + + //////////////////////////////////////////////////////////////////////////// + // WFE REQUESTS + //////////////////////////////////////////////////////////////////////////// + logic wu_wfe_i; + assign wu_wfe_i = `DUT_PATH.wu_wfe_i; + always @(wu_wfe_i) begin + void'(rvvi.net_push("wu_wfe_i", wu_wfe_i)); + end + + //////////////////////////////////////////////////////////////////////////// + // INTERRUPTS + //////////////////////////////////////////////////////////////////////////// + if (CORE_PARAM_CLIC == 0) begin + `RVVI_WRITE_IRQ(MSWInterrupt, 3) + `RVVI_WRITE_IRQ(MTimerInterrupt, 7) + `RVVI_WRITE_IRQ(MExternalInterrupt, 11) + `RVVI_WRITE_IRQ(LocalInterrupt0, 16) + `RVVI_WRITE_IRQ(LocalInterrupt1, 17) + `RVVI_WRITE_IRQ(LocalInterrupt2, 18) + `RVVI_WRITE_IRQ(LocalInterrupt3, 19) + `RVVI_WRITE_IRQ(LocalInterrupt4, 20) + `RVVI_WRITE_IRQ(LocalInterrupt5, 21) + `RVVI_WRITE_IRQ(LocalInterrupt6, 22) + `RVVI_WRITE_IRQ(LocalInterrupt7, 23) + `RVVI_WRITE_IRQ(LocalInterrupt8, 24) + `RVVI_WRITE_IRQ(LocalInterrupt9, 25) + `RVVI_WRITE_IRQ(LocalInterrupt10, 26) + `RVVI_WRITE_IRQ(LocalInterrupt11, 27) + `RVVI_WRITE_IRQ(LocalInterrupt12, 28) + `RVVI_WRITE_IRQ(LocalInterrupt13, 29) + `RVVI_WRITE_IRQ(LocalInterrupt14, 30) + `RVVI_WRITE_IRQ(LocalInterrupt15, 31) + end else begin + logic clic_irq; + logic [10:0] clic_irq_id; + logic [7:0] clic_irq_level; + logic [1:0] clic_irq_priv; + logic clic_irq_shv; + + assign clic_irq = `DUT_PATH.clic_irq_i; + assign clic_irq_id = `DUT_PATH.clic_irq_id_i; + assign clic_irq_level = `DUT_PATH.clic_irq_level_i; + assign clic_irq_priv = `DUT_PATH.clic_irq_priv_i; + assign clic_irq_shv = `DUT_PATH.clic_irq_shv_i; + always @(clic_irq, clic_irq_id, clic_irq_level, clic_irq_priv, clic_irq_shv) begin + void'(rvvi.net_push("irq_i", clic_irq)); + void'(rvvi.net_push("irq_id_i", clic_irq_id)); + void'(rvvi.net_push("irq_lev_i", clic_irq_level)); + void'(rvvi.net_push("irq_sec_i", clic_irq_priv)); + void'(rvvi.net_push("irq_shv_i", clic_irq_shv)); + end + end + + //////////////////////////////////////////////////////////////////////////// + // RVFI Monitor: pass NMI Load/Store and Fetch to the ref + //////////////////////////////////////////////////////////////////////////// + bit InstructionBusFault; + bit DataBusFault; + int DataBusFaultCause; + int order; + + always_comb begin: Monitor_RVFI + bit trap_trap; + bit trap_exception; + bit trap_debug; + bit [5:0] trap_exception_cause; + bit [2:0] trap_debug_cause; + bit [1:0] trap_cause_type; + + bit intr_intr; + bit intr_exception; + bit intr_interrupt; + bit [10:0] intr_cause; + + bit nmi_pending; + bit nmi_load_store; + + bit nmi_c1, nmi_c2; + + bit ifault; + + if (`RVFI_IF.rvfi_valid && (order != `RVFI_IF.rvfi_order)) begin + order = `RVFI_IF.rvfi_order; + + trap_trap = `RVFI_IF.rvfi_trap.trap; + trap_exception = `RVFI_IF.rvfi_trap.exception; + trap_debug = `RVFI_IF.rvfi_trap.debug; + trap_exception_cause = `RVFI_IF.rvfi_trap.exception_cause; + trap_debug_cause = `RVFI_IF.rvfi_trap.debug_cause; + trap_cause_type = `RVFI_IF.rvfi_trap.cause_type; + + intr_intr = `RVFI_IF.rvfi_intr.intr; + intr_exception = `RVFI_IF.rvfi_intr.exception; + intr_interrupt = `RVFI_IF.rvfi_intr.interrupt; + intr_cause = `RVFI_IF.rvfi_intr.cause; + + nmi_pending = `RVFI_IF.rvfi_nmip[0]; + nmi_load_store = `RVFI_IF.rvfi_nmip[1]; + + // Only in debug Mode + `uvm_info(info_tag, $sformatf("RVFI Valid %t", $time), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("valid = %X", `RVFI_IF.rvfi_valid), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("order = %0d", `RVFI_IF.rvfi_order), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("insn = %X", `RVFI_IF.rvfi_insn), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("trap trap=%X exception=%X debug=%X exception_cause=0x%X debug_cause=0x%X cause_type=0x%X", + trap_trap, trap_exception, trap_debug, trap_exception_cause, trap_debug_cause, trap_cause_type), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("halt = %X", `RVFI_IF.rvfi_halt), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("dbg = %X", `RVFI_IF.rvfi_dbg), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("dbg_mode = %X", `RVFI_IF.rvfi_dbg_mode), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("nmip nmi=%X nmi_load0_store1=%X", `RVFI_IF.rvfi_nmip[0], `RVFI_IF.rvfi_nmip[1]), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("intr intr=%X exception=%X interrupt=%X cause=0x%X", + intr_intr, intr_exception, intr_interrupt, intr_cause), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("mode = %X", `RVFI_IF.rvfi_mode), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("ixl = %X", `RVFI_IF.rvfi_ixl), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("pc_rdata = %X", `RVFI_IF.rvfi_pc_rdata), UVM_DEBUG) + `uvm_info(info_tag, $sformatf("pc_wdata = %X", `RVFI_IF.rvfi_pc_wdata), UVM_DEBUG) + + // + // Load Store - NMI + // + nmi_c1 = (intr_intr && intr_interrupt && ((intr_cause==1024 || intr_cause==1025))); + nmi_c2 = nmi_pending; + + if (nmi_c1 || nmi_c2) begin + // Load / Store + if (DataBusFaultCause != intr_cause) begin + void'(rvvi.net_push("nmi_cause", intr_cause)); // Load Error = 1024, Store Error = 1025 + end + if (!DataBusFault) begin + void'(rvvi.net_push("nmi", 1)); + end + DataBusFault = 1; + DataBusFaultCause = intr_cause; + end else begin + if (DataBusFault) begin + void'(rvvi.net_push("nmi", 0)); + end + DataBusFault = 0; + end + + // + // Fetch - Exception on TRAP + // + if (trap_trap && trap_exception && trap_exception_cause==24) begin + if (!InstructionBusFault) begin + void'(rvvi.net_push("InstructionBusFault", 1)); + end + InstructionBusFault = 1; + end else begin + if (InstructionBusFault) begin + void'(rvvi.net_push("InstructionBusFault", 0)); + end + InstructionBusFault = 0; + end + + end + end: Monitor_RVFI + +endmodule : uvmt_cv32e40s_imperas_dv_wrap + +interface uvmt_imperas_dv_if_t; + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import uvme_cv32e40s_pkg::*; + import rvviApiPkg::*; + + string info_tag = "ImperasDV_if"; + + task ref_init; + string test_program_elf; + logic [31:0] hart_id; + + // Select processor name + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "CVE4S")); + // Worst case propagation of events 4 retirements (actually 3 observed) + void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 4)); + // Redirect stdout to parent systemverilog simulator + void'(rvviRefConfigSetInt(IDV_CONFIG_REDIRECT_STDOUT, RVVI_TRUE)); + + // Initialize REF and load the test-program into it's memory (do this before initializing the DUT). + // TODO: is this the best place for this? + if (!rvviVersionCheck(RVVI_API_VERSION)) begin + `uvm_fatal(info_tag, $sformatf("Expecting RVVI API version %0d.", RVVI_API_VERSION)) + end + // Test-program must have been compiled before we got here... + if ($value$plusargs("elf_file=%s", test_program_elf)) begin + `uvm_info(info_tag, $sformatf("ImperasDV loading test_program %0s", test_program_elf), UVM_LOW) + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "openhwgroup.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "CV32E40S_DEV")); + if (!rvviRefInit(test_program_elf)) begin + `uvm_fatal(info_tag, "rvviRefInit failed") + end + else begin + `uvm_info(info_tag, "rvviRefInit() succeed", UVM_LOW) + end + end + else begin + `uvm_fatal(info_tag, "No test_program specified") + end + + hart_id = 32'h0000_0000; + + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MCYCLE_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MCYCLEH_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MINSTRET_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MINSTRETH_ADDR )); + + // cannot predict this register due to latency between + // pending and taken + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MIP_ADDR )); + + // TODO: deal with the MHPMCOUNTER CSRs properly. + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT3_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER4_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER4H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT4_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER5_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER5H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT5_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER6_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER6H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT6_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER7_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER7H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT7_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER8_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER8H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT8_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER9_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER9H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT9_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER10_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER10H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT10_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER11_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER11H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT11_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER12_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER12H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT12_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER13_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER13H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT13_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER14_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER14H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT14_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER15_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER15H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT15_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER16_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER16H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT16_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER17_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER17H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT17_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER18_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER18H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT18_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER19_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER19H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT19_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER20_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER20H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT20_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER21_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER21H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT21_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER22_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER22H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT22_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER23_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER23H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT23_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER24_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER24H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT24_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER25_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER25H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT25_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER26_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER26H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT26_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER27_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER27H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT27_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER28_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER28H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT28_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER29_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER29H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT29_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER30_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER30H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT30_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER31_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER31H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT31_ADDR )); + + // Mask out pending bits, due to interrupts showing as pending + // and enabled but not taken immediately due to instructions + // in-flight, eg Load/Store + rvviRefCsrCompareEnable(hart_id, `CSR_MIP_ADDR, RVVI_FALSE); + void'(rvviRefCsrSetVolatileMask(hart_id, `CSR_DCSR_ADDR, 'h8)); + + // TODO: Set these as volatiles as a temporary fix until + // we have a proper fix implemented in the ISS + if (CORE_PARAM_CLIC == 1) begin + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MNXTI_ADDR)); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MSCRATCHCSW_ADDR)); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MSCRATCHCSWL_ADDR)); + end + + // define asynchronous grouping + // Interrupts + if (CORE_PARAM_CLIC == 0) begin + rvviRefNetGroupSet(rvviRefNetIndexGet("MSWInterrupt"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("MTimerInterrupt"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("MExternalInterrupt"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt0"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt1"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt2"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt3"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt4"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt5"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt6"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt7"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt8"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt9"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt10"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt11"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt12"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt13"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt14"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("LocalInterrupt15"), 1); + end else begin + rvviRefNetGroupSet(rvviRefNetIndexGet("irq_i"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("irq_id_i"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("irq_lev_i"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("irq_sec_i"), 1); + rvviRefNetGroupSet(rvviRefNetIndexGet("irq_shv_i"), 1); + end + + rvviRefNetGroupSet(rvviRefNetIndexGet("InstructionBusFault"), 2); + + // NMI + rvviRefNetGroupSet(rvviRefNetIndexGet("nmi"), 3); + rvviRefNetGroupSet(rvviRefNetIndexGet("nmi_cause"), 3); + + // Debug + rvviRefNetGroupSet(rvviRefNetIndexGet("haltreq"), 4); + + // Add IO regions of memory + // According to silabs this range is 0x0080_0000 to 0x0080_0FFF + void'(rvviRefMemorySetVolatile('h00800000, 'h00800FFF)); //TODO: deal with int return value + + `uvm_info(info_tag, "ref_init() complete", UVM_LOW) + endtask // ref_init +endinterface : uvmt_imperas_dv_if_t + +`endif // USE_IMPERASDV + +`endif // __UVMT_CV32E40S_IMPERAS_DV_WRAP_SV__ + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_integration_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_integration_assert.sv index 533904ad6e..2b7f0c2bb3 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_integration_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_integration_assert.sv @@ -21,23 +21,37 @@ module uvmt_cv32e40s_integration_assert import uvm_pkg::*; + import uvma_rvfi_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import isa_decoder_pkg::*; ( input clk_i, input rst_ni, + uvma_rvfi_instr_if_t rvfi_if, + input fetch_enable_i, input [31:0] boot_addr_i, input [31:0] dm_exception_addr_i, input [31:0] dm_halt_addr_i, input [31:0] mtvec_addr_i, - input [31:0] nmi_addr_i + + input alert_major_o, + input scan_cg_en_i, + + uvmt_cv32e40s_support_logic_module_o_if_t support_if ); default clocking @(posedge clk_i); endclocking default disable iff !rst_ni; + string info_tag = "CV32E40S_INTEGRATION_ASSERT"; + + // Helper Logic + logic fetch_enable_i_sticky; always @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin @@ -66,9 +80,6 @@ module uvmt_cv32e40s_integration_assert a_stable_mtvecaddr : assert property (p_stable_addr(mtvec_addr_i)) else `uvm_error(info_tag, "mtvec_addr_i changed after fetch_enable_i"); - a_stable_nmiaddr : assert property (p_stable_addr(nmi_addr_i)) - else `uvm_error(info_tag, "nmi_addr_i changed after fetch_enable_i"); - // Check that addresses are word-aligned @@ -85,9 +96,69 @@ module uvmt_cv32e40s_integration_assert a_aligned_dmhaltaddr : assert property (p_aligned_addr(dm_halt_addr_i)) else `uvm_error(info_tag, "dm_halt_addr_i not word-aligned"); - //a_aligned_mtvecaddr is not required by the user manual as per now - a_aligned_nmiaddr : assert property (p_aligned_addr(nmi_addr_i)) - else `uvm_error(info_tag, "nmi_addr_i not word-aligned"); + // No major alerts in normal operation + + a_no_alert_major: assert property ( + !alert_major_o + // Note: Do not assume this property + ) else `uvm_error(info_tag, "major alert should not happen in normal operation"); + + + // No scan testing in normal operation + + a_no_scan_cg: assert property ( + !scan_cg_en_i + ) else `uvm_error(info_tag, "scan test should be disabled in normal operation"); + + //if m_ext = M_NONE, all mul and div instructions should trap + if (CORE_PARAM_M_EXT == cv32e40s_pkg::M_NONE) begin: gen_m_none_assert + a_m_none_mul_trap: assert property( + rvfi_if.rvfi_valid && + rvfi_if.instr_asm.instr inside{CLMUL, CLMULH, CLMULR, MUL, MULH, MULHSU, MULHU, C_MUL} + |-> + rvfi_if.rvfi_trap.trap + ) else `uvm_error(info_tag, "Multiply instruction is not illegal when M_EXT = M_NONE"); + + a_m_none_div_trap: assert property( + rvfi_if.rvfi_valid && + rvfi_if.instr_asm.instr inside{DIV, DIVU, REM, REMU} + |-> + rvfi_if.rvfi_trap.trap + ) else `uvm_error(info_tag, "Divide instruction is not illegal when M_EXT = M_NONE"); + + end: gen_m_none_assert + + + // Maximum Outstanding OBI Transactions + + a_maximum_outstanding_instr: assert property ( + support_if.instr_bus_v_addr_ph_cnt inside {0, 1, 2} + ) else `uvm_error(info_tag, "More than 2 outstanding OBI transactions"); + + a_maximum_outstanding_data: assert property ( + support_if.data_bus_v_addr_ph_cnt inside {0, 1, 2} + ) else `uvm_error(info_tag, "More than 2 outstanding OBI transactions"); + + covergroup cg_outstanding @(posedge clk_i); + option.per_instance = 1; + + cp_instr: coverpoint support_if.instr_bus_v_addr_ph_cnt { + bins zero = {0}; + bins one = {1}; + bins two = {2}; + } + + cp_data: coverpoint support_if.data_bus_v_addr_ph_cnt { + bins zero = {0}; + bins one = {1}; + bins two = {2}; + } + + x_instr_data: cross cp_instr, cp_data; + endgroup + + cg_outstanding outstanding_cg = new; + endmodule : uvmt_cv32e40s_integration_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_interrupt_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_interrupt_assert.sv index df7c439a83..ae977dc8f8 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_interrupt_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_interrupt_assert.sv @@ -15,57 +15,87 @@ // limitations under the License. // + +`default_nettype none + + module uvmt_cv32e40s_interrupt_assert import uvm_pkg::*; import cv32e40s_pkg::*; ( - input clk, // Gated clock - input clk_i, // Free-running core clock - input rst_ni, + input wire clk, // Gated clock + input wire clk_i, // Free-running core clock + input wire rst_ni, - // Core inputs - input fetch_enable_i, // external core fetch enable + // Core input wires + input wire fetch_enable_i, // external core fetch enable // External interrupt interface - input [31:0] irq_i, - input irq_ack_o, - input [4:0] irq_id_o, + input wire [31:0] irq_i, + input wire irq_ack_o, + input wire [9:0] irq_id_o, // External debug req (for WFI modeling) - input debug_req_i, - input debug_mode_q, + input wire debug_req_i, + input wire debug_mode_q, // CSR Interface - input [5:0] mcause_n, // mcause_n[5]: interrupt, mcause_n[4]: vector - input [31:0] mip, // machine interrupt pending - input [31:0] mie_q, // machine interrupt enable - input mstatus_mie, // machine mode interrupt enable - input [1:0] mtvec_mode_q, // machine mode interrupt vector mode - - // Instruction fetch stage - input if_stage_instr_req_o, - input if_stage_instr_rvalid_i, // Instruction word is valid - input [31:0] if_stage_instr_rdata_i, // Instruction word data - input [ 1:0] alignbuf_outstanding, // Alignment buffer's number of outstanding transactions - - // Instruction EX stage - input ex_stage_instr_valid, // EX pipeline stage has valid input - - // Instruction WB stage (determines executed instructions) - input wb_stage_instr_valid_i, // instruction word is valid - input [31:0] wb_stage_instr_rdata_i, // Instruction word data - input wb_stage_instr_err_i, // OBI "err" - input mpu_status_e wb_stage_instr_mpu_status, // MPU read/write errors + input wire [5:0] mcause_n, // mcause_n[5]: interrupt, mcause_n[4]: vector + input wire [31:0] mip, // machine interrupt pending + input wire [31:0] mie_q, // machine interrupt enable + input wire mstatus_mie, // machine mode interrupt enable + input wire mstatus_tw, // "timeout wait" + input wire [1:0] mtvec_mode_q, // machine mode interrupt vector mode + input wire dcsr_step, + + // IF stage + input wire if_stage_instr_req_o, + input wire if_stage_instr_rvalid_i, // Instruction word is valid + input wire [31:0] if_stage_instr_rdata_i, // Instruction word data + input wire [ 1:0] alignbuf_outstanding, // Alignment buffer's number of outstanding transactions + + // EX stage + input wire ex_stage_instr_valid, // EX pipeline stage has valid input + + // WB stage (determines executed instructions) + input wire wb_stage_instr_err_i, // OBI "err" + input wire wb_stage_instr_valid_i, // instruction word is valid + input wire [31:0] wb_stage_instr_rdata_i, // Instruction word data + input wire mpu_status_e wb_stage_instr_mpu_status, // MPU read/write errors + input wire wb_kill, + input wire wb_trigger, + input wire wb_valid, // Load-store unit status - input lsu_busy, + input wire lsu_busy, + + // Privilege + input wire privlvl_t priv_lvl, // Determine whether to cancel instruction if branch taken - input branch_taken_ex, + input wire branch_taken_ex, + + // WFI/WFE Interface + input wire core_sleep_o, + input wire wu_wfe_i, + + // OBI + input wire mpu_instr_rvalid, + uvma_obi_memory_if_t obi_instr_if, + uvma_obi_memory_if_t obi_data_if, + + // Writebuffer + input wire write_buffer_state_e writebufstate, - // WFI Interface - input core_sleep_o + // RVFI + uvma_rvfi_instr_if_t rvfi, + + // NMI + input wire pending_nmi, + + // Support Interface + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if ); // --------------------------------------------------------------------------- @@ -75,6 +105,7 @@ module uvmt_cv32e40s_interrupt_assert localparam VALID_IRQ_MASK = 32'hffff_0888; // Valid external interrupt signals localparam WFI_INSTR_DATA = 32'h10500073; + localparam WFE_INSTR_DATA = 32'h8C000073; localparam WFI_TO_CORE_SLEEP_LATENCY = 2; localparam WFI_WAKEUP_LATENCY = 40; @@ -87,8 +118,6 @@ module uvmt_cv32e40s_interrupt_assert wire [31:0] pending_enabled_irq; wire [31:0] pending_enabled_irq_q; - reg in_wfi; // Local model of WFI state of core - reg[31:0] irq_q; reg[31:0] next_irq; @@ -100,6 +129,8 @@ module uvmt_cv32e40s_interrupt_assert reg[31:0] expected_irq; logic expected_irq_ack; + wire is_mmode_mstatusmie = (priv_lvl == PRIV_LVL_M) && mstatus_mie; + wire is_umode_miemip = (priv_lvl == PRIV_LVL_U) && (mie_q & mip); reg[31:0] last_instr_rdata; @@ -131,8 +162,9 @@ module uvmt_cv32e40s_interrupt_assert "Interrupt ack was asserted for more than one cycle"); // irq_id_o is never a reserved irq + let valid_irq_mask_index = irq_id_o[ $clog2($bits(VALID_IRQ_MASK)) - 1 : 0 ]; property p_irq_id_o_not_reserved; - irq_ack_o |-> VALID_IRQ_MASK[irq_id_o]; + irq_ack_o |-> VALID_IRQ_MASK[ valid_irq_mask_index ]; endproperty a_irq_id_o_not_reserved: assert property(p_irq_id_o_not_reserved) else @@ -140,22 +172,24 @@ module uvmt_cv32e40s_interrupt_assert $sformatf("int_id_o output is 0x%0x which is reserved", irq_id_o)); // irq_id_o is never a disabled irq + let mie_q_index = irq_id_o[ $clog2($bits(mie_q)) - 1 : 0 ]; property p_irq_id_o_mie_enabled; - irq_ack_o |-> mie_q[irq_id_o]; + irq_ack_o |-> mie_q[ mie_q_index ]; endproperty a_irq_id_o_mie_enabled: assert property(p_irq_id_o_mie_enabled) else `uvm_error(info_tag, $sformatf("irq_id_o output is 0x%0x which is disabled in MIE: 0x%08x", irq_id_o, mie_q)); - // irq_ack_o cannot be asserted if mstatus_mie is deasserted - property p_irq_id_o_mstatus_mie_enabled; - irq_ack_o |-> mstatus_mie; - endproperty - a_irq_id_o_mstatus_mie_enabled: assert property(p_irq_id_o_mstatus_mie_enabled) - else - `uvm_error(info_tag, - $sformatf("int_id_o output is 0x%0x but MSTATUS.MIE is disabled", irq_id_o)); + // irq_ack_o cannot be asserted without mstatus_mie or U-mode + a_irq_id_o_mstatus_mie_enabled: assert property ( + irq_ack_o + |-> + is_mmode_mstatusmie ^ is_umode_miemip + ) else `uvm_error(info_tag, $sformatf("interrupt handler taken but unexpected mie")); + cov_irq_id_o_mstatus_mstatusmie: cover property (irq_ack_o ##0 is_mmode_mstatusmie); + cov_irq_id_o_mstatus_miemip: cover property (irq_ack_o ##0 is_umode_miemip); + // --------------------------------------------------------------------------- // Interrupt CSR checks @@ -203,14 +237,14 @@ module uvmt_cv32e40s_interrupt_assert endproperty generate for(genvar gv_i = 0; gv_i < NUM_IRQ; gv_i++) begin : gen_irq_cov if (VALID_IRQ_MASK[gv_i]) begin : gen_valid - c_irq_masked: cover property(p_irq_masked(gv_i)); - c_irq_masked_mstatus: cover property(p_irq_masked_mstatus(gv_i)); - c_irq_taken: cover property(p_irq_taken(gv_i)); - c_irq_masked_then_enabled: cover property(p_irq_masked_then_enabled(gv_i)); - c_irq_masked_mstatus_then_enabled: cover property(p_irq_masked_mstatus_then_enabled(gv_i)); - c_irq_deasserted_while_enabled_not_acked: cover property(p_irq_deasserted_while_enabled_not_acked(gv_i)); - c_irq_in_mtvec_fixed: cover property(p_irq_in_mtvec(gv_i, 0)); - c_irq_in_mtvec_vector: cover property(p_irq_in_mtvec(gv_i, 1)); + cov_irq_masked: cover property(p_irq_masked(gv_i)); + cov_irq_masked_mstatus: cover property(p_irq_masked_mstatus(gv_i)); + cov_irq_taken: cover property(p_irq_taken(gv_i)); + cov_irq_masked_then_enabled: cover property(p_irq_masked_then_enabled(gv_i)); + cov_irq_masked_mstatus_then_enabled: cover property(p_irq_masked_mstatus_then_enabled(gv_i)); + cov_irq_deasserted_while_enabled_not_acked: cover property(p_irq_deasserted_while_enabled_not_acked(gv_i)); + cov_irq_in_mtvec_fixed: cover property(p_irq_in_mtvec(gv_i, 0)); + cov_irq_in_mtvec_vector: cover property(p_irq_in_mtvec(gv_i, 1)); end end endgenerate @@ -264,7 +298,7 @@ module uvmt_cv32e40s_interrupt_assert expected_irq <= next_irq_q; end - assign expected_irq_ack = next_irq_valid & mstatus_mie; + assign expected_irq_ack = next_irq_valid && (is_mmode_mstatusmie || is_umode_miemip); // Check expected interrupt wins property p_irq_arb; @@ -280,9 +314,7 @@ module uvmt_cv32e40s_interrupt_assert irq_ack_o |-> expected_irq_ack; endproperty a_irq_expected: assert property(p_irq_expected) - else - `uvm_error(info_tag, - $sformatf("Did not expect interrupt ack: %0d", irq_id_o)) + else `uvm_error(info_tag, $sformatf("Did not expect interrupt ack: %0d", irq_id_o)) // --------------------------------------------------------------------------- // The infamous "first" flag (kludge for $past() handling of t=0 values) @@ -328,64 +360,303 @@ module uvmt_cv32e40s_interrupt_assert end end + // --------------------------------------------------------------------------- // WFI Checks // --------------------------------------------------------------------------- + wire logic is_wfi; assign is_wfi = wb_stage_instr_valid_i && (wb_stage_instr_rdata_i == WFI_INSTR_DATA) && - !branch_taken_ex && !wb_stage_instr_err_i && - (wb_stage_instr_mpu_status == MPU_OK); - always @(posedge clk_i or negedge rst_ni) begin + !((priv_lvl == PRIV_LVL_U) && mstatus_tw) && + (wb_stage_instr_mpu_status == MPU_OK) && + !wb_kill && + !debug_mode_q; + wire logic is_wfe; + assign is_wfe = wb_stage_instr_valid_i && + (wb_stage_instr_rdata_i == WFE_INSTR_DATA) && + !((priv_lvl == PRIV_LVL_U) && mstatus_tw) && + !wb_stage_instr_err_i && + (wb_stage_instr_mpu_status == MPU_OK) && + !wb_kill && + !debug_mode_q; + + wire logic pipeline_ready_for_wfi; + assign pipeline_ready_for_wfi = (alignbuf_outstanding == 0) && !lsu_busy; + + logic wb_wfi_wfe_invalidated; + assign wb_wfi_wfe_invalidated = ( + !wb_stage_instr_valid_i || + (wb_stage_instr_mpu_status != MPU_OK) || + wb_stage_instr_err_i || + wb_kill || + debug_mode_q || + ((priv_lvl == PRIV_LVL_U) && mstatus_tw) || + dcsr_step + ); + + logic is_wfi_wfe_in_wb; + assign is_wfi_wfe_in_wb = ( + (wb_stage_instr_rdata_i inside {WFI_INSTR_DATA, WFE_INSTR_DATA}) && + !wb_wfi_wfe_invalidated + ); + + logic is_wfi_wfe_in_wb_q1; + logic is_wfi_wfe_in_wb_q2; + always @(posedge clk_i) begin + is_wfi_wfe_in_wb_q1 <= is_wfi_wfe_in_wb; + is_wfi_wfe_in_wb_q2 <= is_wfi_wfe_in_wb_q1; + end + + logic [31:0] bus_data_outstanding; + logic [31:0] bus_instr_outstanding; + assign bus_instr_outstanding = support_if.alignment_buff_addr_ph_cnt; + assign bus_data_outstanding = support_if.data_bus_v_addr_ph_cnt; + + logic is_wfi_wfe_blocked; + assign is_wfi_wfe_blocked = ( + |bus_instr_outstanding || + |$past(bus_instr_outstanding) || // Arbitrary uarch decision + |bus_data_outstanding || + |$past(bus_data_outstanding) || // Arbitrary uarch decision + obi_instr_if.req || + obi_data_if.req || + (writebufstate != WBUF_EMPTY) + // TODO:silabs-krdosvik (xif): add bustransaction for x-interface + ); + + logic should_wfi_wfe_awaken; + assign should_wfi_wfe_awaken = ( + (|pending_enabled_irq) || + debug_req_i || + pending_nmi || + wb_trigger || + (wu_wfe_i && is_wfe) + ); + + logic model_sleepmode; + always_latch begin if (!rst_ni) begin - in_wfi <= 1'b0; + model_sleepmode <= 1'b 0; end - else begin - if (is_wfi) - in_wfi <= 1'b1; - else if (|pending_enabled_irq || debug_req_i) - in_wfi <= 1'b0; + + if ( + is_wfi_wfe_in_wb && + is_wfi_wfe_in_wb_q2) // Arbitrary uarch decision (2 cycles) + begin + model_sleepmode <= 1'b 1; + end + + if (is_wfi_wfe_blocked) begin + model_sleepmode <= 1'b 0; + end + + if (should_wfi_wfe_awaken) begin + model_sleepmode <= 1'b 0; end end - assign pipeline_ready_for_wfi = (alignbuf_outstanding == 0) && !lsu_busy; + // Check expectations for sleep mode - // WFI assertion will assert core_sleep_o (in WFI_TO_CORE_SLEEP_LATENCY cycles after wb, given ideal conditions) - property p_wfi_assert_core_sleep_o; - !in_wfi - ##1 (in_wfi && !pending_enabled_irq && !debug_mode_q && !debug_req_i)[*(WFI_TO_CORE_SLEEP_LATENCY-1)] - ##1 ( - (in_wfi && !pending_enabled_irq && !debug_mode_q && !debug_req_i) - throughout $past(pipeline_ready_for_wfi)[->1] - ) + a_wfi_assert_sleepmode_expected: assert property ( + model_sleepmode === core_sleep_o + ) else `uvm_error(info_tag, "core_sleep_o must matchexpectations"); + + a_wfi_assert_sleepmode_nodbg: assert property ( + debug_mode_q |-> - core_sleep_o; - endproperty - a_wfi_assert_core_sleep_o: assert property(p_wfi_assert_core_sleep_o) - else - `uvm_error(info_tag, - $sformatf("Assertion of core_sleep_o did not occur within %0d clocks", WFI_TO_CORE_SLEEP_LATENCY)) - c_wfi_assert_core_sleep_o: cover property(p_wfi_assert_core_sleep_o); - - // WFI assertion will assert core_sleep_o (after required conditions are met) - property p_wfi_assert_core_sleep_o_cond; - !in_wfi - ##1 ( - (in_wfi && !pending_enabled_irq && !debug_mode_q && !debug_req_i) - throughout (##1 ($past(pipeline_ready_for_wfi)[->1]) ) - ) + !model_sleepmode + ) else `uvm_error(info_tag, "there is no sleeping in debug"); + + a_wfi_assert_sleepmode_fellreason: assert property ( + $past(is_wfi_wfe_in_wb) && + !is_wfi_wfe_in_wb |-> - core_sleep_o; - endproperty - a_wfi_assert_core_sleep_o_cond: assert property(p_wfi_assert_core_sleep_o_cond) - else - `uvm_error(info_tag, - "Assertion of core_sleep_o did not occur upon its prerequisite conditions") - c_wfi_assert_core_sleep_o_cond: cover property(p_wfi_assert_core_sleep_o_cond); + $past(wb_valid) + or + ((rvfi.rvfi_valid [->1]) ##0 (rvfi.rvfi_dbg == DBG_CAUSE_HALTREQ)) + ) else `uvm_error(info_tag, "wfe mustn't leave wb unexpectedly"); + + cov_wfi_assert_sleepmode_fellreason_valid: cover property ( + $fell(is_wfi_wfe_in_wb) && $past(wb_valid) + ); - // core_sleep_o deassertion in wfi should be followed by WFI deassertion + cov_wfi_assert_sleepmode_fellreason_killed: cover property ( + $fell(is_wfi_wfe_in_wb) && wb_kill + ); + + + // Blocked wfi/wfe stay in wb (unless excused) + + a_wfi_assert_sleepmode_wait: assert property ( + is_wfi_wfe_in_wb && + is_wfi_wfe_blocked && + !should_wfi_wfe_awaken + |=> + is_wfi_wfe_in_wb + or + $past(support_if.recorded_dbg_req) + or + ((rvfi.rvfi_valid [->1]) ##0 (rvfi.rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER)) + ) else `uvm_error(info_tag, "blocked wfi/wfe must remain in wb unless special conditions"); + + + // Sanity check that sleep mode wasn't prematurely entered + + a_wfi_assert_sleepmode_no_ivalid: assert property ( + core_sleep_o + |-> + !mpu_instr_rvalid && !obi_instr_if.rvalid + ) else `uvm_error(info_tag, "shouldn't enter sleep if outstanding iside"); + + a_wfi_assert_sleepmode_no_dvalid: assert property ( + core_sleep_o + |-> + !obi_data_if.rvalid + ) else `uvm_error(info_tag, "shouldn't enter sleep if outstanding dside"); + + a_wfi_assert_sleepmode_no_wbuf: assert property ( + core_sleep_o + |-> + (writebufstate == WBUF_EMPTY) + ) else `uvm_error(info_tag, "shouldn't enter sleep if wbuf non-empty"); + + + // Check wfi/wfe retirement conditions + + a_wfi_assert_sleepmode_retire0: assert property ( + $rose(is_wfi_wfe_in_wb) + |-> + (wb_valid == (dcsr_step && !debug_req_i)) + ) else `uvm_error(info_tag, "1st cycle retire only on step"); + + a_wfi_assert_sleepmode_retire1: assert property ( + $rose(is_wfi_wfe_in_wb_q1) && + is_wfi_wfe_in_wb + |-> + (wb_valid == should_wfi_wfe_awaken) + or + ((rvfi.rvfi_valid [->1]) ##0 (rvfi.rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER)) + ) else `uvm_error(info_tag, "2nd cycle can retire on 'premature' 'wakeup'"); + + a_wfi_assert_sleepmode_retire2: assert property ( + is_wfi_wfe_in_wb_q2 && + is_wfi_wfe_in_wb_q1 && + is_wfi_wfe_in_wb + |-> + (wb_valid == should_wfi_wfe_awaken) + ) else `uvm_error(info_tag, ">2nd cycle retire only on wake"); + + + // Confirm the uarch sleep delay is as expected (2 cycles) + + a_wfi_assert_sleepmode_nodly0: assert property ( + $rose(is_wfi_wfe_in_wb) + |-> + !core_sleep_o + ) else `uvm_error(info_tag, "1st cycle in wb is too early to sleep"); + + a_wfi_assert_sleepmode_nodly1: assert property ( + $rose( $past(is_wfi_wfe_in_wb, 1) ) + |-> + !core_sleep_o + ) else `uvm_error(info_tag, "2nd cycle in wb is too early to sleep"); + + for (genvar i = 2; i < 8; i++) begin: gen_wfi_assert_sleepmode_nodlyn_outer + for (genvar onoff = 0; onoff < 2; onoff++) begin: gen_wfi_assert_sleepmode_nodlyn_inner + cov_wfi_assert_sleepmode_nodlyn: cover property ( + $rose( $past(is_wfi_wfe_in_wb, i) ) + ##0 + (core_sleep_o == onoff) + ); + end + end + + // Check conditions denying sleep + + a_wfi_assert_core_not_ready: assert property ( + !pipeline_ready_for_wfi |-> !core_sleep_o + ) else `uvm_error(info_tag, "no sleep before pipeline ready"); + + a_wfi_assert_no_entry: assert property ( + (|alignbuf_outstanding || |lsu_busy) + |=> + !core_sleep_o + ) else `uvm_error(info_tag, "no sleep before no outstanding"); + + a_wfi_assert_irq_exit: assert property ( + pending_enabled_irq + |-> + !core_sleep_o + ) else `uvm_error(info_tag, "no sleep when pending irqs"); + + a_wfi_assert_debug_exit: assert property ( + debug_req_i + |-> + !core_sleep_o + ) else `uvm_error(info_tag, "no sleep when pending debug"); + + + // core_sleep_o leads to rvfi_valid + + property p_wfi_assert_to_rvfi; + core_sleep_o + ##1 + (rvfi.rvfi_valid [->1]) + |-> + (rvfi.rvfi_insn inside {WFI_INSTR_DATA, WFE_INSTR_DATA}) + ; + // TODO:INFO:silabs-robin Checking the inverse case gets complicated by uarch + endproperty : p_wfi_assert_to_rvfi + + a_wfi_assert_to_rvfi: assert property (p_wfi_assert_to_rvfi) + else `uvm_error(info_tag, "sleeping wfi/wfe must retire to rvfi"); + + + // core_sleep_o must come, or WFI/WFE must finish + + property p_wfi_assert_coresleepo; + ((is_wfi_wfe_in_wb && !should_wfi_wfe_awaken) [*WFI_TO_CORE_SLEEP_LATENCY]) + |=> + (core_sleep_o && !wb_valid) + || (is_wfi_wfe_in_wb && !should_wfi_wfe_awaken && !wb_valid) + || (should_wfi_wfe_awaken && wb_valid) + ; + endproperty : p_wfi_assert_coresleepo + + property p_wfi_assert_coresleepo_ideal_cond; + ((is_wfi_wfe_in_wb && !should_wfi_wfe_awaken) [*WFI_TO_CORE_SLEEP_LATENCY]) + ##0 !should_wfi_wfe_awaken && pipeline_ready_for_wfi + ##1 !should_wfi_wfe_awaken + |-> + (core_sleep_o && !wb_valid) + ; + endproperty : p_wfi_assert_coresleepo_ideal_cond + + a_wfi_assert_coresleepo: assert property ( + p_wfi_assert_coresleepo + ) else `uvm_error(info_tag, "no retire until sleep or giveup"); + + a_wfi_assert_coresleepo_ideal_cond: assert property ( + p_wfi_assert_coresleepo_ideal_cond + ) else `uvm_error(info_tag, "no retire until sleep or giveup"); + + // WFI assertion will assert core_sleep_o (in WFI_TO_CORE_SLEEP_LATENCY cycles after wb, given ideal conditions) + cov_wfi_assert_core_sleep_long: cover property( + ( + p_wfi_assert_coresleepo_ideal_cond + ) and + ( + ((is_wfi_wfe_in_wb == 1) && (is_wfi_wfe_blocked == 1) && (core_sleep_o == 0)) [*1:$] ##1 + ((is_wfi_wfe_in_wb == 1) && (is_wfi_wfe_blocked == 0) && (core_sleep_o == 0)) [*1:$] ##1 + ((is_wfi_wfe_in_wb == 1) && (is_wfi_wfe_blocked == 0) && (core_sleep_o == 1)) [*1:$] + ) + ); + + + // core_sleep_o deassertion should result in the wfi/wfe instruction retiring property p_core_sleep_deassert; - $fell(core_sleep_o) ##0 in_wfi |-> ##1 !in_wfi; + core_sleep_o ##1 $fell(core_sleep_o) |-> wb_valid; endproperty a_core_sleep_deassert: assert property(p_core_sleep_deassert) else @@ -394,7 +665,7 @@ module uvmt_cv32e40s_interrupt_assert // When WFI deasserts the core should be awake property p_wfi_deassert_core_sleep_o; - core_sleep_o ##1 pending_enabled_irq |-> !core_sleep_o; + core_sleep_o ##1 |pending_enabled_irq |-> !core_sleep_o; endproperty a_wfi_deassert_core_sleep_o: assert property(p_wfi_deassert_core_sleep_o) else @@ -403,16 +674,15 @@ module uvmt_cv32e40s_interrupt_assert // Outside of WFI, the core should not sleep a_wfi_deny_core_sleep_o: assert property ( - !in_wfi |-> !core_sleep_o + !is_wfi_wfe_in_wb |-> !core_sleep_o ) else `uvm_error(info_tag, "Only WFI should trigger core sleep"); // WFI wakeup to next instruction fetch/execution property p_wfi_wake_to_instr_fetch; disable iff (!rst_ni || !fetch_enable_i || debug_mode_q) - core_sleep_o && in_wfi - ##1 !in_wfi[->1] - |-> + $fell(core_sleep_o) + |=> ##[0:WFI_WAKEUP_LATENCY] ($rose(if_stage_instr_req_o) // IF starts fetching again || $rose(ex_stage_instr_valid)); // Or continue with prefetched data @@ -424,15 +694,19 @@ module uvmt_cv32e40s_interrupt_assert // Cover property, detect sleep deassertion due to asserted and non-asserted interrupts property p_wfi_wake_mstatus_mie(irq, mie); - $fell(in_wfi) ##0 irq_i[irq] ##0 mie_q[irq] ##0 mstatus_mie == mie; + irq_i[irq] && mie_q[irq] && mstatus_mie == mie ##1 $fell(is_wfi_wfe_in_wb); endproperty generate for(genvar gv_i = 0; gv_i < 32; gv_i++) begin : gen_wfi_cov if (VALID_IRQ_MASK[gv_i]) begin - c_wfi_wake_mstatus_mie_0: cover property(p_wfi_wake_mstatus_mie(gv_i, 0)); - c_wfi_wake_mstatus_mie_1: cover property(p_wfi_wake_mstatus_mie(gv_i, 1)); + cov_wfi_wake_mstatus_mie_0: cover property(p_wfi_wake_mstatus_mie(gv_i, 0)); + cov_wfi_wake_mstatus_mie_1: cover property(p_wfi_wake_mstatus_mie(gv_i, 1)); end end endgenerate + endmodule : uvmt_cv32e40s_interrupt_assert + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_iss_wrap.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_iss_wrap.sv index be69840427..daa184a484 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_iss_wrap.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_iss_wrap.sv @@ -33,7 +33,7 @@ module uvmt_cv32e40s_iss_wrap ( input realtime clk_period, - uvma_clknrst_if clknrst_if + uvma_clknrst_if_t clknrst_if ); RVVI_bus bus(); @@ -45,7 +45,7 @@ module uvmt_cv32e40s_iss_wrap .ROM_BYTE_SIZE(ROM_BYTE_SIZE), .RAM_BYTE_SIZE(RAM_BYTE_SIZE)) ram(bus); - CPU #(.ID(ID), .VARIANT("CV32E40S")) cpu(bus, io); + CPU #(.ID(ID), .VARIANT("CV32E40S_DEV")) cpu(bus, io); bit use_iss = 0; diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_macros.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_macros.sv index 971a8ddf5c..7d2433e0f9 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_macros.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_macros.sv @@ -23,17 +23,17 @@ // Create bind for RVFI CSR interface `define RVFI_CSR_BIND(csr_name) \ bind cv32e40s_wrapper \ - uvma_rvfi_csr_if#(uvme_cv32e40s_pkg::XLEN) rvfi_csr_``csr_name``_if_0_i(.clk(clk_i), \ - .reset_n(rst_ni), \ - .rvfi_csr_rmask(rvfi_i.rvfi_csr_``csr_name``_rmask), \ - .rvfi_csr_wmask(rvfi_i.rvfi_csr_``csr_name``_wmask), \ - .rvfi_csr_rdata(rvfi_i.rvfi_csr_``csr_name``_rdata), \ - .rvfi_csr_wdata(rvfi_i.rvfi_csr_``csr_name``_wdata) \ + uvma_rvfi_csr_if_t#(uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_csr_``csr_name``_if(.clk(clk_i), \ + .reset_n(rst_ni), \ + .rvfi_csr_rmask(rvfi_i.rvfi_csr_``csr_name``_rmask), \ + .rvfi_csr_wmask(rvfi_i.rvfi_csr_``csr_name``_wmask), \ + .rvfi_csr_rdata(rvfi_i.rvfi_csr_``csr_name``_rdata), \ + .rvfi_csr_wdata(rvfi_i.rvfi_csr_``csr_name``_wdata) \ ); `define RVFI_CSR_IDX_BIND(csr_name,csr_suffix,idx) \ bind cv32e40s_wrapper \ - uvma_rvfi_csr_if#(uvme_cv32e40s_pkg::XLEN) rvfi_csr_``csr_name````idx````csr_suffix``_if_0_i( \ + uvma_rvfi_csr_if_t#(uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_csr_``csr_name````idx````csr_suffix``_if( \ .clk(clk_i), \ .reset_n(rst_ni), \ .rvfi_csr_rmask(rvfi_i.rvfi_csr_``csr_name````csr_suffix``_rmask[``idx``]), \ @@ -44,9 +44,9 @@ // Create uvm_config_db::set call for a CSR interface `define RVFI_CSR_UVM_CONFIG_DB_SET(csr_name) \ - uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \ + uvm_config_db#(virtual uvma_rvfi_csr_if_t)::set(.cntxt(null), \ .inst_name("*.env.rvfi_agent"), \ .field_name({"csr_", `"csr_name`", "_vif0"}), \ - .value(dut_wrap.cv32e40s_wrapper_i.rvfi_csr_``csr_name``_if_0_i)); + .value(dut_wrap.cv32e40s_wrapper_i.rvfi_csr_``csr_name``_if)); `endif // __UVMT_CV32E40S_MACROS_SV__ diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pkg.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pkg.sv index 22c2101daf..6b1cfc2b02 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pkg.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pkg.sv @@ -34,11 +34,12 @@ */ package uvmt_cv32e40s_pkg; - import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; import uvme_cv32e40s_pkg::*; import uvml_hrtbt_pkg::*; import uvml_logs_pkg::*; - import uvma_rvvi_ovpsim_pkg::*; + import uvm_pkg::*; // Constants / Parameters / Structs / Enums diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_assert.sv new file mode 100644 index 0000000000..a7a1afde4e --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_assert.sv @@ -0,0 +1,230 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +// Description: +// Module with assertions for the PMA. +// Note, for historical reasons, some verification-written PMA assertions are +// located among the design assertions in the core's repo. New asserts that +// have been written after that fact, are here in this module. + + +`default_nettype none + + +module uvmt_cv32e40s_pma_assert + import cv32e40s_pkg::*; + import uvm_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; +#( + parameter type CORE_REQ_TYPE, + parameter logic [31:0] DM_REGION_START, + parameter logic [31:0] DM_REGION_END, + parameter logic IS_INSTR_SIDE, + parameter int PMA_NUM_REGIONS, + parameter pma_cfg_t PMA_CFG [PMA_NUM_REGIONS-1:0] +)( + input wire clk, + input wire rst_n, + + // Interface from Core + input CORE_REQ_TYPE core_trans_i, + + // Interface towards OBI + input CORE_REQ_TYPE bus_trans_o, + input wire bus_trans_ready_i, + input wire bus_trans_valid_o, + + // Writebuffer Signals + input wire obi_data_req_t writebuf_trans_i, + input wire obi_data_req_t writebuf_trans_o, + input wire writebuf_ready_o, + + // PMA Verdict + input wire pma_err, + input wire bus_trans_bufferable, + input wire bus_trans_cacheable, + input wire bus_trans_integrity, + + // Support Logic + uvma_obi_memory_if_t obi_memory_if, + uvma_rvfi_instr_if_t rvfi_instr_if, + input wire pma_status_t pma_status_i +); + + + default clocking @(posedge clk); endclocking + default disable iff !rst_n; + + string info_tag = "CV32E40S_PMA_ASSERT"; + + enum {BIT_IDX_BUFFERABLE=0} memtype_bit_idx_e; + + + // Helper logic + + function logic is_bufferable_in_config; + is_bufferable_in_config = 0; + foreach (PMA_CFG[i]) begin + if (PMA_CFG[i].bufferable) begin + is_bufferable_in_config = 1; + //TODO:WARNING:silabs-robin Incorrect if region is overshadowed + end + end + endfunction : is_bufferable_in_config + localparam logic IS_BUFFERABLE_IN_CONFIG = is_bufferable_in_config(); + + + // PMA-restricted regions prohibit OBI req (vplan:InstructionFetches:2) + + a_req_prohibited: assert property ( + pma_err + |-> + !bus_trans_valid_o + //TODO:INFO:silas-robin Idea: rvfi-vs-obi sb refmodel prediction + ) else `uvm_error(info_tag, "pma must block obi reqs"); + + + // memtype[0] matches bufferable flag (vplan:InstructionFetches:0, vplan:DataFetches:0) + + a_memtype_bufferable: assert property ( + bus_trans_o.memtype[BIT_IDX_BUFFERABLE] == bus_trans_bufferable + // Note: Depends on rest of checking to see that "bus_trans_bufferable" is reliable + ) else `uvm_error(info_tag, "MPU bufferable flag must corespond to obi memtype[0]"); + + + // DM region overrules PMA configs (vplan:DebugRange) + + a_dm_region: assert property ( + core_trans_i.dbg && + (core_trans_i.addr inside {[DM_REGION_START:DM_REGION_END]}) + |-> + !pma_err + ) else `uvm_error(info_tag, "dmode in dregion is never blocked"); + + + // Writebuffer usage must be bufferable (vplan:WriteBuffer) + + if (!IS_INSTR_SIDE) begin: gen_writebuf + a_writebuf_bufferable: assert property ( + !bus_trans_bufferable + |-> + (writebuf_trans_i == writebuf_trans_o) // Non-buffable must passthrough... + || + (!writebuf_ready_o) // ...or we are waiting for a previous buffered. + ) else `uvm_error(info_tag, "Non-bufferable regions must pass straight through the writebuf"); + + if (IS_BUFFERABLE_IN_CONFIG) begin: gen_buffering + cov_writebuf_buffering: cover property ( + (writebuf_trans_i != writebuf_trans_o) + ); + end : gen_buffering + + if (PMA_NUM_REGIONS == 0) begin: gen_noregions_nobuf + a_writebuf_noregions: assert property ( + !bus_trans_bufferable && + (writebuf_trans_i == writebuf_trans_o) + ) else `uvm_error(info_tag, "with zero regions, nothing is bufferable"); + end : gen_noregions_nobuf + end : gen_writebuf + + + // After PMA-deny, subsequent accesses are also suppressed (vplan:"Multi-memory operation instructions") + + a_failure_denies_subsequents: assert property ( + rvfi_instr_if.is_pma_instr_fault + |-> + (rvfi_instr_if.rvfi_mem_wmask == '0) + //TODO:ERROR:silabs-robin Zcmp should be able to break this. RVFI bug. + //TODO:ERROR:silabs-robin Also reads + ) else `uvm_error(info_tag, "accesses aftmr pma fault should be suppressed"); + + property p_partial_pma_allow (exc_cause); + rvfi_instr_if.rvfi_valid && + (rvfi_instr_if.rvfi_mem_wmask || rvfi_instr_if.rvfi_mem_rmask) && + rvfi_instr_if.rvfi_trap && + rvfi_instr_if.rvfi_trap.exception && + (rvfi_instr_if.rvfi_trap.cause_type == 0) && // PMA, not PMP + (rvfi_instr_if.rvfi_trap.exception_cause == exc_cause) + //TODO:WARNING:silabs-robin Review after above rvfi bug is fixed + ; + endproperty : p_partial_pma_allow + + cov_partial_pma_allow_load: cover property ( + p_partial_pma_allow (EXC_CAUSE_LOAD_FAULT) + ); + + cov_partial_pma_allow_store: cover property ( + p_partial_pma_allow (EXC_CAUSE_STORE_FAULT) + ); + + + // MPU-accepted transactions must reach OBI (vplan: not a vplan item) + + property p_eventually_mpu2obi; + logic [31:0] addr; + (bus_trans_valid_o && bus_trans_ready_i, addr = bus_trans_o.addr) + |-> + s_eventually (obi_memory_if.req && (obi_memory_if.addr[31:2] == addr[31:2])) + //TODO:INFO:silabs-robin Could use transaction number ID instead of addr + ; + endproperty : p_eventually_mpu2obi + + a_eventually_mpu2obi: assert property ( + p_eventually_mpu2obi + ) else `uvm_error(info_tag, "mpu output must reach the bus"); + + + // MPU output reliably reaches OBI (vplan: not a vplan item) + + if (IS_INSTR_SIDE) begin: gen_attr_instr + a_attributes_to_obi: assert property ( + bus_trans_valid_o && + bus_trans_ready_i + |-> + (obi_memory_if.memtype == bus_trans_o.memtype) && + (obi_memory_if.prot == bus_trans_o.prot) && + (obi_memory_if.dbg == bus_trans_o.dbg) + ) else `uvm_error(info_tag, "obi attributes must mach mpu"); + //TODO:INFO:silabs-robin Data-side Could be checked by comparing with transaction number IDs + end : gen_attr_instr + + + // PMA Verdict Expected + + a_pma_err: assert property ( + pma_err == !pma_status_i.allow + ) else `uvm_error(info_tag, "pma err unexpected value"); + + a_pma_bufferable: assert property ( + bus_trans_bufferable == pma_status_i.bufferable + ) else `uvm_error(info_tag, "pma bufferable unexpected value"); + + a_pma_cacheable: assert property ( + bus_trans_cacheable == pma_status_i.cacheable + ) else `uvm_error(info_tag, "pma cacheable unexpected value"); + + a_pma_integrity: assert property ( + bus_trans_integrity == pma_status_i.integrity + ) else `uvm_error(info_tag, "pma integrity unexpected value"); + + +endmodule : uvmt_cv32e40s_pma_assert + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_cov.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_cov.sv new file mode 100644 index 0000000000..7b61b49a81 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_cov.sv @@ -0,0 +1,396 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +`default_nettype none + + +module uvmt_cv32e40s_pma_cov + import uvmt_cv32e40s_base_test_pkg::*; +#( + parameter bit IS_INSTR_SIDE, + parameter int PMA_NUM_REGIONS, + parameter type CORE_REQ_TYPE +)( + input wire clk, + input wire clk_ungated, + input wire rst_n, + + // MPU Signals + input CORE_REQ_TYPE core_trans_i, + input wire core_trans_pushpop_i, + input wire core_trans_ready_o, + input wire core_trans_valid_i, + input wire load_access, + input wire misaligned_access_i, + + // Helper Logic + input wire pma_status_t pma_status_i, + input wire pma_status_t pma_status_rvfidata_word0highbyte_i, + input wire pma_status_t pma_status_rvfidata_word0lowbyte_i, + uvma_rvfi_instr_if_t rvfi_if +); + + + // Exclude Known Unreachables + + `ifdef FORMAL + localparam bit SIMPLIFY_FV = 1; + `else + localparam bit SIMPLIFY_FV = 0; + `endif + + + // Helper Logic - Match Info + + wire logic [31:0] num_matches; + assign num_matches = $countones(pma_status_i.match_list); + + let have_match = pma_status_i.have_match; + let match_idx = pma_status_i.match_idx; + + + // Helper Logic - MPU Activation + + wire logic is_mpu_activated; + assign is_mpu_activated = (core_trans_ready_o && core_trans_valid_i); + + + // Helper Logic - Split Transactions Main vs I/O + + wire logic [1:0] rvfi_pmamain_lowhigh; + assign rvfi_pmamain_lowhigh[1] = pma_status_rvfidata_word0lowbyte_i.main; + assign rvfi_pmamain_lowhigh[0] = pma_status_rvfidata_word0highbyte_i.main; + + + // typedef to parameterize size of helper signals + typedef logic [$bits(rvfi_if.rvfi_mem_wmask)-1:0] rvfi_mem_wmask_t; + + // Helper Logic - "Past" Values + var logic occured_rvfi_valid; + var logic rvfi_pma_fault_q; + var logic rvfi_mem_act_q; + var logic rvfi_pmamain_low_q; + var rvfi_mem_wmask_t rvfi_mem_wmask_q; + + always_ff @(posedge clk_ungated or negedge rst_n) begin + if (rst_n == 0) begin + occured_rvfi_valid <= '0; + rvfi_pma_fault_q <= '0; + rvfi_mem_wmask_q <= '0; + rvfi_mem_act_q <= '0; + rvfi_pmamain_low_q <= '0; + end else if (rvfi_if.rvfi_valid) begin + occured_rvfi_valid <= 1; + rvfi_pma_fault_q <= rvfi_if.is_pma_fault; + rvfi_mem_wmask_q <= rvfi_mem_wmask_t'(rvfi_if.rvfi_mem_wmask); + rvfi_mem_act_q <= rvfi_if.is_mem_act; + rvfi_pmamain_low_q <= rvfi_pmamain_lowhigh[1]; + end + end + + + // MPU Coverage Definition + + covergroup cg_mpu @(posedge clk); + option.per_instance = 1; + option.detect_overlap = 1; + + // vplan:"Valid number of regions" + cp_numregions: coverpoint PMA_NUM_REGIONS { + bins zero = {0} with (PMA_NUM_REGIONS == 0); + bins mid = {[1:15]} with ((0 < PMA_NUM_REGIONS) && (PMA_NUM_REGIONS < 16)); + bins max = {16} with (PMA_NUM_REGIONS == 16); + } + + // vplan:"Overlapping PMA Regions" + cp_multimatch: coverpoint num_matches iff (is_mpu_activated) { + bins zero = {0} + with (!SIMPLIFY_FV); + bins one = {1} + with (0 < PMA_NUM_REGIONS); + bins many = {[2:PMA_NUM_REGIONS]} + with ((1 < PMA_NUM_REGIONS) && (!SIMPLIFY_FV)); + } + + cp_matchregion: coverpoint match_idx iff (is_mpu_activated) { + bins regions[] = {[0:(PMA_NUM_REGIONS > 0) ? (PMA_NUM_REGIONS-1) : 0 ]} + with (!SIMPLIFY_FV) + iff (have_match == 1); + bins nomatch = {[0:(PMA_NUM_REGIONS > 0) ? (PMA_NUM_REGIONS-1) : 0]} + with (!SIMPLIFY_FV) + iff (have_match == 0); + } + + cp_aligned: coverpoint misaligned_access_i iff (is_mpu_activated) { + bins misaligned = {1} with (!IS_INSTR_SIDE); + illegal_bins illegal = {1} with ( IS_INSTR_SIDE); + bins aligned = {0}; + } + + cp_loadstoreexec: coverpoint load_access iff (is_mpu_activated) { + bins load = {1} with (!IS_INSTR_SIDE); + bins store = {0} with (!IS_INSTR_SIDE); + bins exec = {0, 1} with ( IS_INSTR_SIDE); + } + + cp_store: coverpoint load_access iff (is_mpu_activated) { + bins store = {0} with (!IS_INSTR_SIDE); + } + + cp_allow: coverpoint pma_status_i.allow iff (is_mpu_activated) { + bins allow = {1}; + bins disallow = {0}; + } + + cp_main: coverpoint pma_status_i.main iff (is_mpu_activated) { + bins main = {1}; + bins io = {0}; + } + + cp_bufferable: coverpoint pma_status_i.bufferable iff (is_mpu_activated) { + bins bufferable = {1} with (!IS_INSTR_SIDE); + illegal_bins illegal = {1} with ( IS_INSTR_SIDE); + bins nonbufferable = {0}; + } + + cp_cacheable: coverpoint pma_status_i.cacheable iff (is_mpu_activated) { + bins cacheable = {1}; + bins no = {0}; + } + + cp_integrity: coverpoint pma_status_i.integrity iff (is_mpu_activated) { + bins integrity = {1} with (!SIMPLIFY_FV); + bins no = {0}; + } + + cp_overridedm: coverpoint pma_status_i.override_dm iff (is_mpu_activated) + { + bins override = {1}; + bins no = {0}; + } + + cp_pushpop: coverpoint core_trans_pushpop_i iff (is_mpu_activated) { + bins pushpop = {1} with (!IS_INSTR_SIDE); + illegal_bins illegal = {1} with ( IS_INSTR_SIDE); + bins no = {0}; + } + + // vplan:DebugRange + cp_dmregion: coverpoint pma_status_i.accesses_dmregion + iff (is_mpu_activated) + { + bins in = {1}; + bins out = {0}; + } + cp_dmode: coverpoint core_trans_i.dbg iff (is_mpu_activated) { + bins dmode = {1}; + bins no = {0}; + } + + cp_jvt: coverpoint pma_status_i.accesses_jvt iff (is_mpu_activated) { + bins accesses = {1} with (IS_INSTR_SIDE); + bins no = {0} with (IS_INSTR_SIDE); + } + + x_multimatch_aligned_loadstoreexec_allow: + cross cp_multimatch, cp_aligned, cp_loadstoreexec, cp_allow { + ignore_bins one_disallow = + (binsof(cp_multimatch.one) && binsof(cp_allow.disallow)) + with (SIMPLIFY_FV); + } + x_multimatch_main: cross cp_multimatch, cp_main { + ignore_bins one_io = + (binsof(cp_multimatch.one) && binsof(cp_main.io)) with (SIMPLIFY_FV); + } + x_multimatch_bufferable: cross cp_multimatch, cp_bufferable; + x_multimatch_cacheable: cross cp_multimatch, cp_cacheable { + ignore_bins one_no = + (binsof(cp_multimatch.one) && binsof(cp_cacheable.no)) + with (SIMPLIFY_FV); + } + x_multimatch_integrity: cross cp_multimatch, cp_integrity; + x_multimatch_overridedm: cross cp_multimatch, cp_overridedm { + ignore_bins one_override = + (binsof(cp_multimatch.one) && binsof(cp_overridedm.override)) + with (SIMPLIFY_FV); + } + + x_aligned_allow: cross cp_aligned, cp_allow; + x_aligned_main_loadstoreexec: cross cp_aligned, cp_main, cp_loadstoreexec; + x_aligned_bufferable: cross cp_aligned, cp_bufferable; + x_aligned_cacheable: cross cp_aligned, cp_cacheable; + x_aligned_integrity: cross cp_aligned, cp_integrity; + x_aligned_overridedm: cross cp_aligned, cp_overridedm; + + x_loadstoreexec_allow_main: cross cp_loadstoreexec, cp_allow, cp_main { + ignore_bins ignore = + binsof(cp_allow.allow) && + binsof(cp_main.io); + //Note: Should be specific "illegal_bins" + //Because of tool support, the covers are artificially limited. + illegal_bins disallow_main = + binsof(cp_allow.disallow) && + binsof(cp_main.main); + } + x_loadstoreexec_main_pushpop: cross cp_loadstoreexec, cp_main, cp_pushpop; + //x_loadstoreexec_bufferable: cross cp_loadstoreexec, cp_bufferable; + //Note: Filtering of this cross seems impossible. + //Each tool supports each their own disparate subset of the language, so + //you can seemingly make it work in one or the other but not both at once. + //See "x_store_bufferable" + x_loadstoreexec_cacheable: cross cp_loadstoreexec, cp_cacheable; + x_loadstoreexec_integrity: cross cp_loadstoreexec, cp_integrity; + x_loadstoreexec_overridedm: cross cp_loadstoreexec, cp_overridedm; + + //TODO silabs-robin: Needs update + //x_allow_bufferable: cross cp_allow, cp_bufferable { + // ignore_bins disallow_bufferable = + // (binsof(cp_allow.disallow) && binsof(cp_bufferable.bufferable)) + // with (SIMPLIFY_FV); + //} + //x_allow_cacheable: cross cp_allow, cp_cacheable { + // illegal_bins disallow_cacheable = + // binsof(cp_allow.disallow) && binsof(cp_cacheable.cacheable); + //} + //x_allow_integrity: cross cp_allow, cp_integrity { + // illegal_bins disallow_integrity = + // binsof(cp_allow.disallow) && binsof(cp_integrity.integrity); + //} + x_allow_jvt: cross cp_allow, cp_jvt; + + x_dmregion_dmode: cross cp_dmregion, cp_dmode; + + x_store_bufferable: cross cp_store, cp_bufferable; + + //Note: more crosses are possible, but bordering on impractical/infeasible + endgroup + + cg_mpu mpu_cg = new; + + + // RVFI Coverage Definition + + covergroup cg_rvfi @(posedge clk_ungated); + option.per_instance = 1; + option.detect_overlap = 1; + + cp_aligned: coverpoint rvfi_if.is_split_datatrans_intended + iff (rvfi_if.rvfi_valid) + { + bins misaligned = {1}; + bins aligned = {0}; + } + + cp_pmafault: coverpoint rvfi_if.is_pma_fault iff (rvfi_if.rvfi_valid) { + bins fault = {1}; + bins no = {0}; + } + + cp_waspmafault: coverpoint rvfi_pma_fault_q iff (occured_rvfi_valid) { + bins fault = {1}; + bins no = {0}; + } + + cp_loadstore: coverpoint rvfi_if.rvfi_mem_wmask + iff (rvfi_if.is_mem_act) + { + bins load = {0}; + bins store = {[1:$]}; + illegal_bins undefined = default; // Should be empty + } + + cp_wasloadstore: coverpoint rvfi_mem_wmask_q + iff (rvfi_mem_act_q && occured_rvfi_valid) + { + bins load = {0}; + bins store = {[1:$]}; + illegal_bins undefined = default; // Should be empty + } + + cp_firstfail: coverpoint pma_status_rvfidata_word0lowbyte_i.allow + iff (rvfi_if.is_mem_act) + { + bins yes = {0}; + bins no = {1}; + } + + cp_boundary: coverpoint rvfi_pmamain_lowhigh iff (rvfi_if.is_mem_act) { + bins main2main = {2'b 11}; + bins main2io = {2'b 10}; + bins io2main = {2'b 01}; + bins io2io = {2'b 00}; + } + + cp_wasmain: coverpoint rvfi_pmamain_low_q + iff (rvfi_mem_act_q && occured_rvfi_valid) + { + bins main = {1}; + bins io = {0}; + } + + cp_tablejump: coverpoint rvfi_if.is_tablejump_raw iff (rvfi_if.rvfi_valid) { + bins jump = {1}; + bins no = {0}; + } + + cp_fence: coverpoint rvfi_if.is_fencefencei iff (rvfi_if.rvfi_valid) { + bins fencefencei = {1}; + bins no = {0}; + } + + + // General Crosses + + x_aligned_pmafault_loadstore_firstfail: + cross cp_aligned, cp_pmafault, cp_loadstore, cp_firstfail; + + x_aligned_loadstore_boundary: cross cp_aligned, cp_loadstore, cp_boundary { + ignore_bins aligned = + binsof(cp_aligned.aligned); + ignore_bins misaligned_io2io = + (binsof(cp_aligned.misaligned) && binsof(cp_boundary.io2io)) + with (SIMPLIFY_FV); + } + + + // Table Jump Crosses + + // TODO: silabs-hfegran: these need vector table access on IF side, currently + // only data side is used. + //x_pmafault_firstfail_tablejump: cross cp_pmafault, cp_firstfail, cp_tablejump; + + x_pmafault_tablejump: cross cp_pmafault, cp_tablejump; + + + // Fence Crosses + + x_waspmafault_wasmain_wasloadstore_fence: + cross cp_waspmafault, cp_wasmain, cp_wasloadstore, cp_fence; + endgroup + + if (!IS_INSTR_SIDE) begin: gen_rvfi_cg + cg_rvfi rvfi_cg = new; + // RVFI is 1 interface, so we don't need an exact duplicate at each MPU. + end + + +endmodule : uvmt_cv32e40s_pma_cov + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmp_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmp_assert.sv new file mode 100644 index 0000000000..1f37a6b54c --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmp_assert.sv @@ -0,0 +1,539 @@ +// Copyright 2022 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +`default_nettype none + + +module uvmt_cv32e40s_pmp_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + #( + parameter int PMP_GRANULARITY, + parameter int PMP_NUM_REGIONS, + parameter int IS_INSTR_SIDE, + parameter mseccfg_t PMP_MSECCFG_RV + ) + ( + // Clock and Reset + input wire clk, + input wire rst_n, + + // CSRs + input wire pmp_csr_t csr_pmp_i, + + // Mode Info + input wire privlvl_t priv_lvl_i, + input wire bus_trans_dbg, + + // Access Checking + input wire [33:0] pmp_req_addr_i, + input wire pmp_req_e pmp_req_type_i, + input wire pmp_req_err_o, + + // OBI + input wire obi_req, + input wire [31:0] obi_addr, + input wire obi_gnt, + + // RVFI + input wire rvfi_valid, + input wire [31:0] rvfi_pc_rdata + ); + + + string info_tag = "CV32E40S_PMP_ASSERT"; + + + // Defaults + + default clocking @(posedge clk); endclocking + default disable iff (!rst_n); + + + // Helper logic + + match_status_t match_status; + uvmt_cv32e40s_pmp_model #( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .DM_REGION_START (CORE_PARAM_DM_REGION_START), + .DM_REGION_END (CORE_PARAM_DM_REGION_END) + ) model_i ( + .debug_mode (bus_trans_dbg), + .match_status_o (match_status), + .* + ); + + + // Extra covers and asserts to comprehensively match the spec + + // Cover the helper-RTL internals + generate + if (IS_INSTR_SIDE === 1'b1 && PMP_NUM_REGIONS > 0) begin : gen_cp_instr_side + covergroup cg_internals_instr_side @(posedge clk); + option.per_instance = 1; + + // Machine mode execute accesses + cp_x_mmode_x : coverpoint match_status.val_access_allowed_reason.x_mmode_x { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_mmode_lx : coverpoint match_status.val_access_allowed_reason.x_mmode_lx { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_mmode_mml_lx : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lx { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_mmode_mml_lw : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lw { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_mmode_mml_lwx : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lwx { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_mmode_mml_lrx : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lrx { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_mmode_nomatch_nommwp_x : coverpoint match_status.val_access_allowed_reason.x_mmode_nomatch_nommwp_x { bins low = {1'b0}; bins high = {1'b1}; } + // User mode execute accesses + cp_x_umode_x : coverpoint match_status.val_access_allowed_reason.x_umode_x { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_umode_mml_x : coverpoint match_status.val_access_allowed_reason.x_umode_mml_x { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_umode_mml_rx : coverpoint match_status.val_access_allowed_reason.x_umode_mml_rx { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_umode_mml_rwx : coverpoint match_status.val_access_allowed_reason.x_umode_mml_rwx { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_umode_mml_lw : coverpoint match_status.val_access_allowed_reason.x_umode_mml_lw { bins low = {1'b0}; bins high = {1'b1}; } + cp_x_umode_mml_lwx : coverpoint match_status.val_access_allowed_reason.x_umode_mml_lwx { bins low = {1'b0}; bins high = {1'b1}; } + // Ignore bins for unreachable load/stores on instruction if + // Machine mode l/s accesses + cp_r_mmode_nomatch_nommwp_r : coverpoint match_status.val_access_allowed_reason.r_mmode_nomatch_nommwp_r { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_mmode_nomatch_nommwp_w : coverpoint match_status.val_access_allowed_reason.w_mmode_nomatch_nommwp_w { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_mmode_mml_w : coverpoint match_status.val_access_allowed_reason.w_mmode_mml_w { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_mmode_mml_wx : coverpoint match_status.val_access_allowed_reason.w_mmode_mml_wx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_mmode_mml_lrw : coverpoint match_status.val_access_allowed_reason.w_mmode_mml_lrw { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_r : coverpoint match_status.val_access_allowed_reason.r_mmode_r { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_lr : coverpoint match_status.val_access_allowed_reason.r_mmode_lr { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_mmode_w : coverpoint match_status.val_access_allowed_reason.w_mmode_w { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_mmode_lw : coverpoint match_status.val_access_allowed_reason.w_mmode_lw { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_mml_w : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_w { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_mml_wx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_wx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_mml_lwx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_mml_lr : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lr { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_mml_lrx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lrx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_mml_lrw : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lrw { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_mmode_mml_lrwx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lrwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + // User mode l/s accesses + cp_w_umode_mml_wx : coverpoint match_status.val_access_allowed_reason.w_umode_mml_wx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_umode_mml_rw : coverpoint match_status.val_access_allowed_reason.w_umode_mml_rw { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_umode_mml_rwx : coverpoint match_status.val_access_allowed_reason.w_umode_mml_rwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_r : coverpoint match_status.val_access_allowed_reason.r_umode_r { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_w_umode_w : coverpoint match_status.val_access_allowed_reason.w_umode_w { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_mml_w : coverpoint match_status.val_access_allowed_reason.r_umode_mml_w { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_mml_wx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_wx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_mml_r : coverpoint match_status.val_access_allowed_reason.r_umode_mml_r { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_mml_rx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_rx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_mml_rw : coverpoint match_status.val_access_allowed_reason.r_umode_mml_rw { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_mml_rwx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_rwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_r_umode_mml_lrwx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_lrwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + // TODO:silabs-robin Try swapping all "ignore_bins" with "illegal_bins" in fv + endgroup : cg_internals_instr_side + cg_internals_instr_side cg_instr = new(); + end + else if (IS_INSTR_SIDE === 1'b0 && PMP_NUM_REGIONS > 0) begin : gen_cp_data_side + covergroup cg_internals_data_side @(posedge clk); + option.per_instance = 1; + + // Ignore bins for unreachable execute accesses on lsu if + // Machine mode execute accesses + cp_x_mmode_x : coverpoint match_status.val_access_allowed_reason.x_mmode_x { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_mmode_lx : coverpoint match_status.val_access_allowed_reason.x_mmode_lx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_mmode_mml_lx : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_mmode_mml_lw : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lw { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_mmode_mml_lwx : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_mmode_mml_lrx : coverpoint match_status.val_access_allowed_reason.x_mmode_mml_lrx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_mmode_nomatch_nommwp_x : coverpoint match_status.val_access_allowed_reason.x_mmode_nomatch_nommwp_x { bins low = {1'b0}; ignore_bins high = {1'b1}; } + // User mode execute accesses + cp_x_umode_x : coverpoint match_status.val_access_allowed_reason.x_umode_x { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_umode_mml_x : coverpoint match_status.val_access_allowed_reason.x_umode_mml_x { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_umode_mml_rx : coverpoint match_status.val_access_allowed_reason.x_umode_mml_rx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_umode_mml_rwx : coverpoint match_status.val_access_allowed_reason.x_umode_mml_rwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_umode_mml_lw : coverpoint match_status.val_access_allowed_reason.x_umode_mml_lw { bins low = {1'b0}; ignore_bins high = {1'b1}; } + cp_x_umode_mml_lwx : coverpoint match_status.val_access_allowed_reason.x_umode_mml_lwx { bins low = {1'b0}; ignore_bins high = {1'b1}; } + // Machine mode l/s accesses + cp_r_mmode_nomatch_nommwp_r : coverpoint match_status.val_access_allowed_reason.r_mmode_nomatch_nommwp_r { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_mmode_nomatch_nommwp_w : coverpoint match_status.val_access_allowed_reason.w_mmode_nomatch_nommwp_w { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_mmode_mml_w : coverpoint match_status.val_access_allowed_reason.w_mmode_mml_w { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_mmode_mml_wx : coverpoint match_status.val_access_allowed_reason.w_mmode_mml_wx { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_mmode_mml_lrw : coverpoint match_status.val_access_allowed_reason.w_mmode_mml_lrw { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_r : coverpoint match_status.val_access_allowed_reason.r_mmode_r { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_lr : coverpoint match_status.val_access_allowed_reason.r_mmode_lr { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_mmode_w : coverpoint match_status.val_access_allowed_reason.w_mmode_w { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_mmode_lw : coverpoint match_status.val_access_allowed_reason.w_mmode_lw { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_mml_w : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_w { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_mml_wx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_wx { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_mml_lwx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lwx { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_mml_lr : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lr { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_mml_lrx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lrx { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_mml_lrw : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lrw { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_mmode_mml_lrwx : coverpoint match_status.val_access_allowed_reason.r_mmode_mml_lrwx { bins low = {1'b0}; bins high = {1'b1}; } + // User mode l/s accesses + cp_w_umode_mml_wx : coverpoint match_status.val_access_allowed_reason.w_umode_mml_wx { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_umode_mml_rw : coverpoint match_status.val_access_allowed_reason.w_umode_mml_rw { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_umode_mml_rwx : coverpoint match_status.val_access_allowed_reason.w_umode_mml_rwx { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_r : coverpoint match_status.val_access_allowed_reason.r_umode_r { bins low = {1'b0}; bins high = {1'b1}; } + cp_w_umode_w : coverpoint match_status.val_access_allowed_reason.w_umode_w { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_mml_w : coverpoint match_status.val_access_allowed_reason.r_umode_mml_w { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_mml_wx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_wx { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_mml_r : coverpoint match_status.val_access_allowed_reason.r_umode_mml_r { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_mml_rx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_rx { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_mml_rw : coverpoint match_status.val_access_allowed_reason.r_umode_mml_rw { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_mml_rwx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_rwx { bins low = {1'b0}; bins high = {1'b1}; } + cp_r_umode_mml_lrwx : coverpoint match_status.val_access_allowed_reason.r_umode_mml_lrwx { bins low = {1'b0}; bins high = {1'b1}; } + endgroup : cg_internals_data_side + cg_internals_data_side cg_data = new(); + end + endgenerate + + generate + if (PMP_NUM_REGIONS > 0) begin : gen_cg_common + covergroup cg_internals_common @(posedge clk); + option.per_instance = 1; + + cp_ismatch_tor: coverpoint model_i.is_match_tor(match_status.val_index) iff (match_status.is_matched); + + cp_napot_min_8byte: coverpoint { pmp_req_addr_i[2+PMP_GRANULARITY], csr_pmp_i.addr[match_status.val_index][2+PMP_GRANULARITY] } + iff (csr_pmp_i.cfg[match_status.val_index].mode == PMP_MODE_NAPOT && + match_status.is_matched == 1'b1 && + match_status.is_access_allowed == 1'b1 + ); + + cp_napot_min_8byte_disallowed: coverpoint { pmp_req_addr_i[2+PMP_GRANULARITY], csr_pmp_i.addr[match_status.val_index][2+PMP_GRANULARITY] } + iff (csr_pmp_i.cfg[match_status.val_index].mode == PMP_MODE_NAPOT && + match_status.is_matched == 1'b1 && + match_status.is_access_allowed == 1'b0 + ); + + cp_napot_encoding: coverpoint ( pmp_req_addr_i[33:2+PMP_GRANULARITY] == csr_pmp_i.addr[match_status.val_index][33:2+PMP_GRANULARITY] ) + iff (csr_pmp_i.cfg[match_status.val_index].mode == PMP_MODE_NAPOT && + match_status.is_matched == 1'b1 && + match_status.is_access_allowed == 1'b1 + ); + + cp_napot_encoding_disallowed: coverpoint ( pmp_req_addr_i[33:2+PMP_GRANULARITY] == csr_pmp_i.addr[match_status.val_index][33:2+PMP_GRANULARITY] ) + iff (csr_pmp_i.cfg[match_status.val_index].mode == PMP_MODE_NAPOT && + match_status.is_matched == 1'b1 && + match_status.is_access_allowed == 1'b0 + ); + + endgroup + cg_internals_common cg_int = new(); + end + endgenerate + + // NA4 only available in G=0 (vplan:Na4Unselectable) + generate for (genvar region = 0; region < PMP_NUM_REGIONS; region++) begin: gen_na4onlyg0 + a_na4_only_g0: assert property ( + (csr_pmp_i.cfg[region].mode == PMP_MODE_NA4) + |-> + (PMP_GRANULARITY === 1'b 0) + ) else `uvm_error(info_tag, "G must be 0 if using NA4"); + + + if (PMP_GRANULARITY !== 1'b 0) begin: gen_na4onlyg0_reverse + a_na4_not_when_g: assert property ( + // "Redundant" assert for coverage + (csr_pmp_i.cfg[region].mode !== PMP_MODE_NA4) + ) else `uvm_error(info_tag, "mode can't be NA4 if G=0"); + end + end endgenerate + + // NA4 has 4-byte granularity (vplan:NapotMatching) + generate if (PMP_GRANULARITY == 0 && PMP_NUM_REGIONS > 0) begin: gen_na4is4byte + a_na4_is_4byte: assert property ( + csr_pmp_i.cfg[match_status.val_index].mode == PMP_MODE_NA4 && + match_status.is_matched == 1'b1 && + match_status.is_access_allowed == 1 |-> + pmp_req_addr_i[31:2] == csr_pmp_i.addr[match_status.val_index][31:2] + ) else `uvm_error(info_tag, "NA4 matches must match word-aligned"); + end endgenerate + + // Spec: "The combination R=0 and W=1 is reserved for future use" - Exception: mml set + // (vplan:RwReserved) + generate for (genvar region = 0; region < PMP_NUM_REGIONS; region++) begin: gen_rwfuture + a_rw_futureuse: assert property ( + csr_pmp_i.mseccfg.mml === 1'b0 |-> + !(csr_pmp_i.cfg[region].read == 0 && csr_pmp_i.cfg[region].write == 1) + ) else `uvm_error(info_tag, "'RW' cannot be 01"); + end endgenerate + + // mseccfg.RLB = 1 LOCKED rules may be modified/removed, LOCKED entries may be modified -> test inverse + // (vplan:IgnoreWrites) + generate for (genvar region = 0; region < PMP_NUM_REGIONS; region++) begin: gen_rlb_locked + a_norlb_locked_rules_cannot_modify : assert property ( + csr_pmp_i.mseccfg.rlb === 1'b0 && csr_pmp_i.cfg[region].lock === 1'b1 |=> + $stable(csr_pmp_i.cfg[region]) + ) else `uvm_error(info_tag, "locked unbypassed cfgs must be stable"); + end endgenerate + + generate for (genvar region = 0; region < PMP_NUM_REGIONS; region++) begin: gen_rlb_locked_cov + cov_rlb_locked_rules_can_modify_addr : cover property ( + csr_pmp_i.mseccfg.rlb === 1'b1 && csr_pmp_i.cfg[region].lock === 1'b1 ##1 + $changed(csr_pmp_i.addr[region]) + ); + + cov_rlb_locked_rules_can_modify_lock : cover property ( + csr_pmp_i.mseccfg.rlb === 1'b1 && csr_pmp_i.cfg[region].lock === 1'b1 ##1 + $changed(csr_pmp_i.cfg[region].lock) + ); + + cov_rlb_locked_rules_can_modify_exec : cover property ( + csr_pmp_i.mseccfg.rlb === 1'b1 && csr_pmp_i.cfg[region].lock === 1'b1 ##1 + $changed(csr_pmp_i.cfg[region].exec) + ); + + cov_rlb_locked_rules_can_modify_mode : cover property ( + csr_pmp_i.mseccfg.rlb === 1'b1 && csr_pmp_i.cfg[region].lock === 1'b1 ##1 + $changed(csr_pmp_i.cfg[region].mode) + ); + + cov_rlb_locked_rules_can_modify_write : cover property ( + csr_pmp_i.mseccfg.rlb === 1'b1 && csr_pmp_i.cfg[region].lock === 1'b1 ##1 + $changed(csr_pmp_i.cfg[region].write) + ); + + cov_rlb_locked_rules_can_modify_read : cover property ( + csr_pmp_i.mseccfg.rlb === 1'b1 && csr_pmp_i.cfg[region].lock === 1'b1 ##1 + $changed(csr_pmp_i.cfg[region].read) + ); + + cov_rlb_locked_rules_can_remove : cover property ( + csr_pmp_i.mseccfg.rlb === 1'b1 && + csr_pmp_i.cfg[region].lock == 1'b1 && + csr_pmp_i.cfg[region].mode != PMP_MODE_OFF ##1 + csr_pmp_i.cfg[region].mode === PMP_MODE_OFF + ); + + // Adding an M-mode-only or a locked Shared-Region rule with executable privileges is not possible and + // such pmpcfg writes are ignored, leaving pmpcfg unchanged. This restriction can be temporarily lifted + // e.g. during the boot process, by setting mseccfg.RLB. + // (vplan:ExecIgnored) + a_mmode_only_or_shared_executable_ignore: assert property ( + csr_pmp_i.mseccfg.mml === 1'b1 && csr_pmp_i.mseccfg.rlb === 1'b0 |=> + $stable(csr_pmp_i.cfg[region]) + or + not ($changed(csr_pmp_i.cfg[region]) ##0 + csr_pmp_i.cfg[region].lock === 1'b1 ##0 + csr_pmp_i.cfg[region].read === 1'b0 ##0 + csr_pmp_i.cfg[region].write || csr_pmp_i.cfg[region].exec) + ) else `uvm_error(info_tag, "certain rules can't be added"); + + cov_mmode_only_or_shared_executable: cover property ( + csr_pmp_i.mseccfg.mml === 1'b1 && csr_pmp_i.mseccfg.rlb === 1'b1 + ##1 + $changed(csr_pmp_i.cfg[region]) ##0 + csr_pmp_i.cfg[region].lock === 1'b1 ##0 + csr_pmp_i.cfg[region].read === 1'b0 ##0 + csr_pmp_i.cfg[region].write || csr_pmp_i.cfg[region].exec + ); + end endgenerate + + // Validate PMP mode settings (Not a vplan item) + generate for (genvar region = 0; region < PMP_NUM_REGIONS; region++) begin: gen_matchmode + a_matchmode: assert property ( + csr_pmp_i.cfg[region].mode inside { + PMP_MODE_OFF, + PMP_MODE_TOR, + PMP_MODE_NA4, + PMP_MODE_NAPOT + } + ) else `uvm_error(info_tag, "pmp mode must be supported"); + end endgenerate + + generate if (PMP_NUM_REGIONS > 0) begin : gen_pmp_assert + // Check output vs model (Myriad vplan items) + a_accept_only_legal : assert property ( + (pmp_req_err_o === 1'b0) |-> match_status.is_access_allowed + ) else `uvm_error(info_tag, "mismatch, PMP allow must match model"); + a_deny_only_illegal : assert property ( + pmp_req_err_o |-> (match_status.is_access_allowed === 1'b0) + ) else `uvm_error(info_tag, "mismatch, PMP deny must match model"); + + // Assert that only one (or none) valid access reason can exist for any given access (Not a vplan item) + a_unique_access_allowed_reason: assert property ( + $countones(match_status.val_access_allowed_reason) <= 1 + ) else `uvm_error(info_tag, "there can only be 1 accept reason"); + + // Validate privilege level (Not a vplan item) + a_privmode: assert property ( + priv_lvl_i inside { + PRIV_LVL_M, + PRIV_LVL_U + } + ) else `uvm_error(info_tag, "the privilege mode must be supported"); + + + // Validate access type (TODO:silabs-robin make it a vplan item) + + if (IS_INSTR_SIDE) begin: gen_req_type_instr + a_req_type_instr: assert property ( + pmp_req_type_i inside { + PMP_ACC_EXEC + } + ) else `uvm_error(info_tag, "instr-side access must be execution"); + end : gen_req_type_instr + + if (!IS_INSTR_SIDE) begin: gen_req_type_data + a_req_type_data: assert property ( + pmp_req_type_i inside { + PMP_ACC_READ, + PMP_ACC_WRITE + } + ) else `uvm_error(info_tag, "data-side access must be loadstore"); + end : gen_req_type_data + + + // SMEPMP 2b: When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then + // mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset. + // + // In other words: mseccfg.RLB = 0 and pmpcfg.L = 1 in any rule or entry (including disabled), + // mseccfg.RLB remains 0 and does not change until PMP reset. + // (vplan:RemainZero) + a_rlb_never_fall_while_locked: assert property ( + csr_pmp_i.mseccfg.rlb === 1'b0 && match_status.is_any_locked |=> + $stable(csr_pmp_i.mseccfg.rlb) + ) else `uvm_error(info_tag, "RLB must remain off after it is locked"); + + // SMEPMP 3: On mseccfg we introduce a field in bit 1 called Machine Mode Whitelist Policy (mseccfg.MMWP). + // This is a sticky bit, meaning that once set it cannot be unset until a PMP reset. + // (vplan:WhiteList:StickyUntilReset) + a_mmwp_never_fall_until_reset: assert property ( + csr_pmp_i.mseccfg.mmwp === 1'b1 |=> + $stable(csr_pmp_i.mseccfg.mmwp) + ) else `uvm_error(info_tag, "MMWP is sticky high"); + + // SMEPMP 4: On mseccfg we introduce a field in bit 0 called Machine Mode Lockdown (mseccfg.MML). This is a + // sticky bit, meaning that once set it cannot be unset until a PMP reset. + // (vplan:LockdownGeneral:StickyUntilReset) + a_mml_never_fall_until_reset: assert property ( + csr_pmp_i.mseccfg.mml === 1'b1 |=> + $stable(csr_pmp_i.mseccfg.mml) + ) else `uvm_error(info_tag, "MML is sticky high"); + + // U-mode fails if no match (vplan:UmodeNomatch) + a_nomatch_umode_fails: assert property ( + priv_lvl_i == PRIV_LVL_U && match_status.is_matched == 1'b0 |-> + pmp_req_err_o ^ match_status.is_dm_override + ) else `uvm_error(info_tag, "non-matched umode access must fail"); + + // M-mode fails if: no match, and "mseccfg.MMWP" (vplan:WhiteList:Denied) + a_nomatch_mmode_mmwp_fails: assert property ( + (priv_lvl_i == PRIV_LVL_M) && + !match_status.is_matched && + csr_pmp_i.mseccfg.mmwp + |-> + pmp_req_err_o ^ match_status.is_dm_override + ) else `uvm_error(info_tag, "non-matched mmode access must fail when MMWP"); + + // U-mode or L=1 succeed only if RWX (vplan:RwxUmode) + a_uorl_onlyif_rwx: assert property ( + //TODO:silabs-robin Why, 'L=1' in comment, but 'is_matched' in code? + ( priv_lvl_i == PRIV_LVL_U || match_status.is_matched == 1'b1 ) && !pmp_req_err_o + |-> + match_status.is_rwx_ok || match_status.is_dm_override + ) else `uvm_error(info_tag, "RWX must agree for allowing umode and L"); + + // After a match, LRWX determines access (vplan:LrwxDetermines) + a_lrwx_aftermatch: assert property ( + //TODO:silabs-robin Why, "LRWX" in comment, but "rwx" in code? + match_status.is_matched == 1'b1 && !pmp_req_err_o |-> + match_status.is_rwx_ok || match_status.is_dm_override + ) else `uvm_error(info_tag, "LRWX must agree for allowing matched access"); + + // SMEPMP 1: The reset value of mseccfg is implementation-specific, otherwise if backwards + // compatibility is a requirement it should reset to zero on hard reset. + // (vplan:MsecCfg:ResetValue) + a_mseccfg_reset_val: assert property ( + $rose(rst_n) |-> csr_pmp_i.mseccfg === PMP_MSECCFG_RV + ) else `uvm_error(info_tag, "mseccfg must be reset correctly"); + end endgenerate + + + // Denied accesses don't reach the bus, or don't retire (instr-side) (vplan:SuppressReq) + + if (IS_INSTR_SIDE) begin: gen_supress_req_instr + property p_suppress_req_instr; + logic [31:0] addr = 0; + + ( + // Addr denied, but retires + pmp_req_err_o ##0 + (1, addr = pmp_req_addr_i[31:0]) ##0 + ((rvfi_valid && (rvfi_pc_rdata == addr)) [->1]) + ) + implies + ( + ( + // Doesn't reach bus, until retirement + ( + !(obi_req && (obi_addr == addr)) || // (Forbidden addr doesn't reach bus) + $past(obi_req && !obi_gnt) // (Excuse ongoing remnant) + ) + throughout + ((rvfi_valid && (rvfi_pc_rdata == addr)) [->1]) + ) + or + ( + // ...or, re-attempt got permission + (!pmp_req_err_o && (pmp_req_addr_i[31:2] == addr[31:2])) + within + ((rvfi_valid && (rvfi_pc_rdata == addr)) [->1]) + ) + ) + ; + endproperty : p_suppress_req_instr + + a_suppress_req_instr: assert property ( + p_suppress_req_instr + ) else `uvm_error(info_tag, "denied ifetch must refetch or not retire"); + end + + + // Denied accesses don't reach the bus (data-side) (vplan:SuppressReq) + + if (!IS_INSTR_SIDE) begin: gen_supress_req_data + property p_suppress_req_data; + logic [31:0] addr; + + // When "addr" is denied + pmp_req_err_o ##0 + (1, addr = pmp_req_addr_i[31:0]) + + |-> + + ( + !obi_req ^ // OBI is quelled + ($past(obi_req && !obi_gnt) && (obi_addr == addr)) ^ // (...or has leftovers) + (obi_req && (obi_addr != addr)) // (...or does something completely different + ) + until + ( + // New attempt, got permission + (pmp_req_addr_i == addr) && + !pmp_req_err_o + // Note: Can add timeout if proven to be resource-hungry + ) + ; + endproperty : p_suppress_req_data + + a_suppress_req_data: assert property ( + p_suppress_req_data + ) else `uvm_error(info_tag, "denied data access doesn't reach bus"); + // TODO:silabs-robin Add covers, or get reviews, and become convinced this is "bullet proof". + end + + +endmodule : uvmt_cv32e40s_pmp_assert + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmprvfi_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmprvfi_assert.sv new file mode 100644 index 0000000000..7384639c0b --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmprvfi_assert.sv @@ -0,0 +1,978 @@ +// Copyright 2022 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +`default_nettype none + + +module uvmt_cv32e40s_pmprvfi_assert + import cv32e40s_pkg::*; + import support_pkg::*; + import uvm_pkg::*; + import uvma_rvfi_pkg::*; + import uvma_rvfi_pkg::EXC_CAUSE_INSTR_BUS_FAULT; + import uvma_rvfi_pkg::EXC_CAUSE_INSTR_INTEGRITY_FAULT; + import uvmt_cv32e40s_base_test_pkg::*; +#( + parameter int PMP_GRANULARITY = 0, + parameter int PMP_NUM_REGIONS = 0 +)( + // Clock and Reset + input wire clk_i, + input wire rst_ni, + + //RVFI INSTR IF + uvma_rvfi_instr_if_t rvfi_if, + // RVFI + input wire rvfi_valid, + input wire [31:0] rvfi_insn, + input wire [ 1:0] rvfi_mode, + input wire rvfi_trap_t rvfi_trap, + input wire [ 4:0] rvfi_rd_addr, + input wire [31:0] rvfi_rd_wdata, + input wire [ 4:0] rvfi_rs1_addr, + input wire [31:0] rvfi_rs1_rdata, + input wire [31:0] rvfi_pc_rdata, + input wire [31:0] rvfi_mem_addr, + input wire [ 3:0] rvfi_mem_wmask, + input wire [ 3:0] rvfi_mem_rmask, + + // RVFI CSR + //(pmpcfg) + input wire [PMP_MAX_REGIONS/4-1:0][31:0] rvfi_csr_pmpcfg_rdata, + input wire [PMP_MAX_REGIONS/4-1:0][31:0] rvfi_csr_pmpcfg_wdata, + input wire [PMP_MAX_REGIONS/4-1:0][31:0] rvfi_csr_pmpcfg_wmask, + //(pmpaddr) + input wire [PMP_MAX_REGIONS-1:0] [31:0] rvfi_csr_pmpaddr_rdata, + input wire [PMP_MAX_REGIONS-1:0] [31:0] rvfi_csr_pmpaddr_wdata, + input wire [PMP_MAX_REGIONS-1:0] [31:0] rvfi_csr_pmpaddr_wmask, + //(mseccfg[h]) + input wire [31:0] rvfi_csr_mseccfg_rdata, + input wire [31:0] rvfi_csr_mseccfg_wdata, + input wire [31:0] rvfi_csr_mseccfg_wmask, + input wire [31:0] rvfi_csr_mseccfgh_rdata, + input wire [31:0] rvfi_csr_mseccfgh_wdata, + input wire [31:0] rvfi_csr_mseccfgh_wmask, + //(mstatus) + input wire [31:0] rvfi_csr_mstatus_rdata, + //(jvt) + input wire [31:0] rvfi_csr_jvt_rdata, + + // Debug + input wire rvfi_dbg_mode +); + + + // Defines + + `define max(a,b) ((a) > (b) ? (a) : (b)) + + string info_tag = "CV32E40S_PMPRVFI_ASSERT"; + + localparam logic [1:0] MODE_U = 2'b 00; + localparam logic [1:0] MODE_M = 2'b 11; + localparam logic [2:0] DBG_TRIGGER = 3'd 2; + localparam int NUM_CFG_REGS = 16; + localparam int NUM_ADDR_REGS = 64; + localparam int CSRADDR_FIRST_PMPCFG = 12'h 3A0; + localparam int CSRADDR_FIRST_PMPADDR = 12'h 3B0; + localparam int CSRADDR_MSECCFG = 12'h 747; + + typedef struct packed { + logic pc_lower; + logic pc_upper; + logic tablejump; + logic mret_pointer; + } denial_reasons_t; + + + // Defaults + + default clocking @(posedge clk_i); endclocking + default disable iff !(rst_ni); + + + // Helper signals + + wire is_rvfi_csr_instr = + rvfi_valid && + (rvfi_insn[6:0] == 7'b 1110011) && + (rvfi_insn[14:12] inside {1, 2, 3, 5, 6, 7}); + + wire is_rvfi_exception = + rvfi_valid && + rvfi_trap.trap && + rvfi_trap.exception; + + wire is_rvfi_exc_ill_instr = + is_rvfi_exception && + (rvfi_trap.exception_cause == EXC_CAUSE_ILLEGAL_INSTR); + + wire is_rvfi_exc_instr_acc_fault = + is_rvfi_exception && + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_ACC_FAULT); + + wire is_rvfi_exc_instr_bus_fault= + is_rvfi_exception && + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_BUS_FAULT); + + wire is_rvfi_exc_instr_chksum_fault= + is_rvfi_exception && + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_INTEGRITY_FAULT); + + wire is_rvfi_dbg_trigger = + rvfi_valid && + rvfi_trap.debug && + (rvfi_trap.debug_cause == DBG_TRIGGER); + + wire is_rvfi_csr_read_instr = + is_rvfi_csr_instr && + rvfi_rd_addr; + + wire is_rvfi_csr_write_instr = + is_rvfi_csr_instr && + !((rvfi_insn[13:12] inside {2'b 10, 2'b 11}) && !rvfi_rs1_addr); // CSRRS/C[I] w/ rs1=x0/0 + + wire [1:0] rvfi_effective_mode = + rvfi_csr_mstatus_rdata[17] ? // "mstatus.MPRV", modify privilege? + rvfi_csr_mstatus_rdata[12:11] : // "mstatus.MPP", loadstores act as if "mode==MPP" + rvfi_mode; // Else, act as actual mode + + wire [31:0] rvfi_mem_upperaddr = + (rvfi_mem_rmask[3] || rvfi_mem_wmask[3]) ? ( + rvfi_mem_addr + 3 + ) : ( + (rvfi_mem_rmask[2] || rvfi_mem_wmask[2]) ? ( + rvfi_mem_addr + 2 + ) : ( + (rvfi_mem_rmask[1] || rvfi_mem_wmask[1]) ? ( + rvfi_mem_addr + 1 + ) : ( + rvfi_mem_addr + ) + ) + ); + + denial_reasons_t denial_reasons; + always_comb begin + // WARNING: Some of these are approximations. Useful in some scenarios. + + denial_reasons.pc_lower = !match_status_instr.is_access_allowed; + + denial_reasons.pc_upper = ( + rvfi_if.is_split_instrtrans && + !match_status_upperinstr.is_access_allowed + //TODO:WARNING:silabs-robin Assert, low word match obi if no lower fault. + ); + + denial_reasons.tablejump = ( + rvfi_if.is_tablejump_raw && + !match_status_jvt.is_access_allowed + ); + + denial_reasons.mret_pointer = + rvfi_if.match_instr_raw(rvfi_if.INSTR_OPCODE_MRET, rvfi_if.INSTR_MASK_FULL); + end + + logic is_access_allowed; + always_comb begin + is_access_allowed = + !denial_reasons.pc_lower && + !denial_reasons.pc_upper; + // Note: This is incomplete but useful. Lacks cm.jt, mret ptr, etc. + end + + logic [31:0] jvt_addr; + always_comb begin + jvt_addr = get_jvt_addr_f(rvfi_if.rvfi_insn, rvfi_csr_jvt_rdata); + end + + pmp_csr_t pmp_csr_rvfi_rdata; + pmp_csr_t pmp_csr_rvfi_wdata; + pmp_csr_t pmp_csr_rvfi_wmask; + for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin: gen_pmp_csr_readout + localparam pmpcfg_reg_i = i / 4; + localparam pmpcfg_field_hi = (8 * (i % 4)) + 7; + localparam pmpcfg_field_lo = (8 * (i % 4)); + + assign pmp_csr_rvfi_rdata.cfg[i] = rvfi_csr_pmpcfg_rdata[pmpcfg_reg_i][pmpcfg_field_hi : pmpcfg_field_lo]; + assign pmp_csr_rvfi_wdata.cfg[i] = rvfi_csr_pmpcfg_wdata[pmpcfg_reg_i][pmpcfg_field_hi : pmpcfg_field_lo]; + assign pmp_csr_rvfi_wmask.cfg[i] = rvfi_csr_pmpcfg_wmask[pmpcfg_reg_i][pmpcfg_field_hi : pmpcfg_field_lo]; + + assign pmp_csr_rvfi_rdata.addr[i] = {rvfi_csr_pmpaddr_rdata[i], 2'b 00}; + assign pmp_csr_rvfi_wdata.addr[i] = {rvfi_csr_pmpaddr_wdata[i], 2'b 00}; + assign pmp_csr_rvfi_wmask.addr[i] = {rvfi_csr_pmpaddr_wmask[i], 2'b 00}; + end + assign pmp_csr_rvfi_rdata.mseccfg = rvfi_csr_mseccfg_rdata; + assign pmp_csr_rvfi_wdata.mseccfg = rvfi_csr_mseccfg_wdata; + assign pmp_csr_rvfi_wmask.mseccfg = rvfi_csr_mseccfg_wmask; + + + // Helper models + + match_status_t match_status_instr; + match_status_t match_status_data; + match_status_t match_status_upperinstr; + match_status_t match_status_upperdata; + match_status_t match_status_jvt; + + uvmt_cv32e40s_pmp_model #( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .DM_REGION_START (CORE_PARAM_DM_REGION_START), + .DM_REGION_END (CORE_PARAM_DM_REGION_END) + ) model_instr_i ( + .clk (clk_i), + .rst_n (rst_ni), + + .csr_pmp_i (pmp_csr_rvfi_rdata), + .debug_mode (rvfi_dbg_mode), + .pmp_req_addr_i ({2'b 00, rvfi_pc_rdata}), + .pmp_req_err_o ('Z), + .pmp_req_type_i (PMP_ACC_EXEC), + .priv_lvl_i (privlvl_t'(rvfi_mode)), + + .match_status_o (match_status_instr), + + .* + ); + + uvmt_cv32e40s_pmp_model #( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .DM_REGION_START (CORE_PARAM_DM_REGION_START), + .DM_REGION_END (CORE_PARAM_DM_REGION_END) + ) model_data_i ( + .clk (clk_i), + .rst_n (rst_ni), + + .csr_pmp_i (pmp_csr_rvfi_rdata), + .debug_mode (rvfi_dbg_mode), + .pmp_req_addr_i ({2'b 00, rvfi_mem_addr}), // TODO:WARNING:silabs-robin Multi-op instructions + .pmp_req_err_o ('Z), + .pmp_req_type_i (rvfi_if.is_store_instr ? PMP_ACC_WRITE : PMP_ACC_READ), + .priv_lvl_i (privlvl_t'(rvfi_effective_mode)), + + .match_status_o (match_status_data), + + .* + ); + + uvmt_cv32e40s_pmp_model #( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .DM_REGION_START (CORE_PARAM_DM_REGION_START), + .DM_REGION_END (CORE_PARAM_DM_REGION_END) + ) model_upperinstr_i ( + .clk (clk_i), + .rst_n (rst_ni), + + .csr_pmp_i (pmp_csr_rvfi_rdata), + .debug_mode (rvfi_dbg_mode), + .pmp_req_addr_i ({2'b 00, rvfi_if.rvfi_pc_upperrdata}), + .pmp_req_err_o ('Z), + .pmp_req_type_i (PMP_ACC_EXEC), + .priv_lvl_i (privlvl_t'(rvfi_mode)), + + .match_status_o (match_status_upperinstr), + + .* + ); + + uvmt_cv32e40s_pmp_model #( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .DM_REGION_START (CORE_PARAM_DM_REGION_START), + .DM_REGION_END (CORE_PARAM_DM_REGION_END) + ) model_upperdata_i ( + .clk (clk_i), + .rst_n (rst_ni), + + .csr_pmp_i (pmp_csr_rvfi_rdata), + .debug_mode (rvfi_dbg_mode), + .pmp_req_addr_i ({2'b 00, rvfi_mem_upperaddr}), // TODO:WARNING:silabs-robin Multi-op instructions + .pmp_req_err_o ('Z), + .pmp_req_type_i (rvfi_if.is_store_instr ? PMP_ACC_WRITE : PMP_ACC_READ), + .priv_lvl_i (privlvl_t'(rvfi_effective_mode)), + + .match_status_o (match_status_upperdata), + + .* + ); + + uvmt_cv32e40s_pmp_model #( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .DM_REGION_START (CORE_PARAM_DM_REGION_START), + .DM_REGION_END (CORE_PARAM_DM_REGION_END) + ) model_jvt_i ( + .clk (clk_i), + .rst_n (rst_ni), + + .csr_pmp_i (pmp_csr_rvfi_rdata), + .debug_mode (rvfi_dbg_mode), + .pmp_req_addr_i ({2'b 00, jvt_addr}), + .pmp_req_err_o ('Z), + .pmp_req_type_i (PMP_ACC_EXEC), + .priv_lvl_i (privlvl_t'(rvfi_mode)), + + .match_status_o (match_status_jvt), + + .* + ); + + var [31:0] clk_cnt; + always @(posedge clk_i, negedge rst_ni) begin + if (rst_ni == 0) begin + clk_cnt <= 32'd 1; + end else if (clk_cnt != '1) begin + clk_cnt <= clk_cnt + 32'd 1; + end + end + + + // Assertions: + + + // PMP CSRs only accessible from M-mode (vplan:Csrs:MmodeOnly) + + sequence seq_csrs_mmode_only_ante; + is_rvfi_csr_instr && + (rvfi_mode == MODE_U) && + (rvfi_insn[31:20] inside {['h3A0 : 'h3EF], 'h747, 'h757}) //PMP regs + ; + endsequence : seq_csrs_mmode_only_ante + + a_csrs_mmode_only: assert property ( + seq_csrs_mmode_only_ante + |-> + is_rvfi_exc_ill_instr || + is_rvfi_exc_instr_bus_fault || + is_rvfi_exc_instr_chksum_fault || + is_rvfi_exc_instr_acc_fault || + is_rvfi_dbg_trigger + ) else `uvm_error(info_tag, "PMP CSRs are illegal to access from umode"); + + cov_csrs_mmode_only: cover property ( + // Want to see "the real cause" (ill exc) finishing this property + seq_csrs_mmode_only_ante ##0 is_rvfi_exc_ill_instr + ); + + + // NAPOT, some bits read as ones, depending on G (vplan:NapotOnes) + + if (PMP_GRANULARITY >= 2) begin: gen_napot_ones_g2 + //TODO:INFO:silabs-robin no magic numbers + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_napot_ones_i + a_napot_ones: assert property ( + rvfi_valid && + pmp_csr_rvfi_rdata.cfg[i].mode[1] + |-> + (pmp_csr_rvfi_rdata.addr[i][PMP_GRANULARITY:2] == '1) + ) else `uvm_error(info_tag, "NAPOT LSBs should read as all 1s"); + + cov_napot_ones: cover property ( + // The ones doesn't have to extend past the required part + rvfi_valid && + pmp_csr_rvfi_rdata.cfg[i].mode[1] && + (pmp_csr_rvfi_rdata.addr[i][PMP_GRANULARITY+1] != 1'b 1) + // Note, this cover only checks part of what an assert could + ); + end + end + + + // OFF/TOR, some bits read as zeros, depending on G (vplan:AllZeros) + + if (PMP_GRANULARITY >= 1) begin: gen_all_zeros_g1 + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_all_zeros_i + a_all_zeros: assert property ( + rvfi_valid && + (pmp_csr_rvfi_rdata.cfg[i].mode[1] === 1'b 0) + |-> + (pmp_csr_rvfi_rdata.addr[i][PMP_GRANULARITY-1:0] == '0) + ) else `uvm_error(info_tag, "TOR/OFF LSBs should read as all 0s"); + end + end + + + // Software-view on PMP CSRs matches RVFI-view (Not a vplan item) + + for (genvar i = 0; i < NUM_CFG_REGS; i++) begin: gen_swview_cfg + a_pmpcfg_swview: assert property ( + is_rvfi_csr_read_instr && + (rvfi_insn[31:20] == (CSRADDR_FIRST_PMPCFG + i)) + |-> + (rvfi_rd_wdata == rvfi_csr_pmpcfg_rdata[i]) + ) else `uvm_error(info_tag, "RVFI data should be 'observable via the ISA'"); + end + + for (genvar i = 0; i < NUM_ADDR_REGS; i++) begin: gen_swview_addr + a_pmpaddr_swview: assert property ( + is_rvfi_csr_read_instr && + (rvfi_insn[31:20] == (CSRADDR_FIRST_PMPADDR + i)) + |-> + (rvfi_rd_wdata == rvfi_csr_pmpaddr_rdata[i]) + ) else `uvm_error(info_tag, "RVFI data should be 'observable via the ISA'"); + end + + + // Software views do not change underlying register value (vplan:StorageUnaffected) + + property p_storage_unaffected(i); + logic [33:0] pmpaddr; + accept_on ( + // (A new write resets this behavior) + is_rvfi_csr_write_instr && + (rvfi_insn[31:20] == (CSRADDR_FIRST_PMPADDR + i)) + ) + rvfi_valid ##0 + pmp_csr_rvfi_rdata.cfg[i].mode[1] ##0 // NAPOT/NA4 + (1, pmpaddr = pmp_csr_rvfi_rdata.addr[i]) // (Save pmpaddr) + ##1 + (rvfi_valid [->1]) ##0 + (pmp_csr_rvfi_rdata.cfg[i].mode[1] == 1'b 0) // TOR/OFF + // (Could cover rdata being different than pmpaddr) + ##1 + (rvfi_valid [->1]) ##0 + pmp_csr_rvfi_rdata.cfg[i].mode[1] // NAPOT/NA4 + |-> + (pmp_csr_rvfi_rdata.addr[i] == pmpaddr); // (Unchanged pmpaddr?) + // Note, this _can_ be generalized more, but at a complexity/readability cost + endproperty : p_storage_unaffected + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_storage_unaffected + a_storage_unaffected: assert property ( + p_storage_unaffected(i) + ) else `uvm_error(info_tag, "PMP mode change shouldn't change addresses"); + end + + + // Software-view can read the granularity level (vplan:GranularityDetermination) + + if (PMP_NUM_REGIONS) begin: gen_granularity_determination + a_granularity_determination: assert property ( + (is_rvfi_csr_instr && (rvfi_insn[14:12] == 3'b 001)) && // CSRRW instr, + (rvfi_insn[31:20] == (CSRADDR_FIRST_PMPADDR + 0)) && // to a "pmpaddr" CSR, + ((rvfi_rs1_rdata == '1) && rvfi_rs1_addr) && // writing all ones. + (pmp_csr_rvfi_rdata.cfg[0] == '0) && // Related cfg is 0, + (pmp_csr_rvfi_rdata.cfg[0+1] == '0) && // above cfg is 0. + !rvfi_trap // (Trap doesn't meddle.) + ##1 (rvfi_valid [->1]) + |-> + (rvfi_csr_pmpaddr_rdata[0][31:PMP_GRANULARITY] == '1) && + ( + (rvfi_csr_pmpaddr_rdata[0][`max(PMP_GRANULARITY-1, 0) : 0] == '0) ^ + (PMP_GRANULARITY == 0) + ) + // Note: _Can_ be generalized for all i + ) else `uvm_error(info_tag, "SW-visible granularity must match G"); + end + + + // Locking is forever (vplan:LockingAndPrivmode:UntilReset) + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_until_reset + a_until_reset: assert property ( + pmp_csr_rvfi_rdata.cfg[i].lock && + !pmp_csr_rvfi_rdata.mseccfg.rlb + |-> + always pmp_csr_rvfi_rdata.cfg[i].lock + ) else `uvm_error(info_tag, "locked configs must remain locked"); + end + + + // Stickiness isn't effectuated before triggered (vplan:LockingBypass:UntilReset) + + property p_until_reset_notbefore(logic rlb); + $rose(rst_ni) ##0 + (rvfi_valid [->1]) ##0 // First retire + (is_rvfi_csr_write_instr && (rvfi_insn[14:12] == 3'b 001)) ##0 // ..."csrrw" + (rvfi_insn[31:20] == CSRADDR_MSECCFG) ##0 // ...to mseccfg + !rvfi_trap ##0 + (rvfi_rs1_rdata[2] == rlb) // (Write-attempt's data) + |-> + pmp_csr_rvfi_wmask.mseccfg.rlb && // Must attempt + (pmp_csr_rvfi_wdata.mseccfg.rlb == rlb) // Must succeed + ; + endproperty : p_until_reset_notbefore + + a_until_reset_notbefore_0: assert property ( + p_until_reset_notbefore(1'b 0) + ) else `uvm_error(info_tag, "RLB must be changeable after reset"); + + a_until_reset_notbefore_1: assert property ( + p_until_reset_notbefore(1'b 1) + ) else `uvm_error(info_tag, "RLB must be changeable after reset"); + + + // Locked entries (vplan:IgnoreWrites, vplan:IgnoreTor) + + // Locked entries, ignore pmpicfg/pmpaddri writes + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_ignore_writes_notrap + // "Ignored writes" don't trap: + a_ignore_writes_notrap: assert property ( + is_rvfi_csr_write_instr && + (rvfi_insn[31:20] inside {(CSRADDR_FIRST_PMPADDR + i), (CSRADDR_FIRST_PMPCFG + i)}) && + (pmp_csr_rvfi_rdata.cfg[i].lock && !pmp_csr_rvfi_rdata.mseccfg.rlb) && + (rvfi_mode == MODE_M) + |-> + (rvfi_trap.exception_cause != EXC_CAUSE_ILLEGAL_INSTR) + ) else `uvm_error(info_tag, "writing to locked entries shouldn't except"); + end + + // Locked entries, ignore pmpicfg/pmpaddri writes + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_ignore_writes_nochange + // Ignored writes means stable data + a_ignore_writes_nochange: assert property ( + rvfi_valid && + (pmp_csr_rvfi_rdata.cfg[i].lock && !pmp_csr_rvfi_rdata.mseccfg.rlb) + |=> + always ( + $stable(pmp_csr_rvfi_rdata.cfg[i]) && + $stable(pmp_csr_rvfi_rdata.addr[i]) + ) + ) else `uvm_error(info_tag, "locked entries must never change"); + end + + // Locked entries, ignore pmpicfg/pmpaddri writes + for (genvar i = 0; i < PMP_NUM_REGIONS - 1; i++) begin: gen_not_ignore_writes_torcfg + // We can see change even if "above config" is locked TOR + property p_not_ignore_writes_torcfg; + logic [7:0] cfg; + + rvfi_valid && + pmp_csr_rvfi_rdata.cfg[i+1].lock && + (pmp_csr_rvfi_rdata.cfg[i+1].mode == PMP_MODE_TOR) ##0 + (1, cfg = pmp_csr_rvfi_rdata.cfg[i]) + + ##1 + + (rvfi_valid [->1]) ##0 + (pmp_csr_rvfi_rdata.cfg[i] != cfg) + ; + endproperty : p_not_ignore_writes_torcfg + + cov_not_ignore_writes_torcfg: cover property ( + p_not_ignore_writes_torcfg + ); + end + + + // Written cfgs are legal + // (vplan:LegalRwx, vplan:Na4Unselectable, vplan:IgnoreWrites, vplan:ExecIgnored, vplan:ExecRlb, vplan:Warl) + + // Written cfg is written as expected + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_cfg_expected + wire pmpncfg_t cfg_expected = rectify_cfg_write(pmp_csr_rvfi_rdata.cfg[i], rvfi_rs1_rdata[8*(i%4) +: 8]); + + sequence seq_cfg_expected_ante; + (is_rvfi_csr_write_instr && (rvfi_insn[14:12] == 3'b 001)) && // "csrrw" + (rvfi_insn[31:20] == (CSRADDR_FIRST_PMPCFG + i/4)) && // ...to cfg's csr + (!rvfi_trap) + // Note, this doesn't check csrr(s/c)[i] + ; + endsequence : seq_cfg_expected_ante + + a_cfg_expected: assert property ( + seq_cfg_expected_ante + |-> + (pmp_csr_rvfi_wmask.cfg[i] == 8'h FF) && // Must write cfg + (pmp_csr_rvfi_wdata.cfg[i] == cfg_expected) + ) else `uvm_error(info_tag, "updating cfgs must use legal values"); + + cov_not_ignore_writes_cfg_unlocked: cover property ( + !pmp_csr_rvfi_rdata.cfg[i].lock ##0 + seq_cfg_expected_ante + ); + + cov_cfg_expected_updates: cover property ( + (pmp_csr_rvfi_wdata.cfg[i] != pmp_csr_rvfi_rdata.cfg[i]) ##0 + seq_cfg_expected_ante + ); + + cov_cfg_expected_ones: cover property ( + seq_cfg_expected_ante ##0 + (rvfi_rs1_rdata[8*(i%4) +: 8] == '1) + ); + end + + + // Written cfg is legal (vplan "ExecIgnored", ...) + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_cfgwdata_legal + wire [7:0] rectified_cfg = rectify_cfg_write(pmp_csr_rvfi_rdata.cfg[i], pmp_csr_rvfi_wdata.cfg[i]); + + a_cfgwdata_legal: assert property ( + rvfi_valid && + pmp_csr_rvfi_wmask.cfg[i] + |-> + (pmp_csr_rvfi_wdata.cfg[i] == rectified_cfg) + ) else `uvm_error(info_tag, "updating cfgs must use legal values"); + end + + + // Read cfg is as expected + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_cfgrdata_expected + property p_cfgrdata_expected; + pmpncfg_t cfg_prev; + rvfi_valid ##0 + (1, cfg_prev = pmp_csr_rvfi_rdata.cfg[i]) + ##1 + (rvfi_valid [->1]) + |-> + (pmp_csr_rvfi_rdata.cfg[i] == rectify_cfg_write(cfg_prev, pmp_csr_rvfi_rdata.cfg[i])) + ; + endproperty : p_cfgrdata_expected + + a_cfgrdata_expected: assert property ( + p_cfgrdata_expected + ) else `uvm_error(info_tag, "read cfgs have legal values"); + end + + + // addr/addr-1 unlocked->unstable (vplan:NotIgnore) + + sequence seq_csrrw_pmpaddri (i); + (is_rvfi_csr_write_instr && (rvfi_insn[14:12] == 3'b 001)) && // "csrrw" + (rvfi_insn[31:20] == (CSRADDR_FIRST_PMPADDR + i)) && // ...to addr csr + (!rvfi_trap) + ; + endsequence : seq_csrrw_pmpaddri + + function automatic logic is_beneath_locktor (int cfg_idx); + if (cfg_idx < (PMP_NUM_REGIONS - 1)) begin + return ( + (pmp_csr_rvfi_rdata.cfg[cfg_idx + 1].mode == PMP_MODE_TOR) && + (pmp_csr_rvfi_rdata.cfg[cfg_idx + 1].lock) + ); + end else begin + return 0; + end + endfunction : is_beneath_locktor + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_addr_writes + a_addr_writeattempt: assert property ( + seq_csrrw_pmpaddri(i) + |-> + (pmp_csr_rvfi_wmask.addr[i][33:2] == 32'h FFFF_FFFF) + ) else `uvm_error(info_tag, "writing addr must attempt word write"); + + a_addr_nonlocked: assert property ( + seq_csrrw_pmpaddri(i) and + !pmp_csr_rvfi_rdata.cfg[i].lock and + !is_beneath_locktor(i) + |-> + (pmp_csr_rvfi_wdata.addr[i][33:2+PMP_GRANULARITY] + == rvfi_rs1_rdata[31:PMP_GRANULARITY]) + ) else `uvm_error(info_tag, "unlocked write must update as attempted"); + end + + for (genvar i = 1; i < PMP_NUM_REGIONS; i++) begin: gen_addr_tor + // (Special case of "a_addr_nonlocked") + a_addr_nonlocked_tor: assert property ( + seq_csrrw_pmpaddri(i - 1) and + (pmp_csr_rvfi_rdata.cfg[i].mode == PMP_MODE_TOR) and + !pmp_csr_rvfi_rdata.cfg[i ].lock and + !pmp_csr_rvfi_rdata.cfg[i-1].lock + |-> + (pmp_csr_rvfi_wdata.addr[i-1][33:2+PMP_GRANULARITY] + == rvfi_rs1_rdata[31:PMP_GRANULARITY]) + ) else `uvm_error(info_tag, "unlocked write must update beneath tor too"); + end + + + // RVFI: Reported CSR writes take effect (vplan:AffectSuccessors) + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_rvfi_csr_writes + // cfg: + property p_rvfi_cfg_writes; + logic [7:0] cfg, cfg_r, cfg_w; + rvfi_valid ##0 + (1, cfg_w = (pmp_csr_rvfi_wdata.cfg[i] & pmp_csr_rvfi_wmask.cfg[i])) ##0 + (1, cfg_r = (pmp_csr_rvfi_rdata.cfg[i] & ~pmp_csr_rvfi_wmask.cfg[i])) ##0 + (1, cfg = (cfg_r | cfg_w)) + ##1 (rvfi_valid [->1]) + |-> + (pmp_csr_rvfi_rdata.cfg[i] == cfg) + ; + endproperty : p_rvfi_cfg_writes + a_rvfi_cfg_writes: assert property ( + p_rvfi_cfg_writes + ) else `uvm_error(info_tag, "cfg updates must be present on next retire"); + + // addr: + property p_rvfi_addr_writes; + logic [31:0] addr, addr_r, addr_w; + rvfi_valid ##0 + (1, addr_w = (pmp_csr_rvfi_wdata.addr[i][33:2] & pmp_csr_rvfi_wmask.addr[i][33:2])) ##0 + (1, addr_r = (pmp_csr_rvfi_rdata.addr[i][33:2] & ~pmp_csr_rvfi_wmask.addr[i][33:2])) ##0 + (1, addr = (addr_r | addr_w)) + ##1 (rvfi_valid [->1]) + |-> + (pmp_csr_rvfi_rdata.addr[i][31+2:PMP_GRANULARITY+2] == addr[31:PMP_GRANULARITY]) + ; + endproperty : p_rvfi_addr_writes; + a_rvfi_addr_writes: assert property ( + p_rvfi_addr_writes + ) else `uvm_error(info_tag, "addr updates must be present on next retire"); + end + + + // Locked TOR, ignore i-1 addr writes (vplan:IgnoreTor) + + for (genvar i = 1; i < PMP_NUM_REGIONS; i++) begin: gen_ignore_tor + a_ignore_tor_stable: assert property ( + rvfi_valid && + (pmp_csr_rvfi_rdata.cfg[i].lock && !pmp_csr_rvfi_rdata.mseccfg.rlb) && + (pmp_csr_rvfi_rdata.cfg[i].mode == PMP_MODE_TOR) + |=> + always $stable(pmp_csr_rvfi_rdata.addr[i-1][31+2:PMP_GRANULARITY+2]) + ) else `uvm_error(info_tag, "TOR-locking must lock the subordinate addr"); + + a_ignore_tor_wdata: assert property ( + rvfi_valid && + (pmp_csr_rvfi_rdata.cfg[i].lock && !pmp_csr_rvfi_rdata.mseccfg.rlb) && + (pmp_csr_rvfi_rdata.cfg[i].mode == PMP_MODE_TOR) + |-> + (pmp_csr_rvfi_wmask.addr[i-1] == 0) || + (pmp_csr_rvfi_wdata.addr[i-1] == pmp_csr_rvfi_rdata.addr[i-1]) + ) else `uvm_error(info_tag, "TOR-locking forbids writing subordinate addr"); + end + + + // Expected response on missing execute permission (vplan:WaitUpdate, vplan:AffectSuccessors, myriad vplan items) + + a_noexec_musttrap: assert property ( + rvfi_valid && + !match_status_instr.is_access_allowed + |-> + rvfi_trap + // TODO:INFO:silabs-robin Can assert the opposite too? + ) else `uvm_error(info_tag, "on access denied we must trap"); + + a_noexec_cause: assert property ( + rvfi_valid && + !match_status_instr.is_access_allowed && + rvfi_trap.exception + |-> + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_ACC_FAULT) + // Note, if we implement etrigger etc then priority will change + ) else `uvm_error(info_tag, "on access denied the cause must match"); + + a_noexec_splittrap: assert property ( + rvfi_valid && + rvfi_if.is_split_instrtrans && + !match_status_upperinstr.is_access_allowed + |-> + rvfi_trap + ) else `uvm_error(info_tag, "on split-access denied we must trap"); + + + // Expected response on missing loadstore permission (vplan:WaitUpdate, vplan:AffectSuccessors) + + a_noloadstore_musttrap: assert property ( + rvfi_if.is_loadstore_instr && + !match_status_data.is_access_allowed + |-> + rvfi_trap + ) else `uvm_error(info_tag, "on access denied we must trap"); + + a_noloadstore_cause_load: assert property ( + rvfi_if.is_load_instr && + !match_status_data.is_access_allowed && + rvfi_trap.exception + |-> + (rvfi_trap.exception_cause == EXC_CAUSE_LOAD_ACC_FAULT) ^ + rvfi_if.is_deprioritized_load_acc_fault + ) else `uvm_error(info_tag, "on load denied the cause must match"); + + a_noloadstore_cause_store: assert property ( + rvfi_if.is_store_instr && + !match_status_data.is_access_allowed && + rvfi_trap.exception + |-> + (rvfi_trap.exception_cause == EXC_CAUSE_STORE_ACC_FAULT) ^ + rvfi_if.is_deprioritized_store_acc_fault + ) else `uvm_error(info_tag, "on store denied the cause must match"); + + a_noloadstore_splittrap: assert property ( + rvfi_valid && + rvfi_if.is_split_datatrans_intended && + !match_status_upperdata.is_access_allowed + |-> + rvfi_trap + ) else `uvm_error(info_tag, "on split-access denied we must trap"); + + //TODO:INFO:silabs-robin Could model "is_blocked |-> pma_deny || pmp_deny" etc + + + // RVFI must report what was allowed on the data bus (Not a vplan item) + + a_rvfi_mem_allowed_data: assert property ( + rvfi_if.is_mem_act_actual + |-> + match_status_data.is_access_allowed + ) else `uvm_error(info_tag, "Data trans first word access must be allowed"); + + a_rvfi_mem_allowed_upperdata: assert property ( + rvfi_if.is_split_datatrans_actual + |-> + match_status_upperdata.is_access_allowed + ) else `uvm_error(info_tag, "Data trans second word access must be allowed"); + + + // RVFI must report what was allowed on the instr bus (Not a vplan item) + + a_instr_prediction: assert property ( + rvfi_if.rvfi_valid + |-> + (rvfi_if.is_instr_acc_fault_pmp != is_access_allowed) || + (rvfi_if.is_instr_acc_fault_pmp && denial_reasons) || + rvfi_if.is_dbg_trg + //Would like "fault!=allowed". Alas, impractical. + ) else `uvm_error(info_tag, "RVFI PMP faults must match prediction"); + + a_instr_nofault_nopclower: assert property ( + rvfi_if.rvfi_valid && + !rvfi_if.is_instr_acc_fault_pmp + |-> + !denial_reasons.pc_lower || + rvfi_if.is_dbg_trg + ) else `uvm_error(info_tag, "RVFI no fault, instr first word not denied"); + + a_instr_nofault_nopcupper: assert property ( + rvfi_if.rvfi_valid && + !rvfi_if.is_instr_acc_fault_pmp + |-> + !denial_reasons.pc_upper || + rvfi_if.is_dbg_trg + ) else `uvm_error(info_tag, "RVFI no fault, instr second word not denied"); + + a_instr_yesfault_yesdenial: assert property ( + rvfi_if.is_instr_acc_fault_pmp + |-> + denial_reasons + ) else `uvm_error(info_tag, "RVFI fault must be predicted"); + + a_instr_nodenial_nofault: assert property ( + !denial_reasons + |-> + !rvfi_if.is_instr_acc_fault_pmp + ) else `uvm_error(info_tag, "no prediction, no RVFI fault"); + + + // RWX has reservations (vplan:RwReserved) + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_rwx_mml + a_rwx_mml: assert property ( + !pmp_csr_rvfi_rdata.mseccfg.mml + |-> + (pmp_csr_rvfi_rdata.cfg[i][1:0] != 2'b 10) + ) else `uvm_error(info_tag, "'RW' cannot be 01"); + end + + + // RLB lifts restrictions (vplan:ExecRlb) + + for (genvar i = 0; i < PMP_NUM_REGIONS; i++) begin: gen_rlblifts_lockedexec + logic [31:0] csr_intended_wdata; + always_comb begin + csr_intended_wdata <= + rvfi_if.csr_intended_wdata( + ({24'd 0, pmp_csr_rvfi_rdata.cfg[i]} << 8*(i%4)), + (CSRADDR_FIRST_PMPCFG + (i / 3'd4)) + ); + end + wire pmpncfg_t cfg_attempt = csr_intended_wdata[32'd 8 * (i%4) +: 8]; + + sequence seq_rlblifts_lockedexec_ante; + pmp_csr_rvfi_rdata.mseccfg.rlb && + pmp_csr_rvfi_rdata.mseccfg.mml + ##0 + rvfi_if.is_csr_write(CSRADDR_FIRST_PMPCFG + (i / 3'd4)) && + !rvfi_trap && + !(PMP_GRANULARITY > 0 && cfg_attempt.mode == PMP_MODE_NA4) + ; + endsequence : seq_rlblifts_lockedexec_ante + + a_rlblifts_lockedexec: assert property ( + seq_rlblifts_lockedexec_ante + |-> + (pmp_csr_rvfi_wdata.cfg[i] == (cfg_attempt & 8'h 9F)) + ) else `uvm_error(info_tag, "with rlb, some illegal cfgs must be writable"); + // Note, "lockedexec" is just one case of a restriction that RLB lifts. + + end + + cov_rlb_mml: cover property ( + rvfi_valid && + pmp_csr_rvfi_rdata.mseccfg.rlb && + pmp_csr_rvfi_rdata.mseccfg.mml + ); + + + // Translate write-attempts to legal values + + function automatic pmpncfg_t rectify_cfg_write (pmpncfg_t cfg_pre, pmpncfg_t cfg_attempt); + pmpncfg_t cfg_rfied; + + // Initial assumption: Attempt is ok + cfg_rfied = cfg_attempt; + + // Pick "pre-state" where required + begin + // RWX collective WARL (vplan:LegalRwx) + if ((cfg_attempt[2:0] inside {2, 6}) && !pmp_csr_rvfi_rdata.mseccfg.mml) begin + cfg_rfied[2:0] = cfg_pre[2:0]; + end + + // NA4, G=0 (vplan:Na4Unselectable) + if ((PMP_GRANULARITY >= 1) && (cfg_attempt.mode == PMP_MODE_NA4)) begin + cfg_rfied.mode = cfg_pre.mode; + end + + // Locked config can't change (vplan:IgnoreWrites) + if (cfg_pre.lock && !pmp_csr_rvfi_rdata.mseccfg.rlb) begin + cfg_rfied = cfg_pre; + end + + // MML, no locked-executable (vplan:ExecIgnored, vplan:ExecRlb) + if ( + (pmp_csr_rvfi_rdata.mseccfg.mml && !pmp_csr_rvfi_rdata.mseccfg.rlb) && + ({cfg_attempt.lock, cfg_attempt.read, cfg_attempt.write, cfg_attempt.exec} + inside {4'b 1001, 4'b 1010, 4'b 1011, 4'b 1101}) + ) + begin + cfg_rfied = cfg_pre; + // TODO:WARNING:silabs-robin Test "a_cfg_expected" without this clause. + end + end + + // Tied zero (vplan:Warl) + cfg_rfied.zero0 = '0; + + return cfg_rfied; + endfunction : rectify_cfg_write + + +endmodule : uvmt_cv32e40s_pmprvfi_assert + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_rvfi_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_rvfi_assert.sv new file mode 100644 index 0000000000..4cc7f84419 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_rvfi_assert.sv @@ -0,0 +1,364 @@ +// Copyright 2022 Silicon Labs, Inc. +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +// Description: +// Sanity-checking behavior of "rvfi" and "rvfi_instr_if" helper logic. +// (Note: This does not replace the original "riscv_formal" assertions.) +// +// Rationale: +// We use these interfaces a lot to verify other features. +// But we need to know that these interfaces themselves can be trusted. + + +`default_nettype none + + +module uvmt_cv32e40s_rvfi_assert + import cv32e40s_pkg::*; + import uvm_pkg::*; + import uvma_rvfi_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import isa_decoder_pkg::*; +#( + parameter logic CLIC, + parameter int CLIC_ID_WIDTH +)( + input wire clk_i, + input wire rst_ni, + + input wire rvfi_valid, + input wire [ 4:0] rvfi_rs1_addr, + input wire [ 4:0] rvfi_rs2_addr, + input wire [31:0] rvfi_rs1_rdata, + input wire [31:0] rvfi_rs2_rdata, + input wire [ 2:0] rvfi_dbg, + input wire [31:0] rvfi_csr_dcsr_rdata, + input wire rvfi_trap_t rvfi_trap, + input wire rvfi_intr_t rvfi_intr, + input wire [31:0] rvfi_csr_mcause_wdata, + input wire [31:0] rvfi_csr_mcause_wmask, + input wire rvfi_dbg_mode, + //TODO:INFO:silabs-robin should replace the above with the interface + + uvma_rvfi_instr_if_t rvfi_if, + + input wire writebuf_valid_i, + input wire writebuf_ready_o, + + uvmt_cv32e40s_support_logic_module_o_if_t support_if +); + + default clocking @(posedge clk_i); endclocking + default disable iff !rst_ni; + + string info_tag = "CV32E40S_RVFI_ASSERT"; + + + // Helper signals + + logic was_rvfi_dbg_mode; + always @(posedge clk_i, negedge rst_ni) begin + if (rst_ni == 0) begin + was_rvfi_dbg_mode <= 0; + end else if (rvfi_valid) begin + was_rvfi_dbg_mode <= rvfi_dbg_mode; + end + end + + + // rs1/rs2 reset values + + property p_rs_resetvalue (addr, rdata); + $past(rst_ni == 0) ##0 + (rvfi_valid [->1]) ##0 + addr + |-> + (rdata == 0); // TODO:silabs-robin use "RF_REG_RV" + endproperty : p_rs_resetvalue + + a_rs1_resetvalue: assert property ( + p_rs_resetvalue(rvfi_rs1_addr, rvfi_rs1_rdata) + ) else `uvm_error(info_tag, "unexpected 'rs1' reset value"); + + a_rs2_resetvalue: assert property ( + p_rs_resetvalue(rvfi_rs2_addr, rvfi_rs2_rdata) + ) else `uvm_error(info_tag, "unexpected 'rs2' reset value"); + + + // RVFI debug cause matches dcsr debug cause + + a_dbg_cause_general: assert property ( + rvfi_valid && + rvfi_dbg && + !was_rvfi_dbg_mode + |-> + (rvfi_dbg == rvfi_csr_dcsr_rdata[8:6]) + ) else `uvm_error(info_tag, "'rvfi_dbg' did not match 'dcsr.cause'"); + + property p_dbg_cause_n (n); + rvfi_valid && + rvfi_dbg && + !was_rvfi_dbg_mode && + (rvfi_csr_dcsr_rdata[8:6] == n) + |-> + (rvfi_dbg == n); + endproperty : p_dbg_cause_n + + a_dbg_cause_ebreak: assert property ( + p_dbg_cause_n(1) + ) else `uvm_error(info_tag, "'rvfi_dbg' did not match 'dcsr.cause'"); + + a_dbg_cause_trigger: assert property ( + p_dbg_cause_n(2) + ) else `uvm_error(info_tag, "'rvfi_dbg' did not match 'dcsr.cause'"); + + a_dbg_cause_haltreq: assert property ( + p_dbg_cause_n(3) + ) else `uvm_error(info_tag, "'rvfi_dbg' did not match 'dcsr.cause'"); + + a_dbg_cause_step: assert property ( + p_dbg_cause_n(4) + ) else `uvm_error(info_tag, "'rvfi_dbg' did not match 'dcsr.cause'"); + + + // RVFI exception cause matches "mcause" + + wire logic [10:0] rvfi_mcause_exccode; + // Explicit truncation to avoid warning + assign rvfi_mcause_exccode = $bits(rvfi_mcause_exccode)'(rvfi_csr_mcause_wdata & rvfi_csr_mcause_wmask); + + a_exc_cause: assert property ( + rvfi_valid && + rvfi_trap.exception && + !rvfi_dbg_mode + |-> + (rvfi_trap.exception_cause == rvfi_mcause_exccode) + ) else `uvm_error(info_tag, "'exception_cause' must match 'mcause'"); + + + // RVFI exception clears 'mcause.interrupt' + + a_exc_mcause: assert property ( + rvfi_valid && + rvfi_trap.exception && + !rvfi_dbg_mode + |-> + (rvfi_csr_mcause_wmask[31] == 1'b 1) && + (rvfi_csr_mcause_wdata[31] == 1'b 0) + ) else `uvm_error(info_tag, "exceptions clear 'mcause.interrupt'"); + + + // RVFI interrupt cause matches legal causes + + if (!CLIC) begin: gen_legal_cause_clint + a_irq_cause_clint: assert property ( + rvfi_valid && + rvfi_intr.interrupt + |-> + (rvfi_intr.cause inside {3, 7, 11, [16:31], [1024:1027]}) + ) else `uvm_error(info_tag, "unexpected interrupt cause"); + end : gen_legal_cause_clint + + if (CLIC) begin: gen_legal_cause_clic + localparam logic [31:0] MAX_CLIC_ID = 2**CLIC_ID_WIDTH - 1; + + a_irq_cause_clic: assert property ( + rvfi_valid && + rvfi_intr.interrupt + |-> + (rvfi_intr.cause inside {[0:MAX_CLIC_ID], [1024:1027]}) + ) else `uvm_error(info_tag, "unexpected interrupt cause"); + end : gen_legal_cause_clic + + + // Reported interrupts are not made up + + a_intr_count: assert property ( + support_if.cnt_rvfi_irqs <= support_if.cnt_irq_ack + //Note: This is not comprehensive proof + ) else `uvm_error(info_tag, "rvfi_intr.interrupt over-reported"); + + + // Confirm that the counter is right. + + cov_cycle_cnt_1: cover property ( + rvfi_if.cycle_cnt == 1 + ); + + cov_cycle_cnt_2: cover property ( + rvfi_if.cycle_cnt ==2 + ); + + + // Exceptions/Interrupts/Debugs have a cause + + a_exceptions_cause: assert property ( + rvfi_valid && + rvfi_trap.exception + |-> + rvfi_trap.exception_cause + ) else `uvm_error(info_tag, "rvfi_trap exceptions must have a cause"); + + if (!CLIC) begin: gen_clint_cause + a_interrupts_cause: assert property ( + rvfi_valid && + rvfi_intr + |-> + rvfi_intr.cause + ) else `uvm_error(info_tag, "rvfi_intr interrupts must have a cause"); + end : gen_clint_cause + + a_debug_cause: assert property ( + rvfi_valid && + rvfi_trap.debug + |-> + rvfi_trap.debug_cause + ) else `uvm_error(info_tag, "rvfi_trap debugs must have a cause"); + + + // Synchronous handler had synchronous cause + + property p_sync_cause; + logic exception; + (rvfi_valid, exception = rvfi_trap.exception) + ##1 + (rvfi_valid [->1]) + |-> + (rvfi_intr.exception == exception) || + rvfi_intr.interrupt + ; + endproperty : p_sync_cause + + a_sync_cause: assert property ( + p_sync_cause + ) else `uvm_error(info_tag, "rvfi_intr.exception can't happen unannounced"); + + + // Trap handler is either sync/async + + a_handler_sync_or_async: assert property ( + rvfi_valid + |-> + !(rvfi_intr.exception && rvfi_intr.interrupt) + ) else `uvm_error(info_tag, "ambiguous handler cause"); + + + // Num mem accesses reflect actual bus + + var logic [31:0] rvfi_mem_count_c; + var logic [31:0] rvfi_mem_count_n; + var logic [31:0] rvfi_mem_new; + var logic [31:0] writebuf_req_count_c; + var logic [31:0] writebuf_req_count_n; + + a_obi_vs_rvfi: assert property ( + writebuf_req_count_c >= rvfi_mem_count_c + ) else `uvm_error(info_tag, "rvfi should not report bus transactions that didn't happen"); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (rst_ni == 0) begin + writebuf_req_count_c <= 0; + rvfi_mem_count_c <= 0; + end else begin + if (writebuf_req_count_n > writebuf_req_count_c) begin + writebuf_req_count_c <= writebuf_req_count_n; + end + + if (rvfi_mem_count_n > rvfi_mem_count_c) begin + rvfi_mem_count_c <= rvfi_mem_count_n; + end + end + end + + always_comb begin + writebuf_req_count_n = writebuf_req_count_c; + if (writebuf_valid_i && writebuf_ready_o) begin + writebuf_req_count_n = writebuf_req_count_c + 1; + end + + rvfi_mem_new = 0; + for (int i = 0; i < NMEM; i++) begin + rvfi_mem_new += |rvfi_if.rvfi_mem_wmask[i*XLEN/8+:XLEN/8] && rvfi_if.rvfi_valid; + rvfi_mem_new += |rvfi_if.rvfi_mem_rmask[i*XLEN/8+:XLEN/8] && rvfi_if.rvfi_valid; + end + rvfi_mem_count_n = rvfi_mem_count_c + rvfi_mem_new; + end + + + // Load Instructions + + a_isloadinstr_required: assert property ( + rvfi_if.rvfi_valid && + rvfi_if.rvfi_mem_rmask + |-> + rvfi_if.is_load_instr + ) else `uvm_error(info_tag, "rmask comes from loads"); + + a_isloadinstr_demands: assert property ( + rvfi_if.is_load_instr && + !rvfi_if.rvfi_trap + |-> + rvfi_if.rvfi_mem_rmask + ) else `uvm_error(info_tag, "successful loads have rmask"); + + a_isloadinstr_exception: assert property ( + rvfi_if.rvfi_valid + |-> + rvfi_if.is_load_instr || + !rvfi_if.is_load_acc_fault + ) else `uvm_error(info_tag, "!load->!exce, exce->load"); + + + // Store Instructions + + a_isstoreinstr_required: assert property ( + rvfi_if.rvfi_valid && + rvfi_if.rvfi_mem_wmask + |-> + rvfi_if.is_store_instr + ) else `uvm_error(info_tag, "wmask comes from stores"); + + a_isstoreinstrs_demands: assert property ( + rvfi_if.is_store_instr && + !rvfi_if.rvfi_trap + |-> + rvfi_if.rvfi_mem_wmask + ) else `uvm_error(info_tag, "successful stores have wmask"); + + a_isstoreinstr_exception: assert property ( + rvfi_if.rvfi_valid + |-> + rvfi_if.is_store_instr || + !rvfi_if.is_store_acc_fault + ) else `uvm_error(info_tag, "!store->!exce, exce->store"); + + + +// Disassembler + a_unknowninstr_trap: assert property ( + (rvfi_if.instr_asm.instr == UNKNOWN_INSTR) && rvfi_if.rvfi_valid + |-> + rvfi_if.rvfi_trap.trap + ) else `uvm_error(info_tag, "Unknown instruction is not trapped"); + + + +endmodule : uvmt_cv32e40s_rvfi_assert + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_rvfi_cov.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_rvfi_cov.sv new file mode 100644 index 0000000000..2219edef7c --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_rvfi_cov.sv @@ -0,0 +1,85 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +// Description: +// Coverage definitions for RVFI; mainly the support logic. +// +// Rationale: +// The RVFI support logic has many useful functions. +// They should be coverable in both formal and sim. +// They should be inspected in formal to see that they work as intended. + + +`default_nettype none + + +module uvmt_cv32e40s_rvfi_cov + import cv32e40s_pkg::*; +( + input wire clk_i, + input wire rst_ni, + + uvma_rvfi_instr_if_t rvfi_if +); + + + default clocking @(posedge clk_i); endclocking + default disable iff !rst_ni; + + + // Aliases + + let mem_rmask = rvfi_if.rvfi_mem_rmask; + let mem_wmask = rvfi_if.rvfi_mem_wmask; + + + // Mem access split in two OBI transactions + + cov_split_data: cover property ( + rvfi_if.is_split_datatrans_intended && + !rvfi_if.rvfi_trap + ); + + + // Pushpop instrs + + cov_pushpop: cover property ( + rvfi_if.is_pushpop && + !rvfi_if.rvfi_trap && + ((mem_rmask | mem_wmask) > 'h FF) + ); + + + // Table Jump + + cov_tablejump_notrap: cover property ( + rvfi_if.is_tablejump_raw && + !rvfi_if.rvfi_trap + ); + + cov_tablejump_exception: cover property ( + rvfi_if.is_tablejump_raw && + rvfi_if.rvfi_trap.exception + ); + + +endmodule : uvmt_cv32e40s_rvfi_cov + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv index da7868993a..da62400a07 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv @@ -22,7 +22,6 @@ `ifndef __UVMT_CV32E40S_TB_SV__ `define __UVMT_CV32E40S_TB_SV__ - /** * Module encapsulating the CV32E40S DUT wrapper, and associated SV interfaces. * Also provide UVM environment entry and exit points. @@ -32,13 +31,11 @@ module uvmt_cv32e40s_tb; import uvm_pkg::*; import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; import uvmt_cv32e40s_pkg::*; - import uvme_cv32e40s_pkg::*; - - // ENV (testbench) parameters - parameter int ENV_PARAM_INSTR_ADDR_WIDTH = 32; - parameter int ENV_PARAM_INSTR_DATA_WIDTH = 32; - parameter int ENV_PARAM_RAM_ADDR_WIDTH = 22; + `ifndef FORMAL + import rvviApiPkg::*; + `endif // Capture regs for test status from Virtual Peripheral in dut_wrap.mem_i bit tp; @@ -47,115 +44,201 @@ module uvmt_cv32e40s_tb; bit [31:0] evalue; // Agent interfaces - uvma_isacov_if isacov_if(); - uvma_clknrst_if clknrst_if(); // clock and resets from the clknrst agent - uvma_clknrst_if clknrst_if_iss(); - uvma_debug_if debug_if(); - uvma_interrupt_if interrupt_if(); - uvma_obi_memory_if obi_instr_if_i( - .clk(clknrst_if.clk), - .reset_n(clknrst_if.reset_n) + uvma_clknrst_if_t clknrst_if(); // clock and resets from the clknrst agent + uvma_clknrst_if_t clknrst_if_iss(); + uvma_debug_if_t debug_if(); + uvma_wfe_wu_if_t wfe_wu_if(); + uvma_interrupt_if_t interrupt_if(); + uvma_clic_if_t#( + .CLIC_ID_WIDTH(uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) + ) clic_if(); + uvma_obi_memory_if_t #( + .ADDR_WIDTH (ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH (ENV_PARAM_INSTR_DATA_WIDTH), + .ACHK_WIDTH (ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH (ENV_PARAM_INSTR_RCHK_WIDTH) + ) obi_instr_if ( + .clk (clknrst_if.clk), + .reset_n (clknrst_if.reset_n) ); - uvma_obi_memory_if obi_data_if_i( + + uvma_obi_memory_if_t #( + .ADDR_WIDTH (ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH (ENV_PARAM_DATA_DATA_WIDTH), + .ACHK_WIDTH (ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH (ENV_PARAM_DATA_RCHK_WIDTH) + ) obi_data_if( .clk(clknrst_if.clk), .reset_n(clknrst_if.reset_n) ); - uvma_fencei_if fencei_if_i( + uvma_fencei_if_t fencei_if( .clk(clknrst_if.clk), .reset_n(clknrst_if.reset_n) ); // DUT Wrapper Interfaces - uvmt_cv32e40s_vp_status_if vp_status_if(.tests_passed(), + uvmt_cv32e40s_vp_status_if_t vp_status_if(.tests_passed(), .tests_failed(), .exit_valid(), .exit_value()); // Status information generated by the Virtual Peripherals in the DUT WRAPPER memory. - uvme_cv32e40s_core_cntrl_if core_cntrl_if(); - uvmt_cv32e40s_core_status_if core_status_if(.core_busy(), + uvme_cv32e40s_core_cntrl_if_t core_cntrl_if(); + uvmt_cv32e40s_core_status_if_t core_status_if(.core_busy(), .sec_lvl()); // Core status outputs - /** - * DUT WRAPPER instance: - * This is an update of the riscv_wrapper.sv from PULP-Platform RI5CY project with - * a few mods to bring unused ports from the CORE to this level using SV interfaces. - */ - uvmt_cv32e40s_dut_wrap #( - .B_EXT (uvmt_cv32e40s_pkg::B_EXT), - .PMA_NUM_REGIONS (uvmt_cv32e40s_pkg::CORE_PARAM_PMA_NUM_REGIONS), - .PMA_CFG (uvmt_cv32e40s_pkg::CORE_PARAM_PMA_CFG), - .PMP_NUM_REGIONS (CORE_PARAM_PMP_NUM_REGIONS), - .INSTR_ADDR_WIDTH (ENV_PARAM_INSTR_ADDR_WIDTH), - .INSTR_RDATA_WIDTH (ENV_PARAM_INSTR_DATA_WIDTH), - .RAM_ADDR_WIDTH (ENV_PARAM_RAM_ADDR_WIDTH) - ) - dut_wrap ( - .clknrst_if(clknrst_if), - .interrupt_if(interrupt_if), - .vp_status_if(vp_status_if), - .core_cntrl_if(core_cntrl_if), - .core_status_if(core_status_if), - .obi_instr_if_i(obi_instr_if_i), - .obi_data_if_i(obi_data_if_i), - .fencei_if_i(fencei_if_i), - .*); + // RVVI SystemVerilog Interface + `ifndef FORMAL + rvviTrace #( .NHART(1), .RETIRE(1)) rvvi_if(); + uvmt_imperas_dv_if_t imperas_dv_if(); + `endif + + + // "dut_wrap" + + uvmt_cv32e40s_dut_wrap #( + .INSTR_ADDR_WIDTH (ENV_PARAM_INSTR_ADDR_WIDTH), + .INSTR_RDATA_WIDTH (ENV_PARAM_INSTR_DATA_WIDTH), + .RAM_ADDR_WIDTH (ENV_PARAM_RAM_ADDR_WIDTH) + ) dut_wrap ( + .clknrst_if (clknrst_if), + .interrupt_if (interrupt_if), + .vp_status_if (vp_status_if), + .core_cntrl_if (core_cntrl_if), + .core_status_if (core_status_if), + .obi_instr_if (obi_instr_if), + .obi_data_if (obi_data_if), + .fencei_if (fencei_if), + .clic_if (clic_if), + .* + ); + + assign debug_if.clk = clknrst_if.clk; + assign debug_if.reset_n = clknrst_if.reset_n; + + // OBI Instruction agent v1.2 signal tie-offs + assign obi_instr_if.we = 'b0; + assign obi_instr_if.be = 'hf; // Always assumes 32-bit full bus reads on instruction OBI + assign obi_instr_if.auser = 'b0; + assign obi_instr_if.wuser = 'b0; + assign obi_instr_if.aid = 'b0; + assign obi_instr_if.wdata = 'b0; + assign obi_instr_if.rready = 1'b1; + assign obi_instr_if.rreadypar = 1'b0; + + // OBI Data agent v1.2 signal tie-offs + assign obi_data_if.auser = 'b0; + assign obi_data_if.wuser = 'b0; + assign obi_data_if.aid = 'b0; + assign obi_data_if.rready = 1'b1; + assign obi_data_if.rreadypar = 1'b0; + + // Connect to uvma_interrupt_if + assign interrupt_if.clk = clknrst_if.clk; + assign interrupt_if.reset_n = clknrst_if.reset_n; + assign interrupt_if.irq_id = $bits(interrupt_if.irq_id)'(dut_wrap.cv32e40s_wrapper_i.core_i.irq_id); // cast to avoid the warning with clic (TODO: tieoff with clic instead?) + assign interrupt_if.irq_ack = dut_wrap.cv32e40s_wrapper_i.core_i.irq_ack; + + assign clic_if.clk = clknrst_if.clk; + assign clic_if.reset_n = clknrst_if.reset_n; + assign clic_if.irq_ack = dut_wrap.cv32e40s_wrapper_i.core_i.irq_ack; + + assign wfe_wu_if.clk = clknrst_if.clk; + assign wfe_wu_if.reset_n = clknrst_if.reset_n; + + // Connect to core_cntrl_if + assign core_cntrl_if.b_ext = uvmt_cv32e40s_base_test_pkg::CORE_PARAM_B_EXT; + `ifndef FORMAL + initial begin + core_cntrl_if.pma_cfg = new[CORE_PARAM_PMA_NUM_REGIONS]; + foreach (core_cntrl_if.pma_cfg[i]) begin + core_cntrl_if.pma_cfg[i].word_addr_low = CORE_PARAM_PMA_CFG[i].word_addr_low; + core_cntrl_if.pma_cfg[i].word_addr_high = CORE_PARAM_PMA_CFG[i].word_addr_high; + core_cntrl_if.pma_cfg[i].main = CORE_PARAM_PMA_CFG[i].main; + core_cntrl_if.pma_cfg[i].bufferable = CORE_PARAM_PMA_CFG[i].bufferable; + core_cntrl_if.pma_cfg[i].cacheable = CORE_PARAM_PMA_CFG[i].cacheable; + core_cntrl_if.pma_cfg[i].integrity = CORE_PARAM_PMA_CFG[i].integrity; + end + end + `endif + + + // "rvfi_instr_if" bind cv32e40s_wrapper - uvma_rvfi_instr_if#(uvme_cv32e40s_pkg::ILEN, - uvme_cv32e40s_pkg::XLEN) rvfi_instr_if_0_i(.clk(clk_i), + uvma_rvfi_instr_if_t#(uvmt_cv32e40s_base_test_pkg::ILEN, + uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_instr_if(.clk(clk_i), .reset_n(rst_ni), .rvfi_valid(rvfi_i.rvfi_valid[0]), .rvfi_order(rvfi_i.rvfi_order[uvma_rvfi_pkg::ORDER_WL*0+:uvma_rvfi_pkg::ORDER_WL]), - .rvfi_insn(rvfi_i.rvfi_insn[uvme_cv32e40s_pkg::ILEN*0+:uvme_cv32e40s_pkg::ILEN]), - .rvfi_trap(rvfi_i.rvfi_trap[11:0]), + .rvfi_insn(rvfi_i.rvfi_insn[uvmt_cv32e40s_base_test_pkg::ILEN*0+:uvmt_cv32e40s_base_test_pkg::ILEN]), + .rvfi_trap(rvfi_i.rvfi_trap), .rvfi_halt(rvfi_i.rvfi_halt[0]), - .rvfi_intr(rvfi_i.rvfi_intr[0]), + .rvfi_intr(rvfi_i.rvfi_intr), .rvfi_dbg(rvfi_i.rvfi_dbg), .rvfi_dbg_mode(rvfi_i.rvfi_dbg_mode), .rvfi_nmip(rvfi_i.rvfi_nmip), .rvfi_mode(rvfi_i.rvfi_mode[uvma_rvfi_pkg::MODE_WL*0+:uvma_rvfi_pkg::MODE_WL]), .rvfi_ixl(rvfi_i.rvfi_ixl[uvma_rvfi_pkg::IXL_WL*0+:uvma_rvfi_pkg::IXL_WL]), - .rvfi_pc_rdata(rvfi_i.rvfi_pc_rdata[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), - .rvfi_pc_wdata(rvfi_i.rvfi_pc_wdata[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), + .rvfi_pc_rdata(rvfi_i.rvfi_pc_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]), + .rvfi_pc_wdata(rvfi_i.rvfi_pc_wdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]), .rvfi_rs1_addr(rvfi_i.rvfi_rs1_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rs1_rdata(rvfi_i.rvfi_rs1_rdata[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), + .rvfi_rs1_rdata(rvfi_i.rvfi_rs1_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]), .rvfi_rs2_addr(rvfi_i.rvfi_rs2_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rs2_rdata(rvfi_i.rvfi_rs2_rdata[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), + .rvfi_rs2_rdata(rvfi_i.rvfi_rs2_rdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]), .rvfi_rs3_addr('0), .rvfi_rs3_rdata('0), .rvfi_rd1_addr(rvfi_i.rvfi_rd_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rd1_wdata(rvfi_i.rvfi_rd_wdata[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), + .rvfi_rd1_wdata(rvfi_i.rvfi_rd_wdata[uvmt_cv32e40s_base_test_pkg::XLEN*0+:uvmt_cv32e40s_base_test_pkg::XLEN]), .rvfi_rd2_addr('0), .rvfi_rd2_wdata('0), - .rvfi_mem_addr(rvfi_i.rvfi_mem_addr[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), - .rvfi_mem_rdata(rvfi_i.rvfi_mem_rdata[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), - .rvfi_mem_rmask(rvfi_i.rvfi_mem_rmask[uvme_cv32e40s_pkg::XLEN/8*0+:uvme_cv32e40s_pkg::XLEN/8]), - .rvfi_mem_wdata(rvfi_i.rvfi_mem_wdata[uvme_cv32e40s_pkg::XLEN*0+:uvme_cv32e40s_pkg::XLEN]), - .rvfi_mem_wmask(rvfi_i.rvfi_mem_wmask[uvme_cv32e40s_pkg::XLEN/8*0+:uvme_cv32e40s_pkg::XLEN/8]) + .rvfi_gpr_rdata(rvfi_i.rvfi_gpr_rdata[32*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40s_base_test_pkg::XLEN]), + .rvfi_gpr_rmask(rvfi_i.rvfi_gpr_rmask[32*0 +:32]), + .rvfi_gpr_wdata(rvfi_i.rvfi_gpr_wdata[32*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:32*uvmt_cv32e40s_base_test_pkg::XLEN]), + .rvfi_gpr_wmask(rvfi_i.rvfi_gpr_wmask[32*0 +:32]), + .rvfi_mem_addr(rvfi_i.rvfi_mem_addr[ uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]), + .rvfi_mem_rdata(rvfi_i.rvfi_mem_rdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]), + .rvfi_mem_rmask(rvfi_i.rvfi_mem_rmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8]), + .rvfi_mem_wdata(rvfi_i.rvfi_mem_wdata[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN]), + .rvfi_mem_wmask(rvfi_i.rvfi_mem_wmask[uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8*0 +:uvma_rvfi_pkg::NMEM*uvmt_cv32e40s_base_test_pkg::XLEN/8]), + .instr_prot(rvfi_i.rvfi_instr_prot), + .mem_prot(rvfi_i.rvfi_mem_prot) ); // RVFI CSR binds + `RVFI_CSR_BIND(cpuctrl) + `RVFI_CSR_BIND(jvt) `RVFI_CSR_BIND(marchid) + `RVFI_CSR_BIND(mcause) + `RVFI_CSR_BIND(mcounteren) `RVFI_CSR_BIND(mcountinhibit) - `RVFI_CSR_BIND(mstatus) - `RVFI_CSR_BIND(mstatush) - `RVFI_CSR_BIND(mvendorid) - `RVFI_CSR_BIND(misa) - `RVFI_CSR_BIND(mtvec) - `RVFI_CSR_BIND(mtval) - `RVFI_CSR_BIND(mscratch) + `RVFI_CSR_BIND(mcycle) + `RVFI_CSR_BIND(mcycleh) + `RVFI_CSR_BIND(menvcfg) + `RVFI_CSR_BIND(menvcfgh) `RVFI_CSR_BIND(mepc) - `RVFI_CSR_BIND(mcause) - `RVFI_CSR_BIND(mip) - `RVFI_CSR_BIND(mie) `RVFI_CSR_BIND(mhartid) - `RVFI_CSR_BIND(mcontext) - `RVFI_CSR_BIND(scontext) + `RVFI_CSR_BIND(mie) `RVFI_CSR_BIND(mimpid) `RVFI_CSR_BIND(minstret) `RVFI_CSR_BIND(minstreth) - `RVFI_CSR_BIND(mcycle) - `RVFI_CSR_BIND(mcycleh) + `RVFI_CSR_BIND(mip) + `RVFI_CSR_BIND(misa) + `RVFI_CSR_BIND(mscratch) + `RVFI_CSR_BIND(mstateen0) + `RVFI_CSR_BIND(mstateen1) + `RVFI_CSR_BIND(mstateen2) + `RVFI_CSR_BIND(mstateen3) + `RVFI_CSR_BIND(mstateen0h) + `RVFI_CSR_BIND(mstateen1h) + `RVFI_CSR_BIND(mstateen2h) + `RVFI_CSR_BIND(mstateen3h) + `RVFI_CSR_BIND(mstatus) + `RVFI_CSR_BIND(mstatush) + `RVFI_CSR_BIND(mtval) + `RVFI_CSR_BIND(mtvec) + `RVFI_CSR_BIND(mvendorid) + `RVFI_CSR_BIND(mseccfg) + `RVFI_CSR_BIND(mseccfgh) `RVFI_CSR_BIND(dcsr) `RVFI_CSR_BIND(dpc) @@ -192,6 +275,88 @@ module uvmt_cv32e40s_tb; `RVFI_CSR_IDX_BIND(mhpmcounter,,30) `RVFI_CSR_IDX_BIND(mhpmcounter,,31) + `RVFI_CSR_IDX_BIND(pmpcfg,,0) + `RVFI_CSR_IDX_BIND(pmpcfg,,1) + `RVFI_CSR_IDX_BIND(pmpcfg,,2) + `RVFI_CSR_IDX_BIND(pmpcfg,,3) + `RVFI_CSR_IDX_BIND(pmpcfg,,4) + `RVFI_CSR_IDX_BIND(pmpcfg,,5) + `RVFI_CSR_IDX_BIND(pmpcfg,,6) + `RVFI_CSR_IDX_BIND(pmpcfg,,7) + `RVFI_CSR_IDX_BIND(pmpcfg,,8) + `RVFI_CSR_IDX_BIND(pmpcfg,,9) + `RVFI_CSR_IDX_BIND(pmpcfg,,10) + `RVFI_CSR_IDX_BIND(pmpcfg,,11) + `RVFI_CSR_IDX_BIND(pmpcfg,,12) + `RVFI_CSR_IDX_BIND(pmpcfg,,13) + `RVFI_CSR_IDX_BIND(pmpcfg,,14) + `RVFI_CSR_IDX_BIND(pmpcfg,,15) + + `RVFI_CSR_IDX_BIND(pmpaddr,,0) + `RVFI_CSR_IDX_BIND(pmpaddr,,1) + `RVFI_CSR_IDX_BIND(pmpaddr,,2) + `RVFI_CSR_IDX_BIND(pmpaddr,,3) + `RVFI_CSR_IDX_BIND(pmpaddr,,4) + `RVFI_CSR_IDX_BIND(pmpaddr,,5) + `RVFI_CSR_IDX_BIND(pmpaddr,,6) + `RVFI_CSR_IDX_BIND(pmpaddr,,7) + `RVFI_CSR_IDX_BIND(pmpaddr,,8) + `RVFI_CSR_IDX_BIND(pmpaddr,,9) + `RVFI_CSR_IDX_BIND(pmpaddr,,10) + `RVFI_CSR_IDX_BIND(pmpaddr,,11) + `RVFI_CSR_IDX_BIND(pmpaddr,,12) + `RVFI_CSR_IDX_BIND(pmpaddr,,13) + `RVFI_CSR_IDX_BIND(pmpaddr,,14) + `RVFI_CSR_IDX_BIND(pmpaddr,,15) + `RVFI_CSR_IDX_BIND(pmpaddr,,16) + `RVFI_CSR_IDX_BIND(pmpaddr,,17) + `RVFI_CSR_IDX_BIND(pmpaddr,,18) + `RVFI_CSR_IDX_BIND(pmpaddr,,19) + `RVFI_CSR_IDX_BIND(pmpaddr,,20) + `RVFI_CSR_IDX_BIND(pmpaddr,,21) + `RVFI_CSR_IDX_BIND(pmpaddr,,22) + `RVFI_CSR_IDX_BIND(pmpaddr,,23) + `RVFI_CSR_IDX_BIND(pmpaddr,,24) + `RVFI_CSR_IDX_BIND(pmpaddr,,25) + `RVFI_CSR_IDX_BIND(pmpaddr,,26) + `RVFI_CSR_IDX_BIND(pmpaddr,,27) + `RVFI_CSR_IDX_BIND(pmpaddr,,28) + `RVFI_CSR_IDX_BIND(pmpaddr,,29) + `RVFI_CSR_IDX_BIND(pmpaddr,,30) + `RVFI_CSR_IDX_BIND(pmpaddr,,31) + `RVFI_CSR_IDX_BIND(pmpaddr,,32) + `RVFI_CSR_IDX_BIND(pmpaddr,,33) + `RVFI_CSR_IDX_BIND(pmpaddr,,34) + `RVFI_CSR_IDX_BIND(pmpaddr,,35) + `RVFI_CSR_IDX_BIND(pmpaddr,,36) + `RVFI_CSR_IDX_BIND(pmpaddr,,37) + `RVFI_CSR_IDX_BIND(pmpaddr,,38) + `RVFI_CSR_IDX_BIND(pmpaddr,,39) + `RVFI_CSR_IDX_BIND(pmpaddr,,40) + `RVFI_CSR_IDX_BIND(pmpaddr,,41) + `RVFI_CSR_IDX_BIND(pmpaddr,,42) + `RVFI_CSR_IDX_BIND(pmpaddr,,43) + `RVFI_CSR_IDX_BIND(pmpaddr,,44) + `RVFI_CSR_IDX_BIND(pmpaddr,,45) + `RVFI_CSR_IDX_BIND(pmpaddr,,46) + `RVFI_CSR_IDX_BIND(pmpaddr,,47) + `RVFI_CSR_IDX_BIND(pmpaddr,,48) + `RVFI_CSR_IDX_BIND(pmpaddr,,49) + `RVFI_CSR_IDX_BIND(pmpaddr,,50) + `RVFI_CSR_IDX_BIND(pmpaddr,,51) + `RVFI_CSR_IDX_BIND(pmpaddr,,52) + `RVFI_CSR_IDX_BIND(pmpaddr,,53) + `RVFI_CSR_IDX_BIND(pmpaddr,,54) + `RVFI_CSR_IDX_BIND(pmpaddr,,55) + `RVFI_CSR_IDX_BIND(pmpaddr,,56) + `RVFI_CSR_IDX_BIND(pmpaddr,,57) + `RVFI_CSR_IDX_BIND(pmpaddr,,58) + `RVFI_CSR_IDX_BIND(pmpaddr,,59) + `RVFI_CSR_IDX_BIND(pmpaddr,,60) + `RVFI_CSR_IDX_BIND(pmpaddr,,61) + `RVFI_CSR_IDX_BIND(pmpaddr,,62) + `RVFI_CSR_IDX_BIND(pmpaddr,,63) + `RVFI_CSR_IDX_BIND(mhpmevent,,3) `RVFI_CSR_IDX_BIND(mhpmevent,,4) `RVFI_CSR_IDX_BIND(mhpmevent,,5) @@ -253,198 +418,965 @@ module uvmt_cv32e40s_tb; `RVFI_CSR_IDX_BIND(mhpmcounter,h,31) `RVFI_CSR_BIND(mconfigptr) - + `RVFI_CSR_BIND(secureseed0) + `RVFI_CSR_BIND(secureseed1) + `RVFI_CSR_BIND(secureseed2) + + if (CORE_PARAM_CLIC == 1) begin: gen_clic_rvfi_bind + `RVFI_CSR_BIND(mintstatus) + `RVFI_CSR_BIND(mintthresh) + `RVFI_CSR_BIND(mnxti) + `RVFI_CSR_BIND(mscratchcsw) + `RVFI_CSR_BIND(mscratchcswl) + `RVFI_CSR_BIND(mtvt) + end : gen_clic_rvfi_bind // dscratch0 bind cv32e40s_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40s_pkg::XLEN) rvfi_csr_dscratch0_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_dscratch_rmask[0]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_dscratch_wmask[0]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_dscratch_rdata[0]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_dscratch_wdata[0]) + uvma_rvfi_csr_if_t#(uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_csr_dscratch0_if(.clk(clk_i), + .reset_n(rst_ni), + .rvfi_csr_rmask(rvfi_i.rvfi_csr_dscratch_rmask[0]), + .rvfi_csr_wmask(rvfi_i.rvfi_csr_dscratch_wmask[0]), + .rvfi_csr_rdata(rvfi_i.rvfi_csr_dscratch_rdata[0]), + .rvfi_csr_wdata(rvfi_i.rvfi_csr_dscratch_wdata[0]) ); + // dscratch1 bind cv32e40s_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40s_pkg::XLEN) rvfi_csr_dscratch1_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_dscratch_rmask[1]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_dscratch_wmask[1]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_dscratch_rdata[1]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_dscratch_wdata[1]) + uvma_rvfi_csr_if_t#(uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_csr_dscratch1_if(.clk(clk_i), + .reset_n(rst_ni), + .rvfi_csr_rmask(rvfi_i.rvfi_csr_dscratch_rmask[1]), + .rvfi_csr_wmask(rvfi_i.rvfi_csr_dscratch_wmask[1]), + .rvfi_csr_rdata(rvfi_i.rvfi_csr_dscratch_rdata[1]), + .rvfi_csr_wdata(rvfi_i.rvfi_csr_dscratch_wdata[1]) ); // tdata1 bind cv32e40s_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40s_pkg::XLEN) rvfi_csr_tdata1_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[1]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[1]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[1]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[1]) + uvma_rvfi_csr_if_t#(uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_csr_tdata1_if(.clk(clk_i), + .reset_n(rst_ni), + .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[1]), + .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[1]), + .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[1]), + .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[1]) ); // tdata2 bind cv32e40s_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40s_pkg::XLEN) rvfi_csr_tdata2_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[2]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[2]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[2]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[2]) + uvma_rvfi_csr_if_t#(uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_csr_tdata2_if(.clk(clk_i), + .reset_n(rst_ni), + .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[2]), + .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[2]), + .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[2]), + .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[2]) ); - // tdata3 - bind cv32e40s_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40s_pkg::XLEN) rvfi_csr_tdata3_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[3]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[3]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[3]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[3]) - ); + + + // Bind in verification modules to the design bind uvmt_cv32e40s_dut_wrap uvma_obi_memory_assert_if_wrp#( - .ADDR_WIDTH(32), - .DATA_WIDTH(32), - .AUSER_WIDTH(0), - .WUSER_WIDTH(0), - .RUSER_WIDTH(0), - .ID_WIDTH(0), - .ACHK_WIDTH(0), - .RCHK_WIDTH(0), + .ADDR_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_DATA_WIDTH), + .AUSER_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_RUSER_WIDTH), + .ID_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_RCHK_WIDTH), .IS_1P2(1) - ) obi_instr_memory_assert_i(.obi(obi_instr_if_i)); + ) obi_instr_memory_assert_i(.obi(obi_instr_if)); bind uvmt_cv32e40s_dut_wrap uvma_obi_memory_assert_if_wrp#( - .ADDR_WIDTH(32), - .DATA_WIDTH(32), - .AUSER_WIDTH(0), - .WUSER_WIDTH(0), - .RUSER_WIDTH(0), - .ID_WIDTH(0), - .ACHK_WIDTH(0), - .RCHK_WIDTH(0), + .ADDR_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_DATA_WIDTH), + .AUSER_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_RUSER_WIDTH), + .ID_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_DATA_RCHK_WIDTH), .IS_1P2(1) - ) obi_data_memory_assert_i(.obi(obi_data_if_i)); - - // Bind in verification modules to the design - bind cv32e40s_core - uvmt_cv32e40s_interrupt_assert interrupt_assert_i( - .mcause_n ({cs_registers_i.mcause_n.irq, cs_registers_i.mcause_n.exception_code[4:0]}), - .mip (cs_registers_i.mip), - .mie_q (cs_registers_i.mie_q), - .mstatus_mie (cs_registers_i.mstatus_q.mie), - .mtvec_mode_q (cs_registers_i.mtvec_q.mode), - - .if_stage_instr_req_o (if_stage_i.m_c_obi_instr_if.s_req.req), - .if_stage_instr_rvalid_i (if_stage_i.m_c_obi_instr_if.s_rvalid.rvalid), - .if_stage_instr_rdata_i (if_stage_i.m_c_obi_instr_if.resp_payload.rdata), - .alignbuf_outstanding (if_stage_i.prefetch_unit_i.alignment_buffer_i.outstanding_cnt_q), + ) obi_data_memory_assert_i(.obi(obi_data_if)); + + + if (CORE_PARAM_CLIC == 0) begin: gen_interrupt_assert + `ifndef COREV_ASSERT_OFF + bind cv32e40s_core + uvmt_cv32e40s_interrupt_assert interrupt_assert_i ( + .dcsr_step (cs_registers_i.dcsr_q.step), + .mcause_n ({cs_registers_i.mcause_n.irq, cs_registers_i.mcause_n.exception_code[4:0]}), + .mie_q (cs_registers_i.mie_q), + .mip (cs_registers_i.mip_rdata), + .mstatus_mie (cs_registers_i.mstatus_q.mie), + .mstatus_tw (cs_registers_i.mstatus_q.tw), + .mtvec_mode_q (cs_registers_i.mtvec_q.mode), + + .if_stage_instr_rdata_i (if_stage_i.m_c_obi_instr_if.resp_payload.rdata), + .if_stage_instr_req_o (if_stage_i.m_c_obi_instr_if.s_req.req), + .if_stage_instr_rvalid_i (if_stage_i.m_c_obi_instr_if.s_rvalid.rvalid), + .alignbuf_outstanding (if_stage_i.prefetch_unit_i.alignment_buffer_i.outstanding_cnt_q), + + .ex_stage_instr_valid (ex_stage_i.id_ex_pipe_i.instr_valid), + + .wb_kill (ctrl_fsm.kill_wb), + .wb_stage_instr_err_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.err), + .wb_stage_instr_mpu_status (wb_stage_i.ex_wb_pipe_i.instr.mpu_status), + .wb_stage_instr_rdata_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.rdata), + .wb_stage_instr_valid_i (wb_stage_i.ex_wb_pipe_i.instr_valid), + .wb_trigger (controller_i.controller_fsm_i.trigger_match_in_wb), + .wb_valid (wb_stage_i.wb_valid), + + .branch_taken_ex (controller_i.controller_fsm_i.branch_taken_ex), + .debug_mode_q (controller_i.controller_fsm_i.debug_mode_q), + .pending_nmi (controller_i.controller_fsm_i.pending_nmi), + + .irq_ack_o (core_i.irq_ack), + .irq_id_o (core_i.irq_id), + + .mpu_instr_rvalid (if_stage_i.mpu_i.core_resp_valid_o), + .obi_instr_if (dut_wrap.obi_instr_if), + .obi_data_if (dut_wrap.obi_data_if), + + .writebufstate (load_store_unit_i.write_buffer_i.state), + .rvfi (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .support_if (cv32e40s_wrapper.support_logic_module_o_if.slave_mp), + + .* + ); + `endif + end : gen_interrupt_assert + + if (CORE_PARAM_CLIC == 1) begin: gen_clic_assert + // CLIC assertions + `ifndef COREV_ASSERT_OFF + bind cv32e40s_core + uvmt_cv32e40s_clic_interrupt_assert#( + .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC), + .CLIC_ID_WIDTH (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) + ) clic_assert_i( + .support_if (cv32e40s_wrapper.support_logic_module_o_if.slave_mp), + .rvfi_if(cv32e40s_wrapper.rvfi_instr_if), + .csr_mepc_if(cv32e40s_wrapper.rvfi_csr_mepc_if), + .csr_mstatus_if(cv32e40s_wrapper.rvfi_csr_mstatus_if), + .csr_mcause_if(cv32e40s_wrapper.rvfi_csr_mcause_if), + .csr_mintthresh_if(cv32e40s_wrapper.rvfi_csr_mintthresh_if), + .csr_mintstatus_if(cv32e40s_wrapper.rvfi_csr_mintstatus_if), + .csr_dcsr_if(cv32e40s_wrapper.rvfi_csr_dcsr_if), + + .dpc (cs_registers_i.dpc_rdata), + .mintstatus (cs_registers_i.mintstatus_rdata), + .mintthresh (cs_registers_i.mintthresh_rdata), + .mcause (cs_registers_i.mcause_rdata), + .mtvec (cs_registers_i.mtvec_rdata), + .mtvt (cs_registers_i.mtvt_rdata), + .mepc (cs_registers_i.mepc_rdata), + .mip (cs_registers_i.mip_rdata), + .mie (cs_registers_i.mie_rdata), + .mnxti (cs_registers_i.mnxti_rdata), + .mscratch (cs_registers_i.mscratch_rdata), + .mscratchcsw (cs_registers_i.mscratchcsw_rdata), + .mscratchcswl (cs_registers_i.mscratchcswl_rdata), + .dcsr (cs_registers_i.dcsr_rdata), + + //Control signals: + .pc_set (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_set), + .pc_mux (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_mux), + + .rvfi_mepc_wdata (rvfi_i.rvfi_csr_mepc_wdata), + .rvfi_mepc_wmask (rvfi_i.rvfi_csr_mepc_wmask), + .rvfi_mepc_rdata (rvfi_i.rvfi_csr_mepc_rdata), + .rvfi_mepc_rmask (rvfi_i.rvfi_csr_mepc_rmask), + .rvfi_dpc_rdata (rvfi_i.rvfi_csr_dpc_rdata), + .rvfi_dpc_rmask (rvfi_i.rvfi_csr_dpc_rmask), + .rvfi_mscratch_rdata (rvfi_i.rvfi_csr_mscratch_rdata), + .rvfi_mscratch_rmask (rvfi_i.rvfi_csr_mscratch_rmask), + .rvfi_mscratch_wdata (rvfi_i.rvfi_csr_mscratch_wdata), + .rvfi_mscratch_wmask (rvfi_i.rvfi_csr_mscratch_wmask), + .rvfi_mcause_wdata (rvfi_i.rvfi_csr_mcause_wdata), + .rvfi_mcause_wmask (rvfi_i.rvfi_csr_mcause_wmask), + + .irq_i (core_i.irq_i), + .irq_ack (core_i.irq_ack), + .fetch_enable (core_i.fetch_enable), + .current_priv_mode (core_i.priv_lvl), + .mtvec_addr_i (core_i.mtvec_addr_i), + // External inputs + .clic_if (dut_wrap.clic_if), + // Internal sampled variants + .irq_id (core_i.irq_id[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH-1:0]), + .irq_level (core_i.irq_level), + .irq_priv (core_i.irq_priv), + .irq_shv (core_i.irq_shv), + + .obi_instr_req (core_i.instr_req_o), + .obi_instr_gnt (core_i.instr_gnt_i), + .obi_instr_rvalid (core_i.instr_rvalid_i), + .obi_instr_addr (core_i.instr_addr_o), + .obi_instr_rdata (core_i.instr_rdata_i), + .obi_instr_rready (1'b1), + .obi_instr_err (core_i.instr_err_i), + + .obi_data_addr (core_i.data_addr_o), + .obi_data_wdata (core_i.data_wdata_o), + .obi_data_we (core_i.data_we_o), + .obi_data_be (core_i.data_be_o), + .obi_data_req (core_i.data_req_o), + .obi_data_gnt (core_i.data_gnt_i), + .obi_data_rvalid (core_i.data_rvalid_i), + .obi_data_rready (1'b1), + .obi_data_err (core_i.data_err_i), + + .debug_mode (controller_i.controller_fsm_i.debug_mode_q), + .debug_req (core_i.debug_req_i), + .debug_havereset (core_i.debug_havereset_o), + .debug_running (core_i.debug_running_o), + .debug_halt_addr (dut_wrap.cv32e40s_wrapper_i.dm_halt_addr_i), + .debug_exc_addr (dut_wrap.cv32e40s_wrapper_i.dm_exception_addr_i), + + .rvfi_mode (rvfi_i.rvfi_mode), + .rvfi_insn (rvfi_i.rvfi_insn), + .rvfi_intr (rvfi_i.rvfi_intr), + .rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata), + .rvfi_rs2_rdata (rvfi_i.rvfi_rs2_rdata), + .rvfi_rd_wdata (rvfi_i.rvfi_rd_wdata), + .rvfi_valid (rvfi_i.rvfi_valid), + .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), + .rvfi_pc_wdata (rvfi_i.rvfi_pc_wdata), + .rvfi_trap (rvfi_i.rvfi_trap), + .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), + .rvfi_dbg (rvfi_i.rvfi_dbg), + + .wu_wfe (dut_wrap.cv32e40s_wrapper_i.wu_wfe_i), + .core_sleep_o (core_i.core_sleep_o), + .* + ); + `endif + end : gen_clic_assert + + + // User-Mode Assertions + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_umode_assert #( + .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC) + ) umode_assert_i ( + .rvfi_valid (rvfi_i.rvfi_valid), + .rvfi_mode (rvfi_i.rvfi_mode), + .rvfi_order (rvfi_i.rvfi_order), + .rvfi_trap (rvfi_i.rvfi_trap), + .rvfi_intr (rvfi_i.rvfi_intr), + .rvfi_insn (rvfi_i.rvfi_insn), + .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), + .rvfi_dbg (rvfi_i.rvfi_dbg), + .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), + .rvfi_if (rvfi_instr_if), + + .rvfi_csr_dcsr_rdata (rvfi_i.rvfi_csr_dcsr_rdata), + .rvfi_csr_mcause_rdata (rvfi_i.rvfi_csr_mcause_rdata), + .rvfi_csr_mcause_wdata (rvfi_i.rvfi_csr_mcause_wdata), + .rvfi_csr_mcause_wmask (rvfi_i.rvfi_csr_mcause_wmask), + .rvfi_csr_mcounteren_rdata (rvfi_i.rvfi_csr_mcounteren_rdata), + .rvfi_csr_mie_rdata (rvfi_i.rvfi_csr_mie_rdata), + .rvfi_csr_mip_rdata (rvfi_i.rvfi_csr_mip_rdata), + .rvfi_csr_misa_rdata (rvfi_i.rvfi_csr_misa_rdata), + .rvfi_csr_mscratch_rdata (rvfi_i.rvfi_csr_mscratch_rdata), + .rvfi_csr_mscratch_rmask (rvfi_i.rvfi_csr_mscratch_rmask), + .rvfi_csr_mscratch_wdata (rvfi_i.rvfi_csr_mscratch_wdata), + .rvfi_csr_mscratch_wmask (rvfi_i.rvfi_csr_mscratch_wmask), + .rvfi_csr_mstateen0_rdata (rvfi_i.rvfi_csr_mstateen0_rdata), + .rvfi_csr_mstatus_rdata (rvfi_i.rvfi_csr_mstatus_rdata), + .rvfi_csr_mstatus_wdata (rvfi_i.rvfi_csr_mstatus_wdata), + .rvfi_csr_mstatus_wmask (rvfi_i.rvfi_csr_mstatus_wmask), + + .mpu_iside_valid (core_i.if_stage_i.mpu_i.core_trans_valid_i), + .mpu_iside_addr (core_i.if_stage_i.mpu_i.core_trans_i.addr), + + .obi_iside_prot (core_i.instr_prot_o), + .obi_dside_prot (core_i.data_prot_o), + + .* + ); + `endif + + + // User-mode Coverage + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_umode_cov umode_cov_i ( + .rvfi_valid (rvfi_i.rvfi_valid), + .rvfi_trap (rvfi_i.rvfi_trap), + .rvfi_intr (rvfi_i.rvfi_intr), + .rvfi_insn (rvfi_i.rvfi_insn), + .rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata), + .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), + .rvfi_mode (rvfi_i.rvfi_mode), + .rvfi_rd_addr (rvfi_i.rvfi_rd_addr), + .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), + .rvfi_order (rvfi_i.rvfi_order), + .rvfi_mem_rmask (rvfi_i.rvfi_mem_rmask), + .rvfi_mem_wmask (rvfi_i.rvfi_mem_wmask), + + .rvfi_csr_mstatus_rdata (rvfi_i.rvfi_csr_mstatus_rdata), + .rvfi_csr_mstatus_rmask (rvfi_i.rvfi_csr_mstatus_rmask), + .rvfi_csr_dcsr_rdata (rvfi_i.rvfi_csr_dcsr_rdata), + .rvfi_csr_dcsr_rmask (rvfi_i.rvfi_csr_dcsr_rmask), + + .obi_iside_req (core_i.instr_req_o), + .obi_iside_gnt (core_i.instr_gnt_i), + .obi_iside_addr (core_i.instr_addr_o), + .obi_iside_prot (core_i.instr_prot_o), + + .* + ); + `endif - .ex_stage_instr_valid (ex_stage_i.id_ex_pipe_i.instr_valid), - .wb_stage_instr_valid_i (wb_stage_i.instr_valid), - .wb_stage_instr_rdata_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.rdata), - .wb_stage_instr_err_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.err), - .wb_stage_instr_mpu_status (wb_stage_i.ex_wb_pipe_i.instr.mpu_status), - - .branch_taken_ex (controller_i.controller_fsm_i.branch_taken_ex), - .debug_mode_q (controller_i.controller_fsm_i.debug_mode_q), + // Fence.i assertions - .irq_ack_o (core_i.irq_ack), - .irq_id_o (core_i.irq_id), + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_fencei_assert #( + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) fencei_assert_i ( + .wb_valid (core_i.wb_stage_i.wb_valid), + .wb_instr_valid (core_i.ex_wb_pipe.instr_valid), + .wb_sys_en (core_i.ex_wb_pipe.sys_en), + .wb_sys_fencei_insn (core_i.ex_wb_pipe.sys_fencei_insn), + .wb_pc (core_i.ex_wb_pipe.pc), + .wb_rdata (core_i.ex_wb_pipe.instr.bus_resp.rdata), + .wb_buffer_state (core_i.load_store_unit_i.write_buffer_i.state), + + .rvfi_if (rvfi_instr_if), + + .* + ); + `endif + + + // RVFI Asserts & Covers + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.rvfi_i + uvmt_cv32e40s_rvfi_assert #( + .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC), + .CLIC_ID_WIDTH (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) + ) rvfi_assert_i ( + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .support_if (dut_wrap.cv32e40s_wrapper_i.support_logic_module_o_if.slave_mp), + .writebuf_ready_o (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.ready_o), + .writebuf_valid_i (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.valid_i), + .* + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.rvfi_i + uvmt_cv32e40s_rvfi_cov rvfi_cov_i ( + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .* + ); + `endif - .* - ); - // Fence.i assertions + // Core integration assertions bind cv32e40s_wrapper - uvmt_cv32e40s_fencei_assert #( - .PMA_NUM_REGIONS (uvmt_cv32e40s_pkg::CORE_PARAM_PMA_NUM_REGIONS), - .PMA_CFG (uvmt_cv32e40s_pkg::CORE_PARAM_PMA_CFG) - ) fencei_assert_i ( - .wb_valid (core_i.wb_stage_i.wb_valid), - .wb_instr_valid (core_i.ex_wb_pipe.instr_valid), - .wb_sys_en (core_i.ex_wb_pipe.sys_en), - .wb_sys_fencei_insn (core_i.ex_wb_pipe.sys_fencei_insn), - .wb_pc (core_i.ex_wb_pipe.pc), - .wb_rdata (core_i.ex_wb_pipe.instr.bus_resp.rdata), - .wb_buffer_state (core_i.load_store_unit_i.write_buffer_i.state), - - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_intr (rvfi_i.rvfi_intr), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - + uvmt_cv32e40s_integration_assert integration_assert_i ( + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .support_if (support_logic_module_o_if.slave_mp), .* ); - // Core integration assertions + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_data_independent_timing_assert #( + .SECURE (SECURE) + ) xsecure_data_independent_timing_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Interfaces: + .rvfi_if (rvfi_instr_if), + .rvfi_cpuctrl (rvfi_csr_cpuctrl_if), + + //CSRs: + .dataindtiming_enabled (core_i.xsecure_ctrl.cpuctrl.dataindtiming) + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_pc_assert #( + .SECURE (SECURE) + ) xsecure_hardened_pc_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //CSRs: + .pc_hardening_enabled (core_i.xsecure_ctrl.cpuctrl.pc_hardening), + .dataindtiming_enabled (core_i.xsecure_ctrl.cpuctrl.dataindtiming), + + //Alert: + .alert_major_due_to_pc_err (core_i.alert_i.pc_err_i), + + //IF: + .if_valid (core_i.if_valid), + .ptr_in_if (core_i.if_stage_i.ptr_in_if_o), + .if_instr_cmpr (core_i.if_stage_i.compressed_decoder_i.is_compressed_o), + .if_pc (core_i.pc_if), + .dummy_insert (dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.dummy_insert), + + //ID: + .id_ready (core_i.id_ready), + .id_pc (core_i.id_stage_i.if_id_pipe_i.pc), + .id_last_op (core_i.if_id_pipe.last_op), + .id_first_op (core_i.if_id_pipe.first_op), + .jump_in_id (core_i.controller_i.controller_fsm_i.jump_in_id), + .kill_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_id), + .halt_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_id), + + //EX: + .ex_first_op (core_i.id_ex_pipe.first_op), + .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), + .kill_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_ex), + .halt_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_ex), + + //Controll signals: + .pc_set (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_set), + .pc_mux (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_mux), + + //Signals to glitch check: + .branch_target (core_i.ex_stage_i.branch_target_o), + .branch_decision (core_i.ex_stage_i.alu_i.cmp_result_o), + .jump_target (core_i.jump_target_id), + .mepc (core_i.cs_registers_i.mepc_rdata) + + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert #( + .SECURE (SECURE) + ) xsecure_reduced_profiling_infrastructure_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + .mhpmevent (core_i.cs_registers_i.mhpmevent_rdata), + .mhpmcounter (core_i.cs_registers_i.mhpmcounter_rdata), + .mcountinhibit (core_i.cs_registers_i.mcountinhibit_rdata) + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_csrs_assert #( + .SECURE (SECURE) + ) xsecure_hardened_csrs_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //CSRs: + .mstateen0 (core_i.cs_registers_i.mstateen0_csr_i.rdata_q), + .priv_lvl (core_i.cs_registers_i.privlvl_user.priv_lvl_i.rdata_q), + .jvt (core_i.cs_registers_i.jvt_csr_i.rdata_q), + .mstatus (core_i.cs_registers_i.mstatus_csr_i.rdata_q), + .cpuctrl (core_i.cs_registers_i.xsecure.cpuctrl_csr_i.rdata_q), + .dcsr (core_i.cs_registers_i.gen_debug_csr.dcsr_csr_i.rdata_q), + .mepc (core_i.cs_registers_i.mepc_csr_i.rdata_q), + .mscratch (core_i.cs_registers_i.mscratch_csr_i.rdata_q), + + //Shadows: + .mstateen0_shadow (core_i.cs_registers_i.mstateen0_csr_i.gen_hardened.shadow_q), + .priv_lvl_shadow (core_i.cs_registers_i.privlvl_user.priv_lvl_i.gen_hardened.shadow_q), + .jvt_shadow (core_i.cs_registers_i.jvt_csr_i.gen_hardened.shadow_q), + .mstatus_shadow (core_i.cs_registers_i.mstatus_csr_i.gen_hardened.shadow_q), + .cpuctrl_shadow (core_i.cs_registers_i.xsecure.cpuctrl_csr_i.gen_hardened.shadow_q), + .dcsr_shadow (core_i.cs_registers_i.gen_debug_csr.dcsr_csr_i.gen_hardened.shadow_q), + .mepc_shadow (core_i.cs_registers_i.mepc_csr_i.gen_hardened.shadow_q), + .mscratch_shadow (core_i.cs_registers_i.mscratch_csr_i.gen_hardened.shadow_q) + + ); + `endif + + if (CORE_PARAM_CLIC == 1) begin: gen_hardened_csrs_clic_assert + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert #( + .SECURE (SECURE) + ) xsecure_hardened_csrs_clic_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //CSRs: + .mcause (core_i.cs_registers_i.clic_csrs.mcause_csr_i.rdata_q), + .mtvt (core_i.cs_registers_i.clic_csrs.mtvt_csr_i.rdata_q), + .mtvec (core_i.cs_registers_i.clic_csrs.mtvec_csr_i.rdata_q), + .mintstatus (core_i.cs_registers_i.clic_csrs.mintstatus_csr_i.rdata_q), + .mintthresh (core_i.cs_registers_i.clic_csrs.mintthresh_csr_i.rdata_q), + + //Shadows: + .mcause_shadow (core_i.cs_registers_i.clic_csrs.mcause_csr_i.gen_hardened.shadow_q), + .mtvt_shadow (core_i.cs_registers_i.clic_csrs.mtvt_csr_i.gen_hardened.shadow_q), + .mtvec_shadow (core_i.cs_registers_i.clic_csrs.mtvec_csr_i.gen_hardened.shadow_q), + .mintstatus_shadow (core_i.cs_registers_i.clic_csrs.mintstatus_csr_i.gen_hardened.shadow_q), + .mintthresh_shadow (core_i.cs_registers_i.clic_csrs.mintthresh_csr_i.gen_hardened.shadow_q) + + ); + `endif + end : gen_hardened_csrs_clic_assert + + if (CORE_PARAM_CLIC == 0) begin: gen_hardened_csrs_interrupt_assert + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert #( + .SECURE (SECURE) + ) xsecure_hardened_csrs_interrupt_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //CSRs: + .mcause (core_i.cs_registers_i.basic_mode_csrs.mcause_csr_i.rdata_q), + .mtvec (core_i.cs_registers_i.basic_mode_csrs.mtvec_csr_i.rdata_q), + .mie (core_i.cs_registers_i.basic_mode_csrs.mie_csr_i.rdata_q), + + //Shadows: + .mcause_shadow (core_i.cs_registers_i.basic_mode_csrs.mcause_csr_i.gen_hardened.shadow_q), + .mtvec_shadow (core_i.cs_registers_i.basic_mode_csrs.mtvec_csr_i.gen_hardened.shadow_q), + .mie_shadow (core_i.cs_registers_i.basic_mode_csrs.mie_csr_i.gen_hardened.shadow_q) + ); + `endif + end : gen_hardened_csrs_interrupt_assert + + + + if (CORE_PARAM_PMP_NUM_REGIONS > 0) begin: gen_hardened_csrs_pmp_assert + localparam PMP_ADDR_WIDTH = (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_GRANULARITY > 0) ? 33 - uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_GRANULARITY : 32; + + pmpncfg_t pmpncfg[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_NUM_REGIONS]; + logic [PMP_ADDR_WIDTH-1:0] pmp_addr[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_NUM_REGIONS]; + + logic [$bits(pmpncfg_t)-1:0] pmpncfg_shadow[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_NUM_REGIONS]; + logic [PMP_ADDR_WIDTH-1:0] pmp_addr_shadow[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_NUM_REGIONS]; + + for (genvar n = 0; n < uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_NUM_REGIONS; n++) begin + assign pmpncfg[n] = dut_wrap.cv32e40s_wrapper_i.core_i.cs_registers_i.csr_pmp.gen_pmp_csr[n].pmp_region.pmpncfg_csr_i.rdata_q; + assign pmp_addr[n] = dut_wrap.cv32e40s_wrapper_i.core_i.cs_registers_i.csr_pmp.gen_pmp_csr[n].pmp_region.pmp_addr_csr_i.rdata_q; + + assign pmpncfg_shadow[n] = dut_wrap.cv32e40s_wrapper_i.core_i.cs_registers_i.csr_pmp.gen_pmp_csr[n].pmp_region.pmpncfg_csr_i.gen_hardened.shadow_q; + assign pmp_addr_shadow[n] = dut_wrap.cv32e40s_wrapper_i.core_i.cs_registers_i.csr_pmp.gen_pmp_csr[n].pmp_region.pmp_addr_csr_i.gen_hardened.shadow_q; + end - bind cv32e40s_wrapper - uvmt_cv32e40s_integration_assert integration_assert_i (.*); + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert #( + .SECURE (SECURE), + .PMP_ADDR_WIDTH (core_i.cs_registers_i.PMP_ADDR_WIDTH), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS) + ) xsecure_hardened_csrs_pmp_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //CSRs: + .pmp_mseccfg (core_i.cs_registers_i.csr_pmp.pmp_mseccfg_csr_i.rdata_q), + .pmpncfg (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmpncfg), + .pmp_addr (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmp_addr), + + //Shadows: + .pmp_mseccfg_shadow (core_i.cs_registers_i.csr_pmp.pmp_mseccfg_csr_i.gen_hardened.shadow_q), + .pmpncfg_shadow (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmpncfg_shadow), + .pmp_addr_shadow (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmp_addr_shadow) + ); + `endif + + end : gen_hardened_csrs_pmp_assert + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_register_file_ecc_assert #( + .SECURE (SECURE) + ) xsecure_register_file_ecc_assert_i ( + + //Interfaces: + .rvfi_if (rvfi_instr_if), + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //Register file memory: + .gpr_mem (core_i.register_file_wrapper_i.register_file_i.mem_gated), + + //Soruce registers: + .rs1 (core_i.if_id_pipe.instr.bus_resp.rdata[19:15]), + .rs2 (core_i.if_id_pipe.instr.bus_resp.rdata[24:20]), + + //Writing of GPRs: + .gpr_we (core_i.rf_we_wb), + .gpr_waddr (core_i.rf_waddr_wb), + .gpr_wdata (core_i.rf_wdata_wb) + + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_security_alerts_assert #( + .SECURE (SECURE) + ) xsecure_security_alerts_assert_i ( + + //Interfaces: + .rvfi_if (rvfi_instr_if), + .support_if (support_logic_module_o_if.slave_mp), + + //Signals: + .rst_ni (clknrst_if.reset_n), + .clk_i (clknrst_if.clk), + + //alerts: + .alert_minor (core_i.alert_minor_o), + .alert_major (core_i.alert_major_o), + + //wb: + .wb_valid (core_i.wb_valid), + .exception_in_wb (core_i.controller_i.controller_fsm_i.exception_in_wb), + .exception_cause_wb (core_i.controller_i.controller_fsm_i.exception_cause_wb), + + //dummy and hint: + .dummy_en (core_i.xsecure_ctrl.cpuctrl.rnddummy), + .hint_en (core_i.xsecure_ctrl.cpuctrl.rndhint), + .lfsr0_clock_en (core_i.cs_registers_i.xsecure.lfsr0_i.clock_en), + .lfsr1_clock_en (core_i.cs_registers_i.xsecure.lfsr1_i.clock_en), + .lfsr2_clock_en (core_i.cs_registers_i.xsecure.lfsr2_i.clock_en), + .seed0_we (core_i.cs_registers_i.xsecure.lfsr0_i.seed_we_i), + .seed1_we (core_i.cs_registers_i.xsecure.lfsr1_i.seed_we_i), + .seed2_we (core_i.cs_registers_i.xsecure.lfsr2_i.seed_we_i), + .seed0_i (core_i.cs_registers_i.xsecure.lfsr0_i.seed_i), + .seed1_i (core_i.cs_registers_i.xsecure.lfsr1_i.seed_i), + .seed2_i (core_i.cs_registers_i.xsecure.lfsr2_i.seed_i), + .lfsr0_n (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_n), + .lfsr1_n (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_n), + .lfsr2_n (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_n), + + //OBI: + .obi_data_rvalid (core_i.data_rvalid_i), + .obi_data_err (core_i.data_err_i), + + //NMI: + .nmip (core_i.dcsr.nmip), + + //debug: + .debug_mode (core_i.controller_i.controller_fsm_i.debug_mode_q) + + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert #( + .SECURE (SECURE) + ) xsecure_bus_protocol_hardening_assert_i ( + + //Interfaces: + .support_if (support_logic_module_o_if.slave_mp), + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alerts: + .alert_major (core_i.alert_major_o), + .bus_protocol_hardening_glitch (core_i.alert_i.itf_prot_err_i), + + //OBI: + .obi_data_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), + .obi_instr_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), + + //Resp valids: + .instr_if_mpu_resp (core_i.if_stage_i.prefetch_resp_valid), + .lsu_mpu_resp (core_i.load_store_unit_i.resp_valid), + + //Counters: + .lsu_rf_core_side_cnt (core_i.load_store_unit_i.response_filter_i.core_cnt_q), + .lsu_rf_bus_side_cnt (core_i.load_store_unit_i.response_filter_i.bus_cnt_q) + + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_interface_integrity_assert #( + .SECURE (SECURE), + .ALBUF_DEPTH (core_i.if_stage_i.ALBUF_DEPTH), + .ALBUF_CNT_WIDTH (core_i.if_stage_i.ALBUF_CNT_WIDTH) + ) xsecure_interface_integrity_assert_i ( + + //Interfaces: + .support_if (support_logic_module_o_if.slave_mp), + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + .alert_major_due_to_integrity_err (core_i.alert_i.itf_int_err_i), + + //CSRs: + .integrity_enabled (core_i.xsecure_ctrl.cpuctrl.integrity), + .nmip (core_i.cs_registers_i.dcsr_rdata.nmip), + .mcause_exception_code (core_i.cs_registers_i.mcause_rdata.exception_code), + + //OBI data: + .obi_data_req_packet (core_i.m_c_obi_data_if.req_payload), + .obi_data_resp_packet (core_i.m_c_obi_data_if.resp_payload), + .obi_data_addr (core_i.data_addr_o), + .obi_data_req (core_i.m_c_obi_data_if.s_req.req), + .obi_data_reqpar (core_i.m_c_obi_data_if.s_req.reqpar), + .obi_data_gnt (core_i.m_c_obi_data_if.s_gnt.gnt), + .obi_data_gntpar (core_i.m_c_obi_data_if.s_gnt.gntpar), + .obi_data_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), + .obi_data_rvalidpar (core_i.m_c_obi_data_if.s_rvalid.rvalidpar), + + //OBI instr: + .obi_instr_req_packet (core_i.m_c_obi_instr_if.req_payload), + .obi_instr_resp_packet (core_i.m_c_obi_instr_if.resp_payload), + .obi_instr_addr (core_i.instr_addr_o), + .obi_instr_req (core_i.m_c_obi_instr_if.s_req.req), + .obi_instr_reqpar (core_i.m_c_obi_instr_if.s_req.reqpar), + .obi_instr_gnt (core_i.m_c_obi_instr_if.s_gnt.gnt), + .obi_instr_gntpar (core_i.m_c_obi_instr_if.s_gnt.gntpar), + .obi_instr_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), + .obi_instr_rvalidpar (core_i.m_c_obi_instr_if.s_rvalid.rvalidpar), + + //Register file memory: + .gpr_mem (core_i.register_file_wrapper_i.register_file_i.mem_gated), + .rf_we (core_i.rf_we_wb), + .rf_waddr (core_i.rf_waddr_wb), + .rf_wdata (core_i.rf_wdata_wb), + + //Alignment buffer: + .alb_resp_i (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.resp_i), + .alb_resp_q (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.resp_q), + .alb_valid (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.valid_q), + .alb_wptr (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.wptr), + .alb_rptr1 (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.rptr), + .alb_rptr2 (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.rptr2), + + //If: + .if_valid (core_i.if_valid), + .if_instr_integrity_err (core_i.if_stage_i.bus_resp.integrity_err), + .if_instr_cmpr (core_i.if_stage_i.compressed_decoder_i.is_compressed_o), + .if_instr_pc (core_i.if_stage_i.pc_if_o), + .dummy_insert (dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.dummy_insert), + + //Id: + .id_ready (core_i.id_ready), + .id_instr_integrity_err (core_i.if_id_pipe.instr.bus_resp.integrity_err), + .id_abort_op (dut_wrap.cv32e40s_wrapper_i.core_i.if_id_pipe.abort_op), + .id_illegal_insn (dut_wrap.cv32e40s_wrapper_i.core_i.if_id_pipe.illegal_c_insn), + + //Wb: + .wb_valid (core_i.wb_valid), + .wb_integrity_err (core_i.ex_wb_pipe.instr.bus_resp.integrity_err), + .wb_instr_opcode (core_i.ex_wb_pipe.instr.bus_resp.rdata[6:0]), + .wb_exception (core_i.controller_i.controller_fsm_i.exception_in_wb), + .wb_exception_code (core_i.controller_i.controller_fsm_i.exception_cause_wb), + .data_integrity_err (core_i.load_store_unit_i.bus_resp.integrity_err), + + //MISC: + .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), + .pc_mux (dut_wrap.cv32e40s_wrapper_i.core_i.ctrl_fsm.pc_mux), + .pc_set (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.ctrl_fsm_i.pc_set), + .seq_valid (core_i.if_stage_i.seq_valid), + .kill_if (core_i.ctrl_fsm.kill_if), + .n_flush_q (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.n_flush_q), + .rchk_err_instr (core_i.if_stage_i.instruction_obi_i.rchk_err_resp), + .rchk_err_data (core_i.load_store_unit_i.data_obi_i.rchk_err_resp) + + ); + `endif + + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_dummy_and_hint_assert #( + .SECURE (SECURE) + ) xsecure_dummy_and_hint_assert_i ( + + //Interfaces: + .rvfi_if (rvfi_instr_if), + .rvfi_mcountinhibit_if (rvfi_csr_mcountinhibit_if), + .rvfi_dcsr_if (rvfi_csr_dcsr_if), + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + .gated_clk_enabled (core_i.sleep_unit_i.clock_en), + + //CSRs: + .rnddummy_enabled (core_i.xsecure_ctrl.cpuctrl.rnddummy), + .rndhint_enabled (core_i.xsecure_ctrl.cpuctrl.rndhint), + .dummy_freq (core_i.xsecure_ctrl.cpuctrl.rnddummyfreq), + .mhpmcounter (core_i.cs_registers_i.mhpmcounter_rdata), + .mcountinhibit (core_i.cs_registers_i.mcountinhibit_rdata), + .csr_waddr(core_i.cs_registers_i.csr_waddr), + + //LFSR: + .lfsr0_seed_we (core_i.cs_registers_i.xsecure.lfsr0_i.seed_we_i), + .lfsr1_seed_we (core_i.cs_registers_i.xsecure.lfsr1_i.seed_we_i), + .lfsr2_seed_we (core_i.cs_registers_i.xsecure.lfsr2_i.seed_we_i), + .lfsr0_seed (core_i.cs_registers_i.xsecure.lfsr0_i.seed_i), + .lfsr1_seed (core_i.cs_registers_i.xsecure.lfsr1_i.seed_i), + .lfsr2_seed (core_i.cs_registers_i.xsecure.lfsr2_i.seed_i), + .lfsr0 (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_q), + .lfsr1 (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_q), + .lfsr2 (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_q), + .lfsr0_n (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_n), + .lfsr1_n (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_n), + .lfsr2_n (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_n), + .lfsr0_clk_en (core_i.cs_registers_i.xsecure.lfsr0_i.clock_en), + .lfsr1_clk_en (core_i.cs_registers_i.xsecure.lfsr1_i.clock_en), + .lfsr2_clk_en (core_i.cs_registers_i.xsecure.lfsr2_i.clock_en), + + //IF: + .if_hint (core_i.if_stage_i.instr_hint), + .if_dummy (core_i.if_stage_i.dummy_insert), + .kill_if (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_if), + .if_valid (core_i.if_valid), + .ptr_in_if (core_i.if_stage_i.ptr_in_if_o), + .if_first_op (core_i.if_stage_i.first_op), + + //ID: + .operand_a (core_i.id_stage_i.operand_a), + .operand_b (core_i.id_stage_i.operand_b), + .id_instr (core_i.if_id_pipe.instr.bus_resp.rdata), + .id_dummy (core_i.if_id_pipe.instr_meta.dummy), + .id_hint (core_i.if_id_pipe.instr_meta.hint), + .kill_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_id), + .id_ready (core_i.id_ready), + .id_valid (core_i.id_valid), + .id_last_op (core_i.id_stage_i.last_op), + + //EX: + .kill_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_ex), + .ex_ready (core_i.ex_ready), + + //WB: + .kill_wb (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_wb), + .wb_dummy (core_i.ex_wb_pipe.instr_meta.dummy), + .wb_hint (core_i.ex_wb_pipe.instr_meta.hint), + .wb_valid (core_i.wb_valid), + .wb_instr (core_i.ex_wb_pipe.instr.bus_resp.rdata), + + //Controller: + .debug_mode (core_i.controller_i.controller_fsm_i.debug_mode_q), + .stopcount_in_debug (core_i.cs_registers_i.debug_stopcount) + ); + `endif // Debug assertion and coverage interface // Instantiate debug assertions - bind cv32e40s_wrapper - uvmt_cv32e40s_debug_cov_assert_if debug_cov_assert_if ( - .id_valid (core_i.id_stage_i.id_valid_o), - .sys_fence_insn_i (core_i.id_stage_i.decoder_i.sys_fencei_insn_o), - - .ex_stage_csr_en (core_i.id_ex_pipe.csr_en), - .ex_valid (core_i.ex_stage_i.instr_valid), - .ex_stage_instr_rdata_i (core_i.id_ex_pipe.instr.bus_resp.rdata), - .ex_stage_pc (core_i.id_ex_pipe.pc), - - .wb_stage_instr_rdata_i (core_i.ex_wb_pipe.instr.bus_resp.rdata), - .wb_stage_instr_valid_i (core_i.ex_wb_pipe.instr_valid), - .wb_stage_pc (core_i.wb_stage_i.ex_wb_pipe_i.pc), - .wb_err (core_i.ex_wb_pipe.instr.bus_resp.err), - .wb_illegal (core_i.ex_wb_pipe.illegal_insn), - .wb_valid (core_i.wb_stage_i.wb_valid_o), - .wb_mpu_status (core_i.ex_wb_pipe.instr.mpu_status), - .illegal_insn_i (core_i.ex_wb_pipe.illegal_insn), - .sys_en_i (core_i.ex_wb_pipe.sys_en), - .sys_ecall_insn_i (core_i.ex_wb_pipe.sys_ecall_insn), - - .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), - .debug_req_i (core_i.controller_i.controller_fsm_i.debug_req_i), - .debug_havereset (core_i.debug_havereset_o), - .debug_running (core_i.debug_running_o), - .debug_halted (core_i.debug_halted_o), - - .debug_req_q (core_i.controller_i.controller_fsm_i.debug_req_q), - .pending_debug (core_i.controller_i.controller_fsm_i.pending_debug), - .pending_nmi (core_i.controller_i.controller_fsm_i.pending_nmi), - .nmi_allowed (core_i.controller_i.controller_fsm_i.nmi_allowed), - .debug_mode_q (core_i.controller_i.controller_fsm_i.debug_mode_q), - .trigger_match_in_wb (core_i.controller_i.controller_fsm_i.trigger_match_in_wb), - .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), - - .mie_q (core_i.cs_registers_i.mie_q), - .dcsr_q (core_i.cs_registers_i.dcsr_q), - .depc_q (core_i.cs_registers_i.dpc_q), - .depc_n (core_i.cs_registers_i.dpc_n), - .mcause_q (core_i.cs_registers_i.mcause_q), - .mtvec (core_i.cs_registers_i.mtvec_q), - .mepc_q (core_i.cs_registers_i.mepc_q), - .tdata1 (core_i.cs_registers_i.tmatch_control_q), - .tdata2 (core_i.cs_registers_i.tmatch_value_q), - .mcountinhibit_q (core_i.cs_registers_i.mcountinhibit_q), - .mcycle (core_i.cs_registers_i.mhpmcounter_q[0]), - .minstret (core_i.cs_registers_i.mhpmcounter_q[2]), - .csr_we_int (core_i.cs_registers_i.csr_we_int), - - // TODO: review this change from CV32E40S_HASH f6196bf to a26b194. It should be logically equivalent. - //assign debug_cov_assert_if.inst_ret = core_i.cs_registers_i.inst_ret; + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_debug_cov_assert_if_t debug_cov_assert_if ( + .id_valid (core_i.id_stage_i.id_valid_o), + .sys_fence_insn_i (core_i.id_stage_i.decoder_i.sys_fencei_insn_o), + + .ex_stage_csr_en (core_i.id_ex_pipe.csr_en), + .ex_valid (core_i.ex_stage_i.instr_valid), + .ex_stage_instr_rdata_i (core_i.id_ex_pipe.instr.bus_resp.rdata), + .ex_stage_pc (core_i.id_ex_pipe.pc), + + .wb_stage_instr_rdata_i (core_i.ex_wb_pipe.instr.bus_resp.rdata), + .wb_stage_instr_valid_i (core_i.ex_wb_pipe.instr_valid), + .wb_stage_pc (core_i.wb_stage_i.ex_wb_pipe_i.pc), + .wb_err (core_i.ex_wb_pipe.instr.bus_resp.err), + .wb_illegal (core_i.ex_wb_pipe.illegal_insn), + .wb_valid (core_i.wb_stage_i.wb_valid_o), + .wb_mpu_status (core_i.ex_wb_pipe.instr.mpu_status), + .illegal_insn_i (core_i.ex_wb_pipe.illegal_insn), + .sys_en_i (core_i.ex_wb_pipe.sys_en), + .sys_ecall_insn_i (core_i.ex_wb_pipe.sys_ecall_insn), + + .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), + .debug_req_i (core_i.controller_i.controller_fsm_i.debug_req_i), + .debug_havereset (core_i.debug_havereset_o), + .debug_running (core_i.debug_running_o), + .debug_halted (core_i.debug_halted_o), + .debug_pc_o (core_i.debug_pc_o), + .debug_pc_valid_o (core_i.debug_pc_valid_o), + + .ctrl_fsm_async_debug_allowed (core_i.controller_i.controller_fsm_i.async_debug_allowed), + .pending_sync_debug (core_i.controller_i.controller_fsm_i.pending_sync_debug), + .pending_async_debug (core_i.controller_i.controller_fsm_i.pending_async_debug), + .pending_nmi (core_i.controller_i.controller_fsm_i.pending_nmi), + .nmi_allowed (core_i.controller_i.controller_fsm_i.nmi_allowed), + .debug_mode_q (core_i.controller_i.controller_fsm_i.debug_mode_q), + .debug_mode_if (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.debug_mode_if), + .ctrl_halt_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_ex), + .trigger_match_in_wb (core_i.controller_i.controller_fsm_i.trigger_match_in_wb), + .etrigger_in_wb (core_i.controller_i.controller_fsm_i.etrigger_in_wb), + .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), + + .mie_q (core_i.cs_registers_i.mie_q), + .dcsr_q (core_i.cs_registers_i.dcsr_q), + .dpc_q (core_i.cs_registers_i.dpc_q), + .dpc_n (core_i.cs_registers_i.dpc_n), + .mcause_q (core_i.cs_registers_i.mcause_q), + .mtvec (core_i.cs_registers_i.mtvec_q), + .mepc_q (core_i.cs_registers_i.mepc_q), + .tdata1 (core_i.cs_registers_i.tdata1_rdata), + .tdata2 (core_i.cs_registers_i.tdata2_rdata), + .mcountinhibit_q (core_i.cs_registers_i.mcountinhibit_q), + .mcycle (core_i.cs_registers_i.mhpmcounter_q[0]), + .minstret (core_i.cs_registers_i.mhpmcounter_q[2]), + .csr_we_int (core_i.cs_registers_i.csr_we_int), + + // TODO: review this change from CV32E40S_HASH f6196bf to a26b194. It should be logically equivalent. + //assign debug_cov_assert_if.inst_ret = core_i.cs_registers_i.inst_ret; // First attempt: this causes unexpected failures of a_minstret_count //assign debug_cov_assert_if.inst_ret = (core_i.id_valid & // core_i.is_decoding); @@ -459,25 +1391,12 @@ module uvmt_cv32e40s_tb; .irq_id_o (core_i.irq_id), .dm_halt_addr_i (core_i.dm_halt_addr_i), .dm_exception_addr_i (core_i.dm_exception_addr_i), - .nmi_addr_i (core_i.nmi_addr_i), .core_sleep_o (core_i.core_sleep_o), .irq_i (core_i.irq_i), .pc_set (core_i.ctrl_fsm.pc_set), .boot_addr_i (core_i.boot_addr_i), - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_insn (rvfi_i.rvfi_insn), - .rvfi_intr (rvfi_i.rvfi_intr), - .rvfi_dbg (rvfi_i.rvfi_dbg), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - .rvfi_pc_wdata (rvfi_i.rvfi_pc_wdata), - .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), - .rvfi_csr_dpc_rdata (rvfi_i.rvfi_csr_dpc_rdata), - .rvfi_csr_mepc_wdata (rvfi_i.rvfi_csr_mepc_wdata), - .rvfi_csr_mepc_wmask (rvfi_i.rvfi_csr_mepc_wmask), - .is_wfi (), - .in_wfi (), .dpc_will_hit (), .addr_match (), .is_ebreak (), @@ -488,79 +1407,528 @@ module uvmt_cv32e40s_tb; .* ); + `endif + + + logic [31:0] tdata1_array[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS+1]; + logic [31:0] tdata2_array[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS+1]; + + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS > 0) begin + for (genvar t = 0; t < uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS; t++) begin + assign tdata1_array[t] = dut_wrap.cv32e40s_wrapper_i.core_i.cs_registers_i.debug_triggers_i.gen_triggers.tdata1_rdata[t]; + assign tdata2_array[t] = dut_wrap.cv32e40s_wrapper_i.core_i.cs_registers_i.debug_triggers_i.gen_triggers.tdata2_rdata[t]; + end + assign tdata1_array[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS] = '0; + assign tdata2_array[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS] = '0; + + end else begin + assign tdata1_array = {'0}; + assign tdata2_array = {'0}; + end + + + bind cv32e40s_wrapper + uvmt_cv32e40s_support_logic_module_i_if_t support_logic_module_i_if ( + .clk (core_i.clk), + .rst_n (rst_ni), + + .if_instr (core_i.if_stage_i.prefetch_instr.bus_resp.rdata), + .id_instr (core_i.if_id_pipe.instr.bus_resp.rdata), + .ex_instr (core_i.id_ex_pipe.instr.bus_resp.rdata), + .wb_instr (core_i.ex_wb_pipe.instr.bus_resp.rdata), + + .tdata1_array (uvmt_cv32e40s_tb.tdata1_array), + .tdata2_array (uvmt_cv32e40s_tb.tdata2_array), + + .ctrl_fsm_o (core_i.controller_i.controller_fsm_i.ctrl_fsm_o), + + .fetch_enable (core_i.fetch_enable), + .debug_req_i (core_i.debug_req_i), + .irq_ack (core_i.irq_ack), + + .wb_valid (core_i.wb_stage_i.wb_valid_o), + .wb_tselect (core_i.cs_registers_i.tselect_rdata), + .wb_tdata1 (core_i.cs_registers_i.tdata1_rdata), + .wb_tdata2 (core_i.cs_registers_i.tdata2_rdata), + + .data_bus_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), + .data_bus_req (core_i.m_c_obi_data_if.s_req.req), + .data_bus_gnt (core_i.m_c_obi_data_if.s_gnt.gnt), + .data_bus_gntpar (core_i.m_c_obi_data_if.s_gnt.gntpar), + + .instr_bus_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), + .instr_bus_req (core_i.m_c_obi_instr_if.s_req.req), + .instr_bus_gnt (core_i.m_c_obi_instr_if.s_gnt.gnt), + .instr_bus_gntpar (core_i.m_c_obi_instr_if.s_gnt.gntpar), + + //obi protocol between alignmentbuffer (ab) and instructoin (i) interface (i) mpu (m) is refered to as abiim + .abiim_bus_rvalid (core_i.if_stage_i.prefetch_resp_valid), + .abiim_bus_req (core_i.if_stage_i.prefetch_trans_ready), + .abiim_bus_gnt (core_i.if_stage_i.prefetch_trans_valid), + + //obi protocol between LSU (l) mpu (m) and LSU (l) is refered to as lml + .lml_bus_rvalid (core_i.load_store_unit_i.resp_valid), + .lml_bus_req (core_i.load_store_unit_i.trans_ready), + .lml_bus_gnt (core_i.load_store_unit_i.trans_valid), + + //obi protocol between LSU (l) respons (r) filter (f) and OBI (o) data (d) interface (i) is refered to as lrfodi + .lrfodi_bus_rvalid (core_i.load_store_unit_i.bus_resp_valid), + .lrfodi_bus_req (core_i.load_store_unit_i.buffer_trans_valid), + .lrfodi_bus_gnt (core_i.load_store_unit_i.buffer_trans_ready), + + .req_instr_integrity (core_i.m_c_obi_instr_if.req_payload.integrity), + .req_data_integrity (core_i.m_c_obi_data_if.req_payload.integrity) + ); + + bind cv32e40s_wrapper + uvmt_cv32e40s_support_logic_module_o_if_t support_logic_module_o_if(); + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_pmp : + uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i + uvmt_cv32e40s_pmp_assert #( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .IS_INSTR_SIDE (1'b1), + .PMP_MSECCFG_RV (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_MSECCFG_RV) + ) + u_pmp_assert_if_stage(.rst_n (clknrst_if.reset_n), + .bus_trans_dbg (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.bus_trans_o.dbg), + .obi_addr (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.instr_addr_o), + .obi_gnt (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.instr_gnt_i), + .obi_req (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.instr_req_o), + .rvfi_pc_rdata (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_pc_rdata), + .rvfi_valid (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_valid), + .*); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_pmp : + uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i + uvmt_cv32e40s_pmp_assert#( + .PMP_GRANULARITY (PMP_GRANULARITY), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS), + .IS_INSTR_SIDE (1'b0), + .PMP_MSECCFG_RV (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_MSECCFG_RV) + ) + u_pmp_assert_lsu(.rst_n (clknrst_if.reset_n), + .bus_trans_dbg (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.bus_trans_o.dbg), + .obi_addr (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.data_addr_o), + .obi_gnt (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.data_gnt_i), + .obi_req (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.data_req_o), + .rvfi_pc_rdata (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_pc_rdata), + .rvfi_valid (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_valid), + .*); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.rvfi_i + uvmt_cv32e40s_pmprvfi_assert #( + .PMP_GRANULARITY (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_GRANULARITY), + .PMP_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_NUM_REGIONS) + ) pmprvfi_assert_i ( + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .rvfi_mem_addr (rvfi_mem_addr [31:0]), + .rvfi_mem_wmask (rvfi_mem_wmask[ 3:0]), + .rvfi_mem_rmask (rvfi_mem_rmask[ 3:0]), + .* + ); + `endif + + + // PMA Asserts & Covers + + wire pma_status_t pma_status_instr; + wire pma_status_t pma_status_data; + wire pma_status_t pma_status_rvfidata_word0lowbyte; + wire pma_status_t pma_status_rvfidata_word0highbyte; + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i + uvmt_cv32e40s_pma_model #( + .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), + .DM_REGION_START (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_START), + .IS_INSTR_SIDE (1'b 1), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) pma_model_instr_i ( + .addr_i (pma_i.trans_addr_i), + .dbg (core_trans_i.dbg), + .jvt_q (core_i.cs_registers_i.jvt_q), + .pma_status_o (uvmt_cv32e40s_tb.pma_status_instr), + .* + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i + uvmt_cv32e40s_pma_model #( + .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), + .DM_REGION_START (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_START), + .IS_INSTR_SIDE (1'b 0), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) pma_model_data_i ( + .addr_i (pma_i.trans_addr_i), + .dbg (core_trans_i.dbg), + .jvt_q (core_i.cs_registers_i.jvt_q), + .pma_status_o (uvmt_cv32e40s_tb.pma_status_data), + .* + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i + uvmt_cv32e40s_pma_model #( + .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), + .DM_REGION_START (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_START), + .IS_INSTR_SIDE (1'b 0), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) pma_model_rvfidata_low_i ( + .clk (clknrst_if.clk), + .rst_n (clknrst_if.reset_n), + .addr_i (rvfi_instr_if.rvfi_mem_addr[31:0]), + .core_trans_pushpop_i (rvfi_instr_if.is_pushpop), + .dbg (rvfi_instr_if.rvfi_dbg_mode), + .jvt_q (rvfi_csr_jvt_if.rvfi_csr_rdata), + .load_access (|rvfi_instr_if.rvfi_mem_rmask), + .misaligned_access_i (rvfi_instr_if.is_split_datatrans_intended), + .pma_status_o (uvmt_cv32e40s_tb.pma_status_rvfidata_word0lowbyte) + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i + uvmt_cv32e40s_pma_model #( + .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), + .DM_REGION_START (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_START), + .IS_INSTR_SIDE (1'b 0), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) pma_model_rvfidata_high_i ( + .clk (clknrst_if.clk), + .rst_n (clknrst_if.reset_n), + .addr_i (rvfi_instr_if.rvfi_mem_addr_word0highbyte), + // TODO:WARNING:silabs-robin Should use "instr_mem_addr_word0highbyte"? + .core_trans_pushpop_i (rvfi_instr_if.is_pushpop), + .dbg (rvfi_instr_if.rvfi_dbg_mode), + .jvt_q (rvfi_csr_jvt_if.rvfi_csr_rdata), + .load_access (|rvfi_instr_if.rvfi_mem_rmask), + .misaligned_access_i (rvfi_instr_if.is_split_datatrans_intended), + .pma_status_o (uvmt_cv32e40s_tb.pma_status_rvfidata_word0highbyte) + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i + uvmt_cv32e40s_pma_assert #( + .CORE_REQ_TYPE (cv32e40s_pkg::obi_inst_req_t), + .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), + .DM_REGION_START (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_START), + .IS_INSTR_SIDE (1), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) pma_assert_instr_i ( + .obi_memory_if (dut_wrap.obi_instr_if), + .rvfi_instr_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .writebuf_ready_o ('0), + .writebuf_trans_i ('0), + .writebuf_trans_o ('0), + .pma_status_i (uvmt_cv32e40s_tb.pma_status_instr), + .* + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i + uvmt_cv32e40s_pma_assert #( + .CORE_REQ_TYPE (cv32e40s_pkg::obi_data_req_t), + .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), + .DM_REGION_START (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_START), + .IS_INSTR_SIDE (0), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) pma_assert_data_i ( + .obi_memory_if (dut_wrap.obi_data_if), + .rvfi_instr_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .writebuf_ready_o (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.ready_o), + .writebuf_trans_i (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.trans_i), + .writebuf_trans_o (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.trans_o), + .pma_status_i (uvmt_cv32e40s_tb.pma_status_data), + .* + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i + uvmt_cv32e40s_pma_cov #( + .CORE_REQ_TYPE (cv32e40s_pkg::obi_inst_req_t), + .IS_INSTR_SIDE (1'b 1), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS) + ) pma_cov_instr_i ( + .clk_ungated (clknrst_if.clk), + .pma_status_i (uvmt_cv32e40s_tb.pma_status_instr), + .pma_status_rvfidata_word0lowbyte_i (uvmt_cv32e40s_tb.pma_status_rvfidata_word0lowbyte), + .pma_status_rvfidata_word0highbyte_i (uvmt_cv32e40s_tb.pma_status_rvfidata_word0highbyte), + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .* + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i + uvmt_cv32e40s_pma_cov #( + .CORE_REQ_TYPE (cv32e40s_pkg::obi_data_req_t), + .IS_INSTR_SIDE (1'b 0), + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS) + ) pma_cov_data_i ( + .clk_ungated (clknrst_if.clk), + .pma_status_i (uvmt_cv32e40s_tb.pma_status_data), + .pma_status_rvfidata_word0lowbyte_i (uvmt_cv32e40s_tb.pma_status_rvfidata_word0lowbyte), + .pma_status_rvfidata_word0highbyte_i (uvmt_cv32e40s_tb.pma_status_rvfidata_word0highbyte), + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .* + ); + `endif + + + // Support Logic + + bind cv32e40s_wrapper uvmt_cv32e40s_support_logic u_support_logic(.rvfi (rvfi_instr_if), + .in_support_if (support_logic_module_i_if.driver_mp), + .out_support_if (support_logic_module_o_if.master_mp), + .data_obi_if (dut_wrap.obi_data_if), + .instr_obi_if (dut_wrap.obi_instr_if) + ); + + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper uvmt_cv32e40s_debug_assert u_debug_assert(.rvfi(rvfi_instr_if), + .csr_dcsr(rvfi_csr_dcsr_if), + .csr_dpc(rvfi_csr_dpc_if), + .csr_dscratch0(rvfi_csr_dscratch0_if), + .csr_dscratch1(rvfi_csr_dscratch1_if), + .csr_mepc(rvfi_csr_mepc_if), + .csr_mstatus(rvfi_csr_mstatus_if), + .csr_mcause(rvfi_csr_mcause_if), + .csr_mtvec(rvfi_csr_mtvec_if), + .csr_tdata1(rvfi_csr_tdata1_if), + .csr_tdata2(rvfi_csr_tdata2_if), + .instr_obi(dut_wrap.obi_instr_if), + .data_obi(dut_wrap.obi_data_if), + .cov_assert_if(debug_cov_assert_if), + .support_if (support_logic_module_o_if.slave_mp) + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper uvmt_cv32e40s_triggers_assert_cov debug_trigger_assert_i( + .tdata1_array (uvmt_cv32e40s_tb.tdata1_array), + .priv_lvl (core_i.priv_lvl), + .rvfi_if (rvfi_instr_if), + .clknrst_if (dut_wrap.clknrst_if), + .support_if (support_logic_module_o_if.slave_mp), + .tdata1_if (rvfi_csr_tdata1_if), + .tdata2_if (rvfi_csr_tdata2_if), + .tinfo_if (rvfi_csr_tinfo_if), + .tselect_if (rvfi_csr_tselect_if), + .dcsr_if (rvfi_csr_dcsr_if), + .dpc_if (rvfi_csr_dpc_if) + ); + `endif + + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper uvmt_cv32e40s_zc_assert u_zc_assert(.rvfi(rvfi_instr_if), + .support_if(support_logic_module_o_if.slave_mp) + ); + `endif - bind cv32e40s_wrapper uvmt_cv32e40s_debug_assert u_debug_assert(.cov_assert_if(debug_cov_assert_if)); //uvmt_cv32e40s_rvvi_handcar u_rvvi_handcar(); - /** - * ISS WRAPPER instance: - */ - uvmt_cv32e40s_iss_wrap #( - .ID (0), - .ROM_START_ADDR('h0), - .ROM_BYTE_SIZE('h0), - .RAM_BYTE_SIZE('h1_0000_0000) - ) - iss_wrap ( .clk_period(clknrst_if.clk_period), - .clknrst_if(clknrst_if_iss) - ); - - assign clknrst_if_iss.reset_n = clknrst_if.reset_n; + + // IMPERAS DV + `ifndef FORMAL + uvmt_cv32e40s_imperas_dv_wrap imperas_dv (rvvi_if); + `endif /** * Test bench entry point. */ + `ifndef FORMAL // Formal ignores initial blocks, avoids unnecessary warning initial begin : test_bench_entry_point // Specify time format for simulation (units_number, precision_number, suffix_string, minimum_field_width) $timeformat(-9, 3, " ns", 8); + uvm_config_db#(virtual uvmt_imperas_dv_if_t)::set(.cntxt(null), .inst_name("uvm_test_top"), .field_name("idv_support_vif"), .value(imperas_dv_if)); // Add interfaces handles to uvm_config_db - uvm_config_db#(virtual uvma_isacov_if )::set(.cntxt(null), .inst_name("*.env.isacov_agent"), .field_name("vif"), .value(isacov_if)); - uvm_config_db#(virtual uvma_debug_if )::set(.cntxt(null), .inst_name("*.env.debug_agent"), .field_name("vif"), .value(debug_if)); - uvm_config_db#(virtual uvma_clknrst_if )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"), .value(clknrst_if)); - uvm_config_db#(virtual uvma_interrupt_if )::set(.cntxt(null), .inst_name("*.env.interrupt_agent"), .field_name("vif"), .value(interrupt_if)); - uvm_config_db#(virtual uvma_obi_memory_if )::set(.cntxt(null), .inst_name("*.env.obi_memory_instr_agent"), .field_name("vif"), .value(obi_instr_if_i) ); - uvm_config_db#(virtual uvma_obi_memory_if )::set(.cntxt(null), .inst_name("*.env.obi_memory_data_agent"), .field_name("vif"), .value(obi_data_if_i) ); - uvm_config_db#(virtual uvma_fencei_if )::set(.cntxt(null), .inst_name("*.env.fencei"), .field_name("vif"), .value(fencei_if_i)); - uvm_config_db#(virtual uvma_rvfi_instr_if )::set(.cntxt(null), .inst_name("*.env.rvfi_agent"), .field_name("instr_vif0"),.value(dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if_0_i)); - uvm_config_db#(virtual uvma_fencei_if )::set(.cntxt(null), .inst_name("*.env.fencei_agent"), .field_name("fencei_vif"), .value(fencei_if_i) ); - uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if )::set(.cntxt(null), .inst_name("*"), .field_name("vp_status_vif"), .value(vp_status_if) ); - uvm_config_db#(virtual uvma_interrupt_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("intr_vif"), .value(interrupt_if) ); - uvm_config_db#(virtual uvma_debug_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_vif"), .value(debug_if) ); -// uvm_config_db#(virtual uvmt_cv32e40s_debug_cov_assert_if)::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"), .value(debug_cov_assert_if)); + uvm_config_db#(virtual uvma_debug_if_t )::set(.cntxt(null), .inst_name("*.env.debug_agent"), .field_name("vif"), .value(debug_if)); + uvm_config_db#(virtual uvma_clknrst_if_t )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"), .value(clknrst_if)); + uvm_config_db#(virtual uvma_interrupt_if_t )::set(.cntxt(null), .inst_name("*.env.interrupt_agent"), .field_name("vif"), .value(interrupt_if)); + uvm_config_db#(virtual uvma_wfe_wu_if_t )::set(.cntxt(null), .inst_name("*.env.wfe_wu_agent"), .field_name("vif"), .value(wfe_wu_if)); + uvm_config_db#(virtual uvma_clic_if_t#( + .CLIC_ID_WIDTH(uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) + ))::set(.cntxt(null), .inst_name("*.env.clic_agent"), .field_name("vif"), .value(clic_if)); + + uvm_config_db#(virtual uvma_obi_memory_if_t#( + .AUSER_WIDTH(ENV_PARAM_INSTR_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_INSTR_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_INSTR_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_INSTR_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_INSTR_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_INSTR_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_INSTR_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_INSTR_RCHK_WIDTH) + ))::set(.cntxt(null), .inst_name("*.env.obi_memory_instr_agent"), .field_name("vif"), .value(obi_instr_if) ); + uvm_config_db#(virtual uvma_obi_memory_if_t#( + .AUSER_WIDTH(ENV_PARAM_DATA_AUSER_WIDTH), + .WUSER_WIDTH(ENV_PARAM_DATA_WUSER_WIDTH), + .RUSER_WIDTH(ENV_PARAM_DATA_RUSER_WIDTH), + .ADDR_WIDTH(ENV_PARAM_DATA_ADDR_WIDTH), + .DATA_WIDTH(ENV_PARAM_DATA_DATA_WIDTH), + .ID_WIDTH(ENV_PARAM_DATA_ID_WIDTH), + .ACHK_WIDTH(ENV_PARAM_DATA_ACHK_WIDTH), + .RCHK_WIDTH(ENV_PARAM_DATA_RCHK_WIDTH) + ))::set(.cntxt(null), .inst_name("*.env.obi_memory_data_agent"), .field_name("vif"), .value(obi_data_if) ); + uvm_config_db#(virtual uvma_fencei_if_t )::set(.cntxt(null), .inst_name("*.env.fencei"), .field_name("vif"), .value(fencei_if)); + uvm_config_db#(virtual uvma_rvfi_instr_if_t )::set(.cntxt(null), .inst_name("*.env.rvfi_agent"), .field_name("instr_vif0"), .value(dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if)); + uvm_config_db#(virtual uvma_fencei_if_t )::set(.cntxt(null), .inst_name("*.env.fencei_agent"), .field_name("fencei_vif"), .value(fencei_if) ); + uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if_t)::set(.cntxt(null), .inst_name("*"), .field_name("vp_status_vif"), .value(vp_status_if) ); + uvm_config_db#(virtual uvma_interrupt_if_t )::set(.cntxt(null), .inst_name("*.env"), .field_name("intr_vif"), .value(interrupt_if) ); + uvm_config_db#(virtual uvma_debug_if_t )::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_vif"), .value(debug_if) ); + uvm_config_db#(virtual uvma_wfe_wu_if_t )::set(.cntxt(null), .inst_name("*.env"), .field_name("wfe_wu_vif"), .value(wfe_wu_if) ); + uvm_config_db#(virtual uvma_clic_if_t#( + .CLIC_ID_WIDTH(uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) + ))::set(.cntxt(null), .inst_name("*.env"), .field_name("clic_vif"), .value(clic_if) ); +// uvm_config_db#(virtual uvmt_cv32e40s_debug_cov_assert_if_t)::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"), .value(debug_cov_assert_if)); + `RVFI_CSR_UVM_CONFIG_DB_SET(cpuctrl) + `RVFI_CSR_UVM_CONFIG_DB_SET(jvt) `RVFI_CSR_UVM_CONFIG_DB_SET(marchid) + `RVFI_CSR_UVM_CONFIG_DB_SET(mcause) + `RVFI_CSR_UVM_CONFIG_DB_SET(mcounteren) `RVFI_CSR_UVM_CONFIG_DB_SET(mcountinhibit) - `RVFI_CSR_UVM_CONFIG_DB_SET(mstatus) - `RVFI_CSR_UVM_CONFIG_DB_SET(mstatush) - `RVFI_CSR_UVM_CONFIG_DB_SET(misa) - `RVFI_CSR_UVM_CONFIG_DB_SET(mtvec) - `RVFI_CSR_UVM_CONFIG_DB_SET(mtval) - `RVFI_CSR_UVM_CONFIG_DB_SET(mvendorid) - `RVFI_CSR_UVM_CONFIG_DB_SET(mscratch) + `RVFI_CSR_UVM_CONFIG_DB_SET(mcycle) + `RVFI_CSR_UVM_CONFIG_DB_SET(mcycleh) + `RVFI_CSR_UVM_CONFIG_DB_SET(menvcfg) + `RVFI_CSR_UVM_CONFIG_DB_SET(menvcfgh) `RVFI_CSR_UVM_CONFIG_DB_SET(mepc) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcause) - `RVFI_CSR_UVM_CONFIG_DB_SET(mip) - `RVFI_CSR_UVM_CONFIG_DB_SET(mie) `RVFI_CSR_UVM_CONFIG_DB_SET(mhartid) + `RVFI_CSR_UVM_CONFIG_DB_SET(mie) `RVFI_CSR_UVM_CONFIG_DB_SET(mimpid) `RVFI_CSR_UVM_CONFIG_DB_SET(minstret) `RVFI_CSR_UVM_CONFIG_DB_SET(minstreth) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcontext) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcycle) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcycleh) + `RVFI_CSR_UVM_CONFIG_DB_SET(mip) + `RVFI_CSR_UVM_CONFIG_DB_SET(misa) + `RVFI_CSR_UVM_CONFIG_DB_SET(mscratch) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen0) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen1) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen2) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen3) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen0h) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen1h) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen2h) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstateen3h) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstatus) + `RVFI_CSR_UVM_CONFIG_DB_SET(mstatush) + `RVFI_CSR_UVM_CONFIG_DB_SET(mtval) + `RVFI_CSR_UVM_CONFIG_DB_SET(mtvec) + `RVFI_CSR_UVM_CONFIG_DB_SET(mvendorid) + `RVFI_CSR_UVM_CONFIG_DB_SET(mseccfg) + `RVFI_CSR_UVM_CONFIG_DB_SET(mseccfgh) `RVFI_CSR_UVM_CONFIG_DB_SET(dcsr) `RVFI_CSR_UVM_CONFIG_DB_SET(dpc) `RVFI_CSR_UVM_CONFIG_DB_SET(dscratch0) `RVFI_CSR_UVM_CONFIG_DB_SET(dscratch1) - `RVFI_CSR_UVM_CONFIG_DB_SET(scontext) `RVFI_CSR_UVM_CONFIG_DB_SET(tselect) `RVFI_CSR_UVM_CONFIG_DB_SET(tdata1) `RVFI_CSR_UVM_CONFIG_DB_SET(tdata2) - `RVFI_CSR_UVM_CONFIG_DB_SET(tdata3) `RVFI_CSR_UVM_CONFIG_DB_SET(tinfo) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg0) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg1) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg2) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg3) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg4) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg5) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg6) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg7) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg8) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg9) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg10) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg11) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg12) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg13) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg14) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg15) + + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr0) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr1) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr2) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr3) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr4) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr5) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr6) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr7) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr8) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr9) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr10) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr11) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr12) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr13) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr14) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr15) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr16) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr17) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr18) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr19) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr20) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr21) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr22) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr23) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr24) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr25) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr26) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr27) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr28) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr29) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr30) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr31) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr32) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr33) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr34) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr35) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr36) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr37) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr38) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr39) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr40) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr41) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr42) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr43) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr44) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr45) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr46) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr47) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr48) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr49) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr50) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr51) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr52) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr53) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr54) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr55) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr56) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr57) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr58) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr59) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr60) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr61) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr62) + `RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr63) + `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent3) `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent4) `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent5) @@ -652,17 +2020,31 @@ module uvmt_cv32e40s_tb; `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter31h) `RVFI_CSR_UVM_CONFIG_DB_SET(mconfigptr) - uvm_config_db#(virtual RVVI_state#(.ILEN(uvme_cv32e40s_pkg::ILEN), - .XLEN(uvme_cv32e40s_pkg::XLEN) - ))::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("state_vif"), .value(iss_wrap.cpu.state)); - uvm_config_db#(virtual RVVI_control )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("control_vif"), .value(iss_wrap.cpu.control)); - uvm_config_db#(virtual RVVI_bus )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("ovpsim_bus_vif"), .value(iss_wrap.bus)); - uvm_config_db#(virtual RVVI_io )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("ovpsim_io_vif"), .value(iss_wrap.io)); - uvm_config_db#(virtual RVVI_memory )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("ovpsim_mem_vif"), .value(iss_wrap.ram.memory)); - uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if )::set(.cntxt(null), .inst_name("*"), .field_name("vp_status_vif"), .value(vp_status_if) ); - uvm_config_db#(virtual uvme_cv32e40s_core_cntrl_if )::set(.cntxt(null), .inst_name("*"), .field_name("core_cntrl_vif"), .value(core_cntrl_if) ); - uvm_config_db#(virtual uvmt_cv32e40s_core_status_if )::set(.cntxt(null), .inst_name("*"), .field_name("core_status_vif"), .value(core_status_if) ); - uvm_config_db#(virtual uvmt_cv32e40s_debug_cov_assert_if)::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"),.value(dut_wrap.cv32e40s_wrapper_i.debug_cov_assert_if)); + `RVFI_CSR_UVM_CONFIG_DB_SET(secureseed0) + `RVFI_CSR_UVM_CONFIG_DB_SET(secureseed1) + `RVFI_CSR_UVM_CONFIG_DB_SET(secureseed2) + + `ifdef CLIC_EN + // TODO:silabs-robin What about when using "PARAM_SET_0"? + `RVFI_CSR_UVM_CONFIG_DB_SET(mintstatus) + `RVFI_CSR_UVM_CONFIG_DB_SET(mintthresh) + `RVFI_CSR_UVM_CONFIG_DB_SET(mnxti) + `RVFI_CSR_UVM_CONFIG_DB_SET(mscratchcsw) + `RVFI_CSR_UVM_CONFIG_DB_SET(mscratchcswl) + `RVFI_CSR_UVM_CONFIG_DB_SET(mtvt) + `endif + + // IMPERAS_DV interface + if ($test$plusargs("USE_ISS")) begin + uvm_config_db#(virtual rvviTrace)::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("rvvi_vif"), .value(rvvi_if)); + end + + // Virtual Peripheral Status interface + uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if_t )::set(.cntxt(null), .inst_name("*"), .field_name("vp_status_vif"), .value(vp_status_if) ); + uvm_config_db#(virtual uvme_cv32e40s_core_cntrl_if_t )::set(.cntxt(null), .inst_name("*"), .field_name("core_cntrl_vif"), .value(core_cntrl_if) ); + uvm_config_db#(virtual uvmt_cv32e40s_core_status_if_t )::set(.cntxt(null), .inst_name("*"), .field_name("core_status_vif"), .value(core_status_if) ); + uvm_config_db#(virtual uvmt_cv32e40s_debug_cov_assert_if_t )::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"),.value(dut_wrap.cv32e40s_wrapper_i.debug_cov_assert_if)); + uvm_config_db#(virtual uvmt_cv32e40s_support_logic_module_o_if_t )::set(.cntxt(null), .inst_name("*.env"), .field_name("support_logic_vif"),.value(dut_wrap.cv32e40s_wrapper_i.support_logic_module_o_if)); // Make the DUT Wrapper Virtual Peripheral's status outputs available to the base_test uvm_config_db#(bit )::set(.cntxt(null), .inst_name("*"), .field_name("tp"), .value(1'b0) ); @@ -670,7 +2052,7 @@ module uvmt_cv32e40s_tb; uvm_config_db#(bit )::set(.cntxt(null), .inst_name("*"), .field_name("evalid"), .value(1'b0) ); uvm_config_db#(bit[31:0])::set(.cntxt(null), .inst_name("*"), .field_name("evalue"), .value(32'h00000000)); - // DUT and ENV parameters + // DUT and ENV parameters uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_ADDR_WIDTH"), .value(ENV_PARAM_INSTR_ADDR_WIDTH) ); uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_DATA_WIDTH"), .value(ENV_PARAM_INSTR_DATA_WIDTH) ); uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_RAM_ADDR_WIDTH"), .value(ENV_PARAM_RAM_ADDR_WIDTH) ); @@ -680,62 +2062,46 @@ module uvmt_cv32e40s_tb; uvm_top.finish_on_completion = 1; uvm_top.run_test(); end : test_bench_entry_point + `endif assign core_cntrl_if.clk = clknrst_if.clk; - // Informational print message on loading of OVPSIM ISS to benchmark some elf image loading times - // OVPSIM runs its initialization at the #1ns timestamp, and should dominate the initial startup time - longint start_ovpsim_init_time; - longint end_ovpsim_init_time; - initial begin - if (!$test$plusargs("DISABLE_OVPSIM")) begin - #0.9ns; - `uvm_info("OVPSIM", $sformatf("Start benchmarking OVPSIM initialization"), UVM_LOW) - start_ovpsim_init_time = svlib_pkg::sys_dayTime(); - #1.1ns; - end_ovpsim_init_time = svlib_pkg::sys_dayTime(); - `uvm_info("OVPSIM", $sformatf("Initialization time: %0d seconds", end_ovpsim_init_time - start_ovpsim_init_time), UVM_LOW) - end - end - - //TODO verify these are correct with regards to isacov function - always @(dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if_0_i.rvfi_valid) -> isacov_if.retire; - assign isacov_if.instr = dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if_0_i.rvfi_insn; - //assign isacov_if.is_compressed = dut_wrap.cv32e40s_wrapper_i.tracer_i.insn_compressed; - // Capture the test status and exit pulse flags // TODO: put this logic in the vp_status_if (makes it easier to pass to ENV) - always @(posedge clknrst_if.clk) begin - if (!clknrst_if.reset_n) begin - tp <= 1'b0; - tf <= 1'b0; - evalid <= 1'b0; - evalue <= 32'h00000000; - end - else begin - if (vp_status_if.tests_passed) begin - tp <= 1'b1; - uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("tp"), .value(1'b1)); - end - if (vp_status_if.tests_failed) begin - tf <= 1'b1; - uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("tf"), .value(1'b1)); - end - if (vp_status_if.exit_valid) begin - evalid <= 1'b1; - uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("evalid"), .value(1'b1)); + `ifndef FORMAL // uvm db not used in formal + always @(posedge clknrst_if.clk) begin + if (!clknrst_if.reset_n) begin + tp <= 1'b0; + tf <= 1'b0; + evalid <= 1'b0; + evalue <= 32'h00000000; end - if (vp_status_if.exit_valid) begin - evalue <= vp_status_if.exit_value; - uvm_config_db#(bit[31:0])::set(.cntxt(null), .inst_name("*"), .field_name("evalue"), .value(vp_status_if.exit_value)); + else begin + if (vp_status_if.tests_passed) begin + tp <= 1'b1; + uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("tp"), .value(1'b1)); + end + if (vp_status_if.tests_failed) begin + tf <= 1'b1; + uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("tf"), .value(1'b1)); + end + if (vp_status_if.exit_valid) begin + evalid <= 1'b1; + uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("evalid"), .value(1'b1)); + end + if (vp_status_if.exit_valid) begin + evalue <= vp_status_if.exit_value; + uvm_config_db#(bit[31:0])::set(.cntxt(null), .inst_name("*"), .field_name("evalue"), .value(vp_status_if.exit_value)); + end end end - end + `endif // FORMAL /** * End-of-test summary printout. */ + `ifndef FORMAL // Formal ignores final blocks, this avoids unnecessary warning final begin: end_of_test string summary_string; uvm_report_server rs; @@ -753,9 +2119,13 @@ module uvmt_cv32e40s_tb; warning_count = rs.get_severity_count(UVM_WARNING); fatal_count = rs.get_severity_count(UVM_FATAL); + if ($test$plusargs("USE_ISS")) begin + void'(rvviApiPkg::rvviRefShutdown()); + end + void'(uvm_config_db#(bit)::get(null, "", "sim_finished", sim_finished)); - $display("\n%m: *** Test Summary ***\n"); + `uvm_info("DV_WRAP", $sformatf("\n%m: *** Test Summary ***\n"), UVM_DEBUG); if (sim_finished && (err_count == 0) && (fatal_count == 0)) begin $display(" PPPPPPP AAAAAA SSSSSS SSSSSS EEEEEEEE DDDDDDD "); @@ -794,7 +2164,14 @@ module uvmt_cv32e40s_tb; $display(" --------------------------------------------------------"); end end + // If there are any liveness assertions still pending at this time, + // kill all of them to prevent false failures after end of test. + // Actual failures _should_ have been caught and logged at this time + // This is needed as the core is not necessarily terminated by software, + // and there may be outstanding transactions. + $assertkill(); end + `endif endmodule : uvmt_cv32e40s_tb `default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_files.flist b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_files.flist new file mode 100644 index 0000000000..d913d0e03c --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_files.flist @@ -0,0 +1,55 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +${DV_UVMT_PATH}/uvmt_cv32e40s_dut_wrap.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_tb.sv + +${DV_UVMT_PATH}/uvmt_cv32e40s_clic_interrupt_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_debug_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_triggers_assert_cov.sv +${DV_UVMT_PATH}/../assertions/uvmt_cv32e40s_fencei_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_integration_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_interrupt_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_pma_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_pmp_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_pmprvfi_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_rvfi_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_umode_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_data_independent_timing_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_pc_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_dummy_and_hint_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_security_alerts_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_register_file_ecc_assert.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_zc_assert.sv + +${DV_UVMT_PATH}/../assertions/uvmt_cv32e40s_pma_model.sv +${DV_UVMT_PATH}/../assertions/uvmt_cv32e40s_pmp_model.sv +${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_obi_phases_monitor.sv +${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_fifo.sv +${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_trigger_match_mem.sv +${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_trigger_match.sv +${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_support_logic.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_pma_cov.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_rvfi_cov.sv +${DV_UVMT_PATH}/uvmt_cv32e40s_umode_cov.sv diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv index 654d3a03fb..54aaeacee1 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv @@ -27,7 +27,7 @@ /** * clocks and reset */ -interface uvmt_cv32e40s_clk_gen_if (output logic core_clock, output logic core_reset_n); +interface uvmt_cv32e40s_clk_gen_if_t (output logic core_clock, output logic core_reset_n); import uvm_pkg::*; @@ -69,15 +69,15 @@ interface uvmt_cv32e40s_clk_gen_if (output logic core_clock, output logic core_r /** Triggers the generation of clk. */ function void start(); start_clk = 1; - `uvm_info("CLK_GEN_IF", "uvmt_cv32e40s_clk_gen_if.start() called", UVM_NONE) + `uvm_info("CLK_GEN_IF", "uvmt_cv32e40s_clk_gen_if_t.start() called", UVM_NONE) endfunction : start -endinterface : uvmt_cv32e40s_clk_gen_if +endinterface : uvmt_cv32e40s_clk_gen_if_t /** * Status information generated by the Virtual Peripherals in the DUT WRAPPER memory. */ -interface uvmt_cv32e40s_vp_status_if ( +interface uvmt_cv32e40s_vp_status_if_t ( output bit tests_passed, output bit tests_failed, output bit exit_valid, @@ -87,28 +87,28 @@ interface uvmt_cv32e40s_vp_status_if ( import uvm_pkg::*; // TODO: X/Z checks - initial begin - end -endinterface : uvmt_cv32e40s_vp_status_if +endinterface : uvmt_cv32e40s_vp_status_if_t /** * Core status signals. */ -interface uvmt_cv32e40s_core_status_if ( +interface uvmt_cv32e40s_core_status_if_t ( input wire core_busy, input logic sec_lvl ); import uvm_pkg::*; -endinterface : uvmt_cv32e40s_core_status_if +endinterface : uvmt_cv32e40s_core_status_if_t + // Interface to debug assertions and covergroups -interface uvmt_cv32e40s_debug_cov_assert_if +interface uvmt_cv32e40s_debug_cov_assert_if_t import cv32e40s_pkg::*; + import cv32e40s_rvfi_pkg::*; ( input clk_i, input rst_ni, @@ -116,7 +116,7 @@ interface uvmt_cv32e40s_debug_cov_assert_if // External interrupt interface input [31:0] irq_i, input irq_ack_o, - input [4:0] irq_id_o, + input [9:0] irq_id_o, input [31:0] mie_q, input ex_stage_csr_en, @@ -140,34 +140,26 @@ interface uvmt_cv32e40s_debug_cov_assert_if // Core signals input [31:0] boot_addr_i, - input [31:0] nmi_addr_i, - input fetch_enable_i, - - input rvfi_valid, - input [31:0] rvfi_insn, - input rvfi_intr, - input [2:0] rvfi_dbg, - input rvfi_dbg_mode, - input [31:0] rvfi_pc_wdata, - input [31:0] rvfi_pc_rdata, - input [31:0] rvfi_csr_dpc_rdata, - input [31:0] rvfi_csr_mepc_wdata, - input [31:0] rvfi_csr_mepc_wmask, // Debug signals input debug_req_i, // From controller - input debug_req_q, // From controller + input ctrl_fsm_async_debug_allowed, input debug_havereset, input debug_running, input debug_halted, + input [31:0] debug_pc_o, + input debug_pc_valid_o, - input pending_debug, // From controller + input pending_sync_debug, // From controller + input pending_async_debug, // From controller input pending_nmi, // From controller input nmi_allowed, // From controller input debug_mode_q, // From controller + input debug_mode_if, // From controller + input ctrl_halt_ex, // From controller input [31:0] dcsr_q, // From controller - input [31:0] depc_q, // From cs regs //TODO:ropeders rename "dpc_q" - input [31:0] depc_n, + input [31:0] dpc_q, // From cs regs + input [31:0] dpc_n, input [31:0] dm_halt_addr_i, input [31:0] dm_exception_addr_i, @@ -177,6 +169,7 @@ interface uvmt_cv32e40s_debug_cov_assert_if input [31:0] tdata1, input [31:0] tdata2, input trigger_match_in_wb, + input etrigger_in_wb, // Counter related input from cs_registers input [31:0] mcountinhibit_q, @@ -190,12 +183,11 @@ interface uvmt_cv32e40s_debug_cov_assert_if input sys_fence_insn_i, input csr_access, - input [1:0] csr_op, + input cv32e40s_pkg::csr_opcode_e csr_op, input [11:0] csr_addr, input csr_we_int, output logic is_wfi, - output logic in_wfi, output logic dpc_will_hit, output logic addr_match, output logic is_ebreak, @@ -224,13 +216,11 @@ interface uvmt_cv32e40s_debug_cov_assert_if sys_en_i, sys_ecall_insn_i, boot_addr_i, - rvfi_pc_wdata, - rvfi_pc_rdata, debug_req_i, debug_mode_q, dcsr_q, - depc_q, - depc_n, + dpc_q, + dpc_n, dm_halt_addr_i, dm_exception_addr_i, mcause_q, @@ -238,7 +228,9 @@ interface uvmt_cv32e40s_debug_cov_assert_if mepc_q, tdata1, tdata2, + pending_sync_debug, trigger_match_in_wb, + etrigger_in_wb, sys_fence_insn_i, mcountinhibit_q, mcycle, @@ -250,7 +242,6 @@ interface uvmt_cv32e40s_debug_cov_assert_if csr_op, csr_addr, is_wfi, - in_wfi, dpc_will_hit, addr_match, is_ebreak, @@ -262,6 +253,296 @@ interface uvmt_cv32e40s_debug_cov_assert_if branch_in_ex; endclocking : mon_cb -endinterface : uvmt_cv32e40s_debug_cov_assert_if +endinterface : uvmt_cv32e40s_debug_cov_assert_if_t + +interface uvmt_cv32e40s_support_logic_module_i_if_t + import cv32e40s_pkg::*; + import cv32e40s_rvfi_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + ( + + /* obi bus protocol signal information: + --------------------------------------- + - The obi protocol between alignmentbuffer (ab) and instructoin (i) interface (i) mpu (m) is refered to as abiim + - The obi protocol between LSU (l) mpu (m) and LSU (l) is refered to as lml + - The obi protocol between LSU (l) respons (r) filter (f) and OBI (o) data (d) interface (i) is refered to as lrfodi + */ + + input logic clk, + input logic rst_n, + + //Decoder: + input logic [31:0] if_instr, + input logic [31:0] id_instr, + input logic [31:0] ex_instr, + input logic [31:0] wb_instr, + + //Controller fsm control signals output + input ctrl_fsm_t ctrl_fsm_o, + + input logic fetch_enable, + input logic debug_req_i, + input logic irq_ack, + input logic wb_valid, + input logic [31:0] wb_tselect, + input logic [31:0] wb_tdata1, + input logic [31:0] wb_tdata2, + input logic [31:0] tdata1_array[CORE_PARAM_DBG_NUM_TRIGGERS+1], + input logic [31:0] tdata2_array[CORE_PARAM_DBG_NUM_TRIGGERS+1], + + //Obi signals: + + //Data bus inputs + input logic data_bus_rvalid, + input logic data_bus_gnt, + input logic data_bus_gntpar, + input logic data_bus_req, + + //Instr bus inputs + input logic instr_bus_rvalid, + input logic instr_bus_gnt, + input logic instr_bus_gntpar, + input logic instr_bus_req, + + //Abiim bus inputs + input logic abiim_bus_rvalid, + input logic abiim_bus_gnt, + input logic abiim_bus_req, + + //Lml bus inputs + input logic lml_bus_rvalid, + input logic lml_bus_gnt, + input logic lml_bus_req, + + //Instr bus inputs + input logic lrfodi_bus_rvalid, + input logic lrfodi_bus_gnt, + input logic lrfodi_bus_req, + + //Obi request information + input logic req_instr_integrity, + input logic req_data_integrity + + ); + + modport driver_mp ( + input clk, + rst_n, + + if_instr, + id_instr, + ex_instr, + wb_instr, + + tdata1_array, + tdata2_array, + + ctrl_fsm_o, + + fetch_enable, + debug_req_i, + irq_ack, + wb_valid, + wb_tselect, + wb_tdata1, + wb_tdata2, + + data_bus_rvalid, + data_bus_gnt, + data_bus_gntpar, + data_bus_req, + + instr_bus_rvalid, + instr_bus_gnt, + instr_bus_gntpar, + instr_bus_req, + + abiim_bus_rvalid, + abiim_bus_gnt, + abiim_bus_req, + + lml_bus_rvalid, + lml_bus_gnt, + lml_bus_req, + + lrfodi_bus_rvalid, + lrfodi_bus_gnt, + lrfodi_bus_req, + + req_instr_integrity, + req_data_integrity + ); + +endinterface : uvmt_cv32e40s_support_logic_module_i_if_t + + +interface uvmt_cv32e40s_support_logic_module_o_if_t; + import cv32e40s_pkg::*; + import cv32e40s_rvfi_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import isa_decoder_pkg::*; + + //Decoder: + asm_t asm_if; + asm_t asm_id; + asm_t asm_ex; + asm_t asm_wb; + asm_t asm_rvfi; + + //OBI packets: + obi_data_packet_t obi_data_packet; + obi_instr_packet_t obi_instr_packet; + + // Indicates that a new obi data req arrives after an exception is triggered. + // Used to verify exception timing with multiop instruction + logic req_after_exception; + logic [CORE_PARAM_DBG_NUM_TRIGGERS:0] trigger_match_mem; + logic [CORE_PARAM_DBG_NUM_TRIGGERS:0] trigger_match_execute; + logic [CORE_PARAM_DBG_NUM_TRIGGERS:0] trigger_match_exception; + logic [CORE_PARAM_DBG_NUM_TRIGGERS:0] is_trigger_match; + + + // support logic signals for the obi bus protocol: + + // continued address and respons phase indicators, indicates address and respons phases + // of more than one cycle + logic data_bus_addr_ph_cont; + logic data_bus_resp_ph_cont; + + logic instr_bus_addr_ph_cont; + logic instr_bus_resp_ph_cont; + + logic abiim_bus_addr_ph_cont; + logic alignment_buff_resp_ph_cont; + + logic lml_bus_addr_ph_cont; + logic lsu_resp_ph_cont; + + logic lrfodi_bus_addr_ph_cont; + logic lrfodi_bus_resp_ph_cont; + + // address phase counter, used to verify no response phase preceedes an address phase + integer data_bus_v_addr_ph_cnt; + integer instr_bus_v_addr_ph_cnt; + integer alignment_buff_addr_ph_cnt; + integer lsu_addr_ph_cnt; + //integer lrfodi_bus_v_addr_ph_cnt; TODO: remove? + + // Counter for ack'ed irqs + logic [31:0] cnt_irq_ack; + logic [31:0] cnt_rvfi_irqs; + + //Signals stating whether the request for the current response had the attribute value or not + logic instr_req_had_integrity; + logic data_req_had_integrity; + logic gntpar_error_in_response_instr; + logic gntpar_error_in_response_data; + + // indicates that the current rvfi_valid instruction is the first in a debug handler + logic first_debug_ins; + + // this signal indicates core startup + logic first_fetch; + + // signal indicates that a debug_req has been observed whithin + // a timeframe where the core could oboserve it + logic recorded_dbg_req; + + modport master_mp ( + output asm_if, + asm_id, + asm_ex, + asm_wb, + asm_rvfi, + + req_after_exception, + trigger_match_mem, + trigger_match_execute, + trigger_match_exception, + is_trigger_match, + + data_bus_addr_ph_cont, + data_bus_resp_ph_cont, + data_bus_v_addr_ph_cnt, + + instr_bus_addr_ph_cont, + instr_bus_resp_ph_cont, + instr_bus_v_addr_ph_cnt, + + abiim_bus_addr_ph_cont, + alignment_buff_resp_ph_cont, + alignment_buff_addr_ph_cnt, + + lml_bus_addr_ph_cont, + lsu_resp_ph_cont, + lsu_addr_ph_cnt, + + lrfodi_bus_addr_ph_cont, + lrfodi_bus_resp_ph_cont, + //lrfodi_bus_v_addr_ph_cnt, TODO: remove? + + cnt_irq_ack, + cnt_rvfi_irqs, + + obi_data_packet, + obi_instr_packet, + instr_req_had_integrity, + data_req_had_integrity, + gntpar_error_in_response_instr, + gntpar_error_in_response_data, + first_debug_ins, + first_fetch, + recorded_dbg_req + ); + + modport slave_mp ( + input asm_if, + asm_id, + asm_ex, + asm_wb, + asm_rvfi, + + req_after_exception, + trigger_match_mem, + trigger_match_execute, + trigger_match_exception, + is_trigger_match, + + data_bus_addr_ph_cont, + data_bus_resp_ph_cont, + data_bus_v_addr_ph_cnt, + + instr_bus_addr_ph_cont, + instr_bus_resp_ph_cont, + instr_bus_v_addr_ph_cnt, + + abiim_bus_addr_ph_cont, + alignment_buff_resp_ph_cont, + alignment_buff_addr_ph_cnt, + + lml_bus_addr_ph_cont, + lsu_resp_ph_cont, + lsu_addr_ph_cnt, + + lrfodi_bus_addr_ph_cont, + lrfodi_bus_resp_ph_cont, + + cnt_irq_ack, + cnt_rvfi_irqs, + + obi_data_packet, + obi_instr_packet, + instr_req_had_integrity, + data_req_had_integrity, + gntpar_error_in_response_instr, + gntpar_error_in_response_data, + first_debug_ins, + first_fetch, + recorded_dbg_req + ); + +endinterface : uvmt_cv32e40s_support_logic_module_o_if_t + + `endif // __UVMT_CV32E40S_TB_IFS_SV__ diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tdefs.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tdefs.sv index c073676d1b..da97d6d1a3 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tdefs.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tdefs.sv @@ -19,17 +19,4 @@ `ifndef __UVMT_CV32E40S_TDEFS_SV__ `define __UVMT_CV32E40S_TDEFS_SV__ - -/** - * Test Program Type. See the Verification Strategy for a discussion of this. - */ -typedef enum { - PREEXISTING_SELFCHECKING, - PREEXISTING_NOTSELFCHECKING, - GENERATED_SELFCHECKING, - GENERATED_NOTSELFCHECKING, - NO_TEST_PROGRAM - } test_program_type; - - `endif // __UVMT_CV32E40S_TDEFS_SV__ diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv new file mode 100644 index 0000000000..a54213844a --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv @@ -0,0 +1,1401 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_triggers_assert_cov + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import cv32e40s_rvfi_pkg::*; + import uvmt_cv32e40s_pkg::*; + ( + input logic [31:0] tdata1_array[CORE_PARAM_DBG_NUM_TRIGGERS+1], + input privlvl_t priv_lvl, + + uvma_rvfi_instr_if_t rvfi_if, + uvma_clknrst_if_t clknrst_if, + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if, + + uvma_rvfi_csr_if_t tdata1_if, + uvma_rvfi_csr_if_t tdata2_if, + uvma_rvfi_csr_if_t tinfo_if, + uvma_rvfi_csr_if_t tselect_if, + uvma_rvfi_csr_if_t dcsr_if, + uvma_rvfi_csr_if_t dpc_if + ); + + default clocking @(posedge clknrst_if.clk); endclocking + default disable iff !(clknrst_if.reset_n); + + string info_tag = "TRIGGER ASSERT: "; + + /////////// Local Parameters /////////// + + //tinfo: + localparam VERSION_MSB = 31; + localparam VERSION_LSB = 24; + localparam INFO_MSB = 15; + localparam INFO_LSB = 0; + + //common tdata1 values: + localparam LSB_TYPE = 28; + localparam MSB_TYPE = 31; + localparam DMODE = 27; + + //common tdata1 mcontrol and mcontrol6 values: + localparam LOAD = 0; + localparam STORE = 1; + localparam EXECUTE = 2; + localparam M2_M6_S_MODE = 4; + localparam LSB_MATCH = 7; + localparam MSB_MATCH = 10; + localparam CHAIN = 11; + localparam LSB_ACTION = 12; + localparam MSB_ACTION = 15; + + //tdata1 mcontrol: + localparam MSB_MASKMAX = 26; + localparam LSB_MASKMAX = 21; + localparam M2_HIT = 20; + localparam M2_SELECT = 19; + localparam M2_TIMING = 18; + localparam M2_MSB_SIZELO = 17; + localparam M2_LSB_SIZELO = 16; + + //tdata1 mcontrol6: + localparam M6_UNCERTAIN = 26; + localparam M6_HIT1 = 25; + localparam M6_VS = 24; + localparam M6_VU = 23; + localparam M6_HIT0 = 22; + localparam M6_SELECT = 21; + localparam M6_TIMING = 20; + localparam M6_MSB_SIZE = 19; + localparam M6_LSB_SIZE = 16; + localparam M6_UNCERTAINEN = 5; + + //tdata1 etriggers: + localparam ET_HIT = 26; + localparam ET_VS = 12; + localparam ET_VU = 11; + localparam ET_M_MODE = 9; + localparam ET_S = 7; + localparam ET_U_MODE = 6; + localparam ET_MSB_ACTION = 5; + localparam ET_LSB_ACTION = 0; + + //tdata1 disabled: + localparam DIS_MSB_DATA = 26; + localparam DIS_LSB_DATA = 0; + + //Actions: + localparam ENTER_DBG_ON_MATCH = 1; + + //Trigger match specifications: + localparam MATCH_WHEN_EQUAL = 0; + localparam MATCH_WHEN_GREATER_OR_EQUAL = 2; + localparam MATCH_WHEN_LESSER = 3; + + //Cause of entering debug: + localparam TRIGGER_MATCH = 2; + + //CSR addresses: + localparam ADDR_TSELECT = 12'h7A0; + localparam ADDR_TDATA1 = 12'h7A1; + localparam ADDR_TDATA2 = 12'h7A2; + localparam ADDR_TDATA3 = 12'h7A3; + localparam ADDR_TINFO = 12'h7A4; + localparam ADDR_TCONTROL = 12'h7A5; + localparam ADDR_MCONTEXT = 12'h7A8; + localparam ADDR_MSCONTEXT = 12'h7AA; + localparam ADDR_HCONTEXT = 12'h6A8; + localparam ADDR_SCONTEXT = 12'h5A8; + localparam ADDR_DCSR = 12'h7b0; + localparam ADDR_DPC = 12'h7b1; + + //DCSR: + localparam MSB_CAUSE = 8; + localparam LSB_CAUSE = 6; + + //Initial settings + localparam TDATA1_DISABLED = 32'hF800_0000; + localparam TDATA1_RESET = 32'h2800_1000; + localparam MAX_NUM_TRIGGERS = 5; + localparam MAX_MEM_ACCESS = 13; //Push and pop can do 13 memory access. TODO: XIF, can potentially do more, so for XIF assertion a_dt_max_memory_transaction might fail. + localparam MAX_MEM_ACCESS_PLUS_ONE = 53'b1_0000__0000_0000_0000_0000__0000_0000_0000_0000__0000_0000_0000_0000; + + + + /////////// Signals /////////// + + logic [31:0] tdata1_pre_state; + logic [31:0] tdata2_pre_state; + logic [31:0] tinfo_pre_state; + logic [31:0] tselect_pre_state; + + logic [31:0] tdata1_post_state; + logic [31:0] tdata2_post_state; + logic [31:0] tinfo_post_state; + logic [31:0] tselect_post_state; + + always_comb begin + tdata1_pre_state = tdata1_if.pre_state(); + tdata2_pre_state = tdata2_if.pre_state(); + tinfo_pre_state = tinfo_if.pre_state(); + tselect_pre_state = tselect_if.pre_state(); + end + + always_comb begin + tdata1_post_state = tdata1_if.post_state(); + tdata2_post_state = tdata2_if.post_state(); + tinfo_post_state = tinfo_if.post_state(); + tselect_post_state = tselect_if.post_state(); + end + + + logic valid_instr_in_mmode; + assign valid_instr_in_mmode = rvfi_if.rvfi_valid + && !rvfi_if.rvfi_trap + && !rvfi_if.rvfi_dbg_mode + && rvfi_if.is_mmode; + + logic valid_instr_in_umode; + assign valid_instr_in_umode = rvfi_if.rvfi_valid + && !rvfi_if.rvfi_dbg_mode + && rvfi_if.is_umode; + + logic valid_instr_in_dmode; + assign valid_instr_in_dmode = rvfi_if.rvfi_valid + && !rvfi_if.rvfi_trap + && rvfi_if.rvfi_dbg_mode; + + + logic is_csrrw; + logic is_csrrs; + logic is_csrrc; + logic is_csrrwi; + logic is_csrrsi; + logic is_csrrci; + logic [4:0] csri_uimm; + + always_comb begin + is_csrrw = rvfi_if.match_instr_isb(rvfi_if.INSTR_OPCODE_CSRRW); + is_csrrs = rvfi_if.match_instr_isb(rvfi_if.INSTR_OPCODE_CSRRS); + is_csrrc = rvfi_if.match_instr_isb(rvfi_if.INSTR_OPCODE_CSRRC); + is_csrrwi = rvfi_if.match_instr_isb(rvfi_if.INSTR_OPCODE_CSRRWI); + is_csrrsi = rvfi_if.match_instr_isb(rvfi_if.INSTR_OPCODE_CSRRSI); + is_csrrci = rvfi_if.match_instr_isb(rvfi_if.INSTR_OPCODE_CSRRCI); + csri_uimm = rvfi_if.rvfi_insn[19:15]; + end + + + /////////// Sequences /////////// + + sequence seq_csr_read_mmode(csr_addr); + valid_instr_in_mmode + && rvfi_if.is_csr_read(csr_addr) + && rvfi_if.rvfi_rd1_addr != 0; + endsequence + + sequence seq_csr_write_mmode(csr_addr); + valid_instr_in_mmode + && rvfi_if.is_csr_write(csr_addr); + endsequence + + sequence seq_csr_read_dmode(csr_addr); + valid_instr_in_dmode + && rvfi_if.is_csr_read(csr_addr) + && rvfi_if.rvfi_rd1_addr != 0; + endsequence + + sequence seq_csr_write_dmode(csr_addr); + valid_instr_in_dmode + && rvfi_if.is_csr_write(csr_addr); + endsequence + + sequence seq_tdata1_m2_m6_or_disabled(t); + valid_instr_in_dmode + && tselect_pre_state == t + && (tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL + || tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6 + || tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_DISABLED); + endsequence + + sequence seq_etrigger_hit(t, priv_lvl, exception); + support_if.trigger_match_exception[t] + && !rvfi_if.rvfi_dbg_mode + && priv_lvl + && rvfi_if.rvfi_trap.exception_cause == exception; + endsequence + + + /////////// Properties /////////// + + property p_dt_tcsr_not_implemented(tcsr); + rvfi_if.is_csr_instr(tcsr) //make sure no bus fault exceptions has occured + |-> + (rvfi_if.rvfi_trap.trap + && rvfi_if.rvfi_trap.exception + && (rvfi_if.rvfi_trap.exception_cause == EXC_CAUSE_ILLEGAL_INSN)) + + // Trigger match on PC is registered before exceptions is registered + || (rvfi_if.rvfi_trap.debug + && rvfi_if.rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER); + endproperty + + property p_etrigger_hit(t, priv_lvl, exception); + seq_etrigger_hit(t,priv_lvl, exception) + |-> + rvfi_if.rvfi_trap.debug; + endproperty + + property p_trigger_type(tselect_value, tdata1_type); + tselect_pre_state == tselect_value + && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == tdata1_type; + endproperty + + property p_csrrw_in_dmode(addr, csr_post_state); + seq_csr_write_dmode(addr) + ##0 is_csrrw + |-> + csr_post_state == rvfi_if.rvfi_rs1_rdata; + endproperty + + property p_csrrs_in_dmode(addr, csr_post_state); + seq_csr_write_dmode(addr) + ##0 is_csrrs + |-> + csr_post_state == (tdata2_pre_state | rvfi_if.rvfi_rs1_rdata); + endproperty + + property p_csrrc_in_dmode(addr, csr_post_state); + seq_csr_write_dmode(addr) + ##0 is_csrrc + |-> + csr_post_state == (tdata2_pre_state & (~rvfi_if.rvfi_rs1_rdata)); + endproperty + + property p_csrrwi_in_dmode(addr, csr_post_state); + seq_csr_write_dmode(addr) + ##0 is_csrrwi + |-> + csr_post_state == csri_uimm; + endproperty + + property p_csrrsi_in_dmode(addr, csr_post_state); + seq_csr_write_dmode(addr) + ##0 is_csrrsi + |-> + csr_post_state == (tdata2_pre_state | csri_uimm); + endproperty + + property p_csrrci_in_dmode(addr, csr_post_state); + seq_csr_write_dmode(addr) + ##0 is_csrrci + |-> + csr_post_state == (tdata2_pre_state & (~csri_uimm)); + endproperty + + + /////////// Assertions and Coverages /////////// + + //Verify that it isonly possible to do 13 Memory transactions: + //TODO XIF: this might not be the case for xif, as it can potentionally do more: + + a_dt_max_memory_transaction: assert property ( + rvfi_if.rvfi_valid + |-> + rvfi_if.rvfi_mem_rmask < MAX_MEM_ACCESS_PLUS_ONE + && rvfi_if.rvfi_mem_wmask < MAX_MEM_ACCESS_PLUS_ONE + ); + + //- Vplan: + //Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored. + + //Enter debug mode by any of the above methods. + //Write (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2] + //Exit debug mode (dret instruction) + //Verify that core enters debug mode on breakpoint addr + //Current PC is saved to DPC + //Cause of debug must be saved to DCSR (cause=2) + //PC is updated to value on dm_haltaddr_i input + //Core starts executing debug code + + //- Assertion verification: + //1) Verify that core enters debug mode on breakpoint addr + //2) Current PC is saved to DPC + //3) Cause of debug must be saved to DCSR (cause=2) + //4) PC is updated to value on dm_haltaddr_i input + //5) Core starts executing debug code + + //1) see a_dt_instr_trigger_hit_* + //2) - 5): Debug assertions uvmt_cv32e40s_debug_assert.sv + + + //- Vplan: + //Check that attempts to access "tcontrol" raise an illegal instruction exception, always. (Unless overruled by a higher priority.) + + //- Assertion verification: + //1) Check that attempts to access "tcontrol" raise an illegal instruction exception, always. (Unless overruled by a higher priority.) + + //1) + a_dt_tcontrol_not_implemented: assert property ( + p_dt_tcsr_not_implemented(ADDR_TCONTROL) + ) else `uvm_error(info_tag, "Access to tcontrol does not cause an illegal exception (when no higher priority exception has occured)\n"); + + + //- Vplan: + //Check that attempts to access "tdata3" raise an illegal instruction exception, always. (Unless overruled by a higher priority.) + + //- Assertion verification: + //1) Check that attempts to access "tdata3" raise an illegal instruction exception, always. (Unless overruled by a higher priorit + + //1) + a_dt_tdata3_not_implemented: assert property ( + p_dt_tcsr_not_implemented(ADDR_TDATA3) + ) else `uvm_error(info_tag, "Access to tdata3 does not cause an illegal exception (when no higher priority exception has occured)\n"); + + //- Vplan: + //Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. + //Check that no triggers ever fire. Check that "tselect" is 0. + + //- Assertion verification: + //1) Have 0 triggers, access any trigger register and check that illegal instruction exception occurs + //2) Have 0 triggers, No trigger ever fires + + if (CORE_PARAM_DBG_NUM_TRIGGERS == 0) begin + + //1) + a_dt_0_triggers_tdata1_access: assert property ( + (rvfi_if.is_csr_instr(ADDR_TSELECT) + || rvfi_if.is_csr_instr(ADDR_TDATA1) + || rvfi_if.is_csr_instr(ADDR_TDATA2) + || rvfi_if.is_csr_instr(ADDR_TINFO)) + + |-> + rvfi_if.rvfi_trap.trap + && rvfi_if.rvfi_trap.exception + && (rvfi_if.rvfi_trap.exception_cause == EXC_CAUSE_ILLEGAL_INSN) + + ) else `uvm_error(info_tag, "There are no triggers, but accessing trigger SCRs does not cause exceptions.\n"); + + //2) + a_dt_0_triggers_no_triggering: assert property ( + rvfi_if.rvfi_valid + |-> + rvfi_if.rvfi_dbg != TRIGGER_MATCH + + ) else `uvm_error(info_tag, "There are no triggers, but debug cause indicate a trigger match.\n"); + + end // if CORE_PARAM_DBG_NUM_TRIGGERS == 0 + + + //- Vplan: + //For all number of triggers, use tselect to exercise each trigger with each supported type. + //(Also try writing to higher "tselect" than supported and check that a supported number is read back.) + //Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed. + + //- Assertion verification: + //1) Check also that the four context registers trap when accessed. + //2) For all number of triggers, use tselect to exercise each trigger with each supported type + //3) Make the triggers fire and check that debug mode is entered. + //4) Writing to higher "tselect" than supported, check that a supported number is read back + + + //1) + a_dt_access_context: assert property ( + (rvfi_if.is_csr_instr(ADDR_MCONTEXT) + || rvfi_if.is_csr_instr(ADDR_MSCONTEXT) + || rvfi_if.is_csr_instr(ADDR_HCONTEXT) + || rvfi_if.is_csr_instr(ADDR_SCONTEXT)) + + |-> + rvfi_if.rvfi_trap.trap + ) else `uvm_error(info_tag, "Accessing context registers does not trap.\n"); + + + // Assertions and coverages for when debug triggers are enabled: + + if (CORE_PARAM_DBG_NUM_TRIGGERS > 0) begin + + //2) + for (genvar i = 0; i < CORE_PARAM_DBG_NUM_TRIGGERS; i++) begin + + c_dt_trigger_i_has_type_mcontrol: cover property( + p_trigger_type(i, TTYPE_MCONTROL) + ); + + c_dt_trigger_i_has_type_etrigger: cover property( + p_trigger_type(i, TTYPE_ETRIGGER) + ); + + c_dt_trigger_i_has_type_mcontrol6: cover property( + p_trigger_type(i, TTYPE_MCONTROL6) + ); + + c_dt_trigger_i_has_type_disable: cover property( + p_trigger_type(i, TTYPE_DISABLED) + ); + + end + + //3) see a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason + + //4) + a_dt_tselect_higher_than_dbg_num_triggers: assert property( + rvfi_if.is_csr_instr(ADDR_TSELECT) + |-> + rvfi_if.rvfi_rd1_wdata < CORE_PARAM_DBG_NUM_TRIGGERS + ) else `uvm_error(info_tag, "The CSR tselect is set to equal or higher than the number of trigger.\n"); + + + // Make sure the tdata1 array corresponds with the tdata1 csr. + a_dt_tdata1_array: assert property( + rvfi_if.rvfi_valid + |-> + tdata1_array[tselect_post_state[$clog2(CORE_PARAM_DBG_NUM_TRIGGERS+1)-1:0]] == tdata1_post_state + ) else `uvm_error(info_tag, "Verify that the tdata1 array is correct by compearing it with the tdata1 post state signal.\n"); + + + //- Vplan: + //Configure triggers for load/store/execute and combinations of them, configure tdata2, + //cause triggers to fire and check that debug mode is entered correctly. + //Also check that the tied fields are tied. All of these configurations must be crossed, also against match conditions. + + //- Assertion verification: + //1) trigger on loads if the load setting in tdata1 is set high + //2) trigger on stores if the store setting in tdata1 is set high + //3) trigger on instructions if the execute setting in tdata1 is set high + //4) check that the tied fields are tied + + //1) - 3) see a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_* + + //4) + a_dt_tie_offs_tselect: assert property ( + rvfi_if.rvfi_valid + + |-> + !tselect_pre_state[31:CORE_PARAM_DBG_NUM_TRIGGERS-1] + ) else `uvm_error(info_tag, "There is a problem with tselect's tied off fields.\n"); + + + //mcontrol + a_dt_tie_offs_tdata1_mcontrol: assert property ( + rvfi_if.rvfi_valid + && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL + + |-> + tdata1_pre_state[DMODE] + && !tdata1_pre_state[MSB_MASKMAX:LSB_MASKMAX] + && !tdata1_pre_state[M2_HIT] + && !tdata1_pre_state[M2_SELECT] + && !tdata1_pre_state[M2_TIMING] + && !tdata1_pre_state[M2_MSB_SIZELO:M2_LSB_SIZELO] + && tdata1_pre_state[MSB_ACTION:LSB_ACTION] == ENTER_DBG_ON_MATCH + && !tdata1_pre_state[CHAIN] + && !tdata1_pre_state[5] + && !tdata1_pre_state[M2_M6_S_MODE] + ) else `uvm_error(info_tag, "There is a problem with tdata1-mcontrol's tied off fields.\n"); + + //etrigger + a_dt_tie_offs_tdata1_etrigger: assert property ( + rvfi_if.rvfi_valid + && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_ETRIGGER + + |-> + tdata1_pre_state[DMODE] + && !tdata1_pre_state[ET_HIT] + && !tdata1_pre_state[25:13] + && !tdata1_pre_state[ET_VS] + && !tdata1_pre_state[ET_VU] + && !tdata1_pre_state[10] + && !tdata1_pre_state[8] + && !tdata1_pre_state[ET_S] + && tdata1_pre_state[ET_MSB_ACTION:ET_LSB_ACTION] == ENTER_DBG_ON_MATCH + ) else `uvm_error(info_tag, "There is a problem with tdata1-etrigger's tied off fields.\n"); + + //mcontrol6 + a_dt_tie_offs_tdata1_mcontrol6: assert property ( + rvfi_if.rvfi_valid + && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6 + + |-> + tdata1_pre_state[DMODE] + && !tdata1_pre_state[M6_UNCERTAIN] + && !tdata1_pre_state[M6_VS] + && !tdata1_pre_state[M6_VU] + && !tdata1_pre_state[M6_SELECT] + && !tdata1_pre_state[20:19] + && !tdata1_pre_state[M6_MSB_SIZE:M6_LSB_SIZE] + && tdata1_pre_state[MSB_ACTION:LSB_ACTION] == ENTER_DBG_ON_MATCH + && !tdata1_pre_state[CHAIN] + && !tdata1_pre_state[M6_UNCERTAINEN] + && !tdata1_pre_state[M2_M6_S_MODE] + ) else `uvm_error(info_tag, "There is a problem with tdata1-mcontrol6's tied off fields.\n"); + + //disabled + a_dt_tie_offs_tdata1_disabled: assert property ( + rvfi_if.rvfi_valid + && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_DISABLED + + |-> + tdata1_pre_state[DMODE] + && !tdata1_pre_state[DIS_MSB_DATA:DIS_LSB_DATA] + ) else `uvm_error(info_tag, "There is a problem with tdata1-disabled's tied off fields.\n"); + + + a_dt_tie_offs_tdata2_etrigger: assert property ( + rvfi_if.rvfi_valid + && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_ETRIGGER + + |-> + !tdata2_pre_state[31:26] + && !tdata2_pre_state[23:12] + && !tdata2_pre_state[10:9] + && !tdata2_pre_state[6] + && !tdata2_pre_state[4] + && !tdata2_pre_state[0] + ) else `uvm_error(info_tag, "There is a problem with tdata2-etrigger's tied off fields.\n"); + + + a_dt_tie_offs_tinfo: assert property ( + rvfi_if.rvfi_valid + |-> + tinfo_pre_state[VERSION_MSB:VERSION_LSB] == 1 + && !tinfo_pre_state[23:16] + && tinfo_pre_state[INFO_MSB:INFO_LSB] == 16'h8064 + ) else `uvm_error(info_tag, "There is a problem with tinfo's tied off fields.\n"); + + + //- Vplan: + //Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values. + + //- Assertion verification: + //1) but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly, using different match configurations. + //2) Also check the tied values. (P20-P21: 4)) + + + //1) see a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason + //2) see a_dt_tie_offs_* + + + //- Vplan: + //Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is "15". + + //- Assertion verification: + //1) Sjekk at tdata1 type kun kan være 2, 6, 5 eller 15 + + + //1) + a_dt_tdata1_types: assert property ( + rvfi_if.rvfi_valid + |-> + tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL + || tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_ETRIGGER + || tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6 + || tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_DISABLED + ) else `uvm_error(info_tag, "tdata1 type is neither mcontrol, etrigger, mcontrol6 or disabled.\n"); + + + //- Vplan: + //Try to write tdata registers outside of debug mode, check that they are not writable. Try changing "tdata1.dmode" and check that it is WARL (0x1). Cross the above checks with all supported types. + + //- Assertion verification: + //1) write tdata registers outside of debug mode, check that they are not writable + //2) Try changing "tdata1.dmode" and check that it is WARL (0x1) + + + //1) + a_dt_not_access_tdata1_dbg_mode: assert property ( + !rvfi_if.rvfi_dbg_mode + && rvfi_if.is_csr_instr(ADDR_TDATA1) + |-> + !tdata1_if.rvfi_csr_wmask + //or m6 hit bits are set due to trigger match + || (rvfi_if.rvfi_trap.debug + && rvfi_if.rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER + && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6) + ) else `uvm_error(info_tag, "Writing tdata1 in non-debug mode succeeds.\n"); + + + a_dt_not_access_tdata2_dbg_mode: assert property ( + !rvfi_if.rvfi_dbg_mode + && rvfi_if.is_csr_instr(ADDR_TDATA2) + + |-> + !tdata2_if.rvfi_csr_wmask + ) else `uvm_error(info_tag, "Writing tdata2 in non-debug mode succeeds.\n"); + + + //2) + a_dt_dmode: assert property ( + seq_csr_write_dmode(ADDR_TDATA1) + ##0 !rvfi_if.rvfi_trap.trap + |-> + tdata1_post_state[DMODE] + ) else `uvm_error(info_tag, "Setting tdata1's dmode bit to 0 succeeds.\n"); + + + //- Vplan: + //When num triggers is more than 0, check that "tinfo.info" is "1" for the three supported types, "tinfo.version" is 0x1, and that the remaining bits are 0. + + //- Assertion verification: + //1) When num triggers is more than 0, check that "tinfo.info" is "1" for the three supported types, "tinfo.version" is 0x1, and that the remaining bits are 0. + + //1) + a_dt_triggers_tinfo: assert property ( + CORE_PARAM_DBG_NUM_TRIGGERS != '0 + && rvfi_if.rvfi_valid + |-> + !tinfo_pre_state[1:0] + && tinfo_pre_state[TTYPE_MCONTROL] + && !tinfo_pre_state[4:3] + && tinfo_pre_state[TTYPE_ETRIGGER] + && tinfo_pre_state[TTYPE_MCONTROL6] + && !tinfo_pre_state[14:7] + && tinfo_pre_state[TTYPE_DISABLED] + && tinfo_pre_state[VERSION_MSB:VERSION_LSB] == 1 + + ) else `uvm_error(info_tag, "tinfo does not indicated that only tdata type mcontrol, etrigger, mcontrol6 and disabled are allowed.\n"); + + + //- Vplan: + //Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields. + + //- Assertion verification: + //1) Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. + //2) Check the WARL fields + + + //1) see a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason + + //2) + a_dt_warl_tselect: assert property ( + rvfi_if.rvfi_valid + && |tselect_if.rvfi_csr_wmask != 0 + |-> + tselect_post_state < CORE_PARAM_DBG_NUM_TRIGGERS + ) else `uvm_error(info_tag, "There is a problem with tselect's WARL fields.\n"); + + a_dt_warl_tdata1_general: assert property ( + rvfi_if.rvfi_valid + && |tdata1_if.rvfi_csr_wmask != 0 + |-> + (tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL + || tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_ETRIGGER + || tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6 + || tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_DISABLED) + && tdata1_post_state[DMODE] + ) else `uvm_error(info_tag, "There is a problem with tdata1's general WARL fields.\n"); + + a_dt_warl_tdata1_m2: assert property ( + rvfi_if.rvfi_valid + && |tdata1_if.rvfi_csr_wmask != 0 + && tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL + |-> + !tdata1_post_state[MSB_MASKMAX:LSB_MASKMAX] + && !tdata1_post_state[M2_HIT] + && !tdata1_post_state[M2_SELECT] + && !tdata1_post_state[M2_TIMING] + && !tdata1_post_state[M2_MSB_SIZELO:M2_LSB_SIZELO] + && tdata1_post_state[MSB_ACTION:LSB_ACTION] == ENTER_DBG_ON_MATCH + && !tdata1_post_state[CHAIN] + && (tdata1_post_state[MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + || tdata1_post_state[MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + || tdata1_post_state[MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER) + && !tdata1_post_state[5] + && !tdata1_post_state[M2_M6_S_MODE] + ) else `uvm_error(info_tag, "There is a problem with tdata1-mcontrol's WARL fields.\n"); + + a_dt_warl_tdata1_etrigger: assert property ( + rvfi_if.rvfi_valid + && |tdata1_if.rvfi_csr_wmask != 0 + && tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_ETRIGGER + |-> + !tdata1_post_state[ET_HIT] + && !tdata1_post_state[25:13] + && !tdata1_post_state[ET_VS] + && !tdata1_post_state[ET_VU] + && !tdata1_post_state[10] + && !tdata1_post_state[8] + && !tdata1_post_state[ET_S] + && tdata1_post_state[ET_MSB_ACTION:ET_LSB_ACTION] == ENTER_DBG_ON_MATCH + ) else `uvm_error(info_tag, "There is a problem with tdata1-etrigger's WARL fields.\n"); + + a_dt_warl_tdata1_m6: assert property ( + rvfi_if.rvfi_valid + && |tdata1_if.rvfi_csr_wmask != 0 + && tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6 + |-> + tdata1_post_state[DMODE] + && !tdata1_post_state[M6_UNCERTAIN] + && ({tdata1_post_state[M6_HIT1], tdata1_post_state[M6_HIT0]} == 0 + || {tdata1_post_state[M6_HIT1], tdata1_post_state[M6_HIT0]} == 1) + && !tdata1_post_state[M6_VS] + && !tdata1_post_state[M6_VU] + && !tdata1_post_state[M6_SELECT] + && !tdata1_post_state[20:19] + && !tdata1_post_state[M6_MSB_SIZE:M6_LSB_SIZE] + && tdata1_post_state[MSB_ACTION:LSB_ACTION] == ENTER_DBG_ON_MATCH + && !tdata1_post_state[CHAIN] + && (tdata1_post_state[MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + || tdata1_post_state[MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + || tdata1_post_state[MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER) + && !tdata1_post_state[M6_UNCERTAINEN] + && !tdata1_post_state[M2_M6_S_MODE] + ) else `uvm_error(info_tag, "There is a problem with tdata1-mcontrol6's WARL fields.\n"); + + a_dt_warl_tdata1_disabled: assert property ( + rvfi_if.rvfi_valid + && |tdata1_if.rvfi_csr_wmask != 0 + && tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_DISABLED + |-> + !tdata1_post_state[DIS_MSB_DATA:DIS_LSB_DATA] + ) else `uvm_error(info_tag, "There is a problem with tdata1-disabled's WARL fields.\n"); + + a_dt_warl_tdata2_etrigger: assert property ( + rvfi_if.rvfi_valid + && |tdata2_if.rvfi_csr_wmask != 0 + && tdata1_post_state[MSB_TYPE:LSB_TYPE] == TTYPE_ETRIGGER + |-> + !tdata2_post_state[31:26] + && !tdata2_post_state[23:12] + && !tdata2_post_state[10:9] + && !tdata2_post_state[6] + && !tdata2_post_state[4] + && !tdata2_post_state[0] + ) else `uvm_error(info_tag, "There is a problem with tdata1-etrigger's WARL fields.\n"); + + a_dt_warl_tinfo: assert property ( + rvfi_if.rvfi_valid + && |tinfo_if.rvfi_csr_wmask != 0 + |-> + !tinfo_post_state[23:16] + ) else `uvm_error(info_tag, "There is a problem with tinfo's WARL fields.\n"); + + + //- Vplan: + //Access all tdata registers in M-mode and observe writes have no effects and reads should reflect register content. + //Access registers from D-mode and observe full R/W access. + //Access from U-mode and observe no access at all. + + // - Assertion verification: + //1) Verify that all tdata registers can be read in machine mode, but that writes do not have any effect + //2) Verify that all tdata registers can be read in debug mode, and that writes have an effect + //3) Verify that the tdata registers are unaccessible in user mode + + //1) + a_dt_no_write_access_to_tdata_in_mmode: assert property ( + + valid_instr_in_mmode + && !rvfi_if.rvfi_dbg_mode + |-> + (!tdata1_if.rvfi_csr_wmask + && !tdata2_if.rvfi_csr_wmask) + + // A write to tselect will make the core display new tdata values, and consequently write the tdata csrs. + || rvfi_if.is_csr_write(ADDR_TSELECT) + + ) else `uvm_error(info_tag, "The t-CSRs are written in machine mode (not debug mode), and the write changes the CSRs values.\n"); + + c_dt_write_tdata1_in_mmode: cover property ( + seq_csr_write_mmode(ADDR_TDATA1) + ); + + c_dt_write_tdata2_in_mmode: cover property ( + seq_csr_write_mmode(ADDR_TDATA2) + ); + + a_dt_read_access_to_tdata1_in_mmode: assert property ( + seq_csr_read_mmode(ADDR_TDATA1) + |-> + rvfi_if.rvfi_rd1_wdata == tdata1_pre_state + ) else `uvm_error(info_tag, "No read access to tdata1 in machine mode.\n"); + + a_dt_read_access_to_tdata2_in_mmode: assert property ( + seq_csr_read_mmode(ADDR_TDATA2) + |-> + rvfi_if.rvfi_rd1_wdata == tdata2_pre_state + ) else `uvm_error(info_tag, "No read access to tdata2 in machine mode.\n"); + + + //2) + a_dt_write_access_to_tdata1_in_dmode: assert property ( + p_csrrw_in_dmode(ADDR_TDATA1, tdata1_post_state) + or p_csrrs_in_dmode(ADDR_TDATA1, tdata1_post_state) + or p_csrrc_in_dmode(ADDR_TDATA1, tdata1_post_state) + or p_csrrwi_in_dmode(ADDR_TDATA1, tdata1_post_state) + or p_csrrsi_in_dmode(ADDR_TDATA1, tdata1_post_state) + or p_csrrci_in_dmode(ADDR_TDATA1, tdata1_post_state) + ) else `uvm_error(info_tag, "No write access to tdata1 in debug mode.\n"); + + a_dt_write_access_to_tdata2_in_dmode: assert property ( + p_csrrw_in_dmode(ADDR_TDATA2, tdata2_post_state) + or p_csrrs_in_dmode(ADDR_TDATA2, tdata2_post_state) + or p_csrrc_in_dmode(ADDR_TDATA2, tdata2_post_state) + or p_csrrwi_in_dmode(ADDR_TDATA2, tdata2_post_state) + or p_csrrsi_in_dmode(ADDR_TDATA2, tdata2_post_state) + or p_csrrci_in_dmode(ADDR_TDATA2, tdata2_post_state) + ) else `uvm_error(info_tag, "No write access to tdata2 in debug mode.\n"); + + + a_dt_read_access_to_tdata1_in_dmode: assert property ( + seq_csr_read_dmode(ADDR_TDATA1) + |-> + rvfi_if.rvfi_rd1_wdata == tdata1_pre_state + ) else `uvm_error(info_tag, "No read access to tdata1 in debug mode.\n"); + + a_dt_read_access_to_tdata2_in_dmode: assert property ( + seq_csr_read_dmode(ADDR_TDATA2) + |-> + rvfi_if.rvfi_rd1_wdata == tdata2_pre_state + ) else `uvm_error(info_tag, "No read access to tdata2 in debug mode.\n"); + + + //3) + a_dt_no_access_to_tdata_in_umode: assert property ( + + valid_instr_in_umode + + && (rvfi_if.is_csr_instr(ADDR_TDATA1) + || rvfi_if.is_csr_instr(ADDR_TDATA2)) + + |-> + rvfi_if.rvfi_trap.trap + ) else `uvm_error(info_tag, "Access to the t-CSRs in user mode.\n"); + + + //- Vplan: + //Write 0 to "tdata1", ensure that its state becomes disabled (type 15). Write values to "tdata2" (addresses and/or exception causes) + //and exercise would-have-been triggers and check that the trigger does not fire. + + //- Assertion verification: + //1) Write 0 to "tdata1", ensure that its state becomes disabled (type 15). + //2) Write values to "tdata2" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire (because tdata1 is in disabled state). + + + //1) + a_dt_write_0_to_tdata1: assert property ( + seq_csr_write_dmode(ADDR_TDATA1) + + ##0 rvfi_if.is_csr_write(ADDR_TDATA1) + + && ((rvfi_if.rvfi_insn[14:12] == 3'b001 //write + && rvfi_if.rvfi_rs1_rdata == '0) + + || (rvfi_if.rvfi_insn[14:12] == 3'b011 //clear + && rvfi_if.rvfi_rs1_rdata == 32'hFFFF_FFFF) + + || (rvfi_if.rvfi_insn[14:12] == 3'b101 //write immediate + && rvfi_if.csri_uimm == '0) + + || (rvfi_if.rvfi_insn[14:12] == 3'b111 //clear immediate + && rvfi_if.csri_uimm == 5'h1F + && tdata1_pre_state[31:6] == '0)) + + |-> + tdata1_post_state == TDATA1_DISABLED + ) else `uvm_error(info_tag, "Writing 0 to tdata1 does not set tdata1 into disabled state.\n"); + + + //2) see a_dt_enter_dbg_reason + + + //- Vplan: + //Read the state of all triggers, write to tdata1/2 (using all types in tdata1), read back the state of all triggers and + //check that nothing got changes except the one "tdata*" register that was written. + + //- Assertion verification: + //1) write to tdata1/2/3 and check that nothing got changes except the one "tdata*" register that was written + + //1) + a_dt_write_only_tdata1: assert property ( + seq_csr_write_dmode(ADDR_TDATA1) + |-> + !tdata2_if.rvfi_csr_wmask + ) else `uvm_error(info_tag, "A write to tdata1 writes tdata2 as well.\n"); + + a_dt_write_only_tdata2: assert property ( + seq_csr_write_dmode(ADDR_TDATA2) + |-> + !tdata1_if.rvfi_csr_wmask + ) else `uvm_error(info_tag, "A write to tdata2 writes tdata1 as well.\n"); + + + //- Vplan: + //Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). + //Continue execution in debug, and observe that no action is taken when the trigger matches. + + //- Assertion verification: + //1) Bring core into debug and observe that no action is taken when there are trigger matches + + + //1) + a_dt_no_actions_on_trigger_matches_in_debug_dcsr: assert property ( + rvfi_if.rvfi_valid + && rvfi_if.rvfi_dbg_mode + && dcsr_if.rvfi_csr_wmask + |-> + rvfi_if.is_csr_write(ADDR_DCSR) + ) else `uvm_error(info_tag, "Action is taken when there is a trigger match while in debug mode (dcsr is changed even though we dont do a dcsr write operation).\n"); + + a_dt_no_actions_on_trigger_matches_in_debug_dpc: assert property ( + rvfi_if.rvfi_valid + && rvfi_if.rvfi_dbg_mode + && dpc_if.rvfi_csr_wmask + |-> + rvfi_if.is_csr_write(ADDR_DPC) + ) else `uvm_error(info_tag, "Action is taken when there is a trigger match while in debug mode (dpc is changed even though we dont do a dpc write operation).\n"); + + + for (genvar t = 0; t < CORE_PARAM_DBG_NUM_TRIGGERS; t++) begin + + //- Vplan: + //Configure "tdata1" and "tdata2" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc). + + //- Assertion verification: + //1) Verify that we enter debug when triggering the enabled exceptions + //2) Verify that we do not enter debug when triggering unenabled exceptions + + //1) + a_dt_exception_trigger_hit_m_instr_access_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_INSTR_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, instruction fault) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_u_instr_access_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_INSTR_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, instruction fault) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_m_illegal_instr: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_ILLEGAL_INSN) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, illegal instruction) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_u_illegal_instr: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_ILLEGAL_INSN) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, illegal instruction) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_m_breakpoint: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_BREAKPOINT) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, breakpoint in machine mode) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_u_breakpoint: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_BREAKPOINT) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, breakpoint in user mode) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_m_load_access_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_LOAD_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, load access fault) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_u_load_access_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_LOAD_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, load access fault) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_m_store_AMO_access_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_STORE_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, stor/AMO access fault) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_u_store_AMO_access_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_STORE_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, stor/AMO access fault) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_m_mecall: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_ECALL_MMODE) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, ecall in machine mode) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_u_uecall: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_ECALL_UMODE) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, ecall in user mode) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_m_instr_bus_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_INSTR_BUS_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, instruction bus fault) does not send the core into debug mode.\n"); + + a_dt_exception_trigger_hit_u_instr_bus_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_INSTR_BUS_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, instruction bus fault) does not send the core into debug mode.\n"); + + if (INTEGRITY_ERRORS_ENABLED) begin + + a_glitch_dt_exception_trigger_hit_m_instr_integrity_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_INSTR_INTEGRITY_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, instruction integrity fault) does not send the core into debug mode.\n"); + + a_glitch_dt_exception_trigger_hit_u_instr_integrity_fault: assert property( + p_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_INSTR_INTEGRITY_FAULT) + ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, instruction integrity fault) does not send the core into debug mode.\n"); + + end else begin + + a_glitch_dt_exception_trigger_hit_m_instr_integrity_fault_noprecondition: assert property( + not seq_etrigger_hit( + t, + rvfi_if.is_mmode, + EXC_CAUSE_INSTR_INTEGRITY_FAULT) + ) else `uvm_error(info_tag, "exception trigger hit precondition is met for machine mode even though we assueme no integrity faults.\n"); + + a_glitch_dt_exception_trigger_hit_u_instr_integrity_fault_noprecondition: assert property( + not seq_etrigger_hit( + t, + rvfi_if.is_umode, + EXC_CAUSE_INSTR_INTEGRITY_FAULT) + ) else `uvm_error(info_tag, "exception trigger hit precondition is met for user mode even though we assueme no integrity faults.\n"); + + end + + //2) see a_dt_enter_dbg_reason + + + //- Assertion verification: + //1) Verify that we enter debug when triggering the enabled instruction, memory address or exception + //2) Verify that we do not enter debug when triggering unenabled instruction, memory address or exception + + //It is possible to formulate an assertions for general verification of instruction triggering, + //However, to reduce convergence time we verify this trigger feature with several more constricted assertions: + + a_dt_instr_trigger_hit_mmode_match_when_equal: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + && support_if.trigger_match_execute[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (instruction match, machine mode, match when equal) does not send the core into debug mode.\n"); + + a_dt_instr_trigger_hit_umode_match_when_equal: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + && support_if.trigger_match_execute[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (instruction match, user mode, match when equal) does not send the core into debug mode.\n"); + + a_dt_instr_trigger_hit_mmode_match_when_equal_or_greater: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + && support_if.trigger_match_execute[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (instruction match, machine mode, match when greater or equal) does not send the core into debug mode.\n"); + + a_dt_instr_trigger_hit_umode_match_when_equal_or_greater: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + && support_if.trigger_match_execute[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (instruction match, user mode, match when greater or equal) does not send the core into debug mode.\n"); + + a_dt_instr_trigger_hit_mmode_match_when_lesser: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER + && support_if.trigger_match_execute[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (instruction match, machine mode, match when lesser) does not send the core into debug mode.\n"); + + a_dt_instr_trigger_hit_umode_match_when_lesser: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER + && support_if.trigger_match_execute[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (instruction match, user mode, match when lesser) does not send the core into debug mode.\n"); + + + for (genvar n = 0; n < MAX_MEM_ACCESS; n++) begin + + a_dt_load_trigger_hit_mmode_match_when_equal: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + && rvfi_if.is_load_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (load match, machine mode, match when equal) does not send the core into debug mode.\n"); + + a_dt_load_trigger_hit_umode_match_when_equal: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + && rvfi_if.is_load_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (load match, user mode, match when equal) does not send the core into debug mode.\n"); + + a_dt_load_trigger_hit_mmode_match_when_equal_or_greater: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + && rvfi_if.is_load_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (load match, machine mode, match when greater or equal) does not send the core into debug mode.\n"); + + a_dt_load_trigger_hit_umode_match_when_equal_or_greater: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + && rvfi_if.is_load_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (load match, user mode, match when greater or equal) does not send the core into debug mode.\n"); + + a_dt_load_trigger_hit_mmode_match_when_lesser: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER + && rvfi_if.is_load_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (load match, machine mode, match when lesser) does not send the core into debug mode.\n"); + + a_dt_load_trigger_hit_umode_match_when_lesser: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER + && rvfi_if.is_load_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (load match, user mode, match when lesser) does not send the core into debug mode.\n"); + + //Store: + a_dt_store_trigger_hit_mmode_match_when_equal: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + && rvfi_if.is_store_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (store match, machine mode, match when equal) does not send the core into debug mode.\n"); + + a_dt_store_trigger_hit_umode_match_when_equal: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_EQUAL + && rvfi_if.is_store_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (store match, user mode, match when equal) does not send the core into debug mode.\n"); + + a_dt_store_trigger_hit_mmode_match_when_equal_or_greater: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + && rvfi_if.is_store_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (store match, machine mode, match when greater or equal) does not send the core into debug mode.\n"); + + a_dt_store_trigger_hit_umode_match_when_equal_or_greater: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_GREATER_OR_EQUAL + && rvfi_if.is_store_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (store match, user mode, match when greater or equal) does not send the core into debug mode.\n"); + + a_dt_store_trigger_hit_mmode_match_when_lesser: assert property ( + rvfi_if.is_mmode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER + && rvfi_if.is_store_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (store match, machine mode, match when lesser) does not send the core into debug mode.\n"); + + a_dt_store_trigger_hit_umode_match_when_lesser: assert property ( + rvfi_if.is_umode + && tdata1_array[t][MSB_MATCH:LSB_MATCH] == MATCH_WHEN_LESSER + && rvfi_if.is_store_instr + && support_if.trigger_match_mem[t] + && !rvfi_if.rvfi_dbg_mode + |-> + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "The trigger match (store match, user mode, match when lesser) does not send the core into debug mode.\n"); + + end + end + + + //2) + a_dt_enter_dbg_reason: assert property ( + rvfi_if.rvfi_valid + && rvfi_if.rvfi_trap.debug + && rvfi_if.rvfi_trap.debug_cause == TRIGGER_MATCH + + |-> + support_if.is_trigger_match + + ) else `uvm_error(info_tag, "We have entered debug mode due to triggers but not due to any of the listed reasons.\n"); + + + //- Vplan: + //Change the type to 2/6/15 and write any data to "tdata2", read it back and check that it always gets set. + + //- Assertion verification: + //1) Change the type to 2/6/15 and write any data to "tdata2", read it back and check that it always gets set. + + + //1) + a_dt_write_tdata2_random_in_dmode_type_2_6_15: assert property ( + + (seq_csr_write_dmode(ADDR_TDATA2) + ##0 (tdata1_pre_state[MSB_TYPE:LSB_TYPE] == 2 + || tdata1_pre_state[MSB_TYPE:LSB_TYPE] == 6 + || tdata1_pre_state[MSB_TYPE:LSB_TYPE] == 15)) + + |-> + (is_csrrw && (tdata2_post_state == rvfi_if.rvfi_rs1_rdata)) + || (is_csrrs && (tdata2_post_state == (tdata2_pre_state | rvfi_if.rvfi_rs1_rdata))) + || (is_csrrc && (tdata2_post_state == (tdata2_pre_state & (~rvfi_if.rvfi_rs1_rdata)))) + || (is_csrrwi && (tdata2_post_state == csri_uimm)) + || (is_csrrsi && (tdata2_post_state == (tdata2_pre_state | csri_uimm))) + || (is_csrrci && (tdata2_post_state == (tdata2_pre_state & (~csri_uimm)))) + + ) else `uvm_error(info_tag, "Random values for tdata2 type 2/6/15 in debug mode, is not accepted.\n"); + + + for (genvar t = 0; t < CORE_PARAM_DBG_NUM_TRIGGERS; t++) begin + + c_dt_w_csrrw_tdata2_m2_m6_disabled: cover property ( + seq_tdata1_m2_m6_or_disabled(t) + ##0 is_csrrw + && rvfi_if.rvfi_insn[31:20] == ADDR_TDATA2 + ); + + c_dt_w_csrrs_tdata2_m2_m6_disabled: cover property ( + seq_tdata1_m2_m6_or_disabled(t) + ##0 is_csrrs + && rvfi_if.rvfi_insn[31:20] == ADDR_TDATA2 + ); + + c_dt_w_csrrc_tdata2_m2_m6_disabled: cover property ( + seq_tdata1_m2_m6_or_disabled(t) + ##0 is_csrrc + && rvfi_if.rvfi_insn[31:20] == ADDR_TDATA2 + ); + + c_dt_w_csrrwi_tdata2_m2_m6_disabled: cover property ( + seq_tdata1_m2_m6_or_disabled(t) + ##0 is_csrrwi + && rvfi_if.rvfi_insn[31:20] == ADDR_TDATA2 + ); + + c_dt_w_csrrsi_tdata2_m2_m6_disabled: cover property ( + seq_tdata1_m2_m6_or_disabled(t) + ##0 is_csrrsi + && rvfi_if.rvfi_insn[31:20] == ADDR_TDATA2 + ); + + c_dt_w_csrrci_tdata2_m2_m6_disabled: cover property ( + seq_tdata1_m2_m6_or_disabled(t) + ##0 is_csrrci + && rvfi_if.rvfi_insn[31:20] == ADDR_TDATA2 + ); + + + //- Vplan: + //Induce firing of a trigger. Check that the corresponding "hit" field gets set. Do the same for variations of multiple triggers firing at once. + //Check that the field is WARL 0x0, 0x1. + + //- Assertion verification: + //1) Induce firing of a trigger. Check that the corresponding "hit" field gets set + //2) Check that the field is WARL 0x0, 0x1 + + //1) + a_dt_m6_hit_bit: assert property( + rvfi_if.rvfi_valid + && !rvfi_if.rvfi_dbg_mode + && tdata1_array[t][MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6 + && support_if.is_trigger_match[t] + |-> + {tdata1_array[t][M6_HIT1], tdata1_array[t][M6_HIT0]} == 2'b01 + ) else `uvm_error(info_tag, "The hit bits is not set even though there is a m6 trigger match.\n"); + + end + + //2) see a_dt_warl_tdata1_m6 + + + end // if CORE_PARAM_DBG_NUM_TRIGGERS > 0 + + +endmodule : uvmt_cv32e40s_triggers_assert_cov diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv new file mode 100644 index 0000000000..d3bb6b73ea --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv @@ -0,0 +1,1024 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`default_nettype none + + +module uvmt_cv32e40s_umode_assert + import cv32e40s_pkg::*; + import cv32e40s_rvfi_pkg::*; + import uvm_pkg::*; +#( + parameter bit CLIC +)( + input wire clk_i, + input wire rst_ni, + + input wire rvfi_valid, + input wire [ 1:0] rvfi_mode, + input wire [63:0] rvfi_order, + input wire rvfi_trap_t rvfi_trap, + input wire rvfi_intr_t rvfi_intr, + input wire [31:0] rvfi_insn, + input wire rvfi_dbg_mode, + input wire [ 2:0] rvfi_dbg, + input wire [31:0] rvfi_pc_rdata, + uvma_rvfi_instr_if_t rvfi_if, + //TODO:INFO:silabs-robin Should only use the interface + + input wire [31:0] rvfi_csr_dcsr_rdata, + input wire [31:0] rvfi_csr_mcause_rdata, + input wire [31:0] rvfi_csr_mcause_wdata, + input wire [31:0] rvfi_csr_mcause_wmask, + input wire [31:0] rvfi_csr_mcounteren_rdata, + input wire [31:0] rvfi_csr_mie_rdata, + input wire [31:0] rvfi_csr_mip_rdata, + input wire [31:0] rvfi_csr_misa_rdata, + input wire [31:0] rvfi_csr_mscratch_rdata, + input wire [31:0] rvfi_csr_mscratch_rmask, + input wire [31:0] rvfi_csr_mscratch_wdata, + input wire [31:0] rvfi_csr_mscratch_wmask, + input wire [31:0] rvfi_csr_mstateen0_rdata, + input wire [31:0] rvfi_csr_mstatus_rdata, + input wire [31:0] rvfi_csr_mstatus_wdata, + input wire [31:0] rvfi_csr_mstatus_wmask, + + input wire mpu_iside_valid, + input wire [31:0] mpu_iside_addr, + + input wire [ 2:0] obi_iside_prot, + input wire [ 2:0] obi_dside_prot +); + + default clocking @(posedge clk_i); endclocking + default disable iff !rst_ni; + + string info_tag = "CV32E40S_UMODE_ASSERT"; + + localparam int MISA_U_POS = 20; + localparam int MISA_S_POS = 18; + localparam int MISA_N_POS = 13; + + localparam int MPP_POS = 11; + localparam int MPP_LEN = 2; + localparam int SPP_POS = 8; + localparam int SPP_LEN = 1; + localparam int MPRV_POS = 17; + localparam int MPRV_LEN = 1; + localparam int TW_POS = 21; + localparam int TW_LEN = 1; + localparam int EBREAKU_POS = 12; + localparam int EBREAKU_LEN = 1; + localparam int PRV_POS = 0; + localparam int PRV_LEN = 2; + localparam int XS_POS = 15; + localparam int XS_LEN = 2; + localparam int FS_POS = 13; + localparam int FS_LEN = 2; + localparam int SD_POS = 31; + localparam int SD_LEN = 1; + localparam int CY_POS = 0; + localparam int CY_LEN = 1; + localparam int IR_POS = 2; + localparam int MPRVEN_POS = 4; + localparam int MPRVEN_LEN = 1; + + localparam int MODE_U = 2'b 00; + localparam int MODE_M = 2'b 11; + + localparam int MRET_IDATA = 32'b 0011000_00010_00000_000_00000_1110011; + localparam int DRET_IDATA = 32'h 7b200073; + localparam int WFI_IDATA = 32'b 0001000_00101_00000_000_00000_1110011; + localparam int WFE_IDATA = 32'h 8C00_0073; + localparam int CUSTOM0_IDATA = 32'b 100011_00000000000_000_00000_1110011; + localparam int CUSTOM0_IMASK = 32'b 111111_00000000000_111_00000_1111111; + localparam int CUSTOM1_IDATA = 32'b 110011_00000000000_000_00000_1110011; + localparam int CUSTOM1_IMASK = 32'b 111111_00000000000_111_00000_1111111; + localparam int URET_IDATA = 32'b 0000000_00010_00000_000_00000_1110011; + localparam int EBREAK_IDATA = 32'b 000000000001_00000_000_00000_1110011; + localparam int ECALL_IDATA = 32'b 000000000000_00000_000_00000_1110011; + + localparam int CSRADDR_USTATUS = 12'h 000; + localparam int CSRADDR_UIE = 12'h 004; + localparam int CSRADDR_UTVEC = 12'h 005; + localparam int CSRADDR_JVT = 12'h 017; + localparam int CSRADDR_USCRATCH = 12'h 040; + localparam int CSRADDR_UEPC = 12'h 041; + localparam int CSRADDR_UCAUSE = 12'h 042; + localparam int CSRADDR_UTVAL = 12'h 043; + localparam int CSRADDR_UIP = 12'h 044; + localparam int CSRADDR_CYCLE = 12'h C00; + localparam int CSRADDR_HPM0 = 12'h C00; + localparam int CSRADDR_MEDELEG = 12'h 302; + localparam int CSRADDR_MIDELEG = 12'h 303; + localparam int CSRADDR_MCOUNTEREN = 12'h 306; + + wire [31:0] mstatus_writestate = (rvfi_csr_mstatus_wdata & rvfi_csr_mstatus_wmask); + wire [31:0] mstatus_legacystate = (rvfi_csr_mstatus_rdata & ~rvfi_csr_mstatus_wmask); + wire [31:0] mstatus_poststate = (mstatus_writestate | mstatus_legacystate); + wire [31:0] mcause_writestate = (rvfi_csr_mcause_wdata & rvfi_csr_mcause_wmask); + wire [31:0] mcause_legacystate = (rvfi_csr_mcause_rdata & ~rvfi_csr_mcause_wmask); + wire [31:0] mcause_poststate = (mcause_writestate | mcause_legacystate); + wire is_rvfi_instrrevoked = ( + rvfi_trap.exception && + (rvfi_trap.exception_cause inside {EXC_CAUSE_INSTR_FAULT, EXC_CAUSE_INSTR_BUS_FAULT}) + ); + wire is_rvfi_instrtriggered = ( + rvfi_trap[0] && + rvfi_trap.debug && + (rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER) + ); + wire is_rvfi_illegalinsn = ( + rvfi_trap[0] && + rvfi_trap.exception && + (rvfi_trap.exception_cause == EXC_CAUSE_ILLEGAL_INSN) + ); + wire is_rvfi_valid_norevoke_notrigger = ( + rvfi_valid && + !is_rvfi_instrrevoked && + !is_rvfi_instrtriggered + ); + wire is_rvfi_mret = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn == MRET_IDATA) + ); + wire is_rvfi_dret = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn == DRET_IDATA) + ); + wire is_rvfi_wfi = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn == WFI_IDATA) + ); + wire is_rvfi_customumodeinstr = ( + is_rvfi_valid_norevoke_notrigger && + ( + ((rvfi_insn & CUSTOM0_IMASK) == CUSTOM0_IDATA) || + ((rvfi_insn & CUSTOM1_IMASK) == CUSTOM1_IDATA) + ) + ); + wire is_rvfi_wfe = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn == WFE_IDATA) + ); + wire is_rvfi_uret = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn == URET_IDATA) + ); + wire is_rvfi_ebreak = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn == EBREAK_IDATA) + ); + wire is_rvfi_ecall = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn == ECALL_IDATA) + ); + wire is_rvfi_csrinstr = ( + is_rvfi_valid_norevoke_notrigger && + (rvfi_insn[ 6: 0] == 7'b 1110011) && + (rvfi_insn[14:12] inside {1, 2, 3, 5, 6, 7}) + ); + + reg was_rvfi_valid; + wire clk_rvfi; + always @(posedge clk_i) begin + was_rvfi_valid <= rvfi_valid; + end + assign clk_rvfi = clk_i & was_rvfi_valid; + + reg [1:0] effective_rvfi_privmode; + always @(*) begin + if (rvfi_csr_mstatus_rdata[MPRV_POS+:MPRV_LEN]) begin + effective_rvfi_privmode = rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN]; + end else begin + effective_rvfi_privmode = rvfi_mode; + end + end + + reg [1:0] was_rvfi_mode; + reg [1:0] was_rvfi_mode_wdata; // Expected next mode (ignoring dmode) + reg was_rvfi_dbg_mode; + always @(posedge clk_i) begin + if (rvfi_valid) begin + was_rvfi_mode <= rvfi_mode; + was_rvfi_dbg_mode <= rvfi_dbg_mode; + + was_rvfi_mode_wdata <= + (is_rvfi_mret && !rvfi_trap.exception) ? ( + rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN] + ) : ( + (is_rvfi_dret && !rvfi_trap.exception) ? ( + rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] + ) : ( + (rvfi_trap.exception) ? ( + MODE_M + ) : ( + rvfi_mode + ) + ) + ); + // TODO:INFO:silabs-robin Check "(rvfi_mode == ...wdata) || rvfi_intr" + end + end + + wire logic [MPP_LEN-1:0] mpp_rdata; + wire logic [MPP_LEN-1:0] mpp_rdata_past; + assign mpp_rdata = rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN]; + assign mpp_rdata_past = $past(mpp_rdata, , ,@(posedge clk_rvfi)); + + + // vplan:MisaU & vplan:MisaN + + a_misa_bits: assert property ( + rvfi_valid + |-> + rvfi_csr_misa_rdata[MISA_U_POS] && + !rvfi_csr_misa_rdata[MISA_S_POS] && + !rvfi_csr_misa_rdata[MISA_N_POS] + ) else `uvm_error(info_tag, "misa has wrong extension bits"); + + + // vplan:SupportedLevels + + a_no_unsupported_modes: assert property ( + rvfi_valid + |-> + (rvfi_mode inside {MODE_U, MODE_M}) + ) else `uvm_error(info_tag, "non-supported privilege level executed"); + + cov_umode: cover property ( + rvfi_valid && (rvfi_mode == MODE_U) + ); + + cov_mmode: cover property ( + rvfi_valid && (rvfi_mode == MODE_M) + ); + + + // vplan:ResetMode + + a_initial_mode: assert property ( + $past(rst_ni == 0) ##0 + (rvfi_valid [->1]) + |-> + (rvfi_mode == MODE_M) && + (rvfi_order inside {0, 1}) + ) else `uvm_error(info_tag, "priv mode out of reset should be machine-mode"); + + + // vplan:MscratchReliable + + a_mscratch_reliable: assert property ( + rvfi_valid && (rvfi_mode == MODE_U) + |-> + (rvfi_csr_mscratch_wmask == 'd 0) + ) else `uvm_error(info_tag, "mscratch should not change in user-mode"); + + cov_mscratch_changing: cover property ( + rvfi_valid && + (rvfi_csr_mscratch_wmask != 'd 0) + ); + + + // vplan:MppValues + + a_mpp_mode: assert property ( + rvfi_valid + |-> + mstatus_poststate[MPP_POS+:MPP_LEN] inside {MODE_M, MODE_U} + ) else `uvm_error(info_tag, "mpp can only hold user- and machine-mode"); + + cov_mpp_mmode: cover property ( + rvfi_valid && + (rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN] == MODE_M) + ); + + cov_mpp_umode: cover property ( + rvfi_valid && + (rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN] == MODE_U) + ); + + + // vplan:SppValues + + a_spp_zero: assert property ( + rvfi_valid + |-> + (rvfi_csr_mstatus_rdata[SPP_POS+:SPP_LEN] == 'd 0) + ) else `uvm_error(info_tag, "spp must be zero because supervisor-mode is not implemented"); + + + // vplan:TrapMpp + + property p_trap_mpp_exception; + int was_mode; + int was_dbg; + (rvfi_valid && rvfi_trap.exception) ##0 + (1, was_mode = rvfi_mode) ##0 + (1, was_dbg = rvfi_dbg_mode) + ##1 + (rvfi_valid [->1]) + |-> + (rvfi_mode == MODE_M) && + ( + (rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN] == was_mode) || + rvfi_intr.interrupt || + was_dbg + ) + ; + endproperty : p_trap_mpp_exception + + a_trap_mpp_exception: assert property ( + p_trap_mpp_exception + ) else `uvm_error(info_tag, "when exceptions from mode y are handled, mpp must become y"); + + a_trap_mpp_general: assert property ( + rvfi_valid && + rvfi_intr && + !(was_rvfi_dbg_mode && rvfi_dbg_mode) + |-> + if (rvfi_intr.exception) ( + (mpp_rdata == was_rvfi_mode) + ) else ( + (mpp_rdata == was_rvfi_mode_wdata) || + (rvfi_intr.cause inside {[1024:1027]}) // NMI + // TODO:INFO:silabs-robin Preferably, exclude only "multi-lvl irq" specifically + ) + ) else `uvm_error(info_tag, "when traps from mode y are handled, mpp must become y"); + + a_trap_mpp_debug: assert property ( + @(posedge clk_rvfi) + rvfi_valid && + rvfi_intr && + was_rvfi_dbg_mode && + rvfi_dbg_mode + |-> + (mpp_rdata == mpp_rdata_past) || + (rvfi_dbg && rvfi_intr.interrupt) + ) else `uvm_error(info_tag, "when trapping inside dmode mpp must be M-mode"); + + + // vplan:TrapsMmode & vplan:ToMmode + + a_traps_mmode: assert property ( + rvfi_valid && + rvfi_trap + ##1 + (rvfi_valid [->1]) + |-> + (rvfi_mode == MODE_M) + ) else `uvm_error(info_tag, "all traps handling shall happen in mmode"); + + a_interrupt_mmode: assert property ( + rvfi_valid && + rvfi_intr + |-> + (rvfi_mode == MODE_M) + ) else `uvm_error(info_tag, "all traps shall be handled in mmode"); + + a_umodetrap_zeromprv: assert property ( + (rvfi_valid && (rvfi_mode == MODE_U)) + ##1 + (rvfi_valid [->1]) + |-> + (rvfi_csr_mstatus_rdata[MPRV_POS+:MPRV_LEN] == 1'b 0) + ) else `uvm_error(info_tag, "traps in umode keep mprv at zero"); + + + // vplan:MretLeastPrivileged + + a_mret_to_mpp: assert property ( + is_rvfi_mret && + !rvfi_trap + |-> + (mstatus_poststate[MPP_POS+:MPP_LEN] == MODE_U) + ) else `uvm_error(info_tag, "mret should set mpp to umode"); + + + // vplan:MretMprv + + sequence seq_mret_notrap_toumode; + is_rvfi_mret && + !rvfi_trap && + (rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN] != MODE_M) + ; + endsequence : seq_mret_notrap_toumode + + a_mret_mprv_poststate: assert property ( + seq_mret_notrap_toumode + |-> + (mstatus_poststate[MPRV_POS+:MPRV_LEN] == 1'b 0) + ) else `uvm_error(info_tag, "mret into umode must clear mstatus.mprv"); + + a_mret_mprv_writestate: assert property ( + seq_mret_notrap_toumode + |-> + (mstatus_writestate[MPRV_POS+:MPRV_LEN] == 1'b 0) + ) else `uvm_error(info_tag, "mret into umode must write mstatus.mprv to zero"); + + a_mret_mprv_writempp: assert property ( + seq_mret_notrap_toumode + |-> + rvfi_csr_mstatus_wmask[MPRV_POS+:MPRV_LEN] + ) else `uvm_error(info_tag, "mret into umode must write mstatus.mprv"); + + a_mret_mprv_writemstatus_simplified: assert property ( + seq_mret_notrap_toumode ##0 + (!rvfi_dbg_mode && !rvfi_intr) + |-> + rvfi_csr_mstatus_wmask + ) else `uvm_error(info_tag, "mret into umode must write mstatus"); + + a_mprv_poststate: assert property ( + rvfi_csr_mstatus_wmask[MPRV_POS+:MPRV_LEN] + |-> + (mstatus_writestate[MPRV_POS+:MPRV_LEN] == mstatus_poststate[MPRV_POS+:MPRV_LEN]) + ) else `uvm_error(info_tag, "mstatus writes are reflected in the post state"); + + + // vplan:WfiExecute & vplan:WfiIllegal + + a_wfi_illegal: assert property ( + is_rvfi_wfi && + (rvfi_mode == MODE_U) && + (rvfi_csr_mstatus_rdata[TW_POS+:TW_LEN] == 1) + |-> + is_rvfi_illegalinsn ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "wfi in umode w/ tw==1 is illegal"); + + a_wfi_normal: assert property ( + is_rvfi_wfi && + (rvfi_mode == MODE_U) && + (rvfi_csr_mstatus_rdata[TW_POS+:TW_LEN] == 0) + |-> + !is_rvfi_illegalinsn + ) else `uvm_error(info_tag, "wfi in umode w/ tw==0 is not illegal"); + + + // vplan:CustomInstr & vplan:Uret + + a_custom_instr: assert property ( + is_rvfi_customumodeinstr && + !is_rvfi_wfe + |-> + is_rvfi_illegalinsn ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "user-level custom instrs are not supported"); + + a_uret: assert property ( + is_rvfi_uret + |-> + is_rvfi_illegalinsn ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "the uret instruction is not supported"); + + + // vplan:EbreakuOn + + a_ebreaku_on_rvfivalid: assert property ( + is_rvfi_ebreak && + (rvfi_mode == MODE_U) && + rvfi_csr_dcsr_rdata[EBREAKU_POS+:EBREAKU_LEN] + ##1 + (rvfi_valid [->1]) + |-> + rvfi_dbg_mode + ) else `uvm_error(info_tag, "umode ebreak with ebreaku should cause dmode"); + + cov_ebreaku_bit: cover property ( + rvfi_csr_dcsr_rdata[EBREAKU_POS+:EBREAKU_LEN] + ); + + a_ebreaku_on_dbgtrap: assert property ( + is_rvfi_ebreak && + (rvfi_mode == MODE_U) && + rvfi_csr_dcsr_rdata[EBREAKU_POS+:EBREAKU_LEN] + |-> + rvfi_if.rvfi_trap.trap && + rvfi_if.rvfi_trap.debug + ) else `uvm_error(info_tag, "ebreaku must give debug trap"); + + a_ebreaku_on_noexception: assert property ( + is_rvfi_ebreak && + (rvfi_mode == MODE_U) && + rvfi_csr_dcsr_rdata[EBREAKU_POS+:EBREAKU_LEN] + |-> + !( + rvfi_if.rvfi_trap.exception && + (rvfi_if.rvfi_trap.exception_cause == EXC_CAUSE_BREAKPOINT) + ) + ); + + + // vplan:EbreakuOff + + sequence seq_ebreak_umode_noebreaku; + is_rvfi_ebreak && + (rvfi_mode == MODE_U) && + !rvfi_csr_dcsr_rdata[EBREAKU_POS+:EBREAKU_LEN] + ; + endsequence : seq_ebreak_umode_noebreaku + + a_ebreaku_off_trap: assert property ( + seq_ebreak_umode_noebreaku + |-> + rvfi_trap.trap + ) else `uvm_error(info_tag, "umode ebreak wo/ ebreaku should cause a trap"); + + a_ebreaku_off_exception: assert property ( + seq_ebreak_umode_noebreaku + |-> + rvfi_trap.exception + ) else `uvm_error(info_tag, "umode ebreak wo/ ebreaku should cause an exception"); + + a_ebreaku_off_cause: assert property ( + seq_ebreak_umode_noebreaku + |-> + (rvfi_trap.exception_cause == EXC_CAUSE_BREAKPOINT) + ) else `uvm_error(info_tag, "umode ebreak wo/ ebreaku should cause an exception"); + + a_ebreaku_off_nodebug: assert property ( + seq_ebreak_umode_noebreaku + |-> + !rvfi_trap.debug || + (rvfi_trap.debug_cause inside {DBG_CAUSE_STEP}) + ) else `uvm_error(info_tag, "umode ebreak wo/ ebreaku should not cause debug entry"); + + a_ebreaku_off_nodebugcause: assert property ( + seq_ebreak_umode_noebreaku + ##1 + (rvfi_valid [->1]) + |-> + (rvfi_dbg != DBG_CAUSE_EBREAK) + ) else `uvm_error(info_tag, "umode ebreak wo/ ebreaku should not cause dmode"); + + + // vplan:Ecall (in umode) + + a_ecall_umode_trap: assert property ( + (is_rvfi_ecall && (rvfi_mode == MODE_U)) + |-> + rvfi_trap.trap + ) else `uvm_error(info_tag, "umode ecall causes umode ecall exception"); + + a_ecall_umode_exception: assert property ( + (is_rvfi_ecall && (rvfi_mode == MODE_U)) + |-> + rvfi_trap.exception + ) else `uvm_error(info_tag, "umode ecall causes umode ecall exception"); + + a_ecall_umode_cause: assert property ( + (is_rvfi_ecall && (rvfi_mode == MODE_U)) + |-> + (rvfi_trap.exception_cause inside {EXC_CAUSE_ECALL_UMODE, 1, 2, 24, 25}) // ("It" or higher) + ) else `uvm_error(info_tag, "umode ecall causes umode ecall exception"); + + a_ecall_umode_poststate: assert property ( + (is_rvfi_ecall && (rvfi_mode == MODE_U)) + |-> + (mcause_poststate[11:0] inside {EXC_CAUSE_ECALL_UMODE, 1, 2, 24, 25}) // ("It" or higher) + ) else `uvm_error(info_tag, "umode ecall causes umode ecall exception"); + + + // vplan:ExecuteMmode (in debug) + + a_dmode_mmode: assert property ( + rvfi_valid && + rvfi_dbg_mode + |-> + (rvfi_mode == MODE_M) + ) else `uvm_error(info_tag, "dmode must execute in mmode"); + + + // vplan:ResumePriv + + property p_dret_prv; + int prv; + (rvfi_valid && rvfi_dbg_mode) ##0 + (1, prv = rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN]) + ##1 + (rvfi_valid [->1]) ##0 + !rvfi_dbg_mode + |-> + (rvfi_mode == prv) || + rvfi_intr.interrupt + ; + endproperty : p_dret_prv + + a_dret_prv: assert property ( + p_dret_prv + ) else `uvm_error(info_tag, "resuming from dmode should be in dcsr.prv mode"); + + cov_dret_prv_u: cover property ( + reject_on + (rvfi_valid && !rvfi_dbg_mode && (rvfi_mode != MODE_U)) + p_dret_prv + ); + + cov_dret_prv_m: cover property ( + reject_on + (rvfi_valid && !rvfi_dbg_mode && (rvfi_mode != MODE_M)) + p_dret_prv + ); + + cov_prv_u: cover property ( + rvfi_valid && + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_U) + ); + + cov_prv_m: cover property ( + rvfi_valid && + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_M) + ); + + + + // vplan:ResumeMprv + + a_dret_mprv_umode: assert property ( + (rvfi_valid && rvfi_dbg_mode) + ##1 + ((rvfi_valid [->1]) ##0 !rvfi_dbg_mode) ##0 + (rvfi_mode == MODE_U) + |-> + (rvfi_csr_mstatus_rdata[MPRV_POS+:MPRV_LEN] == 1'b 0) + ) else `uvm_error(info_tag, "exiting dmode into umode should clear mprv"); + + a_dret_mprv_prv: assert property ( + (rvfi_valid && rvfi_dbg_mode) ##0 + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_U) + ##1 + ((rvfi_valid [->1]) ##0 !rvfi_dbg_mode) + |-> + (rvfi_csr_mstatus_rdata[MPRV_POS+:MPRV_LEN] == 1'b 0) + ) else `uvm_error(info_tag, "exiting dmode towards umode should clear mprv"); + + a_dret_mprv_csr: assert property ( + rvfi_if.is_dret && + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_U) && + rvfi_if.rvfi_dbg_mode + |-> + (rvfi_csr_mstatus_wmask[MPRV_POS+:MPRV_LEN] == 1'b 1) && + (rvfi_csr_mstatus_wdata[MPRV_POS+:MPRV_LEN] == 1'b 0) + ) else `uvm_error(info_tag, "dret to umode clears mprv immediately"); + + + // vplan:UmodeUnmodified (wrt MPRV) + + a_umode_unmodified: assert property ( + rvfi_valid && + (rvfi_mode == MODE_U) + |-> + (rvfi_csr_mstatus_rdata[MPRV_POS+:MPRV_LEN] == 1'b 0) + ) else `uvm_error(info_tag, "umode should have no way of running with modified privilege"); + + + // vplan:UserExtensions + + a_umode_extensions: assert property ( + rvfi_valid + |-> + !rvfi_csr_mstatus_rdata[XS_POS+:XS_LEN] && + !rvfi_csr_mstatus_rdata[FS_POS+:FS_LEN] && + !rvfi_csr_mstatus_rdata[SD_POS+:SD_LEN] + ) else `uvm_error(info_tag, "none of the mstatus umode extension bits shall be used"); + + + // vplan:IllegalAccess + + a_illegal_csr_access: assert property ( + is_rvfi_csrinstr && + (rvfi_mode == MODE_U) && + (rvfi_insn[29:28] != MODE_U) + |-> + is_rvfi_illegalinsn ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "access to higher lvl csrs is illegal"); + + + // vplan:MretMpp + + property p_mret_from_mpp (int mode); + is_rvfi_mret && + (rvfi_mode == MODE_M) && + (rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN] == mode) && + !rvfi_trap && + !rvfi_dbg_mode + ##1 + (rvfi_valid [->1]) ##0 + !rvfi_intr.interrupt && + !rvfi_dbg_mode + |-> + (rvfi_mode == mode); + endproperty : p_mret_from_mpp + + a_mret_from_mpp_umode: assert property ( + p_mret_from_mpp(MODE_U) + ) else `uvm_error(info_tag, "mret should result in privmode from mstatus.mpp (umode)"); + + a_mret_from_mpp_mmode: assert property ( + p_mret_from_mpp(MODE_M) + ) else `uvm_error(info_tag, "mret should result in privmode from mstatus.mpp (mmode)"); + + + // vplan:Mret (in umode) + + a_mret_umode_exception: assert property ( + (is_rvfi_mret && (rvfi_mode == MODE_U)) + |-> + is_rvfi_illegalinsn ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "mret in umode is illegal"); + + a_mret_umode_nextmode: assert property ( + (is_rvfi_mret && (rvfi_mode == MODE_U)) + ##1 + (rvfi_valid [->1]) + |-> + (rvfi_mode == MODE_M) + ) else `uvm_error(info_tag, "mret in umode traps to mmode"); + + a_mret_umode_mpp: assert property ( + (is_rvfi_mret && (rvfi_mode == MODE_U)) + ##1 + (rvfi_valid [->1]) + |-> + ( + (rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN] == MODE_U) || + rvfi_intr.interrupt + ) + ) else `uvm_error(info_tag, "mret in umode sets mpp to umode, unless interrupted"); + + // a_mret_umode_mprv - Handled by a_umodetrap_zeromprv. + + + // vplan:McounterenClear & vplan:McounterenSet & vplan:Mcounteren + + for (genvar i = 0; i < 31; i++) begin : gen_mcounteren_clear + a_check: assert property ( + is_rvfi_csrinstr && + (rvfi_mode == MODE_U) && + (rvfi_insn[31:20] == CSRADDR_HPM0 + i) && + !rvfi_csr_mcounteren_rdata[i] + |-> + is_rvfi_illegalinsn ^ + is_rvfi_instrtriggered ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "when mcounteren bit is off then umode access is illegal"); + end + + a_mcounteren_zeros: assert property ( + rvfi_valid + |-> + (rvfi_csr_mcounteren_rdata == 0) + ) else `uvm_error(info_tag, "not all bits in mcounteren can be non-zero"); + + a_mcounteren_access: assert property ( + is_rvfi_csrinstr && + (rvfi_mode == MODE_M) && + (rvfi_insn[31:20] == CSRADDR_MCOUNTEREN) + |-> + !is_rvfi_illegalinsn + ) else `uvm_error(info_tag, "mcounteren must be implemented"); + + + // vplan:Jvt + + a_jvt_access: assert property ( + is_rvfi_csrinstr && + (rvfi_insn[31:20] == CSRADDR_JVT) + |-> + !is_rvfi_illegalinsn || + (!rvfi_csr_mstateen0_rdata[2] && (rvfi_mode == MODE_U)) + ) else `uvm_error(info_tag, "jvt csr should be rw in both modes"); + + + // vplan:SoftwareInterrupts + + property p_softwareinterrupts_zeros(logic [31:0] csr); + rvfi_valid + |-> + //[31:16] + !csr[15:12] && + //[11:11] + !csr[10: 8] && + //[ 7: 7] + !csr[ 6: 4] && + //[ 3: 3] + !csr[ 2: 0] + ; + endproperty : p_softwareinterrupts_zeros + + a_softwareinterrupts_zeromie: assert property ( + p_softwareinterrupts_zeros(rvfi_csr_mie_rdata) + ) else `uvm_error(info_tag, "certain bits in 'mie' must be zero"); + + a_softwareinterrupts_zeromip: assert property ( + p_softwareinterrupts_zeros(rvfi_csr_mip_rdata) + ) else `uvm_error(info_tag, "certain bits in 'mip' must be zero"); + + if (!CLIC) begin: gen_softwareinterrupts_mcausemode + a_softwareinterrupts_mcausemode: assert property ( + rvfi_intr.interrupt + |-> + !(rvfi_intr.cause inside {[0:2], [4:6], [8:10], [12:15]}) + ) else `uvm_error(info_tag, "unexpected interrupt cause"); + end : gen_softwareinterrupts_mcausemode + + + // vplan:NExt + + a_next_csrs: assert property ( + is_rvfi_csrinstr && + (rvfi_insn[31:20] inside { + CSRADDR_USTATUS, CSRADDR_UIE, CSRADDR_UTVEC, CSRADDR_USCRATCH, + CSRADDR_UEPC, CSRADDR_UCAUSE, CSRADDR_UTVAL, CSRADDR_UIP + } + ) + |-> + is_rvfi_illegalinsn ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "none of the n ext csrs should be present"); + + + // vplan:ExecuteMprven (in debug) + + a_mprven_tied: assert property ( + rvfi_valid + |-> + (rvfi_csr_dcsr_rdata[MPRVEN_POS+:MPRVEN_LEN] == 1'b 1) + ) else `uvm_error(info_tag, "dcsr.mprven is not supported"); + + + // vplan:PrvEntry + + property p_prv_entry; + (rvfi_valid && !rvfi_dbg_mode) + ##1 + (rvfi_valid [->1]) ##0 + rvfi_dbg_mode + |-> + if (!rvfi_intr[0]) ( + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == was_rvfi_mode_wdata) + ) else ( + (rvfi_intr.exception ^ rvfi_intr.interrupt) && + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_M) + ); + endproperty : p_prv_entry + + a_prv_entry: assert property ( + p_prv_entry + ) else `uvm_error(info_tag, "on dbg entry, dcsr.prv should be previous privmode"); + + cov_prv_entry_u: cover property ( + reject_on + (rvfi_valid && rvfi_dbg_mode && (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] != MODE_U)) + p_prv_entry + ); + + cov_prv_entry_m: cover property ( + reject_on + (rvfi_valid && rvfi_dbg_mode && (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] != MODE_M)) + p_prv_entry + ); + + + // vplan:PrvSupported + + a_prv_supported: assert property ( + rvfi_valid + |-> + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] inside {MODE_U, MODE_M}) + ) else `uvm_error(info_tag, "dcsr.prv must hold supported privmodes"); + + cov_prv_supported_umode: cover property ( + rvfi_valid && + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_U) + ); + + cov_prv_supported_mmode: cover property ( + rvfi_valid && + (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_M) + ); + + + // vplan:MedelegMideleg + + a_medeleg_mideleg: assert property ( + is_rvfi_csrinstr && + (rvfi_insn[31:20] inside {CSRADDR_MEDELEG, CSRADDR_MIDELEG}) + |-> + is_rvfi_illegalinsn ^ + (rvfi_trap.exception_cause inside {1, 24, 25}) // Higher priority exceptions + ) else `uvm_error(info_tag, "medeleg and mideleg registers should not exist"); + + + // vplan:InstrProt + + a_instr_prot: assert property ( + rvfi_valid + |-> + (rvfi_if.instr_prot[2:1] == rvfi_if.rvfi_mode) || + (rvfi_if.rvfi_trap.exception_cause == cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT) || + (rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER) + //Note: Triggers can overshadow access faults + ) else `uvm_error(info_tag, "the prot on fetch must match the mode on retirement"); + + a_instr_prot_legal: assert property ( + rvfi_valid && + (rvfi_if.rvfi_trap.exception_cause != cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT) + |-> + (rvfi_if.instr_prot[2:0] inside {3'b 000, 3'b 110}) + ) else `uvm_error(info_tag, "instr_prot illegal value"); + + a_prot_iside_legal: assert property ( + obi_iside_prot inside {3'b 000, 3'b 110} + ) else `uvm_error(info_tag, "the prot on fetch must be legal"); + + + // vplan:DataProt + + a_data_prot: assert property ( + rvfi_valid && + (rvfi_if.rvfi_mem_rmask || rvfi_if.rvfi_mem_wmask) + |-> + (rvfi_if.mem_prot[2:1] == effective_rvfi_privmode) + ) else `uvm_error(info_tag, "the prot on load/store must match the effective mode on retirement"); + + a_data_prot_legal: assert property ( + rvfi_valid && + (rvfi_if.rvfi_trap.exception_cause != cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT) + |-> + (rvfi_if.mem_prot[2:0] inside {3'b 001, 3'b 111}) + ) else `uvm_error(info_tag, "data_prot illegal value"); + + a_prot_dside_legal: assert property ( + obi_dside_prot inside {3'b 001, 3'b 111} + ) else `uvm_error(info_tag, "the prot on loadstore must be legal"); + + wire logic [NMEM-1:0] data_prot_equals; + wire logic [NMEM-1:0] mem_act; + for (genvar i = 0; i < NMEM; i++) begin: gen_data_prot_equals + assign data_prot_equals[i] = (rvfi_if.mem_prot[i*3+:3] == rvfi_if.mem_prot[2:0]); + assign mem_act[i] = |rvfi_if.check_mem_act(i); + end + + a_data_prot_equal: assert property ( + rvfi_valid && + (|rvfi_if.rvfi_mem_rmask || |rvfi_if.rvfi_mem_wmask) + |-> + ((data_prot_equals & mem_act) == mem_act) + ) else `uvm_error(info_tag, "data prot should match accesses from same instr"); + + cov_data_prot_equal_memact_load: cover property ( + rvfi_valid && + ($countones(mem_act) > 1) && + (|rvfi_if.rvfi_mem_rmask) + ); + + cov_data_prot_equal_memact_store: cover property ( + rvfi_valid && + ($countones(mem_act) > 1) && + (|rvfi_if.rvfi_mem_wmask) + ); + + + // vplan:DbgProt + + a_dbg_prot_iside: assert property ( + rvfi_if.rvfi_valid && + rvfi_if.rvfi_dbg_mode + |-> + (rvfi_if.instr_prot[2:1] == MODE_M) || + (rvfi_if.rvfi_trap.exception_cause == cv32e40s_pkg::EXC_CAUSE_INSTR_FAULT) + ) else `uvm_error(info_tag, "dmode should fetch as mmode"); + + a_dbg_prot_dside: assert property ( + rvfi_if.rvfi_dbg_mode && + rvfi_valid && + (|rvfi_if.rvfi_mem_rmask || |rvfi_if.rvfi_mem_wmask) + |-> + (rvfi_if.mem_prot[2:1] == effective_rvfi_privmode) + ) else `uvm_error(info_tag, "dmode should fetch as effective mode"); + + +endmodule : uvmt_cv32e40s_umode_assert + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_cov.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_cov.sv new file mode 100644 index 0000000000..510ee6896e --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_cov.sv @@ -0,0 +1,444 @@ +// Copyright 2022 Silicon Labs, Inc. +// Copyright 2022 OpenHW Group +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +// not use this file except in compliance with the License, or, at your option, +// the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`default_nettype none + + +module uvmt_cv32e40s_umode_cov + import uvma_rvfi_pkg::*; +#( + int ILEN = DEFAULT_ILEN, + int XLEN = DEFAULT_XLEN +)( + input wire clk_i, + input wire rst_ni, + + input wire rvfi_valid, + input wire rvfi_trap_t rvfi_trap, + input wire rvfi_intr_t rvfi_intr, + input wire [31:0] rvfi_insn, + input wire [31:0] rvfi_rs1_rdata, + input wire [31:0] rvfi_pc_rdata, + input wire [ 1:0] rvfi_mode, + input wire [ 4:0] rvfi_rd_addr, + input wire rvfi_dbg_mode, + input wire [63:0] rvfi_order, + input wire [(NMEM*XLEN/8)-1:0] rvfi_mem_rmask, + input wire [(NMEM*XLEN/8)-1:0] rvfi_mem_wmask, + + input wire [31:0] rvfi_csr_mstatus_rdata, + input wire [31:0] rvfi_csr_mstatus_rmask, + input wire [31:0] rvfi_csr_dcsr_rdata, + input wire [31:0] rvfi_csr_dcsr_rmask, + + input wire obi_iside_req, + input wire obi_iside_gnt, + input wire [31:0] obi_iside_addr, + input wire [ 2:0] obi_iside_prot +); + + + // Clock & Reset + + default clocking @(posedge clk_i); endclocking + default disable iff !rst_ni; + + + // Helper Definitions + + localparam bit [1:0] MODE_U = 2'b 00; + localparam bit [1:0] MODE_M = 2'b 11; + + localparam bit [11:0] CSRADDR_MISA = 12'h 301; + localparam bit [11:0] CSRADDR_MSCRATCH = 12'h 340; + localparam bit [11:0] CSRADDR_MSTATUS = 12'h 300; + localparam bit [11:0] CSRADDR_MEDELEG = 12'h 302; + localparam bit [11:0] CSRADDR_MIDELEG = 12'h 303; + localparam bit [11:0] CSRADDR_MCOUNTEREN = 12'h 306; + + localparam int EXC_ACCESFAULT = 1; + localparam int EXC_BUSFAULT = 24; + + typedef struct packed { + logic [31:18] dontcare2; + logic [17:17] mprv; + logic [16:13] dontcare1; + logic [12:11] mpp; + logic [10: 0] dontcare0; + } mstatus_t; + + typedef struct packed { + logic [31:2] dontcare; + logic [ 1:0] prv; + } dcsr_t; + + + // Helper Signals + + logic is_rvfi_instrrevoked; + assign is_rvfi_instrrevoked = + rvfi_trap.exception && + (rvfi_trap.exception_cause inside {EXC_ACCESFAULT, EXC_BUSFAULT}); + + logic is_rvfi_valid_norevoke; + assign is_rvfi_valid_norevoke = + rvfi_valid && + !is_rvfi_instrrevoked; + + logic is_rvfi_csr_instr; + assign is_rvfi_csr_instr = + is_rvfi_valid_norevoke && + (rvfi_insn[ 6: 0] == 7'b 1110011) && + (rvfi_insn[14:12] inside {1, 2, 3, 5, 6, 7}) ; + + logic is_rvfi_csr_instr_read; + assign is_rvfi_csr_instr_read = + is_rvfi_csr_instr && + ( + rvfi_rd_addr || // "rd != x0" + !(rvfi_insn[14:12] inside {1, 5}) // ...or not "csrrw[i]" + ); + + logic is_rvfi_csr_instr_write; + assign is_rvfi_csr_instr_write = + is_rvfi_csr_instr && + ( + rvfi_insn[19:15] || // "rs1 != x0/0" + (rvfi_insn[14:12] inside {1, 5}) // ...or "csrrw[i]" + ); + + logic is_rvfi_notrap_csrrw; + assign is_rvfi_notrap_csrrw = + rvfi_valid && + !rvfi_trap && + (rvfi_insn[ 6: 0] == 7'b 1110011) && // op + (rvfi_insn[14:12] == 1'd 1) ; // funct3 + + logic is_rvfi_notrap_csrrw_mstatus; + assign is_rvfi_notrap_csrrw_mstatus = + is_rvfi_notrap_csrrw && + (rvfi_insn[31:20] == 12'h 300) ; // csr + + logic is_rvfi_notrap_csrrw_dcsr; + assign is_rvfi_notrap_csrrw_dcsr = + is_rvfi_notrap_csrrw && + (rvfi_insn[31:20] == 12'h 7B0) ; // csr + + mstatus_t have_rvfi_csrrw_wdata_mstatus; + assign have_rvfi_csrrw_wdata_mstatus = + rvfi_rs1_rdata; + + dcsr_t have_rvfi_csrrw_wdata_dcsr; + assign have_rvfi_csrrw_wdata_dcsr = + rvfi_rs1_rdata; + + mstatus_t have_rvfi_mstatus_rdata; + assign have_rvfi_mstatus_rdata = + (rvfi_csr_mstatus_rdata & rvfi_csr_mstatus_rmask); + + dcsr_t have_rvfi_dcsr_rdata; + assign have_rvfi_dcsr_rdata = + (rvfi_csr_dcsr_rdata & rvfi_csr_dcsr_rmask); + + logic is_rvfi_notrap_mret; + assign is_rvfi_notrap_mret = + rvfi_valid && + !rvfi_trap && + (rvfi_insn == 32'b 0011000_00010_00000_000_00000_1110011); + + logic is_rvfi_notrap_dret; + assign is_rvfi_notrap_dret = + rvfi_valid && + !rvfi_trap && + (rvfi_insn == 32'h 7b20_0073); + + logic is_obi_iside_aphase; + assign is_obi_iside_aphase = + obi_iside_req && + obi_iside_gnt ; + + var [1:0] was_rvfi_mode; + always @(posedge clk_i) begin + if (rvfi_valid) begin + was_rvfi_mode <= rvfi_mode; + end + end + + var [63:0] clk_cnt; + always @(posedge clk_i, negedge rst_ni) begin + if (rst_ni == 0) begin + clk_cnt <= 64'd 1; + end else if (clk_cnt != '1) begin + clk_cnt <= clk_cnt + 64'd 1; + end + end + + + // Helper Sequences + + sequence seq_next_rvfi_valid; + 1 ##1 + (rvfi_valid [->1]) + ; + endsequence : seq_next_rvfi_valid + + sequence seq_write_mstatus_mpp (mode); + is_rvfi_notrap_csrrw_mstatus && + (have_rvfi_csrrw_wdata_mstatus.mpp == mode) + ; + endsequence : seq_write_mstatus_mpp + + sequence seq_write_dcsr_prv (mode); + is_rvfi_notrap_csrrw_dcsr && + (have_rvfi_csrrw_wdata_dcsr.prv == mode) + ; + endsequence : seq_write_dcsr_prv + + + // Cover - vplan:SupportedLevels & vplan:MppValues + + for (genvar mode = 0; mode <= 3; mode++) begin : gen_try_goto_mode + cov_try_goto_mode: cover property ( + seq_write_mstatus_mpp (mode) ##0 + seq_next_rvfi_valid ##0 + is_rvfi_notrap_mret + ); + + // Plus some helper covers to be sure + cov_write_mpp: cover property ( + seq_write_mstatus_mpp (mode) + ); + cov_notrap_mret: cover property ( + is_rvfi_notrap_mret + ); + end : gen_try_goto_mode + + + // Cover - vplan:PrvSupported + + for (genvar mode = 0; mode <= 3; mode++) begin : gen_try_set_prv + cov_try_set_prv: cover property ( + seq_write_dcsr_prv (mode) + ); + end : gen_try_set_prv + + + // Cover - vplan:Refetch + + sequence seq_refetch_as (logic [1:0] mode); + logic [31:0] addr; + + is_obi_iside_aphase ##0 + (obi_iside_prot[2:1] != mode) ##0 + (1, addr = obi_iside_addr) + + ##1 + (is_obi_iside_aphase [->1]) ##0 + (obi_iside_prot[2:1] == mode) ##0 + (obi_iside_addr == addr) + + ##5 // (Traverse pipeline) + (rvfi_valid [->1]) ##0 + (rvfi_pc_rdata == addr) ##0 + (rvfi_mode == mode) + ; + endsequence : seq_refetch_as + + cov_refetch_as_umode_notrap: cover property ( + seq_refetch_as(MODE_U) ##0 !rvfi_trap + ); + cov_refetch_as_mmode_notrap: cover property ( + seq_refetch_as(MODE_M) ##0 !rvfi_trap + ); + cov_refetch_as_umode_trap: cover property ( + seq_refetch_as(MODE_U) ##0 rvfi_trap.exception + ); + cov_refetch_as_mmode_trap: cover property ( + seq_refetch_as(MODE_M) ##0 rvfi_trap.exception + ); + + + // Cover - vplan:TrapsMmode (Helper Covers) + + cov_umode_intr: cover property ( + rvfi_valid && + (was_rvfi_mode == MODE_U) && + rvfi_intr.interrupt && + (rvfi_order > 64'd 1) + ); + + `ifdef FORMAL // (Don't need this specificity in sim) + cov_umode_intr_32: cover property ( + rvfi_valid && + (was_rvfi_mode == MODE_U) && + rvfi_intr.interrupt && + (rvfi_order > 64'd 1) && + (clk_cnt == 32) + ); + `endif + + cov_umode_notrap: cover property ( + rvfi_valid && + (rvfi_mode == MODE_U) && + !rvfi_trap + ); + + `ifdef FORMAL // (Don't need this specificity in sim) + cov_umode_notrap_25: cover property ( + rvfi_valid && + (rvfi_mode == MODE_U) && + !rvfi_trap && + (clk_cnt == 25) + ); + `endif + + + // Cover - vplan:ResumeMprv (Helper Covers) + + cov_umode_mprv: cover property ( + rvfi_valid && + have_rvfi_mstatus_rdata.mprv && + (have_rvfi_dcsr_rdata.prv == MODE_U) && + is_rvfi_notrap_dret + ##1 + (rvfi_valid [->1]) + ); + + + // Covergroup, mixed features + + covergroup cg @(posedge clk_i); + option.per_instance = 1; + + // Coverpoints + + cp_mode: coverpoint rvfi_mode iff (rvfi_valid) { + bins mmode = {MODE_M}; + bins umode = {MODE_U}; + } + + `ifndef FORMAL + cp_csraddr: coverpoint rvfi_insn[31:20] iff (is_rvfi_csr_instr) { + bins addr[4096] = {[0:$]}; + } + `endif + + cp_csrreadwrite: coverpoint + {is_rvfi_csr_instr_read, is_rvfi_csr_instr_write} + iff (is_rvfi_csr_instr) + { + bins r = {2'b 10}; + bins w = {2'b 01}; + // bins rw = {2'b 11}; // Enable for thoroughness + } + + cp_umodecsrs: coverpoint rvfi_insn[31:20] iff (is_rvfi_csr_instr) { + bins misa = {CSRADDR_MISA}; + bins mscratch = {CSRADDR_MSCRATCH}; + bins mstatus = {CSRADDR_MSTATUS}; + bins medeleg = {CSRADDR_MEDELEG}; + bins mideleg = {CSRADDR_MIDELEG}; + bins mcounteren = {CSRADDR_MCOUNTEREN}; + } + + cp_mpp: coverpoint have_rvfi_mstatus_rdata.mpp iff (rvfi_valid) { + bins mmode = {MODE_M}; + bins umode = {MODE_U}; + } + + cp_excint: coverpoint + {rvfi_intr.exception, rvfi_intr.interrupt} iff (rvfi_valid) + { + bins exc = {2'b 10}; + bins intr = {2'b 01}; + } + + cp_prevmode: coverpoint + was_rvfi_mode iff (rvfi_valid && (rvfi_order > 1)) + { + bins mmode = {MODE_M}; + bins umode = {MODE_U}; + } + + cp_dmode: coverpoint rvfi_dbg_mode iff (rvfi_valid) { + bins dmode = {1'b 1}; + bins normal = {1'b 0}; + } + + cp_loadstore: coverpoint + {|rvfi_mem_rmask, |rvfi_mem_wmask} iff (rvfi_valid) + { + bins load = {2'b 10}; + bins store = {2'b 01}; + bins none = {2'b 00}; + } + + cp_mprv: coverpoint have_rvfi_mstatus_rdata.mprv iff (rvfi_valid) { + bins on = {1'b 1}; + bins off = {1'b 0}; + } + + cp_dret: coverpoint is_rvfi_notrap_dret iff (rvfi_valid) { + bins dret = {1'b 1}; + } + + cp_prv: coverpoint have_rvfi_dcsr_rdata.prv iff (rvfi_valid) { + bins mmode = {MODE_M}; + bins umode = {MODE_U}; + } + + // Crosses + + // vplan:AccessLevel & vplan:IllegalAccess + `ifndef FORMAL + x_mode_csraddr: cross cp_mode, cp_csraddr; + `endif + + // vlpan:MisaU & vplan:MisaN & vplan:MscratchReliable & vplan:MedelegMideleg + x_csrreadwrite_mode_umodecsrs: + cross cp_csrreadwrite, cp_mode, cp_umodecsrs; + + // vplan:TrapMpp + x_mpp_excint: cross cp_mpp, cp_excint iff (!rvfi_dbg_mode); + + // vplan:TrapsMmode + x_prevmode_excint: cross cp_prevmode, cp_excint; + + // vplan:ExcecuteMmode (in dmode) + x_dmode_csrreadwrite: cross cp_dmode, cp_csrreadwrite; + + // vplan:ExcecuteMmode & vplan:ExcecuteMprven + x_dmode_loadstore: cross cp_dmode, cp_loadstore; + x_dmode_mprv: cross cp_dmode, cp_mprv; + x_dmode_mpp: cross cp_dmode, cp_mpp; + x_dmode_loadstore_mprv_mpp: + cross cp_dmode, cp_loadstore, cp_mprv, cp_mpp + iff (!rvfi_trap); + + // vplan:ResumeMprv + x_dret_mprv_prv: cross cp_dret, cp_mprv, cp_prv; + endgroup + + cg cg_inst = new; + + +endmodule : uvmt_cv32e40s_umode_cov + + +`default_nettype wire diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv new file mode 100644 index 0000000000..d6c94f3db9 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv @@ -0,0 +1,190 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + //Interfaces: + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if, + + //Signals: + input rst_ni, + input clk_i, + + //Alerts: + input logic alert_major, + input logic bus_protocol_hardening_glitch, + + //OBI: + input logic obi_data_rvalid, + input logic obi_instr_rvalid, + + //Resp valids: + input logic instr_if_mpu_resp, + input logic lsu_mpu_resp, + + //Counters: + input logic [1:0] lsu_rf_core_side_cnt, + input logic [1:0] lsu_rf_bus_side_cnt + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + + + logic bus_protocol_hardening_glitch_sticky; + + always @(posedge clk_i) begin + if(!rst_ni) begin + bus_protocol_hardening_glitch_sticky = 0; + end else if (bus_protocol_hardening_glitch) begin + bus_protocol_hardening_glitch_sticky = bus_protocol_hardening_glitch; + end + end + + + //Verify that there are only response packets when there are outstanding requests in the following OBI protocols + + property p_resp(obi_rvalid, v_addr_ph_cnt); + + obi_rvalid + |-> + v_addr_ph_cnt > 0; + + endproperty; + + + a_xsecure_bus_hardening_no_outstanding_obi_instr_trans: assert property ( + p_resp( + obi_instr_rvalid, + support_if.instr_bus_v_addr_ph_cnt) + ) else `uvm_error(info_tag, "There is a response before a request in the OBI instruction bus handshake.\n"); + + a_xsecure_bus_hardening_no_outstanding_obi_data_trans: assert property ( + p_resp( + obi_data_rvalid, + support_if.data_bus_v_addr_ph_cnt) + ) else `uvm_error(info_tag, "There is a response before a request in the OBI data bus handshake.\n"); + + a_xsecure_bus_hardening_alignment_buff_receive_instr_if_mpu_resp: assert property ( + p_resp( + instr_if_mpu_resp, + support_if.alignment_buff_addr_ph_cnt) + ) else `uvm_error(info_tag, "The alignment buffer does not have outstanding requests but receives a response from the instruction interface MPU.\n"); + + a_xsecure_bus_hardening_lsu_receive_lsu_mpu_resp: assert property ( + p_resp( + lsu_mpu_resp, + support_if.lsu_addr_ph_cnt) + ) else `uvm_error(info_tag, "The load-store unit does not have outstanding requests but receives a response from the load-store unit MPU.\n"); + + + //Verify that the core side and bus side transaction counters in the load store units response filter dont underflow + + property p_counter(cnt); + + cnt == 0 + |=> + cnt == 0 || cnt == 1; + + endproperty + + + a_xsecure_bus_hardening_core_side_cnt: assert property ( + p_counter( + lsu_rf_core_side_cnt + ) + ) else `uvm_error(info_tag, "The core side memory transaction counter in the load-store unit response filter underflows.\n"); + + a_xsecure_bus_hardening_bus_side_cnt: assert property ( + p_counter( + lsu_rf_bus_side_cnt + ) + ) else `uvm_error(info_tag, "The bus side memory transaction counter in the load-store unit response filter underflows.\n"); + + + //Verify that major alert is set when there is a response packet even though there are no outstanding requests, in the following OBI protocols + + property p_resp_no_outstanding_req(obi_rvalid, v_addr_ph_cnt); + + //If there has already been a bus protpcol fault the there will be an underflow error and the system acts strangely + !bus_protocol_hardening_glitch_sticky + && obi_rvalid + && v_addr_ph_cnt == 0 + |=> + alert_major; + endproperty; + + a_glitch_xsecure_bus_hardening_no_outstanding_obi_instr_trans: assert property ( + p_resp_no_outstanding_req( + obi_instr_rvalid, + support_if.instr_bus_v_addr_ph_cnt) + ) else `uvm_error(info_tag_glitch, "A response before a request in the OBI instruction bus handshake, but the alert major is not set.\n"); + + a_glitch_xsecure_bus_hardening_no_outstanding_obi_data_trans: assert property ( + p_resp_no_outstanding_req( + obi_data_rvalid, + support_if.data_bus_v_addr_ph_cnt) + ) else `uvm_error(info_tag_glitch, "A response before a request in the OBI data bus handshake, but the alert major is not set.\n"); + + a_glitch_xsecure_bus_hardening_alignment_buff_receive_instr_if_mpu_resp: assert property ( + p_resp_no_outstanding_req( + instr_if_mpu_resp, + support_if.alignment_buff_addr_ph_cnt) + ) else `uvm_error(info_tag_glitch, "The alignment buffer does not have outstanding requests but receives a response from the instruction interface MPU, but the alert major is not set.\n"); + + a_glitch_xsecure_bus_hardening_lsu_receive_lsu_mpu_resp: assert property ( + p_resp_no_outstanding_req( + lsu_mpu_resp, + support_if.lsu_addr_ph_cnt) + ) else `uvm_error(info_tag_glitch, "The load-store unit does not have outstanding requests but receives a response from the load-store unit MPU, but the alert major is not set.\n"); + + + //Verify that the core side and bus side transaction counters in the load store units response filter dont underflow + + property p_counter_underflows(cnt); + + cnt == 0 + ##1 cnt != 0 + && cnt != 1 + |-> + alert_major; + + endproperty + + a_glitch_xsecure_bus_hardening_core_side_cnt_underflows: assert property ( + p_counter_underflows( + lsu_rf_core_side_cnt + ) + ) else `uvm_error(info_tag_glitch, "The core side memory transaction counter in the load-store unit response filter underflows, but the major alert is not set.\n"); + + a_glitch_xsecure_bus_hardening_bus_side_cnt_underflows: assert property ( + p_counter_underflows( + lsu_rf_bus_side_cnt + ) + ) else `uvm_error(info_tag_glitch, "The bus side memory transaction counter in the load-store unit response filter underflows, but the major alert is not set.\n"); + + + endmodule : uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_data_independent_timing_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_data_independent_timing_assert.sv new file mode 100644 index 0000000000..37bfb46bd6 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_data_independent_timing_assert.sv @@ -0,0 +1,157 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +//Information: +//The division and remainder operation not enabled in all run configurations. +//Make sure to run a configuration that support the division and reminder instructions + +module uvmt_cv32e40s_xsecure_data_independent_timing_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + uvma_rvfi_instr_if_t rvfi_if, + uvma_rvfi_csr_if_t rvfi_cpuctrl, + input rst_ni, + input clk_i, + + input logic dataindtiming_enabled + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + + // Local parameters: + localparam FUNCT7_DIV_REM = 7'b0000001; + localparam FUNCT3_DIV_REM_MSB = 1'b1; + + localparam FUNCT3_BRANCH_CMPR_2_MSBS = 2'b11; + localparam OPCODE_BRANCH_CMPR = 2'b01; + + localparam DATAINDTIMING = 0; + localparam PC_HARDENING = 3; + + + //Verify that data independent timing is enabled when exiting reset mode: + + a_xsecure_dataindtiming_default_on: assert property ( + $rose(rst_ni) + |-> + dataindtiming_enabled + ) else `uvm_error(info_tag, "Data independent timing is disabled when exiting reset.\n"); + + + //Verify that execution of branches has non-varying timing when the data independent timing feature is enabled + + //Information: + //All branch instructions in the EX stage flush the IF and ID stage. + //It will therefore be two empty cycles after a branch instruction. + //However, there are 2 exceptions: + //1) A memory instruction prior to a branch instruction: + //The memory instruction can stall the WB stage and then also the branch instruction in the EX stage, + //The incoming instruction can propegate to IF or ID stage therby reducing the number of empty cycles after a branch instruction. + //2) PC hardening enabled: + //The PC hardening feature make a branch instruction into a multicycled instruction. + //When a branch instruction reach the EX stage, the instruction is recalculated in the ID instead of flushing the ID stage. + //Consequently, it is only the IF stage that is flushed, and the branch instruction is considered retired when the + //second branch instruction is retired. + //There is therefor only 1 empty cycle after a branch instruction. + + sequence seq_no_mem_instr_for_cycles(x); + (!rvfi_if.is_mem_act)[*x]; + endsequence + + a_xsecure_dataindtiming_branch_timing_pc_hardening_disabled: assert property ( + + !rvfi_cpuctrl.rvfi_csr_rdata[PC_HARDENING] + && rvfi_cpuctrl.rvfi_csr_rdata[DATAINDTIMING] + && rvfi_if.is_branch + + //The current cycle is not a memory operation (but a branch operation), + //and the prior cycle is not a memory operation + ##0 seq_no_mem_instr_for_cycles(2).triggered + + |=> + (!rvfi_if.rvfi_valid)[*2] + ) else `uvm_error(info_tag, "Branch instruction is not taken even though independent data timing is enabled (PC hardening enabled).\n"); + + + a_xsecure_dataindtiming_branch_timing_pc_hardening_enabled: assert property ( + + rvfi_cpuctrl.rvfi_csr_rdata[PC_HARDENING] + && rvfi_cpuctrl.rvfi_csr_rdata[DATAINDTIMING] + && rvfi_if.is_branch + + //The current cycle is not a memory operation (but the first part of a branch operation), + //the cycle prior to that is not a memory operation (but the second part of a branch operation), + //the cycle prior to that is not a memory cycle as well + ##0 seq_no_mem_instr_for_cycles(3).triggered + + |-> + !$past(rvfi_if.rvfi_valid) //Verifies that the first branch instruction is not considered a retired instruction + ##1 !rvfi_if.rvfi_valid + ) else `uvm_error(info_tag, "Branch instruction is not taken even though independent data timing is enabled (PC hardening enabled).\n"); + + + //Verify that execution of division or (division)-remainder have non-varying timing when the data independent timing feature is enabled + + sequence seq_no_rvalid_for_past_34_cycles; + (!rvfi_if.rvfi_valid[*34] ##1 1); + endsequence + + a_xsecure_dataindtiming_div_rem_timing: assert property ( + + rvfi_cpuctrl.rvfi_csr_rdata[DATAINDTIMING] + && (rvfi_if.is_div || rvfi_if.is_rem) + && !rvfi_if.rvfi_trap.trap + ##0 seq_no_mem_instr_for_cycles(35).triggered + + |-> + seq_no_rvalid_for_past_34_cycles.triggered + + ) else `uvm_error(info_tag, "DIV/REM operations do not use 35 cycles to execute when data independent timing is enabled\n"); + + + //Verify that there is varying timing of branch, division or (division) remainder operations when the data independent timing feature is disabled + + c_xsecure_dataindtiming_branch_timing_off: cover property ( + + !rvfi_cpuctrl.rvfi_csr_rdata[DATAINDTIMING] + + && rvfi_if.is_branch + + //Make sure the branch instruction can be directly followed by another instruction (as the branch is not taken) + ##1 rvfi_if.rvfi_valid + ); + + + c_xsecure_dataindtiming_core_div_rem_timing_off: cover property ( + + !rvfi_cpuctrl.rvfi_csr_rdata[DATAINDTIMING] + + && rvfi_if.is_div || rvfi_if.is_rem + + //Make sure the DIV or REM can be calculated in one cycle only (indicating that data independent timing is off) + && $past(rvfi_if.rvfi_valid) + ); + + endmodule : uvmt_cv32e40s_xsecure_data_independent_timing_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_dummy_and_hint_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_dummy_and_hint_assert.sv new file mode 100644 index 0000000000..a7097cbb04 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_dummy_and_hint_assert.sv @@ -0,0 +1,809 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_dummy_and_hint_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + import isa_decoder_pkg::*; + import support_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + //Interfaces: + uvma_rvfi_instr_if_t rvfi_if, + uvma_rvfi_csr_if_t rvfi_mcountinhibit_if, + uvma_rvfi_csr_if_t rvfi_dcsr_if, + + //Signals: + input logic rst_ni, + input logic clk_i, + input logic gated_clk_enabled, + + //CSRs: + input logic rnddummy_enabled, + input logic rndhint_enabled, + input logic [3:0] dummy_freq, + input logic [31:0][63:0] mhpmcounter, + input logic [31:0] mcountinhibit, + input logic [11:0] csr_waddr, + + //LFSR: + input logic lfsr0_seed_we, + input logic lfsr1_seed_we, + input logic lfsr2_seed_we, + input logic [31:0] lfsr0_seed, + input logic [31:0] lfsr1_seed, + input logic [31:0] lfsr2_seed, + input logic [31:0] lfsr0, + input logic [31:0] lfsr1, + input logic [31:0] lfsr2, + input logic [31:0] lfsr0_n, + input logic [31:0] lfsr1_n, + input logic [31:0] lfsr2_n, + input logic lfsr0_clk_en, + input logic lfsr1_clk_en, + input logic lfsr2_clk_en, + + //IF: + input logic if_hint, + input logic if_dummy, + input logic kill_if, + input logic ptr_in_if, + input logic if_valid, + input logic if_first_op, + + //ID: + input logic [31:0] operand_a, + input logic [31:0] operand_b, + input logic [31:0] id_instr, + input logic id_dummy, + input logic id_hint, + input logic kill_id, + input logic id_ready, + input logic id_valid, + input logic id_last_op, + + //EX: + input logic kill_ex, + input logic ex_ready, + + //WB: + input logic kill_wb, + input logic wb_dummy, + input logic wb_hint, + input logic wb_valid, + input logic [31:0] wb_instr, + + //Controller: + input logic debug_mode, + input logic stopcount_in_debug + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + + + // Local parameters: + localparam MCYCLE = 0; + localparam MINSTRET = 2; + localparam STOPCOUNT = 10; + + localparam LOCKUP_ERROR = 1'b1; + + localparam FUNCT3_ADD = 3'b000; + localparam FUNCT3_AND = 3'b111; + localparam FUNCT3_MUL = 3'b000; + localparam FUNCT3_BLTU = 3'b110; + + localparam FUNCT7_ADD = 7'b0000000; + localparam FUNCT7_AND = 7'b0000000; + localparam FUNCT7_MUL = 7'b0000001; + + localparam FUNCT3_CSRRW_IMM = 3'b101; + localparam FUNCT3_CSRRW_REG = 3'b001; + + localparam FUNCT3_COMPR_SLLI = 3'b000; + localparam OPCODE_COMPR_SLLI = 2'b10; + + localparam REGISTER_MHPMCOUNTER_MCYCLE_FULL = 64'hFFFFFFFFFFFFFFFF; + + localparam REGISTER_X0 = 5'b00000; + + localparam FREQ_SETTING_64_MIN = 4'b1000; + localparam FREQ_SETTING_64_MAX = 4'b1111; + localparam FREQ_SETTING_32_MIN = 4'b0100; + localparam logic [3:0] FREQ_SETTING_32_MAX = FREQ_SETTING_64_MIN -1; + localparam FREQ_SETTING_16_MIN = 4'b0010; + localparam logic [3:0] FREQ_SETTING_16_MAX = FREQ_SETTING_32_MIN -1; + localparam FREQ_SETTING_8_MIN = 4'b0001; + localparam logic [3:0] FREQ_SETTING_8_MAX = FREQ_SETTING_16_MIN -1; + localparam FREQ_SETTING_4_MIN = 4'b0000; + localparam logic [3:0] FREQ_SETTING_4_MAX = FREQ_SETTING_8_MIN -1; + + localparam DUMMY_INCREMENT = 0; + localparam HINT_INCREMENT = 2; + + logic gated_clk_enabled_q1; + + always @(posedge clk_i) begin + if(!rst_ni) begin + gated_clk_enabled_q1 <= 0; + end else begin + gated_clk_enabled_q1 <= gated_clk_enabled; + end + end + + logic is_wb_csr_write; + asm_t wb_instr_decoded; + asm_t id_instr_decoded; + + always_comb begin + wb_instr_decoded <= decode_instr(wb_instr); + id_instr_decoded <= decode_instr(id_instr); + is_wb_csr_write <= wb_valid && is_csr_write_spec_f(wb_instr_decoded); + end + + //Verify that dummy and hint instructions are default disabled + + property p_setting_default_off(logic setting); + $rose(rst_ni) + |-> + !setting; + endproperty + + a_xsecure_dummy_default_off: assert property ( + p_setting_default_off( + rnddummy_enabled) + ) else `uvm_error(info_tag, "Dummy instruction setting is on when exiting reset.\n"); + + a_xsecure_hint_default_off: assert property ( + p_setting_default_off( + rndhint_enabled) + ) else `uvm_error(info_tag, "Hint instruction setting is on when exiting reset.\n"); + + + //Verify that the dummy and hint features are configurable + //Features enabled: + + property p_generate_dummy_hint_instruction(feature_enabled, hint_or_dummy); + + feature_enabled + && id_valid + && hint_or_dummy; + endproperty + + c_xsecure_dummy_instr_generated_dummy_instr_if_dummy_setting_is_on: cover property( + p_generate_dummy_hint_instruction( + rnddummy_enabled, + id_dummy) + ); + + c_xsecure_hint_instr_generated_hint_instr_if_hint_setting_is_on: cover property( + p_generate_dummy_hint_instruction( + rndhint_enabled, + id_hint) + ); + + //Feature disabled: + + property p_dont_generate_dummy_hint_instruction(feature_enabled, hint_or_dummy); + + !feature_enabled + && id_valid + |-> + !hint_or_dummy; + endproperty + + a_xsecure_dummy_instr_dont_generated_dummy_instr_if_dummy_setting_is_off: assert property( + p_dont_generate_dummy_hint_instruction( + rnddummy_enabled, + id_dummy) + ) else `uvm_error(info_tag, "We generated a dummy instruction even though the dummy setting was off.\n"); + + a_xsecure_hint_instr_dont_generated_hint_instr_if_hint_setting_is_off: assert property( + p_dont_generate_dummy_hint_instruction( + rndhint_enabled, + id_hint) + ) else `uvm_error(info_tag, "We generated a hint instruction even though the hint setting was off.\n"); + + + //Verify that dummy instructions are inserted in the IF stage + + a_xsecure_dummy_instr_is_inserted_in_if_stage: assert property( + if_valid + && id_ready + + ##1 id_dummy + && id_valid + + |-> + $past(if_dummy) + ) else `uvm_error(info_tag, "The dummy instruction is not inserted in the IF stage.\n"); + + + //Verify that dummy and hint instructions are either add, and, mul, or bltu instructions + + property p_dummy_hint_instr_is_either_add_and_mul_or_bltu(id_dummy_or_hint); + + id_valid + && id_dummy_or_hint + + |-> + id_instr_decoded.instr == ADD + || id_instr_decoded.instr == AND + || id_instr_decoded.instr == MUL + || id_instr_decoded.instr == BLTU; + + endproperty + + a_xsecure_dummy_instr_is_add_and_mul_or_bltu: assert property( + p_dummy_hint_instr_is_either_add_and_mul_or_bltu( + id_dummy) + ) else `uvm_error(info_tag, "The dummy instruction is neither an ADD, MUL nor a BTLU instruction.\n"); + + a_xsecure_hint_instr_is_add_and_mul_or_bltu: assert property( + p_dummy_hint_instr_is_either_add_and_mul_or_bltu( + id_dummy) + ) else `uvm_error(info_tag, "The hint instruction is neither an ADD, MUL nor a BTLU instruction.\n"); + + + property p_dummy_hint_instr_is_add_and_or_mul(id_dummy_or_hint, instr_name); + + id_valid + && id_dummy_or_hint + + && id_instr_decoded.instr == instr_name; + + endproperty + + c_xsecure_dummy_instr_is_add: cover property( + p_dummy_hint_instr_is_add_and_or_mul( + id_dummy, + ADD) + ); + + c_xsecure_hint_instr_is_add: cover property( + p_dummy_hint_instr_is_add_and_or_mul( + id_hint, + ADD) + ); + + c_xsecure_dummy_instr_is_and: cover property( + p_dummy_hint_instr_is_add_and_or_mul( + id_dummy, + AND) + ); + + c_xsecure_hint_instr_is_and: cover property( + p_dummy_hint_instr_is_add_and_or_mul( + id_hint, + AND) + ); + + c_xsecure_dummy_instr_is_mul: cover property( + p_dummy_hint_instr_is_add_and_or_mul( + id_dummy, + MUL) + ); + + c_xsecure_hint_instr_is_mul: cover property( + p_dummy_hint_instr_is_add_and_or_mul( + id_hint, + MUL) + ); + + + property p_dummy_hint_instr_bltu(id_dummy_or_hint, instr_name); + + id_valid + && id_dummy_or_hint + + && id_instr_decoded.instr == instr_name; + endproperty + + c_xsecure_dummy_instr_is_bltu: cover property( + p_dummy_hint_instr_bltu( + id_dummy, + BLTU) + ); + + c_xsecure_hint_instr_is_btlu: cover property( + p_dummy_hint_instr_bltu( + id_hint, + BLTU) + ); + + + //Verify that the dummy and hint instructions in form of bltu operations always jump to the subsequent instruction + + property p_bltu_dummy_hint_instr_jumps_to_the_subsequent_instruction(id_dummy_or_hint, dummy_hint_increment); + + id_valid + && id_dummy_or_hint + && id_instr_decoded.instr == BLTU + + |-> + id_instr_decoded.imm.imm_value == dummy_hint_increment; + endproperty + + a_xsecure_dummy_instr_bltu_jumping: assert property( + p_bltu_dummy_hint_instr_jumps_to_the_subsequent_instruction( + id_dummy, + DUMMY_INCREMENT) //A dummy bltu instruction increment with 0 as it is an instruction inserted by the hardware itself + ) else `uvm_error(info_tag, "A dummy branch instruction does not jump to the next non-dummy instruction.\n"); + + a_xsecure_hint_instr_bltu_jumping: assert property( + p_bltu_dummy_hint_instr_jumps_to_the_subsequent_instruction( + id_hint, + HINT_INCREMENT) //A hint bltu instruction increment with 2 as it is an compressed instruction inserted in software + ) else `uvm_error(info_tag, "A hint branch instruction does not jump to the next non-hint instruction.\n"); + + + //Verify that the source for the operands to dummy and hint instructions can be either of the x0 to x32 registers + + + property p_dummy_hint_instr_rs(id_dummy_or_hint, rs, addr_rs); + + id_valid + && id_dummy_or_hint + + && rs == addr_rs; + endproperty + + for (genvar rs_addr = 0; rs_addr < 32; rs_addr++) begin + + c_xsecure_dummy_source_reg1: cover property( + p_dummy_hint_instr_rs( + id_dummy, + id_instr_decoded.rs1.gpr.raw, + rs_addr) + ); + + c_xsecure_dummy_source_reg2: cover property( + p_dummy_hint_instr_rs( + id_dummy, + id_instr_decoded.rs2.gpr.raw, + rs_addr) + ); + + c_xsecure_hint_source_reg1: cover property( + p_dummy_hint_instr_rs( + id_hint, + id_instr_decoded.rs1.gpr.raw, + rs_addr) + ); + + c_xsecure_hint_source_reg2: cover property( + p_dummy_hint_instr_rs( + id_hint, + id_instr_decoded.rs2.gpr.raw, + rs_addr) + ); + + end + + + //Verify that the source for the operands to dummy and hint instructions are fetched from the LFSR1 and LFSR2 registers, + //Or that we fetch data from the R0 register + + property p_dummy_hint_instr_operands_originate_from_lfsr1_lfsr2_or_r0(id_dummy_or_hint); + + id_valid + && id_dummy_or_hint + + |-> + ((operand_a == (lfsr1)) + || id_instr_decoded.rs1.gpr.gpr == X0) + + && ((operand_b == (lfsr2)) + || id_instr_decoded.rs2.gpr.gpr == X0); + + endproperty + + a_xsecure_dummy_instr_operands_from_lfsr1_lfsr2_or_r0: assert property ( + p_dummy_hint_instr_operands_originate_from_lfsr1_lfsr2_or_r0( + id_dummy) + ) else `uvm_error(info_tag, "Dummy instruction does not fetch data from LFSR1 and LFSR2.\n"); + + a_xsecure_hint_instr_operands_from_lfsr1_lfsr2_or_r0: assert property ( + p_dummy_hint_instr_operands_originate_from_lfsr1_lfsr2_or_r0( + id_hint) + ) else `uvm_error(info_tag, "Hint instruction does not fetch data from LFSR1 and LFSR2.\n"); + + + + //Verify that the destination register of dummy and hint instructions are R0 + + property p_dummy_hint_destination_is_r0(id_dummy_or_hint); + + id_valid + && id_dummy_or_hint + && id_instr_decoded.instr != BLTU //branch instructions do not use a destination register + + |-> + id_instr_decoded.rd.gpr.gpr == X0; + endproperty + + + a_xsecure_dummy_instr_destination_is_r0: assert property ( + p_dummy_hint_destination_is_r0(id_dummy) + ) else `uvm_error(info_tag, "The result of a dummy instruction is not stored in the x0 GPR.\n"); + + a_xsecure_hint_instr_destination_is_r0: assert property ( + p_dummy_hint_destination_is_r0(id_hint) + ) else `uvm_error(info_tag, "The result of a hint instruction is not stored in the x0 GPR.\n"); + + + + //Verify that the LFSR registers are updated if a dummy or hint instruction is executed + + property p_dummy_hint_update_lfsr0(is_dummy_or_hint, lfsr); + + //Make sure we detect a dummy/hint instruction + is_dummy_or_hint + && if_valid + && id_ready + + |=> + + lfsr != $past(lfsr); + endproperty + + + a_xsecure_dummy_updates_lfsr0: assert property ( + p_dummy_hint_update_lfsr0( + if_dummy, + lfsr0) + ) else `uvm_error(info_tag, "A dummy instruction does not update the LFSR0 register.\n"); + + a_xsecure_hint_updates_lfsr0: assert property ( + p_dummy_hint_update_lfsr0( + if_hint, + lfsr0) + ) else `uvm_error(info_tag, "A hint instruction does not update the LFSR0 register.\n"); + + + property p_dummy_hint_update_lfsr1_lfsr2(is_dummy_or_hint, lfsr); + + //Make sure we detect a dummy/hint instruction + is_dummy_or_hint + && id_valid + && ex_ready + && id_last_op + + |=> + lfsr != $past(lfsr); + endproperty + + + a_xsecure_dummy_updates_lfsr1: assert property ( + p_dummy_hint_update_lfsr1_lfsr2( + id_dummy, + lfsr1) + ) else `uvm_error(info_tag, "A dummy instruction does not update the LFSR1 register.\n"); + + a_xsecure_dummy_updates_lfsr2: assert property ( + p_dummy_hint_update_lfsr1_lfsr2( + id_dummy, + lfsr2) + ) else `uvm_error(info_tag, "A dummy instruction does not update the LFSR2 register.\n"); + + a_xsecure_hint_updates_lfsr1: assert property ( + p_dummy_hint_update_lfsr1_lfsr2( + id_hint, + lfsr1) + ) else `uvm_error(info_tag, "A hint instruction does not update the LFSR1 register.\n"); + + a_xsecure_hint_updates_lfsr2: assert property ( + p_dummy_hint_update_lfsr1_lfsr2( + id_hint, + lfsr2) + ) else `uvm_error(info_tag, "A hint instruction does not update the LFSR2 register.\n"); + + + //Verify that the source registers of the dummy and hint instructions generate pipeline stalls as normal + + //If a load instruction set a value in rd=rd_load, and the source register of the next instruction is rs=rd_load, + //then the next instruction must wait in id stage untill rd_load is set. This also account for dummy and hint instructions. + //The assertions below state that this is true for dummy and hint instruction by verifying that if there is a dummy/hint + //instruction in wb stage when there is a load instruction in the rvfi stage, the dummy/hint instruction does not have rs=rd_load + + a_xsecure_dummy_instr_load_dummy_stall: assert property ( + + rvfi_if.rvfi_valid + && !rvfi_if.rvfi_trap + && rvfi_if.rvfi_insn[6:0] == OPCODE_LOAD + && rvfi_if.rvfi_rd1_addr != '0 + + && wb_dummy + && wb_valid + + |-> + wb_instr[24:20] != rvfi_if.rvfi_rd1_addr + && wb_instr[19:15] != rvfi_if.rvfi_rd1_addr + ) else `uvm_error(info_tag, "A dummy instruction does not stall in ID stage even though the value of a source register is not fetched from memory yet.\n"); + + + property p_load_stall_for_hints; + logic [4:0] id_hint_rs1; + logic [4:0] id_hint_rs2; + + //Make sure the instruction propegates through the pipeline + (!kill_if + & !kill_id + & !kill_ex + & !kill_wb + ) throughout ( + + (id_hint + && id_valid + && ex_ready, + + id_hint_rs1 = id_instr_decoded.rs1.gpr.raw, + id_hint_rs2 = id_instr_decoded.rs2.gpr.raw) + + ##0 first_match(##[2:$] + wb_hint + && wb_valid) + + ##0 rvfi_if.rvfi_valid + && !rvfi_if.rvfi_trap + && rvfi_if.rvfi_insn[6:0] == OPCODE_LOAD + && rvfi_if.rvfi_rd1_addr != '0 + ) + + |-> + id_hint_rs1 != rvfi_if.rvfi_rd1_addr + && id_hint_rs2 != rvfi_if.rvfi_rd1_addr; + endproperty + + a_xsecure_hint_instr_load_hint_stall: assert property ( + p_load_stall_for_hints + ) else `uvm_error(info_tag, "A hint instruction does not stall in ID stage even though the value of a source register is not fetched from memory yet.\n"); + + + //Verify that both the dummy and the hint instructions update mcycle + + a_xsecure_dummy_instr_updates_mcycle: assert property ( + + !stopcount_in_debug + && !(csr_waddr == cv32e40s_pkg::CSR_MCYCLE || csr_waddr == cv32e40s_pkg::CSR_MCYCLEH) //Writing to the register can give unsequential behavior + + ##1 gated_clk_enabled_q1 //mcycle is only updated when the gated clock is active + && !mcountinhibit[MCYCLE] //mcycle is operative (not inhibited) + + |-> + mhpmcounter[MCYCLE] == ($past(mhpmcounter[MCYCLE]) + 1) //mcycle should count every clock cycle, including the clock cycles used by dummy and hint instructions + or mhpmcounter[MCYCLE] == '0 && $past(mhpmcounter[MCYCLE]) == REGISTER_MHPMCOUNTER_MCYCLE_FULL //Reset + or mhpmcounter[MCYCLE] == $past(mhpmcounter[MCYCLE]) && $past(mcountinhibit[MCYCLE]) //Allow the first mcycle count to not increment + + ) else `uvm_error(info_tag, "Dummy and hint instructions do not update the MCYCLE register.\n"); + + + + //Verify that dummy instructions do not update minstret + + a_xsecure_dummy_instr_do_not_update_minstret: assert property ( + + !mcountinhibit[MINSTRET] //minstret is operative (not inhibited) + && wb_valid + && wb_dummy + + |=> + mhpmcounter[MINSTRET] == $past(mhpmcounter[MINSTRET]) + + ) else `uvm_error(info_tag, "Dummy instruction updated the minstret register.\n"); + + + + //Verify that hint instructions update minstret + + a_xsecure_hint_instructions_updates_minstret: assert property ( + + !rvfi_mcountinhibit_if.rvfi_csr_rdata[MINSTRET] //minstret was operative (not inhibited) + && (!rvfi_dcsr_if.rvfi_csr_rdata[STOPCOUNT] || !rvfi_if.rvfi_dbg_mode) //the minstret counter was not stopped + + && rvfi_if.rvfi_valid + && !rvfi_if.rvfi_trap.trap + + //Hint instruction: + && rvfi_if.is_cslli + && rvfi_if.rvfi_rd1_addr == REGISTER_X0 + && rvfi_if.cslli_shamt != '0 + + |-> + mhpmcounter[MINSTRET] == $past(mhpmcounter[MINSTRET]) + 1 + + ) else `uvm_error(info_tag, "Hint instruction did not update the minstret register.\n"); + + + //Verify that dummy instructions appears within specifyed frequency + + //There is at least one dummy instruction for every valid instructions + sequence seq_dummy_instr_within_normal_valid_instructions (num_valid_instructions); + @(posedge clk_i) + + // Reset the checker every time we see a dummy instruction + first_match(if_dummy) + within + // Within n+1 issued instruction, there should be a dummy instruction (dummy counts as issued) + (if_valid && if_first_op && id_ready && !ptr_in_if)[->0:(num_valid_instructions + 1)]; + endsequence + + property p_xsecure_dummy_instr_frequency(num_normal_valid_instructions_per_dummy_instruction, logic [3:0] rnddummyfreq_reg_value_min, logic [3:0] rnddummyfreq_reg_value_max); + disable iff ( + !rnddummy_enabled + || dummy_freq < rnddummyfreq_reg_value_min + || dummy_freq > rnddummyfreq_reg_value_max + || debug_mode + || is_wb_csr_write && wb_instr_decoded.csr.address.name inside { CPUCTRL, SECURESEED0 } + ) + + // This should always hold, unless disabled by any of the clauses in the disable iff-statement above + seq_dummy_instr_within_normal_valid_instructions(num_normal_valid_instructions_per_dummy_instruction); + endproperty + + + a_xsecure_dummy_instr_frequency_4: assert property ( + p_xsecure_dummy_instr_frequency( + 4, + FREQ_SETTING_4_MIN, + FREQ_SETTING_4_MAX) + ) else `uvm_error(info_tag, "There is not 1 dummy instruction per 1-4 instructions.\n"); + + a_xsecure_dummy_instr_frequency_8: assert property ( + p_xsecure_dummy_instr_frequency( + 8, + FREQ_SETTING_8_MIN, + FREQ_SETTING_8_MAX) + ) else `uvm_error(info_tag, "There is not 1 dummy instruction per 1-8 instructions.\n"); + + a_xsecure_dummy_instr_frequency_16: assert property ( + p_xsecure_dummy_instr_frequency( + 16, + FREQ_SETTING_16_MIN, + FREQ_SETTING_16_MAX) + ) else `uvm_error(info_tag, "There is not 1 dummy instruction per 1-16 instructions.\n"); + + a_xsecure_dummy_instr_frequency_32: assert property ( + p_xsecure_dummy_instr_frequency( + 32, + FREQ_SETTING_32_MIN, + FREQ_SETTING_32_MAX) + ) else `uvm_error(info_tag, "There is not 1 dummy instruction per 1-32 instructions.\n"); + + a_xsecure_dummy_instr_frequency_64: assert property ( + p_xsecure_dummy_instr_frequency( + 64, + FREQ_SETTING_64_MIN, + FREQ_SETTING_64_MAX) + ) else `uvm_error(info_tag, "There is not 1 dummy instruction per 1-64 instructions.\n"); + + + //Verify that the LFSR's seeds are reset when lockups are detected + + sequence seq_xsecure_dummy_hint_instr_LFSRx_lockup_detection(logic get_new_lfsr_value, logic seed_we, logic [31:0] seed_w_value, logic [31:0] lfsr_n); + + (rnddummy_enabled || rndhint_enabled) + && get_new_lfsr_value + && ((!seed_we && lfsr_n == '0) + || (seed_we && seed_w_value == '0)); + endsequence + + + a_xsecure_dummy_hint_instr_LFSR0_lockup_reset: assert property ( + seq_xsecure_dummy_hint_instr_LFSRx_lockup_detection( + lfsr0_clk_en, + lfsr0_seed_we, + lfsr0_seed, + lfsr0_n) + + |=> + + lfsr0 == CORE_PARAM_LFSR0_CFG[31:0] + ) else `uvm_error(info_tag, "LFSR0 does not reset to the default value when there is a lookup error (given that we do not write to the LFSR register).\n"); + + + a_xsecure_dummy_hint_instr_LFSR1_lockup_reset: assert property ( + seq_xsecure_dummy_hint_instr_LFSRx_lockup_detection( + lfsr1_clk_en, + lfsr1_seed_we, + lfsr1_seed, + lfsr1_n) + + |=> + + lfsr1 == CORE_PARAM_LFSR1_CFG[31:0] + + ) else `uvm_error(info_tag, "LFSR0 does not reset to the default value when there is a lookup error (given that we do not write to the LFSR register).\n"); + + + a_xsecure_dummy_hint_instr_LFSR2_lockup_reset: assert property ( + seq_xsecure_dummy_hint_instr_LFSRx_lockup_detection( + lfsr2_clk_en, + lfsr2_seed_we, + lfsr2_seed, + lfsr2_n) + + |=> + + lfsr2 == CORE_PARAM_LFSR2_CFG[31:0] + ) else `uvm_error(info_tag, "LFSR2 does not reset to the default value when there is a lookup error (given that we do not write to the LFSR register).\n"); + + + + //Verify that we can write the value of the LFSRs by writing to the secureseed CSRs + + property p_write_LFSR_by_writing_to_the_secureseed(csr_addr_secureseed, lfsr); + + rvfi_if.rvfi_valid + && !rvfi_if.rvfi_trap + + && rvfi_if.rvfi_insn[6:0] == OPCODE_SYSTEM + && rvfi_if.rvfi_insn[14:12] == FUNCT3_CSRRW_REG + && rvfi_if.rvfi_insn[31:20] == csr_addr_secureseed + && rvfi_if.rvfi_rs1_rdata != 5'b0000_0 + + |-> + lfsr == rvfi_if.rvfi_rs1_rdata; + endproperty + + + a_xsecure_dummy_hint_instr_LFSR0_write_secureseed0_reg: assert property ( + p_write_LFSR_by_writing_to_the_secureseed( + CSR_SECURESEED0, + lfsr0) + ) else `uvm_error(info_tag, "The LFSR0 register is not written to, even though the secureseed CSR is written to (CSR register instruction).\n"); + + a_xsecure_dummy_hint_instr_LFSR1_write_secureseed1_reg: assert property ( + p_write_LFSR_by_writing_to_the_secureseed( + CSR_SECURESEED1, + lfsr1) + ) else `uvm_error(info_tag, "The LFSR1 register is not written to, even though the secureseed CSR is written to (CSR register instruction).\n"); + + a_xsecure_dummy_hint_instr_LFSR2_write_secureseed2_reg: assert property ( + p_write_LFSR_by_writing_to_the_secureseed( + CSR_SECURESEED2, + lfsr2) + ) else `uvm_error(info_tag, "The LFSR2 register is not written to, even though the secureseed CSR is written to (CSR register instruction).\n"); + + + //Verify that hint instructions appears as slt instructions on RVFI + + a_xsecure_hint_instructions_reports_on_rvfi_as_slli: assert property ( + + wb_hint + && wb_valid + + ##1 rvfi_if.rvfi_valid + + |-> + //The hint instruction shall appear as a c.slli instruction with rd=x0 and shamt != 0 + (rvfi_if.is_cslli + && rvfi_if.rvfi_rd1_addr == REGISTER_X0 + && rvfi_if.cslli_shamt != '0) + || !rvfi_if.is_instr_bus_valid + + ) else `uvm_error(info_tag, "Hint instruction do not appears as a c.slli instruction with rd=x0 and shamt != 0 on RVFI.\n"); + + + endmodule : uvmt_cv32e40s_xsecure_dummy_and_hint_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_assert.sv new file mode 100644 index 0000000000..e133c2c03e --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_assert.sv @@ -0,0 +1,194 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_hardened_csrs_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + + input rst_ni, + input clk_i, + + //Alert: + input logic alert_major, + + //CSRs: + input logic [31:0] mstateen0, + input [$bits(privlvl_t)-1:0] priv_lvl, + input jvt_t jvt, + input mstatus_t mstatus, + input cpuctrl_t cpuctrl, + input dcsr_t dcsr, + input logic [31:0] mepc, + input logic [31:0] mscratch, + + //Shadows: + input logic [31:0] mstateen0_shadow, + input logic [$bits(privlvl_t)-1:0] priv_lvl_shadow, + input logic [$bits(jvt_t)-1:0] jvt_shadow, + input logic [$bits(mstatus_t)-1:0] mstatus_shadow, + input logic [$bits(cpuctrl_t)-1:0] cpuctrl_shadow, + input logic [$bits(dcsr_t)-1:0] dcsr_shadow, + input logic [31:0] mepc_shadow, + input logic [31:0] mscratch_shadow + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + + + //Verify that the following CSRs have bit-wise complemented shadows + + property p_hardened_csr(csr, shadow); + csr == ~shadow; + endproperty + + + //MSTATEEN0 + a_xsecure_hardened_csr_mstateen0: assert property ( + p_hardened_csr( + mstateen0, + mstateen0_shadow) + ) else `uvm_error(info_tag, "The CSR MSTATEEN0 is not shadowed.\n"); + + //PRIVILEGE LEVEL + a_xsecure_hardened_csr_privlvl: assert property ( + p_hardened_csr( + priv_lvl, + priv_lvl_shadow) + ) else `uvm_error(info_tag, "The priviliged level is not shadowed.\n"); + + //JVT + a_xsecure_hardened_csr_jvt: assert property ( + p_hardened_csr( + jvt, + jvt_shadow) + ) else `uvm_error(info_tag, "The CSR JVT is not shadowed.\n"); + + //MSTATUS + a_xsecure_hardened_csr_mstatus: assert property ( + p_hardened_csr( + mstatus, + mstatus_shadow) + ) else `uvm_error(info_tag, "The CSR MSTATUS is not shadowed.\n"); + + //CPUCTRL + a_xsecure_hardened_csr_cpuctrl: assert property ( + p_hardened_csr( + cpuctrl, + cpuctrl_shadow) + ) else `uvm_error(info_tag, "The CSR CPUCTRL is not shadowed.\n"); + + //DCSR + a_xsecure_hardened_csr_dcsr: assert property ( + p_hardened_csr( + dcsr, + dcsr_shadow) + ) else `uvm_error(info_tag, "The CSR DCSR is not shadowed.\n"); + + //MEPC + a_xsecure_hardened_csr_mepc: assert property ( + p_hardened_csr( + mepc, + mepc_shadow) + ) else `uvm_error(info_tag, "The CSR MEPC is not shadowed.\n"); + + //MSCRATCH (which includes MSCRATCHCSW and MSCRATCHCSWL) + a_xsecure_hardened_csr_mscratch: assert property ( + p_hardened_csr( + mscratch, + mscratch_shadow) + ) else `uvm_error(info_tag, "The CSR MSCRATCH is not shadowed.\n"); + + + + //Verify that mismatch between the following CSRs and their shadows set alert major + + property p_hardened_csr_mismatch_sets_major_alert(csr, shadow); + + shadow != ~csr + |=> + alert_major; + endproperty + + + //MSTATEEN0 + a_glitch_xsecure_hardened_csr_mismatch_mstateen0: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mstateen0, + mstateen0_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MSTATEEN0 and its shadow does not set the major alert.\n"); + + //PRIVILEGE LEVEL + a_glitch_xsecure_hardened_csr_mismatch_privlvl: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + priv_lvl, + priv_lvl_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the priviliged level and its shadow does not set the major alert.\n"); + + //JVT + a_glitch_xsecure_hardened_csr_mismatch_jvt: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + jvt, + jvt_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR JVT and its shadow does not set the major alert.\n"); + + //MSTATUS + a_glitch_xsecure_hardened_csr_mismatch_mstatus: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mstatus, + mstatus_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MSTATUS and its shadow does not set the major alert.\n"); + + //CPUCTRL + a_glitch_xsecure_hardened_csr_mismatch_cpuctrl: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + cpuctrl, + cpuctrl_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR CPUCTRL and its shadow does not set the major alert.\n"); + + //DCSR + a_glitch_xsecure_hardened_csr_mismatch_dcsr: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + dcsr, + dcsr_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR DCSR and its shadow does not set the major alert.\n"); + + //MEPC + a_glitch_xsecure_hardened_csr_mismatch_mepc: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mepc, + mepc_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MEPC and its shadow does not set the major alert.\n"); + + //MSCRATCH + a_glitch_xsecure_hardened_csr_mismatch_mscratch: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mscratch, + mscratch_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MSCRATCH and its shadow does not set the major alert.\n"); + + + endmodule : uvmt_cv32e40s_xsecure_hardened_csrs_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert.sv new file mode 100644 index 0000000000..0672a8d28c --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert.sv @@ -0,0 +1,144 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + + input rst_ni, + input clk_i, + + //Alert: + input logic alert_major, + + //CSRs: + input mcause_t mcause, + input mtvt_t mtvt, + input mtvec_t mtvec, + input mintstatus_t mintstatus, + input logic [31:0] mintthresh, + + //Shadows: + input logic [$bits(mcause_t)-1:0] mcause_shadow, + input logic [$bits(mtvt_t)-1:0] mtvt_shadow, + input logic [$bits(mtvec_t)-1:0] mtvec_shadow, + input logic [$bits(mintstatus_t)-1:0] mintstatus_shadow, + input logic [31:0] mintthresh_shadow + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + + + //Verify that the following CSRs have bit-wise complemented shadows + + property p_hardened_csr(csr, shadow); + csr == ~shadow; + endproperty + + //MCAUSE + a_xsecure_hardened_csr_mcause: assert property ( + p_hardened_csr( + mcause, + mcause_shadow) + ) else `uvm_error(info_tag, "The CSR MCAUSE is not shadowed.\n"); + + //MTVT + a_xsecure_hardened_csr_mtvt: assert property ( + p_hardened_csr( + mtvt, + mtvt_shadow) + ) else `uvm_error(info_tag, "The CSR MTVT is not shadowed.\n"); + + //MTVEC + a_xsecure_hardened_csr_mtvec: assert property ( + p_hardened_csr( + mtvec, + mtvec_shadow) + ) else `uvm_error(info_tag, "The CSR MTVEC is not shadowed.\n"); + + //MINTSTATUS + a_xsecure_hardened_csr_mintstatus: assert property ( + p_hardened_csr( + mintstatus, + mintstatus_shadow) + ) else `uvm_error(info_tag, "The CSR MINTSTATUS is not shadowed.\n"); + + //MINTTHRESH + a_xsecure_hardened_csr_mintthresh: assert property ( + p_hardened_csr( + mintthresh, + mintthresh_shadow) + ) else `uvm_error(info_tag, "The CSR MINTTHRESH is not shadowed.\n"); + + + //Verify that mismatch between the following CSRs and their shadows set alert major + + property p_hardened_csr_mismatch_sets_major_alert(csr, shadow); + + shadow != ~csr + |=> + alert_major; + + endproperty + + //MCAUSE + a_glitch_xsecure_hardened_csr_mismatch_mcause: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mcause, + mcause_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MCAUSE and its shadow does not set the major alert.\n"); + + //MTVT + a_glitch_xsecure_hardened_csr_mismatch_mtvt: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mtvt, + mtvt_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MTVT and its shadow does not set the major alert.\n"); + + //MTVEC + a_glitch_xsecure_hardened_csr_mismatch_mtvec: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mtvec, + mtvec_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MTVEC and its shadow does not set the major alert.\n"); + + //MINTSTATUS + a_glitch_xsecure_hardened_csr_mismatch_mintstatus: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mintstatus, + mintstatus_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MINTSTATUS and its shadow does not set the major alert.\n"); + + //MINTTHRESH + a_glitch_xsecure_hardened_csr_mismatch_mintthresh: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mintthresh, + mintthresh_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MINTTHRESH and its shadow does not set the major alert.\n"); + + + endmodule : uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert.sv new file mode 100644 index 0000000000..2909590ad5 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert.sv @@ -0,0 +1,112 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + + input rst_ni, + input clk_i, + + //Alert: + input logic alert_major, + + //CSRs: + input mcause_t mcause, + input logic [31:0] mie, + input mtvec_t mtvec, + + //Shadows: + input logic [$bits(mcause_t)-1:0] mcause_shadow, + input logic [31:0] mie_shadow, + input logic [$bits(mtvec_t)-1:0] mtvec_shadow + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + + + //Verify that the following CSRs have bit-wise complemented shadows + + property p_hardened_csr(csr, shadow); + csr == ~shadow; + endproperty + + //MCAUSE + a_xsecure_hardened_csr_mcause: assert property ( + p_hardened_csr( + mcause, + mcause_shadow) + ) else `uvm_error(info_tag, "The CSR MCAUSE is not shadowed.\n"); + + //MTVEC + a_xsecure_hardened_csr_mtvec: assert property ( + p_hardened_csr( + mtvec, + mtvec_shadow) + ) else `uvm_error(info_tag, "The CSR MTVEC is not shadowed.\n"); + + //MIE + a_xsecure_hardened_csr_mie: assert property ( + p_hardened_csr( + mie, + mie_shadow) + ) else `uvm_error(info_tag, "The CSR MIE is not shadowed.\n"); + + + //Verify that mismatch between the following CSRs and their shadows set alert major + + property p_hardened_csr_mismatch_sets_major_alert(csr, shadow); + + shadow != ~csr + |=> + alert_major; + + endproperty + + //MCAUSE + a_glitch_xsecure_hardened_csr_mismatch_mcause: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mcause, + mcause_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MCAUSE and its shadow does not set the major alert.\n"); + + //MTVEC + a_glitch_xsecure_hardened_csr_mismatch_mtvec: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mtvec, + mtvec_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MTVEC and its shadow does not set the major alert.\n"); + + //MIE + a_glitch_xsecure_hardened_csr_mismatch_mie: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + mie, + mie_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MIE and its shadow does not set the major alert.\n"); + + + endmodule : uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert.sv new file mode 100644 index 0000000000..91175252c4 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert.sv @@ -0,0 +1,127 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1, + parameter int PMP_ADDR_WIDTH = 32, + parameter int PMP_NUM_REGIONS = 2 + ) + ( + + input rst_ni, + input clk_i, + + //Alert: + input logic alert_major, + + //CSRs: + input mseccfg_t pmp_mseccfg, + input pmpncfg_t pmpncfg[PMP_NUM_REGIONS], + input logic [PMP_ADDR_WIDTH-1:0] pmp_addr[PMP_NUM_REGIONS], + + //Shadows: + input logic [$bits(mseccfg_t)-1:0] pmp_mseccfg_shadow, + input logic [$bits(pmpncfg_t)-1:0] pmpncfg_shadow[PMP_NUM_REGIONS], + input logic [PMP_ADDR_WIDTH-1:0] pmp_addr_shadow[PMP_NUM_REGIONS] + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + + + //Verify that the following CSRs have bit-wise complemented shadows + + property p_hardened_csr(csr, shadow); + csr == ~shadow; + endproperty + + //MSECCFG + a_xsecure_hardened_csr_mseccfg: assert property ( + p_hardened_csr( + pmp_mseccfg, + pmp_mseccfg_shadow) + ) else `uvm_error(info_tag, "The CSR MSECCFG is not shadowed.\n"); + + generate + for (genvar n = 0; n < PMP_NUM_REGIONS; n++) begin + + //PMPNCFG + a_xsecure_hardened_csr_pmpncfg: assert property ( + p_hardened_csr( + pmpncfg[n], + pmpncfg_shadow[n]) + ) else `uvm_error(info_tag, $sformatf("The CSR PMP%0dCFG is not shadowed.\n", n)); + + //PMPADDR + a_xsecure_hardened_csr_pmpaddr: assert property ( + p_hardened_csr( + pmp_addr[n], + pmp_addr_shadow[n]) + ) else `uvm_error(info_tag, $sformatf("The CSR PMPADDR[%0d] is not shadowed.\n", n)); + + end + endgenerate + + + //Verify that mismatch between the following CSRs and their shadows set alert major + + property p_hardened_csr_mismatch_sets_major_alert(csr, shadow); + + shadow != ~csr + |=> + alert_major; + + endproperty + + + //MSECCFG + a_glitch_xsecure_hardened_csr_mismatch_mseccfg: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + pmp_mseccfg, + pmp_mseccfg_shadow) + ) else `uvm_error(info_tag_glitch, "A mismatch between the CSR MSECCFG and its shadow does not set the major alert.\n"); + + generate + for (genvar n = 0; n < PMP_NUM_REGIONS; n++) begin + + //PMPNCFG + a_glitch_xsecure_hardened_csr_mismatch_pmpncfg: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + pmpncfg[n], + pmpncfg_shadow[n]) + ) else `uvm_error(info_tag_glitch, $sformatf("A mismatch between the CSR PMP%0dCFG and its shadow does not set the major alert.\n", n)); + + //PMPADDR + a_glitch_xsecure_hardened_csr_mismatch_pmpaddr: assert property ( + p_hardened_csr_mismatch_sets_major_alert( + pmp_addr[n], + pmp_addr_shadow[n]) + ) else `uvm_error(info_tag_glitch, $sformatf("A mismatch between the CSR PMPADDR[%0d] and its shadow does not set the major alert.\n", n)); + + end + endgenerate + + + endmodule : uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_pc_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_pc_assert.sv new file mode 100644 index 0000000000..fdd75c571d --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_hardened_pc_assert.sv @@ -0,0 +1,349 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_hardened_pc_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + //Signals: + input clk_i, + input rst_ni, + + //CSRs: + input logic pc_hardening_enabled, + input logic dataindtiming_enabled, + + //Alert: + input logic alert_major_due_to_pc_err, + + //IF: + input logic if_valid, + input logic ptr_in_if, + input logic if_instr_cmpr, + input logic [31:0] if_pc, + input logic dummy_insert, + + //ID: + input logic id_ready, + input logic [31:0] id_pc, + input logic id_last_op, + input logic id_first_op, + input logic jump_in_id, + input logic kill_id, + input logic halt_id, + + //EX: + input logic ex_first_op, + input logic branch_in_ex, + input logic kill_ex, + input logic halt_ex, + + //Controll signals: + input logic pc_set, + input logic [3:0] pc_mux, + + //Signals to glitch check: + input logic [31:0] branch_target, + input logic branch_decision, + input logic [31:0] jump_target, + input logic [31:0] mepc + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + + + // Local parameters: + localparam JUMP = 4'b0100; + localparam MRET = 4'b0001; + + localparam INSTRUCTION_INCREMENT = 4; + localparam INSTR_INCREMENT_CMPR = 2; + + + //Verify that pc hardening is enabled by default + + a_xsecure_pc_hardening_default_on: assert property ( + $rose(rst_ni) + |-> + pc_hardening_enabled + ) else `uvm_error(info_tag, "PC hardening is not enabled when exiting reset.\n"); + + + //Verify that the PC increment correctly when there is no PC jumping + + //Make sure the PC of ID and IF stage is equal when there is a dummy instruction in the ID stage + sequence seq_equal_if_id_pc_if_dummy_instr; + @(posedge clk_i) + + dummy_insert + + ##1 (if_pc == id_pc)[*1:$]; + endsequence + + sequence seq_pc_initialization; + @(posedge clk_i) + + $rose(rst_ni) + + ##0 (!if_pc && !id_pc)[*1:$]; + endsequence + + + //Make sure the PC, which is set due to a PC jump, is stable in the IF stage until it is forwarded to the id stage + sequence seq_pc_set_stable; + @(posedge clk_i) + + pc_set + + //(Uses ##2 because: in the first cycle the PC is set, and in the second cycle the PC is stable + ##2 $stable(if_pc)[*1:$]; + endsequence + + + a_xsecure_pc_hardening: assert property ( + + pc_hardening_enabled + && $past(if_valid) + && $past(id_ready) + + && !$past(ptr_in_if) // pointers insert a non-incremental PC + + |-> + + if_pc == id_pc + INSTR_INCREMENT_CMPR && $past(if_instr_cmpr) + or if_pc == id_pc + INSTRUCTION_INCREMENT && $past(!if_instr_cmpr) + + or seq_pc_initialization.triggered + or if_pc == if_pc && !id_last_op + or seq_equal_if_id_pc_if_dummy_instr.triggered + or $past(pc_set) + or seq_pc_set_stable.triggered + + ) else `uvm_error(info_tag, "There is a PC fault in the IF stage.\n"); + + + //Verify that the major alert is set due to pc hardening fault when the PC is incremented wrongly, when there is no PC jumping and the PC hardening feature is enabled + + sequence seq_unexpected_behavior; + @(posedge clk_i) + + $past(if_valid) + && $past(id_ready) + + && !$past(ptr_in_if) // pointers insert a non-incremental PC + + and !(if_pc == id_pc + INSTR_INCREMENT_CMPR && $past(if_instr_cmpr)) + and !(if_pc == id_pc + INSTRUCTION_INCREMENT && $past(!if_instr_cmpr)) + + and !(seq_pc_initialization.triggered) + and !(if_pc == if_pc && !id_last_op) + and !(seq_equal_if_id_pc_if_dummy_instr.triggered) + and !(seq_pc_set_stable.triggered) + and !($past(pc_set)); + + endsequence + + + a_glitch_xsecure_pc_hardening_sequential_instruction_hardening_enabled: assert property ( + + pc_hardening_enabled + + ##0 seq_unexpected_behavior + + |-> + alert_major_due_to_pc_err + + ) else `uvm_error(info_tag_glitch, "A PC fault in the IF stage does not set the major alert when PC hardening is on.\n"); + + + //Verify that the major alert is not set due to pc hardening fault when the PC is incremented wrongly, when there is no PC jumping and the PC hardening feature is disabled + + a_glitch_xsecure_pc_hardening_sequential_instruction_hardening_disabled: assert property ( + + !pc_hardening_enabled + + ##0 seq_unexpected_behavior + + |-> + !alert_major_due_to_pc_err + + ) else `uvm_error(info_tag_glitch, "A PC fault in the IF stage does set the major alert when PC hardening is off.\n"); + + + //Verify that the major alert is set due to pc hardening fault when the PC target of a jump instruction or a branch decision is unstable, and the PC hardening feature is enabled + + sequence seq_non_hardened_jump(kill, halt, instr, first_op, jump_addr); + + (!kill && !halt) throughout + + ((instr && $rose(first_op)) + || ($rose(instr) && first_op)) + + && pc_set + ##1 instr + && jump_addr != $past(jump_addr); + endsequence + + + a_glitch_xsecure_pc_hardening_branch_hardening_enabled: assert property( + + pc_hardening_enabled + + ##0 seq_non_hardened_jump( + kill_ex, + halt_ex, + branch_in_ex, + ex_first_op, + branch_target) + |-> + alert_major_due_to_pc_err + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed branch instruction does not set the major alert.\n"); + + + a_glitch_xsecure_pc_hardening_jump_hardening_enabled: assert property( + + pc_hardening_enabled + && pc_mux == JUMP + + ##0 seq_non_hardened_jump( + kill_id, + halt_id, + jump_in_id, + id_first_op, + jump_target) + |-> + alert_major_due_to_pc_err + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed jump instruction does not set the major alert.\n"); + + + a_glitch_xsecure_pc_hardening_mret_hardening_enabled: assert property( + + pc_hardening_enabled + && pc_mux == MRET + + ##0 seq_non_hardened_jump( + kill_id, + halt_id, + jump_in_id, + id_first_op, + mepc) + |-> + alert_major_due_to_pc_err + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed mret instruction does not set the major alert.\n"); + + + a_glitch_xsecure_pc_hardening_branch_decision_hardening_enabled: assert property( + + pc_hardening_enabled + && !dataindtiming_enabled //Make sure the branch decision is not always taken + + ##0 seq_non_hardened_jump( + kill_ex, + halt_ex, + branch_in_ex, + ex_first_op, + branch_decision) + + |-> + + alert_major_due_to_pc_err //Decision is first untaken then taken + || $past(alert_major_due_to_pc_err) //Decision is first taken than untaken + + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed branch decision does not set the major alert.\n"); + + + //Verify that the major alert is set due to pc hardening fault when the PC target of a jump instruction or a branch decision is unstable, and the PC hardening feature is disabled + + a_glitch_xsecure_pc_hardening_branch_hardening_disabled: assert property( + + !pc_hardening_enabled + + ##0 seq_non_hardened_jump( + kill_ex, + halt_ex, + branch_in_ex, + ex_first_op, + branch_target) + |-> + !alert_major_due_to_pc_err + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed branch instruction (jump location) sets the major alert even though PC hardening is off.\n"); + + + a_glitch_xsecure_pc_hardening_jump_hardening_disabled: assert property( + + !pc_hardening_enabled + && pc_mux == JUMP + + ##0 seq_non_hardened_jump( + kill_id, + halt_id, + jump_in_id, + id_first_op, + jump_target) + + |-> + !alert_major_due_to_pc_err + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed jump instruction sets the major alert even though PC hardening is off.\n"); + + a_glitch_xsecure_pc_hardening_mret_hardening_disabled: assert property( + + !pc_hardening_enabled + + && pc_mux == MRET + + ##0 seq_non_hardened_jump( + kill_id, + halt_id, + jump_in_id, + id_first_op, + mepc) + + |-> + !alert_major_due_to_pc_err + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed mret instruction sets the major alert even though PC hardening is off.\n"); + + + a_glitch_xsecure_pc_hardening_branch_decision_hardening_disabled: assert property( + + !pc_hardening_enabled + && !dataindtiming_enabled //Make sure the branch decision is not always taken + + ##0 seq_non_hardened_jump( + kill_ex, + halt_ex, + branch_in_ex, + ex_first_op, + branch_decision) + + |-> + + !alert_major_due_to_pc_err //Decision is first untaken then taken + && !$past(alert_major_due_to_pc_err) //Decision is first taken than untaken + + ) else `uvm_error(info_tag_glitch, "Mismatch between the computed and the recomputed branch instruction (decision calculation) sets the major alert even though PC hardening is off.\n"); + + + endmodule : uvmt_cv32e40s_xsecure_hardened_pc_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv new file mode 100644 index 0000000000..68480736fa --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv @@ -0,0 +1,727 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_interface_integrity_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + #( + parameter int SECURE = 1, + parameter int ALBUF_DEPTH = 3, + parameter int ALBUF_CNT_WIDTH = 2 + ) + ( + //Interfaces: + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if, + + //Signals: + input rst_ni, + input clk_i, + + //Alert: + input logic alert_major, + input logic alert_major_due_to_integrity_err, + + //CSR: + input logic integrity_enabled, + input logic nmip, + input logic [10:0] mcause_exception_code, + + + //OBI data: + input obi_data_req_t obi_data_req_packet, + input obi_data_resp_t obi_data_resp_packet, + input logic [31:0] obi_data_addr, + input logic obi_data_req, + input logic obi_data_reqpar, + input logic obi_data_gnt, + input logic obi_data_gntpar, + input logic obi_data_rvalid, + input logic obi_data_rvalidpar, + + //OBI instr: + input obi_inst_req_t obi_instr_req_packet, + input obi_inst_resp_t obi_instr_resp_packet, + input logic [31:0] obi_instr_addr, + input logic obi_instr_req, + input logic obi_instr_reqpar, + input logic obi_instr_gnt, + input logic obi_instr_gntpar, + input logic obi_instr_rvalid, + input logic obi_instr_rvalidpar, + + //Register file memory: + input logic [REGFILE_WORD_WIDTH-1:0] gpr_mem [CORE_PARAM_REGFILE_NUM_WORDS], + input logic rf_we, + input logic [4:0] rf_waddr, + input logic [31:0] rf_wdata, + + //Alignment buffer: + input inst_resp_t alb_resp_i, + input inst_resp_t [ALBUF_DEPTH-1:0] alb_resp_q, + input logic [ALBUF_DEPTH-1:0] alb_valid, + input logic [ALBUF_CNT_WIDTH-1:0] alb_wptr, + input logic [ALBUF_CNT_WIDTH-1:0] alb_rptr1, + input logic [ALBUF_CNT_WIDTH-1:0] alb_rptr2, + + //If: + input logic if_valid, + input logic if_instr_integrity_err, + input logic if_instr_cmpr, + input logic [31:0] if_instr_pc, + input logic dummy_insert, + + //Id: + input logic id_ready, + input logic id_instr_integrity_err, + input logic id_abort_op, + input logic id_illegal_insn, + + //Wb: + input logic wb_valid, + input logic wb_integrity_err, + input logic [6:0] wb_instr_opcode, + input logic wb_exception, + input logic [10:0] wb_exception_code, + input logic data_integrity_err, + + //MISC: + input logic [$bits(ctrl_state_e)-1:0] ctrl_fsm_cs, + input logic [$bits(pc_mux_e)-1:0] pc_mux, + input logic pc_set, + input logic seq_valid, + input logic kill_if, + input logic [1:0] n_flush_q, + input logic rchk_err_instr, + input logic rchk_err_data + ); + + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + string info_tag_rtl_bug = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (RTL BUG)"; + + // Local parameters: + localparam ASSUMED_VALUE_BE = 4'b1111; + localparam ASSUMED_VALUE_WE = 1'b0; + localparam ASSUMED_VALUE_ATOP = 6'b00_0000; + localparam ASSUMED_VALUE_WDATA = 32'h0000_0000; + localparam ASSUMED_VALUE_EXOKAY = 1'b0; + localparam ASSUMED_VALUE_MID = 8'h0; + localparam REQ_WAS_READ = 1'b1; + localparam DEBUG_TAKEN = 2'b11; + + localparam RCHK_STORE = 4; + localparam ZERO = '0; + + localparam LSU_LOAD_INTEGRITY_FAULT = 11'h402; + localparam LSU_STORE_INTEGRITY_FAULT = 11'h403; + + localparam int OBI_DATA_RESP_ERR_BIT0_ERROR_FROM_BUS = 0; + + function logic [12:0] f_achk (logic [31:0] wdata, logic dbg, logic [5:0] atop, logic [7:0] mid, logic [3:0] be, logic we, logic [2:0] prot, logic [1:0] memtype, logic [31:0] addr); + f_achk = { + ^wdata[31:24], + ^wdata[23:16], + ^wdata[15:8], + ^wdata[7:0], + ~^dbg, + ^atop[5:0], + ^mid[7:0], + ~^{be[3:0], we}, + ~^{prot[2:0], memtype[1:0]}, + ^addr[31:24], + ^addr[23:16], + ^addr[15:8], + ^addr[7:0]}; + endfunction + + + function logic [4:0] f_rchk (logic err, logic exokay, logic [31:0] rdata); + f_rchk = { + ^{err, exokay}, + ^rdata[31:24], + ^rdata[23:16], + ^rdata[15:8], + ^rdata[7:0]}; + endfunction + + + + logic [12:0] achk_data_calculated; + logic [12:0] achk_instr_calculated; + logic [4:0] rchk_instr_calculated; + logic [4:0] rchk_data_calculated; + + //Independent generation of the checksum based on the outputted data + + assign achk_data_calculated = f_achk( + obi_data_req_packet.wdata, + obi_data_req_packet.dbg, + ASSUMED_VALUE_ATOP, + ASSUMED_VALUE_MID, + obi_data_req_packet.be, + obi_data_req_packet.we, + obi_data_req_packet.prot, + obi_data_req_packet.memtype, + obi_data_addr); + + assign achk_instr_calculated = f_achk( + ASSUMED_VALUE_WDATA, + obi_instr_req_packet.dbg, + ASSUMED_VALUE_ATOP, + ASSUMED_VALUE_MID, + ASSUMED_VALUE_BE, + ASSUMED_VALUE_WE, + obi_instr_req_packet.prot, + obi_instr_req_packet.memtype, + obi_instr_addr); + + assign rchk_instr_calculated = f_rchk( + obi_instr_resp_packet.err, + ASSUMED_VALUE_EXOKAY, + obi_instr_resp_packet.rdata); + + assign rchk_data_calculated = f_rchk( + obi_data_resp_packet.err[OBI_DATA_RESP_ERR_BIT0_ERROR_FROM_BUS], + ASSUMED_VALUE_EXOKAY, + obi_data_resp_packet.rdata); + + + //Verify that interface integrity is enabled by default + + a_xsecure_integrity_default_on: assert property ( + $rose(rst_ni) + |-> + integrity_enabled + ) else `uvm_error(info_tag, "Interface integrity checking is not enabled when exiting reset.\n"); + + + //Verify that the parity signals are the complements of the non-parity signals at all times. + + property p_parity_signal_is_invers_of_signal(signal, parity_signal); + @(posedge clk_i) + parity_signal == ~signal; + endproperty + + a_xsecure_integrity_data_req_parity: assert property ( + p_parity_signal_is_invers_of_signal( + obi_data_req, + obi_data_reqpar) + ) else `uvm_error(info_tag, "The OBI data bus request parity signal is not inverse of the request signal.\n"); + + a_xsecure_integrity_instr_req_parity: assert property ( + p_parity_signal_is_invers_of_signal( + obi_instr_req, + obi_instr_reqpar) + ) else `uvm_error(info_tag, "The OBI instruction bus request parity signal is not inverse of the request signal.\n"); + + a_xsecure_integrity_data_gnt_parity: assert property ( + p_parity_signal_is_invers_of_signal( + obi_data_gnt, + obi_data_gntpar) + ) else `uvm_error(info_tag, "The OBI data bus grant parity signal is not inverse of the grant signal.\n"); + + a_xsecure_integrity_instr_gnt_parity: assert property ( + p_parity_signal_is_invers_of_signal( + obi_instr_gnt, + obi_instr_gntpar) + ) else `uvm_error(info_tag, "The OBI instruction bus grant parity signal is not inverse of the grant signal.\n"); + + a_xsecure_integrity_data_rvalid_parity: assert property ( + p_parity_signal_is_invers_of_signal( + obi_data_rvalid, + obi_data_rvalidpar) + ) else `uvm_error(info_tag, "The OBI data bus rvalid parity signal is not inverse of the rvalid signal.\n"); + + a_xsecure_integrity_instr_rvalid_parity: assert property ( + p_parity_signal_is_invers_of_signal( + obi_instr_rvalid, + obi_instr_rvalidpar) + ) else `uvm_error(info_tag, "The OBI instruction bus rvalid parity signal is not inverse of the rvalid signal.\n"); + + + //Verify that the received and generated checksums are correct + + property p_checksum(req, chk_input, chk_calculated); + if_valid //TODO: do we need this one? + && req + |-> + chk_input == chk_calculated; + endproperty + + a_xsecure_integrity_data_achk: assert property ( + p_checksum( + obi_data_req, + obi_data_req_packet.achk, + achk_data_calculated) + ) else `uvm_error(info_tag, "The request checksum for the OBI data bus is not as expected.\n"); + + + a_xsecure_integrity_instr_achk: assert property ( + p_checksum( + obi_instr_req, + obi_instr_req_packet.achk, + achk_instr_calculated) + ) else `uvm_error(info_tag_rtl_bug, "The request checksum for the OBI instructions bus is not as expected.\n"); + + + a_xsecure_integrity_instr_rchk: assert property ( + obi_instr_rvalid + |-> + obi_instr_resp_packet.rchk == rchk_instr_calculated + ); + + property p_checksum_data_rchk(memory_op, rvalid, chk_input, chk_calculated); + memory_op + && rvalid + |-> + chk_input == chk_calculated; + endproperty + + a_xsecure_integrity_store_data_rchk: assert property ( + p_checksum_data_rchk( + support_if.obi_data_packet.req.we, + obi_data_rvalid, + obi_data_resp_packet.rchk[RCHK_STORE], + rchk_data_calculated[RCHK_STORE]) + ); + + + a_xsecure_integrity_load_data_rchk: assert property ( + p_checksum_data_rchk( + !support_if.obi_data_packet.req.we, + obi_data_rvalid, + obi_data_resp_packet.rchk, + rchk_data_calculated) + ); + + + //Verify that major alert and exception code "Instruction parity/checksum fault" are set when executing an instruction with an integrity error + + a_glitch_xsecure_integrity_instr_integrity_error: assert property ( + wb_valid + && wb_integrity_err + && ctrl_fsm_cs != DEBUG_TAKEN //When entering debug we dont trigger any exceptions + |-> + wb_exception + && (wb_exception_code == EXC_CAUSE_INSTR_INTEGRITY_FAULT + || wb_exception_code == EXC_CAUSE_INSTR_FAULT) //Instruction fault exception have higher priority than integrity fault + + ##1 alert_major + ) else `uvm_error(info_tag_glitch, "Attempted execution of an instruction with integrity error does set the major alert or correct exception code.\n"); + + + //Verify that major alert is set if the inputted parity signals dont correspond to the inputted non-parity signals + + property p_parity_fault(signal, parity_signal); + parity_signal != ~signal + |=> + alert_major; + endproperty + + + a_glitch_xsecure_integrity_data_gnt_parity: assert property ( + p_parity_fault( + obi_data_gnt, + obi_data_gntpar) + ) else `uvm_error(info_tag_glitch, "A OBI data bus grant parity fault does not set the major alert.\n"); + + a_glitch_xsecure_integrity_instr_gnt_parity: assert property ( + p_parity_fault( + obi_instr_gnt, + obi_instr_gntpar) + ) else `uvm_error(info_tag_glitch, "A OBI instruction bus grant parity fault does not set the major alert.\n"); + + a_glitch_xsecure_integrity_data_rvalid_parity: assert property ( + p_parity_fault( + obi_data_rvalid, + obi_data_rvalidpar) + ) else `uvm_error(info_tag_glitch, "A OBI data bus rvalid parity fault does not set the major alert.\n"); + + a_glitch_xsecure_integrity_instr_rvalid_parity: assert property ( + p_parity_fault( + obi_instr_rvalid, + obi_instr_rvalidpar) + ) else `uvm_error(info_tag_glitch, "A OBI instruction bus rvalid parity fault does not set the major alert.\n"); + + + //Verify that major alert is set if the inputted checksums dont correspond to what the packets contains + //But only if integrity checking is enabled + + sequence seq_checksum_fault(rvalid, req_had_integrity, memory_op, rchk_input, rchk_calculated); + rvalid + && req_had_integrity + && memory_op + && rchk_input != rchk_calculated; + endsequence + + + a_glitch_xsecure_integrity_rchk_instr_read: assert property ( + integrity_enabled + + ##0 seq_checksum_fault( + obi_instr_rvalid, + support_if.instr_req_had_integrity, + REQ_WAS_READ, + obi_instr_resp_packet.rchk, + rchk_instr_calculated) + + |-> + alert_major_due_to_integrity_err + ) else `uvm_error(info_tag_glitch, "An error in the OBI instruction bus's response packet's checksum does not set the major alert.\n"); + + a_glitch_xsecure_integrity_rchk_data_store: assert property ( + integrity_enabled + + ##0 seq_checksum_fault( + obi_data_rvalid, + support_if.data_req_had_integrity, + support_if.obi_data_packet.req.we, + obi_data_resp_packet.rchk[RCHK_STORE], + rchk_data_calculated[RCHK_STORE]) + + |-> + alert_major_due_to_integrity_err + ) else `uvm_error(info_tag_glitch, "An error in the OBI data bus's response packet's checksum does not set the major alert.\n"); + + a_glitch_xsecure_integrity_rchk_data_read: assert property ( + integrity_enabled + + ##0 seq_checksum_fault( + obi_data_rvalid, + support_if.data_req_had_integrity, + !support_if.obi_data_packet.req.we, + obi_data_resp_packet.rchk, + rchk_data_calculated) + + |-> + alert_major_due_to_integrity_err + ) else `uvm_error(info_tag_glitch, "An error in the OBI data bus's response packet's checksum does not set the major alert.\n"); + + + //Verify that checksum errors for instructions and data do not set alert major if the integrity checking is disabled + + a_glitch_xsecure_integrity_rchk_instr_read_integrity_disabled: assert property ( + !integrity_enabled + + ##0 seq_checksum_fault( + obi_instr_rvalid, + support_if.instr_req_had_integrity, + REQ_WAS_READ, + obi_instr_resp_packet.rchk, + rchk_instr_calculated) + + |-> + //No integrity errors have triggered major alert, or an integrity error has triggered major alert, but it is not due to rchk instr error + !alert_major_due_to_integrity_err + || (alert_major_due_to_integrity_err && !rchk_err_instr) + + ) else `uvm_error(info_tag_glitch, "An error in the OBI instruction bus's response packet's checksum sets the major alert even though interface integrity checking is disabled.\n"); + + a_glitch_xsecure_integrity_rchk_data_store_integrity_disabled: assert property ( + !integrity_enabled + + ##0 seq_checksum_fault( + obi_data_rvalid, + support_if.data_req_had_integrity, + support_if.obi_data_packet.req.we, + obi_data_resp_packet.rchk[RCHK_STORE], + rchk_data_calculated[RCHK_STORE]) + + |-> + !alert_major_due_to_integrity_err + || (alert_major_due_to_integrity_err && !rchk_err_data) + ) else `uvm_error(info_tag_glitch, "An error in the OBI data bus's response packet's checksum sets the major alert even though interface integrity checking is disabled.\n"); + + a_glitch_xsecure_integrity_rchk_data_read_integrity_disabled: assert property ( + !integrity_enabled + + ##0 seq_checksum_fault( + obi_data_rvalid, + support_if.data_req_had_integrity, + !support_if.obi_data_packet.req.we, + obi_data_resp_packet.rchk, + rchk_data_calculated) + + |-> + !alert_major_due_to_integrity_err + || (alert_major_due_to_integrity_err && !rchk_err_data) + ) else `uvm_error(info_tag_glitch, "An error in the OBI data bus's response packet's checksum sets the major alert even though interface integrity checking is disabled.\n"); + + + //Verify that the register file is updated even though there is an integrity error + + a_xsecure_integrity_update_register_parity_checksum_error: assert property ( + rf_we + && rf_waddr != ZERO + |=> + gpr_mem[$past(rf_waddr)][31:0] == $past(rf_wdata) + ) else `uvm_error(info_tag_glitch, "The register file is not updated.\n"); + + //Check that it is possible to write to the register file when there is an integrity error + c_glitch_xsecure_integrity_update_register_parity_checksum_error: cover property ( + rf_we + && rf_waddr != ZERO + && obi_data_rvalid + && data_integrity_err + ); + + + //Verify that the integrity bits to the data and instructions fetched from the OBI bus are set if there are parity or checksum faults + + property p_parity_fault_integrity_err_gnt(rvalid, gnt_parity_err, integrity_err); + rvalid + && gnt_parity_err + |-> + integrity_err; + endproperty + + a_glitch_xsecure_integrity_instr_gntparity_fault_integrity_err: assert property ( + p_parity_fault_integrity_err_gnt( + obi_instr_rvalid, + support_if.gntpar_error_in_response_instr, + if_instr_integrity_err) + ) else `uvm_error(info_tag_glitch, "The integrity error bit is not set in the OBI instruction bus's response packet, even though there was grant parity error when generating the request packet.\n"); + + a_glitch_xsecure_integrity_data_gntparity_fault_integrity_err: assert property ( + p_parity_fault_integrity_err_gnt( + obi_data_rvalid, + support_if.gntpar_error_in_response_data, + data_integrity_err) + ) else `uvm_error(info_tag_glitch, "The integrity error bit is not set in the OBI data bus's response packet, even though there was grant parity error when generating the request packet.\n"); + + + property p_parity_fault_integrity_err_rvalid(rvalid, parity_rvalid, integrity_err); + rvalid + && parity_rvalid != ~rvalid + |-> + integrity_err; + endproperty + + a_glitch_xsecure_integrity_instr_rvalidparity_fault_integrity_err: assert property ( + p_parity_fault_integrity_err_rvalid( + obi_instr_rvalid, + obi_instr_rvalidpar, + if_instr_integrity_err) + ) else `uvm_error(info_tag_glitch, "The integrity error bit is not set in the OBI instruction bus's response packet, even though there was a rvalid parity error.\n"); + + a_glitch_xsecure_integrity_data_rvalidparity_fault_integrity_err: assert property ( + p_parity_fault_integrity_err_rvalid( + obi_data_rvalid, + obi_data_rvalidpar, + data_integrity_err) + ) else `uvm_error(info_tag_glitch, "The integrity error bit is not set in the OBI data bus's response packet, even though there was a rvalid parity error.\n"); + + + property p_rchk_fault_integrity_err(req_had_integrity, load_from_memory, rvalid, rchk_input, rchk_calculated, integrity_err); + integrity_enabled + && req_had_integrity + && load_from_memory + && rvalid + && rchk_input != rchk_calculated + |-> + integrity_err; + endproperty + + a_glitch_xsecure_integrity_instr_rchk_fault_integrity_err: assert property ( + p_rchk_fault_integrity_err( + support_if.instr_req_had_integrity, + REQ_WAS_READ, + obi_instr_rvalid, + obi_instr_resp_packet.rchk, + rchk_instr_calculated, + if_instr_integrity_err) + ) else `uvm_error(info_tag_glitch, "The integrity error bit is not set in the OBI instruction bus's response packet, even though there was a checksum error.\n"); + + a_glitch_xsecure_integrity_data_rchk_fault_integrity_err_store: assert property ( + p_rchk_fault_integrity_err( + support_if.data_req_had_integrity, + support_if.obi_data_packet.req.we, + obi_data_rvalid, + obi_data_resp_packet.rchk[RCHK_STORE], + rchk_data_calculated[RCHK_STORE], + data_integrity_err) + ) else `uvm_error(info_tag_glitch, "The integrity error bit is not set in the OBI data bus's response packet, even though there was a checksum error in the store operation.\n"); + + a_glitch_xsecure_integrity_data_rchk_fault_integrity_err_load: assert property ( + p_rchk_fault_integrity_err( + support_if.data_req_had_integrity, + !support_if.obi_data_packet.req.we, + obi_data_rvalid, + obi_data_resp_packet.rchk, + rchk_data_calculated, + data_integrity_err) + ) else `uvm_error(info_tag_glitch, "The integrity error bit is not set in the OBI data bus's response packet, even though there was a checksum error in the load operation.\n"); + + + //Verify that the integrity error bit and the checksum bits is forwarded into the alignement buffer together with the instruction + + property p_instr_to_alignment_buffer(wptr_position); + obi_instr_rvalid + && alb_wptr == wptr_position + && !kill_if + && n_flush_q == 0 //There is no outstanding request that needs to be disregarded (due to unpredicted PC jump) + |=> + alb_resp_q[wptr_position].bus_resp.rchk == $past(obi_instr_resp_packet.rchk) + && alb_resp_q[wptr_position].bus_resp.integrity_err == $past(if_instr_integrity_err) + && alb_resp_q[wptr_position].bus_resp.integrity == $past(support_if.instr_req_had_integrity); + endproperty + + + generate + for (genvar wptr = 0; wptr < ALBUF_DEPTH; wptr++) begin + + a_xsecure_integrity_instr_to_alignment_buffer: assert property ( + p_instr_to_alignment_buffer(wptr) + ) else `uvm_error(info_tag, "The integrity error bit and/or the checksum bits from a response packet is not forwarded into the alignment buffer\n"); + + a_glitch_xsecure_integrity_instr_to_alignment_buffer: assert property ( + p_instr_to_alignment_buffer(wptr) + ) else `uvm_error(info_tag_glitch, "The integrity error bit and/or the checksum bits from a response packet is not forwarded into the alignment buffer\n"); + + end + endgenerate + + + //Verify that the instruction propegated to the id stage have an integrity error if any of its related instruction fetches have integrity errors or alignment buffer based checksum errors. + + logic is_obi_addr; + + logic was_pc_set; + always_latch begin + if(!clknrst_if.reset_n) begin + + end else if ($past(pc_set)) begin + was_pc_set = 1'b1; + end else if (if_instr_pc[31:2] != $past(if_instr_pc[31:2])) begin + was_pc_set = 1'b0; + end + end + + assign is_obi_addr = + !was_pc_set + || (was_pc_set + && (pc_mux != PC_BOOT + && pc_mux != PC_MRET + && pc_mux != PC_DRET + && pc_mux != PC_TRAP_EXC + && pc_mux != PC_TRAP_IRQ + && pc_mux != PC_TRAP_DBD + && pc_mux != PC_TRAP_DBE + && pc_mux != PC_TRAP_NMI + && pc_mux != PC_TRAP_CLICV + && pc_mux != PC_POINTER + && pc_mux != PC_TBLJUMP) + ); + + logic [4:0] alb_input_rchk_calculated; + logic [4:0] alb_rptr1_rchk_calculated; + logic [4:0] alb_rptr2_rchk_calculated; + + assign alb_input_rchk_calculated = f_rchk(alb_resp_i.bus_resp.err, ASSUMED_VALUE_EXOKAY, alb_resp_i.bus_resp.rdata); + assign alb_rptr1_rchk_calculated = f_rchk(alb_resp_q[alb_rptr1].bus_resp.err, ASSUMED_VALUE_EXOKAY, alb_resp_q[alb_rptr1].bus_resp.rdata); + assign alb_rptr2_rchk_calculated = f_rchk(alb_resp_q[alb_rptr2].bus_resp.err, ASSUMED_VALUE_EXOKAY, alb_resp_q[alb_rptr2].bus_resp.rdata); + + logic alb_input_integrity_err; + logic alb_rptr1_integrity_err; + logic alb_rptr2_integrity_err; + + assign alb_input_integrity_err = ((alb_resp_i.bus_resp.rchk != alb_input_rchk_calculated) && (obi_instr_rvalid && support_if.instr_req_had_integrity)) || alb_resp_i.bus_resp.integrity_err; + assign alb_rptr1_integrity_err = ((alb_resp_q[alb_rptr1].bus_resp.rchk != alb_rptr1_rchk_calculated) && (alb_resp_q[alb_rptr1].mpu_status == MPU_OK) && alb_resp_q[alb_rptr1].bus_resp.integrity) || alb_resp_q[alb_rptr1].bus_resp.integrity_err; + assign alb_rptr2_integrity_err = ((alb_resp_q[alb_rptr2].bus_resp.rchk != alb_rptr2_rchk_calculated) && (alb_resp_q[alb_rptr2].mpu_status == MPU_OK) && alb_resp_q[alb_rptr2].bus_resp.integrity) || alb_resp_q[alb_rptr2].bus_resp.integrity_err; + + logic if_instr_aligned; + assign if_instr_aligned = (if_instr_pc[1:0] == '0); + + logic if_integrity_err_calculated; + + always_latch begin + if(!alb_valid[alb_rptr1]) begin + if_integrity_err_calculated = alb_input_integrity_err; + end else if (alb_valid[alb_rptr1] && alb_valid[alb_rptr2]) begin + if_integrity_err_calculated = (if_instr_aligned || if_instr_cmpr) ? alb_rptr1_integrity_err : alb_rptr1_integrity_err || alb_rptr2_integrity_err; + end else if (alb_valid[alb_rptr1] && !alb_valid[alb_rptr2]) begin + if_integrity_err_calculated = (if_instr_aligned || if_instr_cmpr) ? alb_rptr1_integrity_err : alb_rptr1_integrity_err || alb_input_integrity_err; + end + end + + a_glitch_xsecure_integrity_instr_fetch_fusion: assert property ( + if_valid + && id_ready + && integrity_enabled + && is_obi_addr + && !dummy_insert + && !seq_valid + + //Assume no error: + ##1 !id_abort_op + && !id_illegal_insn + |-> + id_instr_integrity_err == $past(if_integrity_err_calculated) + ); + + + //Verify that integrity errors on the OBI data bus set mcause exception code to 1026 or 1027, and set alert major + + a_glitch_xsecure_integrity_data_integrity_err_helper_assert: assert property ( + + obi_data_rvalid + && data_integrity_err + |=> + $rose(nmip) + || $past(nmip) + + ) else `uvm_error(info_tag_glitch, "An associated parity/checksum error does not set the pending NMI signal.\n"); + + + a_glitch_xsecure_integrity_data_integrity_err: assert property ( + + obi_data_rvalid + && data_integrity_err + ##1 $rose(nmip) + ##1 nmip[*0:$] + ##1 !nmip //the nmi is handeled + |-> + (mcause_exception_code == LSU_LOAD_INTEGRITY_FAULT || mcause_exception_code == LSU_STORE_INTEGRITY_FAULT) + && alert_major + + ) else `uvm_error(info_tag_glitch, "The NMI caused by an associated parity/checksum error does not have exception code 1027 or 1026.\n"); + + //Load instructions + c_glitch_xsecure_integrity_parity_checksum_fault_NMI_load_instruction: cover property ( + + obi_data_rvalid + && data_integrity_err + && wb_instr_opcode == OPCODE_LOAD + ##1 $rose(nmip) + ); + + //Store instructions + c_glitch_xsecure_integrity_parity_checksum_fault_NMI_store_instruction: cover property ( + + obi_data_rvalid + && data_integrity_err + && wb_instr_opcode == OPCODE_STORE + ##1 $rose(nmip) + + ); + + endmodule : uvmt_cv32e40s_xsecure_interface_integrity_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert.sv new file mode 100644 index 0000000000..522bfd563a --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert.sv @@ -0,0 +1,82 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + input rst_ni, + input clk_i, + + //CSRs: + input logic [31:0][31:0] mhpmevent, + input logic [31:0][63:0] mhpmcounter, + input logic [31:0] mcountinhibit + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + + localparam ZERO = 0; + + + //Verify that the following bits in these CSRs are hardwired to 0: + //- mphmevent: 3 to 31 + //- mcountinhibit: 1 and 3 to 31 + + //And that the following CSRs are tied to 0: + //- mphmcounter3, + //- mphmcounter4, + //... + //- mphmcounter31, + //- mhpmcounterh3, + //- mhpmcounterh4, + //... + //- mhpmcounterh31 + + + a_xsecure_reduced_profiling_mhpmevent: assert property ( + + mhpmevent[31:3] == ZERO + + ) else `uvm_error(info_tag, "The MHPMEVENT registers 31 to 3 are not hardwired to zero.\n"); + + + a_xsecure_reduced_profiling_mhpmcounter: assert property ( + + //Note that the mhpmcounter signal contain both the mhpmcounter and mhpmcounterh bits + mhpmcounter[31:3] == ZERO + + ) else `uvm_error(info_tag, "The MHPMCOUNTER and MHPMCOUNTERH registers 31 to 3 are not hardwired to zero.\n"); + + + a_xsecure_reduced_profiling_mcountinhibit: assert property ( + + mcountinhibit[1] == ZERO + && mcountinhibit[31:3] == ZERO + + ) else `uvm_error(info_tag, "The MHPMCOUNTINHIBIT registers 1, and 3 to 31 are not hardwired to zero.\n"); + + + endmodule : uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert + diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_register_file_ecc_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_register_file_ecc_assert.sv new file mode 100644 index 0000000000..8787395c74 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_register_file_ecc_assert.sv @@ -0,0 +1,208 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_register_file_ecc_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + import uvmt_cv32e40s_base_test_pkg::*; + + #( + parameter int SECURE = 1 + ) + ( + uvma_rvfi_instr_if_t rvfi_if, + input rst_ni, + input clk_i, + + //alerts: + input logic alert_major, + + //Register file memory: + input logic [REGFILE_WORD_WIDTH-1:0] gpr_mem [CORE_PARAM_REGFILE_NUM_WORDS], + + //Soruce registers: + input logic [4:0] rs1, + input logic [4:0] rs2, + + //Writing of GPRs: + input logic gpr_we, + input logic [4:0] gpr_waddr, + input logic [31:0] gpr_wdata + + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + string info_tag_glitch = "CV32E40S_XSECURE_ASSERT_COVERPOINTS (GLITCH BEHAVIOR)"; + + localparam REG_SIZE = 32; + localparam ECC_SIZE = 6; + localparam ZERO = '0; + localparam REG_DEFAULT = '0; + localparam ECC_DEFAULT = 6'h2A; + + ////////// GENERAL PURPOSE REGISTERS ARE ZERO WHEN EXITING RESET ////////// + + //Verify that the general purpose registers are zero when exiting reset, and that their ECC values are corresponding to value zero (6'h2A) + + property p_gpr_ecc_reset(integer gpr_addr); + + $rose(rst_ni) + |-> + gpr_mem[gpr_addr][(REG_SIZE-1) -:REG_SIZE] == REG_DEFAULT + && gpr_mem[gpr_addr][(ECC_SIZE+REG_SIZE-1) -:ECC_SIZE] == ECC_DEFAULT; + + endproperty + + + //Check the default value of the instructions' register sources by using RVFI + property p_gpr_reset_rvfi(rs_addr, gpr_addr); + + $rose(rst_ni) ##0 rvfi_if.rvfi_valid[->1] + ##0 rs_addr == gpr_addr + + |-> + rvfi_if.rvfi_rs1_rdata == REG_DEFAULT; + endproperty + + + generate for (genvar gpr_addr = 0; gpr_addr < 32; gpr_addr++) begin : gen_gpr_reset_value + + a_xsecure_rf_ecc_gpr_reset_value: assert property ( + p_gpr_ecc_reset( + gpr_addr) + ) else `uvm_error(info_tag, $sformatf("GPR %0d is not set to 0 when exiting reset stage, or the syndrome is not set to 0x2A.\n", gpr_addr)); + + a_xsecure_rf_ecc_gpr_reset_value_rvfi_rs1: assert property ( + p_gpr_reset_rvfi( + rvfi_if.rvfi_rs1_addr, + gpr_addr) + ) else `uvm_error(info_tag, $sformatf("GPR %0d is not set to 0 when exiting reset stage (as RS1 is not 0).\n", gpr_addr)); + + a_xsecure_rf_ecc_gpr_reset_value_rvfi_rs2: assert property ( + p_gpr_reset_rvfi( + rvfi_if.rvfi_rs2_addr, + gpr_addr) + ) else `uvm_error(info_tag, $sformatf("GPR %0d is not set to 0 when exiting reset stage (as RS2 is not 0).\n", gpr_addr)); + + end endgenerate //gen_gpr_reset_value + + + //Verify that the GPRs and their ECC values have not all bits set to 0s or all bits set to 1s in the same clock cycle + + generate for (genvar gpr_addr = 1; gpr_addr < 32; gpr_addr++) begin : gen_gpr_not_1s_or_0s + + a_xsecure_rf_ecc_gpr_not_all_0s_or_1s: assert property ( + gpr_mem[gpr_addr] != '0 + && gpr_mem[gpr_addr] != '1 + ) else `uvm_error(info_tag, $sformatf("The value of GPR %0d is all %0s.\n", gpr_addr, gpr_mem[gpr_addr][0])); + + end endgenerate //gen_gpr_not_1s_or_0s + + + //Verify that we set major alert if the the register sources' values and corresponding ECC score have all bits set to 0s or 1s + + generate for (genvar gpr_addr = 1; gpr_addr < 32; gpr_addr++) begin : gen_gpr_1s_or_0s + + a_glitch_xsecure_rf_gpr_not_all_0s_or_1s: assert property ( + (rs1 == gpr_addr + || rs2 == gpr_addr) + + && (gpr_mem[gpr_addr] == '0 + || gpr_mem[gpr_addr] == '1) + + |=> + alert_major + + ) else `uvm_error(info_tag_glitch, $sformatf("The value of GPR %0d is all %0s, and major alert is not set.\n", gpr_addr, gpr_mem[gpr_addr][0])); + + end endgenerate //gen_gpr_1s_or_0s + + + + + //Verify that decoding missmatch of 1 og 2 bits sets major alert + + /**************************************** + Support logic: + The support logic creates a local memory that shadowes the GPR + In the local memory, we insert data in the same manner as for the GPRs. + We detect bit flip in the GPRs by comparing them with the local memory + ****************************************/ + + logic [31:0][31:0] gpr_mem_shadow; + + always @(posedge clk_i or negedge rst_ni) begin + if(!rst_ni) begin + gpr_mem_shadow = '0; + end else if (gpr_we && gpr_waddr != ZERO) begin + gpr_mem_shadow[gpr_waddr] = gpr_wdata; + end + end + + //Verify that support logic work as expected: + + a_xsecure_rf_ecc_reset_gpr_mem_shadow: assert property ( + ##0 + $rose(rst_ni) + |-> + gpr_mem_shadow == '0 + + ) else `uvm_error(info_tag, "The local support memory is not set to 0s when exiting reset.\n"); + + + a_xsecure_rf_ecc_update_gpr_mem_shadow: assert property ( + + gpr_we + && gpr_waddr != ZERO + |=> + gpr_mem_shadow[$past(gpr_waddr)] == $past(gpr_wdata) + + ) else `uvm_error(info_tag, "The support logic does not update the local memory in the same manner as the GPRs.\n"); + + + //Verify requirements: + + property p_rs_bit_fault(rs_addr, gpr_addr); + + rs_addr == gpr_addr + && ($countbits(gpr_mem[gpr_addr][(REG_SIZE-1) -:REG_SIZE] ^ gpr_mem_shadow[gpr_addr], '1) inside {1,2}) + |=> + alert_major; + + endproperty + + + generate for (genvar gpr_addr = 1; gpr_addr < 32; gpr_addr++) begin : gen_gpr_bit_faults + + a_glitch_xsecure_rf_ecc_rs1_bit_fault: assert property ( + p_rs_bit_fault( + rs1, + gpr_addr) + ) else `uvm_error(info_tag_glitch, $sformatf("1 or 2 bit errors when reading RS1 (address %0d) do not set the alert major.\n", gpr_addr)); + + a_glitch_xsecure_rf_ecc_rs2_bit_fault: assert property ( + p_rs_bit_fault( + rs2, + gpr_addr) + ) else `uvm_error(info_tag_glitch, $sformatf("1 or 2 bit errors when reading RS2 (address %0d) do not set the alert major.\n", gpr_addr)); + + end endgenerate //gen_gpr_bit_faults + + endmodule : uvmt_cv32e40s_xsecure_register_file_ecc_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_security_alerts_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_security_alerts_assert.sv new file mode 100644 index 0000000000..d0108a5daa --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_security_alerts_assert.sv @@ -0,0 +1,205 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +module uvmt_cv32e40s_xsecure_security_alerts_assert + import uvm_pkg::*; + import cv32e40s_pkg::*; + #( + parameter int SECURE = 1 + ) + ( + uvma_rvfi_instr_if_t rvfi_if, + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if, + input rst_ni, + input clk_i, + + //alerts: + input logic alert_minor, + input logic alert_major, + + //wb: + input wb_valid, + input exception_in_wb, + input [10:0] exception_cause_wb, + + //dummy and hint: + input logic dummy_en, + input logic hint_en, + input logic lfsr0_clock_en, + input logic lfsr1_clock_en, + input logic lfsr2_clock_en, + input logic seed0_we, + input logic seed1_we, + input logic seed2_we, + input logic [31:0]seed0_i, + input logic [31:0]seed1_i, + input logic [31:0]seed2_i, + input logic [31:0]lfsr0_n, + input logic [31:0]lfsr1_n, + input logic [31:0]lfsr2_n, + + //OBI: + input logic obi_data_rvalid, + input logic obi_data_err, + + //NMI: + input logic nmip, + + //debug: + input logic debug_mode + ); + + // Default settings: + default clocking @(posedge clk_i); endclocking + default disable iff (!(rst_ni) || !(SECURE)); + string info_tag = "CV32E40S_XSECURE_ASSERT_COVERPOINTS"; + + // Local parameters: + localparam NO_LOCKUP_ERRORS = 3'b000; + + localparam INSTRUCTION_ACCESS_FAULT = 11'd1; + localparam ILLEGAL_INSTRUCTION_FAULT = 11'd2; + localparam LOAD_ACCESS_FAULT = 11'd5; + localparam STORE_AMO_ACCESS_FAULT = 11'd7; + localparam INSTRUCTION_BUS_FAULT = 11'd24; + + function logic detect_lockup_error; + input logic dummy_en, hint_en, clock_en, seed_we; + input logic [31:0] seed_i, lfsr_n; + + detect_lockup_error = (dummy_en || hint_en) && clock_en && ((!seed_we && lfsr_n == '0) || (seed_we && seed_i == '0)); + endfunction + + logic lfsr0_lockup_error_detected; + logic lfsr1_lockup_error_detected; + logic lfsr2_lockup_error_detected; + + assign lfsr0_lockup_error_detected = detect_lockup_error(dummy_en, hint_en, lfsr0_clock_en, seed0_we, seed0_i, lfsr0_n); + assign lfsr1_lockup_error_detected = detect_lockup_error(dummy_en, hint_en, lfsr1_clock_en, seed1_we, seed1_i, lfsr1_n); + assign lfsr2_lockup_error_detected = detect_lockup_error(dummy_en, hint_en, lfsr2_clock_en, seed2_we, seed2_i, lfsr2_n); + + logic triggering_minor_alert_due_to_non_nmi_exceptions; + assign triggering_minor_alert_due_to_non_nmi_exceptions = wb_valid && exception_in_wb + && (exception_cause_wb == INSTRUCTION_ACCESS_FAULT + || exception_cause_wb == ILLEGAL_INSTRUCTION_FAULT + || exception_cause_wb == LOAD_ACCESS_FAULT + || exception_cause_wb == STORE_AMO_ACCESS_FAULT + || exception_cause_wb == INSTRUCTION_BUS_FAULT); + + + //Verify that LFSR lockups set the minor alert: + + a_xsecure_security_alert_lfsr0_lockup: assert property ( + lfsr0_lockup_error_detected + |=> + alert_minor + ) else `uvm_error(info_tag, "LFSR0 Lookup error does not set the minor alert.\n"); + + a_xsecure_security_alert_lfsr1_lockup: assert property ( + lfsr1_lockup_error_detected + |=> + alert_minor + ) else `uvm_error(info_tag, "LFSR0 Lookup error does not set the minor alert.\n"); + + a_xsecure_security_alert_lfsr2_lockup: assert property ( + lfsr2_lockup_error_detected + |=> + alert_minor + ) else `uvm_error(info_tag, "LFSR0 Lookup error does not set the minor alert.\n"); + + + //Verify that the minor alert is set when triggering (non-NMI) exceptions: + //- instruction access fault + //- illegal instruction fault + //- load access fault + //- store/AMO access fault + //- instruction bus fault + + a_xsecure_security_alert_non_nmi_exceptions: assert property ( + triggering_minor_alert_due_to_non_nmi_exceptions + |=> + alert_minor + + //By entering debug we will not trigger exceptions + || $rose(debug_mode) + + ) else `uvm_error(info_tag, "Exception does not set the minor alert.\n"); + + + //Verify that minor alert is set when handeling a triggered store/load bus fault NMI + //If there is an NMI fault, but there is a NMI that is not yet handeld, the NMI-status is not updated. + + property p_set_nmip_no_integrity; + + obi_data_rvalid + && obi_data_err + && !support_if.data_req_had_integrity + + |=> + $rose(nmip) || $past(nmip); + + endproperty + + property p_nmip_no_integrity; + + obi_data_rvalid + && obi_data_err + && !support_if.data_req_had_integrity + ##1 $rose(nmip) + + //Wait for the pending NMI to be handeled + ##1 (!nmip)[->1] + + |-> + alert_minor; + + endproperty + + a_xsecure_security_alert_nmi_no_integrity: assert property ( + p_set_nmip_no_integrity + and p_nmip_no_integrity + ) else `uvm_error(info_tag, "A store/load bus fault NMI does not set the alert minor when the NMI is handeled.\n"); + + + //Verify that minor alert is set only due to the LFSR lockup detections, the exceptions listed above, and NMI fault due to buss error without integrity + + a_xsecure_security_alert_minor_reasons: assert property ( + + alert_minor + + |-> + ($past(lfsr0_n) == '0 + || $past(lfsr1_n) == '0 + || $past(lfsr2_n) == '0 + || $past(seed0_i) == '0 + || $past(seed1_i) == '0 + || $past(seed2_i) == '0) + + or $past(triggering_minor_alert_due_to_non_nmi_exceptions) + + or $past(nmip) + + ) else `uvm_error(info_tag, "TODO!.\n"); + + + //Verify that the major alert is never set + + a_xsecure_security_alert_major: assert property ( + !alert_major + ) else `uvm_error(info_tag, "The mjor alert is set even though there should be no glitches.\n"); + + endmodule : uvmt_cv32e40s_xsecure_security_alerts_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_zc_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_zc_assert.sv new file mode 100644 index 0000000000..9cf4a443d9 --- /dev/null +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_zc_assert.sv @@ -0,0 +1,109 @@ +// +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs +// +// Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +module uvmt_cv32e40s_zc_assert + import uvm_pkg::*; + import uvma_rvfi_pkg::*; + import cv32e40s_pkg::*; + ( + uvma_rvfi_instr_if_t rvfi, + uvmt_cv32e40s_support_logic_module_o_if_t.slave_mp support_if + ); + + + // --------------------------------------------------------------------------- + // Local parameters + // --------------------------------------------------------------------------- +`ifndef DSIM + localparam PUSH_POP_INSTR_MASK = 32'h FFFF_FF03; + localparam PUSH_INSTR_REF = 32'h 0000_B802; + localparam POP_INSTR_REF = 32'h 0000_BA02; + localparam POPRET_INSTR_REF = 32'h 0000_BE02; + localparam POPRETZ_INSTR_REF = 32'h 0000_BC02; + + localparam MVA_INSTR_MASK = 32'h FFFF_FC63; + localparam MVA01S_INSTR_REF = 32'h 0000_AC62; + localparam MVSA01_INSTR_REF = 32'h 0000_AC22; +`else // DSIM + // As of DSIM version 20220822.0.0 or earlier, the DSIM User Guide reports + // the following "known issue": + // Only variables, nets, expressions and event expressions can be passed as + // arguments to named sequences and properties. Arguments or local variables + // of type sequence or property are not yet supported. + int PUSH_POP_INSTR_MASK = 32'h FFFF_FF03; + int PUSH_INSTR_REF = 32'h 0000_B802; + int POP_INSTR_REF = 32'h 0000_BA02; + int POPRET_INSTR_REF = 32'h 0000_BE02; + int POPRETZ_INSTR_REF = 32'h 0000_BC02; + + int MVA_INSTR_MASK = 32'h FFFF_FC63; + int MVA01S_INSTR_REF = 32'h 0000_AC62; + int MVSA01_INSTR_REF = 32'h 0000_AC22; +`endif // DSIM + + + + // --------------------------------------------------------------------------- + // Local variables + // --------------------------------------------------------------------------- + string info_tag = "CV32E40S_ZC_ASSERT"; + + + // --------------------------------------------------------------------------- + // Clocking blocks + // --------------------------------------------------------------------------- + + // Single clock, single reset design, use default clocking + default clocking @(posedge rvfi.clk); endclocking + default disable iff !(rvfi.reset_n); + + + // --------------------------------------- + // Assertions + // --------------------------------------- + + // Asserting that when a suboperation causes an exception, + // no subsequent suboperation of the instruction causes + // any activity on the data bus + property p_multiop_exception_stop_dbus(logic[31:0] ins_mask, logic[31:0] ins_ref); + (rvfi.rvfi_valid && rvfi.rvfi_trap[0] && rvfi.match_instr(ins_ref, ins_mask)) + |-> + support_if.req_after_exception == 0; + + endproperty + + a_multiop_exception_stop_dbus_push : assert property(p_multiop_exception_stop_dbus(PUSH_POP_INSTR_MASK, PUSH_INSTR_REF)) + else `uvm_error(info_tag, "Activity on dbus after exception during push instruction"); + + a_multiop_exception_stop_dbus_pop : assert property(p_multiop_exception_stop_dbus(PUSH_POP_INSTR_MASK, POP_INSTR_REF)) + else `uvm_error(info_tag, "Activity on dbus after exception during pop instruction"); + + a_multiop_exception_stop_dbus_popretz : assert property(p_multiop_exception_stop_dbus(PUSH_POP_INSTR_MASK, POPRETZ_INSTR_REF)) + else `uvm_error(info_tag, "Activity on dbus after exception during popretz instruction"); + + a_multiop_exception_stop_dbus_popret : assert property(p_multiop_exception_stop_dbus(PUSH_POP_INSTR_MASK, POPRET_INSTR_REF)) + else `uvm_error(info_tag, "Activity on dbus after exception during popret instruction"); + + a_multiop_exception_stop_dbus_mvsa01 : assert property(p_multiop_exception_stop_dbus(MVA_INSTR_MASK, MVSA01_INSTR_REF)) + else `uvm_error(info_tag, "Activity on dbus after exception during mvsa01 instruction"); + + a_multiop_exception_stop_dbus_mva01s : assert property(p_multiop_exception_stop_dbus(MVA_INSTR_MASK, MVA01S_INSTR_REF)) + else `uvm_error(info_tag, "Activity on dbus after exception during mva01s instruction"); + + + +endmodule : uvmt_cv32e40s_zc_assert diff --git a/cv32e40s/tests/asm/user_define.h b/cv32e40s/tests/asm/user_define.h index 1e2a93fd0e..ba149eeeba 100644 --- a/cv32e40s/tests/asm/user_define.h +++ b/cv32e40s/tests/asm/user_define.h @@ -1,5 +1,8 @@ # Google UVM Generated Test -# Extracted from riscv_compliance_tests/riscv_test.h +# Extracted from riscv_compliance_tests/riscv_test.h, then modified + +#include "corev_uvmt.h" + .set print_port, 0x00800000 .set test_ret_val, 0x008000c0 .section .data diff --git a/cv32e40s/tests/cfg/b_ext_abs.yaml b/cv32e40s/tests/cfg/b_ext_abs.yaml index 6f0c2e206c..da8d0eeddf 100644 --- a/cv32e40s/tests/cfg/b_ext_abs.yaml +++ b/cv32e40s/tests/cfg/b_ext_abs.yaml @@ -3,12 +3,173 @@ description: Enables the B extensions ZBA_ZBB_ZBS in the cv32e40s compile_flags: +define+ZBA_ZBB_ZBS ovpsim: > + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 # --showoverrides # --trace --tracechange --traceshowicount --monitornets cflags: > -riscv_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbs1p00 + -Wl,--nmagic +cv_sw_march: rv32im_zba1p00_zbb1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/b_ext_all.yaml b/cv32e40s/tests/cfg/b_ext_all.yaml index 3b2ce27568..72cc67f585 100644 --- a/cv32e40s/tests/cfg/b_ext_all.yaml +++ b/cv32e40s/tests/cfg/b_ext_all.yaml @@ -1,14 +1,175 @@ name: b_ext_all description: Enables the B extensions ZBA_ZBB_ZBC_ZBS in the cv32e40s -compile_flags: +compile_flags: +define+ZBA_ZBB_ZBC_ZBS ovpsim: > + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 # --showoverrides # --trace --tracechange --traceshowicount --monitornets cflags: > -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 + -Wl,--nmagic +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/clic_default.yaml b/cv32e40s/tests/cfg/clic_default.yaml new file mode 100644 index 0000000000..a1906d591e --- /dev/null +++ b/cv32e40s/tests/cfg/clic_default.yaml @@ -0,0 +1,36 @@ +name: clic_default +description: Default clic configuration for CV32E40S simulations +compile_flags: + +define+ZBA_ZBB_ZBC_ZBS + +define+CLIC_EN + +define+PMP_ENABLE_64 +ovpsim: > + --override cpu/hpmcounter_undefined=T + --override cpu/CLICLEVELS=256 + --override cpu/CLICXCSW=T + --override cpu/CLICXNXTI=T + --override cpu/CLICSELHVEC=T + --override cpu/CLICINTCTLBITS=8 + --override cpu/CLIC_version=master + --override cpu/externalCLIC=T + --override cpu/PMP_registers=64 + --override cpu/mtvt_mask=0xffffffffffffff80 + #--trace + #--tracechange + #--showoverrides + # --trace --tracechange --traceshowicount --monitornets +cflags: > + -Wl,--nmagic +plusargs: > + +enable_clic=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 + +fix_ra=1 + +fix_sp=1 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zca_zcb_zcmp_zcmt_zicsr_zifencei diff --git a/cv32e40s/tests/cfg/debug_trigger_cfg0.yaml b/cv32e40s/tests/cfg/debug_trigger_cfg0.yaml new file mode 100644 index 0000000000..bd1e521c43 --- /dev/null +++ b/cv32e40s/tests/cfg/debug_trigger_cfg0.yaml @@ -0,0 +1,18 @@ +name: debug_trigger_cfg0 +description: Configuration for 0 triggers in CV32E40S simulations +compile_flags: > + +define+PMP_ENABLE_64 + +define+DBG_NUM_TRIG_0 + +define+ZBA_ZBB_ZBC_ZBS +ovpsim: > + --override cpu/trigger_num=0 + --override cpu/PMP_registers=64 + # --showoverrides +cflags: > + -Wl,--nmagic +plusargs: > + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/debug_trigger_cfg1.yaml b/cv32e40s/tests/cfg/debug_trigger_cfg1.yaml new file mode 100644 index 0000000000..ba2bb1d5e6 --- /dev/null +++ b/cv32e40s/tests/cfg/debug_trigger_cfg1.yaml @@ -0,0 +1,18 @@ +name: debug_trigger_cfg1 +description: Configuration for 1 trigger in CV32E40S simulations +compile_flags: > + +define+PMP_ENABLE_64 + +define+DBG_NUM_TRIG_1 + +define+ZBA_ZBB_ZBC_ZBS +ovpsim: > + --override cpu/trigger_num=1 + --override cpu/PMP_registers=64 + # --showoverrides +cflags: > + -Wl,--nmagic +plusargs: > + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/debug_trigger_cfg2.yaml b/cv32e40s/tests/cfg/debug_trigger_cfg2.yaml new file mode 100644 index 0000000000..ff839721c3 --- /dev/null +++ b/cv32e40s/tests/cfg/debug_trigger_cfg2.yaml @@ -0,0 +1,18 @@ +name: debug_trigger_cfg2 +description: Configuration for 2 triggers in CV32E40S simulations +compile_flags: > + +define+PMP_ENABLE_64 + +define+DBG_NUM_TRIG_2 + +define+ZBA_ZBB_ZBC_ZBS +ovpsim: > + --override cpu/trigger_num=2 + --override cpu/PMP_registers=64 + # --showoverrides +cflags: > + -Wl,--nmagic +plusargs: > + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/debug_trigger_cfg3.yaml b/cv32e40s/tests/cfg/debug_trigger_cfg3.yaml new file mode 100644 index 0000000000..f18736309f --- /dev/null +++ b/cv32e40s/tests/cfg/debug_trigger_cfg3.yaml @@ -0,0 +1,18 @@ +name: debug_trigger_cfg3 +description: Configuration for 3 triggers in CV32E40S simulations +compile_flags: > + +define+PMP_ENABLE_64 + +define+DBG_NUM_TRIG_3 + +define+ZBA_ZBB_ZBC_ZBS +ovpsim: > + --override cpu/trigger_num=3 + --override cpu/PMP_registers=64 + # --showoverrides +cflags: > + -Wl,--nmagic +plusargs: > + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/debug_trigger_cfg4.yaml b/cv32e40s/tests/cfg/debug_trigger_cfg4.yaml new file mode 100644 index 0000000000..3ca9674dcf --- /dev/null +++ b/cv32e40s/tests/cfg/debug_trigger_cfg4.yaml @@ -0,0 +1,18 @@ +name: debug_trigger_cfg4 +description: Configuration for 4 triggers in CV32E40S simulations +compile_flags: > + +define+PMP_ENABLE_64 + +define+DBG_NUM_TRIG_4 + +define+ZBA_ZBB_ZBC_ZBS +ovpsim: > + --override cpu/trigger_num=4 + --override cpu/PMP_registers=64 + # --showoverrides +cflags: > + -Wl,--nmagic +plusargs: > + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/default.yaml b/cv32e40s/tests/cfg/default.yaml index 37b1ea1774..0c0ab5aae5 100644 --- a/cv32e40s/tests/cfg/default.yaml +++ b/cv32e40s/tests/cfg/default.yaml @@ -1,20 +1,97 @@ name: default description: Default configuration for CV32E40S simulations -compile_flags: -#TODO:ropeders un-comment when ISS is patched +define+ZBA_ZBB_ZBC_ZBS +compile_flags: > + +define+ZBA_ZBB_ZBC_ZBS ovpsim: > - # --showoverrides - # --trace --tracechange --traceshowicount --monitornets + --override cpu/envcfg_mask=0x0 + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/hpmcounter_undefined=T + --override cpu/PMP_registers=64 + --override cpu/PMP_grain=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + #--showoverrides + #--trace + #--trace --tracechange --traceshowicount --monitornets cflags: > + -Wl,--nmagic plusargs: > - #TODO:ropeders un-comment when ISS is patched +enable_zba_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbb_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbc_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbs_extension=1 -cv_sw_march: rv32imc -#TODO:ropeders un-comment when ISS is patched cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -# Note: the following are depreciated -#riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 + +fix_sp=1 + +fix_ra=1 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + #+gen_wfe_wu_noise=1 + #+enable_write_pmp_csr=1 + #+pmp_randomize=0 + #+pmp_num_regions=64 + #+pmp_granularity=0 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/dummy_instr.yaml b/cv32e40s/tests/cfg/dummy_instr.yaml new file mode 100644 index 0000000000..3ce8fb8507 --- /dev/null +++ b/cv32e40s/tests/cfg/dummy_instr.yaml @@ -0,0 +1,200 @@ +name: dummy_instr +description: Default configuration for CV32E40S simulations that includes dummy instructions +compile_flags: + +define+ZBA_ZBB_ZBC_ZBS + +define+CLIC_EN + +define+PMP_ENABLE_64 + +define+LFSR_CFG_0 +plusargs: > + +enable_clic=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 + +fix_sp=1 + +fix_ra=1 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +enable_dummy=1 + +enable_hint=1 +ovpsim: > + --override cpu/CLICLEVELS=256 + --override cpu/CLICXCSW=T + --override cpu/CLICXNXTI=T + --override cpu/CLICSELHVEC=T + --override cpu/CLICINTCTLBITS=8 + --override cpu/CLIC_version=master + --override cpu/externalCLIC=T + --override cpu/mtvt_mask=0xffffffffffffff80 + --override cpu/PMP_registers=64 + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 + # --showoverrides + # --trace --tracechange --traceshowicount --monitornets +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zicsr_zba1p00_zbb1p00_zbc1p00_zbs1p00_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/no_bitmanip.yaml b/cv32e40s/tests/cfg/no_bitmanip.yaml deleted file mode 100644 index f3d50206d1..0000000000 --- a/cv32e40s/tests/cfg/no_bitmanip.yaml +++ /dev/null @@ -1,2 +0,0 @@ -name: no_bitmanip -description: Default configuration for CV32E40S simulations diff --git a/cv32e40s/tests/cfg/num_mhpmcounter_29.yaml b/cv32e40s/tests/cfg/num_mhpmcounter_29.yaml deleted file mode 100644 index c3c670177c..0000000000 --- a/cv32e40s/tests/cfg/num_mhpmcounter_29.yaml +++ /dev/null @@ -1,6 +0,0 @@ -name: num_mhpmcounters_29 -description: Configuration for CV32E40S simulations with NUM_MHPMCOUNTER set to 29 -compile_flags: - +define+SET_NUM_MHPMCOUNTERS=29 -ovpsim: > -cflags: > diff --git a/cv32e40s/tests/cfg/param_set_0.yaml b/cv32e40s/tests/cfg/param_set_0.yaml new file mode 100644 index 0000000000..6f07fc3c68 --- /dev/null +++ b/cv32e40s/tests/cfg/param_set_0.yaml @@ -0,0 +1,8 @@ +name: param_set_0 +description: > + Compile with external parameter configuration. + USER_COMPILE_FLAGS="+incdir+path_to_your_param_set_0_directory" + Tests will fail, but you get the coverage model and data. +compile_flags: > + +define+PARAM_SET_0 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/pma.yaml b/cv32e40s/tests/cfg/pma.yaml index eb1ac12e5b..57af372db8 100644 --- a/cv32e40s/tests/cfg/pma.yaml +++ b/cv32e40s/tests/cfg/pma.yaml @@ -2,4 +2,10 @@ name: pma description: PMA configuration for regions and attributes compile_flags: +define+PMA_CUSTOM_CFG - +ovpsim: > + --override cpu/PMP_registers=64 + # --showoverrides + # --trace --tracechange --traceshowicount --monitornets +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/pma_debug.yaml b/cv32e40s/tests/cfg/pma_debug.yaml index 8fdc13a034..047fab9d75 100644 --- a/cv32e40s/tests/cfg/pma_debug.yaml +++ b/cv32e40s/tests/cfg/pma_debug.yaml @@ -2,3 +2,10 @@ name: pma description: PMA configuration for pma_debug test compile_flags: +define+PMA_DEBUG_CFG +ovpsim: > + --override cpu/PMP_registers=64 + # --showoverrides + # --trace --tracechange --traceshowicount --monitornets +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/pma_test_cfg_1.yaml b/cv32e40s/tests/cfg/pma_test_cfg_1.yaml index b434af2b28..f9e234d6af 100644 --- a/cv32e40s/tests/cfg/pma_test_cfg_1.yaml +++ b/cv32e40s/tests/cfg/pma_test_cfg_1.yaml @@ -1,18 +1,189 @@ name: pma_test_cfg_1 description: PMA configuration for the PMA_TEST_CFG_1 test case -compile_flags: +compile_flags: > +define+PMA_TEST_CFG_1 - #TODO:ropeders un-comment when ISS is patched +define+ZBA_ZBB_ZBC_ZBS -plusargs: + +define+ZBA_ZBB_ZBC_ZBS +plusargs: > +enable_pma=1 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +fix_ra=1 +fix_sp=1 - #TODO:ropeders un-comment when ISS is patched +enable_zba_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbb_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbc_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#TODO:ropeders un-comment when ISS is patched cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +ovpsim: > + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 + #--showoverrides + #--trace + #--tracechange + #--trace --tracechange --traceshowicount --monitornetschange +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/pma_test_cfg_2.yaml b/cv32e40s/tests/cfg/pma_test_cfg_2.yaml index 0cfe605096..0edf69a0db 100644 --- a/cv32e40s/tests/cfg/pma_test_cfg_2.yaml +++ b/cv32e40s/tests/cfg/pma_test_cfg_2.yaml @@ -1,18 +1,185 @@ name: pma_test_cfg_2 description: PMA configuration for the PMA_TEST_CFG_2 test case -compile_flags: +compile_flags: > +define+PMA_TEST_CFG_2 - #TODO:ropeders un-comment when ISS is patched +define+ZBA_ZBB_ZBC_ZBS -plusargs: + +define+ZBA_ZBB_ZBC_ZBS +plusargs: > +enable_pma=1 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +fix_ra=1 +fix_sp=1 - #TODO:ropeders un-comment when ISS is patched +enable_zba_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbb_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbc_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#TODO:ropeders un-comment when ISS is patched cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +ovpsim: > + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/pma_test_cfg_3.yaml b/cv32e40s/tests/cfg/pma_test_cfg_3.yaml index 20328e550d..c861a4e657 100644 --- a/cv32e40s/tests/cfg/pma_test_cfg_3.yaml +++ b/cv32e40s/tests/cfg/pma_test_cfg_3.yaml @@ -1,22 +1,188 @@ name: pma_test_cfg_3 description: PMA configuration for the PMA_TEST_CFG_3 test case -compile_flags: +compile_flags: > +define+PMA_TEST_CFG_3 - #TODO:ropeders un-comment when ISS is patched +define+ZBA_ZBB_ZBC_ZBS -plusargs: + +define+ZBA_ZBB_ZBC_ZBS +plusargs: > +enable_pma=1 +boot_addr=0x48000080 +mtvec_addr=0x48000000 - +nmi_addr=0x48100000 +enable_large_mem_support=0 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +fix_ra=1 +fix_sp=1 - #TODO:ropeders un-comment when ISS is patched +enable_zba_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbb_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbc_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#TODO:ropeders un-comment when ISS is patched cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +ovpsim: > + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/pma_test_cfg_4.yaml b/cv32e40s/tests/cfg/pma_test_cfg_4.yaml index 1e4a8f1731..434a09a393 100644 --- a/cv32e40s/tests/cfg/pma_test_cfg_4.yaml +++ b/cv32e40s/tests/cfg/pma_test_cfg_4.yaml @@ -1,23 +1,189 @@ name: pma_test_cfg_4 description: PMA configuration for the PMA_TEST_CFG_4 test case -compile_flags: +compile_flags: > +define+PMA_TEST_CFG_4 - #TODO:ropeders un-comment when ISS is patched +define+ZBA_ZBB_ZBC_ZBS -plusargs: + +define+ZBA_ZBB_ZBC_ZBS +plusargs: > +enable_pma=1 +boot_addr=0x10080 +mtvec_addr=0x10000 - +nmi_addr=0xbc000100 +dm_halt_addr=0x32010000 +dm_exception_addr=0x32010800 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +fix_ra=1 +fix_sp=1 - #TODO:ropeders un-comment when ISS is patched +enable_zba_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbb_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbc_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#TODO:ropeders un-comment when ISS is patched cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +ovpsim: > + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/pma_test_cfg_5.yaml b/cv32e40s/tests/cfg/pma_test_cfg_5.yaml index f08d1cefc1..aa009b2440 100644 --- a/cv32e40s/tests/cfg/pma_test_cfg_5.yaml +++ b/cv32e40s/tests/cfg/pma_test_cfg_5.yaml @@ -1,21 +1,188 @@ name: pma_test_cfg_5 description: PMA configuration for the PMA_TEST_CFG_5 test case -compile_flags: +compile_flags: > +define+PMA_TEST_CFG_5 - #TODO:ropeders un-comment when ISS is patched +define+ZBA_ZBB_ZBC_ZBS -plusargs: + +define+ZBA_ZBB_ZBC_ZBS +plusargs: > +enable_pma=1 +boot_addr=0x80 - +fix_sp=1 +dm_halt_addr=0x301000 +dm_exception_addr=0x301800 - #TODO:ropeders un-comment when ISS is patched +enable_zba_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbb_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbc_extension=1 - #TODO:ropeders un-comment when ISS is patched +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#TODO:ropeders un-comment when ISS is patched cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +fix_ra=1 + +fix_sp=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +ovpsim: > + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/pmp.yaml b/cv32e40s/tests/cfg/pmp.yaml new file mode 100644 index 0000000000..7f826b74a7 --- /dev/null +++ b/cv32e40s/tests/cfg/pmp.yaml @@ -0,0 +1,19 @@ +name: pmp +description: Default pmp configuration for CV32E40S simulations +compile_flags: > + +define+PMP_ENABLE_64 + +define+ZBA_ZBB_ZBC_ZBS +ovpsim: > + --override cpu/hpmcounter_undefined=T + --override cpu/PMP_registers=64 + --override cpu/PMP_grain=0 + #--showoverrides + #--trace +cflags: > + -Wl,--nmagic +plusargs: > + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/pmp_g3r3.yaml b/cv32e40s/tests/cfg/pmp_g3r3.yaml new file mode 100644 index 0000000000..904540dc7b --- /dev/null +++ b/cv32e40s/tests/cfg/pmp_g3r3.yaml @@ -0,0 +1,179 @@ +name: pmp_g3r3 +description: pmp config with GRANULARITY=3 and NUM_REGIONS=3 +compile_flags: + +define+PMP_G3R3 + +define+ZBA_ZBB_ZBC_ZBS +ovpsim: > + --override cpu/PMP_grain=3 + --override cpu/PMP_registers=64 + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0x00FFFFFF + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0xFFFFFFFF + --override cpu/mask_pmpaddr1=0xFFFFFFFF + --override cpu/mask_pmpaddr2=0xFFFFFFFF + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 + #--showoverrides +cflags: > + -Wl,--nmagic +plusargs: > + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zifencei diff --git a/cv32e40s/tests/cfg/xsecure_disable_std.yaml b/cv32e40s/tests/cfg/xsecure_disable_std.yaml new file mode 100644 index 0000000000..a96cdb4db4 --- /dev/null +++ b/cv32e40s/tests/cfg/xsecure_disable_std.yaml @@ -0,0 +1,202 @@ +name: xsecure_disable_std +description: Default configuration for CV32E40S random simulations that includes dummy instructions but disables pc hardening and data independent timing features +compile_flags: + +define+ZBA_ZBB_ZBC_ZBS + +define+CLIC_EN + +define+PMP_ENABLE_64 + +define+LFSR_CFG_0 +plusargs: > + +enable_clic=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 + +fix_sp=1 + +fix_ra=1 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +enable_dummy=1 + +enable_hint=1 + +disable_data_independent_timing=1 + +disable_pc_hardening=1 +ovpsim: > + --override cpu/CLICLEVELS=256 + --override cpu/CLICXCSW=T + --override cpu/CLICXNXTI=T + --override cpu/CLICSELHVEC=T + --override cpu/CLICINTCTLBITS=8 + --override cpu/CLIC_version=master + --override cpu/externalCLIC=T + --override cpu/mtvt_mask=0xffffffffffffff80 + --override cpu/PMP_registers=64 + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 + # --showoverrides + # --trace --tracechange --traceshowicount --monitornets +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zicsr_zba1p00_zbb1p00_zbc1p00_zbs1p00_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_arithmetic_base_test/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_arithmetic_base_test/test.yaml index 8f080c0472..4090bdbbed 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_arithmetic_base_test/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_arithmetic_base_test/test.yaml @@ -4,4 +4,5 @@ name: corev_rand_arithmetic_base_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Math test generated by corev-dv +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/corev-dv.yaml index d6b53a5a0d..c623bf4ad5 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/corev-dv.yaml @@ -15,10 +15,12 @@ plusargs: > +directed_instr_5=riscv_mem_region_stress_test,4 +directed_instr_6=riscv_jal_instr,4 +directed_instr_7=corev_xori_not_instr,1 + +directed_instr_8=corev_zcmp_pushpop_base_stream,4 + +directed_instr_9=corev_zcmt_base_stream,4 +hint_instr_ratio=2 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +enable_interrupt=1 +enable_fast_interrupt_handler=1 +no_wfi=1 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/test.yaml index f6a656c84f..e7dafe03db 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err/test.yaml @@ -9,3 +9,5 @@ plusargs: > +obi_memory_data_random_err_enabled +obi_memory_data_one_shot_err_enabled +gen_irq_noise + +nmi_timeout_instr=1000 +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/corev-dv.yaml index a907ed74df..8da13976d7 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/corev-dv.yaml @@ -13,10 +13,12 @@ plusargs: > +directed_instr_5=riscv_mem_region_stress_test,4 +directed_instr_6=riscv_jal_instr,4 +directed_instr_7=corev_xori_not_instr,1 + +directed_instr_8=corev_zcmp_pushpop_base_stream,4 + +directed_instr_9=corev_zcmt_base_stream,4 +hint_instr_ratio=2 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +enable_interrupt=1 +enable_fast_interrupt_handler=1 +no_wfi=0 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml index f4541fd191..467563d1ea 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml @@ -8,3 +8,8 @@ plusargs: > +obi_memory_data_one_shot_err_enabled +gen_irq_noise +gen_random_debug + +nmi_timeout_instr=1000 + +irq_single_step_threshold=500 + +irq_min_limit=100 + +single_step_min_limit=100 +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_debug/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_debug/test.yaml index 2c848cd4ac..86d11bb9b8 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_debug/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_debug/test.yaml @@ -7,3 +7,4 @@ description: > Random debug generator test plusargs: > +gen_random_debug +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/corev-dv.yaml index 7a844ff1e6..dade52f5e4 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/corev-dv.yaml @@ -10,7 +10,7 @@ plusargs: > +no_data_page=1 +no_branch_jump=0 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +no_wfi=0 +no_ebreak=0 +no_dret=1 @@ -21,4 +21,4 @@ plusargs: > +gen_debug_section=1 +num_debug_sub_program=0 +illegal_instr_ratio=2 - +enable_illegal_csr_instruction=1 \ No newline at end of file + +enable_illegal_csr_instruction=1 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/test.yaml index efa0f580da..1624c2d92a 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_debug_ebreak/test.yaml @@ -4,3 +4,4 @@ description: > Random debug generator test with ebreak in debug ROM supported plusargs: > +gen_random_debug +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_debug_single_step/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_debug_single_step/test.yaml index 8c2c1b6762..62524d7f0c 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_debug_single_step/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_debug_single_step/test.yaml @@ -4,3 +4,4 @@ description: > Random debug generator test with single-stepping supported in the debug ROM plusargs: > +gen_random_debug +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_fencei/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_fencei/test.yaml index 0296bbd835..1e520aec73 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_fencei/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_fencei/test.yaml @@ -3,3 +3,4 @@ name: corev_rand_fencei uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: RISCV-DV generated random fencei test +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/corev-dv.yaml index 4b65e2d94a..0700a8710f 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/corev-dv.yaml @@ -12,6 +12,8 @@ plusargs: > +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 +directed_instr_5=riscv_mem_region_stress_test,4 +directed_instr_6=riscv_jal_instr,4 + +directed_instr_7=corev_zcmp_pushpop_base_stream,4 + +directed_instr_8=corev_zcmt_base_stream,4 +illegal_instr_ratio=10 +hint_instr_ratio=5 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/test.yaml index d391bd59ca..b385e314e3 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_illegal_instr_test/test.yaml @@ -2,3 +2,4 @@ name: corev_rand_illegal_instr_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Random instruction test generated by corev-dv with illegal instructions +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/corev-dv.yaml index 9d2039d7f3..14ebfb469e 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/corev-dv.yaml @@ -14,4 +14,6 @@ plusargs: > +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 +directed_instr_5=riscv_mem_region_stress_test,4 +directed_instr_6=riscv_jal_instr,4 + +directed_instr_7=corev_zcmp_pushpop_base_stream,4 + +directed_instr_8=corev_zcmt_base_stream,4 +hint_instr_ratio=2 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/test.yaml index b7a8a1c392..c01200637e 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_long_stall/test.yaml @@ -7,3 +7,4 @@ description: > plusargs: > +random_fetch_toggle +max_data_zero_instr_stall +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/corev-dv.yaml index 7275f0a61f..be7a28cc01 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/corev-dv.yaml @@ -15,10 +15,12 @@ plusargs: > +directed_instr_5=riscv_mem_region_stress_test,4 +directed_instr_6=riscv_jal_instr,4 +directed_instr_7=corev_xori_not_instr,1 + +directed_instr_8=corev_zcmp_pushpop_base_stream,4 + +directed_instr_9=corev_zcmt_base_stream,4 +hint_instr_ratio=2 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +enable_interrupt=1 +enable_fast_interrupt_handler=1 +no_wfi=0 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/test.yaml index 0c9d538f9c..d85d8335b5 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err/test.yaml @@ -9,3 +9,5 @@ plusargs: > +obi_memory_instr_random_err_enabled +obi_memory_instr_one_shot_err_enabled +gen_irq_noise + +nmi_timeout_instr=1000 +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/corev-dv.yaml index c686844945..3d0d7e5ec1 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/corev-dv.yaml @@ -3,7 +3,7 @@ uvm_test: $(CV_CORE_LC)_instr_base_test description: > RISCV-DV generated test with OBI instruction bus errors in debug mode plusargs: > - +instr_cnt=10000 + +instr_cnt=5000 +num_of_sub_program=6 +directed_instr_0=riscv_load_store_rand_instr_stream,4 +directed_instr_1=riscv_loop_instr,4 @@ -13,10 +13,12 @@ plusargs: > +directed_instr_5=riscv_mem_region_stress_test,4 +directed_instr_6=riscv_jal_instr,4 +directed_instr_7=corev_xori_not_instr,1 + +directed_instr_8=corev_zcmp_pushpop_base_stream,4 + +directed_instr_9=corev_zcmt_base_stream,4 +hint_instr_ratio=2 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +enable_interrupt=1 +enable_fast_interrupt_handler=1 +no_wfi=0 @@ -24,4 +26,4 @@ plusargs: > +set_dcsr_ebreak=0 +enable_debug_single_step=1 +gen_debug_section=1 - +exit_on_debug_exception=1 \ No newline at end of file + +exit_on_debug_exception=1 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/test.yaml index 272dcbcddd..e3f1827a6c 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/test.yaml @@ -8,3 +8,8 @@ plusargs: > +obi_memory_instr_one_shot_err_enabled +gen_irq_noise +gen_random_debug + +nmi_timeout_instr=1000 + +irq_single_step_threshold=500 + +irq_min_limit=100 + +single_step_min_limit=100 +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/corev-dv.yaml index 10893460cf..642059b179 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/corev-dv.yaml @@ -15,4 +15,6 @@ plusargs: > +directed_instr_5=riscv_mem_region_stress_test,4 +directed_instr_6=riscv_jal_instr,4 +directed_instr_7=corev_xori_not_instr,1 + +directed_instr_8=corev_zcmp_pushpop_base_stream,4 + +directed_instr_9=corev_zcmt_base_stream,4 +hint_instr_ratio=2 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/test.yaml index f68eeb1ce4..e9bf4fb6df 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_instr_test/test.yaml @@ -6,3 +6,4 @@ description: > Random instruction test generated by corev-dv plusargs: > +random_fetch_toggle +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/corev-dv.yaml index 917e9c7ad0..95c87230d9 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/corev-dv.yaml @@ -11,9 +11,11 @@ plusargs: > +directed_instr_3=riscv_hazard_instr_stream,1 +directed_instr_4=riscv_jal_instr,3 +directed_instr_5=corev_interrupt_csr_instr_stream,3 + +directed_instr_6=corev_zcmp_pushpop_base_stream,4 + +directed_instr_7=corev_zcmt_base_stream,4 +no_fence=0 +enable_interrupt=1 +enable_fast_interrupt_handler=1 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/test.yaml index bac22a4de1..f387e411af 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt/test.yaml @@ -6,4 +6,5 @@ uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Random interrupt generator test plusargs: > - +gen_irq_noise \ No newline at end of file + +gen_irq_noise +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_debug/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_debug/test.yaml index efcd4c293a..e5344f66cf 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_debug/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_debug/test.yaml @@ -9,4 +9,4 @@ plusargs: > +gen_irq_noise +reset_debug +gen_random_debug - +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/corev-dv.yaml index 8b14f38549..283822aaac 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/corev-dv.yaml @@ -17,7 +17,7 @@ plusargs: > +enable_fast_interrupt_handler=1 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +no_ebreak=0 +no_dret=0 +gen_debug_section=1 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/test.yaml index 03142a613c..39c1e43244 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_exception/test.yaml @@ -7,3 +7,4 @@ description: > Random interrupt generator test with exceptions plusargs: > +gen_irq_noise +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/corev-dv.yaml index 9fb13d12b9..e3a1e28d88 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/corev-dv.yaml @@ -17,4 +17,4 @@ plusargs: > +no_wfi=1 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/test.yaml index e6f65ba0e4..ee3c59c09f 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_nested/test.yaml @@ -4,3 +4,4 @@ description: > Random interrupt generator test with nested interrupts plusargs: > +gen_irq_noise +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/corev-dv.yaml index 628f198123..f2d32e5624 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/corev-dv.yaml @@ -16,7 +16,7 @@ plusargs: > +disable_compressed_instr=0 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +enable_interrupt=1 +enable_fast_interrupt_handler=1 +no_wfi=0 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/test.yaml index a5044e958c..e129aec3e6 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi/test.yaml @@ -4,3 +4,4 @@ description: > Random interrupt generator test with WFI plusargs: > +gen_irq_noise +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/corev-dv.yaml index 5b1301d212..fa3150085b 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/corev-dv.yaml @@ -12,7 +12,7 @@ plusargs: > +disable_compressed_instr=0 +randomize_csr=1 +boot_mode=m - +no_csr_instr=0 + +no_csr_instr=1 +enable_interrupt=1 +enable_fast_interrupt_handler=1 +no_wfi=0 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/test.yaml index e7480171c7..09f1c7289f 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/test.yaml @@ -4,3 +4,4 @@ description: > Random interrupt generator test with WFI plusargs: > +gen_irq_noise +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/corev-dv.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/corev-dv.yaml index be4675955c..842aab8686 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/corev-dv.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/corev-dv.yaml @@ -4,8 +4,12 @@ name: corev_rand_jump_stress_test uvm_test: $(CV_CORE_LC)_instr_base_test description: > RISCV-DV generated jump stress test +cflags: > + -mno-relax plusargs: > +instr_cnt=5000 +num_of_sub_program=5 +directed_instr_1=riscv_jal_instr,20 + +directed_instr_2=corev_zcmp_pushpop_base_stream,20 + +directed_instr_3=corev_zcmt_base_stream,20 diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/test.yaml index 5c1f28ca2e..6ab528f8cf 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_jump_stress_test/test.yaml @@ -4,3 +4,4 @@ name: corev_rand_jump_stress_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Jump stress test generated by corev-dv +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/test.yaml b/cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/test.yaml index db98912b05..b94c4720e9 100644 --- a/cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/test.yaml +++ b/cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/test.yaml @@ -6,3 +6,4 @@ description: > Random instruction test generated by corev-dv plusargs: > +random_fetch_toggle +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/b_ext_test/b_ext_test.c b/cv32e40s/tests/programs/custom/b_ext_test/b_ext_test.c index b80451d370..2042956dcd 100644 --- a/cv32e40s/tests/programs/custom/b_ext_test/b_ext_test.c +++ b/cv32e40s/tests/programs/custom/b_ext_test/b_ext_test.c @@ -1,5 +1,27 @@ +// +// Copyright 2021 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Tests Zb* extension instructions +// +///////////////////////////////////////////////////////////////////////////////// + #include +#include #include unsigned int test; @@ -20,6 +42,11 @@ int test_andn(void); int test_orn(void); int test_xnor(void); int test_rev8(void); +int test_sext(void); +int test_zexth(void); +int test_clmul(void); +int test_clmulh(void); +int test_clmulr(void); int test_bset(void); int test_bseti(void); int test_bclr(void); @@ -50,6 +77,12 @@ int main(int argc, char *argv[]) failures += test_orn(); failures += test_xnor(); failures += test_rev8(); + failures += test_sext(); + failures += test_zexth(); + // Zbc + failures += test_clmul(); + failures += test_clmulh(); + failures += test_clmulr(); // Zbs failures += test_bset(); failures += test_bseti(); @@ -255,12 +288,52 @@ int test_rev8(void){ return failures; } +int test_sext(void){ + int failures = 0; + + __asm__ volatile("addi t3, zero, 15"); // Store 15 in t3 + __asm__ volatile("sext.b t5, t3"); // Sign-extend the least significant byte in t3 by copying the most significant bit to all of the more significant bits. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 15 ) { + printf("ERROR, SEXTB result not as expected: %x\n", test); + failures++; + } + + + __asm__ volatile("addi t3, zero, 15"); // Store 15 in t3 + __asm__ volatile("sext.h t5, t3"); // Sign-extend the least significant halfword in t3 by copying the most significant bit to all of the more significant bits. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 15 ) { + printf("ERROR, SEXTH result not as expected: %x\n", test); + failures++; + } + + return failures; +} + +int test_zexth(void){ + int failures = 0; + + __asm__ volatile("addi t3, zero, 15"); // Store 15 in t3 + __asm__ volatile("zext.h t5, t3"); // Zero-extend the least significant halfword in t3 by inserting zeros to all of the more significant bits. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 15 ) { + printf("ERROR, ZEXTH result not as expected: %x\n", test); + failures++; + } + + return failures; +} + int test_rol(void){ int failures = 0; __asm__ volatile("addi t3, zero, 7"); // Store 7 in t3 __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("rol t5, t3, t4"); // ROtate Left + __asm__ volatile("rol t5, t3, t4"); // Rotate Left __asm__ volatile("sw t5, test, t0"); // Store t5 to test if (test != 14 ) { @@ -304,6 +377,7 @@ int test_rori(void){ return failures; } + int test_bset(void){ int failures = 0; @@ -422,7 +496,58 @@ int test_binvi(void){ return failures; } +int test_clmul(void){ + int failures = 0; + __asm__ volatile("addi t3, zero, 4"); // Store 4 in t3 + __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 + __asm__ volatile("clmul t5, t3, t4"); // Carry-less multiply (low-part) + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 4 ) { + printf("ERROR, CLMUL result not as expected\n"); + failures++; + } + + return failures; +} + +int test_clmulh(void){ + int failures = 0; + + + __asm__ volatile("lui t3, 16"); // Store 16 in the upper 20 bits of t3 + __asm__ volatile("addi t3, t3, 0"); // Store 0 in the lower 12 bits of t3 + __asm__ volatile("lui t4, 16"); // Store 16 in the upper 20 bits of t4 + __asm__ volatile("addi t4, t4, 0"); // Store 0 in the lower 12 bits of t4 + __asm__ volatile("clmulh t5, t3, t4"); // Carry-less multiply (high-part) + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 1 ) { + printf("ERROR, CLMULH result not as expected\n"); + failures++; + } + + return failures; +} + +int test_clmulr(void){ + int failures = 0; + + __asm__ volatile("lui t3, 16"); // Store 16 in the upper 20 bits of t3 + __asm__ volatile("addi t3, t3, 0"); // Store 0 in the lower 12 bits of t3 + __asm__ volatile("lui t4, 16"); // Store 16 in the upper 20 bits of t4 + __asm__ volatile("addi t4, t4, 0"); // Store 0 in the lower 12 bits of t4 + __asm__ volatile("clmulr t5, t3, t4"); // Find min + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 2 ) { + printf("ERROR, CLMULR result not as expected\n"); + failures++; + } + + return failures; +} int test_shnadd(void){ diff --git a/cv32e40s/tests/programs/custom/b_ext_test/test.yaml b/cv32e40s/tests/programs/custom/b_ext_test/test.yaml index dcd8934a23..2a3464b9f2 100644 --- a/cv32e40s/tests/programs/custom/b_ext_test/test.yaml +++ b/cv32e40s/tests/programs/custom/b_ext_test/test.yaml @@ -3,9 +3,4 @@ uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Simple sanity check for B extension instructions -# Toolchain configurations -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 pulp_not_supported: 1 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40s/tests/programs/custom/clic/clic.c b/cv32e40s/tests/programs/custom/clic/clic.c new file mode 100644 index 0000000000..e8e4d27b3d --- /dev/null +++ b/cv32e40s/tests/programs/custom/clic/clic.c @@ -0,0 +1,3219 @@ +// +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran +// +// CLIC CSR directed access tests +// - Tests proper mirroring of mpp/mpie +// - Tests mtvt/mtvec handling with shv pointer fetch exception +// - Tests read/write access, side effects of mnxti with and without interrupts +// - Tests read/write access to mscratchcsw* +// - Tests mintthresh settings with random interrupts +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 23 +// Set which test index to start testing at (for quickly running specific tests during development) +#define START_TEST_IDX 0 +// Abort test at first self-check fail, useful for debugging. +#define ABORT_ON_ERROR_IMMEDIATE 0 +#define CLIC_ID_WIDTH 5 +#define CLIC_LVL_WIDTH 8 +#define MTVEC_ALIGN_BITS 7 + +#define NUM_INTERRUPTS (1 << CLIC_ID_WIDTH) +#define NUM_INTERRUPT_LVLS (1 << CLIC_LVL_WIDTH) + +// Addresses of VP interrupt control registers +#define TIMER_REG_ADDR ((volatile uint32_t * volatile ) (CV_VP_INTR_TIMER_BASE)) +#define TIMER_VAL_ADDR ((volatile uint32_t * volatile ) (CV_VP_INTR_TIMER_BASE + 4)) +#define RANDOM_NUM_ADDR ((volatile uint32_t * volatile ) (CV_VP_RANDOM_NUM_BASE)) + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + +// --------------------------------------------------------------- +// Convenience macros for bit fields +// --------------------------------------------------------------- + +#define MSTATUS_MPP(v) \ + ((v & MSTATUS_MPP_MASK) >> MSTATUS_MPP_OFFSET) + +#define MSTATUS_MPIE(v) \ + ((v & MSTATUS_MPIE_MASK) >> MSTATUS_MPIE_OFFSET) + +#define MCAUSE_MPP(v) \ + ((v & MCAUSE_MPP_MASK) >> MCAUSE_MPP_OFFSET) + +#define MCAUSE_MPIE(v) \ + ((v & MCAUSE_MPIE_MASK) >> MCAUSE_MPIE_OFFSET) + +// Verbosity levels (Akin to the uvm verbosity concept) +typedef enum { + V_OFF = 0, + V_LOW = 1, + V_MEDIUM = 2, + V_HIGH = 3, + V_DEBUG = 4 +} verbosity_t; + +typedef enum { + OFF = 0, + TOR = 1, + NA4 = 2, + NAPOT = 3 +} pmp_mode_t; + +typedef struct { + volatile uint8_t reg_no; + volatile uint8_t lock; + volatile pmp_mode_t mode; + volatile uint8_t execute; + volatile uint8_t write; + volatile uint8_t read; +} pmpcfg_t; + +typedef struct { + volatile uint8_t rlb; + volatile uint8_t mmwp; + volatile uint8_t mml; +} mseccfg_t; + +typedef union { + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_30_12 : 19; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clint; + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_15_12 : 4; + volatile uint32_t mpil : 8; + volatile uint32_t res_26_24 : 3; + volatile uint32_t mpie : 1; + volatile uint32_t mpp : 2; + volatile uint32_t minhv : 1; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clic; + volatile uint32_t raw : 32; +} __attribute__((packed)) mcause_t; + +typedef union { + struct { + volatile uint32_t uil : 8; + volatile uint32_t sil : 8; + volatile uint32_t reserved_23_16 : 8; + volatile uint32_t mil : 8; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) mintstatus_t; + +typedef union { + struct { + volatile uint32_t th : 8; + volatile uint32_t reserved_31_8 : 24; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) mintthresh_t; + +typedef union { + struct { + volatile uint32_t uie : 1; // 0 + volatile uint32_t sie : 1; // 1 + volatile uint32_t wpri : 1; // 2 + volatile uint32_t mie : 1; // 3 + volatile uint32_t upie : 1; // 4 + volatile uint32_t spie : 1; // 5 + volatile uint32_t wpri0 : 1; // 6 + volatile uint32_t mpie : 1; // 7 + volatile uint32_t spp : 1; // 8 + volatile uint32_t wpri1 : 2; // 10: 9 + volatile uint32_t mpp : 2; // 12:11 + volatile uint32_t fs : 2; // 14:13 + volatile uint32_t xs : 2; // 16:15 + volatile uint32_t mprv : 1; // 17 + volatile uint32_t sum : 1; // 18 + volatile uint32_t mxr : 1; // 19 + volatile uint32_t tvm : 1; // 20 + volatile uint32_t tw : 1; // 21 + volatile uint32_t tsr : 1; // 22 + volatile uint32_t wpri3 : 8; // 30:23 + volatile uint32_t sd : 1; // 31 + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mstatus_t; + +typedef union { + struct { + volatile uint32_t shv : 1; + volatile uint32_t priv : 2; + volatile uint32_t level : 8; + volatile uint32_t id : 11; + volatile uint32_t irq : 1; + volatile uint32_t reserved_31_22 : 9; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) clic_t; + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- +// Bitfield offsets for mpp and mpie +const uint32_t MSTATUS_MPP_OFFSET = 11; +const uint32_t MSTATUS_MPIE_OFFSET = 7; +const uint32_t MCAUSE_MPP_OFFSET = 28; +const uint32_t MCAUSE_MPIE_OFFSET = 27; + +// Bitfield masks for mpp and mpie +const uint32_t MSTATUS_MPP_MASK = 0x3 << MSTATUS_MPP_OFFSET; +const uint32_t MSTATUS_MPIE_MASK = 0x1 << MSTATUS_MPIE_OFFSET; +const uint32_t MCAUSE_MPP_MASK = 0x3 << MCAUSE_MPP_OFFSET; +const uint32_t MCAUSE_MPIE_MASK = 0x1 << MCAUSE_MPIE_OFFSET; + +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +extern volatile uint32_t mtvt_table; +extern volatile uint32_t recovery_pt; + +volatile uint32_t test_fail_asm; + +volatile uint32_t * volatile g_expect_illegal; +volatile uint32_t * volatile g_special_handler_idx; +volatile uint32_t * volatile g_asserted_irq_idx; +volatile uint32_t * volatile g_asserted_irq_lvl; +volatile uint32_t * volatile g_irq_handler_reported_error; +volatile uint32_t * volatile g_mepc_triggered; +volatile uint32_t * volatile g_recovery_enable; +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t mcause_mstatus_mirror_init(uint32_t index, uint8_t report_name); +uint32_t w_mcause_mpp_r_mstatus_mpp(uint32_t index, uint8_t report_name); +uint32_t w_mstatus_mpp_r_mcause_mpp(uint32_t index, uint8_t report_name); +uint32_t w_mcause_mpie_r_mstatus_mpie(uint32_t index, uint8_t report_name); +uint32_t w_mstatus_mpie_r_mcause_mpie(uint32_t index, uint8_t report_name); +uint32_t w_mie_notrap_r_zero(uint32_t index, uint8_t report_name); +uint32_t w_mip_notrap_r_zero(uint32_t index, uint8_t report_name); +uint32_t w_mtvt_rd_alignment(uint32_t index, uint8_t report_name); +uint32_t w_mtvec_rd_alignment(uint32_t index, uint8_t report_name); +uint32_t invalid_mtvt_ptr_exec(uint32_t index, uint8_t report_name); +uint32_t r_mnxti_without_irq(uint32_t index, uint8_t report_name); +uint32_t rw_mnxti_without_irq_illegal(uint32_t index, uint8_t report_name); +uint32_t r_mnxti_with_pending_irq(uint32_t index, uint8_t report_name); +uint32_t r_mnxti_with_lower_lvl_pending_irq(uint32_t index, uint8_t report_name); +uint32_t w_mnxti_side_effects(uint32_t index, uint8_t report_name); +uint32_t rw_mscratchcsw(uint32_t index, uint8_t report_name); +uint32_t rw_mscratchcsw_illegal(uint32_t index, uint8_t report_name); +uint32_t rw_mscratchcswl(uint32_t index, uint8_t report_name); +uint32_t rw_mscratchcswl_illegal(uint32_t index, uint8_t report_name); +uint32_t mret_with_minhv(uint32_t index, uint8_t report_name); +uint32_t mintthresh_higher(uint32_t index, uint8_t report_name); +uint32_t mintthresh_lower(uint32_t index, uint8_t report_name); +uint32_t mintthresh_equal(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * max + * + * returns maxval of a and b + */ +uint32_t max(uint32_t a, uint32_t b); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...); + +/* + * vp_assert_irq + * + * Notify clic_interrupt_agent vp to assert given + * clic interrupt + */ +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay); + +/* + * set_pmpcfg + * + * Sets up pmp configuration for a given region + * (defined in pmpcfg_t object) + */ +void set_pmpcfg(pmpcfg_t pmpcfg); + +/* + * set_mseccfg + * + * Sets up mseccfg with the provided + * mseccfg_t object + */ +void set_mseccfg(mseccfg_t mseccfg); + +/* + * increment_mepc + * + * Increments mepc, + * incr_val 0 = auto detect + * 2 = halfword + * 4 = word + */ +void increment_mepc(uint32_t incr_val); + +/* + * reset_cpu_interrupt_lvl + * + * Resets core internal interrupt level (as reported by mintsstatus.mil) + */ +void reset_cpu_interrupt_lvl(void); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + g_expect_illegal = calloc(1, sizeof(uint32_t)); + g_special_handler_idx = calloc(1, sizeof(uint32_t)); + g_asserted_irq_idx = calloc(1, sizeof(uint32_t)); + g_asserted_irq_lvl = calloc(1, sizeof(uint32_t)); + g_irq_handler_reported_error = calloc(1, sizeof(uint32_t)); + g_mepc_triggered = calloc(1, sizeof(uint32_t)); + g_recovery_enable = calloc(1, sizeof(uint32_t)); + + // Add function pointers to new tests here + tests[0] = mcause_mstatus_mirror_init; + tests[1] = w_mcause_mpp_r_mstatus_mpp; + tests[2] = w_mstatus_mpp_r_mcause_mpp; + tests[3] = w_mcause_mpie_r_mstatus_mpie; + tests[4] = w_mstatus_mpie_r_mcause_mpie; + tests[5] = w_mie_notrap_r_zero; + tests[6] = w_mip_notrap_r_zero; + tests[7] = w_mtvt_rd_alignment; + tests[8] = w_mtvec_rd_alignment; + tests[9] = invalid_mtvt_ptr_exec; + tests[10] = r_mnxti_without_irq; + tests[11] = rw_mnxti_without_irq_illegal; + tests[12] = r_mnxti_with_pending_irq; + tests[13] = r_mnxti_with_lower_lvl_pending_irq; + tests[14] = w_mnxti_side_effects; + tests[15] = rw_mscratchcsw; + tests[16] = rw_mscratchcsw_illegal; + tests[17] = rw_mscratchcswl; + tests[18] = rw_mscratchcswl_illegal; + tests[19] = mret_with_minhv; + tests[20] = mintthresh_lower; + tests[21] = mintthresh_higher; + tests[22] = mintthresh_equal; + + // Run all tests in list above + cvprintf(V_LOW, "\nCLIC Test start\n\n"); + for (volatile int i = START_TEST_IDX; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + free((void *)g_expect_illegal ); + free((void *)g_special_handler_idx ); + free((void *)g_asserted_irq_idx ); + free((void *)g_asserted_irq_lvl ); + free((void *)g_irq_handler_reported_error); + free((void *)g_mepc_triggered ); + free((void *)g_recovery_enable ); + return retval; // Nonzero for failing tests +} + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +uint32_t max(uint32_t a, uint32_t b) { + return a > b ? a : b; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_IDX; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } +} + +// ----------------------------------------------------------------------------- + +uint32_t get_random_interrupt_number(uint32_t min, uint32_t max) { + volatile uint32_t num; + num = ((*RANDOM_NUM_ADDR) % ((NUM_INTERRUPTS > max ? max : NUM_INTERRUPTS) - min)) + min; + return num; +} + +// ----------------------------------------------------------------------------- + +uint32_t get_random_interrupt_level(uint32_t min, uint32_t max) { + volatile uint32_t num; + num = ((*RANDOM_NUM_ADDR) % ((NUM_INTERRUPT_LVLS > max ? max : NUM_INTERRUPT_LVLS) - min)) + min; + return num; +} + +// ----------------------------------------------------------------------------- + +void increment_mepc(uint32_t incr_val) { + volatile uint32_t mepc = 0; + + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + )" : [mepc] "=r"(mepc)); + + if (incr_val == 0) { + // No increment specified, check *mepc instruction + if (((*(uint32_t *)mepc) & 0x3UL) == 0x3UL) { + // non-compressed + mepc += 4; + } else { + // compressed + mepc += 2; + } + } else { + // explicitly requested increment + mepc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, mepc, %[mepc] + )" :: [mepc] "r"(mepc)); +} + +// ----------------------------------------------------------------------------- + +void set_mseccfg(mseccfg_t mseccfg){ + volatile uint32_t mseccfg_vector = 0x0; + + mseccfg_vector = ( + ((mseccfg.rlb << 2) & 0x4) | + ((mseccfg.mmwp << 1) & 0x2) | + ((mseccfg.mml << 0) & 0x1)); + + __asm__ volatile ( R"( + csrrs x0, mseccfg, %[cfg_vec] + )" + : + : [cfg_vec] "r"(mseccfg_vector) + :); + + cvprintf(V_DEBUG, "Wrote mseccfg: 0x%08lx\n", mseccfg_vector); +} + +void set_pmpcfg(pmpcfg_t pmpcfg){ + volatile uint32_t pmpcfg_vector = 0x0; + volatile uint32_t temp = 0; + + pmpcfg_vector = ( + ((pmpcfg.lock << 7) & 0x80) | + ((pmpcfg.mode << 3) & 0x18) | + ((pmpcfg.execute << 2) & 0x4 ) | + ((pmpcfg.write << 1) & 0x2 ) | + ((pmpcfg.read << 0) & 0x1 )) << ((pmpcfg.reg_no % 4)*8); + + temp = 0xff << ((pmpcfg.reg_no % 4)*8); + + switch (pmpcfg.reg_no / 4) { + case 0: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg0, t0 + csrrs %[cfg_vec], pmpcfg0, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 1: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg1, t0 + csrrs %[cfg_vec], pmpcfg1, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 2: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg2, t0 + csrrs %[cfg_vec], pmpcfg2, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 3: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg3, t0 + csrrs %[cfg_vec], pmpcfg3, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 4: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg4, t0 + csrrs %[cfg_vec], pmpcfg4, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + case 5: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg5, t0 + csrrs %[cfg_vec], pmpcfg5, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 6: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg6, t0 + csrrs %[cfg_vec], pmpcfg6, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 7: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg7, t0 + csrrs %[cfg_vec], pmpcfg7, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 8: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg8, t0 + csrrs %[cfg_vec], pmpcfg8, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 9: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg9, t0 + csrrs %[cfg_vec], pmpcfg9, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 10: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg10, t0 + csrrs %[cfg_vec], pmpcfg10, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 11: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg11, t0 + csrrs %[cfg_vec], pmpcfg11, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 12: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg12, t0 + csrrs %[cfg_vec], pmpcfg12, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 13: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg13, t0 + csrrs %[cfg_vec], pmpcfg13, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 14: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg14, t0 + csrrs %[cfg_vec], pmpcfg14, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + case 15: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg15, t0 + csrrs %[cfg_vec], pmpcfg15, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg_vector) + : [tmp] "r"(temp) + : "t0" + ); + break; + } + + cvprintf(V_DEBUG, "Wrote pmpcfg_vector: 0x%08lx\n", pmpcfg_vector); + return; +} + +// ----------------------------------------------------------------------------- + +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay){ + *TIMER_REG_ADDR = mask; + *TIMER_VAL_ADDR = 1 + cycle_delay; +} + +// ----------------------------------------------------------------------------- + +_Pragma("GCC push_options") +_Pragma("GCC optimize (\"O0\")") + +// ----------------------------------------------------------------------------- + +uint32_t mcause_mstatus_mirror_init(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val_mcause = 0x0; + volatile uint32_t readback_val_mstatus = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting mirroring of mcause.mpp/mpie and mstatus.mpp/mpie without write\n"); + __asm__ volatile ( R"( + csrrs %[mc], mcause, x0 + csrrs %[ms], mstatus, x0 + )" + : [mc] "=r"(readback_val_mcause), + [ms] "=r"(readback_val_mstatus) + : + : + ); + test_fail += MCAUSE_MPP(readback_val_mcause) != MSTATUS_MPP(readback_val_mstatus); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + test_fail += MCAUSE_MPIE(readback_val_mcause) != MSTATUS_MPIE(readback_val_mstatus); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mcause_mpp_r_mstatus_mpp(uint32_t index, uint8_t report_name){ + + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val = 0x0; + volatile uint32_t mcause_initial_val = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting write to mcause.mpp, read from mstatus.mpp\n"); + // Backup mcause + __asm__ volatile ( R"( + csrrs %[mc], mcause, x0 + )" + : [mc] "=r"(mcause_initial_val) + : + : + ); + cvprintf(V_HIGH, "Initial value mcause.mpp: %0lx\n", ((mcause_initial_val & MCAUSE_MPP_MASK) >> MCAUSE_MPP_OFFSET)); + + // Bit set and read back + __asm__ volatile ( R"( + csrrs x0, mcause, %[mc] + csrrs %[rb], mstatus, x0 + )" + : [rb] "=r"(readback_val) + : [mc] "r"(MCAUSE_MPP_MASK) + : + ); + + test_fail += MSTATUS_MPP(readback_val) != 0x3; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mstatus.mpp after setting bits: %0lx\n", ((readback_val & MSTATUS_MPP_MASK) >> MSTATUS_MPP_OFFSET)); + + // Bit clear and read back + __asm__ volatile ( R"( + csrrc x0, mcause, %[mc] + csrrc %[rb], mstatus, x0 + )" + : [rb] "=r"(readback_val) + : [mc] "r"(MCAUSE_MPP_MASK) + : + ); + + test_fail += MSTATUS_MPP(readback_val) != 0x0; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mstatus.mpp after clearing bits: %0lx\n", ((readback_val & MSTATUS_MPP_MASK) >> MSTATUS_MPP_OFFSET)); + + // Restore value and read back + __asm__ volatile ( R"( + csrrw x0, mcause, %[mc] + csrrw %[rb], mstatus, x0 + )" + : [rb] "=r"(readback_val) + : [mc] "r"(mcause_initial_val) + : + ); + + test_fail += MSTATUS_MPP(readback_val) != MCAUSE_MPP(mcause_initial_val); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mstatus.mpp after restore: %0lx\n", ((readback_val & MSTATUS_MPP_MASK) >> MSTATUS_MPP_OFFSET)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mstatus_mpp_r_mcause_mpp(uint32_t index, uint8_t report_name){ + + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val = 0x0; + volatile uint32_t mstatus_initial_val = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting write to mstatus.mpp, read from mcause.mpp\n"); + + // Backup mstatus + __asm__ volatile ( R"( + csrrs %[ms], mstatus, x0 + )" + : [ms] "=r"(mstatus_initial_val) + : + : + ); + + cvprintf(V_HIGH, "Initial value mstatus.mpp: %0lx\n", ((mstatus_initial_val & MSTATUS_MPP_MASK) >> MSTATUS_MPP_OFFSET)); + + // Bit set and read back + __asm__ volatile ( R"( + csrrs x0, mstatus, %[ms] + csrrs %[rb], mcause, x0 + )" + : [rb] "=r"(readback_val) + : [ms] "r"(MSTATUS_MPP_MASK) + : + ); + + test_fail += MCAUSE_MPP(readback_val) != 0x3; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mcause.mpp after setting bits: %0lx\n", ((readback_val & MCAUSE_MPP_MASK) >> MCAUSE_MPP_OFFSET)); + + // Bit clear and read back + __asm__ volatile ( R"( + csrrc x0, mstatus, %[ms] + csrrc %[rb], mcause, x0 + )" + : [rb] "=r"(readback_val) + : [ms] "r"(MSTATUS_MPP_MASK) + : + ); + + test_fail += MCAUSE_MPP(readback_val) != 0x0; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mcause.mpp after clearing bits: %0lx\n", ((readback_val & MCAUSE_MPP_MASK) >> MCAUSE_MPP_OFFSET)); + + // Restore value and read back + __asm__ volatile ( R"( + csrrw x0, mstatus, %[ms] + csrrw %[rb], mcause, x0 + )" + : [rb] "=r"(readback_val) + : [ms] "r"(mstatus_initial_val) + : + ); + + test_fail += MCAUSE_MPP(readback_val) != MSTATUS_MPP(mstatus_initial_val); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mcause.mpp after restore: %0lx\n", ((readback_val & MCAUSE_MPP_MASK) >> MCAUSE_MPP_OFFSET)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mcause_mpie_r_mstatus_mpie(uint32_t index, uint8_t report_name){ + + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val = 0x0; + volatile uint32_t mcause_initial_val = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting write to mcause.mpie, read from mstatus.mpie\n"); + // Backup mcause + __asm__ volatile ( R"( + csrrs %[mc], mcause, x0 + )" + : [mc] "=r"(mcause_initial_val) + : + : + ); + + cvprintf(V_HIGH, "Initial value mcause.mpie: %0lx\n", ((mcause_initial_val & MCAUSE_MPIE_MASK) >> MCAUSE_MPIE_OFFSET)); + + // Bit set and read back + __asm__ volatile ( R"( + csrrs x0, mcause, %[mc] + csrrs %[rb], mstatus, x0 + )" + : [rb] "=r"(readback_val) + : [mc] "r"(MCAUSE_MPIE_MASK) + : + ); + + test_fail += MSTATUS_MPIE(readback_val) != 0x1; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mstatus.mpie after setting bits: %0lx\n", ((readback_val & MSTATUS_MPIE_MASK) >> MSTATUS_MPIE_OFFSET)); + + // Bit clear and read back + __asm__ volatile ( R"( + csrrc x0, mcause, %[mc] + csrrc %[rb], mstatus, x0 + )" + : [rb] "=r"(readback_val) + : [mc] "r"(MCAUSE_MPIE_MASK) + : + ); + + test_fail += MSTATUS_MPIE(readback_val) != 0x0; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mstatus.mpie after clearing bits: %0lx\n", ((readback_val & MSTATUS_MPIE_MASK) >> MSTATUS_MPIE_OFFSET)); + // Restore value and read back + __asm__ volatile ( R"( + csrrw x0, mcause, %[mc] + csrrw %[rb], mstatus, x0 + )" + : [rb] "=r"(readback_val) + : [mc] "r"(mcause_initial_val) + : + ); + + test_fail += MSTATUS_MPIE(readback_val) != MCAUSE_MPIE(mcause_initial_val); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mcause.mpie after restore: %0lx\n", ((readback_val & MSTATUS_MPIE_MASK) >> MSTATUS_MPIE_OFFSET)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mstatus_mpie_r_mcause_mpie(uint32_t index, uint8_t report_name){ + + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val = 0x0; + volatile uint32_t mstatus_initial_val = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting write to mstatus.mpie, read from mcause.mpie\n"); + + // Backup mstatus + __asm__ volatile ( R"( + csrrs %[ms], mstatus, x0 + )" + : [ms] "=r"(mstatus_initial_val) + : + : + ); + + cvprintf(V_HIGH, "Initial value mstatus.mpie: %0lx\n", ((mstatus_initial_val & MSTATUS_MPIE_MASK) >> MSTATUS_MPIE_OFFSET)); + + // Bit set and read back + __asm__ volatile ( R"( + csrrs x0, mstatus, %[ms] + csrrs %[rb], mcause, x0 + )" + : [rb] "=r"(readback_val) + : [ms] "r"(MSTATUS_MPIE_MASK) + : + ); + + test_fail += MCAUSE_MPIE(readback_val) != 0x1; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mcause.mpie after setting bits: %0lx\n", ((readback_val & MCAUSE_MPIE_MASK) >> MCAUSE_MPIE_OFFSET)); + + // Bit clear and read back + __asm__ volatile ( R"( + csrrc x0, mstatus, %[ms] + csrrc %[rb], mcause, x0 + )" + : [rb] "=r"(readback_val) + : [ms] "r"(MSTATUS_MPIE_MASK) + : + ); + + test_fail += MCAUSE_MPIE(readback_val) != 0x0; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mcause.mpie after clearing bits: %0lx\n", ((readback_val & MCAUSE_MPIE_MASK) >> MCAUSE_MPIE_OFFSET)); + + // Restore value and read back + __asm__ volatile ( R"( + csrrw x0, mstatus, %[ms] + csrrw %[rb], mcause, x0 + )" + : [rb] "=r"(readback_val) + : [ms] "r"(mstatus_initial_val) + : + ); + + test_fail += MCAUSE_MPIE(readback_val) != MSTATUS_MPIE(mstatus_initial_val); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + cvprintf(V_HIGH, "Read back mcause.mpie after restore: %0lx\n", ((readback_val & MCAUSE_MPIE_MASK) >> MCAUSE_MPIE_OFFSET)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +_Pragma("GCC pop_options") + +// ----------------------------------------------------------------------------- + +uint32_t w_mie_notrap_r_zero(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val_mepc = 0x0; + volatile uint32_t readback_val_mie = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting write to mie, should not trap and readback 0\n"); + __asm__ volatile ( R"( + addi t0, x0, -1 + csrrw x0, mepc, t0 + csrrw x0, mie, t0 + csrrw %[mie], mie, x0 + csrrw %[mepc], mepc, x0 + )" + : [mepc] "=r"(readback_val_mepc), [mie] "=r"(readback_val_mie) + : + : "t0" + ); + + test_fail = (readback_val_mepc != 0xfffffffe) || (readback_val_mie != 0); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!un", name); + cvprintf(V_MEDIUM, "\nMIE: 0x%08lx, MEPC: 0x%08lx\n", readback_val_mie, readback_val_mepc); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mip_notrap_r_zero(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val_mepc = 0x0; + volatile uint32_t readback_val_mip = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting write to mip, should not trap and readback 0\n"); + __asm__ volatile ( R"( + addi t0, x0, -1 + csrrw x0, mepc, t0 + csrrw x0, mip, t0 + csrrw %[mip], mip, x0 + csrrw %[mepc], mepc, x0 + )" + : [mepc] "=r"(readback_val_mepc), [mip] "=r"(readback_val_mip) + : + : "t0" + ); + + // Expect all bits of mepc to remain as written (sans the last bit that is cleared by hw) + // mip should read all zeroes after writing all f's + test_fail = (readback_val_mepc != 0xfffffffe) || ( readback_val_mip != 0); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + cvprintf(V_MEDIUM, "\nMIP: 0x%08lx, MEPC: 0x%08lx\n", readback_val_mip, readback_val_mepc); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mtvt_rd_alignment(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile uint32_t mtvt_initial_val = 0x0; + volatile uint32_t readback_val_mtvt = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting mtvt alignment\n"); + + // Clear mtvt + __asm__ volatile ( R"( + csrrw %[mtvt_init], 0x307, x0 + csrrw %[mtvt_rb], 0x307, %[mtvt_init] + )" + : [mtvt_init] "=r"(mtvt_initial_val), [mtvt_rb] "+r"(readback_val_mtvt) + : + : + ); + + // All bits should be zeroed + test_fail += readback_val_mtvt; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + __asm__ volatile ( R"( + addi t0, x0, -1 + csrrw %[mtvt_init], 0x307, t0 + csrrw %[mtvt_rb], 0x307, %[mtvt_init] + )" + : [mtvt_init] "=r"(mtvt_initial_val), [mtvt_rb] "=r"(readback_val_mtvt) + : + : + ); + + // Check for correct alignment + test_fail += ~(readback_val_mtvt >> max(CLIC_ID_WIDTH+2, 6)); + if (ABORT_ON_ERROR_IMMEDIATE) assert (test_fail == 0); + cvprintf(V_HIGH, "\nmtvt readback after 0xffff_ffff write: 0x%08lx\n", readback_val_mtvt); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mtvec_rd_alignment(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile uint32_t mtvec_initial_val = 0x0; + volatile uint32_t readback_val_mtvec = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_MEDIUM, "\nTesting mtvec alignment\n"); + + // Clear mtvec + __asm__ volatile ( R"( + csrrw %[mtvec_init], mtvec, x0 + csrrw %[mtvec_rb], mtvec, %[mtvec_init] + )" + : [mtvec_init] "=r"(mtvec_initial_val), + [mtvec_rb] "=r"(readback_val_mtvec) + : + : + ); + + // All bits above 2 should be zeroed + test_fail += (readback_val_mtvec >> 2); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + __asm__ volatile ( R"( + addi t0, x0, -1 + csrrw %[mtvec_init], mtvec, t0 + csrrw %[mtvec_rb], mtvec, %[mtvec_init] + )" + : [mtvec_init] "=r"(mtvec_initial_val), + [mtvec_rb] "=r"(readback_val_mtvec) + : + : + ); + + // upper bits all writeable + test_fail += ~(readback_val_mtvec >> MTVEC_ALIGN_BITS); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + // lower [MTVEC_ALIGN_BITS-1:2] bits not updated + test_fail += ((readback_val_mtvec << (32 - MTVEC_ALIGN_BITS)) >> 2); + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + cvprintf(V_HIGH, "\nmtvec readback after 0xffff_ffff write: 0x%08lx\n", readback_val_mtvec); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- +_Pragma("GCC push_options") +_Pragma("GCC optimize (\"O0\")") +// ----------------------------------------------------------------------------- + +__attribute__((naked)) void mtvt_code(void) { + __asm__ volatile ( R"( + .global mtvt_table + .align 7 + mtvt_table: .long . + 4096 + mtvt_table_1: .long . + 4092 + mtvt_table_2: .long . + 4088 + mtvt_table_3: .long . + 4084 + mtvt_table_4: .long . + 4080 + .space 100, 0x0 + mtvt_table_30: .long . + 3976 + mtvt_table_31: .long . + 3972 + mtvt_table_32: .long . + 3968 + .space 3952, 0x0 + mtvt_table_1021: .long . + 12 + mtvt_table_1022: .long . + 8 + mtvt_table_1023: .long . + 4 + jal zero, m_fast14_irq_handler + )" + ); +} + +// ----------------------------------------------------------------------------- + +__attribute__((naked)) void m_fast14_irq_handler(void) { + __asm__ volatile ( R"( + # Push saved regs and allocate space for the remaining 16 regs + cm.push {ra, s0-s11}, -112 + addi sp, sp, -12 + + # Save argument registers to stack + # as we want to be able to call C-functions + # from debug + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw a3, 12(sp) + sw a4, 16(sp) + sw a5, 20(sp) + sw a6, 24(sp) + sw a7, 28(sp) + + # Back up remaining temporaries + sw tp, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + + sw gp, 64(sp) + + # Turn off interrupt request + add a0, zero, zero + add a1, zero, zero + call vp_assert_irq + + # Store g_mepc_triggered + lw s0, g_mepc_triggered + csrrs s1, mepc, zero + sw s1, 0(s0) + + # Check if we should skip jump to recovery code + lw s0, g_recovery_enable + lw s1, 0(s0) + beq s1, zero, 1f + add s1, zero, zero + sw s1, 0(s0) + # Else, Get recovery mepc and replace mepc + la s1, recovery_pt + csrrw zero, mepc, s1 + # clear mcause, set mpp + lui s1, 0x30000 + csrrw zero, mcause, s1 + + 1: + ## restore stack + lw gp, 64(sp) + + # Restore temporary registers + lw t6, 60(sp) + lw t5, 56(sp) + lw t4, 52(sp) + lw t3, 48(sp) + lw t2, 44(sp) + lw t1, 40(sp) + lw t0, 36(sp) + lw tp, 32(sp) + + # Restore argument registers + lw a7, 28(sp) + lw a6, 24(sp) + lw a5, 20(sp) + lw a4, 16(sp) + lw a3, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + + # Restore stack ptr + addi sp, sp, 12 + cm.pop {ra, s0-s11}, 112 + + mret + )"); + +} + +// ----------------------------------------------------------------------------- + +uint32_t invalid_mtvt_ptr_exec(uint32_t index, uint8_t report_name) { + + volatile uint8_t test_fail = 0; + + // These needs to be volatile to prevent loop optimization + //volatile uint8_t never = 0; + volatile uint32_t no_timeout_threshold = 10; + //volatile uint32_t mepc_triggered = 0x0; + volatile uint32_t addr = 0x0; + //volatile uint32_t clic_vector = 0x0; + volatile clic_t clic_vector = { 0 }; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Write table location to mtvt and enable interrupts + __asm__ volatile ( R"( + csrrw x0, 0x307, %[mtvt] + csrrsi x0, mstatus, 0x8 + )" + : + : [mtvt] "r"(&mtvt_table) + : + ); + + // Pre-PMP setting, sanity check + cvprintf(V_DEBUG, "mtvt: %08x, %08x\n", &mtvt_table, (uint32_t *)mtvt_table); + clic_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x3, + .fields.level = 0x81, + .fields.priv = 0x3, + .fields.shv = 0x1 + }; + + no_timeout_threshold = 10; + *g_mepc_triggered = 0; + // Instruct clic_interrupt_vp to assert interrupt declared above + vp_assert_irq(clic_vector.raw, 0); + + // Wait for interrupt + while (no_timeout_threshold) { + no_timeout_threshold--; + } + test_fail += (*g_mepc_triggered ? 0 : 1); + cvprintf(V_MEDIUM, "Expect non-zero mepc, MEPC = 0x%08lx\n", *g_mepc_triggered); + if (ABORT_ON_ERROR_IMMEDIATE) assert(*g_mepc_triggered != 0); + + clic_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = (0x1 << CLIC_ID_WIDTH) - 1, + .fields.level = 0xff, + .fields.priv = 0x3, + .fields.shv = 0x1 + }; + + no_timeout_threshold = 10; + *g_mepc_triggered = 0; + // Instruct clic_interrupt_vp to assert interrupt declared above + vp_assert_irq(clic_vector.raw, 0); + + // Wait for interrupt + while (no_timeout_threshold) { + no_timeout_threshold--; + } + test_fail += (*g_mepc_triggered ? 0 : 1); + cvprintf(V_MEDIUM, "Expect non-zero mepc, MEPC = 0x%08lx\n", *g_mepc_triggered); + if (ABORT_ON_ERROR_IMMEDIATE) assert(*g_mepc_triggered != 0); + + // Set PMP configuration + __asm__ volatile ( R"( + la %[addr], mtvt_table; + srli %[addr], %[addr], 2 + csrrw x0, pmpaddr0, %[addr] + la %[addr], mtvt_table + 128*4 + srli %[addr], %[addr], 2 + csrrw x0, pmpaddr1, %[addr] + addi %[addr], x0, -1 + csrrw x0, pmpaddr2, %[addr] + )" + : [addr] "+r"(addr) + : + : "t0" + ); + + set_mseccfg((mseccfg_t){ + .rlb = 1, + .mmwp = 0, + .mml = 0 + }); + + set_pmpcfg((pmpcfg_t){ + .reg_no = 0, + .lock = 0, + .mode = TOR, + .execute = 1, + .write = 1, + .read = 1 + }); + + set_pmpcfg((pmpcfg_t){ + .reg_no = 1, + .lock = 1, + .mode = TOR, + .execute = 0, + .write = 0, + .read = 0 + }); + + set_pmpcfg((pmpcfg_t){ + .reg_no = 2, + .lock = 0, + .mode = TOR, + .execute = 1, + .write = 1, + .read = 1 + }); + + clic_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x4, + .fields.level = 0x55, + .fields.priv = 0x3, + .fields.shv = 0x1 + }; + + no_timeout_threshold = 10; + *g_mepc_triggered = 0; + *g_recovery_enable = 1; + test_fail_asm = 0; + // Instruct clic_interrupt_vp to assert interrupt declared above + vp_assert_irq(clic_vector.raw, 0); + + // Wait for interrupt + while (no_timeout_threshold) { + no_timeout_threshold--; + } + + __asm__ volatile ( R"( + .extern test_fail_asm + # This should never execute (deliberate dead code) + la t0, test_fail_asm + lw t1, 0(t0) + addi t1, t1, 1 + sw t1, 0(t0) + # Execution should continue here + .global recovery_pt + recovery_pt: add x0, x0, x0 + )":::); + + cvprintf(V_LOW, "Entered recovery point, due to unrecoverable clic ptr trap, mepc: %08x, expected: %08x\n", *g_mepc_triggered, (uint32_t)(*((&mtvt_table) + 4))); + test_fail += test_fail_asm || *g_mepc_triggered != (uint32_t)(*(&mtvt_table + 4)); + + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +uint32_t r_mnxti_without_irq(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t mnxti_rval = 0; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // CSRRS ro + __asm__ volatile ( R"( + csrrs %[rd], 0x345, x0 + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)(mnxti_rval ? 1 : 0); // rval should be zero + + // CSRRSI ro + __asm__ volatile ( R"( + csrrsi %[rd], 0x345, 0 + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)(mnxti_rval ? 1 : 0); // rval should be zero + + // CSRRCI ro + __asm__ volatile ( R"( + csrrci %[rd], 0x345, 0 + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)(mnxti_rval ? 1 : 0); // rval should be zero + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t rw_mnxti_without_irq_illegal(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t mnxti_rval = 0; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // CSRRC rw - use sp as that is non-zero to ensure that we actually try clearing (illegal) + *g_expect_illegal = 1; + __asm__ volatile ( R"( + .option push + .option norvc + csrrc %[rd], 0x345, sp + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // CSRRC rw - use zero to do no clear operation (illegal) + *g_expect_illegal = 1; + __asm__ volatile ( R"( + .option push + .option norvc + csrrc %[rd], 0x345, zero + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + + // CSRRW rw - use sp as that is non-zero to ensure that we actually try writing (illegal) + *g_expect_illegal = 1; + __asm__ volatile ( R"( + .option push + .option norvc + csrrw %[rd], 0x345, sp + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // CSRRW rw - use zero to ensure that we actually try writing all zeros (illegal) + *g_expect_illegal = 1; + __asm__ volatile ( R"( + .option push + .option norvc + csrrw %[rd], 0x345, sp + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // CSRRWI rw - use all ones to ensure that we actually try writing (illegal) + *g_expect_illegal = 1; + __asm__ volatile ( R"( + .option push + .option norvc + csrrwi %[rd], 0x345, 0x1f + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // CSRRWI rw - use all zeroes to ensure that we actually try clearing the register (illegal) + *g_expect_illegal = 1; + __asm__ volatile ( R"( + .option push + .option norvc + csrrwi %[rd], 0x345, 0x0 + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // CSRRS with rs1 != x0 - illegal + *g_expect_illegal = 31; + __asm__ volatile ( R"( + .option push + .option norvc + csrrs %[rd], 0x345, x1 + csrrs %[rd], 0x345, x2 + csrrs %[rd], 0x345, x3 + csrrs %[rd], 0x345, x4 + csrrs %[rd], 0x345, x5 + csrrs %[rd], 0x345, x6 + csrrs %[rd], 0x345, x7 + csrrs %[rd], 0x345, x8 + csrrs %[rd], 0x345, x9 + csrrs %[rd], 0x345, x10 + csrrs %[rd], 0x345, x11 + csrrs %[rd], 0x345, x12 + csrrs %[rd], 0x345, x13 + csrrs %[rd], 0x345, x14 + csrrs %[rd], 0x345, x15 + csrrs %[rd], 0x345, x16 + csrrs %[rd], 0x345, x17 + csrrs %[rd], 0x345, x18 + csrrs %[rd], 0x345, x19 + csrrs %[rd], 0x345, x20 + csrrs %[rd], 0x345, x21 + csrrs %[rd], 0x345, x22 + csrrs %[rd], 0x345, x23 + csrrs %[rd], 0x345, x24 + csrrs %[rd], 0x345, x25 + csrrs %[rd], 0x345, x26 + csrrs %[rd], 0x345, x27 + csrrs %[rd], 0x345, x28 + csrrs %[rd], 0x345, x29 + csrrs %[rd], 0x345, x30 + csrrs %[rd], 0x345, x31 + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // CSRRSI with imm[0, 2, 4] = 1 - illegal + *g_expect_illegal = 11; + __asm__ volatile ( R"( + .option push + .option norvc + # bit 0, 2, 4 + csrrsi %[rd], 0x345, 1 << 0 | 1 << 2 | 1 << 4 + # bit 0 + csrrsi %[rd], 0x345, 1 << 0 + # bit 2 + csrrsi %[rd], 0x345, 1 << 2 + # bit 4 + csrrsi %[rd], 0x345, 1 << 4 + # all bits + csrrsi %[rd], 0x345, 0x1f + # all bits without bit 0 and 2 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 0) & ~(1 << 2) + # all bits without bit 2 and 4 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 2) & ~(1 << 4) + # all bits without bit 0 and 4 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 0) & ~(1 << 4) + # all bits without 0 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 0) + # all bits without 2 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 2) + # all bits without 4 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 4) + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t r_mnxti_with_pending_irq(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile clic_t clic_irq_vector = { 0 }; + volatile uint32_t no_timeout_threshold = 1000; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_special_handler_idx = 3; + // Need an mret to clear out mintstatus -> take an interrupt and return + __asm__ volatile ( R"( + csrrsi zero, 0x345, 0x8 + )":::); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x1, + .fields.level = 0xff, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + vp_assert_irq(clic_irq_vector.raw, 0); + + // Enable interrupts + __asm__ volatile (R"( + csrrsi x0, 0x345, 0x8 + )":::); + + *g_special_handler_idx = 1; + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x1, + .fields.level = 0x1, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // Instruct clic_interrupt_vp to assert interrupt declared above + vp_assert_irq(clic_irq_vector.raw, 1); + + // Wait for interrupt + no_timeout_threshold = 100; + while (no_timeout_threshold) { + no_timeout_threshold--; + } + + vp_assert_irq(0, 0); + test_fail += *g_irq_handler_reported_error; + + *g_special_handler_idx = 1; + vp_assert_irq(clic_irq_vector.raw, 1); + // Wait for interrupt + no_timeout_threshold = 100; + while (no_timeout_threshold) { + no_timeout_threshold--; + } + + vp_assert_irq(0, 0); + test_fail += *g_irq_handler_reported_error; + + *g_special_handler_idx = 1; + vp_assert_irq(clic_irq_vector.raw, 1); + // Wait for interrupt + no_timeout_threshold = 100; + while (no_timeout_threshold) { + no_timeout_threshold--; + } + + vp_assert_irq(0, 0); + test_fail += *g_irq_handler_reported_error; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t r_mnxti_with_irq_handler(uint32_t min_id, uint32_t max_id, uint32_t min_lvl, uint32_t max_lvl) { + volatile clic_t clic_irq_vector = { 0 }; + volatile uint32_t mnxti_rval = 0; + volatile mintstatus_t mintstatus_rval = { 0 }; + volatile mcause_t mcause_rval = { 0 }; + + *g_asserted_irq_idx = get_random_interrupt_number(min_id, max_id); + *g_asserted_irq_lvl = get_random_interrupt_level(min_lvl, max_lvl); + cvprintf(V_DEBUG, "called r_mnxti_with_irq_handler, irq: %08x, lvl: %08x\n", *g_asserted_irq_idx, *g_asserted_irq_lvl); + + // Write mnxti to trigger mcause updates, get minstatus.mil and mcause.mpil for manual update + __asm__ volatile ( R"( + csrrci %[rd1], 0x345, 0x8 + csrrs %[rd2], 0xfb1, zero + csrrs %[rd3], mcause, zero + )":[rd1] "=r"(mnxti_rval), + [rd2] "=r"(mintstatus_rval.raw), + [rd3] "=r"(mcause_rval.raw) + :: + ); + + cvprintf(V_DEBUG, "Read mnxti (oic): %08x, mintstatus.mil: %02x, mcause.mpil: %02x\n", mnxti_rval, mintstatus_rval.fields.mil, mcause_rval.clic.mpil); + + // Update mcause.mpil (instead of nesting interrupts), store previous value + mcause_rval.clic.mpil = mintstatus_rval.fields.mil; + + __asm__ volatile ( R"( + csrrw %[rd2], mcause, %[rd2] + )":[rd2] "+r"(mcause_rval.raw) + :: + ); + + // Assert new interrupt within specified parameters + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + vp_assert_irq(clic_irq_vector.raw, 0); + + // Read mnxti to check if correct value can be read + // then + // Revert mcause.mpil to reset mpil prior to mret to restore original interrupt context + + __asm__ volatile ( R"( + csrrci %[rd1], 0x345, 0 + csrrw %[rd2], mcause, %[rd2] + )":[rd1] "=r"(mnxti_rval), + [rd2] "+r"(mcause_rval.raw) + :: + ); + + cvprintf(V_DEBUG, "Read mnxti (nic): %08x\n", mnxti_rval); + + return mnxti_rval; +} + +// ----------------------------------------------------------------------------- + +uint32_t r_mnxti_with_lower_lvl_pending_irq(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile clic_t clic_irq_vector = { 0 }; + volatile uint32_t no_timeout_threshold = 100; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_special_handler_idx = 2; + // Enable interrupts + __asm__ volatile (R"( + csrrsi x0, mstatus, 0x8 + )":::); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x1, + .fields.level = 0xff, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + no_timeout_threshold = 100; + // Instruct clic_interrupt_vp to assert interrupt declared above + vp_assert_irq(clic_irq_vector.raw, 1); + + // Wait for interrupt + while (no_timeout_threshold) { + no_timeout_threshold--; + } + + test_fail += *g_irq_handler_reported_error; + + *g_special_handler_idx = 2; + vp_assert_irq(clic_irq_vector.raw, 1); + // Wait for interrupt + no_timeout_threshold = 100; + while (no_timeout_threshold) { + no_timeout_threshold--; + } + + test_fail += *g_irq_handler_reported_error; + + *g_special_handler_idx = 2; + vp_assert_irq(clic_irq_vector.raw, 1); + // Wait for interrupt + no_timeout_threshold = 100; + while (no_timeout_threshold) { + no_timeout_threshold--; + } + + test_fail += *g_irq_handler_reported_error; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t w_mnxti_side_effects(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t previous_lvl = 0; + volatile uint32_t previous_idx = 0; + volatile mcause_t mcause_rval = { 0 }; + volatile mintstatus_t mintstatus_rval = { 0 }; + volatile clic_t clic_irq_vector = { 0 }; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + vp_assert_irq(0, 0); + *g_special_handler_idx = 3; + // Need an mret to clear out mintstatus -> take an interrupt and return + __asm__ volatile ( R"( + csrrsi zero, 0x345, 0x8 + )":::); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x1, + .fields.level = 0xff, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + vp_assert_irq(clic_irq_vector.raw, 0); + + // Disable interrupts + __asm__ volatile ( R"( + csrrci zero, 0x345, 0x8 + )":::); + + // Disable interrupts (write side-effects should occur): + __asm__ volatile (R"( + csrrci zero, 0x345, 0x8 + csrrs %[rd1], 0xfb1, zero + csrrs %[rd2], mcause, zero + )":[rd1] "=r"(mintstatus_rval.raw), + [rd2] "=r"(mcause_rval.raw) + ::); + + test_fail += mcause_rval.clic.interrupt != 0; + test_fail += mcause_rval.clic.exccode != 0; + test_fail += mintstatus_rval.fields.mil != 0; + + *g_asserted_irq_idx = get_random_interrupt_number(0, NUM_INTERRUPTS); + *g_asserted_irq_lvl = get_random_interrupt_level(0, NUM_INTERRUPT_LVLS); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should not be taken (not enabled) + vp_assert_irq(clic_irq_vector.raw, 0); + + __asm__ volatile (R"( + csrrci zero, 0x345, 0x8 + csrrs %[rd1], 0xfb1, zero + csrrs %[rd2], mcause, zero + )":[rd1] "=r"(mintstatus_rval.raw), + [rd2] "=r"(mcause_rval.raw) + ::); + + cvprintf(V_DEBUG, "mintstatus.mil: %02x, mcause.exccode: %08x, expected: lvl %02x, id %08x\n", mintstatus_rval.fields.mil, mcause_rval.clic.exccode, *g_asserted_irq_lvl, *g_asserted_irq_idx); + + test_fail += mcause_rval.clic.interrupt != 1; + test_fail += mcause_rval.clic.exccode != *g_asserted_irq_idx; + test_fail += mintstatus_rval.fields.mil != *g_asserted_irq_lvl; + + // Higher lvl than previously set + *g_asserted_irq_idx = get_random_interrupt_number(*g_asserted_irq_idx, NUM_INTERRUPTS); + *g_asserted_irq_lvl = get_random_interrupt_level(*g_asserted_irq_lvl, NUM_INTERRUPT_LVLS); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should not be taken (not enabled) + vp_assert_irq(clic_irq_vector.raw, 0); + + __asm__ volatile (R"( + csrrci zero, 0x345, 0x8 + csrrs %[rd1], 0xfb1, zero + csrrs %[rd2], mcause, zero + )":[rd1] "=r"(mintstatus_rval.raw), + [rd2] "=r"(mcause_rval.raw) + ::); + + cvprintf(V_DEBUG, "mintstatus.mil: %02x, mcause.exccode: %08x, expected: lvl %02x, id %08x\n", mintstatus_rval.fields.mil, mcause_rval.clic.exccode, *g_asserted_irq_lvl, *g_asserted_irq_idx); + + if (*g_asserted_irq_idx < NUM_INTERRUPTS && *g_asserted_irq_lvl < NUM_INTERRUPT_LVLS) { + test_fail += mcause_rval.clic.interrupt != 1; + test_fail += mcause_rval.clic.exccode != *g_asserted_irq_idx; + test_fail += mintstatus_rval.fields.mil != *g_asserted_irq_lvl; + } else { + test_fail += mcause_rval.clic.interrupt != 0; + test_fail += mcause_rval.clic.exccode != 0; + test_fail += mintstatus_rval.fields.mil != 0; + } + + // Lower lvl than previously set + previous_idx = *g_asserted_irq_idx; + previous_lvl = *g_asserted_irq_lvl; + *g_asserted_irq_idx = get_random_interrupt_number(0, previous_idx-1); + *g_asserted_irq_lvl = get_random_interrupt_level(0, previous_lvl-1); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should not be taken (not enabled) + vp_assert_irq(clic_irq_vector.raw, 0); + + cvprintf(V_DEBUG, "mintstatus.mil: %02x, mcause.exccode: %08x, expected: lvl %02x, id %08x\n", mintstatus_rval.fields.mil, mcause_rval.clic.exccode, previous_lvl, previous_idx); + test_fail += mcause_rval.clic.interrupt != 1; + test_fail += mcause_rval.clic.exccode != previous_idx; + test_fail += mintstatus_rval.fields.mil != previous_lvl; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; + +} + +// ----------------------------------------------------------------------------- + +uint32_t rw_mscratchcsw(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t reg_backup_1 = 0; + volatile uint32_t reg_backup_2 = 0; + volatile mstatus_t mstatus_rval = { 0 }; + volatile uint32_t mscratch = 0; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + __asm__ volatile (R"( + csrrs %[rd1], mstatus, zero + )":[rd1] "=r"(mstatus_rval.raw) + ::); + + mstatus_rval.fields.mpp = 0x0; + + // Set mpp to zero and attempt swap + __asm__ volatile (R"( + csrrw %[rd1], mstatus, %[rd1] + add %[rd2], sp, zero + csrrw %[rd3], 0x348, sp + csrrs %[rd4], mscratch, zero + csrrw sp, 0x348, %[rd3] + add %[rd3], sp, zero + csrrw zero, mscratch, zero + )":[rd1] "+r"(mstatus_rval.raw), + [rd2] "=r"(reg_backup_1), + [rd3] "+r"(reg_backup_2), + [rd4] "=r"(mscratch) + ::); + + cvprintf(V_DEBUG, "Reg1 read: %08x, mscratchcsw swap result: %08x, mscratch: %08x\n", reg_backup_1, reg_backup_2, mscratch); + test_fail += reg_backup_1 != reg_backup_2 || reg_backup_1 != mscratch; + + mstatus_rval.fields.mpp = 0x3; + // Set mpp to 0x3 and attempt swap + __asm__ volatile (R"( + csrrw %[rd1], mstatus, %[rd1] + add %[rd2], sp, zero + csrrw %[rd3], 0x348, sp + csrrs %[rd4], mscratch, zero + csrrw sp, 0x348, %[rd3] + )":[rd1] "+r"(mstatus_rval.raw), + [rd2] "=r"(reg_backup_1), + [rd3] "=r"(reg_backup_2), + [rd4] "=r"(mscratch) + ::); + + cvprintf(V_DEBUG, "Reg1 read: %08x, mscratchcsw swap result: %08x, mscratch: %08x\n", reg_backup_1, reg_backup_2, mscratch); + test_fail += reg_backup_1 != reg_backup_2 || mscratch != 0; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t rw_mscratchcsw_illegal(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t reg_backup_1 = 0; + volatile mstatus_t mstatus_rval = { 0 }; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Set mpp to 0x3 and attempt swap + mstatus_rval.fields.mpp = 0x3; + __asm__ volatile (R"( csrrs zero, mstatus, %[rs1])" + :: [rs1] "r"(mstatus_rval.raw):); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs %[rd], 0x348, sp)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs zero, 0x348, sp)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc %[rd], 0x348, sp)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc zero, 0x348, sp)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs %[rd], 0x348, zero)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs zero, 0x348, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc %[rd], 0x348, zero)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc zero, 0x348, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi %[rd], 0x348, 0x1f)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi zero, 0x348, 0x1f)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi %[rd], 0x348, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi zero, 0x348, 0x0)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci %[rd], 0x348, 0x1f)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci zero, 0x348, 0x1f)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci %[rd], 0x348, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci zero, 0x348, 0x0)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw zero, 0x348, %[rs1])" + :: [rs1] "r"(reg_backup_1) :); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw zero, 0x348, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw %[rd], 0x348, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // Set mpp to 0x0 and attempt swap + mstatus_rval.fields.mpp = 0x3; + __asm__ volatile (R"( csrrc zero, mstatus, %[rs1])" + :: [rs1] "r"(mstatus_rval.raw):); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs %[rd], 0x348, sp)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs zero, 0x348, sp)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc %[rd], 0x348, sp)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc zero, 0x348, sp)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs %[rd], 0x348, zero)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs zero, 0x348, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc %[rd], 0x348, zero)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc zero, 0x348, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi %[rd], 0x348, 0x1f)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi zero, 0x348, 0x1f)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi %[rd], 0x348, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi zero, 0x348, 0x0)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci %[rd], 0x348, 0x1f)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci zero, 0x348, 0x1f)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci %[rd], 0x348, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci zero, 0x348, 0x0)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw zero, 0x348, %[rs1])" + :: [rs1] "r"(reg_backup_1) :); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw zero, 0x348, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw %[rd], 0x348, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t rw_mscratchcswl(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t reg_backup_1 = 0; + volatile uint32_t reg_backup_2 = 0; + volatile uint32_t mscratch = 0; + volatile mcause_t mcause_rval = { 0 }; + volatile clic_t clic_irq_vector = { 0 }; + volatile mintstatus_t mintstatus_rval = { 0 }; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Need an mret to clear out mintstatus due to previous tests -> take an interrupt and return + *g_special_handler_idx = 3; + mcause_rval.clic.mpil = 0; + __asm__ volatile ( R"( + csrrw zero, mcause, %[rs1] + csrrsi zero, 0x345, 0x8 + )": + :[rs1] "r"(mcause_rval.raw) + :); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x1, + .fields.level = 0xff, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + vp_assert_irq(clic_irq_vector.raw, 0); + + // Case 1: + // No pending interrupt, mpil zero - no swap + vp_assert_irq(0, 0); + + __asm__ volatile ( R"( + csrrw zero, mscratch, zero + add %[rd1], sp, zero + csrrw %[rd2], 0x349, sp + csrrs %[rd3], mscratch, zero + + csrrs %[rd4], mcause, zero + csrrs %[rd5], 0xfb1, zero + )":[rd1] "=r"(reg_backup_1), + [rd2] "=r"(reg_backup_2), + [rd3] "=r"(mscratch), + [rd4] "=r"(mcause_rval.raw), + [rd5] "=r"(mintstatus_rval.raw) + ::); + + cvprintf(V_DEBUG, "Reg1 read: %08x, mscratchcswl swap result: %08x, mscratch: %08x, mcause.mpil: %01x, minstatus.mil: %01x\n", reg_backup_1, reg_backup_2, mscratch, mcause_rval.clic.mpil, mintstatus_rval.fields.mil); + test_fail += reg_backup_1 != reg_backup_2 || mscratch != 0; + + // Case 2: + // Pending interrupt, mpil zero - swap + + // Disable interrupts with mnxti (write side-effects could occur): + __asm__ volatile (R"( + csrrci zero, 0x345, 0x8 + )":::); + + *g_asserted_irq_idx = get_random_interrupt_number(1, NUM_INTERRUPTS); + *g_asserted_irq_lvl = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should not be taken (not enabled) + vp_assert_irq(clic_irq_vector.raw, 0); + + // Disable interrupts with mnxti (write side-effects should occur): + if (*g_asserted_irq_lvl != 0) { + __asm__ volatile (R"( + csrrw zero, mscratch, zero + csrrci zero, 0x345, 0x8 + csrrs %[rd1], 0xfb1, zero + csrrs %[rd2], mcause, zero + add %[rd3], sp, zero + + csrrw %[rd4], 0x349, sp + csrrs %[rd5], mscratch, zero + csrrw sp, 0x349, %[rd4] + + add %[rd4], sp, zero + csrrw zero, mscratch, zero + )":[rd1] "=r"(mintstatus_rval.raw), + [rd2] "=r"(mcause_rval.raw), + [rd3] "=r"(reg_backup_1), + [rd4] "=r"(reg_backup_2), + [rd5] "=r"(mscratch) + ::); + } + + cvprintf(V_DEBUG, "Reg1 read: %08x, mscratchcswl swap result: %08x, mscratch: %08x, mcause.mpil: %01x, minstatus.mil: %01x\n", reg_backup_1, reg_backup_2, mscratch, mcause_rval.clic.mpil, mintstatus_rval.fields.mil); + test_fail += reg_backup_1 != reg_backup_2 || reg_backup_1 != mscratch; + vp_assert_irq(0, 0); + + // Case 3: + // No pending interrupt, mpil non-zero - swap + + // Need an mret to clear out mintstatus -> take an interrupt and return + *g_special_handler_idx = 3; + mcause_rval.clic.mpil = 0; + __asm__ volatile ( R"( + csrrw zero, mcause, %[rs1] + csrrsi zero, 0x345, 0x8 + )": + :[rs1] "r"(mcause_rval.raw) + :); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x1, + .fields.level = 0xff, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + vp_assert_irq(clic_irq_vector.raw, 0); + + vp_assert_irq(0, 0); + + mcause_rval.clic.mpil = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS); + + // clear mscratch, update mintstatus.mil with mnxti, write nonzero value to mcause.mpil then run test + __asm__ volatile ( R"( + csrrw zero, mscratch, zero + csrrci zero, 0x345, 0x8 + csrrw zero, mcause, %[rs1] + csrrs %[rd5], 0xfb1, zero + add %[rd2], sp, zero + + csrrw %[rd3], 0x349, sp + csrrs %[rd4], mscratch, zero + csrrw sp, 0x349, %[rd3] + + add %[rd3], sp, zero + csrrw zero, mscratch, zero + )":[rd2] "=r"(reg_backup_2), + [rd3] "+r"(reg_backup_1), + [rd4] "=r"(mscratch), + [rd5] "=r"(mintstatus_rval.raw) + :[rs1] "r"(mcause_rval.raw) + :); + + cvprintf(V_DEBUG, "Reg1 read: %08x, mscratchcswl swap result: %08x, mscratch: %08x, mcause.mpil: %01x, mintstatus.mil: %01x\n", reg_backup_1, reg_backup_2, mscratch, mcause_rval.clic.mpil, mintstatus_rval.fields.mil); + test_fail += reg_backup_1 != reg_backup_2 || reg_backup_1 != mscratch; + + // Case 4: + // Pending interrupt, mpil non-zero - no swap + + // Need an mret to clear out mintstatus -> take an interrupt and return + *g_special_handler_idx = 3; + mcause_rval.clic.mpil = 0; + __asm__ volatile ( R"( + csrrw zero, mcause, %[rs1] + csrrsi zero, 0x345, 0x8 + )": + :[rs1] "r"(mcause_rval.raw) + :); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = 0x1, + .fields.level = 0xff, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + vp_assert_irq(clic_irq_vector.raw, 0); + + vp_assert_irq(0, 0); + + *g_asserted_irq_idx = get_random_interrupt_number(1, NUM_INTERRUPTS); + *g_asserted_irq_lvl = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should not be taken (not enabled) + vp_assert_irq(clic_irq_vector.raw, 0); + mcause_rval.clic.mpil = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS); + + __asm__ volatile ( R"( + csrrw zero, mscratch, zero + csrrci zero, 0x345, 0x8 + csrrw zero, mcause, %[rd2] + + csrrs %[rd1], 0xfb1, zero + csrrs %[rd2], mcause, zero + + add %[rd3], zero, sp + + csrrw %[rd4], 0x349, sp + csrrs %[rd5], mscratch, zero + csrrw sp, 0x349, %[rd4] + + add %[rd4], sp, zero + csrrw zero, mscratch, zero + )":[rd1] "=r"(mintstatus_rval.raw), + [rd2] "+r"(mcause_rval.raw), + [rd3] "=r"(reg_backup_1), + [rd4] "+r"(reg_backup_2), + [rd5] "=r"(mscratch) + ::); + + cvprintf(V_DEBUG, "Reg1 read: %08x, mscratchcswl swap result: %08x, mscratch: %08x, mcause.mpil: %01x, mintstatus.mil: %01x\n", reg_backup_1, reg_backup_2, mscratch, mcause_rval.clic.mpil, mintstatus_rval.fields.mil); + test_fail += reg_backup_1 != reg_backup_2 || mscratch != 0; + vp_assert_irq(0, 0); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t rw_mscratchcswl_illegal(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t reg_backup_1 = 0; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs %[rd], 0x349, sp)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs zero, 0x349, sp)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc %[rd], 0x349, sp)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc zero, 0x349, sp)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs %[rd], 0x349, zero)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrs zero, 0x349, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc %[rd], 0x349, zero)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrc zero, 0x349, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi %[rd], 0x349, 0x1f)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi zero, 0x349, 0x1f)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi %[rd], 0x349, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrsi zero, 0x349, 0x0)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci %[rd], 0x349, 0x1f)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci zero, 0x349, 0x1f)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci %[rd], 0x349, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrci zero, 0x349, 0x0)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw zero, 0x349, %[rs1])" + :: [rs1] "r"(reg_backup_1) :); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw zero, 0x349, zero)":::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + *g_expect_illegal = 1; + __asm__ volatile (R"( csrrw %[rd], 0x349, 0x0)" + : [rd] "=r"(reg_backup_1) ::); + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t mret_with_minhv(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile mcause_t mcause = { 0 }; + volatile uint32_t check_val = 0; + volatile uint32_t result = 0; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + __asm__ volatile ( R"( + csrrs %[rd1], mcause, zero + )":[rd1] "=r"(mcause.raw) + ::); + + mcause.clic.minhv = 1; + mcause.clic.mpp = 0x3; + mcause.clic.mpie = 0; + + __asm__ volatile (R"( + csrrw zero, mcause, %[mcause] + la t0, 1f + csrrw zero, mepc, t0 + mret + addi %[check_val], zero, 42 + jal zero, 2f + 1: .word(2f) + .space 0x100, 0x0 + 2: addi %[result], %[check_val], 0 + )":[check_val] "+r"(check_val), + [result] "=r"(result) + :[mcause] "r"(mcause.raw) + :"t0"); + + // Clear minhv-bit + mcause.clic.minhv = 0; + + __asm__ volatile (R"( + csrrw zero, mcause, %[mcause] + )"::[mcause] "r"(mcause.raw)); + + test_fail += (result != 0); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +void reset_cpu_interrupt_lvl(void) { + volatile mcause_t mcause = { 0 }; + volatile mstatus_t mstatus = { 0 }; + volatile uint32_t pc = 0; + + __asm__ volatile ( R"( + csrrs %[mstatus], mstatus, zero + csrrs %[mcause], mcause, zero + )":[mstatus] "=r"(mstatus.raw), + [mcause] "=r"(mcause.raw) + ::); + + mcause.clic.mpil = 0; + mcause.clic.mpie = mstatus.fields.mie; + mcause.clic.mpp = 0x3; + mcause.clic.minhv = 0; + + __asm__ volatile ( R"( + la %[pc], continued + csrrw zero, mcause, %[mcause] + csrrw zero, mepc, %[pc] + mret + continued: + nop + )":[pc] "+r"(pc) + :[mcause] "r"(mcause.raw) + :); + return; +} + +// ----------------------------------------------------------------------------- + +uint32_t mintthresh_lower(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile mintthresh_t mintthresh = { 0 }; + volatile mintstatus_t mintstatus = { 0 }; + volatile uint32_t mnxti_rval = 0; + volatile clic_t clic_irq_vector = { 0 }; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + mintthresh.fields.th = 0xff; + *g_special_handler_idx = 4; + + __asm__ volatile (R"(csrrs %[rd], 0xfb1, zero)":[rd] "=r"(mintstatus.raw)); + // To be potentially set by handler if incorrectly entered + *g_irq_handler_reported_error = 0; + + *g_asserted_irq_idx = get_random_interrupt_number(0, NUM_INTERRUPTS); + + // Random interrupt with higher level than core, but lower than mintthresh; + *g_asserted_irq_lvl = get_random_interrupt_level(mintstatus.fields.mil + 1, NUM_INTERRUPT_LVLS-1); + + if (*g_asserted_irq_lvl <= mintstatus.fields.mil) { + // Reset cpu interrupt level, as we cannot not reach our desired test case + reset_cpu_interrupt_lvl(); + } + + cvprintf(V_DEBUG, "mintthresh.th: %01x, interrupt: %02x, level: %02x\n", mintthresh.fields.th, *g_asserted_irq_idx, *g_asserted_irq_lvl); + + __asm__ volatile ( R"( + csrrw zero, 0x347, %[rs1] + csrrsi zero, 0x345, 0x8 + )": + :[rs1] "r"(mintthresh.raw) + :); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should not be taken (mintthresh.th too high) + vp_assert_irq(clic_irq_vector.raw, 0); + + __asm__ volatile ( R"( + csrrci %[rd1], 0x345, 0x8 + )":[rd1] "=r"(mnxti_rval) + : + :); + + cvprintf(V_DEBUG, "mnxti rval: %08x\n", mnxti_rval); + + // Mnxti should have read zero + test_fail += mnxti_rval ? 1 : 0; + // Interrupt should not have been taken + test_fail += *g_irq_handler_reported_error; + vp_assert_irq(0, 0); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t mintthresh_higher(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t mnxti_rval = 0; + volatile uint32_t mtvt = 0; + volatile mintthresh_t mintthresh = { 0 }; + volatile mintstatus_t mintstatus = { 0 }; + volatile clic_t clic_irq_vector = { 0 }; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_special_handler_idx = 5; + + __asm__ volatile (R"(csrrs %[rd], 0xfb1, zero)":[rd] "=r"(mintstatus.raw)); + + // To be cleared by handler + *g_irq_handler_reported_error = 1; + mintthresh.fields.th = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS-1); + *g_asserted_irq_idx = get_random_interrupt_number(1, NUM_INTERRUPTS); + *g_asserted_irq_lvl = get_random_interrupt_level(mintthresh.fields.th + 1, NUM_INTERRUPT_LVLS); + + if (*g_asserted_irq_lvl <= mintstatus.fields.mil) { + // Reset cpu interrupt level, as we cannot not reach our desired test case + reset_cpu_interrupt_lvl(); + } + + cvprintf(V_DEBUG, "mintthresh.th: %01x, interrupt: %02x, level: %02x\n", mintthresh.fields.th, *g_asserted_irq_idx, *g_asserted_irq_lvl); + + vp_assert_irq(0, 0); + __asm__ volatile ( R"( + csrrw zero, 0x347, %[rs1] + csrrsi %[rd1], 0x345, 0x8 + )":[rd1] "=r"(mnxti_rval) + :[rs1] "r"(mintthresh.raw) + :); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should be taken (mintthresh.th low enough) + vp_assert_irq(clic_irq_vector.raw, 0); + + __asm__ volatile ( R"( + csrrci %[rd1], 0x345, 0x8 + csrrs %[rd2], 0x307, zero + )":[rd1] "=r"(mnxti_rval), + [rd2] "=r"(mtvt) + : + :); + + cvprintf(V_DEBUG, "mnxti rval: %08x\n", mnxti_rval); + + test_fail += *g_irq_handler_reported_error; + test_fail += (mnxti_rval != mtvt + (*g_asserted_irq_idx * 4)); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t mintthresh_equal(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t mnxti_rval = 0; + volatile mintthresh_t mintthresh = { 0 }; + volatile mintstatus_t mintstatus = { 0 }; + volatile clic_t clic_irq_vector = { 0 }; + + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_special_handler_idx = 6; + + __asm__ volatile (R"(csrrs %[rd], 0xfb1, zero)":[rd] "=r"(mintstatus.raw)); + + // To be set by handler in case of entry + *g_irq_handler_reported_error = 0; + mintthresh.fields.th = get_random_interrupt_level(1, NUM_INTERRUPT_LVLS); + *g_asserted_irq_idx = get_random_interrupt_number(1, NUM_INTERRUPTS); + *g_asserted_irq_lvl = mintthresh.fields.th; + + if (*g_asserted_irq_lvl <= mintstatus.fields.mil) { + // Reset cpu interrupt level, as we cannot not reach our desired test case + reset_cpu_interrupt_lvl(); + } + + cvprintf(V_DEBUG, "mintthresh.th: %01x, interrupt: %02x, level: %02x\n", mintthresh.fields.th, *g_asserted_irq_idx, *g_asserted_irq_lvl); + + vp_assert_irq(0, 0); + __asm__ volatile ( R"( + csrrw zero, 0x347, %[rs1] + csrrsi %[rd1], 0x345, 0x8 + )":[rd1] "=r"(mnxti_rval) + :[rs1] "r"(mintthresh.raw) + :); + + clic_irq_vector = (clic_t){ + .fields.irq = 0x1, + .fields.id = *g_asserted_irq_idx, + .fields.level = *g_asserted_irq_lvl, + .fields.priv = 0x3, + .fields.shv = 0x0 + }; + + // asserted interrupt should not be taken (mintthresh.th too high) + vp_assert_irq(clic_irq_vector.raw, 0); + + __asm__ volatile ( R"( + csrrci %[rd1], 0x345, 0x8 + )":[rd1] "=r"(mnxti_rval) + : + :); + + cvprintf(V_DEBUG, "mnxti rval: %08x\n", mnxti_rval); + + test_fail += *g_irq_handler_reported_error; + test_fail += (mnxti_rval != 0); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- +// Note that the following interrupt/exception handler is not generic and specific +// to this test. + +__attribute__((interrupt("machine"))) void u_sw_irq_handler(void) { + volatile uint32_t mepc; + volatile uint32_t result = 0; + volatile uint32_t mtvt = 0; + volatile mcause_t mcause = { 0 }; + + // RWX !L & MODE OFF + volatile const uint32_t pmp_enable_access_all = 0x07070707; + + __asm__ volatile ( R"( + csrrs %[mc], mcause, x0 + csrrs %[mp], mepc, x0 + csrrs %[mtvt], 0x307, x0 + )" + : [mc] "=r"(mcause.raw), + [mp] "=r"(mepc), + [mtvt] "=r"(mtvt) + : + : + ); + + cvprintf(V_DEBUG, "In handler, mepc: 0x%08lx, mcause: 0x%08lx\n", mepc, mcause.raw); + + switch (*g_special_handler_idx) { + case 1: + result = r_mnxti_with_irq_handler(0, NUM_INTERRUPTS, 2, NUM_INTERRUPT_LVLS); + if (result != (mtvt + (*g_asserted_irq_idx) * 4)) { + cvprintf(V_DEBUG, "Mismatch, expected: 0x%08lx, actual: 0x%08lx\n", mtvt + ((*g_asserted_irq_idx) * 4), result); + *g_irq_handler_reported_error = 1; + } else { + *g_irq_handler_reported_error = 0; + } + vp_assert_irq(0, 0); + *g_special_handler_idx = 0; + return; + break; + case 2: + result = r_mnxti_with_irq_handler(0, NUM_INTERRUPTS, 0, NUM_INTERRUPT_LVLS); + if (result != 0) { + cvprintf(V_DEBUG, "Mismatch, expected: 0x%08lx, actual: 0x%08lx\n", 0, result); + *g_irq_handler_reported_error = 1; + } else { + *g_irq_handler_reported_error = 0; + } + vp_assert_irq(0, 0); + *g_special_handler_idx = 0; + return; + break; + case 3: + mcause.raw = 0; + mcause.clic.mpp = 0x3; + mcause.clic.mpil = 0; + mcause.clic.mpie = 0; + __asm__ volatile ( R"( + csrrw zero, mcause, %[rs1] + )"::[rs1] "r"(mcause.raw):); + *g_special_handler_idx = 0; + vp_assert_irq(0, 0); + return; + break; + case 4: + *g_irq_handler_reported_error = 1; + vp_assert_irq(0, 0); + return; + break; + case 5: + *g_irq_handler_reported_error = 0; + mcause.clic.mpp = 0x3; + mcause.clic.mpil = 0; + mcause.clic.mpie = 0; + __asm__ volatile ( R"( + csrrw zero, mcause, %[rs1] + )"::[rs1] "r"(mcause.raw):); + return; + break; + case 6: + *g_irq_handler_reported_error = 1; + vp_assert_irq(0, 0); + return; + break; + } + + if (mcause.clic.interrupt == 0 && mcause.clic.exccode == 2) { + (*g_expect_illegal)--; + increment_mepc(0); + return; + } + + switch (mcause.clic.interrupt) { + case 0: + switch (mcause.clic.exccode) { + case 0x1: cvprintf(V_LOW, "Instruction access fault at 0x%08lx\n", mepc); + break; + case 0x2: cvprintf(V_LOW, "Invalid instruction fault at 0x%08lx\n", mepc); + break; + } + break; + case 1: + cvprintf(V_LOW, "Interrupt, ID: 0x%08lx, minhv status: %0d\n", mcause.clic.exccode, mcause.clic.minhv); + vp_assert_irq(0, 0); + break; + } + + // check if address is locked, then unlock + // let test be responsible for cleaning up addr-regs to + // not clutter code here + if ( /*mcause.clic.interrupt &&*/ mcause.clic.exccode == 1 && mcause.clic.minhv ) { + *g_recovery_enable = 1; + vp_assert_irq(0, 0); + cvprintf(V_LOW, "Encountered read access fault, trying to enable pmp access\n"); + __asm__ volatile ( R"( + csrrw x0, pmpcfg0, %[access_ena] + csrrw x0, pmpcfg1, %[access_ena] + csrrw x0, pmpcfg2, %[access_ena] + csrrw x0, pmpcfg3, %[access_ena] + csrrw x0, pmpcfg4, %[access_ena] + csrrw x0, pmpcfg5, %[access_ena] + csrrw x0, pmpcfg6, %[access_ena] + csrrw x0, pmpcfg7, %[access_ena] + csrrw x0, pmpcfg8, %[access_ena] + csrrw x0, pmpcfg9, %[access_ena] + csrrw x0, pmpcfg10, %[access_ena] + csrrw x0, pmpcfg11, %[access_ena] + csrrw x0, pmpcfg12, %[access_ena] + csrrw x0, pmpcfg13, %[access_ena] + csrrw x0, pmpcfg14, %[access_ena] + csrrw x0, pmpcfg15, %[access_ena] + + csrrs t0, mepc, x0 + lw t0, 0(t0) + lui t1, 0x40000 + csrrc x0, mcause, t1 + csrrw x0, mepc, t0 + )" + : + : [access_ena] "r" (pmp_enable_access_all) + : "t0", "t1" + ); + } + + return; +} +// ----------------------------------------------------------------------------- +_Pragma("GCC pop_options") +// ----------------------------------------------------------------------------- + diff --git a/cv32e40s/tests/programs/custom/clic/test.yaml b/cv32e40s/tests/programs/custom/clic/test.yaml new file mode 100644 index 0000000000..90749f7fab --- /dev/null +++ b/cv32e40s/tests/programs/custom/clic/test.yaml @@ -0,0 +1,8 @@ +name: clic +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + CLIC directed test +plusargs: > + +clic_irq_clear_on_ack=0 +cflags: > + -mno-relax diff --git a/cv32e40s/tests/programs/custom/cov_holes_generic/cov_holes_generic.c b/cv32e40s/tests/programs/custom/cov_holes_generic/cov_holes_generic.c new file mode 100644 index 0000000000..ba618efec1 --- /dev/null +++ b/cv32e40s/tests/programs/custom/cov_holes_generic/cov_holes_generic.c @@ -0,0 +1,1000 @@ +// +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran +// +// Debug directed tests +// +// Requires: number of triggers >= 1 +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 1 +// Start at 1 (ignore dummy test that is only used for env sanity checking during dev.) +#define START_TEST_NUM 0 +// Abort test at first self-check fail, useful for debugging. +#define ABORT_ON_ERROR_IMMEDIATE 0 + +// Addresses of VP interrupt control registers +#define TIMER_REG_ADDR ((volatile uint32_t * volatile) (CV_VP_INTR_TIMER_BASE)) +#define TIMER_VAL_ADDR ((volatile uint32_t * volatile) (CV_VP_INTR_TIMER_BASE + 4)) +#define DEBUG_REQ_CONTROL_REG *((volatile uint32_t * volatile) (CV_VP_DEBUG_CONTROL_BASE)) + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + +// --------------------------------------------------------------- +// Type definitions +// --------------------------------------------------------------- + + +// Verbosity levels (Akin to the uvm verbosity concept) +typedef enum { + V_OFF = 0, + V_LOW = 1, + V_MEDIUM = 2, + V_HIGH = 3, + V_DEBUG = 4 +} verbosity_t; + +typedef enum { + MCAUSE_ACCESS_FAULT = 1, + MCAUSE_ILLEGAL = 2, + MCAUSE_BREAKPT = 3, + MCAUSE_LOAD_FAULT = 5, + MCAUSE_STORE_FAULT = 7, + MCAUSE_UMODE_ECALL = 8, + MCAUSE_MMODE_ECALL = 11, + MCAUSE_INSTR_BUS_FAULT = 24, + MCAUSE_CHK_FAULT = 25, +} mcause_exception_status_t; + +typedef enum { + DCAUSE_EBREAK = 1, + DCAUSE_TRIGGER = 2, + DCAUSE_HALTREQ = 3, + DCAUSE_STEP = 4, + DCAUSE_RESETHALTREQ = 5, + DCAUSE_HALTGROUP = 6, +} dcsr_cause_t; + +typedef enum { + MODE_USER = 0, + MODE_SUPERVISOR = 1, + MODE_RESERVED = 2, + MODE_MACHINE = 3 +} mode_t; + +typedef enum { + PMPMODE_OFF = 0, + PMPMODE_TOR = 1, + PMPMODE_NA4 = 2, + PMPMODE_NAPOT = 3 +} pmp_mode_t; + +typedef union { + struct { + volatile uint32_t r : 1; + volatile uint32_t w : 1; + volatile uint32_t x : 1; + volatile uint32_t a : 1; + volatile uint32_t reserved_6_5 : 2; + volatile uint32_t l : 1; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 8; +} __attribute__((packed)) pmpsubcfg_t; + +typedef union { + struct { + volatile uint32_t cfg : 8; + } __attribute__((packed)) volatile reg_idx[4]; + volatile uint32_t raw : 32; +} __attribute__((packed)) pmpcfg_t; + +typedef union { + struct { + volatile uint32_t mml : 1; + volatile uint32_t mmwp : 1; + volatile uint32_t rlb : 1; + volatile uint32_t reserved_31_3 : 29; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} mseccfg_t; + +typedef union { + struct { + volatile uint32_t shv : 1; + volatile uint32_t priv : 2; + volatile uint32_t level : 8; + volatile uint32_t id : 11; + volatile uint32_t irq : 1; + volatile uint32_t reserved_31_22 : 9; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) clic_t ; + +typedef union { + struct { + volatile uint32_t irq_0 : 1; + volatile uint32_t irq_1 : 1; + volatile uint32_t irq_2 : 1; + volatile uint32_t irq_3 : 1; + volatile uint32_t irq_4 : 1; + volatile uint32_t irq_5 : 1; + volatile uint32_t irq_6 : 1; + volatile uint32_t irq_7 : 1; + volatile uint32_t irq_8 : 1; + volatile uint32_t irq_9 : 1; + volatile uint32_t irq_10 : 1; + volatile uint32_t irq_11 : 1; + volatile uint32_t irq_12 : 1; + volatile uint32_t irq_13 : 1; + volatile uint32_t irq_14 : 1; + volatile uint32_t irq_15 : 1; + volatile uint32_t irq_16 : 1; + volatile uint32_t irq_17 : 1; + volatile uint32_t irq_18 : 1; + volatile uint32_t irq_19 : 1; + volatile uint32_t irq_20 : 1; + volatile uint32_t irq_21 : 1; + volatile uint32_t irq_22 : 1; + volatile uint32_t irq_23 : 1; + volatile uint32_t irq_24 : 1; + volatile uint32_t irq_25 : 1; + volatile uint32_t irq_26 : 1; + volatile uint32_t irq_27 : 1; + volatile uint32_t irq_28 : 1; + volatile uint32_t irq_29 : 1; + volatile uint32_t irq_30 : 1; + volatile uint32_t irq_31 : 1; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) clint_t; + +typedef union { + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_30_12 : 19; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clint; + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_15_12 : 4; + volatile uint32_t mpil : 8; + volatile uint32_t res_26_24 : 3; + volatile uint32_t mpie : 1; + volatile uint32_t mpp : 2; + volatile uint32_t minhv : 1; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clic; + volatile uint32_t raw : 32; +} __attribute__((packed)) mcause_t; + +typedef union { + struct { + volatile uint32_t data : 27; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) tdata1_t; + +typedef union { + struct { + volatile uint16_t load : 1; + volatile uint16_t store : 1; + volatile uint16_t execute : 1; + volatile uint16_t u : 1; + volatile uint16_t s : 1; + volatile uint16_t res_5_5 : 1; + volatile uint16_t m : 1; + volatile uint16_t match : 4; + volatile uint16_t chain : 1; + volatile uint16_t action : 4; + volatile uint16_t sizelo : 2; + volatile uint16_t timing : 1; + volatile uint16_t select : 1; + volatile uint16_t hit : 1; + volatile uint16_t maskmax : 6; + volatile uint16_t dmode : 1; + volatile uint16_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mcontrol_t; + +typedef union { + struct { + volatile uint16_t load : 1; + volatile uint16_t store : 1; + volatile uint16_t execute : 1; + volatile uint16_t u : 1; + volatile uint16_t s : 1; + volatile uint16_t res_5_5 : 1; + volatile uint16_t m : 1; + volatile uint16_t match : 4; + volatile uint16_t chain : 1; + volatile uint16_t action : 4; + volatile uint16_t size : 4; + volatile uint16_t timing : 1; + volatile uint16_t select : 1; + volatile uint16_t hit : 1; + volatile uint16_t vu : 1; + volatile uint16_t vs : 1; + volatile uint16_t res_26_25: 2; + volatile uint16_t dmode : 1; + volatile uint16_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mcontrol6_t; + +typedef union { + struct { + volatile uint8_t action : 6; + volatile uint8_t u : 1; + volatile uint8_t s : 1; + volatile uint8_t res_8_8 : 1; + volatile uint8_t m : 1; + volatile uint8_t res_10_10 : 1; + volatile uint8_t vu : 1; + volatile uint8_t vs : 1; + volatile uint16_t res_25_13 : 13; + volatile uint8_t hit : 1; + volatile uint8_t dmode : 1; + volatile uint8_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) etrigger_t; + +typedef union { + struct { + volatile uint16_t info : 16; + volatile uint16_t res_31_16 : 16; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) tinfo_t; + +typedef union { + struct { + volatile uint8_t uie : 1; // 0 + volatile uint8_t sie : 1; // 1 + volatile uint8_t wpri : 1; // 2 + volatile uint8_t mie : 1; // 3 + volatile uint8_t upie : 1; // 4 + volatile uint8_t spie : 1; // 5 + volatile uint8_t wpri0 : 1; // 6 + volatile uint8_t mpie : 1; // 7 + volatile uint8_t spp : 1; // 8 + volatile uint8_t wpri1 : 2; // 10: 9 + volatile uint8_t mpp : 2; // 12:11 + volatile uint8_t fs : 2; // 14:13 + volatile uint8_t xs : 2; // 16:15 + volatile uint8_t mprv : 1; // 17 + volatile uint8_t sum : 1; // 18 + volatile uint8_t mxr : 1; // 19 + volatile uint8_t tvm : 1; // 20 + volatile uint8_t tw : 1; // 21 + volatile uint8_t tsr : 1; // 22 + volatile uint8_t wpri3 : 8; // 30:23 + volatile uint8_t sd : 1; // 31 + } volatile clint; + volatile uint32_t raw; +} __attribute__((packed)) mstatus_t; + +typedef union { + struct { + volatile uint16_t start_delay : 15; // 14: 0 + volatile uint16_t rand_start_delay : 1; // 15 + volatile uint16_t pulse_width : 13; // 28:16 + volatile uint16_t rand_pulse_width : 1; // 29 + volatile uint16_t pulse_mode : 1; // 30 0 = level, 1 = pulse + volatile uint16_t value : 1; // 31 + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) debug_req_control_t; + +typedef union { + struct { + volatile uint16_t prv : 2; // 1:0 WARL (0x0, 0x3) PRV. Returns the privilege mode before debug entry. + volatile uint16_t step : 1; // 2 RW STEP. Set to enable single stepping. + volatile uint16_t nmip : 1; // 3 R NMIP. If set, an NMI is pending + volatile uint16_t mprven : 1; // 4 WARL (0x1) MPRVEN. Hardwired to 1. + volatile uint16_t res_5_5 : 1; // 5 WARL (0x0) V. Hardwired to 0. + volatile uint16_t cause : 3; // 8:6 R CAUSE. Return the cause of debug entry. + volatile uint16_t stoptime : 1; // 9 WARL (0x0) STOPTIME. Hardwired to 0. + volatile uint16_t stopcount : 1; // 10 WARL STOPCOUNT. + volatile uint16_t stepie : 1; // 11 WARL STEPIE. Set to enable interrupts during single stepping. + volatile uint16_t ebreaku : 1; // 12 WARL EBREAKU. Set to enter debug mode on ebreak during user mode. + volatile uint16_t ebreaks : 1; // 13 WARL (0x0) EBREAKS. Hardwired to 0. + volatile uint16_t res_14_14 : 1; // 14 WARL (0x0) Hardwired to 0. + volatile uint16_t ebreakm : 1; // 15 RW EBREAKM. Set to enter debug mode on ebreak during machine mode. + volatile uint16_t ebreakvu : 1; // 16 WARL (0x0) EBREAKVU. Hardwired to 0. + volatile uint16_t ebreakvs : 1; // 17 WARL (0x0) EBREAKVS. Hardwired to 0 + volatile uint16_t res_27_18 : 10; // 27:18 WARL (0x0) Reserved + volatile uint16_t xdebugver : 4; // 31:28 R (0x4) XDEBUGVER. External debug support exists as described in [RISC-V-DEBUG]. + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) dcsr_t; + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- + +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +// Global pointer variables +volatile uint32_t * volatile g_has_clic; + +// External symbols +extern volatile uint32_t mtvt_table; + +// Message strings for use in assembly printf +//const volatile char * const volatile asm_printf_msg_template = "Entered handler %0d\n"; + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t dummy(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Prototypes for functions that are test specific and +// perform the debug part of specific tests. +// --------------------------------------------------------------- +//void template_function_dbg(void) __attribute__((section(".debugger"), __noinline__)); + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +void set_dpc(volatile uint32_t dpc) __attribute__((__noinline__)); +void increment_dpc(volatile uint32_t incr_val); +void increment_mepc(volatile uint32_t incr_val); +void set_pmpcfg(pmpsubcfg_t pmpcfg, uint32_t reg_no); +uint32_t set_val(uint32_t * ptr, uint32_t val); +uint32_t incr_val(uint32_t * ptr); +uint32_t has_pmp_configured(void); + +// IRQ related +uint32_t detect_irq_mode(void); +void setup_clic(void); +void assert_irq(void); +void deassert_irq(void); +void clint_mie_enable(uint8_t irq_num); +void clint_mie_disable(uint8_t irq_num); + +// Debug specific helper code +void disable_debug_req(void) __attribute__((section(".debugger"))); + + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(volatile uint32_t test_no, volatile uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...) __attribute((__noinline__)); + +/* + * vp_assert_irq + * + * Notify clic_interrupt_agent vp to assert given + * clic interrupt + */ +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + // Allocate memory for global pointers here + g_has_clic = calloc(1, sizeof(uint32_t)); + + // Setup clic mtvt if clic is enabled + *g_has_clic = detect_irq_mode(); + setup_clic(); + + // Add function pointers to new tests here + tests[0] = dummy; // unused, can be used for env sanity checking + + // Run all tests in list above + cvprintf(V_LOW, "\nDebug test start\n\n"); + for (volatile uint32_t i = START_TEST_NUM; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + // Free dynamically allocated memory + free((void *)g_has_clic ); + + return retval; // Nonzero for failing tests +} + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(volatile uint32_t test_no, volatile uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_NUM; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } + return res; +} + +// ----------------------------------------------------------------------------- + +uint32_t dummy(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // ... + // Some directed test code here + // ... + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// New tests here... + +// ----------------------------------------------------------------------------- + +void disable_debug_req(void) { + volatile debug_req_control_t debug_req_ctrl; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 0, + .fields.pulse_mode = 0, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0, + .fields.rand_start_delay = 0, + .fields.start_delay = 0 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; +} + +// ----------------------------------------------------------------------------- + +void clint_mie_enable(uint8_t irq_num) { + __asm__ volatile( R"( + csrrsi zero, mstatus, 0x8 + csrrs zero, mie, %[bit] + )" + : : [bit] "r" (0x1 << irq_num) + ); +} + +// ----------------------------------------------------------------------------- + +void clint_mie_disable(uint8_t irq_num) { + __asm__ volatile( R"( + csrrc zero, mie, %[bit] + )" + : : [bit] "r" (0x1 << irq_num) + ); +} + +// ----------------------------------------------------------------------------- + +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay) { + *TIMER_REG_ADDR = mask; + *TIMER_VAL_ADDR = 1 + cycle_delay; +} + +// ----------------------------------------------------------------------------- + +// Tempate wrapper to support both clic/clint +void assert_irq(void) { + volatile clic_t clic_vector = { 0 }; + volatile clint_t clint_vector = { 0 }; + + // Use interrupt id 30 for simplicity + if (*g_has_clic == 1) { + // clic + clic_vector = (clic_t){ .fields.irq = 1, + .fields.id = 30, + .fields.level = 81, + .fields.priv = MODE_MACHINE, + .fields.shv = 1 + }; + vp_assert_irq(clic_vector.raw, 2); + } + else { + // clint + clint_vector.fields.irq_30 = 1; + vp_assert_irq(clint_vector.raw, 2); + } +} + +// ----------------------------------------------------------------------------- + +void deassert_irq(void) { + // Same for clic/clint + vp_assert_irq(0, 0); +} + +// ----------------------------------------------------------------------------- + +void increment_dpc(volatile uint32_t incr_val) { + volatile uint32_t dpc = 0; + + __asm__ volatile ( R"( + csrrs %[dpc], dpc, zero + )" : [dpc] "=r"(dpc)); + + if (incr_val == 0) { + // No increment specified, check *dpc instruction + if (((*(uint32_t *)dpc) & 0x3UL) == 0x3UL) { + // non-compressed + dpc += 4; + } else { + // compressed + dpc += 2; + } + } else { + // explicitly requested increment + dpc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, dpc, %[dpc] + )" :: [dpc] "r"(dpc)); +} + +// ----------------------------------------------------------------------------- + +void increment_mepc(volatile uint32_t incr_val) { + volatile uint32_t mepc = 0; + + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + )" : [mepc] "=r"(mepc)); + + if (incr_val == 0) { + // No increment specified, check *mepc instruction + if (((*(uint32_t *)mepc) & 0x3UL) == 0x3UL) { + // non-compressed + mepc += 4; + } else { + // compressed + mepc += 2; + } + } else { + // explicitly requested increment + mepc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, mepc, %[mepc] + )" :: [mepc] "r"(mepc)); +} + +// ----------------------------------------------------------------------------- + +void set_dpc(volatile uint32_t dpc) { + __asm__ volatile ( R"( + csrrw zero, dpc, %[dpc] + )" :: [dpc] "r"(dpc)); + cvprintf(V_MEDIUM, "Setting dpc to %08lx\n", dpc); +} + +// ----------------------------------------------------------------------------- + +uint32_t has_pmp_configured(void) { + volatile uint32_t pmpaddr0 = 0xffffffff; + volatile uint32_t pmpaddr0_backup = 0; + + __asm__ volatile (R"( + csrrw %[pmpaddr0_backup] , pmpaddr0, %[pmpaddr0] + csrrw %[pmpaddr0], pmpaddr0, %[pmpaddr0_backup] + )" :[pmpaddr0_backup] "+r"(pmpaddr0_backup), + [pmpaddr0] "+r"(pmpaddr0)); + + return (pmpaddr0 != 0); +} + +// ----------------------------------------------------------------------------- + +uint32_t __attribute__((__noinline__)) incr_val(uint32_t * ptr) { + *ptr += 1; + return *ptr; +} + +// ----------------------------------------------------------------------------- + +uint32_t __attribute__((__noinline__)) set_val(uint32_t * ptr, uint32_t val) { + *ptr = val; + return *ptr; +} + +// ----------------------------------------------------------------------------- + +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no){ + volatile pmpcfg_t temp = { 0 }; + volatile pmpcfg_t pmpcfg = { 0 }; + + pmpcfg.reg_idx[reg_no % 4].cfg = pmpsubcfg.raw; + + temp.reg_idx[reg_no % 4].cfg = 0xff; + + switch (reg_no / 4) { + case 0: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg0, t0 + csrrs zero, pmpcfg0, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 1: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg1, t0 + csrrs zero, pmpcfg1, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 2: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg2, t0 + csrrs zero, pmpcfg2, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 3: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg3, t0 + csrrs zero, pmpcfg3, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 4: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg4, t0 + csrrs zero, pmpcfg4, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + case 5: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg5, t0 + csrrs zero, pmpcfg5, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 6: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg6, t0 + csrrs zero, pmpcfg6, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 7: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg7, t0 + csrrs zero, pmpcfg7, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 8: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg8, t0 + csrrs zero, pmpcfg8, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 9: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg9, t0 + csrrs zero, pmpcfg9, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 10: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg10, t0 + csrrs zero, pmpcfg10, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 11: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg11, t0 + csrrs zero, pmpcfg11, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 12: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg12, t0 + csrrs zero, pmpcfg12, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 13: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg13, t0 + csrrs zero, pmpcfg13, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 14: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg14, t0 + csrrs zero, pmpcfg14, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 15: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg15, t0 + csrrs zero, pmpcfg15, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + } + + cvprintf(V_DEBUG, "Set pmpcfg_vector: 0x%08lx\n", pmpcfg.raw); + return; +} + +// ----------------------------------------------------------------------------- + +void setup_clic(void) { + if (*g_has_clic == 1) { + __asm__ volatile ( R"( + csrrw zero, 0x307, %[mtvt_table] + )" :: [mtvt_table] "r"(&mtvt_table)); + } +} + +// ----------------------------------------------------------------------------- + +// Template for mtvt code, this may need adaptation if you want to support +// interrupts with ids in the indices below that are populated by zeros +void __attribute__((naked)) mtvt_code(void) { + __asm__ volatile ( R"( + .global mtvt_table + .align 7 + mtvt_table: .long . + 4096 + mtvt_table_1: .long . + 4092 + mtvt_table_2: .long . + 4088 + mtvt_table_3: .long . + 4084 + mtvt_table_4: .long . + 4080 + .space 100, 0x0 + mtvt_table_30: .long . + 3976 + mtvt_table_31: .long . + 3972 + mtvt_table_32: .long . + 3968 + .space 3952, 0x0 + mtvt_table_1021: .long . + 12 + mtvt_table_1022: .long . + 8 + mtvt_table_1023: .long . + 4 + jal zero, m_fast14_irq_handler + )"); + +} + +// ----------------------------------------------------------------------------- + +uint32_t detect_irq_mode(void) { + volatile uint32_t mtvec = 0; + volatile uint32_t is_clic = 0; + + __asm__ volatile ( R"( + csrrs %[mtvec], mtvec, zero + )" : [mtvec] "=r"(mtvec)); + + if ((mtvec & 0x3) == 0x3) { + is_clic = 1; + } + + return is_clic; +} + +// ----------------------------------------------------------------------------- diff --git a/cv32e40s/tests/programs/custom/cov_holes_generic/test.yaml b/cv32e40s/tests/programs/custom/cov_holes_generic/test.yaml new file mode 100644 index 0000000000..6f3f90dea5 --- /dev/null +++ b/cv32e40s/tests/programs/custom/cov_holes_generic/test.yaml @@ -0,0 +1,8 @@ +# Test definition YAML for test + +# Generic test for known coverage holes +name: cov_holes_generic +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +program: cov_holes_generic +description: > + Generic coverage closure directed test diff --git a/cv32e40s/tests/programs/custom/csr_instr_asm/csr_instr_asm.S b/cv32e40s/tests/programs/custom/csr_instr_asm/csr_instr_asm.S index bc49eddea7..54fb4c2cfd 100644 --- a/cv32e40s/tests/programs/custom/csr_instr_asm/csr_instr_asm.S +++ b/cv32e40s/tests/programs/custom/csr_instr_asm/csr_instr_asm.S @@ -27,7 +27,6 @@ .include "user_define.h" .section .text.start .globl _start -.section .text #.include "user_init.s" .type _start, @function @@ -38,8 +37,6 @@ _start: .section .text _start_main: - #define EXP_MISA 0x40101104 - # CSR 0x340 is a 32-bit R/W scratch-pad # Immediates csrrci x0, 0x340, 0x0 diff --git a/cv32e40s/tests/programs/custom/csr_instr_asm/test.yaml b/cv32e40s/tests/programs/custom/csr_instr_asm/test.yaml index d576cdc194..907bf36721 100644 --- a/cv32e40s/tests/programs/custom/csr_instr_asm/test.yaml +++ b/cv32e40s/tests/programs/custom/csr_instr_asm/test.yaml @@ -2,3 +2,4 @@ name: csr_instr_asm uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > CSR access instruction test +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/csr_instructions/csr_instructions.c b/cv32e40s/tests/programs/custom/csr_instructions/csr_instructions.c index 9e9a7b99c0..08dfe48ed0 100644 --- a/cv32e40s/tests/programs/custom/csr_instructions/csr_instructions.c +++ b/cv32e40s/tests/programs/custom/csr_instructions/csr_instructions.c @@ -23,6 +23,7 @@ */ #include +#include #include int main(int argc, char *argv[]) diff --git a/cv32e40s/tests/programs/custom/csr_priv_gen_test/README.md b/cv32e40s/tests/programs/custom/csr_priv_gen_test/README.md new file mode 100644 index 0000000000..8751f26204 --- /dev/null +++ b/cv32e40s/tests/programs/custom/csr_priv_gen_test/README.md @@ -0,0 +1,26 @@ +Contains generated tests on U-mode csr instructions to insert illegall access + +Needs `CFG=pmp` for allowing U-mode to run. + + +# Python generator files + +## Motivation +Runing through the test-plan it became apparant at some point that it would be necessary to have tests which contained a number of instructions to satisfy testing goals. The solution became python scripts which use string manipulation to generate these instructions directly to the relevant .h and .S files in the directory. + +## Function +The script works by looping through the given file (see the top of the file .py file for name declarations) line by line until a 'trigger' string is reached, usually this string can look something like this: + +``` +// start of generated code +``` + +And everything below this line is then overwritten. + +The script will either have a list called 'reg_string' which is a manually constructed list fetched from a table in the RISC specification. The file will then parse this registry list and create ranges to include all registries within the list. It then writes instructions for that registry to file. Which instructions are based on the test plan. + +Afterwards it searches through the header file and changes the 'ILLEGALLY_GENERATED_INSN' define, which is what both the .S and .c files use when sanity checking or asserting that the number of trapped instructions matches what's been generated. There is also some info printed to the terminal about how many lines and which files are written to. + + +## Maintenance +The scripts are intended to be easily maintenable (although I guess time will tell), and therefore the generation of the instructions themselves are kept within 'generator()' functions and marked variables. If there's a need to change the number of registries, the types of instructions etc. these are found there. Afterwards you should be able to run the script and it will properly update the instructions for you. diff --git a/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen.py b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen.py new file mode 100644 index 0000000000..11c373966f --- /dev/null +++ b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen.py @@ -0,0 +1,131 @@ +""" +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** This script generates four csr-instructions for every csr-register according to the 'reg_str'. This is then written directly to the 'csr_privilege_loop.S' +** +******************************************************************************* +""" + +# Filenames +headername = "csr_priv_gen_test.h" # name of the header file that will be written to +filename = "csr_priv_loop.S" # file which will be written to + + +# Trigger strings +input_string = "// Start of generated code." # start string. This tells the script what to look for and moves the write HEAD to the right line +header_string = "//start of the function header" # Header start string + + +# Global variables +pointer = 0 # file pointer +num_lines = 0 # number of lines written to file + + +# Register list which is used to generate the instructions. +# List fetched manually from the spec (V20211203), contains all S-, R-, and M-mode CSR registers +reg_str = """ +0x100-0x1FF +0x500-0x57F +0x580-0x5BF +0x5C0-0x5FF +0x900-0x97F +0x980-0x9BF +0x9C0-0x9FF +0xD00-0xD7F +0xD80-0xDBF +0xDC0-0xDFF +0x200-0x2FF +0x600-0x67F +0x680-0x6BF +0x6C0-0x6FF +0xA00-0xA7F +0xA80-0xABF +0xAC0-0xAFF +0xE00-0xE7F +0xE80-0xEBF +0xEC0-0xEFF +0x300-0x3FF +0x700-0x77F +0x780-0x79F +0x7A0-0x7AF +0x7B0-0x7BF +0x7C0-0x7FF +0xB00-0xB7F +0xB80-0xBBF +0xBC0-0xBFF +0xF00-0xF7F +0xF80-0xFBF +0xFC0-0xFFF +""" + + +# Generator files below. They get the appropriate starting line from the file openers and generate the instructions. + +def generator(): + """ + It splits the 'reg_str' value line by line (also removes empty lines), then converts to base 16 and creates a range from the two numbers. + It loops through this range and writes the numbers (in hex print format) into the assembly file. + After looping through the list it writes some standard lines. + """ + num_lines = 0 # printed later to help debugging, and assertion checks in C. + string_split = (reg_str.split("\n")) + string_split = string_split[1:-1] # removes empty lines before and after the string_split command + f.seek(pointer) # set write HEAD + for register in string_split: + ranges = register.split("-") + rstart = int(ranges[0], 16) # int(x, 16) converts to hex repr. + rend = int(ranges[1], 16) + for i in range(rstart, rend+1): + num_lines += 4 + h = hex(i) + f.write("csrrs t0, " + h + ", x0 " + "\n") + f.write("csrrw x0, " + h + ", t0 " + "\n") + f.write("csrrs x0, " + h + ", t0 " + "\n") + f.write("csrrc x0, " + h + ", t0 " + "\n") + f.write("j end_handler_ret\n") + f.write("\n") + f.write("//end of generated code") + return num_lines + +def header_generator(): + """ + Works the same as the generator function but on a smaller scale. Looks for the 'header_string' and then rewrites the lines below with the update 'num_lines' value + """ + f.seek(pointer) + f.write("// Number of illegaly generated lines as reported by the 'csr_privilege_gen.py'\n") + f.write("#define ILLEGALLY_GENERATED_INSN " + str(num_lines) + "\n") + f.write("\n") + f.write("#endif") + + +# File openers. They run through the file line by line and looks for the start string. They then update the global pointer value for the write HEAD + +with open(filename, "r+") as f: + while f.readline().strip("\n") != input_string: # place header after input_string + pass + pointer = f.tell() # Save pointer location to set proper HEAD position in generator() + num_lines = generator() + f.truncate() # removes all lines after the last generated line + +with open(headername, "r+") as f: + while f.readline().strip("\n") != header_string: # place HEAD after input_string + pass + pointer = f.tell() + header_generator() + f.truncate() # removes all lines after the last generated line + + +# Print user info to terminal + +print(num_lines, "lines written to file '" + filename + "'") +print("Also changed 'ILLEGALLY_GENERATED_INSN' value to " + str(num_lines) + " in the '" + headername + "' file") + diff --git a/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen_test.c b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen_test.c new file mode 100644 index 0000000000..71d68f6d29 --- /dev/null +++ b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen_test.c @@ -0,0 +1,56 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Contains generated tests on U-mode csr instructions to insert illegall access +** +******************************************************************************* +*/ + +#include +#include +#include "corev_uvmt.h" +#include +#include "csr_priv_gen_test.h" +// extern and global variable declaration +extern volatile void setup_pmp(); +// assembly function which runs and counts all the illegal instructions and exceptions (respectively) +extern volatile uint32_t csr_loop(); +volatile uint32_t exception_trap_increment_counter; + +// Assert function +static __inline__ void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { + if (actual != expect) { + printf(msg); + printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); + exit(EXIT_FAILURE); + } +} + +/* +Tests U-mode access to various custom functions which will not be implemented on the cv32e40s. Should all trap. +*/ +int main(void) { + setup_pmp(); // set the pmp regions for U-mode. + + + exception_trap_increment_counter = csr_loop(); + + // Looks for 0 return value, which means no trapped executions or number of traps exceeded number of illegal excecutions + if (exception_trap_increment_counter == 0){ + printf("trap count exceeded number of generated instructions or instructions were not generated!\n"); + exit(EXIT_FAILURE); + } + + // The assert number stems from the 'csr_privilege_gen.py' script. The number is printed in the terminal once writing is complete. + assert_or_die(exception_trap_increment_counter, ILLEGALLY_GENERATED_INSN, "error: not all illegal csr instructions triggered the trap handler\n"); +} + diff --git a/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen_test.h b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen_test.h new file mode 100644 index 0000000000..15624885ab --- /dev/null +++ b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_gen_test.h @@ -0,0 +1,24 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Header file which contains the generated 'ILLEGALLY_GENERATED_INSN' used by the .S and .C files to assert test success +** +******************************************************************************* +*/ +#ifndef csr_priv_gen_test_h +#define csr_priv_gen_test_h + +//start of the function header +// Number of illegaly generated lines as reported by the 'csr_privilege_gen.py' +#define ILLEGALLY_GENERATED_INSN 12288 + +#endif \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_loop.S b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_loop.S new file mode 100644 index 0000000000..65de6f6fca --- /dev/null +++ b/cv32e40s/tests/programs/custom/csr_priv_gen_test/csr_priv_loop.S @@ -0,0 +1,12384 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly file which holds generated instructions of the 'csr_privilege_test' held in the 'illegal_access_loop_tests.c' file. +** +******************************************************************************* +*/ + +.global csr_custom +.global csr_instr +.global csr_loop +.global u_sw_irq_handler +// Immediate for the trap handler to check to make sure its not looping in infinitely +#include "csr_priv_gen_test.h" + +csr_loop: + addi sp,sp,-52 + sw ra, 0(sp) + sw s0, 4(sp) + sw s1, 8(sp) + sw s2, 12(sp) + sw s3, 16(sp) + sw s4, 20(sp) + sw s5, 24(sp) + sw s6, 28(sp) + sw s7, 32(sp) + sw s8, 36(sp) + sw s9, 40(sp) + sw s10, 44(sp) + sw s11, 48(sp) + li s2, 0 + li s3, ILLEGALLY_GENERATED_INSN // load reference value to sanity-check max exceptions + j csr_custom + +exception_max_traps: // if trap count exceeds 'ILLEGALLY_GENERATED_INSN' break and return 0 instead + li s2, 0 + j end_handler_ret + + +end_handler_ret: + addi a0, s2, 0 // load the increment to return value + lw ra, 0(sp) + lw s0, 4(sp) + lw s1, 8(sp) + lw s2, 12(sp) + lw s3, 16(sp) + lw s4, 20(sp) + lw s5, 24(sp) + lw s6, 28(sp) + lw s7, 32(sp) + lw s8, 36(sp) + lw s9, 40(sp) + lw s10, 44(sp) + lw s11, 48(sp) + addi sp,sp, 52 + ret + +u_sw_irq_handler: + + addi s2, s2, 1 // increment the saved register for every trap + bgt s2, s3, exception_max_traps // check if trap counter has exceeded number of illegal instructions + //csrrwi t0, mepc, x0 + addi s4, s4, 4 // using s4 saves us one csrsw cmd. per loop. + csrrw x0, mepc, s4 // increment to the next execution in the mepc + mret + + + +csr_custom: // puts the core in usermode and starts the test + + // Zero "mstatus" to set MPP=umode + li t0, 0x1800 + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + la t0, csr_instr // load the csr_instr symbol to the mepc + la s4, csr_instr // load csr_instr to the s4 register for optimization in the trap + csrrw x0, mepc, t0 + + mret // call the mret to execute mode change. + + + +csr_instr: // csr privilege loop test + +// Start of generated code. +csrrs t0, 0x100, x0 +csrrw x0, 0x100, t0 +csrrs x0, 0x100, t0 +csrrc x0, 0x100, t0 +csrrs t0, 0x101, x0 +csrrw x0, 0x101, t0 +csrrs x0, 0x101, t0 +csrrc x0, 0x101, t0 +csrrs t0, 0x102, x0 +csrrw x0, 0x102, t0 +csrrs x0, 0x102, t0 +csrrc x0, 0x102, t0 +csrrs t0, 0x103, x0 +csrrw x0, 0x103, t0 +csrrs x0, 0x103, t0 +csrrc x0, 0x103, t0 +csrrs t0, 0x104, x0 +csrrw x0, 0x104, t0 +csrrs x0, 0x104, t0 +csrrc x0, 0x104, t0 +csrrs t0, 0x105, x0 +csrrw x0, 0x105, t0 +csrrs x0, 0x105, t0 +csrrc x0, 0x105, t0 +csrrs t0, 0x106, x0 +csrrw x0, 0x106, t0 +csrrs x0, 0x106, t0 +csrrc x0, 0x106, t0 +csrrs t0, 0x107, x0 +csrrw x0, 0x107, t0 +csrrs x0, 0x107, t0 +csrrc x0, 0x107, t0 +csrrs t0, 0x108, x0 +csrrw x0, 0x108, t0 +csrrs x0, 0x108, t0 +csrrc x0, 0x108, t0 +csrrs t0, 0x109, x0 +csrrw x0, 0x109, t0 +csrrs x0, 0x109, t0 +csrrc x0, 0x109, t0 +csrrs t0, 0x10a, x0 +csrrw x0, 0x10a, t0 +csrrs x0, 0x10a, t0 +csrrc x0, 0x10a, t0 +csrrs t0, 0x10b, x0 +csrrw x0, 0x10b, t0 +csrrs x0, 0x10b, t0 +csrrc x0, 0x10b, t0 +csrrs t0, 0x10c, x0 +csrrw x0, 0x10c, t0 +csrrs x0, 0x10c, t0 +csrrc x0, 0x10c, t0 +csrrs t0, 0x10d, x0 +csrrw x0, 0x10d, t0 +csrrs x0, 0x10d, t0 +csrrc x0, 0x10d, t0 +csrrs t0, 0x10e, x0 +csrrw x0, 0x10e, t0 +csrrs x0, 0x10e, t0 +csrrc x0, 0x10e, t0 +csrrs t0, 0x10f, x0 +csrrw x0, 0x10f, t0 +csrrs x0, 0x10f, t0 +csrrc x0, 0x10f, t0 +csrrs t0, 0x110, x0 +csrrw x0, 0x110, t0 +csrrs x0, 0x110, t0 +csrrc x0, 0x110, t0 +csrrs t0, 0x111, x0 +csrrw x0, 0x111, t0 +csrrs x0, 0x111, t0 +csrrc x0, 0x111, t0 +csrrs t0, 0x112, x0 +csrrw x0, 0x112, t0 +csrrs x0, 0x112, t0 +csrrc x0, 0x112, t0 +csrrs t0, 0x113, x0 +csrrw x0, 0x113, t0 +csrrs x0, 0x113, t0 +csrrc x0, 0x113, t0 +csrrs t0, 0x114, x0 +csrrw x0, 0x114, t0 +csrrs x0, 0x114, t0 +csrrc x0, 0x114, t0 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+csrrc x0, 0xfad, t0 +csrrs t0, 0xfae, x0 +csrrw x0, 0xfae, t0 +csrrs x0, 0xfae, t0 +csrrc x0, 0xfae, t0 +csrrs t0, 0xfaf, x0 +csrrw x0, 0xfaf, t0 +csrrs x0, 0xfaf, t0 +csrrc x0, 0xfaf, t0 +csrrs t0, 0xfb0, x0 +csrrw x0, 0xfb0, t0 +csrrs x0, 0xfb0, t0 +csrrc x0, 0xfb0, t0 +csrrs t0, 0xfb1, x0 +csrrw x0, 0xfb1, t0 +csrrs x0, 0xfb1, t0 +csrrc x0, 0xfb1, t0 +csrrs t0, 0xfb2, x0 +csrrw x0, 0xfb2, t0 +csrrs x0, 0xfb2, t0 +csrrc x0, 0xfb2, t0 +csrrs t0, 0xfb3, x0 +csrrw x0, 0xfb3, t0 +csrrs x0, 0xfb3, t0 +csrrc x0, 0xfb3, t0 +csrrs t0, 0xfb4, x0 +csrrw x0, 0xfb4, t0 +csrrs x0, 0xfb4, t0 +csrrc x0, 0xfb4, t0 +csrrs t0, 0xfb5, x0 +csrrw x0, 0xfb5, t0 +csrrs x0, 0xfb5, t0 +csrrc x0, 0xfb5, t0 +csrrs t0, 0xfb6, x0 +csrrw x0, 0xfb6, t0 +csrrs x0, 0xfb6, t0 +csrrc x0, 0xfb6, t0 +csrrs t0, 0xfb7, x0 +csrrw x0, 0xfb7, t0 +csrrs x0, 0xfb7, t0 +csrrc x0, 0xfb7, t0 +csrrs t0, 0xfb8, x0 +csrrw x0, 0xfb8, t0 +csrrs x0, 0xfb8, t0 +csrrc x0, 0xfb8, t0 +csrrs t0, 0xfb9, x0 +csrrw x0, 0xfb9, t0 +csrrs x0, 0xfb9, t0 +csrrc x0, 0xfb9, t0 +csrrs t0, 0xfba, x0 +csrrw x0, 0xfba, t0 +csrrs x0, 0xfba, t0 +csrrc x0, 0xfba, t0 +csrrs t0, 0xfbb, x0 +csrrw x0, 0xfbb, t0 +csrrs x0, 0xfbb, t0 +csrrc x0, 0xfbb, t0 +csrrs t0, 0xfbc, x0 +csrrw x0, 0xfbc, t0 +csrrs x0, 0xfbc, t0 +csrrc x0, 0xfbc, t0 +csrrs t0, 0xfbd, x0 +csrrw x0, 0xfbd, t0 +csrrs x0, 0xfbd, t0 +csrrc x0, 0xfbd, t0 +csrrs t0, 0xfbe, x0 +csrrw x0, 0xfbe, t0 +csrrs x0, 0xfbe, t0 +csrrc x0, 0xfbe, t0 +csrrs t0, 0xfbf, x0 +csrrw x0, 0xfbf, t0 +csrrs x0, 0xfbf, t0 +csrrc x0, 0xfbf, t0 +csrrs t0, 0xfc0, x0 +csrrw x0, 0xfc0, t0 +csrrs x0, 0xfc0, t0 +csrrc x0, 0xfc0, t0 +csrrs t0, 0xfc1, x0 +csrrw x0, 0xfc1, t0 +csrrs x0, 0xfc1, t0 +csrrc x0, 0xfc1, t0 +csrrs t0, 0xfc2, x0 +csrrw x0, 0xfc2, t0 +csrrs x0, 0xfc2, t0 +csrrc x0, 0xfc2, t0 +csrrs t0, 0xfc3, x0 +csrrw x0, 0xfc3, t0 +csrrs x0, 0xfc3, t0 +csrrc x0, 0xfc3, t0 +csrrs t0, 0xfc4, x0 +csrrw x0, 0xfc4, t0 +csrrs x0, 0xfc4, t0 +csrrc x0, 0xfc4, t0 +csrrs t0, 0xfc5, x0 +csrrw x0, 0xfc5, t0 +csrrs x0, 0xfc5, t0 +csrrc x0, 0xfc5, t0 +csrrs t0, 0xfc6, x0 +csrrw x0, 0xfc6, t0 +csrrs x0, 0xfc6, t0 +csrrc x0, 0xfc6, t0 +csrrs t0, 0xfc7, x0 +csrrw x0, 0xfc7, t0 +csrrs x0, 0xfc7, t0 +csrrc x0, 0xfc7, t0 +csrrs t0, 0xfc8, x0 +csrrw x0, 0xfc8, t0 +csrrs x0, 0xfc8, t0 +csrrc x0, 0xfc8, t0 +csrrs t0, 0xfc9, x0 +csrrw x0, 0xfc9, t0 +csrrs x0, 0xfc9, t0 +csrrc x0, 0xfc9, t0 +csrrs t0, 0xfca, x0 +csrrw x0, 0xfca, t0 +csrrs x0, 0xfca, t0 +csrrc x0, 0xfca, t0 +csrrs t0, 0xfcb, x0 +csrrw x0, 0xfcb, t0 +csrrs x0, 0xfcb, t0 +csrrc x0, 0xfcb, t0 +csrrs t0, 0xfcc, x0 +csrrw x0, 0xfcc, t0 +csrrs x0, 0xfcc, t0 +csrrc x0, 0xfcc, t0 +csrrs t0, 0xfcd, x0 +csrrw x0, 0xfcd, t0 +csrrs x0, 0xfcd, t0 +csrrc x0, 0xfcd, t0 +csrrs t0, 0xfce, x0 +csrrw x0, 0xfce, t0 +csrrs x0, 0xfce, t0 +csrrc x0, 0xfce, t0 +csrrs t0, 0xfcf, x0 +csrrw x0, 0xfcf, t0 +csrrs x0, 0xfcf, t0 +csrrc x0, 0xfcf, t0 +csrrs t0, 0xfd0, x0 +csrrw x0, 0xfd0, t0 +csrrs x0, 0xfd0, t0 +csrrc x0, 0xfd0, t0 +csrrs t0, 0xfd1, x0 +csrrw x0, 0xfd1, t0 +csrrs x0, 0xfd1, t0 +csrrc x0, 0xfd1, t0 +csrrs t0, 0xfd2, x0 +csrrw x0, 0xfd2, t0 +csrrs x0, 0xfd2, t0 +csrrc x0, 0xfd2, t0 +csrrs t0, 0xfd3, x0 +csrrw x0, 0xfd3, t0 +csrrs x0, 0xfd3, t0 +csrrc x0, 0xfd3, t0 +csrrs t0, 0xfd4, x0 +csrrw x0, 0xfd4, t0 +csrrs x0, 0xfd4, t0 +csrrc x0, 0xfd4, t0 +csrrs t0, 0xfd5, x0 +csrrw x0, 0xfd5, t0 +csrrs x0, 0xfd5, t0 +csrrc x0, 0xfd5, t0 +csrrs t0, 0xfd6, x0 +csrrw x0, 0xfd6, t0 +csrrs x0, 0xfd6, t0 +csrrc x0, 0xfd6, t0 +csrrs t0, 0xfd7, x0 +csrrw x0, 0xfd7, t0 +csrrs x0, 0xfd7, t0 +csrrc x0, 0xfd7, t0 +csrrs t0, 0xfd8, x0 +csrrw x0, 0xfd8, t0 +csrrs x0, 0xfd8, t0 +csrrc x0, 0xfd8, t0 +csrrs t0, 0xfd9, x0 +csrrw x0, 0xfd9, t0 +csrrs x0, 0xfd9, t0 +csrrc x0, 0xfd9, t0 +csrrs t0, 0xfda, x0 +csrrw x0, 0xfda, t0 +csrrs x0, 0xfda, t0 +csrrc x0, 0xfda, t0 +csrrs t0, 0xfdb, x0 +csrrw x0, 0xfdb, t0 +csrrs x0, 0xfdb, t0 +csrrc x0, 0xfdb, t0 +csrrs t0, 0xfdc, x0 +csrrw x0, 0xfdc, t0 +csrrs x0, 0xfdc, t0 +csrrc x0, 0xfdc, t0 +csrrs t0, 0xfdd, x0 +csrrw x0, 0xfdd, t0 +csrrs x0, 0xfdd, t0 +csrrc x0, 0xfdd, t0 +csrrs t0, 0xfde, x0 +csrrw x0, 0xfde, t0 +csrrs x0, 0xfde, t0 +csrrc x0, 0xfde, t0 +csrrs t0, 0xfdf, x0 +csrrw x0, 0xfdf, t0 +csrrs x0, 0xfdf, t0 +csrrc x0, 0xfdf, t0 +csrrs t0, 0xfe0, x0 +csrrw x0, 0xfe0, t0 +csrrs x0, 0xfe0, t0 +csrrc x0, 0xfe0, t0 +csrrs t0, 0xfe1, x0 +csrrw x0, 0xfe1, t0 +csrrs x0, 0xfe1, t0 +csrrc x0, 0xfe1, t0 +csrrs t0, 0xfe2, x0 +csrrw x0, 0xfe2, t0 +csrrs x0, 0xfe2, t0 +csrrc x0, 0xfe2, t0 +csrrs t0, 0xfe3, x0 +csrrw x0, 0xfe3, t0 +csrrs x0, 0xfe3, t0 +csrrc x0, 0xfe3, t0 +csrrs t0, 0xfe4, x0 +csrrw x0, 0xfe4, t0 +csrrs x0, 0xfe4, t0 +csrrc x0, 0xfe4, t0 +csrrs t0, 0xfe5, x0 +csrrw x0, 0xfe5, t0 +csrrs x0, 0xfe5, t0 +csrrc x0, 0xfe5, t0 +csrrs t0, 0xfe6, x0 +csrrw x0, 0xfe6, t0 +csrrs x0, 0xfe6, t0 +csrrc x0, 0xfe6, t0 +csrrs t0, 0xfe7, x0 +csrrw x0, 0xfe7, t0 +csrrs x0, 0xfe7, t0 +csrrc x0, 0xfe7, t0 +csrrs t0, 0xfe8, x0 +csrrw x0, 0xfe8, t0 +csrrs x0, 0xfe8, t0 +csrrc x0, 0xfe8, t0 +csrrs t0, 0xfe9, x0 +csrrw x0, 0xfe9, t0 +csrrs x0, 0xfe9, t0 +csrrc x0, 0xfe9, t0 +csrrs t0, 0xfea, x0 +csrrw x0, 0xfea, t0 +csrrs x0, 0xfea, t0 +csrrc x0, 0xfea, t0 +csrrs t0, 0xfeb, x0 +csrrw x0, 0xfeb, t0 +csrrs x0, 0xfeb, t0 +csrrc x0, 0xfeb, t0 +csrrs t0, 0xfec, x0 +csrrw x0, 0xfec, t0 +csrrs x0, 0xfec, t0 +csrrc x0, 0xfec, t0 +csrrs t0, 0xfed, x0 +csrrw x0, 0xfed, t0 +csrrs x0, 0xfed, t0 +csrrc x0, 0xfed, t0 +csrrs t0, 0xfee, x0 +csrrw x0, 0xfee, t0 +csrrs x0, 0xfee, t0 +csrrc x0, 0xfee, t0 +csrrs t0, 0xfef, x0 +csrrw x0, 0xfef, t0 +csrrs x0, 0xfef, t0 +csrrc x0, 0xfef, t0 +csrrs t0, 0xff0, x0 +csrrw x0, 0xff0, t0 +csrrs x0, 0xff0, t0 +csrrc x0, 0xff0, t0 +csrrs t0, 0xff1, x0 +csrrw x0, 0xff1, t0 +csrrs x0, 0xff1, t0 +csrrc x0, 0xff1, t0 +csrrs t0, 0xff2, x0 +csrrw x0, 0xff2, t0 +csrrs x0, 0xff2, t0 +csrrc x0, 0xff2, t0 +csrrs t0, 0xff3, x0 +csrrw x0, 0xff3, t0 +csrrs x0, 0xff3, t0 +csrrc x0, 0xff3, t0 +csrrs t0, 0xff4, x0 +csrrw x0, 0xff4, t0 +csrrs x0, 0xff4, t0 +csrrc x0, 0xff4, t0 +csrrs t0, 0xff5, x0 +csrrw x0, 0xff5, t0 +csrrs x0, 0xff5, t0 +csrrc x0, 0xff5, t0 +csrrs t0, 0xff6, x0 +csrrw x0, 0xff6, t0 +csrrs x0, 0xff6, t0 +csrrc x0, 0xff6, t0 +csrrs t0, 0xff7, x0 +csrrw x0, 0xff7, t0 +csrrs x0, 0xff7, t0 +csrrc x0, 0xff7, t0 +csrrs t0, 0xff8, x0 +csrrw x0, 0xff8, t0 +csrrs x0, 0xff8, t0 +csrrc x0, 0xff8, t0 +csrrs t0, 0xff9, x0 +csrrw x0, 0xff9, t0 +csrrs x0, 0xff9, t0 +csrrc x0, 0xff9, t0 +csrrs t0, 0xffa, x0 +csrrw x0, 0xffa, t0 +csrrs x0, 0xffa, t0 +csrrc x0, 0xffa, t0 +csrrs t0, 0xffb, x0 +csrrw x0, 0xffb, t0 +csrrs x0, 0xffb, t0 +csrrc x0, 0xffb, t0 +csrrs t0, 0xffc, x0 +csrrw x0, 0xffc, t0 +csrrs x0, 0xffc, t0 +csrrc x0, 0xffc, t0 +csrrs t0, 0xffd, x0 +csrrw x0, 0xffd, t0 +csrrs x0, 0xffd, t0 +csrrc x0, 0xffd, t0 +csrrs t0, 0xffe, x0 +csrrw x0, 0xffe, t0 +csrrs x0, 0xffe, t0 +csrrc x0, 0xffe, t0 +csrrs t0, 0xfff, x0 +csrrw x0, 0xfff, t0 +csrrs x0, 0xfff, t0 +csrrc x0, 0xfff, t0 +j end_handler_ret + +//end of generated code \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/csr_priv_gen_test/helpers.S b/cv32e40s/tests/programs/custom/csr_priv_gen_test/helpers.S new file mode 100644 index 0000000000..14a64b26f4 --- /dev/null +++ b/cv32e40s/tests/programs/custom/csr_priv_gen_test/helpers.S @@ -0,0 +1,38 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly file which holds helper functions used in 'illegal_access_loop_tests.c' to declare pmp_regions or switch privilege_modes. +** +******************************************************************************* +*/ + +.section .text + +.global setup_pmp +.global set_u_mode + +setup_pmp: + // Set pmp addr to 0xFFFF_FFFF + li t0, 0xFFFFFFFF + csrrw x0, pmpaddr0, t0 + + // Set pmp region TOR and read/write/execute + li t0, ((1 << 3) + (7 << 0)) + csrrw x0, pmpcfg0, t0 + + ret + +set_u_mode: // puts the core in usermode. + li t0, 0x1800 // load as bitmask + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrw x0, mepc, ra + mret \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/csr_priv_gen_test/test.yaml b/cv32e40s/tests/programs/custom/csr_priv_gen_test/test.yaml new file mode 100644 index 0000000000..89991682e3 --- /dev/null +++ b/cv32e40s/tests/programs/custom/csr_priv_gen_test/test.yaml @@ -0,0 +1,4 @@ +name: csr_priv_gen_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + generated csr instructions to check that the cv32e40s cores handles illegal access. \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/custom_priv_gen_test/README.md b/cv32e40s/tests/programs/custom/custom_priv_gen_test/README.md new file mode 100644 index 0000000000..2b0cdea9f2 --- /dev/null +++ b/cv32e40s/tests/programs/custom/custom_priv_gen_test/README.md @@ -0,0 +1,26 @@ +Generated tests on custom U-mode instructions + +Needs `CFG=pmp` for allowing U-mode to run. + + +# Python generator files + +## Motivation +Runing through the test-plan it became apparant at some point that it would be necessary to have tests which contained a number of instructions to satisfy testing goals. The solution became python scripts which use string manipulation to generate these instructions directly to the relevant .h and .S files in the directory. + +## Function +The script works by looping through the given file (see the top of the file .py file for name declarations) line by line until a 'trigger' string is reached, usually this string can look something like this: + +``` +// start of generated code +``` + +And everything below this line is then overwritten. + +The script will either have a list called 'reg_string' which is a manually constructed list fetched from a table in the RISC specification. The file will then parse this registry list and create ranges to include all registries within the list. It then writes instructions for that registry to file. Which instructions are based on the test plan. + +Afterwards it searches through the header file and changes the 'ILLEGALLY_GENERATED_INSN' define, which is what both the .S and .c files use when sanity checking or asserting that the number of trapped instructions matches what's been generated. There is also some info printed to the terminal about how many lines and which files are written to. + + +## Maintenance +The scripts are intended to be easily maintenable (although I guess time will tell), and therefore the generation of the instructions themselves are kept within 'generator()' functions and marked variables. If there's a need to change the number of registries, the types of instructions etc. these are found there. Afterwards you should be able to run the script and it will properly update the instructions for you. diff --git a/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen.py b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen.py new file mode 100644 index 0000000000..1972bf230d --- /dev/null +++ b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen.py @@ -0,0 +1,96 @@ +""" +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Script which generates the usermode custom instructions, to check illegal access. Instructions are written directly to the 'illegal_custom_loop.S' file after the 'input_string' declared below. +** +******************************************************************************* +""" + + +# Filenames +headername = "custom_priv_gen_test.h" # name of the header file +filename = "custom_priv_gen_test.S" # file which will be written to + + +# Trigger strings +input_string = "// This is the start of the generated code" # start string to move write HEAD. +header_string = "//start of the function header" # start string script looks for + + +# Global variables +# ref Figure 3.30: SYSTEM instruction encodings designated for custom use (PRIVSPEC V20211203) +func6 = {35, 51} # 'funct6' bit-field codes: 100011, 110011 +outer_loop = 2048 # 'custom11' bit-field range (2^11) +inner_loop = 32 # 'custom5' bit-field range (2^5) +opcode = 115 # SYSTEM OPCODE 1110011 +pointer = 0 # file pointer +num_lines = 0 # numebr of lines written to file + + + +# Generator files below. They get the appropriate starting line from the file openers and generate the instructions. +def generator(): + """ + This generator function uses the 'funct6' 'outer_loop' and 'inner_loop' values to generate all possible custom instructions in three nested loops. + It converts a value in each loop and then in the inner loop combines them in a logical OR function before writing it as a custom word to file. + At the end it writes some standard lines to file and returns number of lines written to later update the test value in the head file. + """ + num_lines = 0 + f.seek(pointer) + for func in func6: + funcs = func << 26 # bitshift according to position + for i in range(outer_loop): + bini = i << 15 + for j in range(inner_loop): + binj = j << 7 + h = (funcs | bini | binj | opcode) + num_lines += 1 # inform about num. instructions for easier debugging. + f.write(".word(" + hex(h) + ")" + "\n") + + # These lines are manually added at the end + f.write("j end_handler_ret\n") + f.write("\n") + f.write("//end of generated code") + return num_lines + +def header_gen(): + """ + Works the same as the generator function but on a smaller scale. Looks for the 'header_string' and then rewrites the lines below with the update 'num_lines' value + """ + f.seek(pointer) + f.write("// Number of illegaly generated lines as reported by the 'illegal_mcounteren_loop_gen.py'\n") + f.write("#define ILLEGALLY_GENERATED_INSN " + str(num_lines) + "\n") + f.write("\n") + f.write("#endif") + + +# File openers. They run through the file line by line and looks for the start string. They then update the global pointer value for the write HEAD + +with open(filename, "r+") as f: + while f.readline().strip("\n") != input_string: + pass + pointer = f.tell() # set file header at line after input_string + num_lines = generator() # generate code + f.truncate() # remove all lines after the generated ones. + + +with open(headername, "r+") as f: + while f.readline().strip("\n") != header_string: # place HEAD after input_string + pass + pointer = f.tell() + header_gen() + f.truncate() # removes all lines after the last generated line + + +#Print user info to temrinal +print(num_lines, "lines written to file '" + filename + "'") # user info +print("Also changed 'ILLEGALLY_GENERATED_INSN' value to " + str(num_lines) + " in the '" + headername + "' file") # user info \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.S b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.S new file mode 100644 index 0000000000..b0dd25f51b --- /dev/null +++ b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.S @@ -0,0 +1,131171 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Contains the generated illegal custom tests. +** +******************************************************************************* +*/ +#include "corev_uvmt.h" + + +.global illegal_custom +.global ill_instr +.global illegal_full +.global u_sw_irq_handler +.global put_m_mode +// Immediate for the trap handler to check to make sure its not looping in infinitely +#include "custom_priv_gen_test.h" + +illegal_full: + addi sp,sp,-52 + sw ra, 0(sp) + sw s0, 4(sp) + sw s1, 8(sp) + sw s2, 12(sp) + sw s3, 16(sp) + sw s4, 20(sp) + sw s5, 24(sp) + sw s6, 28(sp) + sw s7, 32(sp) + sw s8, 36(sp) + sw s9, 40(sp) + sw s10, 44(sp) + sw s11, 48(sp) + li s2, 0 + li s3, ILLEGALLY_GENERATED_INSN // load reference value to sanity-check max exceptions + j illegal_custom + +exception_max_traps: // if trap count exceeds 'ILLEGALLY_GENERATED_INSN' break and return 0 instead + li s2, 0 + j end_handler_ret + +u_sw_irq_handler: + + addi s2, s2, 1 // increments every trap + bgt s2, s3, exception_max_traps // check if trap counter has exceeded number of illegal instructions + //csrrw t0, mepc, x0 + addi s4, s4, 4 // increment s4 which holds the pc value (saves a cssrw per loop) + csrrw x0, mepc, s4 // increment to the next instruction + mret + + +end_handler_ret: + addi a0, s2, 0 // load function return value + lw ra, 0(sp) + lw s0, 4(sp) + lw s1, 8(sp) + lw s2, 12(sp) + lw s3, 16(sp) + lw s4, 20(sp) + lw s5, 24(sp) + lw s6, 28(sp) + lw s7, 32(sp) + lw s8, 36(sp) + lw s9, 40(sp) + lw s10, 44(sp) + lw s11, 48(sp) + addi sp,sp,52 + ret + + + + +illegal_custom: // puts the core in usermode. + + // Zero "mstatus" to set MPP=umode + li t0, 0x1800 + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + la t0, ill_instr //this will point to the label below. + la s4, ill_instr // load ill_instr to the s4 register for optimization in the trap + csrrw x0, mepc, t0 + + mret // call the mret to execute mode change. + + +ill_instr: // csr privilege loop test + +// This is the start of the generated code +.word(0xcc000073) +.word(0xcc0000f3) +.word(0xcc000173) +.word(0xcc0001f3) +.word(0xcc000273) +.word(0xcc0002f3) +.word(0xcc000373) +.word(0xcc0003f3) +.word(0xcc000473) +.word(0xcc0004f3) +.word(0xcc000573) +.word(0xcc0005f3) +.word(0xcc000673) +.word(0xcc0006f3) +.word(0xcc000773) +.word(0xcc0007f3) +.word(0xcc000873) +.word(0xcc0008f3) +.word(0xcc000973) +.word(0xcc0009f3) +.word(0xcc000a73) +.word(0xcc000af3) +.word(0xcc000b73) +.word(0xcc000bf3) +.word(0xcc000c73) +.word(0xcc000cf3) +.word(0xcc000d73) +.word(0xcc000df3) +.word(0xcc000e73) +.word(0xcc000ef3) +.word(0xcc000f73) +.word(0xcc000ff3) +.word(0xcc008073) +.word(0xcc0080f3) +.word(0xcc008173) +.word(0xcc0081f3) +.word(0xcc008273) +.word(0xcc0082f3) +.word(0xcc008373) +.word(0xcc0083f3) +.word(0xcc008473) +.word(0xcc0084f3) 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+.word(0x8ffe8173) +.word(0x8ffe81f3) +.word(0x8ffe8273) +.word(0x8ffe82f3) +.word(0x8ffe8373) +.word(0x8ffe83f3) +.word(0x8ffe8473) +.word(0x8ffe84f3) +.word(0x8ffe8573) +.word(0x8ffe85f3) +.word(0x8ffe8673) +.word(0x8ffe86f3) +.word(0x8ffe8773) +.word(0x8ffe87f3) +.word(0x8ffe8873) +.word(0x8ffe88f3) +.word(0x8ffe8973) +.word(0x8ffe89f3) +.word(0x8ffe8a73) +.word(0x8ffe8af3) +.word(0x8ffe8b73) +.word(0x8ffe8bf3) +.word(0x8ffe8c73) +.word(0x8ffe8cf3) +.word(0x8ffe8d73) +.word(0x8ffe8df3) +.word(0x8ffe8e73) +.word(0x8ffe8ef3) +.word(0x8ffe8f73) +.word(0x8ffe8ff3) +.word(0x8fff0073) +.word(0x8fff00f3) +.word(0x8fff0173) +.word(0x8fff01f3) +.word(0x8fff0273) +.word(0x8fff02f3) +.word(0x8fff0373) +.word(0x8fff03f3) +.word(0x8fff0473) +.word(0x8fff04f3) +.word(0x8fff0573) +.word(0x8fff05f3) +.word(0x8fff0673) +.word(0x8fff06f3) +.word(0x8fff0773) +.word(0x8fff07f3) +.word(0x8fff0873) +.word(0x8fff08f3) +.word(0x8fff0973) +.word(0x8fff09f3) +.word(0x8fff0a73) +.word(0x8fff0af3) +.word(0x8fff0b73) +.word(0x8fff0bf3) +.word(0x8fff0c73) +.word(0x8fff0cf3) +.word(0x8fff0d73) +.word(0x8fff0df3) +.word(0x8fff0e73) +.word(0x8fff0ef3) +.word(0x8fff0f73) +.word(0x8fff0ff3) +.word(0x8fff8073) +.word(0x8fff80f3) +.word(0x8fff8173) +.word(0x8fff81f3) +.word(0x8fff8273) +.word(0x8fff82f3) +.word(0x8fff8373) +.word(0x8fff83f3) +.word(0x8fff8473) +.word(0x8fff84f3) +.word(0x8fff8573) +.word(0x8fff85f3) +.word(0x8fff8673) +.word(0x8fff86f3) +.word(0x8fff8773) +.word(0x8fff87f3) +.word(0x8fff8873) +.word(0x8fff88f3) +.word(0x8fff8973) +.word(0x8fff89f3) +.word(0x8fff8a73) +.word(0x8fff8af3) +.word(0x8fff8b73) +.word(0x8fff8bf3) +.word(0x8fff8c73) +.word(0x8fff8cf3) +.word(0x8fff8d73) +.word(0x8fff8df3) +.word(0x8fff8e73) +.word(0x8fff8ef3) +.word(0x8fff8f73) +.word(0x8fff8ff3) +j end_handler_ret + +//end of generated code \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.c b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.c new file mode 100644 index 0000000000..d7fd5ae633 --- /dev/null +++ b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.c @@ -0,0 +1,56 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Contains generated tests on custom U-mode instructions +** +******************************************************************************* +*/ + +#include +#include +#include "corev_uvmt.h" +#include +#include "custom_priv_gen_test.h" + +// extern and global variable declaration +extern volatile void setup_pmp(); +// assembly function which runs and counts all the illegal instructions and exceptions (respectively) +extern volatile uint32_t illegal_full(); +//extern volatile uint8_t gbl_mysignaltothehandler = 0; +volatile uint32_t exception_trap_increment_counter; + +// Assert function +static __inline__ void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { + if (actual != expect) { + printf(msg); + printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); + exit(EXIT_FAILURE); + } +} + +/* +Tests U-mode access to various custom functions which are not yet implemented. Should all trap. +*/ +int main(void) { + setup_pmp(); // set the pmp regions for U-mode. + + exception_trap_increment_counter = illegal_full(); + + // Looks for 0 return value, which means no trapped executions or number of traps exceeded number of illegal excecutions + if (exception_trap_increment_counter == 0){ + printf("trap count exceeded number of generated instructions or instructions were not generated!\n"); + exit(EXIT_FAILURE); + } + + // The assert number stems from the 'illegal_custom_loop.py' script. The number is printed in the terminal once writing is complete. + assert_or_die(exception_trap_increment_counter, ILLEGALLY_GENERATED_INSN, "error: not all illegal custom instructions triggered the trap handler\n"); +} \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.h b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.h new file mode 100644 index 0000000000..ddaf8a1b33 --- /dev/null +++ b/cv32e40s/tests/programs/custom/custom_priv_gen_test/custom_priv_gen_test.h @@ -0,0 +1,26 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Header file which contains the generated 'ILLEGALLY_GENERATED_INSN' used by the .S and .C files to assert test success +** +******************************************************************************* +*/ + + +#ifndef custom_priv_gen_test_h +#define custom_priv_gen_test_h + +//start of the function header +// Number of illegaly generated lines as reported by the 'illegal_mcounteren_loop_gen.py' +#define ILLEGALLY_GENERATED_INSN 131072 + +#endif \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/custom_priv_gen_test/helpers.S b/cv32e40s/tests/programs/custom/custom_priv_gen_test/helpers.S new file mode 100644 index 0000000000..14a64b26f4 --- /dev/null +++ b/cv32e40s/tests/programs/custom/custom_priv_gen_test/helpers.S @@ -0,0 +1,38 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly file which holds helper functions used in 'illegal_access_loop_tests.c' to declare pmp_regions or switch privilege_modes. +** +******************************************************************************* +*/ + +.section .text + +.global setup_pmp +.global set_u_mode + +setup_pmp: + // Set pmp addr to 0xFFFF_FFFF + li t0, 0xFFFFFFFF + csrrw x0, pmpaddr0, t0 + + // Set pmp region TOR and read/write/execute + li t0, ((1 << 3) + (7 << 0)) + csrrw x0, pmpcfg0, t0 + + ret + +set_u_mode: // puts the core in usermode. + li t0, 0x1800 // load as bitmask + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrw x0, mepc, ra + mret \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/custom_priv_gen_test/test.yaml b/cv32e40s/tests/programs/custom/custom_priv_gen_test/test.yaml new file mode 100644 index 0000000000..043687e043 --- /dev/null +++ b/cv32e40s/tests/programs/custom/custom_priv_gen_test/test.yaml @@ -0,0 +1,4 @@ +name: custom_priv_gen_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Large set of generated instructions to check that the cv32e40s cores handles illegal custom instructions \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/README.md b/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/README.md new file mode 100644 index 0000000000..7a1f0f21e0 --- /dev/null +++ b/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/README.md @@ -0,0 +1,24 @@ +CSR access test for (a practical subset of) implemented CSRs (i.e. not for the _whole_ 4096 range). + +Generated from "riscv-dv"'s `scripts/gen_csr_test.py`, via core-v-verif's +`bin/gen_csr_access_test.py`, using the csr yaml definition in the core's repo. + +From top-level: +``` +python3 ./bin/gen_csr_access_test.py \ + --core=cv32e40s \ + --clint_enable \ + --i_base_enable \ + --m_ext_enable \ + --umode_enable \ + --zc_enable \ + --mhpmcounter_num 0 \ + --num_triggers 0 \ + --pmp_num_regions 0 \ + --output=./cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/ \ + --m4 +``` +The above options were the most applicable at the time of writing and are subject to change. +Note that excluded options and parameters need targeted separate testing. + +[comment]: # (TODO:silabs-robin Regen with "--xsecure_enable" etc after iss bugfix and rtl progression) diff --git a/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/cv32e40s_csr_access_test.S b/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/cv32e40s_csr_access_test.S index cceb9659f2..29d8a73ba0 100644 --- a/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/cv32e40s_csr_access_test.S +++ b/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/cv32e40s_csr_access_test.S @@ -1,13 +1,10 @@ - # CSR access test # Generated by gen_csr_test.py (part of riscv-dv) # Manual edits to fit with BSP and enhance debug -#include "corev_uvmt.h" -.include "user_define.h" + +#include "user_define.h" .section .text.start .globl _start -.section .text -#.include "user_init.s" .type _start, @function _start: @@ -17,1555 +14,7311 @@ _start: .section .text _start_main: - #define EXP_MISA 0x40101104 - ############################################################################### # # Generated code starts... # ############################################################################### _start0: - # mcycle - li x13, 0xa5a5a5a5 - csrrw x5, 2816, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 2816, x13 - li x13, 0xa5a5a5a5 - bne x13, x5, csr_fail - li x13, 0xe780d37a - csrrw x5, 2816, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 2816, x13 - li x13, 0xe780d37a - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 2816, x13 - li x13, 0xe7a5f7ff - bne x13, x5, csr_fail - li x13, 0xcace901c - csrrs x5, 2816, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 2816, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 2816, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xe89fc72d - csrrc x5, 2816, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2816, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2816, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 2816, 0b10011 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 2816, 0b00101 - li x13, 0x00000013 - bne x13, x5, csr_fail - csrrsi x5, 2816, 0b11010 - li x13, 0x00000017 - bne x13, x5, csr_fail - csrrsi x5, 2816, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2816, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2816, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 2816, 0b10110 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 2816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2816, x11 + li x11, 0xa5a5a5a5 + bne x11, x9, csr_fail + li x11, 0x1f4dad8a + csrrw x9, 2816, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2816, x11 + li x11, 0x1f4dad8a + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2816, x11 + li x11, 0xbfedadaf + bne x11, x9, csr_fail + li x11, 0x2b5323c9 + csrrs x9, 2816, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2816, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2816, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0x64970e08 + csrrc x9, 2816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2816, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2816, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrwi x9, 2816, 0b00111 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 2816, 0b00101 + li x11, 0x00000007 + bne x11, x9, csr_fail + csrrsi x9, 2816, 0b11010 + li x11, 0x00000007 + bne x11, x9, csr_fail + csrrsi x9, 2816, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2816, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2816, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrci x9, 2816, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail # mcycleh - li x13, 0xa5a5a5a5 - csrrw x5, 2944, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 2944, x13 - li x13, 0xa5a5a5a5 - bne x13, x5, csr_fail - li x13, 0x8ca9fba5 - csrrw x5, 2944, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 2944, x13 - li x13, 0x8ca9fba5 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 2944, x13 - li x13, 0xadadffa5 - bne x13, x5, csr_fail - li x13, 0xded54cd8 - csrrs x5, 2944, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 2944, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 2944, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0x9fb3c5f1 - csrrc x5, 2944, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2944, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2944, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 2944, 0b01110 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 2944, 0b00101 - li x13, 0x0000000e - bne x13, x5, csr_fail - csrrsi x5, 2944, 0b11010 - li x13, 0x0000000f - bne x13, x5, csr_fail - csrrsi x5, 2944, 0b01011 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2944, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2944, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 2944, 0b00110 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 2944, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2944, x11 + li x11, 0xa5a5a5a5 + bne x11, x9, csr_fail + li x11, 0xb675dac3 + csrrw x9, 2944, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2944, x11 + li x11, 0xb675dac3 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2944, x11 + li x11, 0xb7f5ffe7 + bne x11, x9, csr_fail + li x11, 0xfa22660a + csrrs x9, 2944, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2944, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2944, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0x952ab9e + csrrc x9, 2944, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2944, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2944, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrwi x9, 2944, 0b00101 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 2944, 0b00101 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrsi x9, 2944, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrsi x9, 2944, 0b01010 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2944, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2944, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrci x9, 2944, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail # minstret - li x13, 0xa5a5a5a5 - csrrw x5, 2818, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 2818, x13 - li x13, 0xa5a5a5a5 - bne x13, x5, csr_fail - li x13, 0x60eca247 - csrrw x5, 2818, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 2818, x13 - li x13, 0x60eca247 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 2818, x13 - li x13, 0xe5eda7e7 - bne x13, x5, csr_fail - li x13, 0x10a53822 - csrrs x5, 2818, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 2818, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 2818, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0x3ceee60b - csrrc x5, 2818, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2818, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2818, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 2818, 0b11011 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 2818, 0b00101 - li x13, 0x0000001b - bne x13, x5, csr_fail - csrrsi x5, 2818, 0b11010 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrsi x5, 2818, 0b11010 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2818, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2818, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 2818, 0b10111 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 2818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2818, x11 + li x11, 0xa5a5a5a5 + bne x11, x9, csr_fail + li x11, 0x6091126e + csrrw x9, 2818, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2818, x11 + li x11, 0x6091126e + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2818, x11 + li x11, 0xe5b5b7ef + bne x11, x9, csr_fail + li x11, 0x4227fb95 + csrrs x9, 2818, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2818, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2818, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0x492e47e8 + csrrc x9, 2818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2818, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2818, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrwi x9, 2818, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 2818, 0b00101 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 2818, 0b11010 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrsi x9, 2818, 0b00111 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2818, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2818, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrci x9, 2818, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail # minstreth - li x13, 0xa5a5a5a5 - csrrw x5, 2946, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 2946, x13 - li x13, 0xa5a5a5a5 - bne x13, x5, csr_fail - li x13, 0x1e94172a - csrrw x5, 2946, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 2946, x13 - li x13, 0x1e94172a - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 2946, x13 - li x13, 0xbfb5b7af - bne x13, x5, csr_fail - li x13, 0xed103d6e - csrrs x5, 2946, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 2946, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 2946, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xd42207c3 - csrrc x5, 2946, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2946, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2946, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 2946, 0b11000 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 2946, 0b00101 - li x13, 0x00000018 - bne x13, x5, csr_fail - csrrsi x5, 2946, 0b11010 - li x13, 0x0000001d - bne x13, x5, csr_fail - csrrsi x5, 2946, 0b11101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2946, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2946, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 2946, 0b10001 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 2946, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2946, x11 + li x11, 0xa5a5a5a5 + bne x11, x9, csr_fail + li x11, 0x13fa7ef8 + csrrw x9, 2946, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2946, x11 + li x11, 0x13fa7ef8 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2946, x11 + li x11, 0xb7fffffd + bne x11, x9, csr_fail + li x11, 0x3a581c0e + csrrs x9, 2946, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2946, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2946, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xbcd96188 + csrrc x9, 2946, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2946, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2946, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrwi x9, 2946, 0b00001 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 2946, 0b00101 + li x11, 0x00000001 + bne x11, x9, csr_fail + csrrsi x9, 2946, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrsi x9, 2946, 0b10101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2946, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 2946, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrci x9, 2946, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail # mhpmcounter3 - li x13, 0xa5a5a5a5 - csrrw x5, 2819, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 2819, x13 - li x13, 0xa5a5a5a5 - bne x13, x5, csr_fail - li x13, 0x29f6fdef - csrrw x5, 2819, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 2819, x13 - li x13, 0x29f6fdef - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 2819, x13 - li x13, 0xadf7fdef - bne x13, x5, csr_fail - li x13, 0x8e3f2402 - csrrs x5, 2819, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 2819, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 2819, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xf3201b16 - csrrc x5, 2819, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2819, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2819, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 2819, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 2819, 0b00101 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 2819, 0b11010 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrsi x5, 2819, 0b10100 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2819, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2819, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 2819, 0b11011 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x234c97de + csrrw x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xca6585d3 + csrrs x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2aa7e9d9 + csrrc x9, 2819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2819, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2819, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2819, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2819, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2819, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2819, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2819, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2819, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2819, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail # mhpmcounter3h - li x13, 0xa5a5a5a5 - csrrw x5, 2947, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 2947, x13 - li x13, 0xa5a5a5a5 - bne x13, x5, csr_fail - li x13, 0x16499451 - csrrw x5, 2947, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 2947, x13 - li x13, 0x16499451 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 2947, x13 - li x13, 0xb7edb5f5 - bne x13, x5, csr_fail - li x13, 0x654e7828 - csrrs x5, 2947, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 2947, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 2947, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xf747a7ec - csrrc x5, 2947, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2947, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 2947, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 2947, 0b11101 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 2947, 0b00101 - li x13, 0x0000001d - bne x13, x5, csr_fail - csrrsi x5, 2947, 0b11010 - li x13, 0x0000001d - bne x13, x5, csr_fail - csrrsi x5, 2947, 0b00001 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2947, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 2947, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 2947, 0b00000 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x086d6f42 + csrrw x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x502be416 + csrrs x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xfdd49d69 + csrrc x9, 2947, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2947, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2947, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2947, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2947, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2947, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2947, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2947, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2947, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2947, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter4 + li x11, 0xa5a5a5a5 + csrrw x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x697bdfa2 + csrrw x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x03c8fda8 + csrrs x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe8a4dbdb + csrrc x9, 2820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2820, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2820, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2820, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2820, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2820, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2820, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2820, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2820, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2820, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter4h + li x11, 0xa5a5a5a5 + csrrw x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x632d9a8b + csrrw x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1151d04a8 + csrrs x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6e8afad5 + csrrc x9, 2948, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2948, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2948, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2948, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2948, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2948, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2948, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2948, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2948, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2948, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter5 + li x11, 0xa5a5a5a5 + csrrw x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf11db183 + csrrw x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x22b5f469 + csrrs x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x113be3166 + csrrc x9, 2821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2821, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2821, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2821, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2821, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2821, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2821, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2821, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2821, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2821, 0b01111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter5h + li x11, 0xa5a5a5a5 + csrrw x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb60cd82f + csrrw x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x335f687c + csrrs x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8a06aa7e + csrrc x9, 2949, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2949, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2949, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2949, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2949, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2949, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2949, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2949, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2949, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2949, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter6 + li x11, 0xa5a5a5a5 + csrrw x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd5bab2b0 + csrrw x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11379add1 + csrrs x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xdb8b071e + csrrc x9, 2822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2822, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2822, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2822, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2822, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2822, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2822, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2822, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2822, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2822, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter6h + li x11, 0xa5a5a5a5 + csrrw x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8784b7a7 + csrrw x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2d2106ae + csrrs x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0480870b + csrrc x9, 2950, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2950, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2950, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2950, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2950, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2950, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2950, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2950, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2950, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2950, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter7 + li x11, 0xa5a5a5a5 + csrrw x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x67c7774d + csrrw x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8ebeb3dd + csrrs x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa2bb605d + csrrc x9, 2823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2823, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2823, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2823, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2823, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2823, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2823, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2823, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2823, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2823, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter7h + li x11, 0xa5a5a5a5 + csrrw x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xdfb36f89 + csrrw x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb86cb14f + csrrs x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3404d7a1 + csrrc x9, 2951, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2951, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2951, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2951, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2951, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2951, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2951, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2951, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2951, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2951, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter8 + li x11, 0xa5a5a5a5 + csrrw x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xcbb33310 + csrrw x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x115554667 + csrrs x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe0ce9e32 + csrrc x9, 2824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2824, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2824, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2824, 0b11110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2824, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2824, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2824, 0b00100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2824, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2824, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2824, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter8h + li x11, 0xa5a5a5a5 + csrrw x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa19b0227 + csrrw x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8fd17ca0 + csrrs x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x44490dcb + csrrc x9, 2952, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2952, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2952, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2952, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2952, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2952, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2952, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2952, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2952, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2952, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter9 + li x11, 0xa5a5a5a5 + csrrw x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6df9db64 + csrrw x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x21d0c32d + csrrs x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x374f3013 + csrrc x9, 2825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2825, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2825, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2825, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2825, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2825, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2825, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2825, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2825, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2825, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter9h + li x11, 0xa5a5a5a5 + csrrw x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x16563248 + csrrw x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8111dfc8 + csrrs x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x67e56ec3 + csrrc x9, 2953, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2953, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2953, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2953, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2953, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2953, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2953, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2953, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2953, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2953, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter10 + li x11, 0xa5a5a5a5 + csrrw x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4dd562df + csrrw x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc78076b4 + csrrs x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd955811e + csrrc x9, 2826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2826, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2826, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2826, 0b00100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2826, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2826, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2826, 0b01111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2826, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2826, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2826, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter10h + li x11, 0xa5a5a5a5 + csrrw x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x967f6488 + csrrw x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd0f3772a + csrrs x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x92dbc3d9 + csrrc x9, 2954, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2954, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2954, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2954, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2954, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2954, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2954, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2954, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2954, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2954, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter11 + li x11, 0xa5a5a5a5 + csrrw x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd985bd44 + csrrw x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xddd383ec + csrrs x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x136e651b + csrrc x9, 2827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2827, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2827, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2827, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2827, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2827, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2827, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2827, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2827, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2827, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter11h + li x11, 0xa5a5a5a5 + csrrw x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf98daaef + csrrw x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x95065567 + csrrs x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x52ceeb68 + csrrc x9, 2955, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2955, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2955, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2955, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2955, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2955, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2955, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2955, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2955, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2955, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter12 + li x11, 0xa5a5a5a5 + csrrw x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc469278e + csrrw x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3fdf688f + csrrs x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf3a762da + csrrc x9, 2828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2828, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2828, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2828, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2828, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2828, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2828, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2828, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2828, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2828, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter12h + li x11, 0xa5a5a5a5 + csrrw x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd9f997ff + csrrw x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa50dfeac + csrrs x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2a4b92a1 + csrrc x9, 2956, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2956, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2956, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2956, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2956, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2956, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2956, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2956, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2956, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2956, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter13 + li x11, 0xa5a5a5a5 + csrrw x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3e3d3a97 + csrrw x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0d63a340 + csrrs x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8844eff3 + csrrc x9, 2829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2829, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2829, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2829, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2829, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2829, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2829, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2829, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2829, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2829, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter13h + li x11, 0xa5a5a5a5 + csrrw x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf71a3344 + csrrw x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x15b5d8f2 + csrrs x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb61bcf19 + csrrc x9, 2957, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2957, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2957, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2957, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2957, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2957, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2957, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2957, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2957, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2957, 0b01111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter14 + li x11, 0xa5a5a5a5 + csrrw x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xbc19e171 + csrrw x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x587473d4 + csrrs x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf48ec7cb + csrrc x9, 2830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2830, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2830, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2830, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2830, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2830, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2830, 0b11111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2830, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2830, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2830, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter14h + li x11, 0xa5a5a5a5 + csrrw x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9b4ef995 + csrrw x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xde4e36bb + csrrs x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x82ed5a57 + csrrc x9, 2958, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2958, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2958, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2958, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2958, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2958, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2958, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2958, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2958, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2958, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter15 + li x11, 0xa5a5a5a5 + csrrw x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x49fe3b9f + csrrw x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xba519e9f + csrrs x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2c8ee266 + csrrc x9, 2831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2831, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2831, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2831, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2831, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2831, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2831, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2831, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2831, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2831, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter15h + li x11, 0xa5a5a5a5 + csrrw x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x347b664a + csrrw x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x55c36191 + csrrs x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6e8cdd81 + csrrc x9, 2959, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2959, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2959, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2959, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2959, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2959, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2959, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2959, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2959, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2959, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter16 + li x11, 0xa5a5a5a5 + csrrw x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9cb8d491 + csrrw x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4c396722 + csrrs x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xddaf6d7c + csrrc x9, 2832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2832, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2832, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2832, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2832, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2832, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2832, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2832, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2832, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2832, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter16h + li x11, 0xa5a5a5a5 + csrrw x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa33a2c98 + csrrw x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa989dd04 + csrrs x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2ca0ff17 + csrrc x9, 2960, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2960, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2960, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2960, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2960, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2960, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2960, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2960, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2960, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2960, 0b11110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter17 + li x11, 0xa5a5a5a5 + csrrw x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa2cf0b91 + csrrw x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11f43b04c + csrrs x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa757087a + csrrc x9, 2833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2833, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2833, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2833, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2833, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2833, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2833, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2833, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2833, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2833, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter17h + li x11, 0xa5a5a5a5 + csrrw x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x26211829 + csrrw x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x33bac2c5 + csrrs x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x31454d90 + csrrc x9, 2961, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2961, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2961, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2961, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2961, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2961, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2961, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2961, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2961, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2961, 0b11111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter18 + li x11, 0xa5a5a5a5 + csrrw x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x820ce090 + csrrw x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x07d6e7c3 + csrrs x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd0186c7b + csrrc x9, 2834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2834, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2834, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2834, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2834, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2834, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2834, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2834, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2834, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2834, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter18h + li x11, 0xa5a5a5a5 + csrrw x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11d6ff624 + csrrw x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11cfb8283 + csrrs x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3d7d1498 + csrrc x9, 2962, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2962, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2962, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2962, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2962, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2962, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2962, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2962, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2962, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2962, 0b01111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter19 + li x11, 0xa5a5a5a5 + csrrw x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa7647147 + csrrw x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xea76a4ee + csrrs x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x88b278f7 + csrrc x9, 2835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2835, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2835, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2835, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2835, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2835, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2835, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2835, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2835, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2835, 0b11110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter19h + li x11, 0xa5a5a5a5 + csrrw x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x81887006 + csrrw x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6a421be4 + csrrs x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x631cda02 + csrrc x9, 2963, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2963, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2963, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2963, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2963, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2963, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2963, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2963, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2963, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2963, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter20 + li x11, 0xa5a5a5a5 + csrrw x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3bb33bdd + csrrw x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x98adf327 + csrrs x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x113a026d4 + csrrc x9, 2836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2836, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2836, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2836, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2836, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2836, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2836, 0b11110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2836, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2836, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2836, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter20h + li x11, 0xa5a5a5a5 + csrrw x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1a178133 + csrrw x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb4c2a8a8 + csrrs x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x110686d01 + csrrc x9, 2964, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2964, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2964, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2964, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2964, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2964, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2964, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2964, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2964, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2964, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter21 + li x11, 0xa5a5a5a5 + csrrw x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc4188c14 + csrrw x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf9c2d0a5 + csrrs x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3374efc5 + csrrc x9, 2837, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2837, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2837, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2837, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2837, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2837, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2837, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2837, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2837, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2837, 0b00100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter21h + li x11, 0xa5a5a5a5 + csrrw x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe0744071 + csrrw x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6b72b089 + csrrs x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x460b5ce2 + csrrc x9, 2965, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2965, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2965, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2965, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2965, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2965, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2965, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2965, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2965, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2965, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter22 + li x11, 0xa5a5a5a5 + csrrw x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x00044222 + csrrw x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0876b03b + csrrs x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3a8901ec + csrrc x9, 2838, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2838, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2838, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2838, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2838, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2838, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2838, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2838, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2838, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2838, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter22h + li x11, 0xa5a5a5a5 + csrrw x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd3fa3053 + csrrw x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc176f34f + csrrs x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x866a571f + csrrc x9, 2966, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2966, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2966, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2966, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2966, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2966, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2966, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2966, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2966, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2966, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter23 + li x11, 0xa5a5a5a5 + csrrw x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4032f8a5 + csrrw x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x472d0a6d + csrrs x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6956412a + csrrc x9, 2839, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2839, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2839, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2839, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2839, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2839, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2839, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2839, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2839, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2839, 0b10011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter23h + li x11, 0xa5a5a5a5 + csrrw x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8ffd5545 + csrrw x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0179207e + csrrs x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11b3d5418 + csrrc x9, 2967, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2967, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2967, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2967, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2967, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2967, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2967, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2967, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2967, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2967, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter24 + li x11, 0xa5a5a5a5 + csrrw x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc3b6190d + csrrw x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5c1d71b + csrrs x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd9e2d94a + csrrc x9, 2840, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2840, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2840, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2840, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2840, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2840, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2840, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2840, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2840, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2840, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter24h + li x11, 0xa5a5a5a5 + csrrw x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x20c27b27 + csrrw x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd42ad2e1 + csrrs x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb1c22218 + csrrc x9, 2968, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2968, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2968, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2968, 0b01111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2968, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2968, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2968, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2968, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2968, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2968, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter25 + li x11, 0xa5a5a5a5 + csrrw x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2ae625cb + csrrw x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xab703701 + csrrs x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6c79bfad + csrrc x9, 2841, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2841, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2841, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2841, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2841, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2841, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2841, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2841, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2841, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2841, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter25h + li x11, 0xa5a5a5a5 + csrrw x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe7fd1748 + csrrw x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x910adda0 + csrrs x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4accc615 + csrrc x9, 2969, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2969, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2969, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2969, 0b11111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2969, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2969, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2969, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2969, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2969, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2969, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter26 + li x11, 0xa5a5a5a5 + csrrw x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1a36d840 + csrrw x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1b697e5f + csrrs x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd83173e2 + csrrc x9, 2842, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2842, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2842, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2842, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2842, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2842, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2842, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2842, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2842, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2842, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter26h + li x11, 0xa5a5a5a5 + csrrw x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6c05b217 + csrrw x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3e8c55a8 + csrrs x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8d309fde + csrrc x9, 2970, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2970, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2970, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2970, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2970, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2970, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2970, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2970, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2970, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2970, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter27 + li x11, 0xa5a5a5a5 + csrrw x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9a4468a3 + csrrw x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8d38cb81 + csrrs x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5e66a98e + csrrc x9, 2843, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2843, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2843, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2843, 0b01111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2843, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2843, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2843, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2843, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2843, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2843, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter27h + li x11, 0xa5a5a5a5 + csrrw x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb6479ce6 + csrrw x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x697f10d7 + csrrs x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb2371dc5 + csrrc x9, 2971, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2971, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2971, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2971, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2971, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2971, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2971, 0b10011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2971, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2971, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2971, 0b10011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter28 + li x11, 0xa5a5a5a5 + csrrw x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x016c6977 + csrrw x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8686d3df + csrrs x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1440ba1d + csrrc x9, 2844, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2844, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2844, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2844, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2844, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2844, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2844, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2844, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2844, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2844, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter28h + li x11, 0xa5a5a5a5 + csrrw x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9c93f59c + csrrw x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3b4a7607 + csrrs x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6526140d + csrrc x9, 2972, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2972, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2972, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2972, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2972, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2972, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2972, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2972, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2972, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2972, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter29 + li x11, 0xa5a5a5a5 + csrrw x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd8b8311b + csrrw x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8c2e6bc2 + csrrs x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x824ec481 + csrrc x9, 2845, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2845, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2845, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2845, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2845, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2845, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2845, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2845, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2845, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2845, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter29h + li x11, 0xa5a5a5a5 + csrrw x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5ef8afd + csrrw x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd88815c0 + csrrs x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xee9a567e + csrrc x9, 2973, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2973, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2973, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2973, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2973, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2973, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2973, 0b11111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2973, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2973, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2973, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter30 + li x11, 0xa5a5a5a5 + csrrw x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5715c5f0 + csrrw x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xcc3266a3 + csrrs x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x321b63d8 + csrrc x9, 2846, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2846, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2846, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2846, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2846, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2846, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2846, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2846, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2846, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2846, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter30h + li x11, 0xa5a5a5a5 + csrrw x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x12b9a81b + csrrw x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb5fd135e + csrrs x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x44bf5410 + csrrc x9, 2974, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2974, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2974, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2974, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2974, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2974, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2974, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2974, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2974, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2974, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter31 + li x11, 0xa5a5a5a5 + csrrw x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb79f28bf + csrrw x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x524a5fd4 + csrrs x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x35d70289 + csrrc x9, 2847, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2847, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2847, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2847, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2847, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2847, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2847, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2847, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2847, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2847, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmcounter31h + li x11, 0xa5a5a5a5 + csrrw x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd3d01cb5 + csrrw x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x20c606c5 + csrrs x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe99295e4 + csrrc x9, 2975, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2975, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2975, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 2975, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2975, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2975, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 2975, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2975, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2975, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 2975, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail # mstatus - li x13, 0xa5a5a5a5 - csrrw x5, 768, x13 - li x13, 0x00001800 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 768, x13 - li x13, 0x00001880 - bne x13, x5, csr_fail - li x13, 0x4e7ef8bd - csrrw x5, 768, x13 - li x13, 0x00001808 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 768, x13 - li x13, 0x00001888 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 768, x13 - li x13, 0x00001888 - bne x13, x5, csr_fail - li x13, 0x333fe11e - csrrs x5, 768, x13 - li x13, 0x00001888 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 768, x13 - li x13, 0x00001888 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 768, x13 - li x13, 0x00001808 - bne x13, x5, csr_fail - li x13, 0x3111c250 - csrrc x5, 768, x13 - li x13, 0x00001800 - bne x13, x5, csr_fail - csrrwi x5, 768, 0b00101 - li x13, 0x00001800 - bne x13, x5, csr_fail - csrrwi x5, 768, 0b11010 - li x13, 0x00001800 - bne x13, x5, csr_fail - csrrwi x5, 768, 0b01000 - li x13, 0x00001808 - bne x13, x5, csr_fail - csrrsi x5, 768, 0b00101 - li x13, 0x00001808 - bne x13, x5, csr_fail - csrrsi x5, 768, 0b11010 - li x13, 0x00001808 - bne x13, x5, csr_fail - csrrsi x5, 768, 0b10111 - li x13, 0x00001808 - bne x13, x5, csr_fail - csrrci x5, 768, 0b00101 - li x13, 0x00001808 - bne x13, x5, csr_fail - csrrci x5, 768, 0b11010 - li x13, 0x00001808 - bne x13, x5, csr_fail - csrrci x5, 768, 0b10110 - li x13, 0x00001800 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 768, x11 + li x11, 0x00001800 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 768, x11 + li x11, 0x00200080 + bne x11, x9, csr_fail + li x11, 0x9a7c92c1 + csrrw x9, 768, x11 + li x11, 0x00021808 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 768, x11 + li x11, 0x00201880 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 768, x11 + li x11, 0x00201880 + bne x11, x9, csr_fail + li x11, 0x11b8ddf73 + csrrs x9, 768, x11 + li x11, 0x00221888 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 768, x11 + li x11, 0x00221888 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 768, x11 + li x11, 0x00021808 + bne x11, x9, csr_fail + li x11, 0xf89930dc + csrrc x9, 768, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 768, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 768, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 768, 0b00110 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrsi x9, 768, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 768, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 768, 0b01110 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrci x9, 768, 0b00101 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrci x9, 768, 0b11010 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrci x9, 768, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail # misa - li x13, 0xa5a5a5a5 - csrrw x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0x417f1e29 - csrrw x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0x503ffce9 - csrrs x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - li x13, 0xe5391849 - csrrc x5, 769, x13 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrwi x5, 769, 0b00101 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrwi x5, 769, 0b11010 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrwi x5, 769, 0b11001 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrsi x5, 769, 0b00101 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrsi x5, 769, 0b11010 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrsi x5, 769, 0b01110 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrci x5, 769, 0b00101 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrci x5, 769, 0b11010 - li x13, 0x40001104 - bne x13, x5, csr_fail - csrrci x5, 769, 0b11000 - li x13, 0x40001104 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0x971f2a6b + csrrw x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0x97e3090d + csrrs x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + li x11, 0x146ad0c3 + csrrc x9, 769, x11 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrwi x9, 769, 0b00101 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrwi x9, 769, 0b11010 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrwi x9, 769, 0b00100 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrsi x9, 769, 0b00101 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrsi x9, 769, 0b11010 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrsi x9, 769, 0b01000 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrci x9, 769, 0b00101 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrci x9, 769, 0b11010 + li x11, 0x40901104 + bne x11, x9, csr_fail + csrrci x9, 769, 0b11101 + li x11, 0x40901104 + bne x11, x9, csr_fail # mie - li x13, 0xa5a5a5a5 - csrrw x5, 772, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 772, x13 - li x13, 0xa5a50080 - bne x13, x5, csr_fail - li x13, 0x6b5440ff - csrrw x5, 772, x13 - li x13, 0x5a5a0808 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 772, x13 - li x13, 0x6b540088 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 772, x13 - li x13, 0xeff50088 - bne x13, x5, csr_fail - li x13, 0x72bf4a65 - csrrs x5, 772, x13 - li x13, 0xffff0888 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 772, x13 - li x13, 0xffff0888 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 772, x13 - li x13, 0x5a5a0808 - bne x13, x5, csr_fail - li x13, 0x8693065c - csrrc x5, 772, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 772, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 772, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 772, 0b00010 - li x13, 0x00000008 - bne x13, x5, csr_fail - csrrsi x5, 772, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 772, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 772, 0b01010 - li x13, 0x00000008 - bne x13, x5, csr_fail - csrrci x5, 772, 0b00101 - li x13, 0x00000008 - bne x13, x5, csr_fail - csrrci x5, 772, 0b11010 - li x13, 0x00000008 - bne x13, x5, csr_fail - csrrci x5, 772, 0b10110 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 772, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 772, x11 + li x11, 0xa5a50080 + bne x11, x9, csr_fail + li x11, 0x582e2687 + csrrw x9, 772, x11 + li x11, 0x5a5a0808 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 772, x11 + li x11, 0x582e0080 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 772, x11 + li x11, 0xfdaf0080 + bne x11, x9, csr_fail + li x11, 0x2e0235bf + csrrs x9, 772, x11 + li x11, 0xffff0888 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 772, x11 + li x11, 0xffff0888 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 772, x11 + li x11, 0x5a5a0808 + bne x11, x9, csr_fail + li x11, 0xfac4ef3c + csrrc x9, 772, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 772, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 772, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 772, 0b10000 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrsi x9, 772, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 772, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 772, 0b00011 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrci x9, 772, 0b00101 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrci x9, 772, 0b11010 + li x11, 0x00000008 + bne x11, x9, csr_fail + csrrci x9, 772, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail # mtvec - li x13, 0xa5a5a5a5 - csrrw x5, 773, x13 - li x13, 0x00000001 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 773, x13 - li x13, 0xa5a5a501 - bne x13, x5, csr_fail - li x13, 0xf2f39001 - csrrw x5, 773, x13 - li x13, 0x5a5a5a00 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 773, x13 - li x13, 0xf2f39001 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 773, x13 - li x13, 0xf7f7b501 - bne x13, x5, csr_fail - li x13, 0x5233a9f9 - csrrs x5, 773, x13 - li x13, 0xffffff01 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 773, x13 - li x13, 0xffffff01 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 773, x13 - li x13, 0x5a5a5a00 - bne x13, x5, csr_fail - li x13, 0x5074371d - csrrc x5, 773, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 773, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 773, 0b11010 - li x13, 0x00000001 - bne x13, x5, csr_fail - csrrwi x5, 773, 0b00010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 773, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 773, 0b11010 - li x13, 0x00000001 - bne x13, x5, csr_fail - csrrsi x5, 773, 0b00101 - li x13, 0x00000001 - bne x13, x5, csr_fail - csrrci x5, 773, 0b00101 - li x13, 0x00000001 - bne x13, x5, csr_fail - csrrci x5, 773, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 773, 0b11110 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 773, x11 + li x11, 0x00000001 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 773, x11 + li x11, 0xa5a5a581 + bne x11, x9, csr_fail + li x11, 0x1e65bf9c + csrrw x9, 773, x11 + li x11, 0x5a5a5a01 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 773, x11 + li x11, 0x1e65bf80 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 773, x11 + li x11, 0xbfe5bf81 + bne x11, x9, csr_fail + li x11, 0x62f03b0f + csrrs x9, 773, x11 + li x11, 0xffffff81 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 773, x11 + li x11, 0xffffff81 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 773, x11 + li x11, 0x5a5a5a00 + bne x11, x9, csr_fail + li x11, 0x02ab5359 + csrrc x9, 773, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 773, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 773, 0b11010 + li x11, 0x00000001 + bne x11, x9, csr_fail + csrrwi x9, 773, 0b00000 + li x11, 0x00000001 + bne x11, x9, csr_fail + csrrsi x9, 773, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 773, 0b11010 + li x11, 0x00000001 + bne x11, x9, csr_fail + csrrsi x9, 773, 0b10010 + li x11, 0x00000001 + bne x11, x9, csr_fail + csrrci x9, 773, 0b00101 + li x11, 0x00000001 + bne x11, x9, csr_fail + csrrci x9, 773, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 773, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstatush + li x11, 0xa5a5a5a5 + csrrw x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x166f7c9a + csrrw x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9c84a633 + csrrs x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc54e1a19 + csrrc x9, 784, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 784, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 784, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 784, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 784, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 784, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 784, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 784, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 784, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 784, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail # mcountinhibit - li x13, 0xa5a5a5a5 - csrrw x5, 800, x13 - li x13, 0x0000000d - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 800, x13 - li x13, 0x00000005 - bne x13, x5, csr_fail - li x13, 0xa48e0dc7 - csrrw x5, 800, x13 - li x13, 0x00000008 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 800, x13 - li x13, 0x00000005 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 800, x13 - li x13, 0x00000005 - bne x13, x5, csr_fail - li x13, 0x5c31d6e0 - csrrs x5, 800, x13 - li x13, 0x0000000d - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 800, x13 - li x13, 0x0000000d - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 800, x13 - li x13, 0x00000008 - bne x13, x5, csr_fail - li x13, 0x27bf2081 - csrrc x5, 800, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 800, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 800, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 800, 0b10000 - li x13, 0x00000008 - bne x13, x5, csr_fail - csrrsi x5, 800, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 800, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrsi x5, 800, 0b10110 - li x13, 0x0000000d - bne x13, x5, csr_fail - csrrci x5, 800, 0b00101 - li x13, 0x0000000d - bne x13, x5, csr_fail - csrrci x5, 800, 0b11010 - li x13, 0x00000008 - bne x13, x5, csr_fail - csrrci x5, 800, 0b00011 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 800, x11 + li x11, 0x00000005 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 800, x11 + li x11, 0x00000005 + bne x11, x9, csr_fail + li x11, 0x3593122b + csrrw x9, 800, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 800, x11 + li x11, 0x00000001 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 800, x11 + li x11, 0x00000005 + bne x11, x9, csr_fail + li x11, 0xd843e959 + csrrs x9, 800, x11 + li x11, 0x00000005 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 800, x11 + li x11, 0x00000005 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 800, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4b289953 + csrrc x9, 800, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 800, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 800, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrwi x9, 800, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 800, 0b00101 + li x11, 0x00000001 + bne x11, x9, csr_fail + csrrsi x9, 800, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrsi x9, 800, 0b01111 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrci x9, 800, 0b00101 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrci x9, 800, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 800, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail # mhpmevent3 - li x13, 0xa5a5a5a5 - csrrw x5, 803, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 803, x13 - li x13, 0x0000a5a5 - bne x13, x5, csr_fail - li x13, 0x1acbb7b9 - csrrw x5, 803, x13 - li x13, 0x00005a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 803, x13 - li x13, 0x0000b7b9 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 803, x13 - li x13, 0x0000b7bd - bne x13, x5, csr_fail - li x13, 0xb536dfae - csrrs x5, 803, x13 - li x13, 0x0000ffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 803, x13 - li x13, 0x0000ffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 803, x13 - li x13, 0x00005a5a - bne x13, x5, csr_fail - li x13, 0xb8207172 - csrrc x5, 803, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 803, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 803, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 803, 0b00011 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 803, 0b00101 - li x13, 0x00000003 - bne x13, x5, csr_fail - csrrsi x5, 803, 0b11010 - li x13, 0x00000007 - bne x13, x5, csr_fail - csrrsi x5, 803, 0b01000 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 803, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 803, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 803, 0b01100 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4ce47fb0 + csrrw x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6630967e + csrrs x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x133dd208 + csrrc x9, 803, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 803, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 803, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 803, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 803, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 803, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 803, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 803, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 803, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 803, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent4 + li x11, 0xa5a5a5a5 + csrrw x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8f405c14 + csrrw x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8d005f89 + csrrs x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x35394024 + csrrc x9, 804, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 804, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 804, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 804, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 804, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 804, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 804, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 804, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 804, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 804, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent5 + li x11, 0xa5a5a5a5 + csrrw x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0b8ecb5c + csrrw x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe6a47042 + csrrs x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xefa4de00 + csrrc x9, 805, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 805, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 805, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 805, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 805, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 805, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 805, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 805, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 805, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 805, 0b11110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent6 + li x11, 0xa5a5a5a5 + csrrw x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5392799a + csrrw x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11821a868 + csrrs x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xfd4b6e5d + csrrc x9, 806, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 806, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 806, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 806, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 806, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 806, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 806, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 806, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 806, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 806, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent7 + li x11, 0xa5a5a5a5 + csrrw x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4031e5e1 + csrrw x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf04d2553 + csrrs x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5bea1275 + csrrc x9, 807, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 807, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 807, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 807, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 807, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 807, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 807, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 807, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 807, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 807, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent8 + li x11, 0xa5a5a5a5 + csrrw x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x29fa8cef + csrrw x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe41e4929 + csrrs x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6b9ff06c + csrrc x9, 808, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 808, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 808, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 808, 0b10010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 808, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 808, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 808, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 808, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 808, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 808, 0b11110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent9 + li x11, 0xa5a5a5a5 + csrrw x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc58e93ec + csrrw x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0accde55 + csrrs x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x34632455 + csrrc x9, 809, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 809, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 809, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 809, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 809, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 809, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 809, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 809, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 809, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 809, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent10 + li x11, 0xa5a5a5a5 + csrrw x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc3eb7255 + csrrw x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11a7ae15c + csrrs x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xef96b5e1 + csrrc x9, 810, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 810, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 810, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 810, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 810, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 810, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 810, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 810, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 810, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 810, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent11 + li x11, 0xa5a5a5a5 + csrrw x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x98604235 + csrrw x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5267663c + csrrs x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x33fff12d + csrrc x9, 811, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 811, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 811, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 811, 0b10111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 811, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 811, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 811, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 811, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 811, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 811, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent12 + li x11, 0xa5a5a5a5 + csrrw x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x99dacd44 + csrrw x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xbde3d59d + csrrs x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x85fa2a1f + csrrc x9, 812, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 812, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 812, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 812, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 812, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 812, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 812, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 812, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 812, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 812, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent13 + li x11, 0xa5a5a5a5 + csrrw x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb6540329 + csrrw x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc7e02eef + csrrs x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11d14c47b + csrrc x9, 813, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 813, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 813, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 813, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 813, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 813, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 813, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 813, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 813, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 813, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent14 + li x11, 0xa5a5a5a5 + csrrw x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x07085d25 + csrrw x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x386a0ada + csrrs x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8e7a21eb + csrrc x9, 814, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 814, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 814, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 814, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 814, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 814, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 814, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 814, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 814, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 814, 0b01101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent15 + li x11, 0xa5a5a5a5 + csrrw x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9d129238 + csrrw x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xb1e03b26 + csrrs x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8d240040 + csrrc x9, 815, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 815, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 815, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 815, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 815, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 815, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 815, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 815, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 815, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 815, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent16 + li x11, 0xa5a5a5a5 + csrrw x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x828b7663 + csrrw x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc526901a + csrrs x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x14a1f2ce + csrrc x9, 816, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 816, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 816, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 816, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 816, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 816, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 816, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 816, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 816, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 816, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent17 + li x11, 0xa5a5a5a5 + csrrw x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0cb70ea0 + csrrw x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4baa1457 + csrrs x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x322bedbe + csrrc x9, 817, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 817, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 817, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 817, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 817, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 817, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 817, 0b10000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 817, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 817, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 817, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent18 + li x11, 0xa5a5a5a5 + csrrw x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x81254bfb + csrrw x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x43247ccd + csrrs x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9278bafb + csrrc x9, 818, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 818, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 818, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 818, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 818, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 818, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 818, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 818, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 818, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 818, 0b10010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent19 + li x11, 0xa5a5a5a5 + csrrw x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1af51837 + csrrw x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5003adcd + csrrs x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xaa5d8dea + csrrc x9, 819, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 819, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 819, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 819, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 819, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 819, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 819, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 819, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 819, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 819, 0b11111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent20 + li x11, 0xa5a5a5a5 + csrrw x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x119dacb4c + csrrw x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x48e24124 + csrrs x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x333aef34 + csrrc x9, 820, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 820, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 820, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 820, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 820, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 820, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 820, 0b11110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 820, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 820, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 820, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent21 + li x11, 0xa5a5a5a5 + csrrw x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa48d9a74 + csrrw x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6e8305ec + csrrs x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6ce305dd + csrrc x9, 821, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 821, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 821, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 821, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 821, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 821, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 821, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 821, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 821, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 821, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent22 + li x11, 0xa5a5a5a5 + csrrw x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd2948384 + csrrw x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x864cefd3 + csrrs x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xad7a85f0 + csrrc x9, 822, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 822, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 822, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 822, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 822, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 822, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 822, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 822, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 822, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 822, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent23 + li x11, 0xa5a5a5a5 + csrrw x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x811eea21 + csrrw x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5d316974 + csrrs x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe521eb69 + csrrc x9, 823, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 823, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 823, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 823, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 823, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 823, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 823, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 823, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 823, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 823, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent24 + li x11, 0xa5a5a5a5 + csrrw x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x0ef0532e + csrrw x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x81afcb2c + csrrs x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc0be9384 + csrrc x9, 824, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 824, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 824, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 824, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 824, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 824, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 824, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 824, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 824, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 824, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent25 + li x11, 0xa5a5a5a5 + csrrw x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe2d807cd + csrrw x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf72a6b4e + csrrs x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xd6622e1e + csrrc x9, 825, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 825, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 825, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 825, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 825, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 825, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 825, 0b10010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 825, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 825, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 825, 0b10011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent26 + li x11, 0xa5a5a5a5 + csrrw x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe8d89adc + csrrw x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xfb5468cf + csrrs x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe213b87b + csrrc x9, 826, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 826, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 826, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 826, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 826, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 826, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 826, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 826, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 826, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 826, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent27 + li x11, 0xa5a5a5a5 + csrrw x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf14c615f + csrrw x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x9233d4be + csrrs x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1195d3a5b + csrrc x9, 827, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 827, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 827, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 827, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 827, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 827, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 827, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 827, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 827, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 827, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent28 + li x11, 0xa5a5a5a5 + csrrw x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa8ba5b72 + csrrw x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xcba1bbf4 + csrrs x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x986bfc42 + csrrc x9, 828, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 828, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 828, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 828, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 828, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 828, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 828, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 828, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 828, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 828, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent29 + li x11, 0xa5a5a5a5 + csrrw x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x115bb99e8 + csrrw x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xbc5e8e39 + csrrs x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa20ef9ae + csrrc x9, 829, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 829, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 829, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 829, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 829, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 829, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 829, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 829, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 829, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 829, 0b11101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent30 + li x11, 0xa5a5a5a5 + csrrw x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xc6090bef + csrrw x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa480038c + csrrs x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11688b57a + csrrc x9, 830, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 830, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 830, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 830, 0b01000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 830, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 830, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 830, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 830, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 830, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 830, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mhpmevent31 + li x11, 0xa5a5a5a5 + csrrw x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x589e6c7f + csrrw x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x56160d47 + csrrs x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2aaa2efb + csrrc x9, 831, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 831, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 831, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 831, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 831, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 831, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 831, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 831, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 831, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 831, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail # mscratch - li x13, 0xa5a5a5a5 - csrrw x5, 832, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 832, x13 - li x13, 0xa5a5a5a5 - bne x13, x5, csr_fail - li x13, 0x1bac3bb9 - csrrw x5, 832, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 832, x13 - li x13, 0x1bac3bb9 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 832, x13 - li x13, 0xbfadbfbd - bne x13, x5, csr_fail - li x13, 0x1360a992 - csrrs x5, 832, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 832, x13 - li x13, 0xffffffff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 832, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0x605e5206 - csrrc x5, 832, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 832, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 832, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 832, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 832, 0b00101 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 832, 0b11010 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrsi x5, 832, 0b11101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 832, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 832, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 832, 0b11011 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 832, x11 + li x11, 0xa5a5a5a5 + bne x11, x9, csr_fail + li x11, 0x292ce709 + csrrw x9, 832, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 832, x11 + li x11, 0x292ce709 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 832, x11 + li x11, 0xadade7ad + bne x11, x9, csr_fail + li x11, 0xf95e9e92 + csrrs x9, 832, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 832, x11 + li x11, 0xffffffff + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 832, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xa2cb9fa9 + csrrc x9, 832, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 832, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 832, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrwi x9, 832, 0b01001 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 832, 0b00101 + li x11, 0x00000009 + bne x11, x9, csr_fail + csrrsi x9, 832, 0b11010 + li x11, 0x0000000d + bne x11, x9, csr_fail + csrrsi x9, 832, 0b11101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 832, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 832, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrci x9, 832, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail # mepc - li x13, 0xa5a5a5a5 - csrrw x5, 833, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 833, x13 - li x13, 0xa5a5a5a4 - bne x13, x5, csr_fail - li x13, 0x8fd57634 - csrrw x5, 833, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 833, x13 - li x13, 0x8fd57634 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 833, x13 - li x13, 0xaff5f7b4 - bne x13, x5, csr_fail - li x13, 0x863cbd41 - csrrs x5, 833, x13 - li x13, 0xfffffffe - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 833, x13 - li x13, 0xfffffffe - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 833, x13 - li x13, 0x5a5a5a5a - bne x13, x5, csr_fail - li x13, 0xaea1a3ca - csrrc x5, 833, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 833, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 833, 0b11010 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrwi x5, 833, 0b01010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 833, 0b00101 - li x13, 0x0000000a - bne x13, x5, csr_fail - csrrsi x5, 833, 0b11010 - li x13, 0x0000000e - bne x13, x5, csr_fail - csrrsi x5, 833, 0b10100 - li x13, 0x0000001e - bne x13, x5, csr_fail - csrrci x5, 833, 0b00101 - li x13, 0x0000001e - bne x13, x5, csr_fail - csrrci x5, 833, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 833, 0b00000 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 833, x11 + li x11, 0xa5a5a5a4 + bne x11, x9, csr_fail + li x11, 0x2a3212f3 + csrrw x9, 833, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 833, x11 + li x11, 0x2a3212f2 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 833, x11 + li x11, 0xafb7b7f6 + bne x11, x9, csr_fail + li x11, 0x464e8369 + csrrs x9, 833, x11 + li x11, 0xfffffffe + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 833, x11 + li x11, 0xfffffffe + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 833, x11 + li x11, 0x5a5a5a5a + bne x11, x9, csr_fail + li x11, 0xde7db7e9 + csrrc x9, 833, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 833, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 833, 0b11010 + li x11, 0x00000004 + bne x11, x9, csr_fail + csrrwi x9, 833, 0b00110 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 833, 0b00101 + li x11, 0x00000006 + bne x11, x9, csr_fail + csrrsi x9, 833, 0b11010 + li x11, 0x00000006 + bne x11, x9, csr_fail + csrrsi x9, 833, 0b11010 + li x11, 0x0000001e + bne x11, x9, csr_fail + csrrci x9, 833, 0b00101 + li x11, 0x0000001e + bne x11, x9, csr_fail + csrrci x9, 833, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrci x9, 833, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail # mcause - li x13, 0xa5a5a5a5 - csrrw x5, 834, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 834, x13 - li x13, 0x800000a5 - bne x13, x5, csr_fail - li x13, 0x986194c0 - csrrw x5, 834, x13 - li x13, 0x0000005a - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 834, x13 - li x13, 0x800000c0 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 834, x13 - li x13, 0x800000e5 - bne x13, x5, csr_fail - li x13, 0xfeefe913 - csrrs x5, 834, x13 - li x13, 0x800000ff - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 834, x13 - li x13, 0x800000ff - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 834, x13 - li x13, 0x0000005a - bne x13, x5, csr_fail - li x13, 0x167e2e49 - csrrc x5, 834, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 834, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 834, 0b11010 - li x13, 0x00000005 - bne x13, x5, csr_fail - csrrwi x5, 834, 0b01011 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrsi x5, 834, 0b00101 - li x13, 0x0000000b - bne x13, x5, csr_fail - csrrsi x5, 834, 0b11010 - li x13, 0x0000000f - bne x13, x5, csr_fail - csrrsi x5, 834, 0b01000 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 834, 0b00101 - li x13, 0x0000001f - bne x13, x5, csr_fail - csrrci x5, 834, 0b11010 - li x13, 0x0000001a - bne x13, x5, csr_fail - csrrci x5, 834, 0b00010 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 834, x11 + li x11, 0x800005a5 + bne x11, x9, csr_fail + li x11, 0x5eca9a5f + csrrw x9, 834, x11 + li x11, 0x0000025a + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 834, x11 + li x11, 0x0000025f + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 834, x11 + li x11, 0x800007ff + bne x11, x9, csr_fail + li x11, 0x118b23ee3 + csrrs x9, 834, x11 + li x11, 0x800007ff + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 834, x11 + li x11, 0x800007ff + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 834, x11 + li x11, 0x0000025a + bne x11, x9, csr_fail + li x11, 0xe03cb00e + csrrc x9, 834, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 834, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 834, 0b11010 + li x11, 0x00000005 + bne x11, x9, csr_fail + csrrwi x9, 834, 0b11110 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrsi x9, 834, 0b00101 + li x11, 0x0000001e + bne x11, x9, csr_fail + csrrsi x9, 834, 0b11010 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrsi x9, 834, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 834, 0b00101 + li x11, 0x0000001f + bne x11, x9, csr_fail + csrrci x9, 834, 0b11010 + li x11, 0x0000001a + bne x11, x9, csr_fail + csrrci x9, 834, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail # mtval - li x13, 0xa5a5a5a5 - csrrw x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x68859f83 - csrrw x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xcb99fb2b - csrrs x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x0bf231b1 - csrrc x5, 835, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 835, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 835, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 835, 0b10101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 835, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 835, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 835, 0b00010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 835, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 835, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 835, 0b10100 - li x13, 0x00000000 - bne x13, x5, csr_fail + li x11, 0xa5a5a5a5 + csrrw x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xefcaf843 + csrrw x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1d964c42 + csrrs x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5d71203a + csrrc x9, 835, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 835, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 835, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 835, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 835, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 835, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 835, 0b00010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 835, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 835, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 835, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail # mip - li x13, 0xa5a5a5a5 - csrrw x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xbf45c726 - csrrw x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x022d80eb - csrrs x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xcd6b5550 - csrrc x5, 836, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 836, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 836, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 836, 0b00100 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 836, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 836, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 836, 0b11100 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 836, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 836, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 836, 0b10100 - li x13, 0x00000000 - bne x13, x5, csr_fail - # tselect - li x13, 0xa5a5a5a5 - csrrw x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xc069d89e - csrrw x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5c11bb93 - csrrs x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xc56ebeb5 - csrrc x5, 1952, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1952, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1952, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1952, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1952, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1952, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1952, 0b11101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1952, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1952, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1952, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - # tdata1 - li x13, 0xa5a5a5a5 - csrrw x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0x3fe6aa9d - csrrw x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0x5d95c4de - csrrs x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - li x13, 0xdf6e2e65 - csrrc x5, 1953, x13 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrwi x5, 1953, 0b00101 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrwi x5, 1953, 0b11010 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrwi x5, 1953, 0b11000 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrsi x5, 1953, 0b00101 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrsi x5, 1953, 0b11010 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrsi x5, 1953, 0b01110 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrci x5, 1953, 0b00101 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrci x5, 1953, 0b11010 - li x13, 0x28001040 - bne x13, x5, csr_fail - csrrci x5, 1953, 0b11000 - li x13, 0x28001040 - bne x13, x5, csr_fail - # tdata2 - li x13, 0xa5a5a5a5 - csrrw x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x0080519f - csrrw x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa00a91ed - csrrs x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xfc4294a9 - csrrc x5, 1954, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1954, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1954, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1954, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1954, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1954, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1954, 0b10010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1954, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1954, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1954, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - # tdata3 - li x13, 0xa5a5a5a5 - csrrw x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x05fd5b26 - csrrw x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x546e80c5 - csrrs x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xe5027598 - csrrc x5, 1955, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1955, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1955, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1955, 0b01100 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1955, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1955, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1955, 0b10111 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1955, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1955, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1955, 0b10001 - li x13, 0x00000000 - bne x13, x5, csr_fail - # tinfo - li x13, 0xa5a5a5a5 - csrrw x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0xcc54e6cd - csrrw x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0x29764e64 - csrrs x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - li x13, 0x8a62f5d1 - csrrc x5, 1956, x13 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrwi x5, 1956, 0b00101 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrwi x5, 1956, 0b11010 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrwi x5, 1956, 0b11000 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrsi x5, 1956, 0b00101 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrsi x5, 1956, 0b11010 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrsi x5, 1956, 0b00011 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrci x5, 1956, 0b00101 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrci x5, 1956, 0b11010 - li x13, 0x00000004 - bne x13, x5, csr_fail - csrrci x5, 1956, 0b00111 - li x13, 0x00000004 - bne x13, x5, csr_fail - # mcontext - li x13, 0xa5a5a5a5 - csrrw x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa51aa700 - csrrw x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xe0229cb9 - csrrs x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x1a976889 - csrrc x5, 1960, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1960, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1960, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1960, 0b10100 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1960, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1960, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1960, 0b11001 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1960, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1960, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1960, 0b10111 - li x13, 0x00000000 - bne x13, x5, csr_fail - # scontext - li x13, 0xa5a5a5a5 - csrrw x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrw x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xed4294ae - csrrw x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrs x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrs x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xde286229 - csrrs x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xa5a5a5a5 - csrrc x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0x5a5a5a5a - csrrc x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - li x13, 0xda209ad2 - csrrc x5, 1962, x13 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1962, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1962, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrwi x5, 1962, 0b10011 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1962, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1962, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrsi x5, 1962, 0b11001 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1962, 0b00101 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1962, 0b11010 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrrci x5, 1962, 0b11011 - li x13, 0x00000000 - bne x13, x5, csr_fail - csrr x5, 1962 - li x13, 0x00000000 - bne x13, x5, csr_fail - + li x11, 0xa5a5a5a5 + csrrw x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xdfd165e5 + csrrw x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x50c90b19 + csrrs x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xdb9aea03 + csrrc x9, 836, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 836, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 836, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 836, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 836, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 836, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 836, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 836, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 836, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 836, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # jvt + li x11, 0xa5a5a5a5 + csrrw x9, 23, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 23, x11 + li x11, 0xa5a5a580 + bne x11, x9, csr_fail + li x11, 0xa5fc7d39 + csrrw x9, 23, x11 + li x11, 0x5a5a5a40 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 23, x11 + li x11, 0xa5fc7d00 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 23, x11 + li x11, 0xa5fdfd80 + bne x11, x9, csr_fail + li x11, 0x2af6d417 + csrrs x9, 23, x11 + li x11, 0xffffffc0 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 23, x11 + li x11, 0xffffffc0 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 23, x11 + li x11, 0x5a5a5a40 + bne x11, x9, csr_fail + li x11, 0x39b695fc + csrrc x9, 23, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 23, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 23, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 23, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 23, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 23, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 23, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 23, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 23, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 23, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mcounteren + li x11, 0xa5a5a5a5 + csrrw x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x25bc09e4 + csrrw x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x31b6b52c + csrrs x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xe72dba72 + csrrc x9, 774, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 774, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 774, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 774, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 774, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 774, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 774, 0b01100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 774, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 774, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 774, 0b10100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # menvcfg + li x11, 0xa5a5a5a5 + csrrw x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xbc5a8f36 + csrrw x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5f959c4a + csrrs x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x34d7ba81 + csrrc x9, 778, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 778, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 778, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 778, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 778, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 778, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 778, 0b01001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 778, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 778, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 778, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen0 + li x11, 0xa5a5a5a5 + csrrw x9, 780, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 780, x11 + li x11, 0x00000004 + bne x11, x9, csr_fail + li x11, 0x99eae203 + csrrw x9, 780, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 780, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 780, x11 + li x11, 0x00000004 + bne x11, x9, csr_fail + li x11, 0x0ad6a6f4 + csrrs x9, 780, x11 + li x11, 0x00000004 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 780, x11 + li x11, 0x00000004 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 780, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3c833ea0 + csrrc x9, 780, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 780, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 780, 0b11010 + li x11, 0x00000004 + bne x11, x9, csr_fail + csrrwi x9, 780, 0b11001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 780, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 780, 0b11010 + li x11, 0x00000004 + bne x11, x9, csr_fail + csrrsi x9, 780, 0b11001 + li x11, 0x00000004 + bne x11, x9, csr_fail + csrrci x9, 780, 0b00101 + li x11, 0x00000004 + bne x11, x9, csr_fail + csrrci x9, 780, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 780, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen1 + li x11, 0xa5a5a5a5 + csrrw x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1140c5412 + csrrw x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xad20a9a7 + csrrs x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x43b3f50e + csrrc x9, 781, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 781, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 781, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 781, 0b10011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 781, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 781, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 781, 0b00001 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 781, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 781, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 781, 0b10001 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen2 + li x11, 0xa5a5a5a5 + csrrw x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11b7eef78 + csrrw x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf6555e56 + csrrs x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x2579a333 + csrrc x9, 782, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 782, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 782, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 782, 0b00011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 782, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 782, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 782, 0b10110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 782, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 782, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 782, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen3 + li x11, 0xa5a5a5a5 + csrrw x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x11dde970b + csrrw x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xdd6a83ae + csrrs x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xbb425cda + csrrc x9, 783, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 783, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 783, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 783, 0b01111 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 783, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 783, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 783, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 783, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 783, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 783, 0b11011 + li x11, 0x00000000 + bne x11, x9, csr_fail + # menvcfgh + li x11, 0xa5a5a5a5 + csrrw x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x4131e864 + csrrw x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xcfbcf5ff + csrrs x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xf9502a0a + csrrc x9, 794, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 794, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 794, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 794, 0b11100 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 794, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 794, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 794, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 794, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 794, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 794, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen0h + li x11, 0xa5a5a5a5 + csrrw x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x87230986 + csrrw x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x39a79618 + csrrs x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x1d19bf44 + csrrc x9, 796, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 796, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 796, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 796, 0b01110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 796, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 796, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 796, 0b00110 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 796, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 796, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 796, 0b01010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen1h + li x11, 0xa5a5a5a5 + csrrw x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xafa568e9 + csrrw x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3de81a62 + csrrs x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x560bb5f2 + csrrc x9, 797, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 797, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 797, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 797, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 797, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 797, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 797, 0b10010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 797, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 797, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 797, 0b00111 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen2h + li x11, 0xa5a5a5a5 + csrrw x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x3480340e + csrrw x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x8c88b13b + csrrs x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x6f449043 + csrrc x9, 798, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 798, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 798, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 798, 0b00000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 798, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 798, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 798, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 798, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 798, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 798, 0b10010 + li x11, 0x00000000 + bne x11, x9, csr_fail + # mstateen3h + li x11, 0xa5a5a5a5 + csrrw x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrw x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xfc0b9409 + csrrw x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrs x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrs x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xba3459b6 + csrrs x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xa5a5a5a5 + csrrc x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0x5a5a5a5a + csrrc x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + li x11, 0xdd0370c3 + csrrc x9, 799, x11 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 799, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 799, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrwi x9, 799, 0b01011 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 799, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 799, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrsi x9, 799, 0b11000 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 799, 0b00101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 799, 0b11010 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrrci x9, 799, 0b10101 + li x11, 0x00000000 + bne x11, x9, csr_fail + csrr x9, 799 + li x11, 0x00000000 + bne x11, x9, csr_fail ################################################################################ # # Generated code ends... diff --git a/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/test.yaml b/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/test.yaml index df4094384b..b023884329 100644 --- a/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/test.yaml +++ b/cv32e40s/tests/programs/custom/cv32e40s_csr_access_test/test.yaml @@ -1,5 +1,7 @@ name: cv32e40s_csr_access_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +cflags: > + -mno-relax description: > CSR access test for the cv32e40s -llvm_cflags: -fno-integrated-as +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/cv32e40s_readonly_csr_access_test.S b/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/cv32e40s_readonly_csr_access_test.S index 1cd85774d8..4e0b03651e 100644 --- a/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/cv32e40s_readonly_csr_access_test.S +++ b/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/cv32e40s_readonly_csr_access_test.S @@ -122,7 +122,7 @@ main: csrrwi x0, 3858, 0x0a # illegal instruction: attempt to write RO CSR csrrc x5, 3858, x0 # not illegal - li x30, 0x00000014 + li x30, 0x00000015 bne x5, x30, fail # mipmid diff --git a/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/test.yaml b/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/test.yaml index d184ee20f9..fcc3052d94 100644 --- a/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/test.yaml +++ b/cv32e40s/tests/programs/custom/cv32e40s_readonly_csr_access_test/test.yaml @@ -2,3 +2,4 @@ name: cv32e40s_readonly_csr_access_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > CSR access test for RO CSRs of cv32e40s +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/data_bus_error/data_bus_error.c b/cv32e40s/tests/programs/custom/data_bus_error/data_bus_error.c index 45b8a203e2..a988e939f9 100644 --- a/cv32e40s/tests/programs/custom/data_bus_error/data_bus_error.c +++ b/cv32e40s/tests/programs/custom/data_bus_error/data_bus_error.c @@ -26,6 +26,7 @@ #include #include "corev_uvmt.h" + #define TEST_LOOPS 6 // Globals @@ -34,29 +35,64 @@ volatile uint32_t load_bus_fault_exp = 0; volatile uint32_t store_bus_fault_count = 0; volatile uint32_t store_bus_fault_exp = 0; volatile uint32_t error_word = 0x789a1234; +volatile uint32_t data_word; + + +__attribute__((naked)) void u_sw_irq_handler (void) { + __asm__ volatile (R"( + addi sp,sp,-64 + sw ra, 0(sp) + sw a0, 4(sp) + sw a1, 8(sp) + sw a2, 12(sp) + sw a3, 16(sp) + sw a4, 20(sp) + sw a5, 24(sp) + sw a6, 28(sp) + sw a7, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + csrr t3, mcause + andi t0, t3, 0x7FF # Get EXCCODE + li t1, 1 # EXCEPTION_INSN_ACCESS_FAULT + beq t0, t1, handle_insn_access_fault + li t1, 2 # EXCEPTION_ILLEGAL_INSN + beq t0, t1, handle_illegal_insn + li t1, 1024 # INTERRUPT_LOAD_BUS_FAULT + beq t0, t1, handle_data_load_bus_fault + li t1, 1025 # INTERRUPT_STORE_BUS_FAULT + beq t0, t1, handle_data_store_bus_fault + j m_software_irq_handler + )"); +} + -void handle_data_load_bus_fault() { - __asm__ __volatile__( - "la a0, load_bus_fault_count \n" - "lw a1, 0(a0) \n" - "addi a1,a1,1 \n" - "sw a1, 0(a0) \n" - "j nmi_end_handler_ret" : : : - ); +__attribute__((naked)) void handle_data_load_bus_fault() { + __asm__ __volatile__(R"( + la a0, load_bus_fault_count + lw a1, 0(a0) + addi a1,a1,1 + sw a1, 0(a0) + j end_handler_ret + )"); } -void handle_data_store_bus_fault() { - __asm__ __volatile__( - "la a0, store_bus_fault_count \n" - "lw a1, 0(a0) \n" - "addi a1,a1,1 \n" - "sw a1, 0(a0) \n" - "j nmi_end_handler_ret" : : : - ); +__attribute__((naked)) void handle_data_store_bus_fault() { + __asm__ volatile (R"( + la a0, store_bus_fault_count + lw a1, 0(a0) + addi a1,a1,1 + sw a1, 0(a0) + j end_handler_ret + )"); } int test_data_load_error() { - volatile uint32_t data_word; printf("Testing data load bus fault injection\n"); @@ -101,7 +137,6 @@ int test_data_load_error() { } int test_data_store_error() { - volatile uint32_t data_word; printf("Testing data store bus fault injection\n"); diff --git a/cv32e40s/tests/programs/custom/debug_priv_test/README.md b/cv32e40s/tests/programs/custom/debug_priv_test/README.md new file mode 100644 index 0000000000..8f0eaa0714 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_priv_test/README.md @@ -0,0 +1,3 @@ +Several smaller directed test-cases asserting proper execution between debug and user mode. + +Needs `CFG=pmp` for allowing U-mode to run. diff --git a/cv32e40s/tests/programs/custom/debug_priv_test/debug_priv_test.c b/cv32e40s/tests/programs/custom/debug_priv_test/debug_priv_test.c new file mode 100644 index 0000000000..55804e1f77 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_priv_test/debug_priv_test.c @@ -0,0 +1,258 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Several smaller directed test-cases asserting proper execution between debug and user mode. +** +******************************************************************************* +*/ + + +#include +#include +#include +#include "corev_uvmt.h" + + +// Global values to set test_cases for the assembly debug code, or write to global values which the .c code can read and assert + +// Written by assembly debug code to signal .c code that debug is exiting. +volatile uint8_t glb_debug_status = 0; +// Written by main code to set test case in assembly debug code +volatile uint8_t glb_expect_ebreaku_exc = 0; +// Written by main code to set test case in assembly debug code +volatile uint8_t glb_setmprv_test = 0; +// Written by main code to set test case in assembly debug code +volatile uint8_t glb_check_prv_test = 0; +// Written by main code to set test case in assembly debug code +volatile uint8_t glb_check_prv_test_2 = 0; +// Written by main code to set test case in assembly debug code +volatile uint8_t glb_unsupported_mode_test = 0; +// Written by main code to set test case in assembly debug code +volatile uint8_t glb_ebreaku_one_test = 0; +// Written by main code to set test case in assembly debug code +volatile uint8_t glb_check_previous_prv_test = 0; +// Written by assembly debug code. Asserts test case failure +volatile uint8_t glb_unsupported_check_failed = 0; +// Written by assembly debug code. Asserts test case failure +volatile uint8_t glb_ebreaku_one_check = 0; +// Written by assembly debug code. Contains dcsr register value +volatile uint32_t glb_check_prv_test_val = 0; +// Written by assembly debug code. Contains dcsr register value +volatile uint32_t glb_dcsr_register = 0; + +// global variable written while in trap handler. Used to check mcause and mstatus registers in assertions +volatile uint32_t wmcause, wmstatus; +// standard value for the mstatus register +#define MSTATUS_STD_VAL 0x1800 +// mstatus.MPRV bit +#define MPRV_BIT 17 +// Debug define +#define DEBUG_REQ_CONTROL_REG *((volatile uint32_t *) (CV_VP_DEBUG_CONTROL_BASE)) +// external assembly symbol which defines a generous region for user mode execution +extern volatile void setup_pmp(); +// external assembly symbol which sets core into user mode. +extern volatile void set_u_mode(); +// mstatus.MPP bit-field +int MPP_FIELD [2] = {11, 12}; +// dcsr.prv bit-field +int PRV_FIELD [2] = {0, 1}; + +// declaration of the assert function +static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { + if (actual != expect) { + printf(msg); + printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); + exit(EXIT_FAILURE); + } +} + +/* +Retuns specific bit-field from [bit_indx_low : bit_indx_high] in register x +*/ +unsigned int get_field(unsigned int x, int bit_indx_low, int bit_indx_high){ + int field = ( 1 << ( (bit_indx_high - bit_indx_low) + 1) ) - 1; + x = (x & (field << bit_indx_low) ) >> bit_indx_low; + return x; +} + + +/* +Checks the mepc for compressed instructions and increments appropriately +*/ +void increment_mepc(void){ + volatile unsigned int insn, mepc; + + __asm__ volatile("csrrs %0, mepc, x0" : "=r"(mepc)); // read the mepc + __asm__ volatile("lw %0, 0(%1)" : "=r"(insn) : "r"(mepc)); // read the contents of the mepc pc. + if ((insn & 0x3) == 0x3) { // check for compressed instruction before increment. + mepc += 4; + } else { + mepc += 2; + } + __asm__ volatile("csrrw x0, mepc, %0" :: "r"(mepc)); // write to the mepc +} + + +// Rewritten interrupt handler +__attribute__ ((interrupt ("machine"))) +void u_sw_irq_handler(void) { + + __asm__ volatile("csrrs %0, mcause, x0" : "=r"(wmcause)); + __asm__ volatile("csrrs %0, mstatus, x0" : "=r"(wmstatus)); + __asm__ volatile("csrrw x0, mstatus, %0" :: "r"(MSTATUS_STD_VAL)); // set machine mode + increment_mepc(); +} + +// Declaration of the debug struct +typedef union { + struct { + unsigned int start_delay : 15; // 14: 0 + unsigned int rand_start_delay : 1; // 15 + unsigned int pulse_width : 13; // 28:16 + unsigned int rand_pulse_width : 1; // 29 + unsigned int pulse_mode : 1; // 30 0 = level, 1 = pulse + unsigned int value : 1; // 31 + } fields; + unsigned int bits; +} debug_req_control_t; + +/* +When called it starts debug_mode +*/ +void run_debug_mode(void) { + // debug control struct + debug_req_control_t debug_req_control; + debug_req_control = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, //PULSE Mode + .fields.rand_pulse_width = 0, + .fields.pulse_width = 5,// FIXME: BUG: one clock pulse cause core to lock up + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + // this will initiate debug mode + DEBUG_REQ_CONTROL_REG = debug_req_control.bits; + // waits for debug to finish + while(glb_debug_status != 1){ + ; + } + // resets the debug status bit + glb_debug_status = 0; +} + +int main(void){// TODO: test will failed until issue #278 in core-v-verif/cv32e40s is fixed + setup_pmp(); + + + + // Test start: + /* + Have dcsr.ebreaku=0, be in U-mode, execute ebreak, ensure "normal" ebreak behavior and no debug entry. + */ + assert_or_die(glb_debug_status, 0, "Error: Core was in debug mode before test start!\n"); + set_u_mode(); + asm volatile("ebreak"); + assert_or_die(glb_debug_status, 0, "Error: core unexpectedly entered debug mode!\n"); + assert_or_die(wmcause, 0x3, "Error: Illegal 'ebreak' did not trigger breakpoint exception!\n"); + + + + // Test start: + /* + Transition out of D-mode (dret) into U-mode, while mstatus.mprv=1, ensure that when execution continues outside D-mode that mstatus.mprv=0. + */ + glb_setmprv_test = 1; // flag the MRPRV-test for the debug module. + run_debug_mode(); + asm volatile("ecall"); + int mprvfield = get_field(wmstatus, MPRV_BIT, MPRV_BIT); + assert_or_die(mprvfield, 0x0, "Error: MPRV did not change to 0 after Debug --> User mode change! "); // check that MPRV = 0 after debug exit. + glb_setmprv_test = 0; + + + + // Test start: + /* + Transition out of D-mode, ensure that executions starts in the same privilege mode as was indicated in dcsr.prv (dcsr.prv=M and dcsr.prv=U). + */ + // First check machine mode. + glb_check_prv_test = 1; + run_debug_mode(); + asm volatile("ecall"); + uint32_t check_MPP_bit = get_field(wmstatus, MPP_FIELD[0], MPP_FIELD[1]); + assert_or_die(check_MPP_bit, 0x3, "Error: previous privilege mode did not match the one set in dcsr.prv before exiting debug mode!\n"); + uint32_t check_prv_bit = get_field(glb_check_prv_test_val, PRV_FIELD[0], PRV_FIELD[1]); + assert_or_die(check_MPP_bit, check_prv_bit, "Error: previous privilege mode did not match the one set in dcsr.prv before exiting debug mode!\n"); + glb_check_prv_test = 0; + + // Now check user mode. + glb_check_prv_test_2 = 1; + run_debug_mode(); + asm volatile("ecall"); + check_MPP_bit = get_field(wmstatus, MPP_FIELD[0], MPP_FIELD[1]); + assert_or_die(check_MPP_bit, 0x0, "Error: previous privilege mode did not match the one set in dcsr.prv before exiting debug mode!\n"); + check_prv_bit = get_field(glb_check_prv_test_val, PRV_FIELD[0], PRV_FIELD[1]); + assert_or_die(check_MPP_bit, check_prv_bit, "Error: previous privilege mode did not match the one set in dcsr.prv before exiting debug mode!\n"); + glb_check_prv_test_2 = 0; + + + + + // Test start: + /* + Write unsupported modes to dcsr.prv, ensure the value read back is unchanged from the previous value. + */ + glb_unsupported_mode_test = 1; + run_debug_mode(); + assert_or_die(glb_unsupported_check_failed, 0, "Error: unsupported privilege_mode was successfully written and then read back from dcsr.prv!\n"); + glb_unsupported_mode_test = 0; + + + + // TEST WILL FAIL UNTIL dcsr.ebreaku BIT IS IMPLEMENTED! + // TODO: comment the test back in when the above is resolved. + // Test start: + /* + Have dcsr.ebreaku=1, be in U-mode, execute ebreak, ensure debug entry happens instead of "normal" ebreak behavior. + */ + /* + glb_ebreaku_one_test = 1; // make debug mode set dcsr.ebreaku = 0 + run_debug_mode(); + glb_ebreaku_one_test = 0; // shut off flag + glb_expect_ebreaku_exc = 1; // make debug aware we're coming from u-mode ebreak + asm volatile("ebreak"); + assert_or_die(glb_ebreaku_one_check , 1, "Error: User mode could not enter Debug mode, even though dcsr.ebreaku == 0 !"); + glb_expect_ebreaku_exc = 0; + */ + + + // Test start: + /* + Transition into D-mode from M-mode and U-mode, ensure dcsr.prv contains the privilege mode that was running before D-mode. + */ + // First check machine mode + asm volatile("ecall"); // trap handler will force machine mode + glb_check_previous_prv_test = 1; + run_debug_mode(); + int privilege_mode = get_field(glb_dcsr_register, PRV_FIELD[0], PRV_FIELD[1]); + assert_or_die(privilege_mode, 0x3, "Error: dcsr.prv does not match previous privilege mode after entering debug mode!\n"); + + // Now check user mode + set_u_mode(); + run_debug_mode(); + privilege_mode = get_field(glb_dcsr_register, PRV_FIELD[0], PRV_FIELD[1]); + assert_or_die(privilege_mode, 0x0, "Error: dcsr.prv does not match previous privilege mode after entering debug mode!\n"); + glb_check_previous_prv_test = 0; + + + return(EXIT_SUCCESS); +} diff --git a/cv32e40s/tests/programs/custom/debug_priv_test/debugger.S b/cv32e40s/tests/programs/custom/debug_priv_test/debugger.S new file mode 100644 index 0000000000..60a2a69b3b --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_priv_test/debugger.S @@ -0,0 +1,232 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly debug code which executes different test-cases based on global variables acting as flags. +** +******************************************************************************* +*/ + +#include "corev_uvmt.h" + +.section .debugger, "ax" +// Global debugger_start symbol +.global _debugger_start +// Written by main code to set test case in assembly debug code +.global glb_debug_status +// Written by main code to set test case in assembly debug code +.global glb_expect_ebreaku_exc +// Written by main code to set test case in assembly debug code +.global glb_setmprv_test +// Written by main code to set test case in assembly debug code +.global glb_check_prv_test +// Written by main code to set test case in assembly debug code +.global glb_check_prv_test_2 +// Written by main code to set test case in assembly debug code +.global glb_unsupported_mode_test +// Written by main code to set test case in assembly debug code +.global glb_ebreaku_one_test +// Written by main code to set test case in assembly debug code +.global glb_check_previous_prv_test +// Written by assembly debug code. Asserts test case failure +.global glb_unsupported_check_failed +// Written by assembly debug code. Asserts test case failure +.global glb_ebreaku_one_check +// Written by assembly debug code. Contains dcsr register value +.global glb_check_prv_test_val +// Written by assembly debug code. Contains dcsr register value +.global glb_dcsr_register + +// dcsr.ebreaku bit +#define EBREAKU_BIT 0x1000 + +/* +Starts executing when 'DEBUG_REQ_CONTROL_REG = debug_req_control.bits' is set in 'debug_priv_test.c'. +Checks and executes a number of different flags associated with different test-cases and debug_mode behavior. +*/ +_debugger_start: + addi sp,sp,-52 + sw ra, 0(sp) + sw s0, 4(sp) + sw s1, 8(sp) + sw s2, 12(sp) + sw s3, 16(sp) + sw s4, 20(sp) + sw s5, 24(sp) + sw s6, 28(sp) + sw s7, 32(sp) + sw s8, 36(sp) + sw s9, 40(sp) + sw s10, 44(sp) + sw s11, 48(sp) + + la t0, glb_setmprv_test + lw t0, 0(t0) + bnez t0, MPRV_test + + la t0, glb_check_prv_test + lw t0, 0(t0) + bnez t0, Check_prv_test + + la t0, glb_check_prv_test_2 + lw t0, 0(t0) + bnez t0, Check_prv_test_2 + + la t0, glb_unsupported_mode_test + lw t0, 0(t0) + bnez t0, Check_unsupported_modes + + la t0, glb_ebreaku_one_test + lw t0, 0(t0) + bnez t0, Set_ebreaku_bit + + la t0, glb_expect_ebreaku_exc + lw t0, 0(t0) + bnez t0, Successfull_user_mode + + la t0, glb_check_previous_prv_test + lw t0, 0(t0) + bnez t0, Check_previous_privilege_test + + j end_debugger + + +end_debugger: + // sets the glb_debug_status value high to signal 'debug_priv_test.c' that the debugger is finished executing. + la t2, glb_debug_status + lb t1, 0(t2) + addi t1, t1, 1 + sb t1, 0(t2) + + lw ra, 0(sp) + lw s0, 4(sp) + lw s1, 8(sp) + lw s2, 12(sp) + lw s3, 16(sp) + lw s4, 20(sp) + lw s5, 24(sp) + lw s6, 28(sp) + lw s7, 32(sp) + lw s8, 36(sp) + lw s9, 40(sp) + lw s10, 44(sp) + lw s11, 48(sp) + addi sp,sp,52 + dret + + + +/* +Transition out of D-mode (dret) into U-mode, while mstatus.mprv=1, ensure that when execution continues outside D-mode that mstatus.mprv=0. +*/ +MPRV_test: + li t0, 0x3 + csrrc x0, dcsr, t0 // load U-mode into dcsr.prv register. + li t0, 1 + slli t0, t0, 17 + csrrs x0, mstatus, t0 // set MPRV=1 + j end_debugger + + +/* +Transition out of D-mode, ensure that executions starts in the same privilege mode as was indicated in dcsr.prv (dcsr.prv=M and dcsr.prv=U). +*/ +Check_prv_test: + la t0, glb_check_prv_test_val + csrrs t1, dcsr, x0 + sw t1, 0(t0) + j end_debugger + + +/* +Transition out of D-mode, ensure that executions starts in the same privilege mode as was indicated in dcsr.prv (dcsr.prv=M and dcsr.prv=U). +*/ +Check_prv_test_2: + li t0, 0x3 + csrrc x0, dcsr, t0 // load U-mode into dcsr.prv register. + + la t0, glb_check_prv_test_val + csrrs t1, dcsr, x0 + sw t1, 0(t0) + j end_debugger + + + +/* +Write unsupported modes to dcsr.prv, ensure the value read back is unchanged from the previous value. +*/ +Check_unsupported_modes: // TODO: sim this test again. + li t0, 0x3 + csrrs x0, dcsr, t0 // preload supported M-mode to get a reference + + // Check S-mode + li t1, 0x1 + csrrs t2, dcsr, x0 + and t2, t2, t1 + csrrw x0, dcsr, t1 + + csrrs t2, dcsr, x0 + and t2, t2, t0 + bne t2, t0, Unsupported_check_failed + + // Check R-mode + li t1, 0x2 + csrrs t2, dcsr, x0 + and t2, t2, t1 + csrrw x0, dcsr, t1 + + csrrs t2, dcsr, x0 + and t2, t2, t0 + bne t2, t0, Unsupported_check_failed + + j end_debugger + + +/* +Write unsupported modes to dcsr.prv, ensure the value read back is unchanged from the previous value. +*/ +Unsupported_check_failed: // if unsupported mode is written to dcsr.prv go here + la t0, glb_unsupported_check_failed + li t1, 1 + sw t1, 0(t0) + j end_debugger + + + +/* +Have dcsr.ebreaku=1, be in U-mode, execute ebreak, ensure debug entry happens instead of "normal" ebreak behavior. +*/ +Set_ebreaku_bit: + li t0, EBREAKU_BIT + csrrs x0, dcsr, t0 + j end_debugger + + + +/* +Have dcsr.ebreaku=1, be in U-mode, execute ebreak, ensure debug entry happens instead of "normal" ebreak behavior. +*/ +Successfull_user_mode: + la t0, glb_ebreaku_one_check + li t1, 1 + sw t1, 0(t0) + j end_debugger + + + +/* +Transition into D-mode from M-mode and U-mode, ensure dcsr.prv contains the privilege mode that was running before D-mode. +*/ +Check_previous_privilege_test: + la t0, glb_dcsr_register + csrrs t1, dcsr, x0 + sw t1, 0(t0) + j end_debugger diff --git a/cv32e40s/tests/programs/custom/debug_priv_test/helpers.S b/cv32e40s/tests/programs/custom/debug_priv_test/helpers.S new file mode 100644 index 0000000000..869485a825 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_priv_test/helpers.S @@ -0,0 +1,38 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly helper functions for the 'debug_priv_test.c' file. +** +******************************************************************************* +*/ + +.section .text + +.global setup_pmp +.global set_u_mode + +setup_pmp: + // Set pmp addr to 0xFFFF_FFFF + li t0, 0xFFFFFFFF + csrrw x0, pmpaddr0, t0 + + // Set pmp region TOR and read/write/execute + li t0, ((1 << 3) + (7 << 0)) + csrrw x0, pmpcfg0, t0 + + ret + +set_u_mode: // puts the core in usermode. + li t0, 0x1800 // load as bitmask + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrw x0, mepc, ra + mret \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/debug_priv_test/test.yaml b/cv32e40s/tests/programs/custom/debug_priv_test/test.yaml new file mode 100644 index 0000000000..454ed8e192 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_priv_test/test.yaml @@ -0,0 +1,8 @@ +# Test definition YAML for test + +# Debug directed test +name: debug_priv_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +program: debug_priv_tests +description: > + privilege modes and debug access / behaviour diff --git a/cv32e40s/tests/programs/custom/debug_test/debug_test.c b/cv32e40s/tests/programs/custom/debug_test/debug_test.c index be2ff11e2e..b9ed253604 100644 --- a/cv32e40s/tests/programs/custom/debug_test/debug_test.c +++ b/cv32e40s/tests/programs/custom/debug_test/debug_test.c @@ -22,6 +22,7 @@ #include #include +#include #include "corev_uvmt.h" volatile int glb_hart_status = 0; // Written by main code only, read by debug code @@ -247,14 +248,12 @@ int main(int argc, char *argv[]) printf("------------------------\n"); printf(" Test2.2: check access to Trigger registers\n"); // Writes are ignored - temp = 0xFFFFFFFF; + temp = 0xFFFFFFFF; //TODO:MT should these be writes? __asm__ volatile("csrw 0x7a0, %0" : "=r"(temp)); // Trigger TSELECT __asm__ volatile("csrw 0x7a1, %0" : "=r"(temp)); // Trigger TDATA1 __asm__ volatile("csrw 0x7a2, %0" : "=r"(temp)); // Trigger TDATA2 __asm__ volatile("csrw 0x7a3, %0" : "=r"(temp)); // Trigger TDATA3 __asm__ volatile("csrw 0x7a4, %0" : "=r"(temp)); // Trigger TINFO - __asm__ volatile("csrw 0x7a8, %0" : "=r"(temp)); // Trigger MCONTEXT - __asm__ volatile("csrw 0x7aa, %0" : "=r"(temp)); // Trigger SCONTEXT // Read default value __asm__ volatile("csrr %0, 0x7a0" : "=r"(temp)); // Trigger TSELECT @@ -277,13 +276,6 @@ int main(int argc, char *argv[]) // tmatch = 1<<2 if(temp != 1<<2){printf("ERROR: TINFO Read %d \n",temp);TEST_FAILED;} - __asm__ volatile("csrr %0, 0x7a8" : "=r"(temp)); // Trigger MCONTEXT - if(temp != 0x0){printf("ERROR: MCONTEXT Read\n");TEST_FAILED;} - - __asm__ volatile("csrr %0, 0x7aa" : "=r"(temp)); // Trigger SCONTEXT - if(temp != 0x0){printf("ERROR: SCONTEXT Read\n");TEST_FAILED;} - - // Do not expect or allow any more illegal instructions @@ -293,7 +285,7 @@ int main(int argc, char *argv[]) }; if(mstatus_cmp.bits != mstatus.bits) {printf("ERROR: init mstatus mismatch exp=%x val=%x\n", mstatus_cmp.bits, mstatus.bits); TEST_FAILED;} - + //TODO:MT are these switched up? printf("------------------------\n"); printf(" Test3.1: check hart ebreak executes ebreak handler but does not execute debugger code\n"); glb_expect_ebreak_handler = 1; @@ -313,7 +305,7 @@ int main(int argc, char *argv[]) .fields.value = 1, .fields.pulse_mode = 1, //PULSE Mode .fields.rand_pulse_width = 0, - .fields.pulse_width = 5,// FIXME: BUG: one clock pulse cause core to lock up + .fields.pulse_width = 5,// TODO:MT determine pulse width with non-sticky debug_req .fields.rand_start_delay = 0, .fields.start_delay = 200 }; diff --git a/cv32e40s/tests/programs/custom/debug_test/debugger.S b/cv32e40s/tests/programs/custom/debug_test/debugger.S index 9681fcb0e9..67fae0fb25 100644 --- a/cv32e40s/tests/programs/custom/debug_test/debugger.S +++ b/cv32e40s/tests/programs/custom/debug_test/debugger.S @@ -501,10 +501,6 @@ _debugger_csr: bne x0,t2,_debugger_fail csrr t2,tdata3 bne x0,t2,_debugger_fail - csrr t2,0x7a8 //mcontext - bne x0,t2,_debugger_fail - csrr t2,0x7aa //scontext - bne x0,t2,_debugger_fail j _debugger_end diff --git a/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c b/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c new file mode 100644 index 0000000000..6795dad584 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c @@ -0,0 +1,3812 @@ +// +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran +// +// Debug directed tests +// +// Requires: number of triggers >= 1 +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 19 +// Start at 1 (ignore dummy test that is only used for env sanity checking during dev.) +#define START_TEST_NUM 1 +// Abort test at first self-check fail, useful for debugging. +#define ABORT_ON_ERROR_IMMEDIATE 0 + +// Addresses of VP interrupt control registers +#define TIMER_REG_ADDR ((volatile uint32_t * volatile) (CV_VP_INTR_TIMER_BASE)) +#define TIMER_VAL_ADDR ((volatile uint32_t * volatile) (CV_VP_INTR_TIMER_BASE + 4)) +#define DEBUG_REQ_CONTROL_REG *((volatile uint32_t * volatile) (CV_VP_DEBUG_CONTROL_BASE)) + +#define MARCHID_CV32E40X 0x14 +#define MARCHID_CV32E40S 0x15 + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + +// --------------------------------------------------------------- +// Type definitions +// --------------------------------------------------------------- + + +// Verbosity levels (Akin to the uvm verbosity concept) +typedef enum { + V_OFF = 0, + V_LOW = 1, + V_MEDIUM = 2, + V_HIGH = 3, + V_DEBUG = 4 +} verbosity_t; + +typedef enum { + MCAUSE_ACCESS_FAULT = 1, + MCAUSE_ILLEGAL = 2, + MCAUSE_BREAKPT = 3, + MCAUSE_LOAD_FAULT = 5, + MCAUSE_STORE_FAULT = 7, + MCAUSE_UMODE_ECALL = 8, + MCAUSE_MMODE_ECALL = 11, + MCAUSE_INSTR_BUS_FAULT = 24, + MCAUSE_CHK_FAULT = 25, +} mcause_exception_status_t; + +typedef enum { + DCAUSE_EBREAK = 1, + DCAUSE_TRIGGER = 2, + DCAUSE_HALTREQ = 3, + DCAUSE_STEP = 4, + DCAUSE_RESETHALTREQ = 5, + DCAUSE_HALTGROUP = 6, +} dcsr_cause_t; + +typedef enum { + MODE_USER = 0, + MODE_SUPERVISOR = 1, + MODE_RESERVED = 2, + MODE_MACHINE = 3 +} mode_t; + +typedef enum { + PMPMODE_OFF = 0, + PMPMODE_TOR = 1, + PMPMODE_NA4 = 2, + PMPMODE_NAPOT = 3 +} pmp_mode_t; + +typedef union { + struct { + volatile uint32_t r : 1; + volatile uint32_t w : 1; + volatile uint32_t x : 1; + volatile uint32_t a : 1; + volatile uint32_t reserved_6_5 : 2; + volatile uint32_t l : 1; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 8; +} __attribute__((packed)) pmpsubcfg_t; + +typedef union { + struct { + volatile uint32_t cfg : 8; + } __attribute__((packed)) volatile reg_idx[4]; + volatile uint32_t raw : 32; +} __attribute__((packed)) pmpcfg_t; + +typedef union { + struct { + volatile uint32_t mml : 1; + volatile uint32_t mmwp : 1; + volatile uint32_t rlb : 1; + volatile uint32_t reserved_31_3 : 29; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} mseccfg_t; + +typedef union { + struct { + volatile uint32_t shv : 1; + volatile uint32_t priv : 2; + volatile uint32_t level : 8; + volatile uint32_t id : 11; + volatile uint32_t irq : 1; + volatile uint32_t reserved_31_22 : 9; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) clic_t ; + +typedef union { + struct { + volatile uint32_t irq_0 : 1; + volatile uint32_t irq_1 : 1; + volatile uint32_t irq_2 : 1; + volatile uint32_t irq_3 : 1; + volatile uint32_t irq_4 : 1; + volatile uint32_t irq_5 : 1; + volatile uint32_t irq_6 : 1; + volatile uint32_t irq_7 : 1; + volatile uint32_t irq_8 : 1; + volatile uint32_t irq_9 : 1; + volatile uint32_t irq_10 : 1; + volatile uint32_t irq_11 : 1; + volatile uint32_t irq_12 : 1; + volatile uint32_t irq_13 : 1; + volatile uint32_t irq_14 : 1; + volatile uint32_t irq_15 : 1; + volatile uint32_t irq_16 : 1; + volatile uint32_t irq_17 : 1; + volatile uint32_t irq_18 : 1; + volatile uint32_t irq_19 : 1; + volatile uint32_t irq_20 : 1; + volatile uint32_t irq_21 : 1; + volatile uint32_t irq_22 : 1; + volatile uint32_t irq_23 : 1; + volatile uint32_t irq_24 : 1; + volatile uint32_t irq_25 : 1; + volatile uint32_t irq_26 : 1; + volatile uint32_t irq_27 : 1; + volatile uint32_t irq_28 : 1; + volatile uint32_t irq_29 : 1; + volatile uint32_t irq_30 : 1; + volatile uint32_t irq_31 : 1; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) clint_t; + +typedef union { + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_30_12 : 19; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clint; + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_15_12 : 4; + volatile uint32_t mpil : 8; + volatile uint32_t res_26_24 : 3; + volatile uint32_t mpie : 1; + volatile uint32_t mpp : 2; + volatile uint32_t minhv : 1; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clic; + volatile uint32_t raw : 32; +} __attribute__((packed)) mcause_t; + +typedef union { + struct { + volatile uint32_t data : 27; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) tdata1_t; + +typedef union { + struct { + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_5_5 : 1; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t chain : 1; + volatile uint32_t action : 4; + volatile uint32_t sizelo : 2; + volatile uint32_t timing : 1; + volatile uint32_t select : 1; + volatile uint32_t hit : 1; + volatile uint32_t maskmax : 6; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mcontrol_t; + +typedef union { + struct { + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_5_5 : 1; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t chain : 1; + volatile uint32_t action : 4; + volatile uint32_t size : 4; + volatile uint32_t timing : 1; + volatile uint32_t select : 1; + volatile uint32_t hit : 1; + volatile uint32_t vu : 1; + volatile uint32_t vs : 1; + volatile uint32_t res_26_25: 2; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mcontrol6_t; + +typedef union { + struct { + volatile uint32_t action : 6; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_8_8 : 1; + volatile uint32_t m : 1; + volatile uint32_t res_10_10 : 1; + volatile uint32_t vu : 1; + volatile uint32_t vs : 1; + volatile uint32_t res_25_13 : 13; + volatile uint32_t hit : 1; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) etrigger_t; + +typedef union { + struct { + volatile uint32_t info : 16; + volatile uint32_t res_23_16 : 8; + volatile uint32_t version : 8; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) tinfo_t; + +typedef union { + struct { + volatile uint32_t uie : 1; // 0 + volatile uint32_t sie : 1; // 1 + volatile uint32_t wpri : 1; // 2 + volatile uint32_t mie : 1; // 3 + volatile uint32_t upie : 1; // 4 + volatile uint32_t spie : 1; // 5 + volatile uint32_t wpri0 : 1; // 6 + volatile uint32_t mpie : 1; // 7 + volatile uint32_t spp : 1; // 8 + volatile uint32_t wpri1 : 2; // 10: 9 + volatile uint32_t mpp : 2; // 12:11 + volatile uint32_t fs : 2; // 14:13 + volatile uint32_t xs : 2; // 16:15 + volatile uint32_t mprv : 1; // 17 + volatile uint32_t sum : 1; // 18 + volatile uint32_t mxr : 1; // 19 + volatile uint32_t tvm : 1; // 20 + volatile uint32_t tw : 1; // 21 + volatile uint32_t tsr : 1; // 22 + volatile uint32_t wpri3 : 8; // 30:23 + volatile uint32_t sd : 1; // 31 + } volatile clint; + volatile uint32_t raw; +} __attribute__((packed)) mstatus_t; + +typedef union { + struct { + volatile uint32_t start_delay : 15; // 14: 0 + volatile uint32_t rand_start_delay : 1; // 15 + volatile uint32_t pulse_width : 13; // 28:16 + volatile uint32_t rand_pulse_width : 1; // 29 + volatile uint32_t pulse_mode : 1; // 30 0 = level, 1 = pulse + volatile uint32_t value : 1; // 31 + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) debug_req_control_t; + +typedef union { + struct { + volatile uint32_t prv : 2; // 1:0 WARL (0x0, 0x3) PRV. Returns the privilege mode before debug entry. + volatile uint32_t step : 1; // 2 RW STEP. Set to enable single stepping. + volatile uint32_t nmip : 1; // 3 R NMIP. If set, an NMI is pending + volatile uint32_t mprven : 1; // 4 WARL (0x1) MPRVEN. Hardwired to 1. + volatile uint32_t res_5_5 : 1; // 5 WARL (0x0) V. Hardwired to 0. + volatile uint32_t cause : 3; // 8:6 R CAUSE. Return the cause of debug entry. + volatile uint32_t stoptime : 1; // 9 WARL (0x0) STOPTIME. Hardwired to 0. + volatile uint32_t stopcount : 1; // 10 WARL STOPCOUNT. + volatile uint32_t stepie : 1; // 11 WARL STEPIE. Set to enable interrupts during single stepping. + volatile uint32_t ebreaku : 1; // 12 WARL EBREAKU. Set to enter debug mode on ebreak during user mode. + volatile uint32_t ebreaks : 1; // 13 WARL (0x0) EBREAKS. Hardwired to 0. + volatile uint32_t res_14_14 : 1; // 14 WARL (0x0) Hardwired to 0. + volatile uint32_t ebreakm : 1; // 15 RW EBREAKM. Set to enter debug mode on ebreak during machine mode. + volatile uint32_t ebreakvu : 1; // 16 WARL (0x0) EBREAKVU. Hardwired to 0. + volatile uint32_t ebreakvs : 1; // 17 WARL (0x0) EBREAKVS. Hardwired to 0 + volatile uint32_t res_27_18 : 10; // 27:18 WARL (0x0) Reserved + volatile uint32_t xdebugver : 4; // 31:28 R (0x4) XDEBUGVER. External debug support exists as described in [RISC-V-DEBUG]. + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) dcsr_t; + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- + +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +volatile uint32_t * volatile g_handler_triggered; +volatile uint32_t * volatile g_illegal_fail; +volatile uint32_t * volatile g_ebreak_fail; +volatile uint32_t * volatile g_expect_illegal; +volatile uint32_t * volatile g_expect_ebreak; +volatile uint32_t * volatile g_expect_dpc; +volatile uint32_t * volatile g_debug_status; +volatile uint32_t * volatile g_debug_status_prev; +volatile uint32_t * volatile g_debug_test_num; +volatile uint32_t * volatile g_minstret_cnt; +volatile uint32_t * volatile g_mcycle_cnt; +volatile uint32_t * volatile g_single_step_status; +volatile uint32_t * volatile g_single_step_status_prev; +volatile uint32_t * volatile g_single_step_cnt; +volatile uint32_t * volatile g_previous_dpc; +volatile uint32_t * volatile g_expect_irq; +volatile uint32_t * volatile g_unexpected_irq; +volatile uint32_t * volatile g_trigger_matched; +volatile uint32_t * volatile g_has_clic; +volatile uint32_t * volatile g_single_step_unspec_err; + +extern volatile uint32_t *trigger_loc; +extern volatile uint32_t *trigger_loc_dbg; +extern volatile uint32_t *trigger_exit; +extern volatile uint32_t mtvt_table; + +// Message strings for use in assembly printf +const volatile char * const volatile entered_exc_handler_msg = "Entered handler"; +const volatile char * const volatile entered_dbg_msg = "Entered debug"; +const volatile char * const volatile ebreak_msg = "Ebreak\n"; +const volatile char * const volatile dbg_exception = "Exception occurred in debug\n"; + +const volatile char * const volatile test_str = "Test number = %0d\n"; +const volatile char * const volatile test_status_msg = "Test status = %0d\n"; +const volatile char * const volatile debug_exit_msg = "Exiting debug, test_num = %0d\n"; + +// --------------------------------------------------------------- +// Entry and exit locations for debug +// --------------------------------------------------------------- +void _debugger_start(void) __attribute__((section(".debugger"))); +void _debugger_restore_stack(void) __attribute__((section(".debugger"))); +void _debugger_end(void) __attribute__((section(".debugger"))); + +// --------------------------------------------------------------- +// Interrupt/Exception handler related functions +// --------------------------------------------------------------- +void u_sw_irq_handler(void) __attribute__((naked)); +void check_irq_handler(void); +void u_sw_irq_handler_default(void); +void m_fast14_irq_handler(void) __attribute__((naked)); +// Mtvt table implementation +void mtvt_code(void) __attribute__((naked)); + +// Debug exceptions +void _debugger_exception(void) __attribute__((section(".debugger_exception"))); +void debug_exception_handler(void) __attribute__((section(".debugger_exception"), __noinline__)); + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t dummy(uint32_t index, uint8_t report_name); +uint32_t debug_csr_rw(uint32_t index, uint8_t report_name); +uint32_t trigger_default_val(uint32_t index, uint8_t report_name); +uint32_t ebreak_behavior_m_mode(uint32_t index, uint8_t report_name); +uint32_t request_hw_debugger(uint32_t index, uint8_t report_name); +uint32_t request_ebreak_3x(uint32_t index, uint8_t report_name); +uint32_t csr_access_default_val(uint32_t index, uint8_t report_name); +uint32_t mmode_ebreakm_ebreak_executes_debug_code(uint32_t index, uint8_t report_name); +uint32_t illegal_csr_in_dmode(uint32_t index, uint8_t report_name); +uint32_t ecall_in_dmode(uint32_t index, uint8_t report_name); +uint32_t mret_in_dmode(uint32_t index, uint8_t report_name); +uint32_t exception_enters_debug_mode(uint32_t index, uint8_t report_name); +uint32_t dret_in_mmode(uint32_t index, uint8_t report_name); +uint32_t wfi_before_dmode(uint32_t index, uint8_t report_name); +uint32_t check_irq(uint32_t index, uint8_t report_name); +uint32_t check_stopcnt_bits(uint32_t index, uint8_t report_name); +uint32_t single_step(uint32_t index, uint8_t report_name); +uint32_t mprv_dret_to_umode(uint32_t index, uint8_t report_name); +uint32_t cover_known_iss_mismatches(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Prototypes for functions that are test specific and +// perform the debug part of specific tests. +// --------------------------------------------------------------- +void request_hw_debugger_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void request_ebreak_3x_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void mmode_ebreakm_ebreak_executes_debug_code_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void illegal_csr_in_dmode_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void ecall_in_dmode_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void mret_in_dmode_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void exception_enters_debug_mode_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void wfi_before_dmode_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void check_stopcnt_bits_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_trigger_setup_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_stepie_enable_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_stepie_disable_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_c_ebreak_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_ebreak_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_c_ebreak_exception_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_ebreak_exception_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void csr_access_default_val_dbg(void) __attribute__((section(".debugger"), __noinline__)); +void single_step_basic_dbg(void) __attribute__((section(".debugger"), __noinline__)); + +// The following could also be placed in the debug region, but there is simply no space +// unless we go about changing the core-v-verif memory map +void single_step_trigger_entry_dbg(void) __attribute__((__noinline__)); +void cover_known_iss_mismatches_dbg(void) __attribute__((__noinline__)); +void single_step_enable_dbg(void) __attribute__((__noinline__)); +void single_step_disable_dbg(void) __attribute__((__noinline__)); +void mprv_dret_to_umode_dbg(void) __attribute__((__noinline__)); +void exception_status_dbg(void) __attribute__((__noinline__)); +void ebreakm_set_dbg(void); + +// --------------------------------------------------------------- +// Single step test code (non-debug section +// --------------------------------------------------------------- +void single_step_code(void); + + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +void print_tdata1(verbosity_t verbosity, volatile tdata1_t * volatile tdata1); +void set_dpc(volatile uint32_t dpc) __attribute__((__noinline__)); +void increment_dpc(volatile uint32_t incr_val); +void increment_mepc(volatile uint32_t incr_val); +void set_debug_status(volatile uint32_t status); +void set_single_step_status(volatile uint32_t status); +void set_mseccfg(mseccfg_t mseccfg); +void set_pmpcfg(pmpsubcfg_t pmpcfg, uint32_t reg_no); +uint32_t set_val(uint32_t * ptr, uint32_t val); +uint32_t incr_val(uint32_t * ptr); +uint32_t has_pmp_configured(void); + +// Single step test related +void single_step_fail(uint32_t cause); +int get_single_step_result(uint32_t res); +void print_single_step_status(void); +void increment_single_step_status(void); + +// IRQ related +uint32_t detect_irq_mode(void); +void setup_clic(void); +void assert_irq(void); +void deassert_irq(void); +void wait_irq(void); +void clint_mie_enable(uint8_t irq_num); +void clint_mie_disable(uint8_t irq_num); + +// Debug specific helper code +void disable_debug_req(void) __attribute__((section(".debugger"))); +uint32_t get_dcsr_cause(void) __attribute__((section(".debugger"),__noinline__)); + + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(volatile uint32_t test_no, volatile uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...) __attribute((__noinline__)); + +/* + * vp_assert_irq + * + * Notify clic_interrupt_agent vp to assert given + * clic interrupt + */ +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + g_handler_triggered = calloc(1, sizeof(uint32_t)); + g_illegal_fail = calloc(1, sizeof(uint32_t)); + g_ebreak_fail = calloc(1, sizeof(uint32_t)); + g_expect_illegal = calloc(1, sizeof(uint32_t)); + g_expect_ebreak = calloc(1, sizeof(uint32_t)); + g_expect_dpc = calloc(1, sizeof(uint32_t)); + g_debug_status = calloc(1, sizeof(uint32_t)); + g_debug_status_prev = calloc(1, sizeof(uint32_t)); + g_debug_test_num = calloc(1, sizeof(uint32_t)); + g_mcycle_cnt = calloc(1, sizeof(uint32_t)); + g_minstret_cnt = calloc(1, sizeof(uint32_t)); + g_single_step_status = calloc(1, sizeof(uint32_t)); + g_single_step_status_prev = calloc(1, sizeof(uint32_t)); + g_single_step_cnt = calloc(1, sizeof(uint32_t)); + g_previous_dpc = calloc(1, sizeof(uint32_t)); + g_expect_irq = calloc(1, sizeof(uint32_t)); + g_unexpected_irq = calloc(1, sizeof(uint32_t)); + g_trigger_matched = calloc(1, sizeof(uint32_t)); + g_has_clic = calloc(1, sizeof(uint32_t)); + g_single_step_unspec_err = calloc(1, sizeof(uint32_t)); + + // Setup clic mtvt if clic is enabled + *g_has_clic = detect_irq_mode(); + setup_clic(); + + // Add function pointers to new tests here + tests[0] = dummy; // unused, can be used for env sanity checking + tests[1] = debug_csr_rw; + tests[2] = trigger_default_val; + tests[3] = ebreak_behavior_m_mode; + tests[4] = request_hw_debugger; + tests[5] = request_ebreak_3x; + tests[6] = csr_access_default_val; + tests[7] = mmode_ebreakm_ebreak_executes_debug_code; + tests[8] = illegal_csr_in_dmode; + tests[9] = ecall_in_dmode; + tests[10] = mret_in_dmode; + tests[11] = exception_enters_debug_mode; + tests[12] = dret_in_mmode; + tests[13] = wfi_before_dmode; + tests[14] = check_irq; + tests[15] = check_stopcnt_bits; + tests[16] = single_step; + tests[17] = mprv_dret_to_umode; + tests[18] = cover_known_iss_mismatches; + + // Run all tests in list above + cvprintf(V_LOW, "\nDebug test start\n\n"); + for (volatile uint32_t i = START_TEST_NUM; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + free((void *)g_handler_triggered ); + free((void *)g_illegal_fail ); + free((void *)g_ebreak_fail ); + free((void *)g_expect_illegal ); + free((void *)g_expect_ebreak ); + free((void *)g_expect_dpc ); + free((void *)g_debug_status ); + free((void *)g_debug_status_prev ); + free((void *)g_debug_test_num ); + free((void *)g_mcycle_cnt ); + free((void *)g_minstret_cnt ); + free((void *)g_single_step_status ); + free((void *)g_single_step_status_prev); + free((void *)g_single_step_cnt ); + free((void *)g_expect_irq ); + free((void *)g_unexpected_irq ); + free((void *)g_trigger_matched ); + free((void *)g_has_clic ); + free((void *)g_single_step_unspec_err ); + + return retval; // Nonzero for failing tests +} + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(volatile uint32_t test_no, volatile uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_NUM; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } + return res; +} + +// ----------------------------------------------------------------------------- + +int get_single_step_result(uint32_t res) { + for (volatile int i = 0; i < 20; i++) { + if ((res >> (i)) & 0x1) { + cvprintf (V_LOW, "Single step section %0d FAILED\n", i); + } + } + + cvprintf(V_LOW, "Stepped %0d instructions\n", *g_single_step_cnt); + return (res == 0 ? 1 : 0); +} + +// ----------------------------------------------------------------------------- + +void print_tdata1(verbosity_t verbosity, volatile tdata1_t * volatile tdata1){ + volatile mcontrol_t * volatile mcontrol; + volatile mcontrol6_t * volatile mcontrol6; + volatile etrigger_t * volatile etrigger; + + mcontrol = (mcontrol_t *) tdata1; + mcontrol6 = (mcontrol6_t *) tdata1; + etrigger = (etrigger_t *) tdata1; + + switch (tdata1->fields.type) { + case 0: + cvprintf(verbosity, "Type: 0x%0x, dmode: 0x%0x, action: 0x%0x\n", + tdata1->fields.type, + tdata1->fields.dmode, + tdata1->fields.data); + break; + case 2: + cvprintf(verbosity, "Type: 0x%0x, dmode: 0x%0x, maskmax: 0x%0x, hit: 0x%0x, select: 0x%0x, " + "timing: 0x%0x, sizelo: 0x%0x, action: 0x%0x, chain: 0x%0x, match: 0x%0x, " + "m: 0x%0x, zero: 0x%0x, s: 0x%0x, u: 0x%0x, execute: 0x%0x, store: 0x%0x, load: 0x%0x\n", + mcontrol->fields.type, + mcontrol->fields.dmode, + mcontrol->fields.maskmax, + mcontrol->fields.hit, + mcontrol->fields.select, + mcontrol->fields.timing, + mcontrol->fields.sizelo, + mcontrol->fields.action, + mcontrol->fields.chain, + mcontrol->fields.match, + mcontrol->fields.m, + mcontrol->fields.res_5_5, + mcontrol->fields.s, + mcontrol->fields.u, + mcontrol->fields.execute, + mcontrol->fields.store, + mcontrol->fields.load); + break; + case 5: + cvprintf(verbosity, "Type: 0x%0x, dmode: 0x%0x, hit: 0x%0x, zero: 0x%0x, vs: 0x%0x, vu: 0x%0x " + "zero: 0x%0x, m: 0x%0x, zero: 0x%0x, s: 0x%0x, u: 0x%0x, action: 0x%0x\n", + etrigger->fields.type, + etrigger->fields.dmode, + etrigger->fields.hit, + etrigger->fields.res_25_13, + etrigger->fields.vs, + etrigger->fields.vu, + etrigger->fields.res_10_10, + etrigger->fields.m, + etrigger->fields.res_8_8, + etrigger->fields.s, + etrigger->fields.u, + etrigger->fields.action); + break; + case 6: + cvprintf(verbosity, "Type: 0x%0x, dmode: 0x%0x, zero: 0x%0x, vs: 0x%0x, vu: 0x%0x, hit: 0x%0x, " + "select: 0x%0x, timing: 0x%0x, size: 0x%0x, action: 0x%0x, chain: 0x%0x, " + "match: 0x%0x, m: 0x%0x, zero: 0x%0x, s: 0x%0x, u: 0x%0x, execute: 0x%0x, " + "store: 0x%0x, load: 0x%0x\n", + mcontrol6->fields.type, + mcontrol6->fields.dmode, + mcontrol6->fields.res_26_25, + mcontrol6->fields.vs, + mcontrol6->fields.vu, + mcontrol6->fields.hit, + mcontrol6->fields.select, + mcontrol6->fields.timing, + mcontrol6->fields.size, + mcontrol6->fields.action, + mcontrol6->fields.chain, + mcontrol6->fields.match, + mcontrol6->fields.m, + mcontrol6->fields.res_5_5, + mcontrol6->fields.s, + mcontrol6->fields.u, + mcontrol6->fields.execute, + mcontrol6->fields.store, + mcontrol6->fields.load); + break; + case 15: + cvprintf(verbosity, "Type: 0x%0x, dmode: 0x%0x, action: 0x%0x\n", + tdata1->fields.type, + tdata1->fields.dmode, + tdata1->fields.data); + break; + } +} + +// ----------------------------------------------------------------------------- + +uint32_t dummy(uint32_t index, uint8_t report_name) { + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t debug_csr_rw(uint32_t index, uint8_t report_name) { + + volatile uint8_t test_fail = 0; + volatile uint32_t temp = 0xFFFFFFFF; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // ------------------------------------------------------------ + cvprintf(V_MEDIUM, "\nChecking write access in M-mode\n"); + // ------------------------------------------------------------ + // DCSR + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrw zero, dcsr, %[temp])" : : [temp] "r" (temp) :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + // DPC + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrw zero, dpc, %[temp])" : : [temp] "r" (temp) :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + // DSCRATCH0 + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrw zero, dscratch0, %[temp])" : : [temp] "r" (temp) :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + // DSCRATCH1 + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrw zero, dscratch1, %[temp])" : : [temp] "r" (temp) :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + // ------------------------------------------------------------ + cvprintf(V_MEDIUM, "\nChecking read access in M-mode\n"); + // ------------------------------------------------------------ + + // DCSR + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrs %[temp], dcsr, zero)" : [temp] "=r" (temp) : :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + // DPC + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrs %[temp], dpc, zero)" : [temp] "=r" (temp) : :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + // DSCRATCH0 + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrs %[temp], dscratch0, zero)" : [temp] "=r" (temp) : :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + // DSCRATCH1 + *g_expect_illegal = 1; + __asm__ volatile ( R"( csrrs %[temp], dscratch1, zero)" : [temp] "=r" (temp) : :); + test_fail += *g_illegal_fail; + if (ABORT_ON_ERROR_IMMEDIATE) assert(test_fail == 0); + + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; + +} + +// ----------------------------------------------------------------------------- + +uint32_t trigger_default_val(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile uint32_t readback_val; + + volatile uint32_t tdata1_bits; + volatile tdata1_t * volatile tdata1; + volatile tinfo_t * volatile tinfo; + + // Below are volatile for type consistency, ideally should be declared as const + volatile tinfo_t tinfo_reset = { + .fields.version = 0x1, + .fields.info = 0x8064 + }; + + volatile tdata1_t tdata1_reset = { + .fields.type = 2, + .fields.dmode = 1, + .fields.data = 0x1000 + }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // tselect default value + __asm__ volatile ( R"( csrrs %[tselect], tselect, zero )" : [tselect] "=r"(readback_val) : : ); + test_fail += (readback_val != 0); + if (ABORT_ON_ERROR_IMMEDIATE) { assert(test_fail == 0); } + + // tdata1 default value + __asm__ volatile ( R"( csrrs %[tdata1], tdata1, zero)" : [tdata1] "=r"(tdata1_bits) : :); + + tdata1 = (tdata1_t *)&tdata1_bits; + + test_fail += !(tdata1->raw == tdata1_reset.raw); + + if (ABORT_ON_ERROR_IMMEDIATE) { + assert(test_fail == 0); + } + if (test_fail) { + cvprintf(V_MEDIUM, "Got: "); + print_tdata1(V_MEDIUM, tdata1); + cvprintf(V_MEDIUM, "Exp: "); + print_tdata1(V_MEDIUM, &tdata1_reset); + } + + // tdata2 default value + __asm__ volatile ( R"( csrrs %[tdata2], tdata2, zero )" : [tdata2] "=r"(readback_val) : : ); + test_fail += (readback_val != 0); + if (ABORT_ON_ERROR_IMMEDIATE) { assert(test_fail == 0); } + if (test_fail) { + cvprintf(V_MEDIUM, "tdata2 exp: 0x0, got: 0x%0x\n", readback_val); + } + + // tinfo default value + __asm__ volatile ( R"( csrrs %[tinfo], tinfo, zero )" : [tinfo] "=r"(readback_val) : : ); + tinfo = (void *)&readback_val; + test_fail += ( tinfo->fields.info != tinfo_reset.fields.info + || tinfo->fields.res_23_16 != 0 + || tinfo->fields.version != tinfo_reset.fields.version); + if (ABORT_ON_ERROR_IMMEDIATE) { assert(test_fail == 0); } + if (test_fail) { + cvprintf(V_MEDIUM, "tinfo exp: info: 0x%0x, zero: 0x%0x, version: 0x%0x, got: info: 0x%0x, zero: 0x%0x, version: 0x%0x\n", + tinfo_reset.fields.info, tinfo_reset.fields.res_23_16, tinfo_reset.fields.version, + tinfo->fields.info, tinfo->fields.res_23_16, tinfo->fields.version); + } + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; + +} + +// ----------------------------------------------------------------------------- + +uint32_t ebreak_behavior_m_mode(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_handler_triggered = 0; + *g_expect_ebreak = 1; + + __asm__ volatile ( R"( + .option push + .option norvc + ebreak + .option pop + )"); + test_fail += (*g_ebreak_fail || !*g_handler_triggered); + if (ABORT_ON_ERROR_IMMEDIATE) { assert(test_fail == 0); } + if (*g_ebreak_fail) { + cvprintf(V_MEDIUM, "ebreak behavior incorrect\n"); + } + *g_ebreak_fail = 0; + + *g_handler_triggered = 0; + *g_expect_ebreak = 1; + __asm__ volatile ( R"( c.ebreak )" :::); + test_fail += (*g_ebreak_fail || !*g_handler_triggered); + if (ABORT_ON_ERROR_IMMEDIATE) { assert(test_fail == 0); } + if (*g_ebreak_fail) { + cvprintf(V_MEDIUM, "c.ebreak behavior incorrect\n"); + } + + *g_ebreak_fail = 0; + *g_handler_triggered = 0; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t request_hw_debugger(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + *g_debug_test_num = 1; + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + while (!*g_debug_status) { + ;; + } + + test_fail += *g_debug_status > 1 ? 1 : 0; + *g_debug_status = 0; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t request_ebreak_3x(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + *g_debug_status = 0; + *g_debug_test_num = 2; + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + while (*g_debug_status < 3) { + ;; + } + if (*g_debug_status != *g_debug_status_prev) { + cvprintf(V_MEDIUM, "Debug status: %0ld\n", *g_debug_status); + } + *g_debug_status_prev = *g_debug_status; + + test_fail += *g_debug_status == 4 ? 0 : 1; + *g_debug_status = 0; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +__attribute__((naked)) void m_fast14_irq_handler(void) { + + __asm__ volatile ( R"( + + # Push saved regs and allocate space for the remaining 16 regs + cm.push {ra, s0-s11}, -112 + addi sp, sp, -12 + + # Save argument registers to stack + # as we want to be able to call C-functions + # from debug + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw a3, 12(sp) + sw a4, 16(sp) + sw a5, 20(sp) + sw a6, 24(sp) + sw a7, 28(sp) + + # Back up remaining temporaries + sw tp, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + + sw gp, 64(sp) + + # Get test number + lw s1, g_debug_test_num + lw s1, 0(s1) + + addi s0, zero, 11 + bne s0, s1, 1f + lw s0, g_debug_status + lw s1, 0(s0) + addi s1, zero, 1 + sw s1, 0(s0) + + 1: + + ## restore stack + lw gp, 64(sp) + + # Restore temporary registers + lw t6, 60(sp) + lw t5, 56(sp) + lw t4, 52(sp) + lw t3, 48(sp) + lw t2, 44(sp) + lw t1, 40(sp) + lw t0, 36(sp) + lw tp, 32(sp) + + # Restore argument registers + lw a7, 28(sp) + lw a6, 24(sp) + lw a5, 20(sp) + lw a4, 16(sp) + lw a3, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + + # Restore stack ptr + addi sp, sp, 12 + cm.pop {ra, s0-s11}, 112 + + mret + )"); +} + +// --------------------------------------------------------------- + +__attribute__((naked)) void u_sw_irq_handler(void) { + + __asm__ volatile ( R"( + # Push saved regs and allocate space for the remaining 16 regs + cm.push {ra, s0-s11}, -112 + addi sp, sp, -12 + + # Save argument registers to stack + # as we want to be able to call C-functions + # from debug + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw a3, 12(sp) + sw a4, 16(sp) + sw a5, 20(sp) + sw a6, 24(sp) + sw a7, 28(sp) + + # Back up remaining temporaries + sw tp, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + + sw gp, 64(sp) + + # Get test number + lw s1, g_debug_test_num + lw s1, 0(s1) + + # Jump to test specific code + addi s0, zero, 8 + beq s0, s1, 8f + addi s0, zero, 9 + beq s0, s1, 9f + addi s0, zero, 11 + beq s0, s1, 11f + + beq zero, zero, 98f + + 8: + c.ebreak + beq zero, zero, 99f + + 9: + lw s1, g_debug_status + lw s0, 0(s1) + addi s0, zero, 1 + sw s0, 0(s1) + beq zero, zero, 99f + + 11: + call check_irq_handler + beq zero, zero, 99f + + 98: + call u_sw_irq_handler_default + beq zero, zero, 99f # Added to prevent omission if adding further cases + + 99: + # increment mepc by appropriate amount + add a0, zero, zero + call increment_mepc + + # set g_handler_triggered + lw s0, g_handler_triggered + addi s1, zero, 1 + sw s1, 0(s0) + + # clear g_expect_ebreak + lw s0, g_expect_ebreak + addi s1, zero, 0 + sw s1, 0(s0) + + # clear g_expect_illegal + lw s0, g_expect_illegal + addi s1, zero, 0 + sw s1, 0(s0) + + ## restore stack + lw gp, 64(sp) + + # Restore temporary registers + lw t6, 60(sp) + lw t5, 56(sp) + lw t4, 52(sp) + lw t3, 48(sp) + lw t2, 44(sp) + lw t1, 40(sp) + lw t0, 36(sp) + lw tp, 32(sp) + + # Restore argument registers + lw a7, 28(sp) + lw a6, 24(sp) + lw a5, 20(sp) + lw a4, 16(sp) + lw a3, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + + # Restore stack ptr + addi sp, sp, 12 + cm.pop {ra, s0-s11}, 112 + + mret + + )"); +} + +// --------------------------------------------------------------- + +void u_sw_irq_handler_default(void) { + volatile mcause_t mcause = { 0 }; + + // Fields to clear; + // Exists in both clic and clint, no need to have + // special consideration for clic/clint. + // Clearing all bits as for clint would break clic + // mpp behavior + mcause.clic.interrupt = 0x1; + mcause.clic.exccode = 0x7FF; + + __asm__ volatile ( R"( + csrrc %[mc], mcause, %[mc] + )" + : [mc] "=r"(mcause.raw) + : + ); + + if (mcause.clint.interrupt == 0 || mcause.clic.interrupt == 0) { + if (mcause.clint.exccode == MCAUSE_ILLEGAL || mcause.clic.exccode == MCAUSE_ILLEGAL) { + if (!*g_expect_illegal) { + *g_illegal_fail = 1; + } + } + else if (mcause.clint.exccode == MCAUSE_BREAKPT || mcause.clic.exccode == MCAUSE_BREAKPT) { + if (!*g_expect_ebreak) { + *g_ebreak_fail = 1; + } + } + else { + if (*g_expect_illegal) { + *g_illegal_fail = 1; + } + if (*g_expect_ebreak) { + *g_ebreak_fail = 1; + } + } + } + return; +} + +// ----------------------------------------------------------------------------- + +// Main debug code, note that all test sections triggered inside +// this function are suffixed with _dbg. +void __attribute__((naked)) _debugger_start(void) { + __asm__ volatile ( R"( + + # Setup debug stack and save sp, gp + csrrw zero, dscratch0, sp + 1:auipc sp, %pcrel_hi(__debugger_stack_start) + addi sp, sp, %pcrel_lo(1b) + + # Push saved regs and allocate space for the remaining 16 regs + cm.push {ra, s0-s11}, -112 + addi sp, sp, -12 + + # Save argument registers to stack + # as we want to be able to call C-functions + # from debug + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw a3, 12(sp) + sw a4, 16(sp) + sw a5, 20(sp) + sw a6, 24(sp) + sw a7, 28(sp) + + # Back up remaining temporaries + sw tp, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + + sw gp, 64(sp) + + # Save mcycle/minstret + csrrs s0, mcycle, zero + lw s1, g_mcycle_cnt + sw s0, 0(s1) + + csrrs s0, minstret, zero + lw s1, g_minstret_cnt + sw s0, 0(s1) + + call disable_debug_req + + # Get current test number + addi s1, zero, 0 + addi s0, zero, 0 + lw s1, g_debug_test_num + lw s1, 0(s1) + + # Jump to correct test + addi s0, zero, 1 + beq s0, s1, 1f + addi s0, zero, 2 + beq s0, s1, 2f + addi s0, zero, 3 + beq s0, s1, 3f + addi s0, zero, 4 + beq s0, s1, 4f + addi s0, zero, 5 + beq s0, s1, 5f + addi s0, zero, 6 + beq s0, s1, 6f + addi s0, zero, 7 + beq s0, s1, 7f + addi s0, zero, 8 + beq s0, s1, 8f + addi s0, zero, 10 + beq s0, s1, 10f + addi s0, zero, 12 + beq s0, s1, 12f + addi s0, zero, 13 + beq s0, s1, 13f + addi s0, zero, 14 + beq s0, s1, 14f + addi s0, zero, 18 + beq s0, s1, 18f + + # no match, exit + beq zero, zero, 99f + + 1: call request_hw_debugger_dbg + beq zero, zero, 99f + + 2: call request_ebreak_3x_dbg + beq zero, zero, 99f + + 3: call csr_access_default_val_dbg + beq zero, zero, 99f + + 4: call mmode_ebreakm_ebreak_executes_debug_code_dbg + beq zero, zero, 99f + + 5: call illegal_csr_in_dmode_dbg + beq zero, zero, 99f + + 6: call ecall_in_dmode_dbg + beq zero, zero, 99f + + 7: call mret_in_dmode_dbg + beq zero, zero, 99f + + 8: call exception_enters_debug_mode_dbg + beq zero, zero, 99f + + 10: call wfi_before_dmode_dbg + beq zero, zero, 99f + + 12: call check_stopcnt_bits_dbg + beq zero, zero, 99f + + 13: call single_step_dbg + beq zero, zero, 99f + + 14: call mprv_dret_to_umode_dbg + beq zero, zero, 99f + + 18: call cover_known_iss_mismatches_dbg + beq zero, zero, 99f + + 99: call _debugger_end + dret + + )"); +} + +// ----------------------------------------------------------------------------- + +void disable_debug_req(void) { + volatile debug_req_control_t debug_req_ctrl; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 0, + .fields.pulse_mode = 0, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0, + .fields.rand_start_delay = 0, + .fields.start_delay = 0 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; +} + +// ----------------------------------------------------------------------------- + +void __attribute__((__noinline__)) request_hw_debugger_dbg(void) { + volatile dcsr_t dcsr; + + __asm__ volatile ( R"( csrrs %[dcsr], dcsr, zero)" : [dcsr] "=r"(dcsr.raw) : : ); + cvprintf(V_MEDIUM, "dcsr cause: %0x\n", dcsr.fields.cause); + + if (dcsr.fields.cause != DCAUSE_HALTREQ) { + *g_debug_status = 99; + } else { + *g_debug_status = 1; + } + +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) request_ebreak_3x_dbg(void) { + __asm__ volatile ( R"( + call get_dcsr_cause + add s2, zero, a0 + + addi s3, zero, 3 + bne s2, s3, 1f + + lw s4, g_debug_status + add a0, s4, zero + call incr_val + sw a0, 0(s4) + + beq zero, zero, 2f + + 1: + lw a0, g_debug_status + addi a1, zero, 99 + call set_val + add s4, a0, zero + + 2: + lw s4, 0(s4) + # switch(g_debug_status) + # case 1: + addi s5, zero, 1 + beq s4, s5, 1f + + # case 2: + addi s5, zero, 2 + beq s4, s5, 2f + + # case 3: + addi s5, zero, 3 + beq s4, s5, 1f + + # default: + beq zero, zero, 3f + + 1: + # pop stack + + ### la s5, e2 + 1:auipc s5, %pcrel_hi(e1) + addi s5, s5, %pcrel_lo(1b) + csrrw zero, dscratch1, s5 + + ### jal zero, _debugger_restore_stack + 99: auipc s11, %pcrel_hi(_debugger_restore_stack) + addi s11, s11, %pcrel_lo(99b) + jalr zero, 0(s11) + + e1: csrrw s5, dscratch1, zero + + # force uncompressed ebreak + .option push + .option norvc + ebreak + .option pop + + 2: + addi s5, zero, 2 + bne s4, s5, 1f + + # pop stack + + ### la s5, e2 + 1:auipc s5, %pcrel_hi(e2) + addi s5, s5, %pcrel_lo(1b) + + csrrw zero, dscratch1, s5 + + ### j _debugger_restore_stack + 99: auipc s11, %pcrel_hi(_debugger_restore_stack) + addi s11, s11, %pcrel_lo(99b) + jalr zero, 0(s11) + + e2: csrrw s5, dscratch1, zero + + c.ebreak + + # return if we are done + 3: + csrrw zero, dscratch1, zero + 99: auipc s11, %pcrel_hi(_debugger_end) + addi s11, s11, %pcrel_lo(99b) + jalr zero, 0(s11) + + )"); +} + +// ----------------------------------------------------------------------------- + +// Csr access test entry +uint32_t csr_access_default_val(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 3; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + while (*g_debug_status == 0) { + ;; + } + + test_fail += (*g_debug_status == 1) ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Debug portion of csr access test +void csr_access_default_val_dbg(void) { + volatile uint32_t mvendorid; + volatile uint32_t marchid; + volatile uint32_t mimpid; + volatile uint32_t mhartid; + volatile uint32_t mstatus; + volatile uint32_t misa; + volatile uint32_t mie; + volatile uint32_t mtvec; + volatile uint32_t mtval; + volatile uint32_t mscratch; + volatile uint32_t mepc; + volatile uint32_t mcause; + volatile uint32_t mip; + volatile dcsr_t dcsr; + volatile dcsr_t dcsr_default; + volatile uint32_t dpc; + volatile uint32_t tdata1; + volatile uint32_t tdata2; + + __asm__ volatile ( R"( + # access + csrrs %[mvendorid], mvendorid, zero + csrrs %[marchid], marchid, zero + csrrs %[mimpid], mimpid, zero + csrrs %[mhartid], mhartid, zero + csrrs %[mstatus], mstatus, zero + csrrs %[misa], misa, zero + csrrs %[mie], mie, zero + csrrs %[mtvec], mtvec, zero + csrrs %[mtval], mtval, zero + csrrs %[mscratch], mscratch, zero + csrrs %[mepc], mepc, zero + csrrs %[mcause], mcause, zero + csrrs %[mip], mip, zero + + # default values + csrrs %[dcsr], dcsr, zero + csrrs %[dpc], dpc, zero + csrrs %[tdata1], tdata1, zero + csrrs %[tdata2], tdata2, zero + )" + : [mvendorid] "=r"(mvendorid), + [marchid] "=r"(marchid), + [mimpid] "=r"(mimpid), + [mhartid] "=r"(mhartid), + [mstatus] "=r"(mstatus), + [misa] "=r"(misa), + [mie] "=r"(mie), + [mtvec] "=r"(mtvec), + [mtval] "=r"(mtval), + [mscratch] "=r"(mscratch), + [mepc] "=r"(mepc), + [mcause] "=r"(mcause), + [mip] "=r"(mip), + [dcsr] "=r"(dcsr.raw), + [dpc] "=r"(dpc), + [tdata1] "=r"(tdata1), + [tdata2] "=r"(tdata2) + ::); + + dcsr_default.raw = 0x00000000; + dcsr_default = (dcsr_t){ + .fields.xdebugver = 4, + .fields.stopcount = 1, + .fields.cause = DCAUSE_HALTREQ, + .fields.mprven = 1, + .fields.prv = MODE_MACHINE }; + + if (dcsr.raw != dcsr_default.raw) { + cvprintf(V_MEDIUM, "dcsr default value wrong, expected: 0x%08lx, got 0x%08lx\n", dcsr.raw, dcsr_default.raw); + *g_debug_status = 99; + } + + if (dpc == 0x00000000) { + cvprintf(V_MEDIUM, "dpc should not be zero\n"); + *g_debug_status = 99; + } + + dcsr.raw = 0x00000000; + + dcsr = (dcsr_t){ + .fields.xdebugver = 4, + .fields.cause = DCAUSE_HALTREQ, + .fields.prv = MODE_MACHINE, + .fields.ebreakm = 1 + }; + + // Enable ebreakm + __asm__ volatile ( R"( + csrrw zero, dcsr, %[dcsr] + csrrw zero, dscratch1, zero + )" + : [dcsr] "=r"(dcsr.raw) + ::); + + if (*g_debug_status != 99) { + *g_debug_status = 1; + } +} + +// ----------------------------------------------------------------------------- + +// Test ebreak entry to debug mode, flags that we successfully +// entered debug. +void mmode_ebreakm_ebreak_executes_debug_code_dbg(void) { + volatile uint32_t dpc; + *g_debug_status += 1; + + __asm__ volatile ( R"( + csrrs %[dpc], dpc, zero + addi %[dpc], %[dpc], 4 + csrrw zero, dpc, %[dpc] + )" : [dpc] "+r"(dpc) :: ); +} + +// ----------------------------------------------------------------------------- + +// Machine mode section of ebreak->debug mode test +uint32_t mmode_ebreakm_ebreak_executes_debug_code(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 4; + + __asm__ volatile ( R"( + .option push + .option norvc + ebreak + .option pop + )"); + + test_fail += (*g_debug_status == 1) ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Illegal csr in dmode test entry +uint32_t illegal_csr_in_dmode(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 5; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + while (*g_debug_status == 0) { + ;; + } + + test_fail += (*g_debug_status == 1) ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Illegal csr in dmode debug code +void __attribute__((naked)) illegal_csr_in_dmode_dbg(void) { + __asm__ volatile ( R"( + csrrw s10, 0xeaf, s10 + )"); +} + +// ----------------------------------------------------------------------------- + +// Ecall in dmode test entry +uint32_t ecall_in_dmode(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 6; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + while (*g_debug_status == 0) { + ;; + } + + test_fail += (*g_debug_status == 1) ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Debug mode ecall +void ecall_in_dmode_dbg(void) { + __asm__ volatile ( R"( + ecall + )"); +} + +// ----------------------------------------------------------------------------- + +// Mret in dmode test entry +uint32_t mret_in_dmode(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 7; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + while (*g_debug_status == 0) { + ;; + } + + test_fail += (*g_debug_status == 1) ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Mret in debug mode, debug portion +// This does technically not need to be in a function +// but for test structure and readability keeps the +// structure used for other tests. +void mret_in_dmode_dbg(void) { + __asm__ volatile ( R"( + mret + )"); +} + +// ----------------------------------------------------------------------------- + +// Exception to dmode test entry +uint32_t exception_enters_debug_mode(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 8; + + __asm__ volatile (R"(csrrs s11, dcsr, zero)"); + + while (*g_debug_status == 0) { + ;; + } + + test_fail += (*g_debug_status == 1) ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Debug portion of exception -> debug entry test +void exception_enters_debug_mode_dbg(void) { + volatile uint32_t dpc; + + *g_debug_status = 1; + __asm__ volatile ( R"( + csrrs %[dpc], dpc, zero + addi %[dpc], %[dpc], 2 + csrrw zero, dpc, %[dpc] + )": [dpc] "+r"(dpc)); +} + +// ----------------------------------------------------------------------------- + +// Dret in m-mode test entry +uint32_t dret_in_mmode(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 9; + + __asm__ volatile (R"(dret)"); + + test_fail += *g_debug_status ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Wfi prior to dmode test entry +uint32_t wfi_before_dmode(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 10; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + __asm__ volatile (R"(wfi)"); + + while (*g_debug_status == 0) { + ;; + } + + + test_fail += *g_debug_status ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// Wfi before dmode debug portion +void wfi_before_dmode_dbg(void) { + *g_debug_status = 1; +} + +// ----------------------------------------------------------------------------- + +void clint_mie_enable(uint8_t irq_num) { + __asm__ volatile( R"( + csrrsi zero, mstatus, 0x8 + csrrs zero, mie, %[bit] + )" + : : [bit] "r" (0x1 << irq_num) + ); +} + +// ----------------------------------------------------------------------------- + +void clint_mie_disable(uint8_t irq_num) { + __asm__ volatile( R"( + csrrc zero, mie, %[bit] + )" + : : [bit] "r" (0x1 << irq_num) + ); +} + +// ----------------------------------------------------------------------------- + +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay) { + *TIMER_REG_ADDR = mask; + *TIMER_VAL_ADDR = 1 + cycle_delay; +} + +// ----------------------------------------------------------------------------- + +uint32_t check_irq(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 11; + + clint_mie_enable(30); + *g_expect_irq = 1; + assert_irq(); + + while (!(*g_debug_status)) { + ;; + } + + test_fail += *g_debug_status ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +void check_irq_handler(void) { + volatile mcause_t mcause = { 0 }; + + // Fields to clear; + // Exists in both clic and clint, no need to have + // special consideration for clic/clint. + // Clearing all bits as for clint would break clic + // mpp behavior + mcause.clic.interrupt = 0x1; + mcause.clic.exccode = 0x7FF; + + __asm__ volatile ( R"( + csrrc %[mc], mcause, %[mc] + )" + : [mc] "+r"(mcause.raw) + : + ); + + cvprintf(V_LOW, "mcause.exccode: %0d, mcause.interrupt: %0d\n", mcause.clic.exccode, mcause.clic.interrupt); + // we use same id for clic and clint for simplicity + if (((mcause.clint.interrupt == 1) && + (mcause.clint.exccode == 30)) || + (mcause.clic.interrupt == 1 && + mcause.clic.exccode == 30)) { + *g_debug_status = 1; + // No effect for clic + clint_mie_disable(30); + deassert_irq(); + } + else { + *g_debug_status = 0; + // No effect for clic + clint_mie_disable(30); + deassert_irq(); + } +} + +// ----------------------------------------------------------------------------- + +uint32_t check_stopcnt_bits(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_status = 0; + *g_debug_test_num = 12; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + while (!(*g_debug_status)) { + ;; + } + test_fail += *g_debug_status ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +void check_stopcnt_bits_dbg(void) { + volatile dcsr_t dcsr; + dcsr.raw = 0; + dcsr.fields.stopcount = 1; + + __asm__ volatile (R"( + csrrs zero, dcsr, %[dcsr] + csrrw zero, dscratch1, zero + )" + : [dcsr] "=r"(dcsr.raw) + ); + + // Set ok, this will be cleared by _debugger end if + // the counters have incremented + *g_debug_status = 1; +} + + +// --------------------------------------------------------------- +// single_step +// +// Main test initiator for single step tests, follows the common +// test template +// --------------------------------------------------------------- +uint32_t single_step(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_illegal_fail = 0; + *g_debug_status = 0; + *g_debug_test_num = 13; + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + while (!(*g_single_step_status)) { + ;; + } + + single_step_code(); + + test_fail += get_single_step_result(*g_debug_status) ? 0 : 1; + // Also check for some failures during certain checkpoints + // that is not necessarily connected to specific subtest - + // the log should contain the actual error location. + test_fail += *g_single_step_unspec_err ? 1 : 0; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// --------------------------------------------------------------- +// single_step_code +// +// Main regular code to be single stepped in M-mode, is a set +// of subtests in itself, each test/function initialized with a +// dashed comment line and a label to ease debugging. +// Note: These labels are not used by the code itself. +// --------------------------------------------------------------- +void __attribute__((naked)) single_step_code(void) { + __asm__ volatile (R"( + cm.push {ra, s0-s11}, -64 + + # ---------------- + ebreak_into_debug_mode_cause_1: + + add s2, zero, zero + # Enter debug mode to execute cause=1 + c.ebreak + # Load value to s3 to verify correct dpc increment + addi s2, zero, 1 + + # add a few nops, to avoid missing setting fail + # in case of minor increment errors + c.nop + c.nop + c.nop + c.nop + + bne s2, zero, 1f + # first single step checkpoint, set bit 1 if fail + addi a0, zero, 1 << 1 + call set_debug_status + + 1: # continue + # ---------------- + # single_step_status is updated in debug mode here + # unlike the following tests + wfi_should_nop_in_single_step: + wfi + + # Not setting an error bit here if fail, test will hang if + # a wfi is not treated as nop in single_step + + # ---------------- + addi a0, zero, 3 + call set_single_step_status + + illegal_instr_handle: + add s2, zero, zero + + # illegal csr instruction (dcsr access in m-mode) + csrrs s2, dcsr, zero + # illegal instruction (dret in m-mode) + dret + + # If number of invalid instructions mismatch, set status + # bit 3 + + # Expect two illegal instructions + lw s3, g_illegal_fail + lw s4, 0(s3) + addi s4, s4, -2 + bne s4, zero, ss_fail_3 + # Expect no change to s2, as instruction should not retire + beq s2, zero, 1f + + ss_fail_3: + addi a0, zero, 1 << 3 + call set_debug_status + + 1: # Continue + # ---------------- + + trigger_match_setup_reason_4: + # Trigger match setup + addi a0, zero, 4 + call set_single_step_status + addi s3, zero, 0 + + .global trigger_loc + .global trigger_exit + + add s3, zero, zero + + trigger_loc: + addi s3, zero, 1 # This instruction should be skipped due to trigger + trigger_exit: + addi s3, s3, 2 # Thus we should end up with 2, not 3 in s3 + + # wait here for one instruction to let debug mode attempt + # trigger match inside debug mode + + addi s3, s3, -2 + + # trigger skipped correctly, continue + bne s3, zero, 2f + beq zero, zero, 1f + + 2: + # we observed exactly one cause = trigger, continue + # g_trigger matched should == 2 as we also use this to + # signal debug mode to attempt trigger in debug + lw s4, g_trigger_matched + lw s5, 0(s4) + addi s5, s5, -3 + beq s5, zero, 1f + + # one of the above conditions failed + addi a0, zero, 1 << 4 + call set_debug_status + + 1: # Continue + # ---------------- + step_with_interrupt_with_stepie_reason_5: + addi a0, zero, 30 + call clint_mie_enable + addi a0, zero, 5 + call set_single_step_status + lw s3, g_expect_irq + addi s4, zero, 1 + sw s4, 0(s3) + call assert_irq + call wait_irq + + lw s4, 0(s3) + beq s4, zero, 1f + addi a0, zero, 1 << 5 + call set_debug_status + + 1: # Continue + # ---------------- + step_with_interrupt_without_stepie_reason_6: + addi a0, zero, 30 + call clint_mie_enable + addi a0, zero, 6 + call set_single_step_status + call assert_irq + nop + nop + nop + nop + nop + nop + nop + call deassert_irq + nop + nop + + lw s3, g_unexpected_irq + lw s4, 0(s3) + beq s4, zero, 1f + sw zero, 0(s3) + addi a0, zero, 1 << 6 + call set_debug_status + # TODO need this many NOPs? + + 1: # Continue + # ---------------- + step_with_c_ebreak_reason_7: + lw s3, g_ebreak_fail + sw zero, 0(s3) + + addi a0, zero, 7 + call set_single_step_status + c.ebreak + + lw s4, 0(s3) + beq s4, zero, 1f + addi a0, zero, 1 << 7 + call set_debug_status + + 1: # Continue + # ---------------- + step_with_ebreak_reason_8: + lw s3, g_ebreak_fail + sw zero, 0(s3) + addi a0, zero, 8 + call set_single_step_status + # force noncompressed ebreak + .option push + .option norvc + ebreak + .option pop + + lw s4, 0(s3) + beq s4, zero, 1f + addi a0, zero, 1 << 8 + call set_debug_status + + 1: # Continue + # ---------------- + step_with_ebreak_without_dcsr_ebreakm_reason_9: + addi a0, zero, 9 + call set_single_step_status + + lw s0, g_expect_ebreak + addi s1, zero, 1 + sw s1, 0(s0) + + # force noncompressed ebreak + .option push + .option norvc + ebreak + .option pop + + lw s1, 0(s0) + beq s1, zero, 1f + + addi a0, zero, 1 + slli a0, a0, 9 + call set_debug_status + + 1: # Continue + # ---------------- + step_with_cebreak_without_dcsr_ebreakm_reason_10: + addi a0, zero, 10 + call set_single_step_status + + lw s0, g_expect_ebreak + addi s1, zero, 1 + sw s1, 0(s0) + + c.ebreak + + lw s1, 0(s0) + beq s1, zero, 1f + + addi a0, zero, 1 + slli a0, a0, 10 + call set_debug_status + + 1: # Continue + # ---------------- + # disable single step + addi a0, zero, 11 + call set_single_step_status + ecall + + 99: cm.pop {ra, s0-s11}, 64 + + # return + jalr zero, 0(ra) + )"); +} + +// ----------------------------------------------------------------------------- + +// Wrappers to support both clic/clint +void assert_irq(void) { + volatile clic_t clic_vector = { 0 }; + volatile clint_t clint_vector = { 0 }; + + // Use interrupt id 30 for simplicity + if (*g_has_clic == 1) { + // clic + clic_vector = (clic_t){ .fields.irq = 1, + .fields.id = 30, + .fields.level = 81, + .fields.priv = MODE_MACHINE, + .fields.shv = 1 + }; + vp_assert_irq(clic_vector.raw, 2); + } + else { + // clint + clint_vector.fields.irq_30 = 1; + vp_assert_irq(clint_vector.raw, 2); + } +} + +// ----------------------------------------------------------------------------- + +void deassert_irq(void) { + // Same for clic/clint + vp_assert_irq(0, 0); +} + +// ----------------------------------------------------------------------------- + +void wait_irq(void) { + while (*g_expect_irq) { + ;; + } +} + +// ----------------------------------------------------------------------------- +// Single step support functions +// ----------------------------------------------------------------------------- + +void increment_single_step_status(void) { + *g_single_step_status += 1; +} + +// ----------------------------------------------------------------------------- + +void set_debug_status(volatile uint32_t status) { + *g_debug_status |= status; +} + +// ----------------------------------------------------------------------------- + +void set_single_step_status(volatile uint32_t status) { + *g_single_step_status = status; +} + +// ----------------------------------------------------------------------------- + +void print_single_step_status(void) { + if (*g_single_step_status != *g_single_step_status_prev) { + cvprintf(V_DEBUG, "status: %0d\n", *g_single_step_status); + } + *g_single_step_status_prev = *g_single_step_status; +} + +// ----------------------------------------------------------------------------- + +void ebreakm_set_dbg(void) { + volatile dcsr_t dcsr; + dcsr.raw = 0; + + dcsr.fields.ebreakm = 1; + + __asm__ volatile ( R"( + csrrs zero, dcsr, %[dcsr] + )":: [dcsr] "r"(dcsr.raw) + ); +} + +// ----------------------------------------------------------------------------- + +void single_step_dbg(void) { + // Check for single step exceptions and handle correct return addr + // Use this function to handle exceptions and verify correct + // pc after taking exceptions/interrupts while in single step + // to avoid having to single step through exception code with + // excessive test run times. + exception_status_dbg(); + + print_single_step_status(); + __asm__ volatile ( R"( + csrrs %[dpc], dpc, zero + )" : [dpc] "=r"(*g_previous_dpc)); + + switch (*g_single_step_status) { + case 0: + ebreakm_set_dbg(); + increment_single_step_status(); + break; + case 1: + single_step_enable_dbg(); + increment_single_step_status(); + break; + case 2: + ;; // Not used, kept for consistency + break; + case 3: + single_step_basic_dbg(); + break; + case 4: + single_step_trigger_setup_dbg(); + single_step_basic_dbg(); + break; + case 5: + single_step_stepie_enable_dbg(); + break; + case 6: + single_step_stepie_disable_dbg(); + break; + case 7: + single_step_c_ebreak_dbg(); + break; + case 8: + single_step_ebreak_dbg(); + break; + case 9: + single_step_ebreak_exception_dbg(); + break; + case 10: + single_step_c_ebreak_exception_dbg(); + break; + case 11: + single_step_disable_dbg(); + break; + default: break; + } + + *g_single_step_cnt += 1; +} + +// ----------------------------------------------------------------------------- +// Handle execptions and interupts inside debug mode instead of single stepping +// through the entire handler to speed up the process - we still verify that +// we actually entered the handler, and then handle it here +// ----------------------------------------------------------------------------- + +void exception_status_dbg(void) { + volatile uint32_t dpc = 0; + volatile uint32_t mtvec = 0; + volatile uint32_t mepc = 0; + volatile mcause_t mcause = { 0 }; + volatile dcsr_t dcsr; + volatile uint32_t temp; + volatile mcontrol_t mcontrol = { 0 }; + volatile mcontrol_t mcontrol_backup = { 0 }; + volatile uint32_t tdata2_backup; + + // Fields to clear; + // Exists in both clic and clint, no need to have + // special consideration for clic/clint. + // Clearing all bits as for clint would break clic + // mpp behavior + mcause.clic.interrupt = 0x1; + mcause.clic.exccode = 0x7FF; + + __asm__ volatile ( R"( + csrrs %[dpc], dpc, zero + csrrs %[mtvec], mtvec, zero + csrrc %[mcause], mcause, %[mcause] + csrrs %[dcsr], dcsr, zero + csrrs %[mepc], mepc, zero + )" : [dpc] "=r"(dpc), + [mtvec] "=r"(mtvec), + [mcause]"+r"(mcause.raw), + [dcsr] "=r"(dcsr.raw), + [mepc] "=r"(mepc)); + + if (mcause.clint.interrupt == 1 || mcause.clic.interrupt == 1) { + // Disable interrupt + deassert_irq(); + if (*g_expect_irq) { + *g_expect_irq = 0; + } else { + *g_unexpected_irq = 1; + single_step_fail(5); + cvprintf(V_LOW, "mcause.interrupt: %0d, mcause.exccode: %0d\n", mcause.clint.interrupt, mcause.clint.exccode); + } + } else if (*g_single_step_status == 4) { + + if (*g_trigger_matched == 1) { + + *g_trigger_matched += 1; + mcontrol = (mcontrol_t) { + .fields.type = 2, + .fields.dmode = 1, + .fields.action = 1, + .fields.m = 1, + .fields.execute = 1 + }; + + __asm__ volatile ( R"( + .global trigger_loc_dbg + csrrw %[tdata2_backup], tdata2, %[trigger_loc_dbg] + csrrw %[mcontrol_backup], tdata1, %[mcontrol] + + trigger_loc_dbg: + addi %[temp], zero, 5 + nop + )" : [temp] "=r"(temp), + [mcontrol_backup] "=r"(mcontrol_backup.raw), + [tdata2_backup] "=r"(tdata2_backup) + : [trigger_loc_dbg] "r"(&trigger_loc_dbg), + [mcontrol] "r"(mcontrol.raw)); + + if (temp == 5) { + // Correctly executed trigger address + *g_trigger_matched += 1; + } else { + // Triggered, should not happen + *g_trigger_matched += 10; + } + // Restore previous value + __asm__ volatile ( R"( + csrrw zero, tdata1, %[mcontrol_backup] + csrrw zero, tdata2, %[tdata2_backup] + )" :: [mcontrol_backup] "r"(mcontrol_backup.raw), + [tdata2_backup] "r"(&tdata2_backup) + ); + } + + *g_trigger_matched += (dcsr.fields.cause == DCAUSE_TRIGGER) ? 1 : 0; + + } + else { + if ( (dcsr.fields.cause == DCAUSE_EBREAK) + && (*g_single_step_status == 7 + || *g_single_step_status == 8) ) { + *g_ebreak_fail += (mcause.clint.exccode == MCAUSE_BREAKPT) ? 1 : 0; + } + if (dpc == (mtvec & ~0x3UL)) { + if ( *g_single_step_status == 3 + || *g_single_step_status == 9 + || *g_single_step_status == 10 + ) { + // Count illegal instructions in single step test section 3 + *g_illegal_fail += ((*g_single_step_status == 3) && (mcause.clint.exccode == MCAUSE_ILLEGAL)); + // Check for ebreak with correct cause as we ended up in handler. + // If this code branch gets bypassed the check against g_expect_ebreak will fail + *g_expect_ebreak -= ( (*g_single_step_status == 9 || *g_single_step_status == 10) + && mcause.clint.exccode == MCAUSE_BREAKPT) ? 1 : 0; + increment_mepc(0); + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + csrrw zero, dpc, %[mepc] + )" : [mepc] "+r"(mepc)); + cvprintf(V_MEDIUM, "Single step trap: mtvec: %08lx, dpc: %08lx, return addr: %08lx, mcause: %08lx, dcsr: %08lx\n", mtvec & ~0x3UL, dpc, mepc, mcause.raw, dcsr.raw); + } + } + } +} + +// ----------------------------------------------------------------------------- + +void single_step_trigger_setup_dbg(void) { + volatile mcontrol_t mcontrol = { 0 }; + volatile mcontrol_t mcontrol_exp = { 0 }; + + mcontrol_exp = (mcontrol_t) { + .fields.type = 2, + .fields.dmode = 1, + .fields.action = 1, + .fields.m = 1, + .fields.execute = 1 + }; + + __asm__ volatile ( R"( + csrrw zero, tdata2, %[trigger_loc] + csrrw zero, tdata1, %[mcontrol_exp] + csrrs %[mcontrol], tdata1, zero + + )" : + [mcontrol] "=r"(mcontrol.raw) + : [mcontrol_exp] "r"(mcontrol_exp.raw), + [trigger_loc] "r"(&trigger_loc) + ); + + if (mcontrol.raw != mcontrol_exp.raw) { + single_step_fail(6); + cvprintf(V_LOW, "ERROR: mcontrol readback wrong value\n"); + print_tdata1(V_LOW, (tdata1_t *)&mcontrol); + } +} + +// ----------------------------------------------------------------------------- + +void single_step_trigger_entry_dbg(void) { + set_dpc((uint32_t)(&trigger_exit)); +} + +// ----------------------------------------------------------------------------- + +void single_step_fail(uint32_t cause) { + cvprintf(V_LOW, "Single step failure, cause: %0d\n", cause); + *g_single_step_unspec_err |= 1 << cause; +} + +// ----------------------------------------------------------------------------- + +void single_step_stepie_enable_dbg(void) { + volatile dcsr_t dcsr = { 0 }; + + dcsr.fields.stepie = 1; + + __asm__ volatile ( R"( + csrrs zero, dcsr, %[dcsr] + )" :: [dcsr] "r"(dcsr.raw)); +} + +// ----------------------------------------------------------------------------- + +void single_step_stepie_disable_dbg(void) { + volatile dcsr_t dcsr = { 0 }; + dcsr.fields.stepie = 1; + + __asm__ volatile ( R"( + csrrc zero, dcsr, %[dcsr] + )" :: [dcsr] "r"(dcsr.raw)); +} + +// ----------------------------------------------------------------------------- + +void single_step_c_ebreak_dbg(void) { + volatile dcsr_t dcsr = { 0 }; + volatile uint32_t dpc = 0; + + __asm__ volatile ( R"( + csrrs %[dcsr], dcsr, zero + csrrs %[dpc], dpc, zero + )" : [dcsr] "=r"(dcsr.raw), + [dpc] "=r"(dpc)); + + if (dcsr.fields.cause == DCAUSE_EBREAK) { + increment_dpc(2); + } +} + +// ----------------------------------------------------------------------------- + +void single_step_ebreak_dbg(void) { + volatile dcsr_t dcsr = { 0 }; + volatile uint32_t dpc = 0; + + __asm__ volatile ( R"( + csrrs %[dcsr], dcsr, zero + csrrs %[dpc], dpc, zero + )" : [dcsr] "=r"(dcsr.raw), + [dpc] "=r"(dpc)); + + if (dcsr.fields.cause == DCAUSE_EBREAK) { + increment_dpc(4); + } +} + +// ----------------------------------------------------------------------------- + +void increment_dpc(volatile uint32_t incr_val) { + volatile uint32_t dpc = 0; + + __asm__ volatile ( R"( + csrrs %[dpc], dpc, zero + )" : [dpc] "=r"(dpc)); + + if (incr_val == 0) { + // No increment specified, check *dpc instruction + if (((*(uint32_t *)dpc) & 0x3UL) == 0x3UL) { + // non-compressed + dpc += 4; + } else { + // compressed + dpc += 2; + } + } else { + // explicitly requested increment + dpc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, dpc, %[dpc] + )" :: [dpc] "r"(dpc)); +} + +// ----------------------------------------------------------------------------- + +void increment_mepc(volatile uint32_t incr_val) { + volatile uint32_t mepc = 0; + + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + )" : [mepc] "=r"(mepc)); + + if (incr_val == 0) { + // No increment specified, check *mepc instruction + if (((*(uint32_t *)mepc) & 0x3UL) == 0x3UL) { + // non-compressed + mepc += 4; + } else { + // compressed + mepc += 2; + } + } else { + // explicitly requested increment + mepc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, mepc, %[mepc] + )" :: [mepc] "r"(mepc)); +} + +// ----------------------------------------------------------------------------- + +void set_dpc(volatile uint32_t dpc) { + __asm__ volatile ( R"( + csrrw zero, dpc, %[dpc] + )" :: [dpc] "r"(dpc)); + cvprintf(V_MEDIUM, "Setting dpc to %08lx\n", dpc); +} + +// ----------------------------------------------------------------------------- + +void single_step_ebreak_exception_dbg(void) { + volatile dcsr_t dcsr = { 0 }; + + dcsr.fields.ebreakm = 1; + + __asm__ volatile ( R"( + csrrc zero, dcsr, %[dcsr] + )" : [dcsr] "=r"(dcsr.raw)); +} + +// ----------------------------------------------------------------------------- + +void single_step_c_ebreak_exception_dbg(void) { + volatile dcsr_t dcsr = { 0 }; + + // The actual check happens on entry to debug, + // when reaching this point it is safe to assume + // that we can reenable dcsr.ebreakm again + + dcsr.fields.ebreakm = 1; + + __asm__ volatile ( R"( + csrrc zero, dcsr, %[dcsr] + )" :: [dcsr] "r"(dcsr.raw)); +} + +// ----------------------------------------------------------------------------- + +void single_step_disable_dbg(void) { + volatile dcsr_t dcsr; + dcsr.raw = 0; + dcsr.fields.step = 1; + + __asm__ volatile ( R"( + csrrc zero, dcsr, %[dcsr] + )" :: [dcsr] "r"(dcsr.raw)); + + cvprintf(V_LOW, "Disable single step\n"); +} + +// ----------------------------------------------------------------------------- + +void single_step_enable_dbg(void) { + volatile dcsr_t dcsr; + + dcsr.raw = 0; + dcsr.fields.step = 1; + + __asm__ volatile ( R"( + csrrs zero, dcsr, %[dcsr] + )" :: [dcsr] "r"(dcsr.raw) + ); + + // Entered ebreak with c.ebreak, increment + increment_dpc(2); +} + +// ----------------------------------------------------------------------------- + +void single_step_basic_dbg(void) { + volatile dcsr_t dcsr; + volatile dcsr_t dcsr_exp; + volatile uint32_t mtval; + volatile uint32_t dpc; + + dcsr_exp = (dcsr_t){ + .fields.xdebugver = 4, + .fields.ebreakm = 1, + .fields.stopcount = 1, + .fields.cause = 2, // trigger + .fields.mprven = 1, + .fields.step = 1, + .fields.prv = 3 + }; + + __asm__ volatile (R"( + csrrs %[dcsr], dcsr, zero + )" : [dcsr] "=r"(dcsr.raw) + ); + + if (dcsr.raw == dcsr_exp.raw) { + single_step_trigger_entry_dbg(); + } else { + // Check that mtval is always zero + __asm__ volatile (R"( + csrrs %[mtval], mtval, zero + )": [mtval] "=r"(mtval) + :); + + if (mtval != 0) { + single_step_fail(1); + } + + dcsr_exp = (dcsr_t){ + .fields.xdebugver = 4, + .fields.ebreakm = 1, + .fields.stopcount = 1, + .fields.cause = DCAUSE_STEP, + .fields.mprven = 1, + .fields.step = 1, + .fields.prv = MODE_MACHINE + }; + + if (dcsr.raw != dcsr_exp.raw) { + single_step_fail(2); + } + + __asm__ volatile (R"( + csrrs %[dpc], dpc, zero + )": [dpc] "=r"(dpc) + ); + + if ( (dpc == (*g_previous_dpc + 2)) || (dpc == (*g_previous_dpc + 4)) ) { + single_step_fail(3); + } + } + +} + +// ----------------------------------------------------------------------------- + +uint32_t has_pmp_configured(void) { + volatile uint32_t pmpaddr0 = 0xffffffff; + volatile uint32_t pmpaddr0_backup = 0; + volatile uint32_t marchid = 0x0; + + __asm__ volatile (R"( + csrrs %[marchid], marchid, zero + )":[marchid] "=r"(marchid)); + + // CV32E40X does not support PMP, skip test + switch (marchid) { + case (MARCHID_CV32E40X): + return 0; + break; + case (MARCHID_CV32E40S): + ;; // Do nothing and continue execution + break; + } + + __asm__ volatile (R"( + csrrw %[pmpaddr0_backup] , pmpaddr0, %[pmpaddr0] + csrrw %[pmpaddr0], pmpaddr0, %[pmpaddr0_backup] + )" :[pmpaddr0_backup] "+r"(pmpaddr0_backup), + [pmpaddr0] "+r"(pmpaddr0)); + + return (pmpaddr0 != 0); +} + +// ----------------------------------------------------------------------------- + +uint32_t mprv_dret_to_umode(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail; + volatile uint32_t pmpaddr = 0xffffffff; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_debug_test_num = 14; + *g_debug_status = 0; + + // Check if there are configured pmp-regions: + if (!has_pmp_configured()) { + cvprintf(V_LOW, "Skipping test: 0 PMP regions or PMP not supported, cannot enter user mode\n"); + return 0; + } + + // Setup PMP access for u-mode (otherwise all deny) + set_mseccfg((mseccfg_t){ + .fields.mml = 0, + .fields.mmwp = 0, + .fields.rlb = 1, + }); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + __asm__ volatile ( R"( + csrrw zero, pmpaddr0, %[pmpaddr] + )":: [pmpaddr] "r"(pmpaddr)); + + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + // Debug mode, dret to user mode + while ((*g_debug_status & 0x7UL) == 0) { + ;; + } + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + // Debug mode, dret back to machine mode + while ((*g_debug_status & 0x7UL) == 1) { + ;; + } + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + // Debug mode, dret back to user mode + while ((*g_debug_status & 0x7UL) == 2) { + ;; + } + + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + + // Debug mode, dret back to machine mode + while ((*g_debug_status & 0x7UL) == 3) { + ;; + } + + test_fail = (*g_debug_status == 4) ? 0 : 1; + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +void mprv_dret_to_umode_dbg(void) { + volatile dcsr_t dcsr = { 0 }; + volatile dcsr_t dcsr_readback = { 0 }; + volatile mstatus_t mstatus = { 0 }; + + dcsr.fields.prv = MODE_MACHINE; + + // Enter user mode first, set mstatus.mprv and expect it to be cleared + if (*g_debug_status == 0) { + mstatus.clint.mprv = 1; + __asm__ volatile ( R"( + csrrs zero, mstatus, %[mstatus] + csrrc %[dcsr_readback], dcsr, %[dcsr] + )" : [dcsr_readback] "=r"(dcsr_readback.raw) + : [mstatus] "r"(mstatus.raw), + [dcsr] "r"(dcsr.raw)); + *g_debug_status += 1; + if (dcsr_readback.fields.prv != MODE_MACHINE) { + *g_debug_status = (*g_debug_status | 0x01000000); + } + } + + // Enter machine mode when reentering debug mode, readback mstatus.mprv and clear it + else if (*g_debug_status == 1) { + mstatus.clint.mprv = 1; + __asm__ volatile ( R"( + csrrc %[mstatus], mstatus, %[mstatus] + csrrs %[dcsr_readback], dcsr, %[dcsr] + )" : [mstatus] "+r"(mstatus.raw), + [dcsr_readback] "=r"(dcsr_readback.raw) + : [dcsr] "r"(dcsr.raw)); + if (mstatus.clint.mprv != 0) { + cvprintf(V_LOW, "readback: mprv not cleared correctly\n"); + *g_debug_status = (*g_debug_status | 0x40000000); + } + if (dcsr_readback.fields.prv != 0x0) { + *g_debug_status = (*g_debug_status | 0x02000000); + } + *g_debug_status += 1; + } + + // Enter debug mode again, this time with mstatus.mprv cleared + else if (*g_debug_status == 2) { + mstatus.clint.mprv = 1; + __asm__ volatile ( R"( + csrrc zero, mstatus, %[mstatus] + csrrc %[dcsr_readback], dcsr, %[dcsr] + )" :[dcsr_readback] "=r"(dcsr_readback.raw) + :[mstatus] "r"(mstatus.raw), + [dcsr] "r"(dcsr.raw)); + *g_debug_status += 1; + if (dcsr_readback.fields.prv != MODE_MACHINE) { + *g_debug_status = (*g_debug_status | 0x04000000); + } + } + + // Return to machine mode, check that mstatus.mprv i still cleared + else if (*g_debug_status == 3) { + mstatus.clint.mprv = 1; + __asm__ volatile ( R"( + csrrs %[mstatus], mstatus, %[mstatus] + csrrs %[dcsr_readback], dcsr, %[dcsr] + )": [mstatus] "+r"(mstatus.raw), + [dcsr_readback] "=r"(dcsr_readback.raw) + : [dcsr] "r"(dcsr.raw)); + if (mstatus.clint.mprv != 0) { + cvprintf(V_LOW, "readback: mprv not cleared correctly\n"); + *g_debug_status = (*g_debug_status | 0x80000000); + } + if (dcsr_readback.fields.prv != 0x0) { + *g_debug_status = (*g_debug_status | 0x08000000); + } + *g_debug_status += 1; + } + +} + +// ----------------------------------------------------------------------------- + +uint32_t __attribute__((__noinline__)) incr_val(uint32_t * ptr) { + *ptr += 1; + return *ptr; +} + +// ----------------------------------------------------------------------------- + +uint32_t __attribute__((__noinline__)) set_val(uint32_t * ptr, uint32_t val) { + *ptr = val; + return *ptr; +} + +// ----------------------------------------------------------------------------- + +uint32_t __attribute__((__noinline__)) get_dcsr_cause(void) { + volatile dcsr_t dcsr; + __asm__ volatile ( R"( csrrs %[dcsr], dcsr, zero )" : [dcsr] "=r"(dcsr.raw) : :); + cvprintf (V_MEDIUM, "get_dcsr_cause: %0x\n", dcsr.fields.cause); + return (uint32_t)dcsr.fields.cause; +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) _debugger_end(void) { + __asm__ volatile ( R"( + lw a0, debug_exit_msg + lw s1, g_debug_test_num + lw a1, 0(s1) + + call check_mcycle_minstret + + # clear stopcount bit if set by test + addi s2, zero, 12 + bne s1, s2, clear_stopcount_skip + addi s2, zero, 1 << 10 + csrrc zero, dcsr, s2 + + clear_stopcount_skip: + csrrw zero, dscratch1, zero + + 1: auipc s11, %pcrel_hi(_debugger_restore_stack) + addi s11, s11, %pcrel_lo(1b) + jalr zero, 0(s11) + + .globl _debugger_restore_stack_end + _debugger_restore_stack_end: + dret + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((__noinline__)) check_mcycle_minstret(void) { + volatile uint32_t minstret_end_cnt; + volatile uint32_t mcycle_end_cnt; + + __asm__ volatile ( R"( + csrrs %[minstret], minstret, zero + csrrs %[mcycle], mcycle, zero + )": [minstret] "=r"(minstret_end_cnt), + [mcycle] "=r"(mcycle_end_cnt) + ); + if ((minstret_end_cnt != *g_minstret_cnt) || + (mcycle_end_cnt != *g_mcycle_cnt)) { + *g_debug_status = 0; + } +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) _debugger_restore_stack(void) { + __asm__ volatile ( R"( + # Keep return address, remember to recover after return + + lw gp, 64(sp) + + # Restore temporary registers + lw t6, 60(sp) + lw t5, 56(sp) + lw t4, 52(sp) + lw t3, 48(sp) + lw t2, 44(sp) + lw t1, 40(sp) + lw t0, 36(sp) + lw tp, 32(sp) + + # Restore argument registers + lw a7, 28(sp) + lw a6, 24(sp) + lw a5, 20(sp) + lw a4, 16(sp) + lw a3, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + + # Restore debug stack ptr + addi sp, sp, 12 + cm.pop {ra, s0-s11}, 112 + + # restore s0, s1 + csrrs sp, dscratch0, zero + csrrw s0, dscratch1, s0 + + bne zero, s0, 2f + + csrrw s0, dscratch1, s0 + 1: auipc s11, %pcrel_hi(_debugger_restore_stack_end) + addi s11, s11, %pcrel_lo(1b) + jalr zero, 0(s11) + + 2: + jalr zero, 0(s0) + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) _debugger_exception(void) { + __asm__ volatile ( R"( + call debug_exception_handler + + 1: auipc s11, %pcrel_hi(_debugger_end) + addi s11, s11, %pcrel_lo(1b) + jalr zero, 0(s11) + )"); +} + +// ----------------------------------------------------------------------------- + +void debug_exception_handler(void) { + volatile dcsr_t dcsr; + + __asm__ volatile ( R"( + csrrs %[dcsr], dcsr, zero + )" + : [dcsr] "=r"(dcsr.raw) : :); + + switch (*g_debug_test_num) { + case 5: + *g_debug_status = 1; + __asm__ volatile ( R"(csrrw zero, dscratch1, zero)"); + break; + case 6: + *g_debug_status = 1; + break; + case 7: + *g_debug_status = 1; + break; + case 13: + if (dcsr.fields.cause == DCAUSE_TRIGGER) { + single_step_disable_dbg(); + } + default : + break; + } + + cvprintf(V_MEDIUM, "dcsr cause: %0x\n", dcsr.fields.cause); + return; +} + +// ----------------------------------------------------------------------------- + +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no){ + volatile pmpcfg_t temp = { 0 }; + volatile pmpcfg_t pmpcfg = { 0 }; + + pmpcfg.reg_idx[reg_no % 4].cfg = pmpsubcfg.raw; + + temp.reg_idx[reg_no % 4].cfg = 0xff; + + switch (reg_no / 4) { + case 0: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg0, t0 + csrrs zero, pmpcfg0, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 1: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg1, t0 + csrrs zero, pmpcfg1, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 2: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg2, t0 + csrrs zero, pmpcfg2, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 3: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg3, t0 + csrrs zero, pmpcfg3, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 4: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg4, t0 + csrrs zero, pmpcfg4, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + case 5: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg5, t0 + csrrs zero, pmpcfg5, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 6: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg6, t0 + csrrs zero, pmpcfg6, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 7: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg7, t0 + csrrs zero, pmpcfg7, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 8: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg8, t0 + csrrs zero, pmpcfg8, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 9: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg9, t0 + csrrs zero, pmpcfg9, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 10: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg10, t0 + csrrs zero, pmpcfg10, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 11: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg11, t0 + csrrs zero, pmpcfg11, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 12: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg12, t0 + csrrs zero, pmpcfg12, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 13: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg13, t0 + csrrs zero, pmpcfg13, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 14: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg14, t0 + csrrs zero, pmpcfg14, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 15: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg15, t0 + csrrs zero, pmpcfg15, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + } + + cvprintf(V_DEBUG, "Set pmpcfg_vector: 0x%08lx\n", pmpcfg.raw); + return; +} + +// ----------------------------------------------------------------------------- + +void set_mseccfg(mseccfg_t mseccfg){ + + __asm__ volatile ( R"( + csrrs x0, mseccfg, %[cfg_vec] + )" + : + : [cfg_vec] "r"(mseccfg.raw) + :); + + cvprintf(V_DEBUG, "Wrote mseccfg: 0x%08lx\n", mseccfg.raw); +} + +// ----------------------------------------------------------------------------- + +void setup_clic(void) { + if (*g_has_clic == 1) { + __asm__ volatile ( R"( + csrrw zero, 0x307, %[mtvt_table] + )" :: [mtvt_table] "r"(&mtvt_table)); + } +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) mtvt_code(void) { + __asm__ volatile ( R"( + .global mtvt_table + .align 7 + mtvt_table: .long . + 4096 + mtvt_table_1: .long . + 4092 + mtvt_table_2: .long . + 4088 + mtvt_table_3: .long . + 4084 + mtvt_table_4: .long . + 4080 + .space 100, 0x0 + mtvt_table_30: .long . + 3976 + mtvt_table_31: .long . + 3972 + mtvt_table_32: .long . + 3968 + .space 3952, 0x0 + mtvt_table_1021: .long . + 12 + mtvt_table_1022: .long . + 8 + mtvt_table_1023: .long . + 4 + jal zero, m_fast14_irq_handler + )"); + +} + +// ----------------------------------------------------------------------------- + +uint32_t detect_irq_mode(void) { + volatile uint32_t mtvec = 0; + volatile uint32_t is_clic = 0; + + __asm__ volatile ( R"( + csrrs %[mtvec], mtvec, zero + )" : [mtvec] "=r"(mtvec)); + + if ((mtvec & 0x3) == 0x3) { + is_clic = 1; + } + + return is_clic; +} + +// ----------------------------------------------------------------------------- + +// This function should cover corner cases encountered by broken code during +// test development that made the ISS and RTL deviate. After resolving issues, +// leave this function in place to ensure that these issues do not return. +uint32_t cover_known_iss_mismatches(uint32_t index, uint8_t report_name) { + volatile clic_t clic_vector = { 0 }; + volatile debug_req_control_t debug_req_ctrl; + + SET_FUNC_INFO + + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // 1. Mismatch when an interrupt is asserted without its + // irq bit set (clic only) + if (*g_has_clic == 1) { + // Make the vc provoke the clic signals, but not set clic.irq + clic_vector = (clic_t){ + .fields.reserved_31_22 = 0x1FF, + .fields.irq = 0x0, + .fields.id = 0X7FF, + .fields.level = 0xFF, + .fields.priv = MODE_MACHINE, + .fields.shv = 0x1, + }; + + vp_assert_irq(clic_vector.raw, 2); + + // Give the interrupt signals some time + for (volatile int i = 0; i < 20; i++) { + __asm__ volatile ( R"(nop)"); + } + + deassert_irq(); + } + + // 2. dpc lower bit writable + debug_req_ctrl = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, + .fields.rand_pulse_width = 0, + .fields.pulse_width = 0x1fff, + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + + *g_debug_status = 0; + *g_debug_test_num = 18; + DEBUG_REQ_CONTROL_REG = debug_req_ctrl.raw; + while (!*g_debug_status) { + ;; + } + + // Don't flag this test as pass fail, only needs ISS check + + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +void cover_known_iss_mismatches_dbg(void) { + volatile uint32_t temp; + volatile dcsr_t dcsr_backup = { 0 }; + + __asm__ volatile ( R"( + add %[temp], zero, zero + csrrw %[dcsr_bu], dcsr, %[temp] + addi %[temp], zero, -1 + csrrw %[temp], dcsr, %[temp] + csrrw %[temp], dcsr, %[dcsr_bu] + )": [temp] "+r"(temp), + [dcsr_bu] "+r"(dcsr_backup.raw) + ); + + *g_debug_status = 1; +} diff --git a/cv32e40x/tests/programs/custom/generic_exception_test/test.yaml b/cv32e40s/tests/programs/custom/debug_test2/test.yaml similarity index 50% rename from cv32e40x/tests/programs/custom/generic_exception_test/test.yaml rename to cv32e40s/tests/programs/custom/debug_test2/test.yaml index 7d815c16db..5cacfbb7be 100644 --- a/cv32e40x/tests/programs/custom/generic_exception_test/test.yaml +++ b/cv32e40s/tests/programs/custom/debug_test2/test.yaml @@ -1,7 +1,8 @@ # Test definition YAML for test -# Interrupt directed test -name: generic_exception_test +# Debug directed test +name: debug_test2 uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +program: debug_test2 description: > - Generic directed exception test + Debug directed test diff --git a/cv32e40s/tests/programs/custom/debug_test_0_triggers/debug_test_0_trigger.c b/cv32e40s/tests/programs/custom/debug_test_0_triggers/debug_test_0_trigger.c new file mode 100644 index 0000000000..4611f0e9c4 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_test_0_triggers/debug_test_0_trigger.c @@ -0,0 +1,549 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// This file, and derivatives thereof are licensed under the +// Solderpad License, Version 2.0 (the "License"); +// Use of this file means you agree to the terms and conditions +// of the license and are in full compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.0/ +// +// Unless required by applicable law or agreed to in writing, software +// and hardware implementations thereof +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Author: Halfdan Bechmann - halfdan.bechmann@silabs.com // +// // +// Debug 0 Triggers Test // +// // +// Requires: DBG_NUM_TRIG == 0 // +// // +//////////////////////////////////////////////////////////////////////////////// + + +#include +#include +#include +#include "corev_uvmt.h" + +#define FAIL 1 +#define SUCCESS 0 + +#define DEBUG_REQ_CONTROL_REG *(volatile int *) CV_VP_DEBUG_CONTROL_BASE + +#define DEBUG_SEL_IDLE 0 +#define DEBUG_SEL_REGTEST 4 +#define DEBUG_SEL_ENTER_USERMODE 5 +#define DEBUG_SEL_ENTER_MACHINEMODE 6 + +#define DEBUG_STATUS_NOT_ENTERED 0 +#define DEBUG_STATUS_ENTERED_OK 1 +#define DEBUG_STATUS_ENTERED_FAIL 2 + +#define PRIV_LVL_USER_MODE 0 +#define PRIV_LVL_MACHINE_MODE 1 + + // Place in debugger section +void _debugger_start(void) __attribute__((section(".debugger"), naked)); +void _debug_handler(void) __attribute__((section(".debugger"))); +int _debug_mode_register_test(void) __attribute__((section(".debugger"))); + +void _debugger_exception_start(void) __attribute__((section(".debugger_exception"), naked)); + +void handle_illegal_insn(void) __attribute__((naked)); +extern void end_handler_incr_mepc(void); + +volatile uint32_t num_triggers; + +volatile int debug_sel; +volatile int debug_break_loop; +volatile int debug_entry_status; + +volatile uint32_t illegal_insn_status; +volatile uint32_t debug_exception_status; + +/* + * handle_illegal_insn + * + * Illegal Instruction Handler + * + * Sets the illegal_insn_status variable to 1 when an illegal instruction traps + * + */ +void handle_illegal_insn (void) { + __asm__ volatile (R"( + la t0, illegal_insn_status + li t1, 1 + sw t1, 0(t0) + call end_handler_incr_mepc + )" ::: "t0", "t1", "memory"); +} + + +/* + * _debugger_exception_start + * + * Debug exception handler + * + * Handles exceptions that occur in debug mode, generally seen as irrecoverable event + * But used in this test to check register access. Sets debug_exception_status and + * returns to address saved in the debug scratch register (dscratch). + */ +void _debugger_exception_start(void) { + __asm__ volatile (R"( + cm.push {ra, s0-s2}, -16 + + la s1, debug_exception_status + li s0, 1 + sw s0, 0(s1) + + cm.pop {ra, s0-s2}, 16 + csrr t6, dscratch + jr t6 + )" ::: "t6"); +} + +/* + * debugger_start + * + * Debug handler wrapper + * + * Saves registers, calls debug handler and then restores the registers again. + * + */ +void _debugger_start(void) { + __asm__ volatile (R"( + # Store return address and saved registers + + sw a0, -4(sp) + sw a1, -8(sp) + sw a2, -12(sp) + sw a3, -16(sp) + sw a4, -20(sp) + sw a5, -24(sp) + sw a6, -28(sp) + sw a7, -32(sp) + sw t0, -36(sp) + sw t1, -40(sp) + sw t2, -44(sp) + sw t3, -48(sp) + sw t4, -52(sp) + sw t5, -56(sp) + sw t6, -60(sp) + addi sp, sp, -64 + + cm.push {ra, s0-s11}, -64 + + # Execute _debug_handler() function + call ra, _debug_handler + + # Restore return address and saved registers + cm.pop {ra, s0-s11}, 64 + + addi sp, sp, 64 + lw a0, -4(sp) + lw a1, -8(sp) + lw a2, -12(sp) + lw a3, -16(sp) + lw a4, -20(sp) + lw a5, -24(sp) + lw a6, -28(sp) + lw a7, -32(sp) + lw t0, -36(sp) + lw t1, -40(sp) + lw t2, -44(sp) + lw t3, -48(sp) + lw t4, -52(sp) + lw t5, -56(sp) + lw t6, -60(sp) + + # Exit debug mode + dret + )"); +} + +/* + * _debug_handler + * + * Debug Handler + * + * Handles all actions needed in debug mode. + * + */ +void _debug_handler (void) { + + printf(" Entered debug\n"); + + debug_entry_status = DEBUG_STATUS_ENTERED_OK; + + switch (debug_sel) { + + case DEBUG_SEL_REGTEST: + _debug_mode_register_test(); + break; + + case DEBUG_SEL_ENTER_USERMODE: + printf("-- User Mode --\n"); + __asm__ volatile ("csrci dcsr, 0x3"); + break; + + case DEBUG_SEL_ENTER_MACHINEMODE: + printf("-- Machine Mode --\n"); + __asm__ volatile ("csrsi dcsr, 0x3"); + break; + + } + + __asm__ volatile (R"( + # Increment dpc to skip matched instruction + csrr s0, dpc + lb s1, 0(s0) + li s2, 0x3 + and s1, s1, s2 + bne s1, s2, 1f + addi s0, s0, 0x2 + 1:addi s0, s0, 0x2 + csrw dpc, s0 + )" ::: "s0", "s1", "s2"); + + return; +} + + +/* + * execute_debug_command + * + * Sends commands debug handler + * + * Needed to execute commands that require to run with debug privelege + * + */ +void execute_debug_command (uint32_t dbg_cmd) { + // Disable trigger after use + debug_sel = dbg_cmd; + + debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + // Assert debug req + DEBUG_REQ_CONTROL_REG = (CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | + CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | + CV_VP_DEBUG_CONTROL_START_DELAY(0xc8)); + // Wait for debug entry + while (debug_entry_status == DEBUG_STATUS_NOT_ENTERED); +} + +/* + * _debug_mode_register_test + * + * Debug mode register access test + * + * Checks that registers that should not exist cause a trap in debug mode + * + */ +int _debug_mode_register_test(void) { + printf(" _debug_mode_register_test():\n"); + + // TSELECT - Read/write valid value (in debug mode), check that it traps + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrr s0, tselect + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi tselect, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + // TDATA1 - Read/write valid value (in debug mode), check that it traps + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrr s0, tdata1 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi tdata1, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + // TDATA2 - Read/Write valid value (in debug mode), check that it traps + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrr s0, tdata2 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi tdata2, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + // TINFO - Read/Write valid value (in debug mode), check that it traps + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrr s0, tinfo + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi tinfo, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + // TCONTROL - Read/Write valid value (in debug mode), check that it traps + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrr s0, tcontrol + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi tcontrol, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + // Context Registers - Access Checks (in debug mode) + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi mcontext, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi mscontext, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi hcontext, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + debug_exception_status = 0; + __asm__ volatile (R"(la s0, 1f + csrw dscratch, s0 + csrwi scontext, 0x0 + 1:nop)" ::: "s0"); + if (!debug_exception_status) return FAIL; + + return SUCCESS; +} + + +/* + * test_register_access + * + * Register access test + * + * Checks that registers that should not exist + * cause a trap in machine mode and user mode + */ +int test_register_access(void) { + + printf("\n\n\n --- Testing register access ---\n\n"); + + printf(" Checking register access from debug mode\n"); + debug_sel = DEBUG_SEL_REGTEST; + debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + DEBUG_REQ_CONTROL_REG = (CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | + CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | + CV_VP_DEBUG_CONTROL_START_DELAY(0xc8)); + // Wait for debug entry + while (debug_entry_status == DEBUG_STATUS_NOT_ENTERED); + if (debug_entry_status == DEBUG_STATUS_ENTERED_FAIL) return FAIL; + debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + + printf("\n Checking register access from Machine mode\n"); + + // TSELECT - Read/write valid value (in machine mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tselect" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tselect, 0x0"); + if (!illegal_insn_status) return FAIL; + + // TDATA1 - Read/write valid value (in machine mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tdata1" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata1, 0x0"); + if (!illegal_insn_status) return FAIL; + + // TDATA2 - Read/Write valid value (in machine mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tdata2" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata2, 0x0"); + if (!illegal_insn_status) return FAIL; + + // TINFO - Read/Write valid value (in machine mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tinfo" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tinfo, 0x0"); + if (!illegal_insn_status) return FAIL; + + // TCONTROL - Read/Write valid value (in machine mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tcontrol" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tcontrol, 0x0"); + if (!illegal_insn_status) return FAIL; + + // Context Registers - Access Checks (in machine mode) + illegal_insn_status = 0; + __asm__ volatile ("csrwi mcontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi mscontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi hcontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi scontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + execute_debug_command(DEBUG_SEL_ENTER_USERMODE); + + // TSELECT - Read/write valid value (in u-mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tselect" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tselect, 0x0"); + if (!illegal_insn_status) return FAIL; + + // TDATA1 - Read/write valid value (in u-mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tdata1" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata1, 0x0"); + if (!illegal_insn_status) return FAIL; + + + // TDATA2 - Read/Write valid value (in u-mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tdata2" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata2, 0x0"); + if (!illegal_insn_status) return FAIL; + + // TINFO - Read/Write valid value (in u-mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tinfo" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tinfo, 0x0"); + if (!illegal_insn_status) return FAIL; + + // TCONTROL - Read/Write valid value (in u-mode), check that it traps + illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tcontrol" ::: "s0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi tcontrol, 0x0"); + if (!illegal_insn_status) return FAIL; + + // Context Registers - Access Checks (in user mode) + illegal_insn_status = 0; + __asm__ volatile ("csrwi mcontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi mscontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi hcontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + illegal_insn_status = 0; + __asm__ volatile ("csrwi scontext, 0x0"); + if (!illegal_insn_status) return FAIL; + + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + + return SUCCESS; +} + +/* + * pmp_setup + * + * PMP setup function + * + * Allows access to full memory map from user mode + */ +void pmp_setup(void) { + __asm__ volatile (R"(li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 + csrwi pmpcfg0, ((1 << 3) | (7 << 0)) + )" ::: "t0"); +} + + +/* + * main + * + * Test Entry point + * + */ +int main(int argc, char *argv[]) +{ + pmp_setup(); + + if (test_register_access()) { + printf("Register access test failed\n"); + return FAIL; + } + + printf("Finished \n"); + return SUCCESS; +} + diff --git a/cv32e40s/tests/programs/custom/debug_test_0_triggers/test.yaml b/cv32e40s/tests/programs/custom/debug_test_0_triggers/test.yaml new file mode 100644 index 0000000000..d5d11cadc9 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_test_0_triggers/test.yaml @@ -0,0 +1,7 @@ +# Test definition YAML for test + +name: debug_test_0_triggers +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Debug trigger directed test for DBG_NUM_TRIG == 0 + diff --git a/cv32e40s/tests/programs/custom/debug_test_boot_set/debug_test_reset.c b/cv32e40s/tests/programs/custom/debug_test_boot_set/debug_test_reset.c index edf6e2a93a..d8ecd76f89 100644 --- a/cv32e40s/tests/programs/custom/debug_test_boot_set/debug_test_reset.c +++ b/cv32e40s/tests/programs/custom/debug_test_boot_set/debug_test_reset.c @@ -22,6 +22,7 @@ #include #include +#include extern volatile uint32_t test_debugger_entry; diff --git a/cv32e40s/tests/programs/custom/debug_test_reset/debug_test_reset.c b/cv32e40s/tests/programs/custom/debug_test_reset/debug_test_reset.c index edf6e2a93a..d8ecd76f89 100644 --- a/cv32e40s/tests/programs/custom/debug_test_reset/debug_test_reset.c +++ b/cv32e40s/tests/programs/custom/debug_test_reset/debug_test_reset.c @@ -22,6 +22,7 @@ #include #include +#include extern volatile uint32_t test_debugger_entry; diff --git a/cv32e40s/tests/programs/custom/debug_test_reset/debugger.S b/cv32e40s/tests/programs/custom/debug_test_reset/debugger.S index f5a24e9859..518548b918 100644 --- a/cv32e40s/tests/programs/custom/debug_test_reset/debugger.S +++ b/cv32e40s/tests/programs/custom/debug_test_reset/debugger.S @@ -49,14 +49,9 @@ _debugger_trigger_regs_access: li t0, 0xff csrw 0x7a4, t0 # tinfo csrr t0, 0x7a4 - li t1, 4 + li t1, 1<<0x18 | 1<<0xF | 1<<6 | 1<<5 | 1<<2 # Supported trigger types bne t0, t1, _debugger_error - li t0, 0xff - csrw 0x7a3, t0 # tdata3 - csrr t0, 0x7a3 - bne t0, x0, _debugger_error - li t0, 0xff csrw 0x7a0, t0 # tsel csrr t0, 0x7a0 @@ -69,7 +64,7 @@ _debugger_trigger_regs_access: csrrsi t0, 0x7A1, 0x4 # Set bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 + li t1, 2<<28 | 1<<27 | 1<<12 | 1<<2 bne t0, t1, _debugger_error # TDATA1, CSRRCI @@ -77,7 +72,7 @@ _debugger_trigger_regs_access: csrrci t0, 0x7A1, 0x4 # Clear bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 0<<2 + li t1, 2<<28 | 1<<27 | 1<<12 | 0<<2 bne t0, t1, _debugger_error # TDATA1, CSRRS @@ -86,7 +81,7 @@ _debugger_trigger_regs_access: csrrs t0, 0x7A1, t0 # Set bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 + li t1, 2<<28 | 1<<27 | 1<<12 | 1<<2 bne t0, t1, _debugger_error # TDATA1, CSRRC @@ -95,7 +90,7 @@ _debugger_trigger_regs_access: csrrc t0, 0x7A1, t0 # Clear bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 0<<2 + li t1, 2<<28 | 1<<27 | 1<<12 | 0<<2 bne t0, t1, _debugger_error # TDATA1, CSRRWI @@ -103,7 +98,7 @@ _debugger_trigger_regs_access: csrrwi t0, 0x7A1, 0x4 # Set bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 + li t1, 0xF<<28 | 1<<27 # Trigger disabled bne t0, t1, _debugger_error # TDATA1, CSRRW @@ -112,7 +107,7 @@ _debugger_trigger_regs_access: csrrw t0, 0x7A1, t0 bne t0, t1, _debugger_error csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 + li t1, 0xF<<28 | 1<<27 # Trigger disabled bne t0, t1, _debugger_error # TDATA2, CSRRSI @@ -158,56 +153,13 @@ _debugger_trigger_regs_access: li t1, 1<<2 bne t0, t1, _debugger_error - # TDATA3, CSRRSI - csrw 0x7A3, x0 # clear before test - csrr t1, 0x7A3 - csrrsi t0, 0x7A3, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRCI - csrr t1, 0x7A3 - csrrci t0, 0x7A3, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRS - csrr t1, 0x7A3 - li t0, 0xa5a5a5a5 - csrrs t0, 0x7A3, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRC - csrr t1, 0x7A3 - li t0, 0xFFFFFFFF - csrrc t0, 0x7A3, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRWI - csrr t1, 0x7A3 - csrrwi t0, 0x7A3, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - # TINFO, CSRRSI csrw 0x7A4, x0 # clear before test csrr t1, 0x7A4 csrrsi t0, 0x7A4, 0x4 # Set bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A4 - li t1, 4 + li t1, 1<<0x18 | 1<<0xF | 1<<6 | 1<<5 | 1<<2 # Supported trigger types bne t0, t1, _debugger_error # TINFO, CSRRCI @@ -215,7 +167,7 @@ _debugger_trigger_regs_access: csrrci t0, 0x7A4, 0x4 # Clear bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A4 - li t1, 4 + li t1, 1<<0x18 | 1<<0xF | 1<<6 | 1<<5 | 1<<2 # Supported trigger types bne t0, t1, _debugger_error # TINFO, CSRRS @@ -224,7 +176,7 @@ _debugger_trigger_regs_access: csrrs t0, 0x7A4, t0 bne t0, t1, _debugger_error csrr t0, 0x7A4 - li t1, 4 + li t1, 1<<0x18 | 1<<0xF | 1<<6 | 1<<5 | 1<<2 # Supported trigger types bne t0, t1, _debugger_error # TINFO, CSRRC @@ -233,7 +185,7 @@ _debugger_trigger_regs_access: csrrc t0, 0x7A4, t0 bne t0, t1, _debugger_error csrr t0, 0x7A4 - li t1, 4 + li t1, 1<<0x18 | 1<<0xF | 1<<6 | 1<<5 | 1<<2 # Supported trigger types bne t0, t1, _debugger_error # TINFO, CSRRWI @@ -241,7 +193,7 @@ _debugger_trigger_regs_access: csrrwi t0, 0x7A4, 0x4 # Set bit 2 bne t0, t1, _debugger_error csrr t0, 0x7A4 - li t1, 4 + li t1, 1<<0x18 | 1<<0xF | 1<<6 | 1<<5 | 1<<2 # Supported trigger types bne t0, t1, _debugger_error # TSELECT, CSRRSI @@ -437,7 +389,7 @@ _debugger_trigger_regs_access: csrrsi t0, dcsr, 0x4 # Set bit 2 bne t0, t1, _debugger_error csrr t0, dcsr - addi t1, t2, 0x4 + addi t1, t1, 0x4 bne t0, t1, _debugger_error # DCSR, CSRRCI @@ -445,7 +397,6 @@ _debugger_trigger_regs_access: csrrci t0, dcsr, 0x4 # Clear bit 2 bne t0, t1, _debugger_error csrr t0, dcsr - bne t0, t2, _debugger_error # DCSR, CSRRS csrr t1, dcsr @@ -462,18 +413,14 @@ _debugger_trigger_regs_access: li t0, 0x4 csrrc t0, dcsr, t0 bne t0, t1, _debugger_error - csrr t0, dcsr - bne t0, t2, _debugger_error # DCSR, CSRRWI csrr t1, dcsr csrrwi t0, dcsr, 0x4 # Set bit 2 bne t0, t1, _debugger_error csrr t0, dcsr - addi t1, t2, 0x4 - bne t0, t1, _debugger_error - # Restore dpc + # Restore dcsr csrw dcsr, t2 dret diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/debug_test.c b/cv32e40s/tests/programs/custom/debug_test_trigger/debug_test.c deleted file mode 100644 index db5a005051..0000000000 --- a/cv32e40s/tests/programs/custom/debug_test_trigger/debug_test.c +++ /dev/null @@ -1,207 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Basic debugger test. Needs more work and bugs fixed -** It will launch a debug request and have debugger code execute (debugger.S) -******************************************************************************* -*/ - -#include -#include -#include "corev_uvmt.h" - -volatile int glb_hart_status = 0; // Written by main code only, read by debug code -volatile int glb_debug_status = 0; // Written by debug code only, read by main code -volatile int glb_ebreak_status = 0; // Written by ebreak code only, read by main code -volatile int glb_illegal_insn_status = 0; // Written by illegal instruction code only, read by main code -volatile int glb_debug_exception_status = 0; // Written by debug code during exception only -volatile int glb_exception_ebreak_status = 0; // Written by main code, read by exception handler - -// Expectation flags. Raise an error if handler or routine is enterred when not expected, -volatile int glb_expect_illegal_insn = 0; -volatile int glb_expect_ebreak_handler = 0; -volatile int glb_expect_debug_entry = 0; -volatile int glb_expect_debug_exception = 0; -volatile int glb_expect_irq_entry = 0; -// Counter values -// Checked at start and end of debug code -// Only lower 32 bits checked, as simulation cannot overflow on 32 bits -volatile int glb_mcycle_start = 0; -volatile int glb_mcycle_end = 0; -volatile int glb_minstret_start = 0; -volatile int glb_minstret_end = 0; -#define TEST_FAILED *(volatile int *)CV_VP_STATUS_FLAGS_BASE = 1 -#define TEST_PASSED *(volatile int *)CV_VP_STATUS_FLAGS_BASE = 123456789 - -extern int __stack_start; -extern int _trigger_code; -extern int _trigger_code_ebreak; -extern int _trigger_code_cebreak; -extern int _trigger_code_illegal_insn; -extern int _trigger_code_branch_insn; -extern int _trigger_code_multicycle_insn; -typedef union { - struct { - unsigned int start_delay : 15; // 14: 0 - unsigned int rand_start_delay : 1; // 15 - unsigned int pulse_width : 13; // 28:16 - unsigned int rand_pulse_width : 1; // 29 - unsigned int pulse_mode : 1; // 30 0 = level, 1 = pulse - unsigned int value : 1; // 31 - } fields; - unsigned int bits; -} debug_req_control_t; - -#define DEBUG_REQ_CONTROL_REG *(volatile int *) CV_VP_DEBUG_CONTROL_BASE -#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE+0)) -#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE+4)) - -typedef union { - struct { - unsigned int uie : 1; // 0 // Implemented if USER mode enabled - unsigned int sie : 1; // 1 - unsigned int wpri : 1; // 2 - unsigned int mie : 1; // 3 // Implemented - unsigned int upie : 1; // 4 // Implemented if USER mode enabled - unsigned int spie : 1; // 5 - unsigned int wpri0 : 1; // 6 - unsigned int mpie : 1; // 7 // Implemented - unsigned int spp : 1; // 8 - unsigned int wpri1 : 2; // 10: 9 - unsigned int mpp : 2; // 12:11 // Implemented - unsigned int fs : 2; // 14:13 - unsigned int xs : 2; // 16:15 - unsigned int mprv : 1; // 17 - unsigned int sum : 1; // 18 - unsigned int mxr : 1; // 19 - unsigned int tvm : 1; // 20 - unsigned int tw : 1; // 21 - unsigned int tsr : 1; // 22 - unsigned int wpri3 : 8; // 30:23 - unsigned int sd : 1; // 31 - } fields; - unsigned int bits; -} mstatus_t; - -extern void _trigger_test(int d); -extern void _trigger_test_ebreak(int d); -extern void _trigger_test_combo(); -extern void _single_step(int d); -// Tag is simply to help debug and determine where the failure came from -void check_debug_status(int tag, int value) -{ - if(glb_debug_status != value){ - printf("ERROR: check_debug_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_debug_status, value); - TEST_FAILED; - } -} -void check_debug_exception_status(int tag, int value) -{ - if(glb_debug_exception_status != value){ - printf("ERROR: check_debug_exception_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_debug_exception_status, value); - TEST_FAILED; - } -} -void check_hart_status(int tag, int value) -{ - if(glb_hart_status != value){ - printf("ERROR: check_hart_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_hart_status, value); - TEST_FAILED; - } -} -void check_ebreak_status(int tag, int value) -{ - if(glb_ebreak_status != value){ - printf("ERROR: check_ebreak_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_ebreak_status, value); - TEST_FAILED; - } -} -void check_illegal_insn_status(int tag, int value) -{ - if(glb_illegal_insn_status != value){ - printf("ERROR: check_illegal_insn_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_illegal_insn_status, value); - TEST_FAILED; - } -} -void delay(int count) { - for (volatile int d = 0; d < count; d++); -} - -void mstatus_mie_enable() { - int mie_bit = 0x1 << 3; - asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mstatus_mie_disable() { - int mie_bit = 0x1 << 3; - asm volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mie_enable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_disable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_enable(uint32_t irq) { - // Enable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); -} - -void mie_disable(uint32_t irq) { - // Disable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); -} - -void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { - *TIMER_REG_ADDR = mask; - *TIMER_VAL_ADDR = 1 + cycle_delay; -} - -void counters_enable() { - // Enable counters mcycle (bit0) and minstret (bit2) - uint32_t mask = 1<<2 | 1<<0; - asm volatile("csrrc x0, 0x320, %0" : : "r" (mask)); -} -#define MACHINE 3 -int main(int argc, char *argv[]) -{ - debug_req_control_t debug_req_control; - counters_enable(); - - // Enable interrupt - mstatus_mie_enable(); - mie_enable(30); - - // Assembly code from here to get better control of timing - _trigger_test_combo(); - - printf("------------------------\n"); - printf("Finished \n"); - return EXIT_SUCCESS; -} diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/debug_test_trigger.c b/cv32e40s/tests/programs/custom/debug_test_trigger/debug_test_trigger.c new file mode 100644 index 0000000000..e2ccfc9325 --- /dev/null +++ b/cv32e40s/tests/programs/custom/debug_test_trigger/debug_test_trigger.c @@ -0,0 +1,1799 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// This file, and derivatives thereof are licensed under the +// Solderpad License, Version 2.0 (the "License"); +// Use of this file means you agree to the terms and conditions +// of the license and are in full compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.0/ +// +// Unless required by applicable law or agreed to in writing, software +// and hardware implementations thereof +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. +// See the License for the specific language governing permissions and +// limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Author: Halfdan Bechmann - halfdan.bechmann@silabs.com // +// // +// Debug Trigger Test // +// // +// Requires: DBG_NUM_TRIG > 0 // +// // +//////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include "corev_uvmt.h" + +#define FAIL 1 +#define SUCCESS 0 + +#define SETUP_NO 0 +#define SETUP_YES 1 + +#define EXPECT_TRIGGER_NO 0 +#define EXPECT_TRIGGER_YES 1 + +#define DEBUG_PRINT 0 + +#define DEBUG_REQ_CONTROL_REG *(volatile int *) CV_VP_DEBUG_CONTROL_BASE + +#define DEBUG_SEL_IDLE 0 +#define DEBUG_SEL_DISABLE_TRIGGER 1 +#define DEBUG_SEL_SETUP_TRIGGER 2 +#define DEBUG_SEL_CLEAR_TDATA2 3 +#define DEBUG_SEL_REGTEST 4 +#define DEBUG_SEL_ENTER_USERMODE 5 +#define DEBUG_SEL_ENTER_MACHINEMODE 6 + +#define DEBUG_STATUS_NOT_ENTERED 0 +#define DEBUG_STATUS_ENTERED_OK 1 +#define DEBUG_STATUS_ENTERED_FAIL 2 + +#define PRIV_LVL_USER_MODE 0 +#define PRIV_LVL_MACHINE_MODE 1 + +#define DEBUG_LOOPBREAK_NONE 0 +#define DEBUG_LOOPBREAK_TDATA1 1 +#define DEBUG_LOOPBREAK_TDATA2 2 +#define DEBUG_LOOPBREAK_DPCINCR 3 + +#define TRIGGER_NONE 0 +#define TRIGGER_LOAD_BYTE 1 +#define TRIGGER_LOAD_HALFWORD 2 +#define TRIGGER_LOAD_WORD 3 +#define TRIGGER_STORE_BYTE 4 +#define TRIGGER_STORE_HALFWORD 5 +#define TRIGGER_STORE_WORD 6 +#define TRIGGER_EXECUTE 7 +#define TRIGGER_EXCEPTION_ILLEGAL 8 +#define TRIGGER_EXCEPTION_EBREAK 9 + +// --------------------------------------------------------------- +// Type definitions +// --------------------------------------------------------------- + +typedef enum { + MATCH_EQ = 0, + MATCH_GEQ = 2, + MATCH_LESS = 3 +} tdata1_match_t; + +typedef union { + + struct { + volatile uint32_t data : 27; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; // Always F + } __attribute__((packed)) volatile disabled; + + struct { + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t reserved_4_5 : 2; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t reserved_11 : 1; + volatile uint32_t action : 4; + volatile uint32_t reserved_16_26 : 11; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; // Always 2 + } __attribute__((packed)) volatile mcontrol; + + struct { + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t reserved_4_5 : 2; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t reserved_11 : 1; + volatile uint32_t action : 4; + volatile uint32_t reserved_16_26 : 11; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; // Always 6 + } __attribute__((packed)) volatile mcontrol6; + + struct { + volatile uint32_t action : 6; + volatile uint32_t u : 1; + volatile uint32_t reserved_7_8 : 2; + volatile uint32_t m : 1; + volatile uint32_t reserved_10_26 : 17; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; // Always 5 + } __attribute__((packed)) volatile etrigger; + volatile uint32_t raw : 32; +} __attribute__((packed)) tdata1_t; + + +typedef union { + struct { + volatile uint32_t data : 32; + } __attribute__((packed)) volatile disabled; + struct { + volatile uint32_t data : 32; + } __attribute__((packed)) volatile mcontrol; + struct { + volatile uint32_t data : 32; + } __attribute__((packed)) volatile mcontrol6; + struct { + volatile uint32_t reserved_0 : 1; + volatile uint32_t instruction_access_fault : 1; + volatile uint32_t illegal_instruction : 1; + volatile uint32_t breakpoint : 1; + volatile uint32_t reserved_4 : 1; + volatile uint32_t load_access_fault : 1; + volatile uint32_t reserved_6 : 1; + volatile uint32_t store_access_fault : 1; + volatile uint32_t ecall_user_mode : 1; + volatile uint32_t reserved_9_10 : 2; + volatile uint32_t ecall_macine_mode : 1; + volatile uint32_t reserved_12_23 : 12; + volatile uint32_t instruction_bus_fault : 1; + volatile uint32_t instruction_integrity_fault : 1; + volatile uint32_t reserved_26_31 : 6; + } __attribute__((packed)) volatile etrigger; + volatile uint32_t raw : 32; +} __attribute__((packed)) tdata2_t; + +extern void end_handler_incr_mepc(void); + +void _debugger_start(void) __attribute__((section(".debugger"), naked)); +void _debug_handler(void) __attribute__((section(".debugger"))); +void _debug_mode_register_test(void) __attribute__((section(".debugger"))); +void execute_test_high_addr(void) __attribute__((section(".debugger_exception"), noinline)); +void load_store_test_high_addr(void) __attribute__((section(".debugger_exception"), noinline)); + +void handle_illegal_insn(void) __attribute__ ((naked)); + +void execute_test_constructor(void) __attribute__ ((constructor, noinline)); +void load_store_test_constructor(void) __attribute__ ((constructor, noinline)); + +volatile void trigger_code_nop(void) __attribute__((naked, noinline)); +volatile void trigger_code_ebreak(void) __attribute__((naked, noinline)); +volatile void trigger_code_cebreak(void) __attribute__((naked, noinline)); +volatile void trigger_code_branch_insn(void) __attribute__((naked, noinline)); +volatile void trigger_code_illegal_insn(void) __attribute__((naked, noinline)); +volatile void trigger_code_multicycle_insn(void) __attribute__((naked, noinline)); + +int test_execute_trigger(int); +int test_load_trigger(int); +int test_store_trigger(int); +int test_exception_trigger(int); + +volatile tdata1_t g_tdata1_next; +volatile tdata2_t g_tdata2_next; +volatile uint32_t g_tdata2_next_offset; + +volatile int g_trigger_type; +volatile uint32_t g_trigger_address; +volatile uint32_t g_trigger_sel; +volatile uint32_t g_num_triggers; + +volatile int g_debug_sel; +volatile int g_debug_break_loop; +volatile int g_debug_entry_status; + +volatile uint32_t g_illegal_insn_status; +volatile uint32_t g_register_access_status; + +volatile uint8_t g_some_data_bytes[4] = {0xC0, 0xFF, 0xEB, 0xEE}; +volatile uint16_t g_some_data_halfwords[2] = {0xDEAD, 0xBEEF}; +volatile uint32_t g_some_data_word = 0xC0DECAFE; + +/* + * execute_test_constructor + * + * Executes nop. + * + * Defined as constructor to be placed before main in memory + * used for its low address in execute LESS comparisons + */ +void execute_test_constructor(void) { + __asm__ volatile ("nop"); +} + +/* + * execute_test_high_addr + * + * Executes nop. + * + * Placed in debugger_exception section and used for + * its high address in execute test GEQ comparisons + * + */ +void execute_test_high_addr(void) { + __asm__ volatile ("nop"); +} + +/* + * load_store_test_constructor + * + * Uncompressed nop, to be used as variable after construction phase. + * + * Defined as constructor to be placed before main in memory + * used for its low address in load/store LESS comparisons + */ +void load_store_test_constructor(void) { + __asm__ volatile (R"(.option push + .option norvc + nop + .option pop)"); +} +/* + * load_store_test_high_addr + * + * To be used as variable. + * + * Placed in debugger_exception section and used for + * its high address in load/store test GEQ comparisons + */ +void load_store_test_high_addr(void) { + __asm__ volatile (".word(0xDEADBEEF)"); +} + +/* + * handle_illegal_insn + * + * Sets g_illegal_insn_status. + * + * Simple handler used to check illegal intructuction trap + */ +void handle_illegal_insn(void) { + __asm__ volatile (R"( + la t0, g_illegal_insn_status + li t1, 1 + sw t1, 0(t0) + call end_handler_incr_mepc + )"); +} + + +/* + * debugger_start + * + * Debug handler wrapper + * + * Saves registers, calls debug handler and then restores the registers again. + * + */ +void _debugger_start(void) { + __asm__ volatile (R"( + # Store return address and saved registers + + sw a0, -4(sp) + sw a1, -8(sp) + sw a2, -12(sp) + sw a3, -16(sp) + sw a4, -20(sp) + sw a5, -24(sp) + sw a6, -28(sp) + sw a7, -32(sp) + sw t0, -36(sp) + sw t1, -40(sp) + sw t2, -44(sp) + sw t3, -48(sp) + sw t4, -52(sp) + sw t5, -56(sp) + sw t6, -60(sp) + addi sp, sp, -64 + + cm.push {ra, s0-s11}, -64 + + # Execute _debug_handler() function + call ra, _debug_handler + + # Restore return address and saved registers + cm.pop {ra, s0-s11}, 64 + + addi sp, sp, 64 + lw a0, -4(sp) + lw a1, -8(sp) + lw a2, -12(sp) + lw a3, -16(sp) + lw a4, -20(sp) + lw a5, -24(sp) + lw a6, -28(sp) + lw a7, -32(sp) + lw t0, -36(sp) + lw t1, -40(sp) + lw t2, -44(sp) + lw t3, -48(sp) + lw t4, -52(sp) + lw t5, -56(sp) + lw t6, -60(sp) + + # Exit debug mode + dret + )"); +} + +/* + * _debug_handler + * + * Debug Handler + * + * Handles all actions needed in debug mode. + * + */ +void _debug_handler(void) { + + if (DEBUG_PRINT) printf(" Entered debug\n"); + + g_debug_entry_status = DEBUG_STATUS_ENTERED_OK; + + switch (g_debug_sel) { + + case DEBUG_SEL_DISABLE_TRIGGER: + switch (g_trigger_type) { + case TRIGGER_LOAD_BYTE: + case TRIGGER_LOAD_HALFWORD: + case TRIGGER_LOAD_WORD: + __asm__ volatile ("csrci tdata1, (1 << 0)"); // Clear load bit + if (DEBUG_PRINT) printf(" Disabling trigger by clearing TDATA1->LOAD\n"); + break; + case TRIGGER_STORE_BYTE: + case TRIGGER_STORE_HALFWORD: + case TRIGGER_STORE_WORD: + __asm__ volatile ("csrci tdata1, (1 << 1)"); // Clear load bit + if (DEBUG_PRINT) printf(" Disabling trigger by clearing TDATA1->STORE\n"); + break; + case TRIGGER_EXECUTE: + __asm__ volatile ("csrci tdata1, (1 << 2)"); // Clear execute bit + if (DEBUG_PRINT) printf(" Disabling trigger by clearing TDATA1->EXECUTE\n"); + break; + } + break; + + case DEBUG_SEL_SETUP_TRIGGER: + // Load tdata config csrs + if (DEBUG_PRINT) { + printf(" Setting up triggers\n csr_write: tdata1 = 0x%08lx\n csr_write: tdata2 = 0x%08lx (0x%lx + 0x%lx)\n", + g_tdata1_next.raw, g_tdata2_next.raw, g_trigger_address, g_tdata2_next_offset); + } + __asm__ volatile (R"(csrwi tdata2, 0x0 + la s1, g_tdata1_next + lw s0, 0(s1) + csrw tdata1, s0 + la s1, g_tdata2_next + lw s0, 0(s1) + csrw tdata2, s0)" ::: "s0", "s1", "memory"); + break; + + case DEBUG_SEL_CLEAR_TDATA2: + __asm__ volatile ("csrwi tdata2, 0x0"); + if (DEBUG_PRINT) printf(" Disabling trigger by clearing TDATA2\n"); + break; + + case DEBUG_SEL_REGTEST: + _debug_mode_register_test(); + break; + + case DEBUG_SEL_ENTER_USERMODE: + if (DEBUG_PRINT) printf("-- User Mode --\n"); + __asm__ volatile ("csrci dcsr, 0x3"); + break; + + case DEBUG_SEL_ENTER_MACHINEMODE: + if (DEBUG_PRINT) printf("-- Machine Mode --\n"); + __asm__ volatile ("csrsi dcsr, 0x3"); + break; + + } + + switch (g_debug_break_loop) { + case DEBUG_LOOPBREAK_NONE: + break; + case DEBUG_LOOPBREAK_TDATA1: + g_debug_sel = DEBUG_SEL_DISABLE_TRIGGER; + break; + case DEBUG_LOOPBREAK_TDATA2: + // Avoid re-triggering when returning to dpc + g_debug_sel = DEBUG_SEL_CLEAR_TDATA2; + break; + case DEBUG_LOOPBREAK_DPCINCR: + __asm__ volatile (R"( + # Increment dpc to skip matched instruction + csrr s0, dpc + lb s1, 0(s0) + li s2, 0x3 + and s1, s1, s2 + bne s1, s2, 1f + addi s0, s0, 0x2 + 1:addi s0, s0, 0x2 + csrw dpc, s0 + )" ::: "s0", "s1", "s2"); + if (DEBUG_PRINT) printf(" Incrementing dpc\n"); + break; + } + return; +} + +/* + * execute_debug_command + * + * Sends commands debug handler + * + * Needed to execute commands that require to run with debug privelege + * + */ +void execute_debug_command(uint32_t dbg_cmd) { + // Disable trigger after use + g_debug_sel = dbg_cmd; + + g_debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + // Assert debug req + DEBUG_REQ_CONTROL_REG = (CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | + CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | + CV_VP_DEBUG_CONTROL_START_DELAY(0xc8)); + // Wait for debug entry + while (g_debug_entry_status == DEBUG_STATUS_NOT_ENTERED); +} + +/* + * trigger_code_nop + * + * Function for testing execute triggers. + * + * These functions need at least two intructions as the first can be skipped with a dpc inrement + * + */ +volatile void trigger_code_nop() { + __asm__ volatile (R"(nop + nop + ret)"); +} + +/* + * trigger_code_* + * + * Functions with different first instructions for testing execte triggers. + * + * These functions are used to check that different types of instructions are preempted + * correctly with "before"-timing during trigger match + * + */ +volatile void trigger_code_ebreak() { + __asm__ volatile (R"(.option push + .option norvc + ebreak + .option pop + nop + ret)"); +} +volatile void trigger_code_cebreak() { + __asm__ volatile (R"(c.ebreak + nop + ret)"); +} +volatile void trigger_code_branch_insn() { + __asm__ volatile (R"(beq t0, t0, trigger_code_ebreak + nop + ret)"); +} +volatile void trigger_code_illegal_insn() { + __asm__ volatile (R"(dret + nop + ret)"); +} +volatile void trigger_code_multicycle_insn() { + __asm__ volatile (R"(mulhsu t0, t0, t1 + nop + ret)"); +} + +/* + * trigger_test + * + * Test function that configures and tests triggers + * + * Configures triggers based on input and global variables, + * runs test and checks if the result is expected. + * + */ + int trigger_test( int setup, int expect_trigger_match, uint32_t tdata2_arg) { + + if (DEBUG_PRINT) printf ("\ntrigger_test():\n"); + + g_tdata2_next.raw = tdata2_arg + g_tdata2_next_offset; + g_trigger_address = tdata2_arg; + g_debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + + if (setup) { + g_debug_sel = DEBUG_SEL_SETUP_TRIGGER; + + // Assert debug req + DEBUG_REQ_CONTROL_REG = (CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | + CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | + CV_VP_DEBUG_CONTROL_START_DELAY(0xc8)); + // Wait for debug entry + while (g_debug_entry_status == DEBUG_STATUS_NOT_ENTERED); + g_debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + } + + g_debug_sel = DEBUG_SEL_IDLE; + + if (g_trigger_type == TRIGGER_LOAD_BYTE) { + __asm__ volatile (R"(lw s4, g_trigger_address + lb s3, 0(s4) )" ::: "s3", "s4"); + } + if (g_trigger_type == TRIGGER_LOAD_HALFWORD) { + __asm__ volatile (R"(lw s4, g_trigger_address + lh s3, 0(s4) )" ::: "s3", "s4"); + } + if (g_trigger_type == TRIGGER_LOAD_WORD) { + __asm__ volatile (R"(lw s4, g_trigger_address + lw s3, 0(s4) )" ::: "s3", "s4"); + } + if (g_trigger_type == TRIGGER_STORE_BYTE) { + __asm__ volatile (R"(lw s4, g_trigger_address + sb s3, 0(s4) )" ::: "s3", "s4", "memory"); + } + if (g_trigger_type == TRIGGER_STORE_HALFWORD) { + __asm__ volatile (R"(lw s4, g_trigger_address + sh s3, 0(s4) )" ::: "s3", "s4", "memory"); + } + if (g_trigger_type == TRIGGER_STORE_WORD) { + __asm__ volatile (R"(lw s4, g_trigger_address + sw s3, 0(s4) )" ::: "s3", "s4", "memory"); + } + if (g_trigger_type == TRIGGER_EXECUTE) { + __asm__ volatile (R"(lw s4, g_trigger_address + jalr ra, s4 )" ::: "ra", "s4"); // Jump to triggered address + } + if (g_trigger_type == TRIGGER_EXCEPTION_ILLEGAL) { + __asm__ volatile ("csrwi mcontext, 0x0"); + } + if (g_trigger_type == TRIGGER_EXCEPTION_EBREAK) { + __asm__ volatile ("ebreak"); + } + + if (g_debug_entry_status == expect_trigger_match) { + if (DEBUG_PRINT) { + printf (" Debug entry status: %d (expected: %d)\n\n", + g_debug_entry_status, expect_trigger_match); + } + return SUCCESS; + } else { + printf (" FAIL: Debug entry did not match expectation: %d (expected: %d)\n\n", + g_debug_entry_status, expect_trigger_match); + return FAIL; + } +} + +/* + * test_execute_trigger + * + * Execute trigger test + * + * Tests execute triggers with a range of configurations. + * + */ +int test_execute_trigger(int priv_lvl) { + int retval = 0; + g_tdata2_next_offset = 0; + + if (priv_lvl == PRIV_LVL_USER_MODE) { + printf("\n\n\n --- Testing execute triggers (in user mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_USERMODE); + + } else if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + printf("\n\n\n --- Testing execute triggers (in machine mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + } + + // Set up trigger + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.m = 1, // Match in machine mode + .mcontrol6.u = 1, // Match in user mode + .mcontrol6.execute = 1}; // Match on instruction address + + g_trigger_type = TRIGGER_EXECUTE; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + + // Check that executing trigger_code function does not trigger when it is not set up + retval += trigger_test(SETUP_NO, EXPECT_TRIGGER_NO, (uint32_t) &trigger_code_nop); + + // Check that clearing tdata2 prevents re-triggering upon return + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_nop); + + // Check that executing trigger_code function does not trigger when it is disabled in tdata1 + retval += trigger_test(SETUP_NO, EXPECT_TRIGGER_NO, (uint32_t) &trigger_code_nop); + + // Check that executing various instructions at the triggered address causes debug entry + // and make sure it is not executed before entering debug + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_nop); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_ebreak); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_cebreak); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_branch_insn); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_illegal_insn); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_multicycle_insn); + + + + // Trigger on current privilege mode only // + + // Set up trigger + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.execute = 1}; // Match on instruction address + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.mcontrol6.m = 1; // Match in machine mode + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.mcontrol6.u = 1; // Match in user mode + } + g_trigger_type = TRIGGER_EXECUTE; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + + // Check that clearing tdata2 prevents re-triggering upon return + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_nop); + + // Check that executing various instructions at the triggered address causes debug entry + // and make sure it is not executed before entering debug + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_nop); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_ebreak); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_cebreak); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_branch_insn); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_illegal_insn); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &trigger_code_multicycle_insn); + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Executing from start of debug memory to avoid triggering on instructions executed in the the test flow (like debug handler) + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &execute_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &execute_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &execute_test_high_addr); + + g_tdata1_next.mcontrol6.match = MATCH_LESS; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Executing from constructor as it is known to have a lower address than other functions + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &execute_test_constructor); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &execute_test_constructor); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &execute_test_constructor); + + // Test with only oposite privilege mode enabled, expect no matches // + + // Set up trigger + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.execute = 1}; // Match on instruction address + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.mcontrol6.u = 1; // Match in user mode only + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.mcontrol6.m = 1; // Match in machine mode only + } + + // Check that executing trigger address does not trigger in wrong mode + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &trigger_code_nop); + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Executing from start of debug memory to avoid triggering on instructions executed in the the test flow (like debug handler) + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &execute_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &execute_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &execute_test_high_addr); + + execute_debug_command(DEBUG_SEL_DISABLE_TRIGGER); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + + return retval; +} + + +/* + * test_load_trigger + * + * Load trigger test + * + * Tests Load triggers with a range of configurations. + * + */ +int test_load_trigger (int priv_lvl) { + int retval = 0; + + if (priv_lvl == PRIV_LVL_USER_MODE) { + printf("\n\n\n --- Testing load triggers (in user mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_USERMODE); + + } else if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + printf("\n\n\n --- Testing load triggers (in machine mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + } + + // Set up trigger + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.m = 1, // Match in machine mode + .mcontrol6.u = 1, // Match in user mode + .mcontrol6.load = 1}; // Match on load address + + // Check with both machine and user mode + + g_trigger_type = TRIGGER_LOAD_WORD; + g_tdata2_next_offset = 0; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 0; + + g_trigger_type = TRIGGER_LOAD_HALFWORD; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[1]); + + g_trigger_type = TRIGGER_LOAD_BYTE; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[1]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[2]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[3]); + + g_trigger_type = TRIGGER_LOAD_WORD; + + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Loading from start of debug memory to avoid triggering on loads from other variables + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + + g_tdata1_next.mcontrol6.match = MATCH_LESS; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Loading from constructor function as it is known to have a lower address than other variables loaded in test code + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_constructor); + + + // Trigger on current privilege mode only // + + // Set up trigger + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.load = 1}; // Match on load address + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.mcontrol6.m = 1; // Match in machine mode + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.mcontrol6.u = 1; // Match in user mode + } + + g_trigger_type = TRIGGER_LOAD_WORD; + g_tdata2_next_offset = 0; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 0; + + g_trigger_type = TRIGGER_LOAD_HALFWORD; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[1]); + + g_trigger_type = TRIGGER_LOAD_BYTE; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[1]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[2]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[3]); + + g_trigger_type = TRIGGER_LOAD_WORD; + + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Loading from start of debug memory to avoid triggering on loads from other variables + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + + g_tdata1_next.mcontrol6.match = MATCH_LESS; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Loading from constructor function as it is known to have a lower address than other functions + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_constructor); + + + // Test with only oposite privilege mode enabled, expect no matches + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.load = 1}; // Match on load address + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.mcontrol6.u = 1; // Match in user mode only + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.mcontrol6.m = 1; // Match in machine mode only + } + + g_trigger_type = TRIGGER_LOAD_WORD; + g_tdata2_next_offset = 0; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 0; + + g_trigger_type = TRIGGER_LOAD_HALFWORD; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_halfwords[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_halfwords[1]); + + g_trigger_type = TRIGGER_LOAD_BYTE; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[1]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[2]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[3]); + + g_trigger_type = TRIGGER_LOAD_WORD; + + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Loading from start of debug memory to avoid triggering on loads from other variables + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + + g_tdata1_next.mcontrol6.match = MATCH_LESS; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Loading from constructor function as it is known to have a lower address than other functions + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + + + execute_debug_command(DEBUG_SEL_DISABLE_TRIGGER); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + + return retval; +} + + +/* + * test_store_trigger + * + * Store trigger test + * + * Tests store triggers for a range of configurations. + * + */ +int test_store_trigger(int priv_lvl) { + int retval = 0; + + if (priv_lvl == PRIV_LVL_USER_MODE) { + printf("\n\n\n --- Testing store triggers (in user mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_USERMODE); + + } else if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + printf("\n\n\n --- Testing store triggers (in machine mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + } + + // Set up trigger + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.m = 1, // Match in machine mode + .mcontrol6.u = 1, // Match in user mode + .mcontrol6.store = 1}; // Match on load address + + g_trigger_type = TRIGGER_STORE_WORD; + g_tdata2_next_offset = 0; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 0; + + g_trigger_type = TRIGGER_STORE_HALFWORD; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[1]); + + g_trigger_type = TRIGGER_STORE_BYTE; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[1]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[2]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[3]); + + g_trigger_type = TRIGGER_STORE_WORD; + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Storing to unsused debugger_exception section to ensure it is not triggered by variables at higher addresses + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + + g_tdata1_next.mcontrol6.match = MATCH_LESS; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_constructor); + + + // Trigger on current privilege mode only // + + // Set up trigger + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.store = 1}; // Match on load address + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.mcontrol6.m = 1; // Match in machine mode + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.mcontrol6.u = 1; // Match in user mode + } + + g_trigger_type = TRIGGER_STORE_WORD; + g_tdata2_next_offset = 0; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 0; + + g_trigger_type = TRIGGER_STORE_HALFWORD; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_halfwords[1]); + + g_trigger_type = TRIGGER_STORE_BYTE; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[1]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[2]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &g_some_data_bytes[3]); + + g_trigger_type = TRIGGER_STORE_WORD; + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Storing to unsused debugger_exception section to ensure it is not triggered by variables at higher addresses + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + + g_tdata1_next.mcontrol6.match = MATCH_LESS; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, (uint32_t) &load_store_test_constructor); + + + // Test with only oposite privilege mode enabled, expect no matches + g_tdata1_next = (tdata1_t){.mcontrol6.type = 6, // Set to mcontrol6 type + .mcontrol6.match = MATCH_EQ, + .mcontrol6.store = 1}; // Match on load address + + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.mcontrol6.u = 1; // Match in user mode only + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.mcontrol6.m = 1; // Match in machine mode only + } + + g_trigger_type = TRIGGER_STORE_WORD; + g_tdata2_next_offset = 0; + + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA2; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_debug_break_loop = DEBUG_LOOPBREAK_DPCINCR; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_word); + + g_tdata2_next_offset = 0; + + g_trigger_type = TRIGGER_STORE_HALFWORD; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_halfwords[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_halfwords[1]); + + g_trigger_type = TRIGGER_STORE_BYTE; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[0]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[1]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[2]); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &g_some_data_bytes[3]); + + g_trigger_type = TRIGGER_STORE_WORD; + + g_tdata1_next.mcontrol6.match = MATCH_GEQ; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + // Storing to unsused debugger_exception section to ensure it is not triggered by variables at higher addresses + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_high_addr); + + g_tdata1_next.mcontrol6.match = MATCH_LESS; + g_debug_break_loop = DEBUG_LOOPBREAK_TDATA1; + + g_tdata2_next_offset = 0; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = -4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + g_tdata2_next_offset = 4; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, (uint32_t) &load_store_test_constructor); + + execute_debug_command(DEBUG_SEL_DISABLE_TRIGGER); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + + return retval; +} + +/* + * test_exception_trigger + * + * Exception trigger test + * + * Tests Exception triggers with a range of configurations + * + */ +int test_exception_trigger(int priv_lvl) { + int retval = 0; + + if (priv_lvl == PRIV_LVL_USER_MODE) { + printf("\n\n\n --- Testing Exception triggers (in user mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_USERMODE); + + } else if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + printf("\n\n\n --- Testing Exception triggers (in machine mode) ---\n\n"); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + } + + // Set up trigger + g_tdata1_next = (tdata1_t){.etrigger.type = 5, // Set to etrigger type + .etrigger.u = 1, // Match in user mode + .etrigger.m = 1}; // Match in machine mode + + g_tdata2_next_offset = 0; + g_trigger_type = TRIGGER_EXCEPTION_ILLEGAL; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, -1); + + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.breakpoint = 1, + .etrigger.reserved_6 = 1}).raw); + + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.reserved_6 = 1, + .etrigger.reserved_4 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.breakpoint = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.illegal_instruction = 1}).raw); + + g_trigger_type = TRIGGER_EXCEPTION_EBREAK; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, -1); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.breakpoint = 1}).raw); + + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.breakpoint = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + + + // Set up trigger + g_tdata1_next = (tdata1_t){.etrigger.type = 5}; // Set to etrigger type + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.etrigger.m = 1; // Match in machine mode + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.etrigger.u = 1; // Match in user mode + } + + g_tdata2_next_offset = 0; + g_trigger_type = TRIGGER_EXCEPTION_ILLEGAL; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, -1); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.breakpoint = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.reserved_6 = 1, + .etrigger.reserved_4 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.breakpoint = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.illegal_instruction = 1}).raw); + + g_trigger_type = TRIGGER_EXCEPTION_EBREAK; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, -1); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.breakpoint = 1}).raw); + + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_YES, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.breakpoint = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + + // Set up trigger + g_tdata1_next = (tdata1_t){.etrigger.type = 5}; // Set to etrigger type + + if (priv_lvl == PRIV_LVL_MACHINE_MODE) { + g_tdata1_next.etrigger.u = 1; // Match in user mode only + } else if (priv_lvl == PRIV_LVL_USER_MODE){ + g_tdata1_next.etrigger.m = 1; // Match in machine mode only + } + + g_tdata2_next_offset = 0; + g_trigger_type = TRIGGER_EXCEPTION_ILLEGAL; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, -1); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.breakpoint = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.reserved_6 = 1, + .etrigger.reserved_4 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.breakpoint = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.illegal_instruction = 1}).raw); + + g_trigger_type = TRIGGER_EXCEPTION_EBREAK; + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, -1); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.breakpoint = 1}).raw); + + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, ((tdata2_t){.etrigger.illegal_instruction = 1, + .etrigger.breakpoint = 1, + .etrigger.reserved_6 = 1}).raw); + retval += trigger_test(SETUP_YES, EXPECT_TRIGGER_NO, 0); + + + execute_debug_command(DEBUG_SEL_DISABLE_TRIGGER); + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + + return retval; +} + +/* + * _debug_mode_register_test + * + * Debug mode register access test + * + * Checks that registers are implemented according to spec for debug mode + * + */ +void _debug_mode_register_test(void) { + printf(" _debug_mode_register_test():\n"); + + // TDATA1 - Check reset value + __asm__ volatile (R"(csrr s0, tdata1 + li s1, 0x28001000 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 (Type==6) - Write 1s + __asm__ volatile (R"(li s0, 0x6FFFFFFF + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0x6800104F + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 (Type==6) - Write 0s + __asm__ volatile (R"(li s0, 0x60000000 + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0x68001000 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2"); + + // TDATA2 (Type==6) - Address match - Write 1s + __asm__ volatile (R"(li s1, 0xFFFFFFFF + csrw tdata2, s1 + csrr s0, tdata2 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA2 (Type==6) - Address match - Write 0s + __asm__ volatile (R"(csrwi tdata2, 0x0 + csrr s0, tdata2 + beqz s0, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 (Type==2) - Write 1s + __asm__ volatile (R"(li s0, 0x2FFFFFFF + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0x2800104F + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 (Type==2) - Write 0s + __asm__ volatile (R"(li s0, 0x20000000 + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0x28001000 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + + // TDATA2 (Type==2) - Legacy Address match - Write 1s + __asm__ volatile (R"(li s1, 0xFFFFFFFF + csrw tdata2, s1 + csrr s0, tdata2 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA2 (Type==2) - Legacy Address match - Write 0s + __asm__ volatile (R"(csrwi tdata2, 0x0 + csrr s0, tdata2 + beqz s0, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 (Type==5) - Exception Trigger - Write when tdata2 is illegal + __asm__ volatile (R"(csrwi tdata1, 0x0 + li s1, 0xFFFFFFFF + csrw tdata2, s1 + li s0, 0x5FFFFFFF + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0xF8000000 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:csrwi tdata2, 0x0 + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 (Type==5) - Exception Trigger - Write 1s + __asm__ volatile (R"(li s0, 0x5FFFFFFF + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0x58000241 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 (Type==5) - Exception Trigger - Write 0s + __asm__ volatile (R"(li s0, 0x50000000 + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0x58000001 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + + // TDATA2 (Type==5) - Exception Trigger - Write 1s + __asm__ volatile (R"(li s1, 0xFFFFFFFF + csrw tdata2, s1 + csrr s0, tdata2 + li s1, 0x030009AE + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA2 (Type==5) - Exception Trigger - Write 0s + __asm__ volatile (R"(csrwi tdata2, 0x0 + csrr s0, tdata2 + beqz s0, 2f + 1:li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 2:nop + )" ::: "s0", "s1", "s2", "memory"); + // TDATA1 - Write 0s + __asm__ volatile (R"(csrwi tdata1, 0x0 + csrr s0, tdata1 + li s1, 0xF8000000 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA1 - Write 1s + __asm__ volatile (R"(li s0, 0xFFFFFFFF + csrw tdata1, s0 + csrr s1, tdata1 + li s0, 0xF8000000 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2"); + + + // TDATA2 (Disabled) - Write 1s + __asm__ volatile (R"(li s0, 0xFFFFFFFF + csrw tdata2, s0 + csrr s1, tdata2 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TDATA2 (Disabled) - Write 0s + __asm__ volatile (R"(csrwi tdata2, 0x0 + csrr s0, tdata2 + beqz s0, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + // TINFO - Write 1s, Debug Access test + __asm__ volatile (R"(li s1, 0xFFFFFFFF + csrw tinfo, s1 + csrr s0, tinfo + li s1, 0x01008064 + beq s0, s1, 1f + li s1, 0x2 #DEBUG_STATUS_ENTERED_FAIL + sw s1, g_debug_entry_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + + if (g_debug_entry_status == DEBUG_STATUS_ENTERED_FAIL) { + printf("Debug Mode Register test FAILED\n\n"); + } + return; +} + +/* + * test_register_access + * + * Register access test + * + * Checks that registers are implemented according to spec for machine mode and user mode + * + */ +int test_register_access(void) { + + printf("\n\n\n --- Testing register access ---\n\n"); + + if (DEBUG_PRINT) printf(" Checking register access from debug mode\n"); + + g_debug_sel = DEBUG_SEL_REGTEST; + g_debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + DEBUG_REQ_CONTROL_REG = (CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | + CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | + CV_VP_DEBUG_CONTROL_START_DELAY(0xc8)); + // Wait for debug entry + while (g_debug_entry_status == DEBUG_STATUS_NOT_ENTERED); + if (g_debug_entry_status == DEBUG_STATUS_ENTERED_FAIL) return FAIL; + g_debug_entry_status = DEBUG_STATUS_NOT_ENTERED; + + if (DEBUG_PRINT) printf("\n Checking register access from Machine mode\n"); + + // TDATA1 - Write valid value (in m-mode), check that is ignored + g_register_access_status = FAIL; + __asm__ volatile (R"(li s1, 0x60000000 + csrw tdata1, s1 + csrr s0, tdata1 + li s1, 0xF8000000 + bne s0, s1, 1f + li s1, 0x0 #SUCCESS + sw s1, g_register_access_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + if (g_register_access_status != SUCCESS) return FAIL; + + // TDATA2 - Write valid value (in m-mode), check that is ignored + g_register_access_status = FAIL; + __asm__ volatile (R"(li s1, 0xFFFFFFFF + csrw tdata2, s1 + csrr s0, tdata2 + bnez s0, 1f + li s1, 0x0 #SUCCESS + sw s1, g_register_access_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + if (g_register_access_status != SUCCESS) return FAIL; + + // TINFO - Write 0s, machine mode access test + g_register_access_status = FAIL; + __asm__ volatile (R"(li s1, 0x0 + csrw tinfo, s1 + csrr s0, tinfo + li s1, 0x01008064 + bne s0, s1, 1f + li s1, 0x0 #SUCCESS + sw s1, g_register_access_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + if (g_register_access_status != SUCCESS) return FAIL; + + // TDATA1 - Write valid value (in m-mode), check that is ignored + g_register_access_status = FAIL; + __asm__ volatile (R"(li s1, 0x60000000 + csrw tdata1, s1 + csrr s0, tdata1 + li s1, 0xF8000000 + bne s0, s1, 1f + li s1, 0x0 #SUCCESS + sw s1, g_register_access_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + if (g_register_access_status != SUCCESS) return FAIL; + + // TDATA2 - Write valid value (in m-mode), check that is ignored + g_register_access_status = FAIL; + __asm__ volatile (R"(li s1, 0xFFFFFFFF + csrw tdata2, s1 + csrr s0, tdata2 + bnez s0, 1f + li s1, 0x0 #SUCCESS + sw s1, g_register_access_status, s2 + 1:nop + )" ::: "s0", "s1", "s2", "memory"); + if (g_register_access_status != SUCCESS) return FAIL; + + // TINFO - Write 0s, machine mode access test + g_register_access_status = FAIL; + __asm__ volatile (R"(li s1, 0x0 + csrw tinfo, s1 + csrr s0, tinfo + li s1, 0x01008064 + bne s0, s1, 1f + li s1, 0x0 #SUCCESS + sw s1, g_register_access_status, s2 + 1:nop + )" ::: "s0", "s1", "s2"); + if (g_register_access_status != SUCCESS) return FAIL; + + // TDATA3 - Access Checks (in machine mode) - CSR should not exist + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata3, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + // TCONTROL - Access Checks (in machine mode) - CSR should not exist + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tcontrol, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + // Context Registers - Access Checks (in machine mode) + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi mcontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi mscontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi hcontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi scontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + + execute_debug_command(DEBUG_SEL_ENTER_USERMODE); + + // TDATA1 - Read/write valid value (in u-mode), check that it traps + g_illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tdata1" ::: "s0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata1, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + // TDATA2 - Read/Write valid value (in u-mode), check that it traps + g_illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tdata2" ::: "s0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata2, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + // TINFO - Read/Write valid value (in u-mode), check that it traps + g_illegal_insn_status = 0; + __asm__ volatile ("csrr s0, tinfo" ::: "s0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tinfo, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + // TDATA3 - Access Checks (in user mode) - CSR should not exist + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tdata3, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + // TCONTROL - Access Checks (in user mode) - CSR should not exist + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tcontrol, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + // Context Registers - Access Checks (in user mode) + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi mcontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi mscontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi hcontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi scontext, 0x0"); + if (!g_illegal_insn_status) return FAIL; + + execute_debug_command(DEBUG_SEL_ENTER_MACHINEMODE); + + return SUCCESS; +} + +/* + * pmp_setup + * + * PMP setup function + * + * Allows access to full memory map from user mode + */ +void pmp_setup(void) { + // Allow user mode access to full memory map + __asm__ volatile (R"(li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 + csrwi pmpcfg0, ((1 << 3) | (7 << 0)) + )" ::: "t0"); +} + +/* + * get_num_triggers + * + * Get number of triggers + * + * Determine number of triggers implemented by probing tselect + * + */ +void get_num_triggers(void) { + g_illegal_insn_status = 0; + __asm__ volatile ("csrwi tselect, 0x0"); + + if (g_illegal_insn_status) { + g_num_triggers = 0; + } else { + __asm__ volatile (R"( + csrwi tselect, 0x1 + csrwi tselect, 0x2 + csrwi tselect, 0x3 + csrr s2, tselect + la s3, g_num_triggers + sw s2, 0(s3) + + csrwi tselect, 0x0 + )" ::: "s2", "s3", "memory"); + + g_num_triggers++; + } + + printf ("NUM_TRIGGERS = %ld\n", g_num_triggers); + +} + +/* + * main + * + * Test Entry point + * + */ +int main(int argc, char *argv[]) +{ + pmp_setup(); + get_num_triggers(); + + if (g_num_triggers > 0) { + for (int i = 0; i < g_num_triggers; i++) { + + g_trigger_sel = i; + printf ("csr_write: tselect = %ld\n", g_trigger_sel); + __asm__ volatile (R"(lw s2, g_trigger_sel + csrw tselect, s2 )" ::: "s2"); + + if (test_register_access()) { + printf("Register access test failed\n"); + return FAIL; + } + if (test_execute_trigger(PRIV_LVL_MACHINE_MODE)) { + printf("Execute trigger test (machine mode) failed\n"); + return FAIL; + } + if (test_execute_trigger(PRIV_LVL_USER_MODE)) { + printf("Execute trigger test (user mode) failed\n"); + return FAIL; + } + if (test_load_trigger(PRIV_LVL_MACHINE_MODE)) { + printf("Load trigger test (machine mode) failed\n"); + return FAIL; + } + if (test_load_trigger(PRIV_LVL_USER_MODE)) { + printf("Load trigger (user mode) test failed\n"); + return FAIL; + } + if (test_store_trigger(PRIV_LVL_MACHINE_MODE)) { + printf("Store trigger test (machine mode) failed\n"); + return FAIL; + } + if (test_store_trigger(PRIV_LVL_USER_MODE)) { + printf("Store trigger (user mode) test failed\n"); + return FAIL; + } + if (test_exception_trigger(PRIV_LVL_MACHINE_MODE)) { + printf("Exception trigger test (machine mode) failed\n"); + return FAIL; + } + if (test_exception_trigger(PRIV_LVL_USER_MODE)) { + printf("Exception trigger (user mode) test failed\n"); + return FAIL; + } + } + printf("Finished \n"); + return SUCCESS; + } else { + printf("Error: Tselect register does not exist (NUM_TRIGGERS=0 not supported in this test) \n"); + return FAIL; + } +} + diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/debugger.S b/cv32e40s/tests/programs/custom/debug_test_trigger/debugger.S deleted file mode 100644 index fd1a85b09c..0000000000 --- a/cv32e40s/tests/programs/custom/debug_test_trigger/debugger.S +++ /dev/null @@ -1,380 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger code -******************************************************************************* -*/ - -#include "corev_uvmt.h" - -.section .debugger, "ax" -.global _debugger_start -.global glb_debug_status -.global glb_hart_status -.global glb_expect_debug_entry -.global glb_mcycle_start -.global glb_mcycle_end -.global glb_minstret_start -.global glb_minstret_end -.global _trigger_code -.global _trigger_code_ebreak -.global _trigger_code_cebreak -.global _trigger_code_illegal_insn -.global _trigger_code_branch_insn -.global _trigger_code_multicycle_insn -.global __debugger_stack_start -.global _debugger_fail -.global _debugger_end -.set test_fail, 0x1 - -_debugger_start: - // Debugger Stack - csrw dscratch, a0 // dscratch0 - la a0, __debugger_stack_start - //sw t0, 0(a0) - csrw 0x7b3, t0 // dscratch1 - sw t1, 4(a0) - sw t2, 8(a0) - sw a1, 12(a0) - sw a2, 16(a0) - // Check if expecting debug entry - la a1, glb_expect_debug_entry - lw t1, 0(a1) - beq x0,t1,_debugger_fail - - // Read lower 32 bits of mcycle and minstret - // and store in globals for check at exit - csrr t1, mcycle - csrr t2, minstret - la a1, glb_mcycle_start - sw t1, 0(a1) - la a1, glb_minstret_start - sw t2, 0(a1) - - // Determine Test to execute in debugger code based on glb_hart_status - la a2, glb_hart_status - lw t2, 0(a2) - - - // For all other tests, - // Set debug status = hart status - la a1, glb_debug_status - sw t2, 0(a1) - - - li t0,7 - beq t2,t0,_debugger_trigger_setup // Test 7 - - li t0,10 - beq t2,t0, _debugger_trigger_match_no_dpc // Test 10 - - li t0,8 - beq t2,t0,_debugger_trigger_match // Test 8 - - li t0, 81 - beq t2,t0, _debugger_trigger_match_ebreak - - li t0, 82 - beq t2, t0, _debugger_trigger_match_cebreak - - li t0, 83 - beq t2, t0, _debugger_trigger_match_illegal_insn - - li t0, 84 - beq t2, t0, _debugger_trigger_match_branch_insn - - li t0, 85 - beq t2, t0, _debugger_trigger_match_multicycle_insn - - li t0,9 - beq t2,t0, _debugger_trigger_disable // Test 9 - - li t0,13 - beq t2,t0, _debugger_mret_call // Test 13 - - li t0,15 - beq t2,t0, _debugger_trigger_in_debug // Test 15 - - -_debugger_mret_call: - mret // will invoke debugger exception routine - -_debugger_trigger_setup: - // setup address to trigger on - la a1,_trigger_code - csrw tdata2,a1 - li t1, 1<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrw dcsr, t1 - j _debugger_end - -_debugger_trigger_match_no_dpc: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - // Clear the tdata1 execute field (tdata1[2]) to avoid re-entering the trigger when dret executes - csrci tdata1, 0x4 - - j _debugger_end - -_debugger_trigger_match: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code - csrr a2,dpc - bne a1,a2,_debugger_fail - la a1,_trigger_exit - csrw dpc,a1 - - // Setup match addr for next match: ebreak - la a1, _trigger_code_ebreak - csrw tdata2, a1 - j _debugger_end -_debugger_trigger_match_ebreak: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_ebreak - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past ebreak insn - addi a2, a2, 4 - csrw dpc, a2 - - # Setup match addr for next match: c.ebreak - la a1, _trigger_code_cebreak - csrw tdata2, a1 - - j _debugger_end -_debugger_trigger_match_cebreak: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_cebreak - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past c.ebreak insn - addi a2, a2, 2 - csrw dpc, a2 - - # Setup match addr for next match: illegal_insn - la a1, _trigger_code_illegal_insn - csrw tdata2, a1 - - // Disable trigger - //csrw tdata1, x0 - j _debugger_end - -_debugger_trigger_match_illegal_insn: - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_illegal_insn - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past illegal insn (dret, 4 bytes) - addi a2, a2, 4 - csrw dpc, a2 - - # Setup match addr for next match: branch_insn - la a1, _trigger_code_branch_insn - csrw tdata2, a1 - - j _debugger_end - -_debugger_trigger_match_branch_insn: - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_branch_insn - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past illegal branch (beq, 4 bytes) - addi a2, a2, 4 - csrw dpc, a2 - - # Setup match addr for next match: multicycle_insn - la a1, _trigger_code_multicycle_insn - csrw tdata2, a1 - - j _debugger_end - -_debugger_trigger_match_multicycle_insn: - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_multicycle_insn - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past multicycle insn (mulhsu, 4 bytes) - addi a2, a2, 4 - csrw dpc, a2 - - # disable trigger - csrw tdata1, x0 - - j _debugger_end - -_debugger_trigger_disable: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 3 debugger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 3<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - csrw tdata1,x0 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - j _debugger_end - - -_debugger_trigger_in_debug: - // setup address to trigger on - la a1, _debugger_trig_point - csrw tdata2,a1 - li t1, 1<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - // Clear glb_expect_debug_entry - // If we trig, we'll reenter debug and - // test will fail due to 0 flag - la a1, glb_expect_debug_entry - li t1, 0 - sw t1, 0(a1) -_debugger_trig_point: - // Should _not_trig here - nop - // Clear trigger - li t1, 0<<2 - csrw tdata1, t1 - j _debugger_end - -_debugger_trigger_disabled_in_debug: - // setup address to trigger on - la a1, _debugger_trig_point_dis - // Set trig enable to 0 - csrw tdata2,a1 - li t1, 0<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 0 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - // Clear glb_expect_debug_entry - // If we trig, we'll reenter debug and - // test will fail due to 0 flag - la a1, glb_expect_debug_entry - li t1, 0 - sw t1, 0(a1) -_debugger_trig_point_dis: - // Should _not_trig here - nop - // Clear trigger - li t1, 0<<2 - csrw tdata1, t1 - j _debugger_end - -_debugger_end: - // Check counter values. They should have increased while in debug - // regardless of stopcount bit in csr - csrr t1, mcycle - la a1, glb_mcycle_start - lw t2, 0(a1) - sub t1, t1, t2 - beq t1, x0, _debugger_fail - - csrr t1, minstret - la a1, glb_minstret_start - lw t2, 0(a1) - sub t1, t1, t2 - beq t1, x0, _debugger_fail - - // If single stepping, do not clear - la a1, glb_hart_status - lw t0, 0(a1) - li t1, 18 - beq t0, t1, _debugger_end_continue - - // Clear debug entry expectation flag - la a1, glb_expect_debug_entry - sw x0, 0(a1) -_debugger_end_continue: - // Debugger Un-Stack - //lw t0, 0(a0) - la a0, __debugger_stack_start - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - dret -_debugger_fail: //Test Failed - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - nop - nop - nop - nop - diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/debugger_exception.S b/cv32e40s/tests/programs/custom/debug_test_trigger/debugger_exception.S deleted file mode 100644 index d3d1e9dd4c..0000000000 --- a/cv32e40s/tests/programs/custom/debug_test_trigger/debugger_exception.S +++ /dev/null @@ -1,77 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger Exception code -******************************************************************************* -*/ - -#include "corev_uvmt.h" - -.section .debugger_exception, "ax" -.global _debugger_exception_start -.global glb_debug_status -.global glb_hart_status -.global glb_debug_exception_status -.global glb_expect_debug_exception -//.global _debugger_fail -//.global _debugger_end -.set test_fail, 0x1 - -_debugger_exception_start: - // First check to see if exception was expected - la a1, glb_expect_debug_exception - lw t1, 0(a1) - //beq x0,t1,_debugger_fail - beq x0,t1,_debugger_exception_fail - - // Set exception status to hart status - la a1, glb_hart_status - lw t1, 0(a1) - la a2, glb_debug_exception_status - sw t1, 0(a2) - - //j _debugger_end - j _debugger_exception_end - -// Should be exact same function as implmented in debugger.S - // I can't seem to point to that symble from this file -_debugger_exception_end: - // Clear debug entry expectation flag - la a1, glb_expect_debug_entry - sw x0, 0(a1) - la a1, glb_expect_debug_exception - sw x0, 0(a1) - // Debugger Un-Stack - //lw t0, 0(a0) - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - dret -// Should be exact same function as implmented in debugger.S -_debugger_exception_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - nop - nop - nop - nop - diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/handlers.S b/cv32e40s/tests/programs/custom/debug_test_trigger/handlers.S deleted file mode 100644 index bebe00743a..0000000000 --- a/cv32e40s/tests/programs/custom/debug_test_trigger/handlers.S +++ /dev/null @@ -1,348 +0,0 @@ -/* -* Copyright 2019 ETH Zürich and University of Bologna -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include "corev_uvmt.h" - -/* Exception codes */ -#define EXCEPTION_ILLEGAL_INSN 2 -#define EXCEPTION_BREAKPOINT 3 -#define EXCEPTION_ECALL_M 11 - -.section .text.handlers -.global __no_irq_handler -.global u_sw_irq_handler -.global m_software_irq_handler -.global m_timer_irq_handler -.global m_external_irq_handler -.global m_fast0_irq_handler -.global m_fast1_irq_handler -.global m_fast2_irq_handler -.global m_fast3_irq_handler -.global m_fast4_irq_handler -.global m_fast5_irq_handler -.global m_fast6_irq_handler -.global m_fast7_irq_handler -.global m_fast8_irq_handler -.global m_fast9_irq_handler -.global m_fast10_irq_handler -.global m_fast11_irq_handler -.global m_fast12_irq_handler -.global m_fast13_irq_handler -.global m_fast14_irq_handler -.global m_fast15_irq_handler - -.weak m_software_irq_handler -.weak m_timer_irq_handler -.weak m_external_irq_handler -.weak m_fast0_irq_handler -.weak m_fast1_irq_handler -.weak m_fast2_irq_handler -.weak m_fast3_irq_handler -.weak m_fast4_irq_handler -.weak m_fast5_irq_handler -.weak m_fast6_irq_handler -.weak m_fast7_irq_handler -.weak m_fast8_irq_handler -.weak m_fast9_irq_handler -.weak m_fast10_irq_handler -.weak m_fast11_irq_handler -.weak m_fast12_irq_handler -.weak m_fast13_irq_handler -.weak m_fast14_irq_handler -.weak m_fast15_irq_handler - -.global glb_illegal_insn_status -.global glb_ebreak_status -.global glb_expect_illegal_insn -.global glb_expect_ebreak_handler -.global glb_exception_ebreak_status -.global glb_expect_irq_entry -.set test_fail, 0x1 - -/* exception handling */ -__no_irq_handler: - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - - la a0, no_exception_handler_msg - jal ra, puts - - // Check if we expected to enter irq - la a1, glb_expect_irq_entry - lw t0, 0(a1) - beq t0, x0, _irq_fail - - // Clear entry flag - li t0, 0 - sw t0, 0(a1) - //j __no_irq_handler - - // Return - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret - -_irq_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - ret - -u_sw_irq_handler: - /* While we are still using puts in handlers, save all caller saved - regs. Eventually, some of these saves could be deferred. */ - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr t0, mcause - li t1, EXCEPTION_ILLEGAL_INSN - beq t0, t1, handle_illegal_insn - li t1, EXCEPTION_ECALL_M - beq t0, t1, handle_ecall - li t1, EXCEPTION_BREAKPOINT - beq t0, t1, handle_ebreak - j handle_unknown - -handle_ecall: - la a0, ecall_msg - jal ra, handle_syscall - j end_handler_incr_mepc - -m_software_irq_handler: - j __no_irq_handler - -m_timer_irq_handler: - j __no_irq_handler - -m_external_irq_handler: - j __no_irq_handler - -m_fast0_irq_handler: - j __no_irq_handler - -m_fast1_irq_handler: - j __no_irq_handler - -m_fast2_irq_handler: - j __no_irq_handler - -m_fast3_irq_handler: - j __no_irq_handler - -m_fast4_irq_handler: - j __no_irq_handler - -m_fast5_irq_handler: - j __no_irq_handler - -m_fast6_irq_handler: - j __no_irq_handler - -m_fast7_irq_handler: - j __no_irq_handler - -m_fast8_irq_handler: - j __no_irq_handler - -m_fast9_irq_handler: - j __no_irq_handler - -m_fast10_irq_handler: - j __no_irq_handler - -m_fast11_irq_handler: - j __no_irq_handler - -m_fast12_irq_handler: - j __no_irq_handler - -m_fast13_irq_handler: - j __no_irq_handler - -m_fast14_irq_handler: - j __no_irq_handler - -m_fast15_irq_handler: - j __no_irq_handler - - -handle_ebreak: - /* TODO support debug handling requirements. */ - la a0, ebreak_msg - jal ra, puts - // Check if expecting ebreak handler - la a0, glb_expect_ebreak_handler - lw t0, 0(a0) - bne t0, x0, cont_handle_ebreak - // Not expecting ebreak, assert test failed - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) - j end_handler_incr_mepc -cont_handle_ebreak: - //increment hart status - sw x0, 0(a0) - la a0, glb_ebreak_status - lw t0, 0(a0) - addi t0,t0,1 - sw t0, 0(a0) - j end_handler_incr_mepc - - - -handle_illegal_insn: - la a0, illegal_insn_msg - jal ra, puts - // Check if expecting illegal instruction - la a0, glb_expect_illegal_insn - lw t0, 0(a0) - bne t0, x0, cont_illegal_insn - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) //Test Failed - j end_handler_incr_mepc -cont_illegal_insn: - //increment hart status - sw x0, 0(a0) - la a0, glb_illegal_insn_status - lw t0, 0(a0) - addi t0,t0,1 - sw t0, 0(a0) - - // Check if we are expected to execute ebreak - la a0, glb_exception_ebreak_status - lw t0, 0(a0) - // End handler if no ebreak is to be executed - beq t0, x0, end_handler_incr_mepc - - // Clear ebreak flag - sw x0, 0(a0) - // Execute ebreak - .4byte 0x00100073 - // Exit handler - j end_handler_incr_mepc - - j end_handler_incr_mepc - - - - - - - -handle_unknown: - la a0, unknown_msg - jal ra, puts - /* We don't know what interrupt/exception is being handled, so don't - increment mepc. */ - j end_handler_ret - - - - - - -end_handler_incr_mepc: - csrr t0, mepc - lb t1, 0(t0) - li a0, 0x3 - and t1, t1, a0 - /* Increment mepc by 2 or 4 depending on whether the instruction at mepc - is compressed or not. */ - bne t1, a0, end_handler_incr_mepc2 - addi t0, t0, 2 -end_handler_incr_mepc2: - addi t0, t0, 2 - csrw mepc, t0 -end_handler_ret: - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret -/* this interrupt can be generated for verification purposes, random or when the - PC is equal to a given value*/ -verification_irq_handler: - mret - -.section .rodata -illegal_insn_msg: - .string "illegal instruction exception handler entered\n" -ecall_msg: - .string "ecall exception handler entered\n" -ebreak_msg: - .string "ebreak exception handler entered\n" -unknown_msg: - .string "unknown exception handler entered\n" -no_exception_handler_msg: - .string "no exception handler installed\n" diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml b/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml index 332d7f4107..3fd76f835d 100644 --- a/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml +++ b/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml @@ -1,6 +1,3 @@ -# Test definition YAML for test - -# Debug trigger directed test name: debug_test_trigger uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/trigger_code.S b/cv32e40s/tests/programs/custom/debug_test_trigger/trigger_code.S deleted file mode 100644 index c35ffd29c8..0000000000 --- a/cv32e40s/tests/programs/custom/debug_test_trigger/trigger_code.S +++ /dev/null @@ -1,567 +0,0 @@ -#Copyright 202[x] Silicon Labs, Inc. -# -#This file, and derivatives thereof are licensed under the -#Solderpad License, Version 2.0 (the "License"); -#Use of this file means you agree to the terms and conditions -#of the license and are in full compliance with the License. -#You may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.0/ -# -#Unless required by applicable law or agreed to in writing, software -#and hardware implementations thereof -#distributed under the License is distributed on an "AS IS" BASIS, -#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. -#See the License for the specific language governing permissions and -#limitations under the License. - -#include "corev_uvmt.h" - -.section .trigger_code_sect, "ax" -.set test_ret_val, CV_VP_STATUS_FLAGS_BASE -.set test_fail, 0x1 -.set timer_reg_addr, CV_VP_INTR_TIMER_BASE -.set timer_val_addr, CV_VP_INTR_TIMER_BASE+4 -.set debug_req_reg, CV_VP_DEBUG_CONTROL_BASE -.global _trigger_exit -.global _trigger_test -.global _trigger_code -.global _trigger_test_ebreak -.global _trigger_code_ebreak -.global _trigger_code_illegal_insn -.global _trigger_code_branch_insn -.global _trigger_code_multicycle_insn -.global _trigger_code_cebreak -.global _trigger_test_combo -.global glb_hart_status -.global glb_expect_debug_entry -.global glb_expect_irq_entry -.global glb_expect_illegal_insn -.global glb_debug_status -.type _trigger_code, @function -.type _trigger_code_ebreak, @function -.type _trigger_code_cebreak, @function -.type _trigger_code_illegal_insn, @function -.type _trigger_code_branch_insn, @function -.type _trigger_code_multicycle_insn, @function -#.type _trigger_test_combo, @function - -_trigger_code_ebreak: - .4byte 0x00100073 - ret - -_trigger_code_cebreak: - c.ebreak - ret - -_trigger_code_illegal_insn: - dret - ret - -_trigger_code_branch_insn: - beq t0, t1, __trigger_fail - ret - -_trigger_code_multicycle_insn: - mulhsu t0, t0, t1 - ret - -_trigger_test_ebreak: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - # a0 holds argument - # 0 - ebreak - # 1 - c.c.ebreak - # 2 - illegal instruction - # 3 - branch instruction - # 4 - multicycle instruction (mulhsu) - - mv t1, a0 - li t0, 0 - beq t0, t1, _jmp_ebreak - - li t0, 1 - beq t0, t1, _jmp_cebreak - - li t0, 2 - beq t0, t1, _jmp_illegal_insn - - li t0, 3 - beq t0, t1, _jmp_branch_insn - - li t0, 4 - beq t0, t1, _jmp_multicycle_insn - -_jmp_ebreak: - jal ra, _trigger_code_ebreak - j __trigger_done -_jmp_cebreak: - jal ra, _trigger_code_cebreak - j __trigger_done -_jmp_illegal_insn: - jal ra, _trigger_code_illegal_insn - j __trigger_done -_jmp_branch_insn: - jal ra, _trigger_code_branch_insn - j __trigger_done -_jmp_multicycle_insn: - jal ra, _trigger_code_multicycle_insn - j __trigger_done - -# Enter debug mode to set tdata1 and tdata2 for triggering on execution of instruction at _trigger_code -_trigger_setup: - addi sp,sp,-8 - sw ra, 4(sp) - - # Don't expect trigger match - li a0, 0 - jal ra, _trigger_test - - # Setup trigger - la a1, glb_hart_status - li t0, 7 - sw t0, 0(a1) - - # expect debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # Assert debug_req - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0xc8) - sw t0, 0(a1) -_wait1: - la a1, glb_hart_status - lw t0, 0(a1) - la a1, glb_debug_status - lw t1, 0(a1) - bne t0, t1, _wait1 - - // Check csrs - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 - bne t0, t1, __trigger_fail - - csrr t0, 0x7A2 - la t1, _trigger_code - bne t0, t1, __trigger_fail - - lw ra, 4(sp) - addi sp,sp,8 - - ret - -# Assembly code for generating -# cycle accurate debug_req -# and irq -_trigger_test_combo: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - jal ra, _trigger_setup - - # ---------------------------------------------------- - # Test 10: Expect trigger and return to the same instruction - # Debugger will clear tdata[2] to avoid re-triggering upon return - # ---------------------------------------------------- - la a1, glb_hart_status - li t0, 10 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # execute trigger code - li a0, 0 - jal ra, _trigger_test - - # Re-set the triger to re-enable - jal ra, _trigger_setup - - # ---------------------------------------------------- - # Test 8: Expect trigger with dpc changed in debugger handler to avoid - # ---------------------------------------------------- - la a1, glb_hart_status - li t0, 8 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # execute trigger code - li a0, 1 - jal ra, _trigger_test - -_wait2: - la a1, glb_hart_status - lw t0, 0(a1) - la a1, glb_debug_status - lw t1, 0(a1) - bne t0, t1, _wait2 - - # Setup trigger again - la a1, glb_hart_status - li t0, 7 - sw t0, 0(a1) - - # expect debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # Assert debug_req - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0xc8) - sw t0, 0(a1) -_wait3: - la a1, glb_hart_status - lw t0, 0(a1) - la a1, glb_debug_status - lw t1, 0(a1) - bne t0, t1, _wait3 - - # ---------------------------------------------------- - # debug_req and trigger on same cycle - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 8 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x5) - sw t0, 0(a1) - - # Call trigger function - li a0, 1 - jal ra, _trigger_code - - # ---------------------------------------------------- - # debug_req and irq when trigger on ebreak - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 81 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # ---------------------------------------------------- - # Enable debug_req in VP - # ---------------------------------------------------- - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1c) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 18 - sw t0, 0(a1) - - # Call trigger function - li a0, 0 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on c.ebreak - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 82 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1c) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 19 - sw t0, 0(a1) - - # Call trigger function - li a0, 1 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on illegal insn - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 83 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x20) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 23 - sw t0, 0(a1) - - # Call trigger function - li a0, 2 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on branch insn - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 84 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x20) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 23 - sw t0, 0(a1) - - # Call trigger function - li a0, 3 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on multicycle insn - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 85 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x24) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 27 - sw t0, 0(a1) - - # Call trigger function - li a0, 4 - jal ra, _trigger_test_ebreak - - # Trigger disabled - la a1, glb_hart_status - li t0, 9 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1) - sw t0, 0(a1) - nop - nop - nop - - li a0, 0 - jal ra, _trigger_test - - la a1, glb_debug_status - lw t0, 0(a1) - li t1, 9 - bne t0, t1, __trigger_fail - - # ---------------------------------------------------- - # trigger match in debug mode - # ---------------------------------------------------- - la a1, glb_hart_status - li t0, 15 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1) - sw t0, 0(a1) - nop - nop - - la a1, glb_debug_status - lw t0, 0(a1) - li t1, 15 - bne t0, t1, __trigger_fail - - j __trigger_done - - - // We will trigger on the _trigger_code addess - // We should not expect the first instruction to execute - // The debugger code will move the PC to the trigger_exit_code - // We will trigger on the _trigger_code addess -_trigger_code: - add a2,a0,a1 - ret -_trigger_exit: - ret -_trigger_test: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - // a0 holds input to function (expect trigger) - mv t1, a0 - - // Load up some random data to add - li a0, 7893 - li a1, 1452 - li a2, 191 // a2 value will be overwrriten by _trigger_code - mv t2, a2 // keep a copy of the value to compare against - - // Call function that will have a trigger match - // If no trigger match, then a2=a0+a1 - // Else if trigger matched, then a2 is not modified - jal ra, _trigger_code - - // if (expect trigger) check against original value (in t2) - bne t1 ,x0, __trigger_check - // else - // trigger match not expected, function executes as normal - // set execpted value to t2 = a0 + a1 - add t2, a0, a1 -__trigger_check: - beq t2,a2,__trigger_done -__trigger_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) -__trigger_done: - lw t0, 0(sp) - lw t1, 4(sp) - lw a0, 8(sp) - lw a1, 12(sp) - lw a2, 16(sp) - lw ra, 20(sp) - addi sp,sp,30 - ret diff --git a/cv32e40s/tests/programs/custom/dhrystone/dhrystone.c b/cv32e40s/tests/programs/custom/dhrystone/dhrystone.c index a74cfaa0aa..dcf4da7714 100644 --- a/cv32e40s/tests/programs/custom/dhrystone/dhrystone.c +++ b/cv32e40s/tests/programs/custom/dhrystone/dhrystone.c @@ -16,6 +16,7 @@ */ #include "stdio.h" #include +#include #include "corev_uvmt.h" /* diff --git a/cv32e40s/tests/programs/custom/fencei/fencei.c b/cv32e40s/tests/programs/custom/fencei/fencei.c index 718c7ca75b..702d3c1054 100644 --- a/cv32e40s/tests/programs/custom/fencei/fencei.c +++ b/cv32e40s/tests/programs/custom/fencei/fencei.c @@ -16,6 +16,7 @@ // SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 #include +#include #include #include "corev_uvmt.h" diff --git a/cv32e40s/tests/programs/custom/fibonacci/fibonacci.c b/cv32e40s/tests/programs/custom/fibonacci/fibonacci.c index c803377ea3..1d2dce70db 100644 --- a/cv32e40s/tests/programs/custom/fibonacci/fibonacci.c +++ b/cv32e40s/tests/programs/custom/fibonacci/fibonacci.c @@ -17,6 +17,7 @@ */ #include +#include #include static int fib(int i) { diff --git a/cv32e40s/tests/programs/custom/generic_exception_test/test.yaml b/cv32e40s/tests/programs/custom/generic_exception_test/test.yaml index 7d815c16db..6aa55b1384 100644 --- a/cv32e40s/tests/programs/custom/generic_exception_test/test.yaml +++ b/cv32e40s/tests/programs/custom/generic_exception_test/test.yaml @@ -5,3 +5,4 @@ name: generic_exception_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Generic directed exception test +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/hello-world/hello-world.c b/cv32e40s/tests/programs/custom/hello-world/hello-world.c index e65e32bb53..78d1d44f8c 100644 --- a/cv32e40s/tests/programs/custom/hello-world/hello-world.c +++ b/cv32e40s/tests/programs/custom/hello-world/hello-world.c @@ -25,14 +25,16 @@ */ #include +#include #include -#define EXP_MISA 0x40101104 +#define EXP_MISA 0x40901104 int main(int argc, char *argv[]) { - unsigned int misa_rval, mvendorid_rval, marchid_rval, mimpid_rval, mxl; - int reserved, tentative, nonstd, user, super; + + volatile unsigned int misa_rval, mvendorid_rval, marchid_rval, mimpid_rval, mxl; + volatile int reserved, tentative, nonstd, user, super; mxl = 0; reserved = 0; tentative = 0; nonstd = 0; user = 0; super = 0; @@ -54,7 +56,7 @@ int main(int argc, char *argv[]) return EXIT_FAILURE; } - /* Check MARCHID CSR: 0x4 is the value assigned by the RISC-V Foundation to CV32E40S */ + /* Check MARCHID CSR: 0x15 is the value assigned by the RISC-V Foundation to CV32E40S */ if (marchid_rval != 0x15) { printf("\tERROR: CSR MARCHID reads as 0x%x - should be 0x00000015 for CV32E40S.\n\n", marchid_rval); return EXIT_FAILURE; diff --git a/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c b/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c index 3d5c439144..ba68d5f4fe 100644 --- a/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c +++ b/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c @@ -22,6 +22,10 @@ ** ** Very basic sanity check for: ** +** - Retired instruction counter +** - Cycle counter +** +** This test is derived from a test that also checked the hpmcounters on 40x; where it tested: ** - Count load use hazards ** - Count jump register hazards ** - Count memory read transactions @@ -30,16 +34,15 @@ ** - Count branches (conditional) ** - Count branches taken (conditional) ** - Compressed instructions -** - Retired instructions ** -** Make sure to instantiate cv32e40s_wrapper with the parameter -** NUM_MHPMCOUNTERS = 1 (or higher) +** The test is therefore unnecessarily complex for the task ** ******************************************************************************* */ #include #include +#include #include static int chck(unsigned int is, unsigned int should) @@ -57,51 +60,24 @@ int main(int argc, char *argv[]) { int err_cnt = 0; - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - volatile unsigned int event; - volatile unsigned int count; volatile unsigned int minstret; - volatile unsigned int count_while_on; volatile unsigned int mcycle_count; - __asm__ volatile(".option rvc"); - ////////////////////////////////////////////////////////////// // Cycle count printf("\nCycle count"); // Setup events and set csrs to 0 - event = EVENT_CYCLES; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB00, 0x0"); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); // Readback Counter to verify 0 __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nCheck proper zeroization\n"); err_cnt += chck(minstret, 0); - err_cnt += chck(count, 0); - err_cnt += chck(count, mcycle_count); + err_cnt += chck(mcycle_count, 0); // Enable counters __asm__ volatile("csrwi 0x320, 0x0"); @@ -111,26 +87,20 @@ int main(int argc, char *argv[]) addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("\nCycle count while running = %d", count); printf("\nMCYCLE counted cycles = %d\n", mcycle_count); - err_cnt += chck(count, mcycle_count); - err_cnt += chck(count, 6); + err_cnt += chck(mcycle_count, 5); ////////////////////////////////////////////////////////////// // IF_INVALID printf("\nIF_INVALID"); - event = EVENT_IF_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("addi t1, x0, 0\n\t\ @@ -140,22 +110,16 @@ int main(int argc, char *argv[]) nop" \ : : : "t0", "t1"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4 + (2*5)); - printf("\nUnderutilized cycles on ID-stage due to IF stage = %d\n", count); - err_cnt += chck(count, 4); ////////////////////////////////////////////////////////////// // ID_INVALID - LD_STALL printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("lw x4, 0(sp)\n\t\ @@ -164,22 +128,16 @@ int main(int argc, char *argv[]) addi x7, x0, 1" \ : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck(count, 2); ////////////////////////////////////////////////////////////// // ID_INVALID - JR STALL printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("auipc x4, 0\n\t\ @@ -187,23 +145,17 @@ int main(int argc, char *argv[]) nop" \ : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck(count, 3); ////////////////////////////////////////////////////////////// // EX_INVALID printf("\nEX_INVALID"); - event = EVENT_EX_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("lw x0, 0(x0)"); @@ -227,23 +179,17 @@ int main(int argc, char *argv[]) __asm__ volatile("rem x0, x31, x30"); // 32 cycles __asm__ volatile("lw x0, 0(sp)"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 21); - printf("\nUnderutilized cycles on WB-stage due to EX stage = %d\n", count); - err_cnt += chck(count, 104); ////////////////////////////////////////////////////////////// // WB_INVALID Write port underutilization printf("\nWrite port underutilization"); - event = EVENT_WB_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("li x31, 1\n\t\ @@ -253,23 +199,17 @@ int main(int argc, char *argv[]) sw x29, 0(sp)" \ : : : "x28", "x29", "x30", "x31"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 6); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck(count, 34); ////////////////////////////////////////////////////////////// // WB_DATA_STALL Write port underutilization due to data_rvalid_i (0) printf("\nWrite port underutilization due to data_rvalid_i"); - event = EVENT_WB_DATA_STALL; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters // Do not count stall cycles (WB_INVALID) due to multicycle instructions @@ -289,35 +229,24 @@ int main(int argc, char *argv[]) div x0, x31, x30" \ : : : "x28", "x29", "x30", "x31"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 14); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck(count, 3); ////////////////////////////////////////////////////////////// // Retired instruction count (0) - Immediate minstret read printf("\nRetired instruction count (0)"); - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("csrr t0, minstret\n\t\ addi t1, x0, 0\n\t\ addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on - - printf("\nminstret count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 0); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); @@ -326,10 +255,7 @@ int main(int argc, char *argv[]) // Retired instruction count (1) - minstret read-after-write printf("\nRetired instruction count (1)"); - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("csrwi minstret, 0xA\n\t\ csrr t0, minstret\n\t\ @@ -337,13 +263,8 @@ int main(int argc, char *argv[]) addi t2, x0, 0\n\t\ nop" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // - - printf("\nminstret count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 0xA); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 0xF); @@ -352,10 +273,7 @@ int main(int argc, char *argv[]) // Retired instruction count (2) printf("\nRetired instruction count (2)"); - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("sw x0, 0(sp)\n\t\ addi t0, x0, 5\n\t\ @@ -375,9 +293,8 @@ int main(int argc, char *argv[]) nop\n\t\ nop" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5 + 6*5 + 4 + 1); @@ -386,110 +303,74 @@ int main(int argc, char *argv[]) // Count load use hazards printf("\nCount load use hazards"); - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x4, 0(sp)\n\t\ addi x5, x4, 1\n\t\ lw x6, 0(sp)\n\t\ addi x7, x0, 1" \ : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load use hazards count = %d\n", count); - err_cnt += chck(count, 1); // Hazard count is 1 in the absence of interface stalls - ////////////////////////////////////////////////////////////// // Count jump register hazards printf("\nCount Jump register hazards"); - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("auipc x4, 0x0\n\t\ addi x4, x4, 10\n\t\ jalr x0, x4, 0x0" \ : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Jump register hazards count = %d\n", count); - err_cnt += chck(count, 1); // Hazard count is 1 in the absence of interface stalls - ////////////////////////////////////////////////////////////// // Count memory read transactions - Read while enabled printf("\nCount memory read transactions (0)"); - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x0, 0(sp)\n\t\ csrr t0, mhpmcounter3\n\t\ addi t1, x0, 0\n\t\ addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 1); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 1); - ////////////////////////////////////////////////////////////// // Count memory read transactions - Write after load event printf("\nCount memory read transactions (1)"); - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x0, 0(sp)\n\t\ csrwi mhpmcounter3, 0xA\n\t\ addi t1, x0, 0\n\t\ addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load count = %d\n", count); - err_cnt += chck(count, 0xA); - ////////////////////////////////////////////////////////////// // Count memory read transactions printf("\nCount memory read transactions (2)"); - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x0, 0(sp)"); // count++ __asm__ volatile("mulh x0, x0, x0"); @@ -497,69 +378,48 @@ int main(int argc, char *argv[]) __asm__ volatile("nop"); // do not count nop in instret __asm__ volatile("jump_target_memread:"); __asm__ volatile("lw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Count memory write transactions printf("\nCount memory write transactions"); - event = EVENT_DATA_WRITE; // Trigger on stores - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("sw x0, 0(sp)"); // count++ __asm__ volatile("mulh x0, x0, x0"); __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Store count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Count jumps printf("\nCount jumps"); - event = EVENT_JUMP; // Trigger on jumps - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("j jump_target_0"); // count++ __asm__ volatile("jump_target_0:"); __asm__ volatile("j jump_target_1"); // count++ __asm__ volatile("jump_target_1:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 3); - printf("Jump count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Count branches (conditional) printf("\nCount branches (conditional)"); - event = EVENT_BRANCH; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("beq x0, x0, branch_target_0"); // count++ __asm__ volatile("branch_target_0:"); @@ -567,24 +427,17 @@ int main(int argc, char *argv[]) __asm__ volatile("branch_target_1:"); __asm__ volatile("beq x0, x0, branch_target_2"); // count++ __asm__ volatile("branch_target_2:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Branch count = %d\n", count); - err_cnt += chck(count, 3); - ////////////////////////////////////////////////////////////// // Count branches taken (conditional) printf("\nCount branches taken (conditional)"); - event = EVENT_BRANCH_TAKEN; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("beq x0, x0, branch_target_3"); // count++ __asm__ volatile("branch_target_3:"); @@ -592,39 +445,28 @@ int main(int argc, char *argv[]) __asm__ volatile("branch_target_4:"); __asm__ volatile("beq x0, x0, branch_target_5"); // count++ __asm__ volatile("branch_target_5:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Branch taken count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Compressed instructions printf("\nCompressed instructions"); - event = EVENT_COMP_INSTR; // Trigger on compressed instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("c.addi x15, 1\n\t\ c.nop\n\t\ c.addi x15, 1" \ : : : "x15"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Compressed count = %d\n", count); - err_cnt += chck(count, 3); - ////////////////////////////////////////////////////////////// // Check for errors printf("\nDone\n\n"); diff --git a/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c b/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c index 6a156909b4..1287b08c63 100644 --- a/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c +++ b/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c @@ -22,6 +22,10 @@ ** ** Very basic sanity check for: ** +** - Retired Instruction Counter +** - Cycle counter +** +** This test is derived from a test that also checked the hpmcounters on 40x; where it tested: ** - Count load use hazards ** - Count jump register hazards ** - Count memory read transactions @@ -30,16 +34,15 @@ ** - Count branches (conditional) ** - Count branches taken (conditional) ** - Compressed instructions -** - Retired instructions ** -** Make sure to instantiate cv32e40s_wrapper with the parameter -** NUM_MHPMCOUNTERS = 1 (or higher) +** The test is therefore unnecessarily complex for the task ** ******************************************************************************* */ #include #include +#include #include #define MAX_STALL_CYCLES 5 @@ -55,17 +58,6 @@ static int chck(unsigned int is, unsigned int should) return err; } -static int chck_le(unsigned int is, unsigned int should) -{ - int err; - err = is <= should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - static int chck_with_pos_margin(unsigned int is, unsigned int should, unsigned int margin) { int err; @@ -81,51 +73,24 @@ int main(int argc, char *argv[]) { int err_cnt = 0; - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - volatile unsigned int event; - volatile unsigned int count; volatile unsigned int minstret; volatile unsigned int count_while_on; volatile unsigned int mcycle_count; - __asm__ volatile(".option rvc"); - ////////////////////////////////////////////////////////////// // Cycle count printf("\nCycle count"); // Setup events and set csrs to 0 - event = EVENT_CYCLES; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB00, 0x0"); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); // Readback Counter to verify 0 __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nCheck proper zeroization\n"); err_cnt += chck(minstret, 0); - err_cnt += chck(count, 0); - err_cnt += chck(count, mcycle_count); // Enable counters __asm__ volatile("csrwi 0x320, 0x0"); @@ -135,26 +100,20 @@ int main(int argc, char *argv[]) addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("\nCycle count while running = %d", count); printf("\nMCYCLE counted cycles = %d\n", mcycle_count); - err_cnt += chck(count, mcycle_count); - err_cnt += chck_with_pos_margin(count, 6, 4*MAX_STALL_CYCLES); + err_cnt += chck_with_pos_margin(mcycle_count, 5, 4*MAX_STALL_CYCLES); ////////////////////////////////////////////////////////////// // IF_INVALID printf("\nIF_INVALID"); - event = EVENT_IF_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("addi t1, x0, 0\n\t\ @@ -164,26 +123,18 @@ int main(int argc, char *argv[]) nop" \ : : : "t0", "t1"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4+(2*5)); - printf("\nUnderutilized cycles on ID-stage due to IF stage = %d\n", count); - err_cnt += chck_with_pos_margin(count, 4, (4 /*non looped*/ + - 5 /*looped addi*/ + - 4*2 /*taken branches, potenially misaligned*/ + - 2 /*non-taken, potentially misaligned*/)*MAX_STALL_CYCLES); ////////////////////////////////////////////////////////////// // ID_INVALID - LD_STALL printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); + __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("lw x4, 0(sp)\n\t\ @@ -192,22 +143,16 @@ int main(int argc, char *argv[]) addi x7, x0, 1" \ : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck_with_pos_margin(count, 2, 5*MAX_STALL_CYCLES); ////////////////////////////////////////////////////////////// // ID_INVALID - JR STALL printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("auipc x4, 0\n\t\ @@ -215,23 +160,17 @@ int main(int argc, char *argv[]) nop" \ : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck_with_pos_margin(count, 3, 4*MAX_STALL_CYCLES); ////////////////////////////////////////////////////////////// // EX_INVALID printf("\nEX_INVALID"); - event = EVENT_EX_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); __asm__ volatile("csrwi 0x320, 0x0"); __asm__ volatile("lw x0, 0(x0)"); @@ -255,24 +194,17 @@ int main(int argc, char *argv[]) __asm__ volatile("rem x0, x31, x30"); // 32 cycles __asm__ volatile("lw x0, 0(sp)"); - __asm__ volatile("csrwi 0x320, 0x1F"); + __asm__ volatile("csrwi 0x320, 0x5"); __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 21); - printf("\nUnderutilized cycles on WB-stage due to EX stage = %d\n", count); - // -6 due to potential random stalls preventing hazard stalls - err_cnt += chck_with_pos_margin(count, 104 - 6, 21*MAX_STALL_CYCLES + 6); ////////////////////////////////////////////////////////////// // WB_INVALID Write port underutilization printf("\nWrite port underutilization"); - event = EVENT_WB_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("li x31, 1\n\t\ @@ -282,23 +214,17 @@ int main(int argc, char *argv[]) sw x29, 0(sp)" \ : : : "x28", "x29", "x30", "x31"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 6); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck_with_pos_margin(count, 34, 6*MAX_STALL_CYCLES); ////////////////////////////////////////////////////////////// // WB_DATA_STALL Write port underutilization due to data_rvalid_i (0) printf("\nWrite port underutilization due to data_rvalid_i"); - event = EVENT_WB_DATA_STALL; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("li x31, 7\n\t\ @@ -316,32 +242,25 @@ int main(int argc, char *argv[]) div x0, x31, x30" \ : : : "x28", "x29", "x30", "x31"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 14); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck_with_pos_margin(count, 3, 14*MAX_STALL_CYCLES); ////////////////////////////////////////////////////////////// // Retired instruction count (0) - Immediate minstret read printf("\nRetired instruction count (0)"); - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("csrr t0, minstret\n\t\ addi t1, x0, 0\n\t\ addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on printf("\nminstret count while running = %d\n", count_while_on); @@ -354,10 +273,7 @@ int main(int argc, char *argv[]) // Retired instruction count (1) - minstret read-after-write printf("\nRetired instruction count (1)"); - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("csrwi minstret, 0xA\n\t\ csrr t0, minstret\n\t\ @@ -365,9 +281,8 @@ int main(int argc, char *argv[]) addi t2, x0, 0\n\t\ nop" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // printf("\nminstret count while running = %d\n", count_while_on); @@ -380,10 +295,7 @@ int main(int argc, char *argv[]) // Retired instruction count (2) printf("\nRetired instruction count (2)"); - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("sw x0, 0(sp)\n\t\ addi t0, x0, 5\n\t\ @@ -403,9 +315,8 @@ int main(int argc, char *argv[]) nop\n\t\ nop" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret + __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5 + 6*5 + 4 + 1); @@ -414,110 +325,75 @@ int main(int argc, char *argv[]) // Count load use hazards printf("\nCount load use hazards"); - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x4, 0(sp)\n\t\ addi x5, x4, 1\n\t\ lw x6, 0(sp)\n\t\ addi x7, x0, 1" \ : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load use hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Hazard count is 0 or 1 (0 if due to instruction interface stalls 'use' did not closely follow the load) - ////////////////////////////////////////////////////////////// // Count jump register hazards printf("\nCount Jump register hazards"); - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("auipc x4, 0x0\n\t\ addi x4, x4, 10\n\t\ jalr x0, x4, 0x0" \ : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Jump register hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Hazard count is 0 or 1 (0 if due to instruction interface stalls jalr did not closely follow the addi before it) - ////////////////////////////////////////////////////////////// // Count memory read transactions - Read while enabled printf("\nCount memory read transactions (0)"); - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x0, 0(sp)\n\t\ csrr t0, mhpmcounter3\n\t\ addi t1, x0, 0\n\t\ addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 1); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 1); - ////////////////////////////////////////////////////////////// // Count memory read transactions - Write after load event printf("\nCount memory read transactions (1)"); - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x0, 0(sp)\n\t\ csrwi mhpmcounter3, 0xA\n\t\ addi t1, x0, 0\n\t\ addi t2, x0, 0" \ : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load count = %d\n", count); - err_cnt += chck(count, 0xA); - ////////////////////////////////////////////////////////////// // Count memory read transactions printf("\nCount memory read transactions (2)"); - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x0, 0(sp)"); // count++ __asm__ volatile("mulh x0, x0, x0"); @@ -525,69 +401,48 @@ int main(int argc, char *argv[]) __asm__ volatile("nop"); // do not count nop in instret __asm__ volatile("jump_target_memread:"); __asm__ volatile("lw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Count memory write transactions printf("\nCount memory write transactions"); - event = EVENT_DATA_WRITE; // Trigger on stores - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("sw x0, 0(sp)"); // count++ __asm__ volatile("mulh x0, x0, x0"); __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Store count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Count jumps printf("\nCount jumps"); - event = EVENT_JUMP; // Trigger on jumps - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("j jump_target_0"); // count++ __asm__ volatile("jump_target_0:"); __asm__ volatile("j jump_target_1"); // count++ __asm__ volatile("jump_target_1:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 3); - printf("Jump count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Count branches (conditional) printf("\nCount branches (conditional)"); - event = EVENT_BRANCH; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("beq x0, x0, branch_target_0"); // count++ __asm__ volatile("branch_target_0:"); @@ -595,24 +450,17 @@ int main(int argc, char *argv[]) __asm__ volatile("branch_target_1:"); __asm__ volatile("beq x0, x0, branch_target_2"); // count++ __asm__ volatile("branch_target_2:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Branch count = %d\n", count); - err_cnt += chck(count, 3); - ////////////////////////////////////////////////////////////// // Count branches taken (conditional) printf("\nCount branches taken (conditional)"); - event = EVENT_BRANCH_TAKEN; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("beq x0, x0, branch_target_3"); // count++ __asm__ volatile("branch_target_3:"); @@ -620,39 +468,28 @@ int main(int argc, char *argv[]) __asm__ volatile("branch_target_4:"); __asm__ volatile("beq x0, x0, branch_target_5"); // count++ __asm__ volatile("branch_target_5:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Branch taken count = %d\n", count); - err_cnt += chck(count, 2); - ////////////////////////////////////////////////////////////// // Compressed instructions printf("\nCompressed instructions"); - event = EVENT_COMP_INSTR; // Trigger on compressed instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("c.addi x15, 1\n\t\ c.nop\n\t\ c.addi x15, 1" \ : : : "x15"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Compressed count = %d\n", count); - err_cnt += chck(count, 3); - ////////////////////////////////////////////////////////////// // Check for errors printf("\nDone\n\n"); diff --git a/cv32e40s/tests/programs/custom/hpmcounter_hazard_test/hpmcounter_hazard_test.c b/cv32e40s/tests/programs/custom/hpmcounter_hazard_test/hpmcounter_hazard_test.c index 2393345de6..44505786ee 100644 --- a/cv32e40s/tests/programs/custom/hpmcounter_hazard_test/hpmcounter_hazard_test.c +++ b/cv32e40s/tests/programs/custom/hpmcounter_hazard_test/hpmcounter_hazard_test.c @@ -22,11 +22,14 @@ ** ** Very basic sanity check for: ** +** - Retired Instruction Counter +** - Cycle counter +** +** This test is derived from a test that also checked the hpmcounters on 40x; where it tested: ** - Count load use hazards ** - Count jump register hazards ** -** Make sure to instantiate cv32e40s_wrapper with the parameter -** NUM_MHPMCOUNTERS = 1 (or higher) +** The test is therefore unnecessarily complex for the task ** ** Make sure to only run this test without wait states on instr_gnt_i/ ** instr_rvalid_i. The test should tolerate wait states on data_gnt_i/ @@ -37,6 +40,7 @@ #include #include +#include #include static int chck(unsigned int is, unsigned int should) @@ -50,91 +54,45 @@ static int chck(unsigned int is, unsigned int should) return err; } -static int chck_le(unsigned int is, unsigned int should) -{ - int err; - err = is <= should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - int main(int argc, char *argv[]) { int err_cnt = 0; - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - volatile unsigned int event; - volatile unsigned int count; volatile unsigned int minstret; - __asm__ volatile(".option rvc"); - ////////////////////////////////////////////////////////////// // Count load use hazards printf("\nCount load use hazards"); - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("lw x4, 0(sp)\n\t\ addi x5, x4, 1\n\t\ lw x6, 0(sp)\n\t\ addi x7, x0, 1" \ : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 5); - printf("Load use hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Interface stalls can cause this to be 0, otherwise 1 - ////////////////////////////////////////////////////////////// // Count jump register hazards printf("\nCount Jump register hazards"); - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters __asm__ volatile("auipc x4, 0x0\n\t\ addi x4, x4, 10\n\t\ jalr x28, x4, 0x0" \ : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 + __asm__ volatile("csrwi 0x320, 0x5"); // Inhibit mcycle, minstret __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); - printf("Jump register hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Interface stalls can cause this to be 0, otherwise 1 - ////////////////////////////////////////////////////////////// // Check for errors printf("\nDone"); diff --git a/cv32e40s/tests/programs/custom/illegal/illegal.c b/cv32e40s/tests/programs/custom/illegal/illegal.c index 544dab1e8a..e9b7971fc5 100644 --- a/cv32e40s/tests/programs/custom/illegal/illegal.c +++ b/cv32e40s/tests/programs/custom/illegal/illegal.c @@ -1,9 +1,10 @@ #include +#include #include // This is an illegal instruction that is not decodable (in the C extension space) static void illegalCExtOP() { - asm(".short 0x9e41 \n"); + asm(".short 0x3084 \n"); return; } diff --git a/cv32e40s/tests/programs/custom/illegal_instr_test/test.yaml b/cv32e40s/tests/programs/custom/illegal_instr_test/test.yaml index 9e68dafb5d..7fd1a1938e 100644 --- a/cv32e40s/tests/programs/custom/illegal_instr_test/test.yaml +++ b/cv32e40s/tests/programs/custom/illegal_instr_test/test.yaml @@ -4,3 +4,6 @@ name: illegal_instr_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Script-generated test contributed by em-micro to exercise all (?) illegal instruction types +plusargs: > + +iss_suppress_invalid_msg +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/instr_bus_error/instr_bus_error.c b/cv32e40s/tests/programs/custom/instr_bus_error/instr_bus_error.c index c24522edc5..146b731c47 100644 --- a/cv32e40s/tests/programs/custom/instr_bus_error/instr_bus_error.c +++ b/cv32e40s/tests/programs/custom/instr_bus_error/instr_bus_error.c @@ -23,6 +23,7 @@ #include #include +#include #include "corev_uvmt.h" #define TEST_LOOPS 6 diff --git a/cv32e40x/bsp/crt0.S b/cv32e40s/tests/programs/custom/interrupt_bootstrap/crt0.S similarity index 66% rename from cv32e40x/bsp/crt0.S rename to cv32e40s/tests/programs/custom/interrupt_bootstrap/crt0.S index b0ee48373d..41b7be0b87 100644 --- a/cv32e40x/bsp/crt0.S +++ b/cv32e40s/tests/programs/custom/interrupt_bootstrap/crt0.S @@ -1,5 +1,4 @@ -/* Copyright (c) 2017 SiFive Inc. All rights reserved. - * Copyright (c) 2019 ETH Zürich and University of Bologna +/* Copyright (c) 2023 Silicon Laboratories Inc. * This copyrighted material is made available to anyone wishing to use, * modify, copy, or redistribute it subject to the terms and conditions * of the FreeBSD License. This program is distributed in the hope that @@ -8,6 +7,9 @@ * A PARTICULAR PURPOSE. A copy of this license is available at * http://www.opensource.org/licenses. */ + +/* This is a copy of crt0 from the BSP folder but without setting the vector address*/ + /* Make sure the vector table gets linked into the binary. */ .global vector_table @@ -23,45 +25,43 @@ _start: /* initialize global pointer */ .option push .option norelax -1: auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) +1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + +/* initialize vector table pointer */ +1:auipc a0, %pcrel_hi(__jvt_base$) + addi a0, a0, %pcrel_lo(1b) + csrw jvt, a0 .option pop /* initialize stack pointer */ - la sp, __stack_end - -/* set vector table address */ - la a0, __vector_start - ori a0, a0, 1 /*vector mode = vectored */ - csrw mtvec, a0 + la sp, __stack_end /* clear the bss segment */ - la a0, _edata - la a2, _end - sub a2, a2, a0 - li a1, 0 - call memset + la a0, _edata + la a2, _end + sub a2, a2, a0 + li a1, 0 + call memset /* new-style constructors and destructors */ - la a0, __libc_fini_array - call atexit - call __libc_init_array + la a0, __libc_fini_array + call atexit + call __libc_init_array /* call main */ -// lw a0, 0(sp) /* a0 = argc */ -// addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ -// li a2, 0 /* a2 = envp = NULL */ // Initialize these variables to 0. Cannot use argc or argv // since the stack is not initialized - li a0, 0 - li a1, 0 - li a2, 0 + li a0, 0 + li a1, 0 + li a2, 0 - call main - tail exit + call main + tail exit .size _start, .-_start + .global _init .type _init, @function .global _fini @@ -70,6 +70,6 @@ _init: _fini: /* These don't have to do anything since we use init_array/fini_array. Prevent missing symbol error */ - ret + ret .size _init, .-_init .size _fini, .-_fini diff --git a/cv32e40s/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.S b/cv32e40s/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.S deleted file mode 100644 index b757411076..0000000000 --- a/cv32e40s/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.S +++ /dev/null @@ -1,101 +0,0 @@ -/* Make sure the vector table gets linked into the binary. */ -.global vector_table - -/* Entry point for bare metal programs */ -.section .text.start -.global _start -.type _start, @function - -_start: -/* initialize global pointer */ -.option push -.option norelax -1: auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) -.option pop - -/* initialize stack pointer */ - la sp, __stack_end - -/* clear the bss segment */ - la a0, _edata - la a2, _end - sub a2, a2, a0 - li a1, 0 - call memset - -/* new-style constructors and destructors */ - la a0, __libc_fini_array - call atexit - call __libc_init_array - -/* call main */ -// lw a0, 0(sp) /* a0 = argc */ -// addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ -// li a2, 0 /* a2 = envp = NULL */ -// Initialize these variables to 0. Cannot use argc or argv -// since the stack is not initialized - li a0, 0 - li a1, 0 - li a2, 0 - - call main - tail exit - -.size _start, .-_start - -.global _init -.type _init, @function -.global _fini -.type _fini, @function -_init: -_fini: - /* These don't have to do anything since we use init_array/fini_array. Prevent - missing symbol error */ - ret -.size _init, .-_init -.size _fini, .-_fini - - -// Custom alternate vector table to load at interrupt boostrap address -.section .vectors.alt, "ax" - -.global alt_vector_table -.option norvc -.align 8 - -alt_vector_table: - - j u_sw_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_software_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_timer_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_external_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_fast0_irq_handler - j m_fast1_irq_handler - j m_fast2_irq_handler - j m_fast3_irq_handler - j m_fast4_irq_handler - j m_fast5_irq_handler - j m_fast6_irq_handler - j m_fast7_irq_handler - j m_fast8_irq_handler - j m_fast9_irq_handler - j m_fast10_irq_handler - j m_fast11_irq_handler - j m_fast12_irq_handler - j m_fast13_irq_handler - j m_fast14_irq_handler - j m_fast15_irq_handler - diff --git a/cv32e40s/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c b/cv32e40s/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c index 4f8b1465ba..d82720c553 100644 --- a/cv32e40s/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c +++ b/cv32e40s/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c @@ -1,14 +1,18 @@ #include -#include -#include -#include - #include "interrupt_test.h" +void alt_vector_table (void) __attribute__ ((naked, // No stack manipulation needed as this is a table and not an actual function + aligned(8), // Align table + section(".vectors.alt"), // Put in alternate vector section + target("arch=rv32i"), // Avoid compressed instructions + norelax)); // Prevent linker from adding compressed instructions + +void generic_irq_handler(uint32_t) __attribute__((naked)); // Handle function entry and exit manually to ensure all registers are saved and restored + // There is no way to commnicate UVM side information to firmware currently // so use a fixed value for moving mtvec // This should be safely away from the code area and yet safely "down" the stack area -#define BOOTSTRAP_MTVEC 0x00000200 +#define BOOTSTRAP_MTVEC 0x00000201 volatile uint32_t irq_id = 0; volatile uint32_t irq_id_q[IRQ_NUM]; @@ -19,7 +23,8 @@ volatile uint32_t nested_irq = 0; volatile uint32_t nested_irq_valid = 0; volatile uint32_t in_direct_handler = 0; -uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { + +volatile uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { FAST15_IRQ_ID , FAST14_IRQ_ID , FAST13_IRQ_ID , @@ -41,250 +46,344 @@ uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { TIMER_IRQ_ID }; +void alt_vector_table (void) { + __asm__ volatile (R"( + j u_sw_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_software_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_timer_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_external_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_fast0_irq_handler + j m_fast1_irq_handler + j m_fast2_irq_handler + j m_fast3_irq_handler + j m_fast4_irq_handler + j m_fast5_irq_handler + j m_fast6_irq_handler + j m_fast7_irq_handler + j m_fast8_irq_handler + j m_fast9_irq_handler + j m_fast10_irq_handler + j m_fast11_irq_handler + j m_fast12_irq_handler + j m_fast13_irq_handler + j m_fast14_irq_handler + j m_fast15_irq_handler + )"); +} + void delay(int count) { - for (volatile int d = 0; d < count; d++); + for (volatile int d = 0; d < count; d++); } void mstatus_mie_enable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - __asm__ volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); + volatile uint32_t mie_bit = 0x1 << MSTATUS_MIE_BIT; + __asm__ volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); } void mstatus_mie_disable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - __asm__ volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); + volatile uint32_t mie_bit = 0x1 << MSTATUS_MIE_BIT; + __asm__ volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); } void mie_enable_all() { - uint32_t mie_mask = (uint32_t) -1; - __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); + volatile uint32_t mie_mask = (uint32_t) -1; + __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); } void mie_disable_all() { - uint32_t mie_mask = (uint32_t) -1; - __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); + volatile uint32_t mie_mask = (uint32_t) -1; + __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); } void mie_enable(uint32_t irq) { - // Enable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); + // Enable the interrupt irq in MIE + volatile uint32_t mie_bit = 0x1 << irq; + __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); } void mie_disable(uint32_t irq) { - // Disable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); + // Disable the interrupt irq in MIE + volatile uint32_t mie_bit = 0x1 << irq; + __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); } void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { - *TIMER_REG_ADDR = mask; - *TIMER_VAL_ADDR = 1 + cycle_delay; + *TIMER_REG_ADDR = mask; + *TIMER_VAL_ADDR = 1 + cycle_delay; } uint32_t random_num(uint32_t upper_bound, uint32_t lower_bound) { - uint32_t random_num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); - uint32_t num = (random_num % (upper_bound - lower_bound + 1)) + lower_bound; - return num; + volatile uint32_t random_num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); + volatile uint32_t num = (random_num % (upper_bound - lower_bound + 1)) + lower_bound; + return num; } uint32_t random_num32() { - uint32_t num = *((volatile int *)CV_VP_RANDOM_NUM_BASE); - return num; + volatile uint32_t num = *((volatile int *)CV_VP_RANDOM_NUM_BASE); + return num; } extern void __no_irq_handler(); void nested_irq_handler(uint32_t id) { - // First stack mie, mepc and mstatus - // Must be done in critical section with MSTATUS.MIE == 0 - volatile uint32_t mie, mepc, mstatus; - __asm__ volatile("csrr %0, mie" : "=r" (mie)); - __asm__ volatile("csrr %0, mepc" :"=r" (mepc)); - __asm__ volatile("csrr %0, mstatus" : "=r" (mstatus)); - - // Re enable interrupts and create window to enable nested irqs - mstatus_mie_enable(); - for (volatile int i = 0; i < 20; i++); - - // Disable MSTATUS.MIE and restore from critical section - mstatus_mie_disable(); - __asm__ volatile("csrw mie, %0" : : "r" (mie)); - __asm__ volatile("csrw mepc, %0" : : "r" (mepc)); - __asm__ volatile("csrw mstatus, %0" : : "r" (mstatus)); + // First stack mie, mepc and mstatus + // Must be done in critical section with MSTATUS.MIE == 0 + volatile uint32_t mie, mepc, mstatus; + __asm__ volatile("csrr %0, mie" : "=r" (mie)); + __asm__ volatile("csrr %0, mepc" :"=r" (mepc)); + __asm__ volatile("csrr %0, mstatus" : "=r" (mstatus)); + + // Re enable interrupts and create window to enable nested irqs + mstatus_mie_enable(); + for (volatile int i = 0; i < 20; i++){ + __asm__ volatile("nop"); + }; + + // Disable MSTATUS.MIE and restore from critical section + mstatus_mie_disable(); + __asm__ volatile("csrw mie, %0" : : "r" (mie)); + __asm__ volatile("csrw mepc, %0" : : "r" (mepc)); + __asm__ volatile("csrw mstatus, %0" : : "r" (mstatus)); } + void generic_irq_handler(uint32_t id) { - __asm__ volatile("csrr %0, mcause": "=r" (mmcause)); - irq_id = id; + __asm__ volatile (R"( + # Store return address and saved registers + + sw a0, -4(sp) + sw a1, -8(sp) + sw a2, -12(sp) + sw a3, -16(sp) + sw a4, -20(sp) + sw a5, -24(sp) + sw a6, -28(sp) + sw a7, -32(sp) + sw t0, -36(sp) + sw t1, -40(sp) + sw t2, -44(sp) + sw t3, -48(sp) + sw t4, -52(sp) + sw t5, -56(sp) + sw t6, -60(sp) + addi sp, sp, -64 + + cm.push {ra, s0-s11}, -64 + + call generic_irq_handler_wrapped + + # Restore return address and saved registers + cm.pop {ra, s0-s11}, 64 + + addi sp, sp, 64 + lw a0, -4(sp) + lw a1, -8(sp) + lw a2, -12(sp) + lw a3, -16(sp) + lw a4, -20(sp) + lw a5, -24(sp) + lw a6, -28(sp) + lw a7, -32(sp) + lw t0, -36(sp) + lw t1, -40(sp) + lw t2, -44(sp) + lw t3, -48(sp) + lw t4, -52(sp) + lw t5, -56(sp) + lw t6, -60(sp) + )"); +} - if (active_test == 2 || active_test == 3 || active_test == 4) { - irq_id_q[irq_id_q_ptr++] = id; - } - if (active_test == 3) { - if (nested_irq_valid) { - nested_irq_valid = 0; - mm_ram_assert_irq(0x1 << nested_irq, random_num(10,0)); - } - nested_irq_handler(id); +void generic_irq_handler_wrapped(uint32_t id) { + __asm__ volatile("csrr %0, mcause": "=r" (mmcause)); + irq_id = id; + + if (active_test == 2 || active_test == 3 || active_test == 4) { + irq_id_q[irq_id_q_ptr++] = id; + } + if (active_test == 3) { + if (nested_irq_valid) { + nested_irq_valid = 0; + mm_ram_assert_irq(0x1 << nested_irq, random_num(10,0)); } + nested_irq_handler(id); + } } void m_software_irq_handler(void) { generic_irq_handler(SOFTWARE_IRQ_ID); } -void m_timer_irq_handler(void) { generic_irq_handler(TIMER_IRQ_ID); } +void m_timer_irq_handler(void) { generic_irq_handler(TIMER_IRQ_ID); } void m_external_irq_handler(void) { generic_irq_handler(EXTERNAL_IRQ_ID); } -void m_fast0_irq_handler(void) { generic_irq_handler(FAST0_IRQ_ID); } -void m_fast1_irq_handler(void) { generic_irq_handler(FAST1_IRQ_ID); } -void m_fast2_irq_handler(void) { generic_irq_handler(FAST2_IRQ_ID); } -void m_fast3_irq_handler(void) { generic_irq_handler(FAST3_IRQ_ID); } -void m_fast4_irq_handler(void) { generic_irq_handler(FAST4_IRQ_ID); } -void m_fast5_irq_handler(void) { generic_irq_handler(FAST5_IRQ_ID); } -void m_fast6_irq_handler(void) { generic_irq_handler(FAST6_IRQ_ID); } -void m_fast7_irq_handler(void) { generic_irq_handler(FAST7_IRQ_ID); } -void m_fast8_irq_handler(void) { generic_irq_handler(FAST8_IRQ_ID); } -void m_fast9_irq_handler(void) { generic_irq_handler(FAST9_IRQ_ID); } -void m_fast10_irq_handler(void) { generic_irq_handler(FAST10_IRQ_ID); } -void m_fast11_irq_handler(void) { generic_irq_handler(FAST11_IRQ_ID); } -void m_fast12_irq_handler(void) { generic_irq_handler(FAST12_IRQ_ID); } -void m_fast13_irq_handler(void) { generic_irq_handler(FAST13_IRQ_ID); } -void m_fast14_irq_handler(void) { generic_irq_handler(FAST14_IRQ_ID); } -void m_fast15_irq_handler(void) { generic_irq_handler(FAST15_IRQ_ID); } +void m_fast0_irq_handler(void) { generic_irq_handler(FAST0_IRQ_ID); } +void m_fast1_irq_handler(void) { generic_irq_handler(FAST1_IRQ_ID); } +void m_fast2_irq_handler(void) { generic_irq_handler(FAST2_IRQ_ID); } +void m_fast3_irq_handler(void) { generic_irq_handler(FAST3_IRQ_ID); } +void m_fast4_irq_handler(void) { generic_irq_handler(FAST4_IRQ_ID); } +void m_fast5_irq_handler(void) { generic_irq_handler(FAST5_IRQ_ID); } +void m_fast6_irq_handler(void) { generic_irq_handler(FAST6_IRQ_ID); } +void m_fast7_irq_handler(void) { generic_irq_handler(FAST7_IRQ_ID); } +void m_fast8_irq_handler(void) { generic_irq_handler(FAST8_IRQ_ID); } +void m_fast9_irq_handler(void) { generic_irq_handler(FAST9_IRQ_ID); } +void m_fast10_irq_handler(void) { generic_irq_handler(FAST10_IRQ_ID); } +void m_fast11_irq_handler(void) { generic_irq_handler(FAST11_IRQ_ID); } +void m_fast12_irq_handler(void) { generic_irq_handler(FAST12_IRQ_ID); } +void m_fast13_irq_handler(void) { generic_irq_handler(FAST13_IRQ_ID); } +void m_fast14_irq_handler(void) { generic_irq_handler(FAST14_IRQ_ID); } +void m_fast15_irq_handler(void) { generic_irq_handler(FAST15_IRQ_ID); } // A Special version of the SW Handler (vector 0) used in the direct mode __attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void) { - in_direct_handler = 1; - __asm__ volatile("csrr %0, mcause" : "=r" (mmcause)); + in_direct_handler = 1; + __asm__ volatile("csrr %0, mcause" : "=r" (mmcause)); } int test_mtvec() { - uint32_t mtvec_act; - uint32_t mtvec_exp = BOOTSTRAP_MTVEC | 0x1; - - __asm__ volatile("csrr %0, mtvec" : "=r" (mtvec_act)); - if (mtvec_act != mtvec_exp) { - printf("MTVEC bootstrap failure, exp 0x%08lx, act 0x%08lx\n", mtvec_exp, mtvec_act); - return 1; - } - return EXIT_SUCCESS; + volatile uint32_t mtvec_act; + volatile uint32_t mtvec_exp = BOOTSTRAP_MTVEC | 0x1; + + __asm__ volatile("csrr %0, mtvec" : "=r" (mtvec_act)); + if (mtvec_act != mtvec_exp) { + printf("MTVEC bootstrap failure, exp 0x%08lx, act 0x%08lx\n", mtvec_exp, mtvec_act); + return 1; + } + return EXIT_SUCCESS; } int main(int argc, char *argv[]) { - int retval; + volatile int retval = 1; - // Trash the "default" 0 table - for (int i = 0; i < 32; i++) { - volatile uint32_t *ptr = (volatile uint32_t *) (0 + i*4); - *ptr = 0x0; - } + // Trash the "default" 0 table + for (volatile int i = 0; i < 32; i++) { + volatile uint32_t * volatile ptr = (volatile uint32_t * volatile) (0 + i*4); + *ptr = 0x0; + } + + // Test that mtvec is correct + retval = test_mtvec(); + if (retval != EXIT_SUCCESS) + return retval; - // Test that mtvec is correct - retval = test_mtvec(); - if (retval != EXIT_SUCCESS) - return retval; + // Test 1 + retval = test1(); + if (retval != EXIT_SUCCESS) + return retval; - // Test 1 - retval = test1(); - if (retval != EXIT_SUCCESS) - return retval; + return EXIT_SUCCESS; } // Test 1 will issue individual interrupts one at a time and ensure that each ISR is entered int test1() { - printf("TEST 1 - TRIGGER ALL IRQS IN SEQUENCE:\n"); + printf("TEST 1 - TRIGGER ALL IRQS IN SEQUENCE:\n"); - active_test = 1; + active_test = 1; - if (test1_impl(0) != EXIT_SUCCESS) - return ERR_CODE_TEST_1; + if (test1_impl(0) != EXIT_SUCCESS) + return ERR_CODE_TEST_1; - return EXIT_SUCCESS; + return EXIT_SUCCESS; } // To share implementation of basic interrupt test with vector relocation tests, // break out the test 1 implementation here int test1_impl(int direct_mode) { - for (uint32_t i = 0; i < 32; i++) { + + for (volatile uint32_t i = 0; i < 32; i++) { #ifdef DEBUG_MSG - printf("Test1 -> Testing interrupt %lu\n", i); + printf("Test1 -> Testing interrupt %lu\n", i); #endif - for (uint32_t gmie = 0; gmie <= 1; gmie++) { - for (uint32_t mie = 0; mie <= 1; mie++) { - uint32_t mip; - - // Set global MIE - if (gmie) mstatus_mie_enable(); - else mstatus_mie_disable(); - - // Set individual mie - if (mie) mie_enable(i); - else mie_disable(i); - - in_direct_handler = 0; - mmcause = 0; - mm_ram_assert_irq(0x1 << i, 1); - - if (((0x1 << i) & IRQ_MASK) && mie && gmie) { - // Interrupt is valid and enabled - // wait for the irq to be served - while (!mmcause); - - if ((mmcause & (0x1 << 31)) == 0) { - printf("MCAUSE[31] was not set: mmcause = 0x%08lx\n", (uint32_t) mmcause); - - return ERR_CODE_TEST_1; - } - if ((mmcause & MCAUSE_IRQ_MASK) != i) { - printf("MCAUSE reported wrong irq, exp = %lu, act = 0x%08lx", i, mmcause); - - return ERR_CODE_TEST_1; - } - } else { - // Unimplemented interrupts, or is a masked irq, delay a bit, waiting for any mmcause - for (int j = 0; j < 20; j++) { - if (mmcause != 0) { - printf("MMCAUSE = 0x%08lx when unimplmented interrupt %lu first", mmcause, i); - return ERR_CODE_TEST_1; - } - } - } - - // Check MIP - // For unimplemented irqs, this should always be 0 - // For masked irqs, this should always be 0 - // If the IRQ occurred then acking will cause it to clear by here, so do not check - __asm__ volatile ("csrr %0,mip" : "=r" (mip)); - if (((0x1 << i) & IRQ_MASK) && (!mie || !gmie)) { - // Implemented, masked IRQ - if (!(mip & (0x1 << i))) { - printf("MIP for IRQ[%lu] not set\n", i); - return ERR_CODE_TEST_1; - } - } else { - // Unimplemented IRQ - if (mip & (0x1 << i)) { - printf("MIP for unimplemented IRQ[%lu] set\n", i); - return ERR_CODE_TEST_1; - } - } - - // Check flag at direct mode handler - if (((0x1 << i) & IRQ_MASK) && mie && gmie) { - if (direct_mode && !in_direct_handler) { - printf("In direct mode, the direct sw handler was not entered, irq: %lu\n", i); - return ERR_CODE_TEST_1; - } - if (!direct_mode && in_direct_handler) { - printf("In vector mode, the direct sw handler was entered, irq: %lu\n", i); - return ERR_CODE_TEST_1; - } - } - - // Clear vp irq - mm_ram_assert_irq(0, 0); + for (volatile uint32_t gmie = 0; gmie <= 1; gmie++) { + for (volatile uint32_t mie = 0; mie <= 1; mie++) { + volatile uint32_t mip; + printf("i: %lu, gmie: %lu, mie: %lu\n", i, gmie, mie); + + // Set global MIE + if (gmie) mstatus_mie_enable(); + else mstatus_mie_disable(); + + // Set individual mie + if (mie) mie_enable(i); + else mie_disable(i); + + in_direct_handler = 0; + mmcause = 0; + mm_ram_assert_irq(0x1 << i, 1); + + + if (((IRQ_MASK >> i) & 1) && mie && gmie) { + // Interrupt is valid and enabled + // wait for the irq to be served + while (!mmcause); + + if ((mmcause & (0x1 << 31)) == 0) { + printf("MCAUSE[31] was not set: mmcause = 0x%08lx\n", (uint32_t) mmcause); + + return ERR_CODE_TEST_1; + } + if ((mmcause & MCAUSE_IRQ_MASK) != i) { + printf("MCAUSE reported wrong irq, exp = %lu, act = 0x%08lx\n", i, mmcause); + + return ERR_CODE_TEST_1; + } + } else { +#ifdef DEBUG_MSG + printf("(0x1 << i):%x, IRQ_MASK:%x, mie:%lx, gmie:%lx\n", (0x1 << i), IRQ_MASK, mie, gmie); +#endif + // Unimplemented interrupts, or is a masked irq, delay a bit, waiting for any mmcause + for (volatile int j = 0; j < 20; j++) { + if (mmcause != 0) { + printf("MMCAUSE = 0x%08lx when unimplmented interrupt %lu first\n", mmcause, i); + return ERR_CODE_TEST_1; } + } + } + + // Check MIP + // For unimplemented irqs, this should always be 0 + // For masked irqs, this should always be 0 + // If the IRQ occurred then acking will cause it to clear by here, so do not check + __asm__ volatile ("csrr %0,mip" : "=r" (mip)); + if (((0x1 << i) & IRQ_MASK) && (!mie || !gmie)) { + // Implemented, masked IRQ + if (!(mip & (0x1 << i))) { + printf("MIP for IRQ[%lu] not set\n", i); + return ERR_CODE_TEST_1; + } + } else { + // Unimplemented IRQ + if (mip & (0x1 << i)) { + printf("MIP for unimplemented IRQ[%lu] set\n", i); + return ERR_CODE_TEST_1; + } } - } - return EXIT_SUCCESS; + // Check flag at direct mode handler + if (((0x1 << i) & IRQ_MASK) && mie && gmie) { + if (direct_mode && !in_direct_handler) { + printf("In direct mode, the direct sw handler was not entered, irq: %lu\n", i); + return ERR_CODE_TEST_1; + } + if (!direct_mode && in_direct_handler) { + printf("In vector mode, the direct sw handler was entered, irq: %lu\n", i); + return ERR_CODE_TEST_1; + } + } + + // Clear vp irq + mm_ram_assert_irq(0, 0); + } + } + } + return EXIT_SUCCESS; } diff --git a/cv32e40s/tests/programs/custom/interrupt_bootstrap/link.ld b/cv32e40s/tests/programs/custom/interrupt_bootstrap/link.ld index 758e19f344..e1e2dac9f3 100644 --- a/cv32e40s/tests/programs/custom/interrupt_bootstrap/link.ld +++ b/cv32e40s/tests/programs/custom/interrupt_bootstrap/link.ld @@ -11,18 +11,18 @@ */ OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", - "elf32-littleriscv") + "elf32-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) /* CORE-V */ MEMORY { - /* Our testbench is a bit weird in that we initialize the RAM (thus - allowing initialized sections to be placed there). Infact we dump all - sections to ram. */ + /* Our testbench is a bit weird in that we initialize the RAM (thus + allowing initialized sections to be placed there). Infact we dump all + sections to ram. */ - ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 + ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000 } @@ -32,17 +32,18 @@ SECTIONS DM_HaltAddress parameter in the RTL */ .debugger (ORIGIN(dbg)): { + PROVIDE(_debugger_start = .); KEEP(*(.debugger)); } >dbg .debugger_exception (0x1A111000): { + PROVIDE(_debugger_exception = .); KEEP(*(.debugger_exception)); } >dbg /* Debugger Stack*/ .debugger_stack : ALIGN(16) { - PROVIDE(__debugger_stack_start = .); - . = 0x80; + PROVIDE(__debugger_stack_start = ALIGN(ORIGIN(dbg) + LENGTH(dbg) - 15, 16)); } >dbg @@ -54,7 +55,6 @@ SECTIONS KEEP(*(.nmi)); } >ram - /* CORE-V: we want a fixed entry point */ PROVIDE(__boot_address = 0x80); @@ -65,6 +65,7 @@ SECTIONS KEEP(*(.vectors)); } >ram + /* CORE-V: crt0 init code */ .init (__boot_address): { @@ -119,6 +120,9 @@ SECTIONS .iplt : { *(.iplt) } .text : { + /* FIXME: the naming for text.tbljal will most likely change and move out of .text */ + . = ALIGN(1024); + *(.text.tbljal) *(.text.unlikely .text.*_unlikely .text.unlikely.*) *(.text.exit .text.exit.*) *(.text.startup .text.startup.*) @@ -157,12 +161,12 @@ SECTIONS .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >ram .exception_ranges : ONLY_IF_RW { *(.exception_ranges*) } >ram /* Thread Local Storage sections */ - .tdata : + .tdata : { PROVIDE_HIDDEN (__tdata_start = .); *(.tdata .tdata.* .gnu.linkonce.td.*) } >ram - .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); @@ -259,7 +263,7 @@ SECTIONS . = ALIGN(32 / 8); __bss_end = .; __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, - MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800)); + MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800)); _end = .; PROVIDE (end = .); . = DATA_SEGMENT_END (.); diff --git a/cv32e40s/tests/programs/custom/interrupt_bootstrap/test.yaml b/cv32e40s/tests/programs/custom/interrupt_bootstrap/test.yaml index 16371e980c..2534dc2d24 100644 --- a/cv32e40s/tests/programs/custom/interrupt_bootstrap/test.yaml +++ b/cv32e40s/tests/programs/custom/interrupt_bootstrap/test.yaml @@ -4,4 +4,5 @@ description: > Interrupt directed test for mtvec_addr_i bootstrap pins plusargs: > +mtvec_addr=0x00000201 -llvm_cflags: -fno-integrated-as \ No newline at end of file +llvm_cflags: -fno-integrated-as +cflags: -mno-relax \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/interrupt_priv_test/README.md b/cv32e40s/tests/programs/custom/interrupt_priv_test/README.md new file mode 100644 index 0000000000..b0ae0811aa --- /dev/null +++ b/cv32e40s/tests/programs/custom/interrupt_priv_test/README.md @@ -0,0 +1,3 @@ +Small interrupt test to check that interrupt are always handled in machine mode. + +Needs `CFG=pmp` for allowing U-mode to run. diff --git a/cv32e40s/tests/programs/custom/interrupt_priv_test/helpers.S b/cv32e40s/tests/programs/custom/interrupt_priv_test/helpers.S new file mode 100644 index 0000000000..869485a825 --- /dev/null +++ b/cv32e40s/tests/programs/custom/interrupt_priv_test/helpers.S @@ -0,0 +1,38 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly helper functions for the 'debug_priv_test.c' file. +** +******************************************************************************* +*/ + +.section .text + +.global setup_pmp +.global set_u_mode + +setup_pmp: + // Set pmp addr to 0xFFFF_FFFF + li t0, 0xFFFFFFFF + csrrw x0, pmpaddr0, t0 + + // Set pmp region TOR and read/write/execute + li t0, ((1 << 3) + (7 << 0)) + csrrw x0, pmpcfg0, t0 + + ret + +set_u_mode: // puts the core in usermode. + li t0, 0x1800 // load as bitmask + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrw x0, mepc, ra + mret \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/interrupt_priv_test/interrupt_priv_test.c b/cv32e40s/tests/programs/custom/interrupt_priv_test/interrupt_priv_test.c new file mode 100644 index 0000000000..9e77a9977b --- /dev/null +++ b/cv32e40s/tests/programs/custom/interrupt_priv_test/interrupt_priv_test.c @@ -0,0 +1,197 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Small interrupt test to check that interrupt exceptions are always taken in machine mode. +** +******************************************************************************* +*/ + + +#include +#include +#include +#include +#include "corev_uvmt.h" + + +#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE)) +#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE + 4)) +#define M_ext_intr_bit 11 +#define MSTATUS_MIE_BIT 3 +#define external_machine_interrupt 0x800 +// standard value for the mstatus register +#define MSTATUS_STD_VAL 0x1800 + +volatile uint32_t mmcause = 0; +volatile uint32_t mmstatus = 0; +volatile uint32_t mmie = 0; +volatile uint32_t num_taken_interrupts = 0; +// MPP bit-field +volatile int MPP_FIELD [2] = {11, 12}; + +// Assembly function to setup a generous PMP-region for user mode. +extern volatile void setup_pmp(); +// Assembly function to set privilege-mode to user-mode +extern volatile void set_u_mode(); + +// Declaration of assert +static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { + if (actual != expect) { + printf(msg); + printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); + exit(EXIT_FAILURE); + } +} + +/* +Returns specific bit-field from [bit_indx_low : bit_indx_high] in register x +*/ +unsigned int get_field(unsigned int x, int bit_indx_low, int bit_indx_high){ + int field = ( 1 << ( (bit_indx_high - bit_indx_low) + 1) ) - 1; + x = (x & (field << bit_indx_low) ) >> bit_indx_low; + return x; +} + +/* Checks the mepc for compressed instructions and increments appropriately */ +void increment_mepc(void){ + volatile unsigned int insn, mepc; + + __asm__ volatile("csrrs %0, mepc, x0" : "=r"(mepc)); // read the mepc + __asm__ volatile("lw %0, 0(%1)" : "=r"(insn) : "r"(mepc)); // read the contents of the mepc pc. + if ((insn & 0x3) == 0x3) { // check for compressed instruction before increment. + mepc += 4; + } else { + mepc += 2; + } + __asm__ volatile("csrrw x0, mepc, %0" :: "r"(mepc)); // write to the mepc +} + +// example use: "mm_ram_assert_irq(0x1 << i, 1);" +void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { + *TIMER_REG_ADDR = mask; + *TIMER_VAL_ADDR = 1 + cycle_delay; +} + +void mstatus_mie_enable() { + int mie_bit = 0x1 << MSTATUS_MIE_BIT; + asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); +} + +void mie_enable(uint32_t irq) { + // Enable the interrupt irq in MIE + uint32_t mie_bit = 0x1 << irq; + asm volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); +} + +typedef enum { + GET_MSTATUS, + EXCEPTION_MODE, +} trap_behavior_t; + +// trap handler behavior definitions +volatile trap_behavior_t trap_handler_beh; + + +/* +There is (currently) no way for the hart to know which privilege mode it is executing in, but its possible to use the mstatus to figure out the previous privilege mode. +Therefore the interrupt tests will have the m_external_irq_handler trap into u_sw_irq_handler, in order to see the interrupt handlers privilege. +For the trap tests the trap handler will trap again into itself to see which mode its operating in, a sort of self-policing action. +*/ +__attribute__ ((interrupt ("machine"))) +void u_sw_irq_handler(void) { + volatile uint32_t mepc = 0; + switch(trap_handler_beh) { + + case GET_MSTATUS : + asm volatile("csrrs %0, mstatus, x0": "=r" (mmstatus)); + // set the mode going forward to machine mode. + asm volatile("csrrs x0, mstatus, %0" :: "r"(MSTATUS_STD_VAL)); + increment_mepc(); + break; + + case EXCEPTION_MODE : + __asm__ volatile("csrrs %0, mepc, x0" : "=r"(mepc)); // read the mepc + trap_handler_beh = GET_MSTATUS; + asm volatile("ecall"); + __asm__ volatile("csrrw x0, mepc, %0" :: "r"(mepc)); // write to the mepc + increment_mepc(); + break; + } +} + +// specific interrupt handler +__attribute__((interrupt ("machine"))) +void m_external_irq_handler(void) { + volatile uint32_t mepc = 0; + __asm__ volatile("csrrs %0, mepc, x0" : "=r"(mepc)); // read the mepc + asm volatile("csrrs %0, mcause, x0": "=r" (mmcause)); + // Increment if interrupt + if (mmcause >> 31) { + num_taken_interrupts++; + } + + // ecall to trap handler in order to see previous privilege mode. + asm volatile("ecall"); + asm volatile("csrrs x0, mstatus, %0" :: "r"(MSTATUS_STD_VAL)); + __asm__ volatile("csrrw x0, mepc, %0" :: "r"(mepc)); // write to the mepc + increment_mepc(); + +} + +int main(void) { + setup_pmp(); + + + // Test start: + /* + Observe traps (interrupts and exceptions) getting triggered while in M-mode and U-mode, ensure the handler always starts in M-mode. + */ + mstatus_mie_enable(); + mie_enable(M_ext_intr_bit); + num_taken_interrupts = 0; + + // case 1 user mode interrupt + trap_handler_beh = GET_MSTATUS; + set_u_mode(); + mm_ram_assert_irq(external_machine_interrupt, 1); + while (!mmcause); // wait for interrupt to finish + assert_or_die(num_taken_interrupts, 1, "Error: No interrupts registered!\n"); + volatile int get_mpp = get_field(mmstatus, 11, 12); + assert_or_die(get_mpp, 0x3, "Error: Interrupt handler did not execute in machine mode!\n"); + + // case 2 user mode exception + trap_handler_beh = EXCEPTION_MODE; + set_u_mode(); + asm volatile("ecall"); + get_mpp = get_field(mmstatus, MPP_FIELD[0], MPP_FIELD[1]); + assert_or_die(get_mpp, 0x3, "Error: Interrupt handler did not execute in machine mode!\n"); + + + // case 3 machine mode interrupt + mmcause = 0; + trap_handler_beh = GET_MSTATUS; + mm_ram_assert_irq(external_machine_interrupt, 1); + while (!mmcause); // wait for interrupt to finish + assert_or_die(num_taken_interrupts, 2, "Error: No interrupts registered!\n"); + get_mpp = get_field(mmstatus, MPP_FIELD[0], MPP_FIELD[1]); + assert_or_die(get_mpp, 0x3, "Error: Interrupt handler did not execute in machine mode!\n"); + + + // case 4 machine mode exception + trap_handler_beh = EXCEPTION_MODE; + asm volatile("ecall"); + get_mpp = get_field(mmstatus, MPP_FIELD[0], MPP_FIELD[1]); + assert_or_die(get_mpp, 0x3, "Error: Interrupt handler did not execute in machine mode!\n"); + + + exit(EXIT_SUCCESS); +} diff --git a/cv32e40s/tests/programs/custom/interrupt_priv_test/test.yaml b/cv32e40s/tests/programs/custom/interrupt_priv_test/test.yaml new file mode 100644 index 0000000000..8473650cdc --- /dev/null +++ b/cv32e40s/tests/programs/custom/interrupt_priv_test/test.yaml @@ -0,0 +1,7 @@ +name: interrupt_priv_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Interrupt directed test for privilege mode behavior. + + + diff --git a/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.c b/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.c index d483ccfa67..90950fb727 100644 --- a/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.c +++ b/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.c @@ -1,5 +1,6 @@ #include #include +#include #include #include "interrupt_test.h" @@ -14,9 +15,8 @@ volatile uint32_t nested_irq_valid = 0; volatile uint32_t in_direct_handler = 0; volatile uint32_t event; volatile uint32_t num_taken_interrupts; -volatile uint32_t num_counted_interrupts; -uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { +volatile uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { FAST15_IRQ_ID , FAST14_IRQ_ID , FAST13_IRQ_ID , @@ -45,35 +45,35 @@ void delay(int count) { } void mstatus_mie_enable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); + volatile int mie_bit = 0x1 << MSTATUS_MIE_BIT; + __asm__ volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); } void mstatus_mie_disable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - asm volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); + volatile int mie_bit = 0x1 << MSTATUS_MIE_BIT; + __asm__ volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); } void mie_enable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); + volatile uint32_t mie_mask = (uint32_t) -1; + __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); } void mie_disable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); + volatile uint32_t mie_mask = (uint32_t) -1; + __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); } void mie_enable(uint32_t irq) { // Enable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); + volatile uint32_t mie_bit = 0x1 << irq; + __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); } void mie_disable(uint32_t irq) { // Disable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); + volatile uint32_t mie_bit = 0x1 << irq; + __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); } void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { @@ -82,13 +82,13 @@ void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { } uint32_t random_num(uint32_t upper_bound, uint32_t lower_bound) { - uint32_t random_num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); - uint32_t num = (random_num % (upper_bound - lower_bound + 1)) + lower_bound; + volatile uint32_t random_num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); + volatile uint32_t num = (random_num % (upper_bound - lower_bound + 1)) + lower_bound; return num; } uint32_t random_num32() { - uint32_t num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); + volatile uint32_t num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); return num; } @@ -98,9 +98,9 @@ void nested_irq_handler(uint32_t id) { // First stack mie, mepc and mstatus // Must be done in critical section with MSTATUS.MIE == 0 volatile uint32_t mie, mepc, mstatus; - asm volatile("csrr %0, mie" : "=r" (mie)); - asm volatile("csrr %0, mepc" :"=r" (mepc)); - asm volatile("csrr %0, mstatus" : "=r" (mstatus)); + __asm__ volatile("csrr %0, mie" : "=r" (mie)); + __asm__ volatile("csrr %0, mepc" :"=r" (mepc)); + __asm__ volatile("csrr %0, mstatus" : "=r" (mstatus)); // Re enable interrupts and create window to enable nested irqs mstatus_mie_enable(); @@ -108,14 +108,13 @@ void nested_irq_handler(uint32_t id) { // Disable MSTATUS.MIE and restore from critical section mstatus_mie_disable(); - asm volatile("csrw mie, %0" : : "r" (mie)); - asm volatile("csrw mepc, %0" : : "r" (mepc)); - asm volatile("csrw mstatus, %0" : : "r" (mstatus)); + __asm__ volatile("csrw mie, %0" : : "r" (mie)); + __asm__ volatile("csrw mepc, %0" : : "r" (mepc)); + __asm__ volatile("csrw mstatus, %0" : : "r" (mstatus)); } void generic_irq_handler(uint32_t id) { - asm volatile("csrr %0, mcause": "=r" (mmcause)); - asm volatile("csrr %0, 0xB03" : "=r" (num_counted_interrupts)); + __asm__ volatile("csrr %0, mcause": "=r" (mmcause)); irq_id = id; // Increment if interrupt @@ -158,72 +157,83 @@ void m_fast15_irq_handler(void) { generic_irq_handler(FAST15_IRQ_ID); } // A Special version of the SW Handler (vector 0) used in the direct mode __attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void) { in_direct_handler = 1; - asm volatile("csrr %0, mcause" : "=r" (mmcause)); + __asm__ volatile ("csrr %0, mcause" : "=r" (mmcause)); if (mmcause >> 31) { num_taken_interrupts++; } } - asm ( +__attribute__((naked)) void alt_vector_table_func() { + __asm__ volatile ( ".global alt_vector_table\n" + ".option push\n" ".option norvc\n" ".align 8\n" "alt_vector_table:\n" - "j u_sw_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_software_irq_handler\n" - "j __no_irq_handler\n" + "j u_sw_irq_handler\n" "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_timer_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_external_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_fast0_irq_handler\n" - "j m_fast1_irq_handler\n" - "j m_fast2_irq_handler\n" - "j m_fast3_irq_handler\n" - "j m_fast4_irq_handler\n" - "j m_fast5_irq_handler\n" - "j m_fast6_irq_handler\n" - "j m_fast7_irq_handler\n" - "j m_fast8_irq_handler\n" - "j m_fast9_irq_handler\n" - "j m_fast10_irq_handler\n" - "j m_fast11_irq_handler\n" - "j m_fast12_irq_handler\n" - "j m_fast13_irq_handler\n" - "j m_fast14_irq_handler\n" - "j m_fast15_irq_handler\n" + "j __no_irq_handler\n" + "j m_software_irq_handler\n" + "j __no_irq_handler\n" + "j __no_irq_handler\n" + "j __no_irq_handler\n" + "j m_timer_irq_handler\n" + "j __no_irq_handler\n" + "j __no_irq_handler\n" + "j __no_irq_handler\n" + "j m_external_irq_handler\n" + "j __no_irq_handler\n" + "j __no_irq_handler\n" + "j __no_irq_handler\n" + "j __no_irq_handler\n" + "j m_fast0_irq_handler\n" + "j m_fast1_irq_handler\n" + "j m_fast2_irq_handler\n" + "j m_fast3_irq_handler\n" + "j m_fast4_irq_handler\n" + "j m_fast5_irq_handler\n" + "j m_fast6_irq_handler\n" + "j m_fast7_irq_handler\n" + "j m_fast8_irq_handler\n" + "j m_fast9_irq_handler\n" + "j m_fast10_irq_handler\n" + "j m_fast11_irq_handler\n" + "j m_fast12_irq_handler\n" + "j m_fast13_irq_handler\n" + "j m_fast14_irq_handler\n" + "j m_fast15_irq_handler\n" + ".option pop\n" ); +} - asm ( +__attribute__((naked)) void alt_direct_vector_table_func() { + __asm__ volatile ( ".global alt_direct_vector_table\n" + ".option push\n" ".option norvc\n" ".align 8\n" "alt_direct_vector_table:\n" - "j u_sw_direct_irq_handler\n" + "j u_sw_direct_irq_handler\n" + ".option pop\n" ); +} - asm ( +__attribute__((naked)) void alt_direct_ecall_table_func() { + __asm__ volatile ( ".global alt_direct_ecall_table\n" + ".option push\n" ".option norvc\n" ".align 8\n" "alt_direct_ecall_table:\n" "wfi\n" - "j u_sw_irq_handler\n" + "j u_sw_irq_handler\n" + ".option pop\n" ); +} int main(int argc, char *argv[]) { - int retval; + volatile int retval; - num_counted_interrupts = 0; num_taken_interrupts = 0; // Enable interrupt performance counter (mhpmcounter3) @@ -289,12 +299,6 @@ int main(int argc, char *argv[]) { // Clear MIE for final WFI mie_disable_all(); - // Check that the interrupt taken counter - if (num_counted_interrupts != num_taken_interrupts) { - printf("mhpmcounter3 (number of events taken) does not match actual interrupts taken: %0d != %0d\n", (int)num_counted_interrupts, (int)num_taken_interrupts); - return ERR_CODE_INTR_CNT; - } - return EXIT_SUCCESS; } @@ -313,13 +317,13 @@ int test1() { // To share implementation of basic interrupt test with vector relocation tests, // break out the test 1 implementation here int test1_impl(int direct_mode) { - for (uint32_t i = 0; i < 32; i++) { + for (volatile uint32_t i = 0; i < 32; i++) { #ifdef DEBUG_MSG printf("Test1 -> Testing interrupt %lu\n", i); #endif - for (uint32_t gmie = 0; gmie <= 1; gmie++) { - for (uint32_t mie = 0; mie <= 1; mie++) { - uint32_t mip; + for (volatile uint32_t gmie = 0; gmie < 1; gmie++) { + for (volatile uint32_t mie = 0; mie < 1; mie++) { + volatile uint32_t mip; // Set global MIE if (gmie) mstatus_mie_enable(); @@ -344,15 +348,15 @@ int test1_impl(int direct_mode) { return ERR_CODE_TEST_1; } if ((mmcause & MCAUSE_IRQ_MASK) != i) { - printf("MCAUSE reported wrong irq, exp = %lu, act = 0x%08lx", i, mmcause); + printf("MCAUSE reported wrong irq, exp = %lu, act = 0x%08lx\n", i, mmcause); return ERR_CODE_TEST_1; } } else { // Unimplemented interrupts, or is a masked irq, delay a bit, waiting for any mmcause - for (int j = 0; j < 20; j++) { + for (volatile int j = 0; j < 20; j++) { if (mmcause != 0) { - printf("MMCAUSE = 0x%08lx when unimplmented interrupt %lu first", mmcause, i); + printf("MMCAUSE = 0x%08lx when unimplmented interrupt %lu first\n", mmcause, i); return ERR_CODE_TEST_1; } } @@ -410,8 +414,8 @@ int test2() { mm_ram_assert_irq(0, 0); // Enable all interrupts (MIE and MSTATUS.MIE) - uint32_t mie = (uint32_t) -1; - asm volatile("csrw mie, %0" : : "r" (mie)); + volatile uint32_t mie = (uint32_t) -1; + __asm__ volatile("csrw mie, %0" : : "r" (mie)); mstatus_mie_enable(); irq_id_q_ptr = 0; @@ -420,7 +424,7 @@ int test2() { delay(100); - for (int i = 0; i < IRQ_NUM; i++) { + for (volatile int i = 0; i < IRQ_NUM; i++) { // The irq_id_q should now contain interrupt IDs in the same order as IRQ_ID_PRIORITY if (IRQ_ID_PRIORITY[i] != irq_id_q[i]) { printf("priority mismatch, index %d, exp %lu, act %lu\n", @@ -448,8 +452,8 @@ int test3() { mstatus_mie_enable(); // Set 2 interrupts - for (uint32_t loop = 0; loop < 50; loop++) { - uint32_t irq[2]; + for (volatile uint32_t loop = 0; loop < 50; loop++) { + volatile uint32_t irq[2]; // Pick 2 random interrupts irq[0] = IRQ_ID_PRIORITY[random_num(IRQ_NUM-1, 0)]; @@ -465,7 +469,7 @@ int test3() { mm_ram_assert_irq(0x1 << irq[0], 0); - delay(50); + delay(10); if (irq_id_q[0] != irq[0]) { printf("TEST3, first interrupt exp %lu act %lu\n", irq[0], irq_id_q[0]); @@ -494,12 +498,12 @@ int test4() { active_test = 4; // Iterate through multiple loops - for (int irq = 0; irq < 32; irq++) { + for (volatile int irq = 0; irq < 32; irq++) { if (!(((0x1 << irq) & IRQ_MASK))) continue; - for (uint32_t gmie = 0; gmie <= 1; gmie++) { - uint32_t rand_irq; + for (volatile uint32_t gmie = 0; gmie <= 1; gmie++) { + volatile uint32_t rand_irq; // Clear MIE and all pending irqs mie_disable_all(); @@ -527,7 +531,7 @@ int test4() { // Random assert "enabled" irq mm_ram_assert_irq(rand_irq | (0x1 << irq), (random_num32() & 0x3f) + 32); - asm volatile("wfi"); + __asm__ volatile("wfi"); if (gmie) { @@ -552,17 +556,17 @@ int test4() { // But with a relocated vector table via mtvec CSR int test5() { volatile uint32_t save_mtvec; - int retval; + volatile int retval; printf("TEST 5 - TRIGGER ALL IRQS IN SEQUENCE (RELOCATED MTVEC):\n"); active_test = 5; - asm volatile("csrr %0, mtvec" : "=r" (save_mtvec)); - asm volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_vector_table | (save_mtvec & 0x3))); + __asm__ volatile("csrr %0, mtvec" : "=r" (save_mtvec)); + __asm__ volatile("csrw mtvec, %0" : : "r" ((volatile uint32_t) alt_vector_table | (save_mtvec & 0x3))); retval = test1_impl(0); - asm volatile("csrw mtvec, %0" : : "r" (save_mtvec)); + __asm__ volatile("csrw mtvec, %0" : : "r" (save_mtvec)); if (retval != EXIT_SUCCESS) { return ERR_CODE_TEST_5; } @@ -574,17 +578,17 @@ int test5() { // But with a relocated vector table via mtvec CSR and DIRECT vector mode int test6() { volatile uint32_t save_mtvec; - int retval; + volatile int retval; printf("TEST 6 - TRIGGER ALL IRQS IN SEQUENCE (DIRECT-MODE MTVEC):\n"); active_test = 6; - asm volatile("csrr %0, mtvec" : "=r" (save_mtvec)); - asm volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_direct_vector_table)); // Leave mode at 0 + __asm__ volatile("csrr %0, mtvec" : "=r" (save_mtvec)); + __asm__ volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_direct_vector_table)); // Leave mode at 0 retval = test1_impl(1); - asm volatile("csrw mtvec, %0" : : "r" (save_mtvec)); + __asm__ volatile("csrw mtvec, %0" : : "r" (save_mtvec)); if (retval != EXIT_SUCCESS) { return ERR_CODE_TEST_6; } @@ -644,18 +648,18 @@ int test9() { active_test = 9; - asm volatile("csrr %0, mtvec" : "=r" (save_mtvec)); - asm volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_direct_ecall_table)); // Leave mode at 0 + __asm__ volatile("csrr %0, mtvec" : "=r" (save_mtvec)); + __asm__ volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_direct_ecall_table)); // Leave mode at 0 mm_ram_assert_irq(0, 0); // Iterate through multiple loops - for (int irq = 0; irq < 32; irq++) { + for (volatile int irq = 0; irq < 32; irq++) { if (!(((0x1 << irq) & IRQ_MASK))) continue; - for (uint32_t gmie = 0; gmie <= 0; gmie++) { - uint32_t rand_irq; + for (volatile uint32_t gmie = 0; gmie <= 0; gmie++) { + volatile uint32_t rand_irq; // Clear MIE and all pending irqs mie_disable_all(); @@ -682,7 +686,7 @@ int test9() { // Random assert "enabled" irq mm_ram_assert_irq(rand_irq | (0x1 << irq), (random_num32() & 0x3f) + 64); - asm volatile("ecall"); + __asm__ volatile("ecall"); if (gmie) { // Expected an interrupt taken @@ -700,7 +704,7 @@ int test9() { } } - asm volatile("csrw mtvec, %0" : : "r" (save_mtvec)); + __asm__ volatile("csrw mtvec, %0" : : "r" (save_mtvec)); return EXIT_SUCCESS; } diff --git a/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.h b/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.h index ebbc09863b..0ef9b7222c 100644 --- a/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.h +++ b/cv32e40s/tests/programs/custom/interrupt_test/interrupt_test.h @@ -14,6 +14,8 @@ // Enable debug messages, note that this will change test timing //#define DEBUG_MSG +#define EXIT_SUCCESS 0 + #define ERR_CODE_TEST_1 1 #define ERR_CODE_TEST_2 2 #define ERR_CODE_TEST_3 3 diff --git a/cv32e40s/tests/programs/custom/interrupt_test/test.yaml b/cv32e40s/tests/programs/custom/interrupt_test/test.yaml index 189f10cb55..a0356e7b53 100644 --- a/cv32e40s/tests/programs/custom/interrupt_test/test.yaml +++ b/cv32e40s/tests/programs/custom/interrupt_test/test.yaml @@ -2,6 +2,8 @@ name: interrupt_test uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Interrupt directed test +cflags: > + -mno-relax diff --git a/cv32e40s/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S b/cv32e40s/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S index c0899c2e4a..5f3c471dbd 100644 --- a/cv32e40s/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S +++ b/cv32e40s/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S @@ -5,7 +5,6 @@ .include "user_define.h" .section .text.start .globl _start -.section .text #.include "user_init.s" .type _start, @function diff --git a/cv32e40s/tests/programs/custom/isa_fcov_holes/test.yaml b/cv32e40s/tests/programs/custom/isa_fcov_holes/test.yaml index e15f2ada00..0afa150406 100644 --- a/cv32e40s/tests/programs/custom/isa_fcov_holes/test.yaml +++ b/cv32e40s/tests/programs/custom/isa_fcov_holes/test.yaml @@ -2,3 +2,4 @@ name: isa_fcov_holes uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Hand-crafted testcase to fill ISA functional coverage holes +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S b/cv32e40s/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S index 708d40c9a7..b685f22802 100644 --- a/cv32e40s/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S +++ b/cv32e40s/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S @@ -32,7 +32,6 @@ .include "user_define.h" .section .text.start .globl _start -.section .text .type _start, @function _start: diff --git a/cv32e40s/tests/programs/custom/load_store_rs1_zero/test.yaml b/cv32e40s/tests/programs/custom/load_store_rs1_zero/test.yaml index 8847229ae2..3681fc8325 100644 --- a/cv32e40s/tests/programs/custom/load_store_rs1_zero/test.yaml +++ b/cv32e40s/tests/programs/custom/load_store_rs1_zero/test.yaml @@ -2,3 +2,4 @@ name: load_store_rs1_zero uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > load and store with rs1=zero +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/README.md b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/README.md new file mode 100644 index 0000000000..54471c257a --- /dev/null +++ b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/README.md @@ -0,0 +1,26 @@ +Generated tests on U-mode access and privilege instructions. + +Needs `CFG=pmp` for allowing U-mode to run. + + +# Python generator files + +## Motivation +Runing through the test-plan it became apparant at some point that it would be necessary to have tests which contained a number of instructions to satisfy testing goals. The solution became python scripts which use string manipulation to generate these instructions directly to the relevant .h and .S files in the directory. + +## Function +The script works by looping through the given file (see the top of the file .py file for name declarations) line by line until a 'trigger' string is reached, usually this string can look something like this: + +``` +// start of generated code +``` + +And everything below this line is then overwritten. + +The script will either have a list called 'reg_string' which is a manually constructed list fetched from a table in the RISC specification. The file will then parse this registry list and create ranges to include all registries within the list. It then writes instructions for that registry to file. Which instructions are based on the test plan. + +Afterwards it searches through the header file and changes the 'ILLEGALLY_GENERATED_INSN' define, which is what both the .S and .c files use when sanity checking or asserting that the number of trapped instructions matches what's been generated. There is also some info printed to the terminal about how many lines and which files are written to. + + +## Maintenance +The scripts are intended to be easily maintenable (although I guess time will tell), and therefore the generation of the instructions themselves are kept within 'generator()' functions and marked variables. If there's a need to change the number of registries, the types of instructions etc. these are found there. Afterwards you should be able to run the script and it will properly update the instructions for you. diff --git a/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/helpers.S b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/helpers.S new file mode 100644 index 0000000000..14a64b26f4 --- /dev/null +++ b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/helpers.S @@ -0,0 +1,38 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly file which holds helper functions used in 'illegal_access_loop_tests.c' to declare pmp_regions or switch privilege_modes. +** +******************************************************************************* +*/ + +.section .text + +.global setup_pmp +.global set_u_mode + +setup_pmp: + // Set pmp addr to 0xFFFF_FFFF + li t0, 0xFFFFFFFF + csrrw x0, pmpaddr0, t0 + + // Set pmp region TOR and read/write/execute + li t0, ((1 << 3) + (7 << 0)) + csrrw x0, pmpcfg0, t0 + + ret + +set_u_mode: // puts the core in usermode. + li t0, 0x1800 // load as bitmask + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrw x0, mepc, ra + mret \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen.py b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen.py new file mode 100644 index 0000000000..253ad778e1 --- /dev/null +++ b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen.py @@ -0,0 +1,99 @@ +""" +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Script to generate access instructions based on 'reg_str' below. Places them in the 'illegal_mcounteren_test.S' file. +** +******************************************************************************* + """ + +# Filenames +filename = "mcounteren_priv_gen_test.S" # file which will be written to +headername = "mcounteren_priv_gen_test.h" # name of the header file + + +# Trigger strings +input_string = "// Start of generated code" # start string, this will move the wrie HEAD +header_string = "#define MCOUNTEREN_DEFAULT_VAL 0x0" # start string script looks for + + +# Global variables +pointer = 0 # file pointer +num_lines = 0 # numebr of lines written to file + + +# Register list which is used to generate the instructions +# List fetched manually from the spec (V20211203), contains all S-, R-, and M-mode CSR registers +reg_str = """ +0xC00-0xC1F +""" + + +# Generator files below. They get the appropriate starting line from the file openers and generate the instructions. + +def generator(): + """ + It splits the 'reg_str' value line by line (also removes empty lines), then converts to base 16 and creates a range from the two numbers. + It loops through this range and writes the numbers (in hex print format) into the assembly file. + After looping through the list it writes some standard lines. + """ + num_lines = 0 # printed later to help debugging, and assertion checks in C. + string_split = (reg_str.split("\n")) + string_split = string_split[1:-1] # removes empty lines after the string_split command + f.seek(pointer) + for register in string_split: + ranges = register.split("-") + rstart = int(ranges[0], 16) # int(x, 16) converts to hex repr. + rend = int(ranges[1], 16) + for i in range(rstart, rend+1): + num_lines += 1 + h = hex(i) + f.write("csrrs t0, " + h + ", x0 " + "\n") + f.write("j end_handler_ret\n") + f.write("\n") + f.write("// end of generated code") + return num_lines + +def header_gen(): + """ + Works the same as the generator function but on a smaller scale. Looks for the 'header_string' and then rewrites the lines below with the update 'num_lines' value + """ + f.seek(pointer) + f.write("// Number of illegaly generated lines as reported by the 'illegal_mcounteren_loop_gen.py'\n") + f.write("#define ILLEGALLY_GENERATED_INSN " + str(num_lines) + "\n") + f.write("\n") + f.write("#endif") + + +# File openers. They run through the file line by line and looks for the start string. They then update the global pointer value for the write HEAD + +with open(filename, "r+") as f: + while f.readline().strip("\n") != input_string: # place header after input_string + pass + pointer = f.tell() + num_lines = generator() + f.truncate() # removes all lines after the last generated line + + + + +with open(headername, "r+") as f: + while f.readline().strip("\n") != header_string: # place HEAD after input_string + pass + pointer = f.tell() + header_gen() + f.truncate() # removes all lines after the last generated line + + +# Print user info to terminal + +print(num_lines, "lines written to file '" + filename + "'") # user info +print("Also changed 'ILLEGALLY_GENERATED_INSN' value to " + str(num_lines) + " in the '" + headername + "' file") # user info \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.S b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.S new file mode 100644 index 0000000000..0a6e1677cd --- /dev/null +++ b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.S @@ -0,0 +1,130 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** This will run the generated mhpcounteren instructions when called from the 'illegal_access_loop_tests.c' +** +******************************************************************************* +*/ + +.global mco_custom +.global mco_instr +.global mco_loop +.global u_sw_irq_handler +.global Check_mcounteren +// Immediate for the trap handler to check to make sure its not looping in infinitely +#include "mcounteren_priv_gen_test.h" + + +mco_loop: // function called from the .c test code. + addi sp,sp,-52 + sw ra, 0(sp) + sw s0, 4(sp) + sw s1, 8(sp) + sw s2, 12(sp) + sw s3, 16(sp) + sw s4, 20(sp) + sw s5, 24(sp) + sw s6, 28(sp) + sw s7, 32(sp) + sw s8, 36(sp) + sw s9, 40(sp) + sw s10, 44(sp) + sw s11, 48(sp) + li s2, 0 + li s3, ILLEGALLY_GENERATED_INSN // load reference value to sanity-check max exceptions + j mco_custom + +exception_max_traps: // if trap count exceeds 'ILLEGALLY_GENERATED_INSN' break and return 0 instead + li s2, 0 + j end_handler_ret + + +Check_mcounteren: // read and return the mcounteren value + add a0, x0, x0 + csrr a0, mcounteren + ret + +end_handler_ret: + addi a0, s2, 0 // load the trap handler return value + lw ra, 0(sp) + lw s0, 4(sp) + lw s1, 8(sp) + lw s2, 12(sp) + lw s3, 16(sp) + lw s4, 20(sp) + lw s5, 24(sp) + lw s6, 28(sp) + lw s7, 32(sp) + lw s8, 36(sp) + lw s9, 40(sp) + lw s10, 44(sp) + lw s11, 48(sp) + addi sp,sp,52 + ret + +u_sw_irq_handler: + + addi s2, s2, 1 // increments every trap + bgt s2, s3, exception_max_traps // check if trap counter has exceeded number of illegal instructions + // csrrw t0, mepc, x0 + addi s4, s4, 4 // increment s4 which holds the pc value (saves a cssrw per loop) + csrrw x0, mepc, s4 // increment to the next execution + mret + + +mco_custom: // puts the core in usermode. + li t0, 0x1800 + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + la t0, mco_instr // load mco_instr to the mepc + la s4, mco_instr // load mco to the s4 register for optimization in the trap handler + csrrw x0, mepc, t0 + mret // call the mret to execute mode change. + + +mco_instr: // start of mcounteren loop test + +// Start of generated code +csrrs t0, 0xc00, x0 +csrrs t0, 0xc01, x0 +csrrs t0, 0xc02, x0 +csrrs t0, 0xc03, x0 +csrrs t0, 0xc04, x0 +csrrs t0, 0xc05, x0 +csrrs t0, 0xc06, x0 +csrrs t0, 0xc07, x0 +csrrs t0, 0xc08, x0 +csrrs t0, 0xc09, x0 +csrrs t0, 0xc0a, x0 +csrrs t0, 0xc0b, x0 +csrrs t0, 0xc0c, x0 +csrrs t0, 0xc0d, x0 +csrrs t0, 0xc0e, x0 +csrrs t0, 0xc0f, x0 +csrrs t0, 0xc10, x0 +csrrs t0, 0xc11, x0 +csrrs t0, 0xc12, x0 +csrrs t0, 0xc13, x0 +csrrs t0, 0xc14, x0 +csrrs t0, 0xc15, x0 +csrrs t0, 0xc16, x0 +csrrs t0, 0xc17, x0 +csrrs t0, 0xc18, x0 +csrrs t0, 0xc19, x0 +csrrs t0, 0xc1a, x0 +csrrs t0, 0xc1b, x0 +csrrs t0, 0xc1c, x0 +csrrs t0, 0xc1d, x0 +csrrs t0, 0xc1e, x0 +csrrs t0, 0xc1f, x0 +j end_handler_ret + +// end of generated code \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.c b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.c new file mode 100644 index 0000000000..bc837f61ed --- /dev/null +++ b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.c @@ -0,0 +1,61 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Contains generated tests on U-mode access and privilege instructions. +** +******************************************************************************* +*/ + +#include +#include +#include "corev_uvmt.h" +#include +#include "mcounteren_priv_gen_test.h" +// extern and global variable declaration +extern volatile void setup_pmp(); +// assembly function which runs and counts all the illegal instructions and exceptions (respectively) +extern volatile uint32_t mco_loop(); +// reads and return the mcounteren register +extern volatile uint32_t Check_mcounteren(); +//extern volatile uint8_t gbl_mysignaltothehandler = 0; +volatile uint32_t exception_trap_increment_counter; + + +// Assert function +static __inline__ void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { + if (actual != expect) { + printf(msg); + printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); + exit(EXIT_FAILURE); + } +} + + + +int main(void){ + + setup_pmp(); // set the pmp regions for U-mode. + + volatile unsigned int mcounteren_assert_val; + mcounteren_assert_val = Check_mcounteren(); // load mcounteren into 'mcounteren_assert_val' + assert_or_die(mcounteren_assert_val, MCOUNTEREN_DEFAULT_VAL, "error: mcounteren illegitimate value\n"); // assert register is zeroed + exception_trap_increment_counter = mco_loop(); + + // Looks for 0 return value, which means no trapped executions or number of traps exceeded number of illegal excecutions + if (exception_trap_increment_counter == 0){ + printf("trap count exceeded number of generated instructions or instructions were not generated!\n"); + exit(EXIT_FAILURE); + } + // The assert number stems from the 'illegal_mcounteren_loop_gen.py' script. The number is printed in the terminal once writing is complete. + assert_or_die(exception_trap_increment_counter, ILLEGALLY_GENERATED_INSN, "error: executions based on zeroed mcounteren did not all trap correctly\n"); + +} \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.h b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.h new file mode 100644 index 0000000000..81f7ffd70c --- /dev/null +++ b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/mcounteren_priv_gen_test.h @@ -0,0 +1,28 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Header file which contains the generated 'ILLEGALLY_GENERATED_INSN' used by the .S and .C files to assert test success. +** Also incudes other defines used in the directory. +******************************************************************************* +*/ + + +#ifndef mcounteren_priv_gen_test_h +#define mcounteren_priv_gen_test_h + +//put your function headers here +// MCOUNTEREN_DEFAULT_VAL is also a target line for the 'illegal_mcounteren_loop_gen.py' file. Changes to this line means you must also change the 'header_string' value in that file! +#define MCOUNTEREN_DEFAULT_VAL 0x0 +// Number of illegaly generated lines as reported by the 'illegal_mcounteren_loop_gen.py' +#define ILLEGALLY_GENERATED_INSN 32 + +#endif \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/test.yaml b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/test.yaml new file mode 100644 index 0000000000..0a297d5e2f --- /dev/null +++ b/cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/test.yaml @@ -0,0 +1,4 @@ +name: mcounteren_priv_gen_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Generated test to check illegal access of csr's \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S b/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S deleted file mode 100644 index 2b8ff9a7a6..0000000000 --- a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S +++ /dev/null @@ -1,1099 +0,0 @@ -# -# Copyright (C) EM Microelectronic US Inc. -# Copyright (C) 2020 OpenHW Group -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. -# -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 -# -############################################################################### -# MHPMCOUNTERS29: access testcase for mhpmcounter3..31 CSRs in cv32e40s. -# Notes: -# 1. This test requires NUM_MHPMCOUNTERS set to 29. -# 2. Does not test function - just access. -# 3. FIXME: ISS currently does not set mcountinhibit correctly on reset -# for non-default number of registers, RVVI and RVFI will mismatch if -# sb checking is enabled. -############################################################################### -#include "corev_uvmt.h" - -.globl _start -.globl main -.globl exit -.global debug -.section .text -.global u_sw_irq_handler - - -#define TEST_PASS 123456789 -#define TEST_FAIL 1 -#define VIRT_PERIPH_STATUS_FLAG_ADDR CV_VP_STATUS_FLAGS_BASE -#define EXPECTED_ILLEGAL_INSTRUCTIONS 24 - -main: - li t0, (0x1 << 3) - csrs mstatus, t0 - li x5, 0x0 - li x6, 0x6 - li x7, 0x7 - li x8, 0x8 - li x9, 0x9 - li x10, 0xa - li x11, 0xb - li x12, 0xc - li x13, 0xd - li x14, 0xe - li x15, 0xf - li x16, 0x10 - li x17, 0x11 - li x18, 0x12 - li x19, 0x13 - li x20, 0x14 - li x21, 0x15 - li x22, 0x16 - li x23, 0x17 - li x24, 0x18 - li x25, 0x19 - li x28, 0x1c - li x29, 0x1d - li x30, 0x1e - li x31, 0x0 - addi sp,sp,-84 - sw x6,80(sp) - sw x7,76(sp) - sw x8,72(sp) - sw x9,68(sp) - sw x10,64(sp) - sw x11,60(sp) - sw x12,56(sp) - sw x13,52(sp) - sw x14,48(sp) - sw x15,44(sp) - sw x16,40(sp) - sw x17,36(sp) - sw x18,32(sp) - sw x19,28(sp) - sw x20,24(sp) - sw x21,20(sp) - sw x22,16(sp) - sw x23,12(sp) - sw x24,8(sp) - sw x25,4(sp) -############################################################################### -# Do-nothing reads/writes to mhpmevent3..31, mhpmcounter3..31, mhpmcounterh3..31, -# to ensure that all CSR instructions ping each of these CSRs at least once. - - # mhpmevent3 - csrrci x5, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0x323, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0x323, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0x323, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0x323, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmevent4 - csrrci x5, 0x324, 0x0a - csrrc x5, 0x324, x0 - csrrc x0, 0x324, x5 - csrrci x5, 0x324, 0x0a - csrrs x0, 0x324, x5 - csrrsi x0, 0x324, 0x0a - csrrw x0, 0x324, x0 - csrrwi x0, 0x324, 0x0a - - # mhpmevent5 - csrrci x5, 0x325, 0x0a - csrrc x5, 0x325, x0 - csrrc x0, 0x325, x5 - csrrci x5, 0x325, 0x0a - csrrs x0, 0x325, x5 - csrrsi x0, 0x325, 0x0a - csrrw x0, 0x325, x0 - csrrwi x0, 0x325, 0x0a - - # mhpmevent6 - csrrci x5, 0x326, 0x0a - csrrc x5, 0x326, x0 - csrrc x0, 0x326, x5 - csrrci x5, 0x326, 0x0a - csrrs x0, 0x326, x5 - csrrsi x0, 0x326, 0x0a - csrrw x0, 0x326, x0 - csrrwi x0, 0x326, 0x0a - - # mhpmevent7 - csrrci x5, 0x327, 0x0a - csrrc x5, 0x327, x0 - csrrc x0, 0x327, x5 - csrrci x5, 0x327, 0x0a - csrrs x0, 0x327, x5 - csrrsi x0, 0x327, 0x0a - csrrw x0, 0x327, x0 - csrrwi x0, 0x327, 0x0a - - # mhpmevent8 - csrrci x5, 0x328, 0x0a - csrrc x5, 0x328, x0 - csrrc x0, 0x328, x5 - csrrci x5, 0x328, 0x0a - csrrs x0, 0x328, x5 - csrrsi x0, 0x328, 0x0a - csrrw x0, 0x328, x0 - csrrwi x0, 0x328, 0x0a - - # mhpmevent9 - csrrci x5, 0x329, 0x0a - csrrc x5, 0x329, x0 - csrrc x0, 0x329, x5 - csrrci x5, 0x329, 0x0a - csrrs x0, 0x329, x5 - csrrsi x0, 0x329, 0x0a - csrrw x0, 0x329, x0 - csrrwi x0, 0x329, 0x0a - - # mhpmevent10 - csrrci x5, 0x32a, 0x0a - csrrc x5, 0x32a, x0 - csrrc x0, 0x32a, x5 - csrrci x5, 0x32a, 0x0a - csrrs x0, 0x32a, x5 - csrrsi x0, 0x32a, 0x0a - csrrw x0, 0x32a, x0 - csrrwi x0, 0x32a, 0x0a - - # mhpmevent11 - csrrci x5, 0x32b, 0x0a - csrrc x5, 0x32b, x0 - csrrc x0, 0x32b, x5 - csrrci x5, 0x32b, 0x0a - csrrs x0, 0x32b, x5 - csrrsi x0, 0x32b, 0x0a - csrrw x0, 0x32b, x0 - csrrwi x0, 0x32b, 0x0a - - # mhpmevent12 - csrrci x5, 0x32c, 0x0a - csrrc x5, 0x32c, x0 - csrrc x0, 0x32c, x5 - csrrci x5, 0x32c, 0x0a - csrrs x0, 0x32c, x5 - csrrsi x0, 0x32c, 0x0a - csrrw x0, 0x32c, x0 - csrrwi x0, 0x32c, 0x0a - - # mhpmevent13 - csrrci x5, 0x32d, 0x0a - csrrc x5, 0x32d, x0 - csrrc x0, 0x32d, x5 - csrrci x5, 0x32d, 0x0a - csrrs x0, 0x32d, x5 - csrrsi x0, 0x32d, 0x0a - csrrw x0, 0x32d, x0 - csrrwi x0, 0x32d, 0x0a - - # mhpmevent14 - csrrci x5, 0x32e, 0x0a - csrrc x5, 0x32e, x0 - csrrc x0, 0x32e, x5 - csrrci x5, 0x32e, 0x0a - csrrs x0, 0x32e, x5 - csrrsi x0, 0x32e, 0x0a - csrrw x0, 0x32e, x0 - csrrwi x0, 0x32e, 0x0a - - # mhpmevent15 - csrrci x5, 0x32f, 0x0a - csrrc x5, 0x32f, x0 - csrrc x0, 0x32f, x5 - csrrci x5, 0x32f, 0x0a - csrrs x0, 0x32f, x5 - csrrsi x0, 0x32f, 0x0a - csrrw x0, 0x32f, x0 - csrrwi x0, 0x32f, 0x0a - - # mhpmevent16 - csrrci x5, 0x330, 0x0a - csrrc x5, 0x330, x0 - csrrc x0, 0x330, x5 - csrrci x5, 0x330, 0x0a - csrrs x0, 0x330, x5 - csrrsi x0, 0x330, 0x0a - csrrw x0, 0x330, x0 - csrrwi x0, 0x330, 0x0a - - # mhpmevent17 - csrrci x5, 0x331, 0x0a - csrrc x5, 0x331, x0 - csrrc x0, 0x331, x5 - csrrci x5, 0x331, 0x0a - csrrs x0, 0x331, x5 - csrrsi x0, 0x331, 0x0a - csrrw x0, 0x331, x0 - csrrwi x0, 0x331, 0x0a - - # mhpmevent18 - csrrci x5, 0x332, 0x0a - csrrc x5, 0x332, x0 - csrrc x0, 0x332, x5 - csrrci x5, 0x332, 0x0a - csrrs x0, 0x332, x5 - csrrsi x0, 0x332, 0x0a - csrrw x0, 0x332, x0 - csrrwi x0, 0x332, 0x0a - - # mhpmevent19 - csrrci x5, 0x333, 0x0a - csrrc x5, 0x333, x0 - csrrc x0, 0x333, x5 - csrrci x5, 0x333, 0x0a - csrrs x0, 0x333, x5 - csrrsi x0, 0x333, 0x0a - csrrw x0, 0x333, x0 - csrrwi x0, 0x333, 0x0a - - # mhpmevent20 - csrrci x5, 0x334, 0x0a - csrrc x5, 0x334, x0 - csrrc x0, 0x334, x5 - csrrci x5, 0x334, 0x0a - csrrs x0, 0x334, x5 - csrrsi x0, 0x334, 0x0a - csrrw x0, 0x334, x0 - csrrwi x0, 0x334, 0x0a - - # mhpmevent21 - csrrci x5, 0x335, 0x0a - csrrc x5, 0x335, x0 - csrrc x0, 0x335, x5 - csrrci x5, 0x335, 0x0a - csrrs x0, 0x335, x5 - csrrsi x0, 0x335, 0x0a - csrrw x0, 0x335, x0 - csrrwi x0, 0x335, 0x0a - - # mhpmevent22 - csrrci x5, 0x336, 0x0a - csrrc x5, 0x336, x0 - csrrc x0, 0x336, x5 - csrrci x5, 0x336, 0x0a - csrrs x0, 0x336, x5 - csrrsi x0, 0x336, 0x0a - csrrw x0, 0x336, x0 - csrrwi x0, 0x336, 0x0a - - # mhpmevent23 - csrrci x5, 0x337, 0x0a - csrrc x5, 0x337, x0 - csrrc x0, 0x337, x5 - csrrci x5, 0x337, 0x0a - csrrs x0, 0x337, x5 - csrrsi x0, 0x337, 0x0a - csrrw x0, 0x337, x0 - csrrwi x0, 0x337, 0x0a - - # mhpmevent24 - csrrci x5, 0x338, 0x0a - csrrc x5, 0x338, x0 - csrrc x0, 0x338, x5 - csrrci x5, 0x338, 0x0a - csrrs x0, 0x338, x5 - csrrsi x0, 0x338, 0x0a - csrrw x0, 0x338, x0 - csrrwi x0, 0x338, 0x0a - - # mhpmevent25 - csrrci x5, 0x339, 0x0a - csrrc x5, 0x339, x0 - csrrc x0, 0x339, x5 - csrrci x5, 0x339, 0x0a - csrrs x0, 0x339, x5 - csrrsi x0, 0x339, 0x0a - csrrw x0, 0x339, x0 - csrrwi x0, 0x339, 0x0a - - # mhpmevent26 - csrrci x5, 0x33a, 0x0a - csrrc x5, 0x33a, x0 - csrrc x0, 0x33a, x5 - csrrci x5, 0x33a, 0x0a - csrrs x0, 0x33a, x5 - csrrsi x0, 0x33a, 0x0a - csrrw x0, 0x33a, x0 - csrrwi x0, 0x33a, 0x0a - - # mhpmevent27 - csrrci x5, 0x33b, 0x0a - csrrc x5, 0x33b, x0 - csrrc x0, 0x33b, x5 - csrrci x5, 0x33b, 0x0a - csrrs x0, 0x33b, x5 - csrrsi x0, 0x33b, 0x0a - csrrw x0, 0x33b, x0 - csrrwi x0, 0x33b, 0x0a - - # mhpmevent28 - csrrci x5, 0x33c, 0x0a - csrrc x5, 0x33c, x0 - csrrc x0, 0x33c, x5 - csrrci x5, 0x33c, 0x0a - csrrs x0, 0x33c, x5 - csrrsi x0, 0x33c, 0x0a - csrrw x0, 0x33c, x0 - csrrwi x0, 0x33c, 0x0a - - # mhpmevent29 - csrrci x5, 0x33d, 0x0a - csrrc x5, 0x33d, x0 - csrrc x0, 0x33d, x5 - csrrci x5, 0x33d, 0x0a - csrrs x0, 0x33d, x5 - csrrsi x0, 0x33d, 0x0a - csrrw x0, 0x33d, x0 - csrrwi x0, 0x33d, 0x0a - - # mhpmevent30 - csrrci x5, 0x33e, 0x0a - csrrc x5, 0x33e, x0 - csrrc x0, 0x33e, x5 - csrrci x5, 0x33e, 0x0a - csrrs x0, 0x33e, x5 - csrrsi x0, 0x33e, 0x0a - csrrw x0, 0x33e, x0 - csrrwi x0, 0x33e, 0x0a - - # mhpmevent31 - csrrci x5, 0x33f, 0x0a - csrrc x5, 0x33f, x0 - csrrc x0, 0x33f, x5 - csrrci x5, 0x33f, 0x0a - csrrs x0, 0x33f, x5 - csrrsi x0, 0x33f, 0x0a - csrrw x0, 0x33f, x0 - csrrwi x0, 0x33f, 0x0a - - ################ - - # mhpmcounter3 - csrrci x5, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0xB03, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0xB03, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0xB03, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0xB03, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmcounter4 - csrrci x5, 0xB04, 0x0a - csrrc x5, 0xB04, x0 - csrrc x0, 0xB04, x5 - csrrci x5, 0xB04, 0x0a - csrrs x0, 0xB04, x5 - csrrsi x0, 0xB04, 0x0a - csrrw x0, 0xB04, x0 - csrrwi x0, 0xB04, 0x0a - - # mhpmcounter5 - csrrci x5, 0xB05, 0x0a - csrrc x5, 0xB05, x0 - csrrc x0, 0xB05, x5 - csrrci x5, 0xB05, 0x0a - csrrs x0, 0xB05, x5 - csrrsi x0, 0xB05, 0x0a - csrrw x0, 0xB05, x0 - csrrwi x0, 0xB05, 0x0a - - # mhpmcounter6 - csrrci x5, 0xB06, 0x0a - csrrc x5, 0xB06, x0 - csrrc x0, 0xB06, x5 - csrrci x5, 0xB06, 0x0a - csrrs x0, 0xB06, x5 - csrrsi x0, 0xB06, 0x0a - csrrw x0, 0xB06, x0 - csrrwi x0, 0xB06, 0x0a - - # mhpmcounter7 - csrrci x5, 0xB07, 0x0a - csrrc x5, 0xB07, x0 - csrrc x0, 0xB07, x5 - csrrci x5, 0xB07, 0x0a - csrrs x0, 0xB07, x5 - csrrsi x0, 0xB07, 0x0a - csrrw x0, 0xB07, x0 - csrrwi x0, 0xB07, 0x0a - - # mhpmcounter8 - csrrci x5, 0xB08, 0x0a - csrrc x5, 0xB08, x0 - csrrc x0, 0xB08, x5 - csrrci x5, 0xB08, 0x0a - csrrs x0, 0xB08, x5 - csrrsi x0, 0xB08, 0x0a - csrrw x0, 0xB08, x0 - csrrwi x0, 0xB08, 0x0a - - # mhpmcounter9 - csrrci x5, 0xB09, 0x0a - csrrc x5, 0xB09, x0 - csrrc x0, 0xB09, x5 - csrrci x5, 0xB09, 0x0a - csrrs x0, 0xB09, x5 - csrrsi x0, 0xB09, 0x0a - csrrw x0, 0xB09, x0 - csrrwi x0, 0xB09, 0x0a - - # mhpmcounter10 - csrrci x5, 0xB0A, 0x0a - csrrc x5, 0xB0A, x0 - csrrc x0, 0xB0A, x5 - csrrci x5, 0xB0A, 0x0a - csrrs x0, 0xB0A, x5 - csrrsi x0, 0xB0A, 0x0a - csrrw x0, 0xB0A, x0 - csrrwi x0, 0xB0A, 0x0a - - # mhpmcounter11 - csrrci x5, 0xB0B, 0x0a - csrrc x5, 0xB0B, x0 - csrrc x0, 0xB0B, x5 - csrrci x5, 0xB0B, 0x0a - csrrs x0, 0xB0B, x5 - csrrsi x0, 0xB0B, 0x0a - csrrw x0, 0xB0B, x0 - csrrwi x0, 0xB0B, 0x0a - - # mhpmcounter12 - csrrci x5, 0xB0C, 0x0a - csrrc x5, 0xB0C, x0 - csrrc x0, 0xB0C, x5 - csrrci x5, 0xB0C, 0x0a - csrrs x0, 0xB0C, x5 - csrrsi x0, 0xB0C, 0x0a - csrrw x0, 0xB0C, x0 - csrrwi x0, 0xB0C, 0x0a - - # mhpmcounter13 - csrrci x5, 0xB0D, 0x0a - csrrc x5, 0xB0D, x0 - csrrc x0, 0xB0D, x5 - csrrci x5, 0xB0D, 0x0a - csrrs x0, 0xB0D, x5 - csrrsi x0, 0xB0D, 0x0a - csrrw x0, 0xB0D, x0 - csrrwi x0, 0xB0D, 0x0a - - # mhpmcounter14 - csrrci x5, 0xB0E, 0x0a - csrrc x5, 0xB0E, x0 - csrrc x0, 0xB0E, x5 - csrrci x5, 0xB0E, 0x0a - csrrs x0, 0xB0E, x5 - csrrsi x0, 0xB0E, 0x0a - csrrw x0, 0xB0E, x0 - csrrwi x0, 0xB0E, 0x0a - - # mhpmcounter15 - csrrci x5, 0xB0F, 0x0a - csrrc x5, 0xB0F, x0 - csrrc x0, 0xB0F, x5 - csrrci x5, 0xB0F, 0x0a - csrrs x0, 0xB0F, x5 - csrrsi x0, 0xB0F, 0x0a - csrrw x0, 0xB0F, x0 - csrrwi x0, 0xB0F, 0x0a - - # mhpmcounter16 - csrrci x5, 0xB10, 0x0a - csrrc x5, 0xB10, x0 - csrrc x0, 0xB10, x5 - csrrci x5, 0xB10, 0x0a - csrrs x0, 0xB10, x5 - csrrsi x0, 0xB10, 0x0a - csrrw x0, 0xB10, x0 - csrrwi x0, 0xB10, 0x0a - - # mhpmcounter17 - csrrci x5, 0xB11, 0x0a - csrrc x5, 0xB11, x0 - csrrc x0, 0xB11, x5 - csrrci x5, 0xB11, 0x0a - csrrs x0, 0xB11, x5 - csrrsi x0, 0xB11, 0x0a - csrrw x0, 0xB11, x0 - csrrwi x0, 0xB11, 0x0a - - # mhpmcounter18 - csrrci x5, 0xB12, 0x0a - csrrc x5, 0xB12, x0 - csrrc x0, 0xB12, x5 - csrrci x5, 0xB12, 0x0a - csrrs x0, 0xB12, x5 - csrrsi x0, 0xB12, 0x0a - csrrw x0, 0xB12, x0 - csrrwi x0, 0xB12, 0x0a - - # mhpmcounter19 - csrrci x5, 0xB13, 0x0a - csrrc x5, 0xB13, x0 - csrrc x0, 0xB13, x5 - csrrci x5, 0xB13, 0x0a - csrrs x0, 0xB13, x5 - csrrsi x0, 0xB13, 0x0a - csrrw x0, 0xB13, x0 - csrrwi x0, 0xB13, 0x0a - - # mhpmcounter20 - csrrci x5, 0xB14, 0x0a - csrrc x5, 0xB14, x0 - csrrc x0, 0xB14, x5 - csrrci x5, 0xB14, 0x0a - csrrs x0, 0xB14, x5 - csrrsi x0, 0xB14, 0x0a - csrrw x0, 0xB14, x0 - csrrwi x0, 0xB14, 0x0a - - # mhpmcounter21 - csrrci x5, 0xB15, 0x0a - csrrc x5, 0xB15, x0 - csrrc x0, 0xB15, x5 - csrrci x5, 0xB15, 0x0a - csrrs x0, 0xB15, x5 - csrrsi x0, 0xB15, 0x0a - csrrw x0, 0xB15, x0 - csrrwi x0, 0xB15, 0x0a - - # mhpmcounter22 - csrrci x5, 0xB16, 0x0a - csrrc x5, 0xB16, x0 - csrrc x0, 0xB16, x5 - csrrci x5, 0xB16, 0x0a - csrrs x0, 0xB16, x5 - csrrsi x0, 0xB16, 0x0a - csrrw x0, 0xB16, x0 - csrrwi x0, 0xB16, 0x0a - - # mhpmcounter23 - csrrci x5, 0xB17, 0x0a - csrrc x5, 0xB17, x0 - csrrc x0, 0xB17, x5 - csrrci x5, 0xB17, 0x0a - csrrs x0, 0xB17, x5 - csrrsi x0, 0xB17, 0x0a - csrrw x0, 0xB17, x0 - csrrwi x0, 0xB17, 0x0a - - # mhpmcounter24 - csrrci x5, 0xB18, 0x0a - csrrc x5, 0xB18, x0 - csrrc x0, 0xB18, x5 - csrrci x5, 0xB18, 0x0a - csrrs x0, 0xB18, x5 - csrrsi x0, 0xB18, 0x0a - csrrw x0, 0xB18, x0 - csrrwi x0, 0xB18, 0x0a - - # mhpmcounter25 - csrrci x5, 0xB19, 0x0a - csrrc x5, 0xB19, x0 - csrrc x0, 0xB19, x5 - csrrci x5, 0xB19, 0x0a - csrrs x0, 0xB19, x5 - csrrsi x0, 0xB19, 0x0a - csrrw x0, 0xB19, x0 - csrrwi x0, 0xB19, 0x0a - - # mhpmcounter26 - csrrci x5, 0xB1A, 0x0a - csrrc x5, 0xB1A, x0 - csrrc x0, 0xB1A, x5 - csrrci x5, 0xB1A, 0x0a - csrrs x0, 0xB1A, x5 - csrrsi x0, 0xB1A, 0x0a - csrrw x0, 0xB1A, x0 - csrrwi x0, 0xB1A, 0x0a - - # mhpmcounter27 - csrrci x5, 0xB1B, 0x0a - csrrc x5, 0xB1B, x0 - csrrc x0, 0xB1B, x5 - csrrci x5, 0xB1B, 0x0a - csrrs x0, 0xB1B, x5 - csrrsi x0, 0xB1B, 0x0a - csrrw x0, 0xB1B, x0 - csrrwi x0, 0xB1B, 0x0a - - # mhpmcounter28 - csrrci x5, 0xB1C, 0x0a - csrrc x5, 0xB1C, x0 - csrrc x0, 0xB1C, x5 - csrrci x5, 0xB1C, 0x0a - csrrs x0, 0xB1C, x5 - csrrsi x0, 0xB1C, 0x0a - csrrw x0, 0xB1C, x0 - csrrwi x0, 0xB1C, 0x0a - - # mhpmcounter29 - csrrci x5, 0xB1D, 0x0a - csrrc x5, 0xB1D, x0 - csrrc x0, 0xB1D, x5 - csrrci x5, 0xB1D, 0x0a - csrrs x0, 0xB1D, x5 - csrrsi x0, 0xB1D, 0x0a - csrrw x0, 0xB1D, x0 - csrrwi x0, 0xB1D, 0x0a - - # mhpmcounter30 - csrrci x5, 0xB1E, 0x0a - csrrc x5, 0xB1E, x0 - csrrc x0, 0xB1E, x5 - csrrci x5, 0xB1E, 0x0a - csrrs x0, 0xB1E, x5 - csrrsi x0, 0xB1E, 0x0a - csrrw x0, 0xB1E, x0 - csrrwi x0, 0xB1E, 0x0a - - # mhpmcounter31 - csrrci x5, 0xB1F, 0x0a - csrrc x5, 0xB1F, x0 - csrrc x0, 0xB1F, x5 - csrrci x5, 0xB1F, 0x0a - csrrs x0, 0xB1F, x5 - csrrsi x0, 0xB1F, 0x0a - csrrw x0, 0xB1F, x0 - csrrwi x0, 0xB1F, 0x0a - - ################ - - # mhpmcounter3h - csrrci x5, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0xB83, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0xB83, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0xB83, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0xB83, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmcounter4h - csrrci x5, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0xB84, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0xB84, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0xB84, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0xB84, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmcounterh5 - csrrci x5, 0xB85, 0x0a - csrrc x5, 0xB85, x0 - csrrc x0, 0xB85, x5 - csrrci x5, 0xB85, 0x0a - csrrs x0, 0xB85, x5 - csrrsi x0, 0xB85, 0x0a - csrrw x0, 0xB85, x0 - csrrwi x0, 0xB85, 0x0a - - # mhpmcounterh6 - csrrci x5, 0xB86, 0x0a - csrrc x5, 0xB86, x0 - csrrc x0, 0xB86, x5 - csrrci x5, 0xB86, 0x0a - csrrs x0, 0xB86, x5 - csrrsi x0, 0xB86, 0x0a - csrrw x0, 0xB86, x0 - csrrwi x0, 0xB86, 0x0a - - # mhpmcounterh7 - csrrci x5, 0xB87, 0x0a - csrrc x5, 0xB87, x0 - csrrc x0, 0xB87, x5 - csrrci x5, 0xB87, 0x0a - csrrs x0, 0xB87, x5 - csrrsi x0, 0xB87, 0x0a - csrrw x0, 0xB87, x0 - csrrwi x0, 0xB87, 0x0a - - # mhpmcounterh8 - csrrci x5, 0xB88, 0x0a - csrrc x5, 0xB88, x0 - csrrc x0, 0xB88, x5 - csrrci x5, 0xB88, 0x0a - csrrs x0, 0xB88, x5 - csrrsi x0, 0xB88, 0x0a - csrrw x0, 0xB88, x0 - csrrwi x0, 0xB88, 0x0a - - # mhpmcounterh9 - csrrci x5, 0xB89, 0x0a - csrrc x5, 0xB89, x0 - csrrc x0, 0xB89, x5 - csrrci x5, 0xB89, 0x0a - csrrs x0, 0xB89, x5 - csrrsi x0, 0xB89, 0x0a - csrrw x0, 0xB89, x0 - csrrwi x0, 0xB89, 0x0a - - # mhpmcounterh10 - csrrci x5, 0xB8A, 0x0a - csrrc x5, 0xB8A, x0 - csrrc x0, 0xB8A, x5 - csrrci x5, 0xB8A, 0x0a - csrrs x0, 0xB8A, x5 - csrrsi x0, 0xB8A, 0x0a - csrrw x0, 0xB8A, x0 - csrrwi x0, 0xB8A, 0x0a - - # mhpmcounterh11 - csrrci x5, 0xB8B, 0x0a - csrrc x5, 0xB8B, x0 - csrrc x0, 0xB8B, x5 - csrrci x5, 0xB8B, 0x0a - csrrs x0, 0xB8B, x5 - csrrsi x0, 0xB8B, 0x0a - csrrw x0, 0xB8B, x0 - csrrwi x0, 0xB8B, 0x0a - - # mhpmcounterh12 - csrrci x5, 0xB8C, 0x0a - csrrc x5, 0xB8C, x0 - csrrc x0, 0xB8C, x5 - csrrci x5, 0xB8C, 0x0a - csrrs x0, 0xB8C, x5 - csrrsi x0, 0xB8C, 0x0a - csrrw x0, 0xB8C, x0 - csrrwi x0, 0xB8C, 0x0a - - # mhpmcounterh13 - csrrci x5, 0xB8D, 0x0a - csrrc x5, 0xB8D, x0 - csrrc x0, 0xB8D, x5 - csrrci x5, 0xB8D, 0x0a - csrrs x0, 0xB8D, x5 - csrrsi x0, 0xB8D, 0x0a - csrrw x0, 0xB8D, x0 - csrrwi x0, 0xB8D, 0x0a - - # mhpmcounterh14 - csrrci x5, 0xB8E, 0x0a - csrrc x5, 0xB8E, x0 - csrrc x0, 0xB8E, x5 - csrrci x5, 0xB8E, 0x0a - csrrs x0, 0xB8E, x5 - csrrsi x0, 0xB8E, 0x0a - csrrw x0, 0xB8E, x0 - csrrwi x0, 0xB8E, 0x0a - - # mhpmcounterh15 - csrrci x5, 0xB8F, 0x0a - csrrc x5, 0xB8F, x0 - csrrc x0, 0xB8F, x5 - csrrci x5, 0xB8F, 0x0a - csrrs x0, 0xB8F, x5 - csrrsi x0, 0xB8F, 0x0a - csrrw x0, 0xB8F, x0 - csrrwi x0, 0xB8F, 0x0a - - # mhpmcounterh16 - csrrci x5, 0xB90, 0x0a - csrrc x5, 0xB90, x0 - csrrc x0, 0xB90, x5 - csrrci x5, 0xB90, 0x0a - csrrs x0, 0xB90, x5 - csrrsi x0, 0xB90, 0x0a - csrrw x0, 0xB90, x0 - csrrwi x0, 0xB90, 0x0a - - # mhpmcounterh17 - csrrci x5, 0xB91, 0x0a - csrrc x5, 0xB91, x0 - csrrc x0, 0xB91, x5 - csrrci x5, 0xB91, 0x0a - csrrs x0, 0xB91, x5 - csrrsi x0, 0xB91, 0x0a - csrrw x0, 0xB91, x0 - csrrwi x0, 0xB91, 0x0a - - # mhpmcounterh18 - csrrci x5, 0xB92, 0x0a - csrrc x5, 0xB92, x0 - csrrc x0, 0xB92, x5 - csrrci x5, 0xB92, 0x0a - csrrs x0, 0xB92, x5 - csrrsi x0, 0xB92, 0x0a - csrrw x0, 0xB92, x0 - csrrwi x0, 0xB92, 0x0a - - # mhpmcounterh19 - csrrci x5, 0xB93, 0x0a - csrrc x5, 0xB93, x0 - csrrc x0, 0xB93, x5 - csrrci x5, 0xB93, 0x0a - csrrs x0, 0xB93, x5 - csrrsi x0, 0xB93, 0x0a - csrrw x0, 0xB93, x0 - csrrwi x0, 0xB93, 0x0a - - # mhpmcounterh20 - csrrci x5, 0xB94, 0x0a - csrrc x5, 0xB94, x0 - csrrc x0, 0xB94, x5 - csrrci x5, 0xB94, 0x0a - csrrs x0, 0xB94, x5 - csrrsi x0, 0xB94, 0x0a - csrrw x0, 0xB94, x0 - csrrwi x0, 0xB94, 0x0a - - # mhpmcounterh21 - csrrci x5, 0xB95, 0x0a - csrrc x5, 0xB95, x0 - csrrc x0, 0xB95, x5 - csrrci x5, 0xB95, 0x0a - csrrs x0, 0xB95, x5 - csrrsi x0, 0xB95, 0x0a - csrrw x0, 0xB95, x0 - csrrwi x0, 0xB95, 0x0a - - # mhpmcounterh22 - csrrci x5, 0xB96, 0x0a - csrrc x5, 0xB96, x0 - csrrc x0, 0xB96, x5 - csrrci x5, 0xB96, 0x0a - csrrs x0, 0xB96, x5 - csrrsi x0, 0xB96, 0x0a - csrrw x0, 0xB96, x0 - csrrwi x0, 0xB96, 0x0a - - # mhpmcounterh23 - csrrci x5, 0xB97, 0x0a - csrrc x5, 0xB97, x0 - csrrc x0, 0xB97, x5 - csrrci x5, 0xB97, 0x0a - csrrs x0, 0xB97, x5 - csrrsi x0, 0xB97, 0x0a - csrrw x0, 0xB97, x0 - csrrwi x0, 0xB97, 0x0a - - # mhpmcounterh24 - csrrci x5, 0xB98, 0x0a - csrrc x5, 0xB98, x0 - csrrc x0, 0xB98, x5 - csrrci x5, 0xB98, 0x0a - csrrs x0, 0xB98, x5 - csrrsi x0, 0xB98, 0x0a - csrrw x0, 0xB98, x0 - csrrwi x0, 0xB98, 0x0a - - # mhpmcounterh25 - csrrci x5, 0xB99, 0x0a - csrrc x5, 0xB99, x0 - csrrc x0, 0xB99, x5 - csrrci x5, 0xB99, 0x0a - csrrs x0, 0xB99, x5 - csrrsi x0, 0xB99, 0x0a - csrrw x0, 0xB99, x0 - csrrwi x0, 0xB99, 0x0a - - # mhpmcounterh26 - csrrci x5, 0xB9A, 0x0a - csrrc x5, 0xB9A, x0 - csrrc x0, 0xB9A, x5 - csrrci x5, 0xB9A, 0x0a - csrrs x0, 0xB9A, x5 - csrrsi x0, 0xB9A, 0x0a - csrrw x0, 0xB9A, x0 - csrrwi x0, 0xB9A, 0x0a - - # mhpmcounterh27 - csrrci x5, 0xB9B, 0x0a - csrrc x5, 0xB9B, x0 - csrrc x0, 0xB9B, x5 - csrrci x5, 0xB9B, 0x0a - csrrs x0, 0xB9B, x5 - csrrsi x0, 0xB9B, 0x0a - csrrw x0, 0xB9B, x0 - csrrwi x0, 0xB9B, 0x0a - - # mhpmcounterh28 - csrrci x5, 0xB9C, 0x0a - csrrc x5, 0xB9C, x0 - csrrc x0, 0xB9C, x5 - csrrci x5, 0xB9C, 0x0a - csrrs x0, 0xB9C, x5 - csrrsi x0, 0xB9C, 0x0a - csrrw x0, 0xB9C, x0 - csrrwi x0, 0xB9C, 0x0a - - # mhpmcounterh29 - csrrci x5, 0xB9D, 0x0a - csrrc x5, 0xB9D, x0 - csrrc x0, 0xB9D, x5 - csrrci x5, 0xB9D, 0x0a - csrrs x0, 0xB9D, x5 - csrrsi x0, 0xB9D, 0x0a - csrrw x0, 0xB9D, x0 - csrrwi x0, 0xB9D, 0x0a - - # mhpmcounterh30 - csrrci x5, 0xB9E, 0x0a - csrrc x5, 0xB9E, x0 - csrrc x0, 0xB9E, x5 - csrrci x5, 0xB9E, 0x0a - csrrs x0, 0xB9E, x5 - csrrsi x0, 0xB9E, 0x0a - csrrw x0, 0xB9E, x0 - csrrwi x0, 0xB9E, 0x0a - - # mhpmcounterh31 - csrrci x5, 0xB9F, 0x0a - csrrc x5, 0xB9F, x0 - csrrc x0, 0xB9F, x5 - csrrci x5, 0xB9F, 0x0a - csrrs x0, 0xB9F, x5 - csrrsi x0, 0xB9F, 0x0a - csrrw x0, 0xB9F, x0 - csrrwi x0, 0xB9F, 0x0a - -############################################################################### -# Access a few other CSRs, including accesses that throw illegal instruction -# exceptions. - - # mvendorid - csrrc x5, 3857, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3857, x5 # illegal instruction: attempt to write RO CSR - csrrci x5, 3857, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3857, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3857, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3857, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3857, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3857, x0 # not illegal - li x30, 0x00000602 - bne x5, x30, fail - - # marchid - csrrc x5, 3858, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3858, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 3858, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3858, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3858, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3858, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3858, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3858, x0 # not illegal - li x30, 0x00000014 - bne x5, x30, fail - - # mipmid - csrrc x5, 3859, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3859, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3859, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3859, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3859, x0 # not illegal - li x30, 0x00000000 - bne x5, x30, fail - - # mhartid - csrrc x5, 3860, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3860, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 3860, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3860, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3860, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3860, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3860, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3860, x0 # not illegal - li x30, 0x00000000 - bne x5, x30, fail - -############################################################################### - lw x5,80(sp) - bne x5, x6, fail - lw x5,76(sp) - bne x5, x7, fail - lw x5,72(sp) - bne x5, x8, fail - lw x5,68(sp) - bne x5, x9, fail - lw x5,64(sp) - bne x5, x10, fail - lw x5,60(sp) - bne x5, x11, fail - lw x5,56(sp) - bne x5, x12, fail - lw x5,52(sp) - bne x5, x13, fail - lw x5,48(sp) - bne x5, x14, fail - lw x5,44(sp) - bne x5, x15, fail - lw x5,40(sp) - bne x5, x16, fail - lw x5,36(sp) - bne x5, x17, fail - lw x5,32(sp) - bne x5, x18, fail - lw x5,28(sp) - bne x5, x19, fail - lw x5,24(sp) - bne x5, x20, fail - lw x5,20(sp) - bne x5, x21, fail - lw x5,16(sp) - bne x5, x22, fail - lw x5,12(sp) - bne x5, x23, fail - lw x5,8(sp) - bne x5, x24, fail - lw x5,4(sp) - bne x5, x25, fail - addi sp,sp,84 - li x18, TEST_PASS - li x16, EXPECTED_ILLEGAL_INSTRUCTIONS - beq x31, x16, test_end -csr_fail: -fail: - li x18, TEST_FAIL -test_end: - li x17, VIRT_PERIPH_STATUS_FLAG_ADDR - sw x18,0(x17) - j _exit - -# The "sw_irq_handler" is entered on each illegal instruction. Clears -# mepc and increments the illegal instruction count in x31. -u_sw_irq_handler: - li x30, 0xf - csrrc x29, mcause, x0 - and x30, x29, x30 - li x28, 2 - bne x30, x28, _exit - csrrc x27, mepc, x0 - c.addi x27, 4 - csrrw x0, mepc, x27 - c.addi x31, 1 - mret - -_exit: - j _exit - -debug: - j _exit diff --git a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_1/test.yaml b/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_1/test.yaml deleted file mode 100644 index 8263bbc669..0000000000 --- a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_1/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: mhpmcounter29_csr_access_test_1 -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR access test with NUM_MHPMCOUNTER = 29 (FIXME ISS does not set correct reset value for mcountinhibit) diff --git a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S b/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S deleted file mode 100644 index f621a53538..0000000000 --- a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S +++ /dev/null @@ -1,5701 +0,0 @@ -# -# Copyright (C) EM Microelectronic US Inc. -# Copyright (C) 2020 OpenHW Group -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. -# -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 -# -############################################################################### -# MHPMCOUNTERS29: access testcase for mhpmcounter3..31 CSRs in cv32e40s. -# Notes: -# 1. This test requires NUM_MHPMCOUNTERS set to 29. -# 2. Does not test function - just access. -# 3. FIXME: ISS currently does not set mcountinhibit correctly on reset -# for non-default number of registers, RVVI and RVFI will mismatch if -# sb checking is enabled. -############################################################################### -#include "corev_uvmt.h" - -.include "user_define.h" -.section .text.start -.globl _start -.section .text -#.include "user_init.s" -.type _start, @function - -_start: - j _start_main - -.globl _start_main -.section .text -_start_main: - - #define EXP_MISA 0x40001104 - - -############################################################################### -# Script generated code to verify write/read access of these CSRs. -#start - # mhpmevent3 - li x12, 0xa5a5a5a5 - csrrw x14, 803, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 803, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x5599ca67 - csrrw x14, 803, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 803, x12 - li x12, 0x0000ca67 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 803, x12 - li x12, 0x0000efe7 - bne x12, x14, csr_fail - li x12, 0x943b6954 - csrrs x14, 803, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 803, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 803, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x7c4c5d22 - csrrc x14, 803, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 803, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 803, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 803, 0b01010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 803, 0b00101 - li x12, 0x0000000a - bne x12, x14, csr_fail - csrrsi x14, 803, 0b11010 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 803, 0b11100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 803, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 803, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 803, 0b10110 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent4 - li x12, 0xa5a5a5a5 - csrrw x14, 804, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 804, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x192b5afa - csrrw x14, 804, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 804, x12 - li x12, 0x00005afa - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 804, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x86015c6d - csrrs x14, 804, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 804, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 804, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x029db46e - csrrc x14, 804, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 804, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 804, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 804, 0b10111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 804, 0b00101 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 804, 0b11010 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 804, 0b11000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 804, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 804, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 804, 0b10111 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent5 - li x12, 0xa5a5a5a5 - csrrw x14, 805, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 805, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xe3ab797d - csrrw x14, 805, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 805, x12 - li x12, 0x0000797d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 805, x12 - li x12, 0x0000fdfd - bne x12, x14, csr_fail - li x12, 0x3d002294 - csrrs x14, 805, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 805, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 805, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x1e882616 - csrrc x14, 805, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 805, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 805, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 805, 0b00001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 805, 0b00101 - li x12, 0x00000001 - bne x12, x14, csr_fail - csrrsi x14, 805, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 805, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 805, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 805, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 805, 0b01001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent6 - li x12, 0xa5a5a5a5 - csrrw x14, 806, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 806, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xbbaff885 - csrrw x14, 806, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 806, x12 - li x12, 0x0000f885 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 806, x12 - li x12, 0x0000fda5 - bne x12, x14, csr_fail - li x12, 0x3c6f2d52 - csrrs x14, 806, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 806, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 806, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x809d900c - csrrc x14, 806, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 806, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 806, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 806, 0b11001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 806, 0b00101 - li x12, 0x00000019 - bne x12, x14, csr_fail - csrrsi x14, 806, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 806, 0b11001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 806, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 806, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 806, 0b11101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent7 - li x12, 0xa5a5a5a5 - csrrw x14, 807, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 807, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xf550d5ab - csrrw x14, 807, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 807, x12 - li x12, 0x0000d5ab - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 807, x12 - li x12, 0x0000f5af - bne x12, x14, csr_fail - li x12, 0xe62f0e49 - csrrs x14, 807, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 807, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 807, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x5f55ce76 - csrrc x14, 807, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 807, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 807, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 807, 0b00100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 807, 0b00101 - li x12, 0x00000004 - bne x12, x14, csr_fail - csrrsi x14, 807, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 807, 0b11001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 807, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 807, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 807, 0b11100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent8 - li x12, 0xa5a5a5a5 - csrrw x14, 808, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 808, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x36cd731a - csrrw x14, 808, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 808, x12 - li x12, 0x0000731a - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 808, x12 - li x12, 0x0000f7bf - bne x12, x14, csr_fail - li x12, 0x578155b4 - csrrs x14, 808, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 808, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 808, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x21794a9c - csrrc x14, 808, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 808, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 808, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 808, 0b11011 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 808, 0b00101 - li x12, 0x0000001b - bne x12, x14, csr_fail - csrrsi x14, 808, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 808, 0b10000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 808, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 808, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 808, 0b11011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent9 - li x12, 0xa5a5a5a5 - csrrw x14, 809, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 809, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x4df46846 - csrrw x14, 809, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 809, x12 - li x12, 0x00006846 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 809, x12 - li x12, 0x0000ede7 - bne x12, x14, csr_fail - li x12, 0x46e6d02b - csrrs x14, 809, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 809, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 809, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xb07c4e41 - csrrc x14, 809, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 809, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 809, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 809, 0b00100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 809, 0b00101 - li x12, 0x00000004 - bne x12, x14, csr_fail - csrrsi x14, 809, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 809, 0b00011 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 809, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 809, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 809, 0b00100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent10 - li x12, 0xa5a5a5a5 - csrrw x14, 810, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 810, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x249666b3 - csrrw x14, 810, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 810, x12 - li x12, 0x000066b3 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 810, x12 - li x12, 0x0000e7b7 - bne x12, x14, csr_fail - li x12, 0x5a36a091 - csrrs x14, 810, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 810, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 810, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xf26df110 - csrrc x14, 810, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 810, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 810, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 810, 0b11001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 810, 0b00101 - li x12, 0x00000019 - bne x12, x14, csr_fail - csrrsi x14, 810, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 810, 0b01100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 810, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 810, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 810, 0b10011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent11 - li x12, 0xa5a5a5a5 - csrrw x14, 811, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 811, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xaf9407ee - csrrw x14, 811, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 811, x12 - li x12, 0x000007ee - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 811, x12 - li x12, 0x0000a7ef - bne x12, x14, csr_fail - li x12, 0x9c1024e8 - csrrs x14, 811, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 811, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 811, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x823a6c57 - csrrc x14, 811, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 811, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 811, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 811, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 811, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 811, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 811, 0b10100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 811, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 811, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 811, 0b11010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent12 - li x12, 0xa5a5a5a5 - csrrw x14, 812, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 812, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xb3cd262d - csrrw x14, 812, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 812, x12 - li x12, 0x0000262d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 812, x12 - li x12, 0x0000a7ad - bne x12, x14, csr_fail - li x12, 0xd44e7e03 - csrrs x14, 812, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 812, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 812, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xfe9717de - csrrc x14, 812, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 812, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 812, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 812, 0b10111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 812, 0b00101 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 812, 0b11010 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 812, 0b01101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 812, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 812, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 812, 0b11011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent13 - li x12, 0xa5a5a5a5 - csrrw x14, 813, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 813, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xeb86004c - csrrw x14, 813, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 813, x12 - li x12, 0x0000004c - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 813, x12 - li x12, 0x0000a5ed - bne x12, x14, csr_fail - li x12, 0x8f03af04 - csrrs x14, 813, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 813, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 813, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xd665472c - csrrc x14, 813, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 813, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 813, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 813, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 813, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 813, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 813, 0b00000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 813, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 813, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 813, 0b00000 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent14 - li x12, 0xa5a5a5a5 - csrrw x14, 814, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 814, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xc25aaf9d - csrrw x14, 814, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 814, x12 - li x12, 0x0000af9d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 814, x12 - li x12, 0x0000afbd - bne x12, x14, csr_fail - li x12, 0x6232f2cf - csrrs x14, 814, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 814, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 814, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xab4c8b27 - csrrc x14, 814, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 814, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 814, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 814, 0b00111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 814, 0b00101 - li x12, 0x00000007 - bne x12, x14, csr_fail - csrrsi x14, 814, 0b11010 - li x12, 0x00000007 - bne x12, x14, csr_fail - csrrsi x14, 814, 0b10001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 814, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 814, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 814, 0b00100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent15 - li x12, 0xa5a5a5a5 - csrrw x14, 815, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 815, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xfc450eb6 - csrrw x14, 815, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 815, x12 - li x12, 0x00000eb6 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 815, x12 - li x12, 0x0000afb7 - bne x12, x14, csr_fail - li x12, 0xdf21d66b - csrrs x14, 815, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 815, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 815, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x5d877b70 - csrrc x14, 815, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 815, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 815, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 815, 0b01111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 815, 0b00101 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 815, 0b11010 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 815, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 815, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 815, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 815, 0b01001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent16 - li x12, 0xa5a5a5a5 - csrrw x14, 816, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 816, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x60c43ac1 - csrrw x14, 816, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 816, x12 - li x12, 0x00003ac1 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 816, x12 - li x12, 0x0000bfe5 - bne x12, x14, csr_fail - li x12, 0xa353dd27 - csrrs x14, 816, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 816, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 816, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x25d46c45 - csrrc x14, 816, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 816, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 816, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 816, 0b01010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 816, 0b00101 - li x12, 0x0000000a - bne x12, x14, csr_fail - csrrsi x14, 816, 0b11010 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 816, 0b00010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 816, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 816, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 816, 0b00010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent17 - li x12, 0xa5a5a5a5 - csrrw x14, 817, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 817, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x6d77c506 - csrrw x14, 817, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 817, x12 - li x12, 0x0000c506 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 817, x12 - li x12, 0x0000e5a7 - bne x12, x14, csr_fail - li x12, 0x615f4a97 - csrrs x14, 817, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 817, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 817, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xaba4a7c0 - csrrc x14, 817, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 817, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 817, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 817, 0b11101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 817, 0b00101 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 817, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 817, 0b10110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 817, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 817, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 817, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent18 - li x12, 0xa5a5a5a5 - csrrw x14, 818, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 818, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xa006a626 - csrrw x14, 818, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 818, x12 - li x12, 0x0000a626 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 818, x12 - li x12, 0x0000a7a7 - bne x12, x14, csr_fail - li x12, 0x4a2ebbef - csrrs x14, 818, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 818, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 818, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa4d3b6b3 - csrrc x14, 818, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 818, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 818, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 818, 0b00100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 818, 0b00101 - li x12, 0x00000004 - bne x12, x14, csr_fail - csrrsi x14, 818, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 818, 0b01011 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 818, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 818, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 818, 0b00010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent19 - li x12, 0xa5a5a5a5 - csrrw x14, 819, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 819, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x2db1490a - csrrw x14, 819, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 819, x12 - li x12, 0x0000490a - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 819, x12 - li x12, 0x0000edaf - bne x12, x14, csr_fail - li x12, 0x48747d08 - csrrs x14, 819, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 819, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 819, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa0f18bd1 - csrrc x14, 819, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 819, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 819, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 819, 0b11111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 819, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 819, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 819, 0b11110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 819, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 819, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 819, 0b00011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent20 - li x12, 0xa5a5a5a5 - csrrw x14, 820, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 820, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xd9df844d - csrrw x14, 820, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 820, x12 - li x12, 0x0000844d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 820, x12 - li x12, 0x0000a5ed - bne x12, x14, csr_fail - li x12, 0xde339ea9 - csrrs x14, 820, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 820, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 820, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa6382e89 - csrrc x14, 820, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 820, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 820, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 820, 0b01101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 820, 0b00101 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 820, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 820, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 820, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 820, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 820, 0b01001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent21 - li x12, 0xa5a5a5a5 - csrrw x14, 821, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 821, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x8a23cad8 - csrrw x14, 821, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 821, x12 - li x12, 0x0000cad8 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 821, x12 - li x12, 0x0000effd - bne x12, x14, csr_fail - li x12, 0xe23ee27b - csrrs x14, 821, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 821, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 821, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xce9f2bb9 - csrrc x14, 821, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 821, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 821, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 821, 0b11101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 821, 0b00101 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 821, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 821, 0b01000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 821, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 821, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 821, 0b11000 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent22 - li x12, 0xa5a5a5a5 - csrrw x14, 822, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 822, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x7942fd02 - csrrw x14, 822, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 822, x12 - li x12, 0x0000fd02 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 822, x12 - li x12, 0x0000fda7 - bne x12, x14, csr_fail - li x12, 0x67a9e836 - csrrs x14, 822, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 822, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 822, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xbd53627f - csrrc x14, 822, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 822, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 822, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 822, 0b00101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 822, 0b00101 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 822, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 822, 0b01010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 822, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 822, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 822, 0b10011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent23 - li x12, 0xa5a5a5a5 - csrrw x14, 823, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 823, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x297f98b8 - csrrw x14, 823, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 823, x12 - li x12, 0x000098b8 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 823, x12 - li x12, 0x0000bdbd - bne x12, x14, csr_fail - li x12, 0x122088b3 - csrrs x14, 823, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 823, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 823, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x848ec6e4 - csrrc x14, 823, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 823, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 823, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 823, 0b00110 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 823, 0b00101 - li x12, 0x00000006 - bne x12, x14, csr_fail - csrrsi x14, 823, 0b11010 - li x12, 0x00000007 - bne x12, x14, csr_fail - csrrsi x14, 823, 0b01111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 823, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 823, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 823, 0b10011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent24 - li x12, 0xa5a5a5a5 - csrrw x14, 824, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 824, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xf48c6acd - csrrw x14, 824, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 824, x12 - li x12, 0x00006acd - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 824, x12 - li x12, 0x0000efed - bne x12, x14, csr_fail - li x12, 0x32d05494 - csrrs x14, 824, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 824, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 824, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xbc98c71d - csrrc x14, 824, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 824, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 824, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 824, 0b10111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 824, 0b00101 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 824, 0b11010 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 824, 0b00110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 824, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 824, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 824, 0b00100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent25 - li x12, 0xa5a5a5a5 - csrrw x14, 825, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 825, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x5f668177 - csrrw x14, 825, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 825, x12 - li x12, 0x00008177 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 825, x12 - li x12, 0x0000a5f7 - bne x12, x14, csr_fail - li x12, 0x73970670 - csrrs x14, 825, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 825, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 825, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa1adae60 - csrrc x14, 825, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 825, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 825, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 825, 0b01001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 825, 0b00101 - li x12, 0x00000009 - bne x12, x14, csr_fail - csrrsi x14, 825, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 825, 0b01001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 825, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 825, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 825, 0b10101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent26 - li x12, 0xa5a5a5a5 - csrrw x14, 826, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 826, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xd6668cc8 - csrrw x14, 826, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 826, x12 - li x12, 0x00008cc8 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 826, x12 - li x12, 0x0000aded - bne x12, x14, csr_fail - li x12, 0xbd9ed990 - csrrs x14, 826, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 826, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 826, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xcedecfcd - csrrc x14, 826, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 826, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 826, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 826, 0b11100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 826, 0b00101 - li x12, 0x0000001c - bne x12, x14, csr_fail - csrrsi x14, 826, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 826, 0b11100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 826, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 826, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 826, 0b10001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent27 - li x12, 0xa5a5a5a5 - csrrw x14, 827, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 827, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xa425e498 - csrrw x14, 827, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 827, x12 - li x12, 0x0000e498 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 827, x12 - li x12, 0x0000e5bd - bne x12, x14, csr_fail - li x12, 0x3556abe1 - csrrs x14, 827, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 827, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 827, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xbf4d3dd4 - csrrc x14, 827, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 827, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 827, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 827, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 827, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 827, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 827, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 827, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 827, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 827, 0b10111 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent28 - li x12, 0xa5a5a5a5 - csrrw x14, 828, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 828, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x356e8358 - csrrw x14, 828, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 828, x12 - li x12, 0x00008358 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 828, x12 - li x12, 0x0000a7fd - bne x12, x14, csr_fail - li x12, 0x60d5d1c4 - csrrs x14, 828, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 828, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 828, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x3f6d5395 - csrrc x14, 828, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 828, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 828, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 828, 0b00101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 828, 0b00101 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 828, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 828, 0b01110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 828, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 828, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 828, 0b11101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent29 - li x12, 0xa5a5a5a5 - csrrw x14, 829, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 829, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x5f596028 - csrrw x14, 829, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 829, x12 - li x12, 0x00006028 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 829, x12 - li x12, 0x0000e5ad - bne x12, x14, csr_fail - li x12, 0x61430933 - csrrs x14, 829, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 829, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 829, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x6717a138 - csrrc x14, 829, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 829, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 829, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 829, 0b01100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 829, 0b00101 - li x12, 0x0000000c - bne x12, x14, csr_fail - csrrsi x14, 829, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 829, 0b11100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 829, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 829, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 829, 0b11110 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent30 - li x12, 0xa5a5a5a5 - csrrw x14, 830, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 830, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x28c0c58e - csrrw x14, 830, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 830, x12 - li x12, 0x0000c58e - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 830, x12 - li x12, 0x0000e5af - bne x12, x14, csr_fail - li x12, 0x32370e52 - csrrs x14, 830, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 830, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 830, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x8d540cb7 - csrrc x14, 830, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 830, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 830, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 830, 0b11111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 830, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 830, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 830, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 830, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 830, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 830, 0b00010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent31 - li x12, 0xa5a5a5a5 - csrrw x14, 831, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 831, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xfb37c936 - csrrw x14, 831, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 831, x12 - li x12, 0x0000c936 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 831, x12 - li x12, 0x0000edb7 - bne x12, x14, csr_fail - li x12, 0x8e300970 - csrrs x14, 831, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 831, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 831, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x6056a394 - csrrc x14, 831, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 831, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 831, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 831, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 831, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 831, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 831, 0b11111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 831, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 831, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 831, 0b00000 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrr x14, 831 - li x12, 0x00000000 - bne x12, x14, csr_fail -############################################################################### - # mhpmcounter3 - li x13, 0xa5a5a5a5 - csrrw x11, 2819, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2819, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x58d817e6 - csrrw x11, 2819, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2819, x13 - li x13, 0x58d817e6 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2819, x13 - li x13, 0xfdfdb7e7 - bne x13, x11, csr_fail - li x13, 0x11b4174c - csrrs x11, 2819, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2819, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2819, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x60f899eb - csrrc x11, 2819, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2819, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2819, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2819, 0b01110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2819, 0b00101 - li x13, 0x0000000e - bne x13, x11, csr_fail - csrrsi x11, 2819, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2819, 0b10011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2819, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2819, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2819, 0b10101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter4 - li x13, 0xa5a5a5a5 - csrrw x11, 2820, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2820, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xd62407a2 - csrrw x11, 2820, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2820, x13 - li x13, 0xd62407a2 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2820, x13 - li x13, 0xf7a5a7a7 - bne x13, x11, csr_fail - li x13, 0xaf7d9050 - csrrs x11, 2820, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2820, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2820, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xab8b9bbc - csrrc x11, 2820, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2820, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2820, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2820, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2820, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2820, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2820, 0b01101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2820, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2820, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2820, 0b01111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter5 - li x13, 0xa5a5a5a5 - csrrw x11, 2821, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2821, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x233a825d - csrrw x11, 2821, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2821, x13 - li x13, 0x233a825d - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2821, x13 - li x13, 0xa7bfa7fd - bne x13, x11, csr_fail - li x13, 0x7e568133 - csrrs x11, 2821, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2821, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2821, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x6edf1ab9 - csrrc x11, 2821, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2821, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2821, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2821, 0b11000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2821, 0b00101 - li x13, 0x00000018 - bne x13, x11, csr_fail - csrrsi x11, 2821, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2821, 0b01001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2821, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2821, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2821, 0b10110 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter6 - li x13, 0xa5a5a5a5 - csrrw x11, 2822, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2822, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xc7a32aad - csrrw x11, 2822, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2822, x13 - li x13, 0xc7a32aad - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2822, x13 - li x13, 0xe7a7afad - bne x13, x11, csr_fail - li x13, 0x9ace7026 - csrrs x11, 2822, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2822, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2822, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xc92bf27a - csrrc x11, 2822, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2822, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2822, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2822, 0b01010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2822, 0b00101 - li x13, 0x0000000a - bne x13, x11, csr_fail - csrrsi x11, 2822, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2822, 0b11011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2822, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2822, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2822, 0b11011 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter7 - li x13, 0xa5a5a5a5 - csrrw x11, 2823, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2823, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x184a572d - csrrw x11, 2823, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2823, x13 - li x13, 0x184a572d - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2823, x13 - li x13, 0xbdeff7ad - bne x13, x11, csr_fail - li x13, 0x85cfd036 - csrrs x11, 2823, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2823, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2823, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x86ac69a6 - csrrc x11, 2823, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2823, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2823, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2823, 0b10011 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2823, 0b00101 - li x13, 0x00000013 - bne x13, x11, csr_fail - csrrsi x11, 2823, 0b11010 - li x13, 0x00000017 - bne x13, x11, csr_fail - csrrsi x11, 2823, 0b10010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2823, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2823, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2823, 0b01111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter8 - li x13, 0xa5a5a5a5 - csrrw x11, 2824, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2824, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x9355a775 - csrrw x11, 2824, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2824, x13 - li x13, 0x9355a775 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2824, x13 - li x13, 0xb7f5a7f5 - bne x13, x11, csr_fail - li x13, 0x9f6de57c - csrrs x11, 2824, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2824, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2824, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x85ec8fd2 - csrrc x11, 2824, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2824, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2824, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2824, 0b01010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2824, 0b00101 - li x13, 0x0000000a - bne x13, x11, csr_fail - csrrsi x11, 2824, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2824, 0b11000 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2824, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2824, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2824, 0b01000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter9 - li x13, 0xa5a5a5a5 - csrrw x11, 2825, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2825, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xb4a0230e - csrrw x11, 2825, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2825, x13 - li x13, 0xb4a0230e - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2825, x13 - li x13, 0xb5a5a7af - bne x13, x11, csr_fail - li x13, 0x882e6ec1 - csrrs x11, 2825, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2825, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2825, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xb5886b83 - csrrc x11, 2825, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2825, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2825, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2825, 0b11101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2825, 0b00101 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2825, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2825, 0b11110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2825, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2825, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2825, 0b11000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter10 - li x13, 0xa5a5a5a5 - csrrw x11, 2826, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2826, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xeb5456ff - csrrw x11, 2826, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2826, x13 - li x13, 0xeb5456ff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2826, x13 - li x13, 0xeff5f7ff - bne x13, x11, csr_fail - li x13, 0xbd1f6642 - csrrs x11, 2826, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2826, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2826, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xfa6e3d89 - csrrc x11, 2826, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2826, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2826, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2826, 0b01110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2826, 0b00101 - li x13, 0x0000000e - bne x13, x11, csr_fail - csrrsi x11, 2826, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2826, 0b00110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2826, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2826, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2826, 0b11010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter11 - li x13, 0xa5a5a5a5 - csrrw x11, 2827, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2827, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xf07058c6 - csrrw x11, 2827, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2827, x13 - li x13, 0xf07058c6 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2827, x13 - li x13, 0xf5f5fde7 - bne x13, x11, csr_fail - li x13, 0x35e3d846 - csrrs x11, 2827, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2827, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2827, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x8a77a20e - csrrc x11, 2827, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2827, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2827, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2827, 0b00001 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2827, 0b00101 - li x13, 0x00000001 - bne x13, x11, csr_fail - csrrsi x11, 2827, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2827, 0b10110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2827, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2827, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2827, 0b11101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter12 - li x13, 0xa5a5a5a5 - csrrw x11, 2828, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2828, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xdbbe17ed - csrrw x11, 2828, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2828, x13 - li x13, 0xdbbe17ed - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2828, x13 - li x13, 0xffbfb7ed - bne x13, x11, csr_fail - li x13, 0x6c87baac - csrrs x11, 2828, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2828, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2828, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x8b90c327 - csrrc x11, 2828, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2828, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2828, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2828, 0b01111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2828, 0b00101 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2828, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2828, 0b10100 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2828, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2828, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2828, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter13 - li x13, 0xa5a5a5a5 - csrrw x11, 2829, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2829, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x6e69c984 - csrrw x11, 2829, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2829, x13 - li x13, 0x6e69c984 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2829, x13 - li x13, 0xefededa5 - bne x13, x11, csr_fail - li x13, 0x9285cadb - csrrs x11, 2829, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2829, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2829, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x51afbfef - csrrc x11, 2829, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2829, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2829, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2829, 0b00101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2829, 0b00101 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2829, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2829, 0b01010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2829, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2829, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2829, 0b11111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter14 - li x13, 0xa5a5a5a5 - csrrw x11, 2830, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2830, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xe045db3e - csrrw x11, 2830, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2830, x13 - li x13, 0xe045db3e - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2830, x13 - li x13, 0xe5e5ffbf - bne x13, x11, csr_fail - li x13, 0xf14d1b59 - csrrs x11, 2830, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2830, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2830, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x44a8f6a6 - csrrc x11, 2830, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2830, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2830, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2830, 0b10010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2830, 0b00101 - li x13, 0x00000012 - bne x13, x11, csr_fail - csrrsi x11, 2830, 0b11010 - li x13, 0x00000017 - bne x13, x11, csr_fail - csrrsi x11, 2830, 0b01001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2830, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2830, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2830, 0b01001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter15 - li x13, 0xa5a5a5a5 - csrrw x11, 2831, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2831, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xb6a578fb - csrrw x11, 2831, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2831, x13 - li x13, 0xb6a578fb - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2831, x13 - li x13, 0xb7a5fdff - bne x13, x11, csr_fail - li x13, 0xc8c54afb - csrrs x11, 2831, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2831, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2831, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x7198a93f - csrrc x11, 2831, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2831, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2831, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2831, 0b11100 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2831, 0b00101 - li x13, 0x0000001c - bne x13, x11, csr_fail - csrrsi x11, 2831, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2831, 0b00011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2831, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2831, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2831, 0b01101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter16 - li x13, 0xa5a5a5a5 - csrrw x11, 2832, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2832, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xf55fd3fa - csrrw x11, 2832, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2832, x13 - li x13, 0xf55fd3fa - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2832, x13 - li x13, 0xf5fff7ff - bne x13, x11, csr_fail - li x13, 0xe2b12d78 - csrrs x11, 2832, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2832, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2832, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x7cb08e77 - csrrc x11, 2832, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2832, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2832, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2832, 0b01111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2832, 0b00101 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2832, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2832, 0b11111 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2832, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2832, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2832, 0b01000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter17 - li x13, 0xa5a5a5a5 - csrrw x11, 2833, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2833, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x0c51d700 - csrrw x11, 2833, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2833, x13 - li x13, 0x0c51d700 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2833, x13 - li x13, 0xadf5f7a5 - bne x13, x11, csr_fail - li x13, 0x812bd85e - csrrs x11, 2833, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2833, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2833, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xbc1cacdf - csrrc x11, 2833, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2833, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2833, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2833, 0b11110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2833, 0b00101 - li x13, 0x0000001e - bne x13, x11, csr_fail - csrrsi x11, 2833, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2833, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2833, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2833, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2833, 0b10010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter18 - li x13, 0xa5a5a5a5 - csrrw x11, 2834, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2834, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x27f2b3f5 - csrrw x11, 2834, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2834, x13 - li x13, 0x27f2b3f5 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2834, x13 - li x13, 0xa7f7b7f5 - bne x13, x11, csr_fail - li x13, 0x50daa8a6 - csrrs x11, 2834, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2834, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2834, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xaed090af - csrrc x11, 2834, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2834, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2834, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2834, 0b10101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2834, 0b00101 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2834, 0b11010 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2834, 0b00001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2834, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2834, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2834, 0b11010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter19 - li x13, 0xa5a5a5a5 - csrrw x11, 2835, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2835, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xbb9f11de - csrrw x11, 2835, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2835, x13 - li x13, 0xbb9f11de - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2835, x13 - li x13, 0xbfbfb5ff - bne x13, x11, csr_fail - li x13, 0xb8b44a62 - csrrs x11, 2835, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2835, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2835, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x8cfc8f2d - csrrc x11, 2835, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2835, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2835, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2835, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2835, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2835, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2835, 0b01001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2835, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2835, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2835, 0b00000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter20 - li x13, 0xa5a5a5a5 - csrrw x11, 2836, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2836, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x481e52b3 - csrrw x11, 2836, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2836, x13 - li x13, 0x481e52b3 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2836, x13 - li x13, 0xedbff7b7 - bne x13, x11, csr_fail - li x13, 0x6a7ac135 - csrrs x11, 2836, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2836, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2836, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x27c10d05 - csrrc x11, 2836, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2836, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2836, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2836, 0b00110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2836, 0b00101 - li x13, 0x00000006 - bne x13, x11, csr_fail - csrrsi x11, 2836, 0b11010 - li x13, 0x00000007 - bne x13, x11, csr_fail - csrrsi x11, 2836, 0b00110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2836, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2836, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2836, 0b10111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter21 - li x13, 0xa5a5a5a5 - csrrw x11, 2837, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2837, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x7429cf49 - csrrw x11, 2837, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2837, x13 - li x13, 0x7429cf49 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2837, x13 - li x13, 0xf5adefed - bne x13, x11, csr_fail - li x13, 0x9d4886ce - csrrs x11, 2837, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2837, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2837, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x05ddcfef - csrrc x11, 2837, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2837, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2837, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2837, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2837, 0b00101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2837, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2837, 0b00000 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2837, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2837, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2837, 0b00010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter22 - li x13, 0xa5a5a5a5 - csrrw x11, 2838, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2838, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x9d16666a - csrrw x11, 2838, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2838, x13 - li x13, 0x9d16666a - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2838, x13 - li x13, 0xbdb7e7ef - bne x13, x11, csr_fail - li x13, 0x142246a0 - csrrs x11, 2838, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2838, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2838, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x61cde58d - csrrc x11, 2838, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2838, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2838, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2838, 0b00101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2838, 0b00101 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2838, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2838, 0b11100 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2838, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2838, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2838, 0b11110 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter23 - li x13, 0xa5a5a5a5 - csrrw x11, 2839, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2839, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xc7a95284 - csrrw x11, 2839, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2839, x13 - li x13, 0xc7a95284 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2839, x13 - li x13, 0xe7adf7a5 - bne x13, x11, csr_fail - li x13, 0xa7e4b1fe - csrrs x11, 2839, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2839, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2839, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xca65a5e3 - csrrc x11, 2839, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2839, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2839, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2839, 0b11000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2839, 0b00101 - li x13, 0x00000018 - bne x13, x11, csr_fail - csrrsi x11, 2839, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2839, 0b10111 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2839, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2839, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2839, 0b01011 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter24 - li x13, 0xa5a5a5a5 - csrrw x11, 2840, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2840, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x448a9e22 - csrrw x11, 2840, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2840, x13 - li x13, 0x448a9e22 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2840, x13 - li x13, 0xe5afbfa7 - bne x13, x11, csr_fail - li x13, 0xf4d3cb7f - csrrs x11, 2840, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2840, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2840, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x24425424 - csrrc x11, 2840, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2840, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2840, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2840, 0b00010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2840, 0b00101 - li x13, 0x00000002 - bne x13, x11, csr_fail - csrrsi x11, 2840, 0b11010 - li x13, 0x00000007 - bne x13, x11, csr_fail - csrrsi x11, 2840, 0b11110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2840, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2840, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2840, 0b00001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter25 - li x13, 0xa5a5a5a5 - csrrw x11, 2841, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2841, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x9c79f6e9 - csrrw x11, 2841, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2841, x13 - li x13, 0x9c79f6e9 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2841, x13 - li x13, 0xbdfdf7ed - bne x13, x11, csr_fail - li x13, 0xd9dd54c2 - csrrs x11, 2841, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2841, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2841, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x2711d141 - csrrc x11, 2841, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2841, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2841, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2841, 0b00011 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2841, 0b00101 - li x13, 0x00000003 - bne x13, x11, csr_fail - csrrsi x11, 2841, 0b11010 - li x13, 0x00000007 - bne x13, x11, csr_fail - csrrsi x11, 2841, 0b01100 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2841, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2841, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2841, 0b11101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter26 - li x13, 0xa5a5a5a5 - csrrw x11, 2842, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2842, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x5443f6a3 - csrrw x11, 2842, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2842, x13 - li x13, 0x5443f6a3 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2842, x13 - li x13, 0xf5e7f7a7 - bne x13, x11, csr_fail - li x13, 0x4a3510d1 - csrrs x11, 2842, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2842, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2842, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x5a4d1518 - csrrc x11, 2842, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2842, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2842, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2842, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2842, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2842, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2842, 0b11110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2842, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2842, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2842, 0b11011 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter27 - li x13, 0xa5a5a5a5 - csrrw x11, 2843, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2843, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x64d8b2de - csrrw x11, 2843, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2843, x13 - li x13, 0x64d8b2de - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2843, x13 - li x13, 0xe5fdb7ff - bne x13, x11, csr_fail - li x13, 0x9ca8e026 - csrrs x11, 2843, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2843, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2843, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xeee2ae60 - csrrc x11, 2843, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2843, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2843, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2843, 0b10000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2843, 0b00101 - li x13, 0x00000010 - bne x13, x11, csr_fail - csrrsi x11, 2843, 0b11010 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2843, 0b01101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2843, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2843, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2843, 0b11111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter28 - li x13, 0xa5a5a5a5 - csrrw x11, 2844, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2844, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x2e03ed20 - csrrw x11, 2844, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2844, x13 - li x13, 0x2e03ed20 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2844, x13 - li x13, 0xafa7eda5 - bne x13, x11, csr_fail - li x13, 0x5fe9e959 - csrrs x11, 2844, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2844, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2844, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xf91e6877 - csrrc x11, 2844, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2844, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2844, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2844, 0b01000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2844, 0b00101 - li x13, 0x00000008 - bne x13, x11, csr_fail - csrrsi x11, 2844, 0b11010 - li x13, 0x0000000d - bne x13, x11, csr_fail - csrrsi x11, 2844, 0b10000 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2844, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2844, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2844, 0b01001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter29 - li x13, 0xa5a5a5a5 - csrrw x11, 2845, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2845, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x499c9ef2 - csrrw x11, 2845, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2845, x13 - li x13, 0x499c9ef2 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2845, x13 - li x13, 0xedbdbff7 - bne x13, x11, csr_fail - li x13, 0xb43b0f6f - csrrs x11, 2845, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2845, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2845, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xe1c1be2d - csrrc x11, 2845, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2845, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2845, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2845, 0b11110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2845, 0b00101 - li x13, 0x0000001e - bne x13, x11, csr_fail - csrrsi x11, 2845, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2845, 0b01110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2845, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2845, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2845, 0b11010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter30 - li x13, 0xa5a5a5a5 - csrrw x11, 2846, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2846, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x7427b2d4 - csrrw x11, 2846, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2846, x13 - li x13, 0x7427b2d4 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2846, x13 - li x13, 0xf5a7b7f5 - bne x13, x11, csr_fail - li x13, 0xf6a36392 - csrrs x11, 2846, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2846, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2846, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xe0384721 - csrrc x11, 2846, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2846, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2846, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2846, 0b10101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2846, 0b00101 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2846, 0b11010 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2846, 0b10010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2846, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2846, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2846, 0b10001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter31 - li x13, 0xa5a5a5a5 - csrrw x11, 2847, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2847, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x99220c48 - csrrw x11, 2847, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2847, x13 - li x13, 0x99220c48 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2847, x13 - li x13, 0xbda7aded - bne x13, x11, csr_fail - li x13, 0x8ae5417c - csrrs x11, 2847, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2847, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2847, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xfd516423 - csrrc x11, 2847, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2847, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2847, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2847, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2847, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2847, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2847, 0b01011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2847, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2847, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2847, 0b10101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrr x11, 2847 - li x13, 0x00000000 - bne x13, x11, csr_fail -############################################################################### - # mhpmcounterh3 - li x5, 0xa5a5a5a5 - csrrw x15, 2947, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2947, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x3eb0a869 - csrrw x15, 2947, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2947, x5 - li x5, 0x3eb0a869 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2947, x5 - li x5, 0xbfb5aded - bne x5, x15, csr_fail - li x5, 0x080bee67 - csrrs x15, 2947, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2947, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2947, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x31462855 - csrrc x15, 2947, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2947, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2947, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2947, 0b00001 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2947, 0b00101 - li x5, 0x00000001 - bne x5, x15, csr_fail - csrrsi x15, 2947, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrsi x15, 2947, 0b11110 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2947, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2947, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2947, 0b00100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh4 - li x5, 0xa5a5a5a5 - csrrw x15, 2948, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2948, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x4c90ee23 - csrrw x15, 2948, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2948, x5 - li x5, 0x4c90ee23 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2948, x5 - li x5, 0xedb5efa7 - bne x5, x15, csr_fail - li x5, 0x502190eb - csrrs x15, 2948, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2948, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2948, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x5b6fc098 - csrrc x15, 2948, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2948, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2948, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2948, 0b00011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2948, 0b00101 - li x5, 0x00000003 - bne x5, x15, csr_fail - csrrsi x15, 2948, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2948, 0b01011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2948, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2948, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2948, 0b01111 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh5 - li x5, 0xa5a5a5a5 - csrrw x15, 2949, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2949, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x359322b3 - csrrw x15, 2949, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2949, x5 - li x5, 0x359322b3 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2949, x5 - li x5, 0xb5b7a7b7 - bne x5, x15, csr_fail - li x5, 0x7f1393f5 - csrrs x15, 2949, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2949, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2949, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x6b55cf35 - csrrc x15, 2949, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2949, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2949, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2949, 0b01001 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2949, 0b00101 - li x5, 0x00000009 - bne x5, x15, csr_fail - csrrsi x15, 2949, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2949, 0b01010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2949, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2949, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2949, 0b11010 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh6 - li x5, 0xa5a5a5a5 - csrrw x15, 2950, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2950, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x677f9bec - csrrw x15, 2950, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2950, x5 - li x5, 0x677f9bec - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2950, x5 - li x5, 0xe7ffbfed - bne x5, x15, csr_fail - li x5, 0x85c1ef2f - csrrs x15, 2950, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2950, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2950, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x37e60d36 - csrrc x15, 2950, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2950, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2950, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2950, 0b11011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2950, 0b00101 - li x5, 0x0000001b - bne x5, x15, csr_fail - csrrsi x15, 2950, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2950, 0b11111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2950, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2950, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2950, 0b10110 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh7 - li x5, 0xa5a5a5a5 - csrrw x15, 2951, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2951, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xf42a7164 - csrrw x15, 2951, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2951, x5 - li x5, 0xf42a7164 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2951, x5 - li x5, 0xf5aff5e5 - bne x5, x15, csr_fail - li x5, 0xd0928679 - csrrs x15, 2951, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2951, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2951, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xad3fa01c - csrrc x15, 2951, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2951, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2951, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2951, 0b01011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2951, 0b00101 - li x5, 0x0000000b - bne x5, x15, csr_fail - csrrsi x15, 2951, 0b11010 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2951, 0b11100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2951, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2951, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2951, 0b11100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh8 - li x5, 0xa5a5a5a5 - csrrw x15, 2952, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2952, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xe64a378d - csrrw x15, 2952, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2952, x5 - li x5, 0xe64a378d - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2952, x5 - li x5, 0xe7efb7ad - bne x5, x15, csr_fail - li x5, 0xd6ebbc1c - csrrs x15, 2952, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2952, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2952, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x663587a9 - csrrc x15, 2952, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2952, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2952, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2952, 0b11100 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2952, 0b00101 - li x5, 0x0000001c - bne x5, x15, csr_fail - csrrsi x15, 2952, 0b11010 - li x5, 0x0000001d - bne x5, x15, csr_fail - csrrsi x15, 2952, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2952, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2952, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2952, 0b01011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh9 - li x5, 0xa5a5a5a5 - csrrw x15, 2953, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2953, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x1bf9e6dd - csrrw x15, 2953, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2953, x5 - li x5, 0x1bf9e6dd - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2953, x5 - li x5, 0xbffde7fd - bne x5, x15, csr_fail - li x5, 0x67d15643 - csrrs x15, 2953, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2953, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2953, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xbc1e804b - csrrc x15, 2953, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2953, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2953, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2953, 0b00110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2953, 0b00101 - li x5, 0x00000006 - bne x5, x15, csr_fail - csrrsi x15, 2953, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2953, 0b10000 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2953, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2953, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2953, 0b01011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh10 - li x5, 0xa5a5a5a5 - csrrw x15, 2954, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2954, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x19bfdb8a - csrrw x15, 2954, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2954, x5 - li x5, 0x19bfdb8a - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2954, x5 - li x5, 0xbdbfffaf - bne x5, x15, csr_fail - li x5, 0x1dc114af - csrrs x15, 2954, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2954, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2954, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x0948d631 - csrrc x15, 2954, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2954, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2954, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2954, 0b01101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2954, 0b00101 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2954, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2954, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2954, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2954, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2954, 0b10100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh11 - li x5, 0xa5a5a5a5 - csrrw x15, 2955, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2955, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x0bea34fa - csrrw x15, 2955, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2955, x5 - li x5, 0x0bea34fa - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2955, x5 - li x5, 0xafefb5ff - bne x5, x15, csr_fail - li x5, 0xa32b5c5b - csrrs x15, 2955, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2955, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2955, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x77b267a0 - csrrc x15, 2955, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2955, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2955, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2955, 0b00110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2955, 0b00101 - li x5, 0x00000006 - bne x5, x15, csr_fail - csrrsi x15, 2955, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2955, 0b01111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2955, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2955, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2955, 0b10001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh12 - li x5, 0xa5a5a5a5 - csrrw x15, 2956, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2956, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x51b87738 - csrrw x15, 2956, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2956, x5 - li x5, 0x51b87738 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2956, x5 - li x5, 0xf5bdf7bd - bne x5, x15, csr_fail - li x5, 0xef71fa43 - csrrs x15, 2956, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2956, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2956, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x6e04d174 - csrrc x15, 2956, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2956, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2956, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2956, 0b10010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2956, 0b00101 - li x5, 0x00000012 - bne x5, x15, csr_fail - csrrsi x15, 2956, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2956, 0b10111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2956, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2956, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2956, 0b10011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh13 - li x5, 0xa5a5a5a5 - csrrw x15, 2957, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2957, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x4906d0a6 - csrrw x15, 2957, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2957, x5 - li x5, 0x4906d0a6 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2957, x5 - li x5, 0xeda7f5a7 - bne x5, x15, csr_fail - li x5, 0xf643ef2d - csrrs x15, 2957, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2957, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2957, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa6be64e9 - csrrc x15, 2957, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2957, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2957, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2957, 0b10101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2957, 0b00101 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2957, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2957, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2957, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2957, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2957, 0b10011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh14 - li x5, 0xa5a5a5a5 - csrrw x15, 2958, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2958, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x7772d54a - csrrw x15, 2958, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2958, x5 - li x5, 0x7772d54a - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2958, x5 - li x5, 0xf7f7f5ef - bne x5, x15, csr_fail - li x5, 0x5e2d84b5 - csrrs x15, 2958, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2958, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2958, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xfd804e78 - csrrc x15, 2958, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2958, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2958, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2958, 0b01000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2958, 0b00101 - li x5, 0x00000008 - bne x5, x15, csr_fail - csrrsi x15, 2958, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2958, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2958, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2958, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2958, 0b01100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh15 - li x5, 0xa5a5a5a5 - csrrw x15, 2959, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2959, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x2d2f3ca0 - csrrw x15, 2959, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2959, x5 - li x5, 0x2d2f3ca0 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2959, x5 - li x5, 0xadafbda5 - bne x5, x15, csr_fail - li x5, 0xed51c6ed - csrrs x15, 2959, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2959, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2959, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x2b93882f - csrrc x15, 2959, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2959, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2959, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2959, 0b11110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2959, 0b00101 - li x5, 0x0000001e - bne x5, x15, csr_fail - csrrsi x15, 2959, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2959, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2959, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2959, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2959, 0b10101 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh16 - li x5, 0xa5a5a5a5 - csrrw x15, 2960, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2960, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x0b99311d - csrrw x15, 2960, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2960, x5 - li x5, 0x0b99311d - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2960, x5 - li x5, 0xafbdb5bd - bne x5, x15, csr_fail - li x5, 0xa20d6c13 - csrrs x15, 2960, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2960, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2960, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x0e4813b8 - csrrc x15, 2960, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2960, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2960, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2960, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2960, 0b00101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2960, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2960, 0b10100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2960, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2960, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2960, 0b10100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh17 - li x5, 0xa5a5a5a5 - csrrw x15, 2961, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2961, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x8c7062a5 - csrrw x15, 2961, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2961, x5 - li x5, 0x8c7062a5 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2961, x5 - li x5, 0xadf5e7a5 - bne x5, x15, csr_fail - li x5, 0x168b744f - csrrs x15, 2961, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2961, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2961, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x679bf535 - csrrc x15, 2961, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2961, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2961, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2961, 0b01010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2961, 0b00101 - li x5, 0x0000000a - bne x5, x15, csr_fail - csrrsi x15, 2961, 0b11010 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2961, 0b11100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2961, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2961, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2961, 0b11100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh18 - li x5, 0xa5a5a5a5 - csrrw x15, 2962, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2962, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x19175bd2 - csrrw x15, 2962, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2962, x5 - li x5, 0x19175bd2 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2962, x5 - li x5, 0xbdb7fff7 - bne x5, x15, csr_fail - li x5, 0x78e5331f - csrrs x15, 2962, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2962, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2962, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x030c0f19 - csrrc x15, 2962, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2962, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2962, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2962, 0b00001 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2962, 0b00101 - li x5, 0x00000001 - bne x5, x15, csr_fail - csrrsi x15, 2962, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrsi x15, 2962, 0b10001 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2962, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2962, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2962, 0b10000 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh19 - li x5, 0xa5a5a5a5 - csrrw x15, 2963, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2963, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x1d5d199e - csrrw x15, 2963, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2963, x5 - li x5, 0x1d5d199e - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2963, x5 - li x5, 0xbdfdbdbf - bne x5, x15, csr_fail - li x5, 0xebff1c39 - csrrs x15, 2963, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2963, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2963, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x927e647f - csrrc x15, 2963, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2963, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2963, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2963, 0b10011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2963, 0b00101 - li x5, 0x00000013 - bne x5, x15, csr_fail - csrrsi x15, 2963, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2963, 0b00011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2963, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2963, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2963, 0b10000 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh20 - li x5, 0xa5a5a5a5 - csrrw x15, 2964, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2964, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x7c713b24 - csrrw x15, 2964, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2964, x5 - li x5, 0x7c713b24 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2964, x5 - li x5, 0xfdf5bfa5 - bne x5, x15, csr_fail - li x5, 0x1d6635ee - csrrs x15, 2964, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2964, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2964, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x0968a804 - csrrc x15, 2964, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2964, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2964, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2964, 0b00110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2964, 0b00101 - li x5, 0x00000006 - bne x5, x15, csr_fail - csrrsi x15, 2964, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2964, 0b00010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2964, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2964, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2964, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh21 - li x5, 0xa5a5a5a5 - csrrw x15, 2965, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2965, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x612df4ba - csrrw x15, 2965, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2965, x5 - li x5, 0x612df4ba - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2965, x5 - li x5, 0xe5adf5bf - bne x5, x15, csr_fail - li x5, 0x4c97cb48 - csrrs x15, 2965, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2965, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2965, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x7fe2f772 - csrrc x15, 2965, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2965, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2965, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2965, 0b10000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2965, 0b00101 - li x5, 0x00000010 - bne x5, x15, csr_fail - csrrsi x15, 2965, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2965, 0b00010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2965, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2965, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2965, 0b11110 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh22 - li x5, 0xa5a5a5a5 - csrrw x15, 2966, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2966, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xce837a0f - csrrw x15, 2966, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2966, x5 - li x5, 0xce837a0f - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2966, x5 - li x5, 0xefa7ffaf - bne x5, x15, csr_fail - li x5, 0x923e9fde - csrrs x15, 2966, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2966, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2966, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xad473df8 - csrrc x15, 2966, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2966, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2966, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2966, 0b10111 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2966, 0b00101 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2966, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2966, 0b01000 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2966, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2966, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2966, 0b01011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh23 - li x5, 0xa5a5a5a5 - csrrw x15, 2967, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2967, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xe6276ce9 - csrrw x15, 2967, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2967, x5 - li x5, 0xe6276ce9 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2967, x5 - li x5, 0xe7a7eded - bne x5, x15, csr_fail - li x5, 0x30a2bc64 - csrrs x15, 2967, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2967, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2967, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x1993db40 - csrrc x15, 2967, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2967, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2967, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2967, 0b11000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2967, 0b00101 - li x5, 0x00000018 - bne x5, x15, csr_fail - csrrsi x15, 2967, 0b11010 - li x5, 0x0000001d - bne x5, x15, csr_fail - csrrsi x15, 2967, 0b11011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2967, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2967, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2967, 0b11001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh24 - li x5, 0xa5a5a5a5 - csrrw x15, 2968, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2968, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x33aec0ed - csrrw x15, 2968, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2968, x5 - li x5, 0x33aec0ed - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2968, x5 - li x5, 0xb7afe5ed - bne x5, x15, csr_fail - li x5, 0xfa5a4dd9 - csrrs x15, 2968, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2968, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2968, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x16b2cdd0 - csrrc x15, 2968, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2968, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2968, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2968, 0b10000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2968, 0b00101 - li x5, 0x00000010 - bne x5, x15, csr_fail - csrrsi x15, 2968, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2968, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2968, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2968, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2968, 0b01001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh25 - li x5, 0xa5a5a5a5 - csrrw x15, 2969, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2969, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x7981abbb - csrrw x15, 2969, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2969, x5 - li x5, 0x7981abbb - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2969, x5 - li x5, 0xfda5afbf - bne x5, x15, csr_fail - li x5, 0x2a637600 - csrrs x15, 2969, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2969, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2969, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x8e5de396 - csrrc x15, 2969, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2969, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2969, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2969, 0b01111 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2969, 0b00101 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2969, 0b11010 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2969, 0b10111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2969, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2969, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2969, 0b11010 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh26 - li x5, 0xa5a5a5a5 - csrrw x15, 2970, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2970, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x453b4cc5 - csrrw x15, 2970, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2970, x5 - li x5, 0x453b4cc5 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2970, x5 - li x5, 0xe5bfede5 - bne x5, x15, csr_fail - li x5, 0x9af3ee1b - csrrs x15, 2970, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2970, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2970, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x9b5af5a0 - csrrc x15, 2970, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2970, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2970, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2970, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2970, 0b00101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2970, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2970, 0b11111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2970, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2970, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2970, 0b11011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh27 - li x5, 0xa5a5a5a5 - csrrw x15, 2971, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2971, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x2ea119f8 - csrrw x15, 2971, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2971, x5 - li x5, 0x2ea119f8 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2971, x5 - li x5, 0xafa5bdfd - bne x5, x15, csr_fail - li x5, 0x263ed361 - csrrs x15, 2971, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2971, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2971, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x3559f480 - csrrc x15, 2971, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2971, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2971, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2971, 0b10010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2971, 0b00101 - li x5, 0x00000012 - bne x5, x15, csr_fail - csrrsi x15, 2971, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2971, 0b01100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2971, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2971, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2971, 0b00001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh28 - li x5, 0xa5a5a5a5 - csrrw x15, 2972, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2972, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x8e030ab4 - csrrw x15, 2972, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2972, x5 - li x5, 0x8e030ab4 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2972, x5 - li x5, 0xafa7afb5 - bne x5, x15, csr_fail - li x5, 0x1c55a07b - csrrs x15, 2972, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2972, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2972, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x69b45543 - csrrc x15, 2972, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2972, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2972, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2972, 0b01000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2972, 0b00101 - li x5, 0x00000008 - bne x5, x15, csr_fail - csrrsi x15, 2972, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2972, 0b11100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2972, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2972, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2972, 0b10100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh29 - li x5, 0xa5a5a5a5 - csrrw x15, 2973, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2973, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xeeaee738 - csrrw x15, 2973, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2973, x5 - li x5, 0xeeaee738 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2973, x5 - li x5, 0xefafe7bd - bne x5, x15, csr_fail - li x5, 0x184d62ef - csrrs x15, 2973, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2973, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2973, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xd1aee09c - csrrc x15, 2973, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2973, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2973, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2973, 0b10000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2973, 0b00101 - li x5, 0x00000010 - bne x5, x15, csr_fail - csrrsi x15, 2973, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2973, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2973, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2973, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2973, 0b11101 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh30 - li x5, 0xa5a5a5a5 - csrrw x15, 2974, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2974, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x11c41528 - csrrw x15, 2974, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2974, x5 - li x5, 0x11c41528 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2974, x5 - li x5, 0xb5e5b5ad - bne x5, x15, csr_fail - li x5, 0xce03cd76 - csrrs x15, 2974, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2974, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2974, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x8d82832d - csrrc x15, 2974, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2974, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2974, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2974, 0b10010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2974, 0b00101 - li x5, 0x00000012 - bne x5, x15, csr_fail - csrrsi x15, 2974, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2974, 0b00011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2974, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2974, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2974, 0b00000 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh31 - li x5, 0xa5a5a5a5 - csrrw x15, 2975, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2975, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x8fbb05fb - csrrw x15, 2975, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2975, x5 - li x5, 0x8fbb05fb - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2975, x5 - li x5, 0xafbfa5ff - bne x5, x15, csr_fail - li x5, 0x4b6a3f57 - csrrs x15, 2975, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2975, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2975, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xcf06f89a - csrrc x15, 2975, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2975, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2975, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2975, 0b10110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2975, 0b00101 - li x5, 0x00000016 - bne x5, x15, csr_fail - csrrsi x15, 2975, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2975, 0b00011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2975, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2975, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2975, 0b00011 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrr x15, 2975 - li x5, 0x00000000 - bne x5, x15, csr_fail - -################################################################################ -# -# Generated code ends... -# -################################################################################ -test_done: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'D' - sw a1,0(a0) - addi a1,zero,'O' - sw a1,0(a0) - addi a1,zero,'N' - sw a1,0(a0) - addi a1,zero,'E' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - -csr_pass: - li x18, 123456789 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi - -csr_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - - li x18, 1 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi -# -# end -# diff --git a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_2/test.yaml b/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_2/test.yaml deleted file mode 100644 index b6de2a05eb..0000000000 --- a/cv32e40s/tests/programs/custom/mhpmcounter29_csr_access_test_2/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: mhpmcounter29_csr_access_test_2 -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR access test with NUM_MHPMCOUNTER = 29 (FIXME ISS does not set correct reset value for mcountinhibit) diff --git a/cv32e40s/tests/programs/custom/misalign/misalign.c b/cv32e40s/tests/programs/custom/misalign/misalign.c index 70c72a4843..c545da74d4 100644 --- a/cv32e40s/tests/programs/custom/misalign/misalign.c +++ b/cv32e40s/tests/programs/custom/misalign/misalign.c @@ -1,6 +1,7 @@ #include #include -#include +#include +#include //#include "../../../core/custom/startup/support.h" #include "./support.h" @@ -84,15 +85,15 @@ int main () { printf("\n"); printf("Load Index=%d off=%d\n", i, i%4); - bzero(cpa, 32); + memset((void *)(cpa-i), 0, 32); *spa = *(u16 *)(pLoad + i); printf(" (u16 *) = %04X\n", *spa); - bzero(cpa, 32); + memset((void *)(cpa-i), 0, 32); *ipa = *(u32 *)(pLoad + i); printf(" (u32 *) = %08X\n", *ipa); - bzero(cpa, 32); + memset((void *)(cpa-i), 0, 32); *lpa = *(u64 *)(pLoad + i); u64_32.u64v = *lpa; printf(" (u64 *) = %08X%08X\n", u64_32.u32v[1], u64_32.u32v[0]); diff --git a/cv32e40s/tests/programs/custom/modeled_csr_por/modeled_csr_por.c b/cv32e40s/tests/programs/custom/modeled_csr_por/modeled_csr_por.c index f1ec9d88c6..c6861712d5 100644 --- a/cv32e40s/tests/programs/custom/modeled_csr_por/modeled_csr_por.c +++ b/cv32e40s/tests/programs/custom/modeled_csr_por/modeled_csr_por.c @@ -32,8 +32,9 @@ #include #include +#include -#define EXP_MISA 0x40101104 +#define EXP_MISA 0x40901104 int main(int argc, char *argv[]) { diff --git a/cv32e40s/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.c b/cv32e40s/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.c deleted file mode 100644 index 23f380436f..0000000000 --- a/cv32e40s/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.c +++ /dev/null @@ -1,941 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Performance Counters Basic test: -** -******************************************************************************* - //lw x8, 4(sp)\n\t\ - //lh x8, 4(sp)\n\t\ - //lhu x8, 4(sp)\n\t\ - //lb x8, 4(sp)\n\t\ - //lbu x8, 4(sp)\n\t\ -*/ - -#include -#include - -#ifndef NUM_MPHMCOUNTERS -#define NUM_MHPMCOUNTERS 1 -#endif - -static int chck(unsigned int is, unsigned int should) -{ - int err; - err = is == should ? 0 : 1; - if (err) - printf("fail %d %d\n", is, should); - else - printf("pass\n"); - return err; -} - -static int chck_le(unsigned int is, unsigned int should) -{ - int err; - err = is <= should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -int main(int argc, char *argv[]) -{ - - volatile unsigned int mcycle_rval; - volatile unsigned int minstret_rval; - volatile unsigned int mcountinhibit_rval; - volatile unsigned int mhpmcounter_rval[32]; - volatile unsigned int mhpmevent_rval[32]; - volatile unsigned int mhartid_rval; - volatile unsigned int sum; - volatile unsigned int count; - volatile unsigned int event; - volatile unsigned int err_cnt; - - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - - __asm__ volatile(".option rvc"); - - sum = 0; - err_cnt = 0; - count = 0; - event = 0; - - unsigned int writable_counters_l = 0; - unsigned int writable_counters_h = 0; - unsigned int temp_readable; - - // Check number of implemented counters - // and test read/write by reading and writing all bits of - // the respective counter CSRs - verify that the - // read CSRs that are nonzero match up with the bits read - // from mcountinhibit - __asm__ volatile("addi t1, x0, 0xFFFFFFFF"); - __asm__ volatile("csrrw x0, 0x320, t1"); - - __asm__ volatile("csrw 0xB03, t1"); - __asm__ volatile("csrw 0xB04, t1"); - __asm__ volatile("csrw 0xB05, t1"); - __asm__ volatile("csrw 0xB06, t1"); - __asm__ volatile("csrw 0xB07, t1"); - __asm__ volatile("csrw 0xB08, t1"); - __asm__ volatile("csrw 0xB09, t1"); - __asm__ volatile("csrw 0xB0A, t1"); - __asm__ volatile("csrw 0xB0B, t1"); - __asm__ volatile("csrw 0xB0C, t1"); - __asm__ volatile("csrw 0xB0D, t1"); - __asm__ volatile("csrw 0xB0E, t1"); - __asm__ volatile("csrw 0xB0F, t1"); - __asm__ volatile("csrw 0xB10, t1"); - __asm__ volatile("csrw 0xB11, t1"); - __asm__ volatile("csrw 0xB12, t1"); - __asm__ volatile("csrw 0xB13, t1"); - __asm__ volatile("csrw 0xB14, t1"); - __asm__ volatile("csrw 0xB15, t1"); - __asm__ volatile("csrw 0xB16, t1"); - __asm__ volatile("csrw 0xB17, t1"); - __asm__ volatile("csrw 0xB18, t1"); - __asm__ volatile("csrw 0xB19, t1"); - __asm__ volatile("csrw 0xB1A, t1"); - __asm__ volatile("csrw 0xB1B, t1"); - __asm__ volatile("csrw 0xB1C, t1"); - __asm__ volatile("csrw 0xB1D, t1"); - __asm__ volatile("csrw 0xB1E, t1"); - __asm__ volatile("csrw 0xB1F, t1"); - - __asm__ volatile("csrw 0xB83, t1"); - __asm__ volatile("csrw 0xB84, t1"); - __asm__ volatile("csrw 0xB85, t1"); - __asm__ volatile("csrw 0xB86, t1"); - __asm__ volatile("csrw 0xB87, t1"); - __asm__ volatile("csrw 0xB88, t1"); - __asm__ volatile("csrw 0xB89, t1"); - __asm__ volatile("csrw 0xB8A, t1"); - __asm__ volatile("csrw 0xB8B, t1"); - __asm__ volatile("csrw 0xB8C, t1"); - __asm__ volatile("csrw 0xB8D, t1"); - __asm__ volatile("csrw 0xB8E, t1"); - __asm__ volatile("csrw 0xB8F, t1"); - __asm__ volatile("csrw 0xB90, t1"); - __asm__ volatile("csrw 0xB91, t1"); - __asm__ volatile("csrw 0xB92, t1"); - __asm__ volatile("csrw 0xB93, t1"); - __asm__ volatile("csrw 0xB94, t1"); - __asm__ volatile("csrw 0xB95, t1"); - __asm__ volatile("csrw 0xB96, t1"); - __asm__ volatile("csrw 0xB97, t1"); - __asm__ volatile("csrw 0xB98, t1"); - __asm__ volatile("csrw 0xB99, t1"); - __asm__ volatile("csrw 0xB9A, t1"); - __asm__ volatile("csrw 0xB9B, t1"); - __asm__ volatile("csrw 0xB9C, t1"); - __asm__ volatile("csrw 0xB9D, t1"); - __asm__ volatile("csrw 0xB9E, t1"); - __asm__ volatile("csrw 0xB9F, t1"); - - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 3) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB04" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 4) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB05" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 5) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB06" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 6) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB07" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 7) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB08" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 8) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB09" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 9) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0A" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 10) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0B" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 11) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0C" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 12) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0D" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 13) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0E" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 14) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0F" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 15) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB10" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 16) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB11" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 17) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB12" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 18) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB13" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 19) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB14" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 20) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB15" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 21) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB16" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 22) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB17" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 23) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB18" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 24) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB19" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 25) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1A" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 26) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1B" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 27) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1C" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 28) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1D" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 29) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1E" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 30) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1F" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 31) : writable_counters_l; - - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr %0, 0xB83" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 3) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB84" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 4) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB85" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 5) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB86" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 6) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB87" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 7) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB88" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 8) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB89" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 9) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8A" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 10) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8B" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 11) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8C" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 12) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8D" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 13) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8E" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 14) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8F" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 15) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB90" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 16) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB91" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 17) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB92" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 18) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB93" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 19) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB94" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 20) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB95" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 21) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB96" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 22) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB97" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 23) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB98" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 24) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB99" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 25) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9A" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 26) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9B" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 27) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9C" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 28) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9D" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 29) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9E" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 30) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9F" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 31) : writable_counters_h; - - __asm__ volatile("addi t0, x0, 0"); - __asm__ volatile("csrw 0xB03, t0"); - __asm__ volatile("csrw 0xB04, t0"); - __asm__ volatile("csrw 0xB05, t0"); - __asm__ volatile("csrw 0xB06, t0"); - __asm__ volatile("csrw 0xB07, t0"); - __asm__ volatile("csrw 0xB08, t0"); - __asm__ volatile("csrw 0xB09, t0"); - __asm__ volatile("csrw 0xB0A, t0"); - __asm__ volatile("csrw 0xB0B, t0"); - __asm__ volatile("csrw 0xB0C, t0"); - __asm__ volatile("csrw 0xB0D, t0"); - __asm__ volatile("csrw 0xB0E, t0"); - __asm__ volatile("csrw 0xB0F, t0"); - __asm__ volatile("csrw 0xB10, t0"); - __asm__ volatile("csrw 0xB11, t0"); - __asm__ volatile("csrw 0xB12, t0"); - __asm__ volatile("csrw 0xB13, t0"); - __asm__ volatile("csrw 0xB14, t0"); - __asm__ volatile("csrw 0xB15, t0"); - __asm__ volatile("csrw 0xB16, t0"); - __asm__ volatile("csrw 0xB17, t0"); - __asm__ volatile("csrw 0xB18, t0"); - __asm__ volatile("csrw 0xB19, t0"); - __asm__ volatile("csrw 0xB1A, t0"); - __asm__ volatile("csrw 0xB1B, t0"); - __asm__ volatile("csrw 0xB1C, t0"); - __asm__ volatile("csrw 0xB1D, t0"); - __asm__ volatile("csrw 0xB1E, t0"); - __asm__ volatile("csrw 0xB1F, t0"); - - __asm__ volatile("csrw 0xB83, t0"); - __asm__ volatile("csrw 0xB84, t0"); - __asm__ volatile("csrw 0xB85, t0"); - __asm__ volatile("csrw 0xB86, t0"); - __asm__ volatile("csrw 0xB87, t0"); - __asm__ volatile("csrw 0xB88, t0"); - __asm__ volatile("csrw 0xB89, t0"); - __asm__ volatile("csrw 0xB8A, t0"); - __asm__ volatile("csrw 0xB8B, t0"); - __asm__ volatile("csrw 0xB8C, t0"); - __asm__ volatile("csrw 0xB8D, t0"); - __asm__ volatile("csrw 0xB8E, t0"); - __asm__ volatile("csrw 0xB8F, t0"); - __asm__ volatile("csrw 0xB90, t0"); - __asm__ volatile("csrw 0xB91, t0"); - __asm__ volatile("csrw 0xB92, t0"); - __asm__ volatile("csrw 0xB93, t0"); - __asm__ volatile("csrw 0xB94, t0"); - __asm__ volatile("csrw 0xB95, t0"); - __asm__ volatile("csrw 0xB96, t0"); - __asm__ volatile("csrw 0xB97, t0"); - __asm__ volatile("csrw 0xB98, t0"); - __asm__ volatile("csrw 0xB99, t0"); - __asm__ volatile("csrw 0xB9A, t0"); - __asm__ volatile("csrw 0xB9B, t0"); - __asm__ volatile("csrw 0xB9C, t0"); - __asm__ volatile("csrw 0xB9D, t0"); - __asm__ volatile("csrw 0xB9E, t0"); - __asm__ volatile("csrw 0xB9F, t0"); - - __asm__ volatile("csrr %0, 0x320" : "=r"(mcountinhibit_rval)); - - int v = writable_counters_l & writable_counters_h; - int num_implemented_counters = 0; - if ((mcountinhibit_rval >> 3) && ((writable_counters_l & writable_counters_h) >> 3)) { - printf("\nWritable: %0x", writable_counters_l & writable_counters_h); - for (num_implemented_counters = 0; v; num_implemented_counters++) { - v &= v - 1; - } - printf("\nNumber of detected writable/readable counters: %0d", num_implemented_counters); - } - else { - printf("\nError, writable counters / mcountinhibit mismatch: %0x, %0x", v, mcountinhibit_rval); - err_cnt += 1; - } - - printf("\n\nPerformance Counters Basic Test\n"); - - __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_rval)); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); - - - __asm__ volatile("csrr %0, 0x320" : "=r"(mcountinhibit_rval)); - - - __asm__ volatile("csrr %0, 0xB03" : "=r"(mhpmcounter_rval[3])); - __asm__ volatile("csrr %0, 0xB04" : "=r"(mhpmcounter_rval[4])); - __asm__ volatile("csrr %0, 0xB05" : "=r"(mhpmcounter_rval[5])); - __asm__ volatile("csrr %0, 0xB06" : "=r"(mhpmcounter_rval[6])); - __asm__ volatile("csrr %0, 0xB07" : "=r"(mhpmcounter_rval[7])); - __asm__ volatile("csrr %0, 0xB08" : "=r"(mhpmcounter_rval[8])); - __asm__ volatile("csrr %0, 0xB09" : "=r"(mhpmcounter_rval[9])); - __asm__ volatile("csrr %0, 0xB0A" : "=r"(mhpmcounter_rval[10])); - __asm__ volatile("csrr %0, 0xB0B" : "=r"(mhpmcounter_rval[11])); - __asm__ volatile("csrr %0, 0xB0C" : "=r"(mhpmcounter_rval[12])); - __asm__ volatile("csrr %0, 0xB0D" : "=r"(mhpmcounter_rval[13])); - __asm__ volatile("csrr %0, 0xB0E" : "=r"(mhpmcounter_rval[14])); - __asm__ volatile("csrr %0, 0xB0F" : "=r"(mhpmcounter_rval[15])); - __asm__ volatile("csrr %0, 0xB10" : "=r"(mhpmcounter_rval[16])); - __asm__ volatile("csrr %0, 0xB11" : "=r"(mhpmcounter_rval[17])); - __asm__ volatile("csrr %0, 0xB12" : "=r"(mhpmcounter_rval[18])); - __asm__ volatile("csrr %0, 0xB13" : "=r"(mhpmcounter_rval[19])); - __asm__ volatile("csrr %0, 0xB14" : "=r"(mhpmcounter_rval[20])); - __asm__ volatile("csrr %0, 0xB15" : "=r"(mhpmcounter_rval[21])); - __asm__ volatile("csrr %0, 0xB16" : "=r"(mhpmcounter_rval[22])); - __asm__ volatile("csrr %0, 0xB17" : "=r"(mhpmcounter_rval[23])); - __asm__ volatile("csrr %0, 0xB18" : "=r"(mhpmcounter_rval[24])); - __asm__ volatile("csrr %0, 0xB19" : "=r"(mhpmcounter_rval[25])); - __asm__ volatile("csrr %0, 0xB1A" : "=r"(mhpmcounter_rval[26])); - __asm__ volatile("csrr %0, 0xB1B" : "=r"(mhpmcounter_rval[27])); - __asm__ volatile("csrr %0, 0xB1C" : "=r"(mhpmcounter_rval[28])); - __asm__ volatile("csrr %0, 0xB1D" : "=r"(mhpmcounter_rval[29])); - __asm__ volatile("csrr %0, 0xB1E" : "=r"(mhpmcounter_rval[30])); - __asm__ volatile("csrr %0, 0xB1F" : "=r"(mhpmcounter_rval[31])); - - - __asm__ volatile("csrr %0, 0x323" : "=r"(mhpmevent_rval[3])); - __asm__ volatile("csrr %0, 0x324" : "=r"(mhpmevent_rval[4])); - __asm__ volatile("csrr %0, 0x325" : "=r"(mhpmevent_rval[5])); - __asm__ volatile("csrr %0, 0x326" : "=r"(mhpmevent_rval[6])); - __asm__ volatile("csrr %0, 0x327" : "=r"(mhpmevent_rval[7])); - __asm__ volatile("csrr %0, 0x328" : "=r"(mhpmevent_rval[8])); - __asm__ volatile("csrr %0, 0x329" : "=r"(mhpmevent_rval[9])); - __asm__ volatile("csrr %0, 0x32A" : "=r"(mhpmevent_rval[10])); - __asm__ volatile("csrr %0, 0x32B" : "=r"(mhpmevent_rval[11])); - __asm__ volatile("csrr %0, 0x32C" : "=r"(mhpmevent_rval[12])); - __asm__ volatile("csrr %0, 0x32D" : "=r"(mhpmevent_rval[13])); - __asm__ volatile("csrr %0, 0x32E" : "=r"(mhpmevent_rval[14])); - __asm__ volatile("csrr %0, 0x32F" : "=r"(mhpmevent_rval[15])); - __asm__ volatile("csrr %0, 0x330" : "=r"(mhpmevent_rval[16])); - __asm__ volatile("csrr %0, 0x331" : "=r"(mhpmevent_rval[17])); - __asm__ volatile("csrr %0, 0x332" : "=r"(mhpmevent_rval[18])); - __asm__ volatile("csrr %0, 0x333" : "=r"(mhpmevent_rval[19])); - __asm__ volatile("csrr %0, 0x334" : "=r"(mhpmevent_rval[20])); - __asm__ volatile("csrr %0, 0x335" : "=r"(mhpmevent_rval[21])); - __asm__ volatile("csrr %0, 0x336" : "=r"(mhpmevent_rval[22])); - __asm__ volatile("csrr %0, 0x337" : "=r"(mhpmevent_rval[23])); - __asm__ volatile("csrr %0, 0x338" : "=r"(mhpmevent_rval[24])); - __asm__ volatile("csrr %0, 0x339" : "=r"(mhpmevent_rval[25])); - __asm__ volatile("csrr %0, 0x33A" : "=r"(mhpmevent_rval[26])); - __asm__ volatile("csrr %0, 0x33B" : "=r"(mhpmevent_rval[27])); - __asm__ volatile("csrr %0, 0x33C" : "=r"(mhpmevent_rval[28])); - __asm__ volatile("csrr %0, 0x33D" : "=r"(mhpmevent_rval[29])); - __asm__ volatile("csrr %0, 0x33E" : "=r"(mhpmevent_rval[30])); - __asm__ volatile("csrr %0, 0x33F" : "=r"(mhpmevent_rval[31])); - - for (int i=3; i<32; i++) { - sum += mhpmevent_rval[i]; - } - if (sum) { - printf("ERROR: CSR MHPMEVENT[3..31] not 0x0!\n\n"); - ++err_cnt; - } - - - sum = 0; - for (int i=3; i<32; i++) { - sum += mhpmcounter_rval[i]; - } - if (sum) { - printf("ERROR: CSR MHPMCOUNTER[3..31] not 0x0!\n\n"); - ++err_cnt; - } - - - if (mcycle_rval != 0x0) { - printf("ERROR: CSR MCYCLE not 0x0!\n\n"); - ++err_cnt; - } - - if (minstret_rval != 0x0) { - printf("ERROR: CSR MINSTRET not 0x0!\n\n"); - ++err_cnt; - } - - if (mcountinhibit_rval != 0xD) { - printf("ERROR: CSR MCOUNTINHIBIT not 0xD!\n\n"); - ++err_cnt; - } - - - printf("MCYCLE Initial Value is %0x\n", mcycle_rval); - printf("MINSTRET Initial Value is %0x\n", minstret_rval); - printf("MCOUNTINHIBIT Initial Value is %0x\n", mcountinhibit_rval); - -////////////////////////////////////////////////////////////// - // To complete code coverage try to write all unimplemented HPMEVENT registers - for (int i = 3; i <= 31; i++) { - volatile unsigned int revent; - volatile unsigned int wevent = (unsigned int) -1; - - - if (i >= NUM_MHPMCOUNTERS+3) { - switch (i) { - case 3: - __asm__ volatile("csrw mhpmevent3, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent3" : "=r"(revent)); - break; - case 4: - __asm__ volatile("csrw mhpmevent4, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent4" : "=r"(revent)); - break; - case 5: - __asm__ volatile("csrw mhpmevent5, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent5" : "=r"(revent)); - break; - case 6: - __asm__ volatile("csrw mhpmevent6, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent6" : "=r"(revent)); - break; - case 7: - __asm__ volatile("csrw mhpmevent7, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent7" : "=r"(revent)); - break; - case 8: - __asm__ volatile("csrw mhpmevent8, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent8" : "=r"(revent)); - break; - case 9: - __asm__ volatile("csrw mhpmevent9, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent9" : "=r"(revent)); - break; - case 10: - __asm__ volatile("csrw mhpmevent10, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent10" : "=r"(revent)); - break; - case 11: - __asm__ volatile("csrw mhpmevent11, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent11" : "=r"(revent)); - break; - case 12: - __asm__ volatile("csrw mhpmevent12, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent12" : "=r"(revent)); - break; - case 13: - __asm__ volatile("csrw mhpmevent13, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent13" : "=r"(revent)); - break; - case 14: - __asm__ volatile("csrw mhpmevent14, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent14" : "=r"(revent)); - break; - case 15: - __asm__ volatile("csrw mhpmevent15, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent15" : "=r"(revent)); - break; - case 16: - __asm__ volatile("csrw mhpmevent16, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent16" : "=r"(revent)); - break; - case 17: - __asm__ volatile("csrw mhpmevent17, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent17" : "=r"(revent)); - break; - case 18: - __asm__ volatile("csrw mhpmevent18, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent18" : "=r"(revent)); - break; - case 19: - __asm__ volatile("csrw mhpmevent19, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent19" : "=r"(revent)); - break; - case 20: - __asm__ volatile("csrw mhpmevent20, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent20" : "=r"(revent)); - break; - case 21: - __asm__ volatile("csrw mhpmevent21, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent21" : "=r"(revent)); - break; - case 22: - __asm__ volatile("csrw mhpmevent22, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent22" : "=r"(revent)); - break; - case 23: - __asm__ volatile("csrw mhpmevent23, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent23" : "=r"(revent)); - break; - case 24: - __asm__ volatile("csrw mhpmevent24, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent24" : "=r"(revent)); - break; - case 25: - __asm__ volatile("csrw mhpmevent25, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent25" : "=r"(revent)); - break; - case 26: - __asm__ volatile("csrw mhpmevent26, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent26" : "=r"(revent)); - break; - case 27: - __asm__ volatile("csrw mhpmevent27, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent27" : "=r"(revent)); - break; - case 28: - __asm__ volatile("csrw mhpmevent28, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent28" : "=r"(revent)); - break; - case 29: - __asm__ volatile("csrw mhpmevent29, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent29" : "=r"(revent)); - break; - case 30: - __asm__ volatile("csrw mhpmevent30, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent30" : "=r"(revent)); - break; - case 31: - __asm__ volatile("csrw mhpmevent31, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent31" : "=r"(revent)); - break; - } - - if (revent != 0) { - printf("ERROR: MHPMEVENT%d does not read back zero 0x%0x\n", i, revent); - ++err_cnt; - } - } - } - -////////////////////////////////////////////////////////////// - // Count load use hazards - printf("\nCount load use hazards"); - - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x4, 0(sp)\n\t\ - addi x5, x4, 1\n\t\ - lw x4, 0(sp)\n\t\ - lw x4, 4(sp)\n\t\ - addi x6, x4, 4\n\t\ - lh x8, 4(sp)\n\t\ - addi x6, x8, 4\n\t\ - lhu x6, 4(sp)\n\t\ - lb x6, 4(sp)\n\t\ - addi x5, x6, 1\n\t\ - lbu x6, 4(sp)\n\t\ - lh x5, 4(sp)\n\t\ - addi x5, x5, 4\n\t\ - addi x7, x0, 1" \ - : : : "x4", "x5", "x6", "x7", "x8"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 15); - - - printf("Load use hazards count = %d\n", count); - - err_cnt += chck_le(count, 5); - - - ////////////////////////////////////////////////////////////// - // Count jump register hazards - printf("\nCount Jump register hazards"); - - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - lh x4, 4(sp)\n\t\ - addi x4, x4, 10\n\t\ - lw x4, 4(sp)\n\t\ - addi x4, x4, 10\n\t\ - addi x4, x4, 10\n\t\ - addi x4, x4, 10\n\t\ - auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0" \ - : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 18); - - printf("Jump register hazards count = %d\n", count); - err_cnt += chck_le(count, 3); // 3 if no instruction if stalls are present - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - printf("\nCount memory read transactions"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x4, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("j jump_target_memread"); // do not count jump in mhpmevent3 - __asm__ volatile("nop"); // do not count nop in instret - __asm__ volatile("jump_target_memread:"); - __asm__ volatile("lw x4, 0(sp)"); // count++ - __asm__ volatile("addi x4, x4, 10"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 6); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count memory write transactions - printf("\nCount memory write transactions"); - - event = EVENT_DATA_WRITE; // Trigger on stores - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Store count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count jumps - printf("\nCount jumps"); - - event = EVENT_JUMP; // Trigger on jumps - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("j jump_target_0"); // count++ - __asm__ volatile("jump_target_0:"); - __asm__ volatile("j jump_target_1"); // count++ - __asm__ volatile("jump_target_1:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 3); - - printf("Jump count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count branches (conditional) - printf("\nCount branches (conditional)"); - - event = EVENT_BRANCH; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_0"); // count++ - __asm__ volatile("branch_target_0:"); - __asm__ volatile("bne x0, x0, branch_target_1"); // count++ - __asm__ volatile("branch_target_1:"); - __asm__ volatile("beq x0, x0, branch_target_2"); // count++ - __asm__ volatile("branch_target_2:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Branch count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Count branches taken (conditional) - printf("\nCount branches taken (conditional)"); - - event = EVENT_BRANCH_TAKEN; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_3"); // count++ - __asm__ volatile("branch_target_3:"); - __asm__ volatile("bne x0, x0, branch_target_4"); // (not taken) - __asm__ volatile("branch_target_4:"); - __asm__ volatile("beq x0, x0, branch_target_5"); // count++ - __asm__ volatile("branch_target_5:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Branch taken count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Compressed instructions - printf("\nCompressed instructions"); - - event = EVENT_COMP_INSTR; // Trigger on compressed instructions - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("c.addi x15, 1\n\t\ - c.nop\n\t\ - c.addi x15, 1" \ - : : : "x15"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Compressed count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Retired instruction count - printf("\nRetired instruction count"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile(".option rvc"); - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)\n\t\ - addi t0, x0, 5\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0\n\t\ - lw t2, 0(sp)\n\t\ - branch_target: addi t2, t2, 1\n\t\ - addi t1, t1, 1\n\t\ - lw t2, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - bne t0, t1, branch_target\n\t\ - j jump_target\n\t\ - lw t2, 0(sp)\n\t\ - lw t2, 0(sp)\n\t\ - jump_target: nop\n\t\ - nop\n\t\ - nop" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 5 + 6*5 + 4 + 1); - - printf("Retired instruction count = %d\n", count); - err_cnt += chck(count, 5 + 6*5 + 4 + 1); - - ////////////////////////////////////////////////////////////// - // Check for errors - printf("\nDone\n"); - - if (err_cnt) - printf("FAILURE. %d errors\n\n", err_cnt); - else - printf("SUCCESS\n\n"); - - return err_cnt; - - - printf("MCYCLE Final Read Value is %0x\n", mcycle_rval); - printf("MINSTRET Final Read Value is %0x\n", minstret_rval); - printf("MCOUNTINHIBIT Final Read Value is %0x\n", mcountinhibit_rval); - printf("MHARTID Final Read Value is %0x\n", mhartid_rval); - - printf("DONE!\n\n"); - -} - diff --git a/cv32e40s/tests/programs/custom/perf_counters_instructions/test.yaml b/cv32e40s/tests/programs/custom/perf_counters_instructions/test.yaml deleted file mode 100644 index 41f2fd970a..0000000000 --- a/cv32e40s/tests/programs/custom/perf_counters_instructions/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: perf_counters_instructions -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Performance Counters Basic Test diff --git a/cv32e40s/tests/programs/custom/pma/README.md b/cv32e40s/tests/programs/custom/pma/README.md index 0367c97aa0..9a68050788 100644 --- a/cv32e40s/tests/programs/custom/pma/README.md +++ b/cv32e40s/tests/programs/custom/pma/README.md @@ -1,3 +1,7 @@ -Here are directed tests for the PMA. -It captures the majority of the directed tests specified in the vPlan. -When running, one must specify a config like `make ... CFG=pma`. +Directed tests for the PMA. + +Captures the majority of directed tests in the vPlan. +Requires `CFG=pma`. + +This test re-uses the debug memory area since no debug features are used here. +This avoids changing the linker files for the testing needs. diff --git a/cv32e40s/tests/programs/custom/pma/pma.c b/cv32e40s/tests/programs/custom/pma/pma.c index d87b665182..36f0e99274 100644 --- a/cv32e40s/tests/programs/custom/pma/pma.c +++ b/cv32e40s/tests/programs/custom/pma/pma.c @@ -1,5 +1,5 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. +// +// Copyright 2023 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,418 +13,1147 @@ // See the License for the specific language governing permissions and // limitations under the License. // -// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Robin Pedersen/Henrik Fegran +// +// PMA directed tests +// +///////////////////////////////////////////////////////////////////////////////// #include #include +#include +#include +#include +#include +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 9 +// Start at 1 (ignore dummy test that is only used for env sanity checking during dev.) +#define START_TEST_NUM 1 +// Abort test at first self-check fail, useful for debugging. +#define ABORT_ON_ERROR_IMMEDIATE 0 + +// Addresses of VP interrupt control registers +#define TIMER_REG_ADDR ((volatile uint32_t * volatile) (CV_VP_INTR_TIMER_BASE)) +#define TIMER_VAL_ADDR ((volatile uint32_t * volatile) (CV_VP_INTR_TIMER_BASE + 4)) +#define DEBUG_REQ_CONTROL_REG *((volatile uint32_t * volatile) (CV_VP_DEBUG_CONTROL_BASE)) + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + +// --------------------------------------------------------------- +// Type definitions +// --------------------------------------------------------------- + + +// Verbosity levels (Akin to the uvm verbosity concept) +typedef enum { + V_OFF = 0, + V_LOW = 1, + V_MEDIUM = 2, + V_HIGH = 3, + V_DEBUG = 4 +} verbosity_t; + +typedef enum { + MCAUSE_ACCESS_FAULT = 1, + MCAUSE_ILLEGAL = 2, + MCAUSE_BREAKPT = 3, + MCAUSE_LOAD_FAULT = 5, + MCAUSE_STORE_FAULT = 7, + MCAUSE_UMODE_ECALL = 8, + MCAUSE_MMODE_ECALL = 11, + MCAUSE_INSTR_BUS_FAULT = 24, + MCAUSE_CHK_FAULT = 25, +} mcause_exception_status_t; + +typedef union { + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_30_12 : 19; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clint; + struct { + volatile uint32_t exccode : 12; + volatile uint32_t res_15_12 : 4; + volatile uint32_t mpil : 8; + volatile uint32_t res_26_24 : 3; + volatile uint32_t mpie : 1; + volatile uint32_t mpp : 2; + volatile uint32_t minhv : 1; + volatile uint32_t interrupt : 1; + } __attribute__((packed)) volatile clic; + volatile uint32_t raw : 32; +} __attribute__((packed)) mcause_t; + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- + +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +// Global pointer variables +volatile uint32_t * volatile g_has_clic; +volatile uint32_t * volatile g_exp_fault; +volatile mcause_t * volatile g_mcause; +volatile uint32_t * volatile g_mepc; +volatile uint32_t * volatile g_mtval; +volatile uint32_t * volatile g_test_num; +volatile uint32_t * volatile g_recovery_ptr; + +// External symbols +extern volatile uint32_t mtvt_table; + +// Message strings for use in assembly printf +//const volatile char * const volatile asm_printf_msg_template = "Entered handler %0d\n"; + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t dummy(uint32_t index, uint8_t report_name); +uint32_t exec_only_for_main_regions(uint32_t index, uint8_t report_name); +uint32_t non_natural_aligned_store_to_io(uint32_t index, uint8_t report_name); +uint32_t non_natural_aligned_loads_from_io(uint32_t index, uint8_t report_name); +uint32_t misaligned_fault_nochange_regfile(uint32_t index, uint8_t report_name); +uint32_t misaligned_border_io_to_mem(uint32_t index, uint8_t report_name); +uint32_t misaligned_border_mem_to_io(uint32_t index, uint8_t report_name); +uint32_t misalign_store_fault_no_bus_access_second(uint32_t index, uint8_t report_name); +uint32_t misalign_store_fault_io_no_bus_access_first(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Prototypes for functions that are test specific and +// perform the debug part of specific tests. +// --------------------------------------------------------------- +//void template_function_dbg(void) __attribute__((section(".debugger"), __noinline__)); + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +void increment_mepc(volatile uint32_t incr_val); +void clear_status_csrs(void); + +// IRQ related +uint32_t detect_irq_mode(void); +void setup_clic(void); + + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(volatile uint32_t test_no, volatile uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...) __attribute((__noinline__)); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + // Allocate memory for global pointers here + g_has_clic = calloc(1, sizeof(uint32_t)); + g_mcause = calloc(1, sizeof(mcause_t)); + g_mepc = calloc(1, sizeof(uint32_t)); + g_mtval = calloc(1, sizeof(uint32_t)); + g_test_num = calloc(1, sizeof(uint32_t)); + g_exp_fault = calloc(1, sizeof(uint32_t)); + g_recovery_ptr = calloc(1, sizeof(uint32_t)); + + // Setup clic mtvt if clic is enabled + *g_has_clic = detect_irq_mode(); + setup_clic(); + + // Add function pointers to new tests here + tests[0] = dummy; // unused, can be used for env sanity checking + tests[1] = exec_only_for_main_regions; + tests[2] = non_natural_aligned_store_to_io; + tests[3] = non_natural_aligned_loads_from_io; + tests[4] = misaligned_fault_nochange_regfile; + tests[5] = misaligned_border_io_to_mem; + tests[6] = misaligned_border_mem_to_io; + tests[7] = misalign_store_fault_no_bus_access_second; + tests[8] = misalign_store_fault_io_no_bus_access_first; + // Run all tests in list above + cvprintf(V_LOW, "\nPMA test start\n\n"); + for (volatile uint32_t i = START_TEST_NUM; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + // Free dynamically allocated memory + free((void *)g_has_clic ); + free((void *)g_mcause ); + free((void *)g_mepc ); + free((void *)g_mtval ); + free((void *)g_test_num ); + free((void *)g_exp_fault ); + free((void *)g_recovery_ptr ); -#define EXCEPTION_INSN_ACCESS_FAULT 1 -#define EXCEPTION_LOAD_ACCESS_FAULT 5 -#define EXCEPTION_STOREAMO_ACCESS_FAULT 7 -#define MEM_ADDR_0 0 -#define IO_ADDR (0x1A110800 + 16) -#define MEM_ADDR_1 0x1A111000 -#define MTVAL_READ 0 -#define MTBLJALVEC 0 // TODO update when RTL is implemented -#define TBLJ_TARGET_ADDR (IO_ADDR + 8) - -static volatile uint32_t mcause = 0; -static volatile uint32_t mepc = 0; -static volatile uint32_t mtval = 0; -static volatile uint32_t retpc = 0; - -// Exception-causing instructions -static void (*instr_access_fault)(void) = (void (*)(void))IO_ADDR; -void misaligned_store(void) { - uint32_t tmp; - tmp = 0xBBBBBBBB; - __asm__ volatile("sw %0, 1(%1)" : "=r"(tmp) : "r"(IO_ADDR)); + return retval; // Nonzero for failing tests } -void load_misaligned_io(void) {__asm__ volatile("lw t0, 3(%0)" : : "r"(IO_ADDR));} -void load_misaligned_iomem(void) {__asm__ volatile("lw t0, 0(%0)" : : "r"(MEM_ADDR_1 - 3));} -void load_misaligned_memio(void) {__asm__ volatile("lw t0, 0(%0)" : : "r"(IO_ADDR - 1));} -void store_first_access(void) {__asm__ volatile("sw %0, 2(%1)" : : "r"(0x11223344), "r"(IO_ADDR));} -void store_second_access(void) {__asm__ volatile("sw %0, -2(%1)" : : "r"(0x22334455), "r"(MEM_ADDR_1));} - -__attribute__((naked)) -void provoke(void (*f)(void)) { - // Prolog - __asm__ volatile("addi sp,sp,-64"); - __asm__ volatile("sw ra, 0(sp)"); - __asm__ volatile("sw a0, 4(sp)"); - __asm__ volatile("sw a1, 8(sp)"); - __asm__ volatile("sw a2, 12(sp)"); - __asm__ volatile("sw a3, 16(sp)"); - __asm__ volatile("sw a4, 20(sp)"); - __asm__ volatile("sw a5, 24(sp)"); - __asm__ volatile("sw a6, 28(sp)"); - __asm__ volatile("sw a7, 32(sp)"); - __asm__ volatile("sw t0, 36(sp)"); - __asm__ volatile("sw t1, 40(sp)"); - __asm__ volatile("sw t2, 44(sp)"); - __asm__ volatile("sw t3, 48(sp)"); - __asm__ volatile("sw t4, 52(sp)"); - __asm__ volatile("sw t5, 56(sp)"); - __asm__ volatile("sw t6, 60(sp)"); - - // Let trap handler know where to continue - __asm__ volatile("addi %0, ra, 0" : "=r"(retpc)); - - // Call the function that shall trap - f(); - - // Handler must do epilog + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(volatile uint32_t test_no, volatile uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_NUM; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } + return res; } -static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { - if (actual != expect) { - printf(msg); - printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); - exit(EXIT_FAILURE); +// ----------------------------------------------------------------------------- + +uint32_t dummy(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; } + + // Example: + // ... + // Some directed test code here + // ... + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; } -__attribute__((naked)) -void u_sw_irq_handler(void) { // overrides a "weak" symbol in the bsp - __asm__ volatile("csrr %0, mcause" : "=r"(mcause)); - __asm__ volatile("csrr %0, mepc" : "=r"(mepc)); - __asm__ volatile("csrr %0, mtval" : "=r"(mtval)); - - __asm__ volatile("csrw mepc, %0" : : "r"(retpc)); - printf("exec in u_sw_irq_handler, mcause=%lx, mepc=%lx, retpc=%lx\n", mcause, mepc, retpc); - - // provoke() did prolog, handler does epilog - __asm__ volatile("lw ra, 0(sp)"); - __asm__ volatile("lw a0, 4(sp)"); - __asm__ volatile("lw a1, 8(sp)"); - __asm__ volatile("lw a2, 12(sp)"); - __asm__ volatile("lw a3, 16(sp)"); - __asm__ volatile("lw a4, 20(sp)"); - __asm__ volatile("lw a5, 24(sp)"); - __asm__ volatile("lw a6, 28(sp)"); - __asm__ volatile("lw a7, 32(sp)"); - __asm__ volatile("lw t0, 36(sp)"); - __asm__ volatile("lw t1, 40(sp)"); - __asm__ volatile("lw t2, 44(sp)"); - __asm__ volatile("lw t3, 48(sp)"); - __asm__ volatile("lw t4, 52(sp)"); - __asm__ volatile("lw t5, 56(sp)"); - __asm__ volatile("lw t6, 60(sp)"); - __asm__ volatile("addi sp,sp,64"); - __asm__ volatile("mret"); +// ----------------------------------------------------------------------------- + +uint32_t exec_only_for_main_regions(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile void (* volatile io_addr)(void) = (volatile void (* volatile)(void))0x1a110810; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_test_num = index; + *g_exp_fault = 1; + + test_fail += (g_mcause->raw != 0); + test_fail += (*g_mtval != 0); + test_fail += (*g_mepc != 0); + + io_addr(); + + test_fail += (g_mcause->raw != MCAUSE_ACCESS_FAULT); + test_fail += (*g_mtval != 0); + test_fail += (*g_mepc != (uint32_t)io_addr); + + test_fail += *g_exp_fault; + clear_status_csrs(); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; } -static void reset_volatiles(void) { - mcause = -1; - mepc = -1; - mtval = -1; +// ----------------------------------------------------------------------------- + +uint32_t non_natural_aligned_store_to_io(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t io_addr = 0x1a110810; + volatile uint32_t tmp = 0xaaaaaaaa; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_test_num = index; + // Sanity, aligned store to IO + *g_exp_fault = 0; + + __asm__ volatile (R"( + sw %[tmp], 0(%[addr]) + )" : [tmp] "=r"(tmp) + : [addr] "r"(io_addr) + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + // Misalgined store to IO + *g_exp_fault = 1; + tmp = 0xbbbbbbbb; + + __asm__ volatile (R"( + sw %[tmp], 1(%[addr]) + )" : [tmp] "=r"(tmp) + : [addr] "r"(io_addr) + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != MCAUSE_STORE_FAULT; + test_fail += *g_mepc == 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + // Sanity, misaligned store to MAIN + *g_exp_fault = 0; + + __asm__ volatile (R"( + sw %[tmp], -9(%[addr]) + )" : [tmp] "=r"(tmp) + : [addr] "r"(io_addr) + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; } -static void check_load_vs_regfile(void) { - // within this scope, t0 regs etc should be free to use (ABI, not preserved) - uint32_t tmp; - - // check misaligned in IO - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xAAAAAAAA), "r"(IO_ADDR)); - __asm__ volatile("sw %0, 4(%1)" : : "r"(0xBBBBBBBB), "r"(IO_ADDR)); - __asm__ volatile("li t0, 0x11223344"); - provoke(load_misaligned_io); - __asm__ volatile("mv %0, t0" : "=r"(tmp)); // t0 must be "rd" in load_misaligned_io() - /* TODO enable when RTL is implemented - assert_or_die(tmp, 0x11223344, "error: misaligned IO load shouldn't touch regfile\n"); - */ - - // check misaligned border from IO to MEM - __asm__ volatile("sw %0, -4(%1)" : : "r"(0xAAAAAAAA), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xBBBBBBBB), "r"(MEM_ADDR_1)); - __asm__ volatile("li t0, 0x22334455"); - provoke(load_misaligned_iomem); - __asm__ volatile("mv %0, t0" : "=r"(tmp)); - /* TODO enable when RTL is implemented - assert_or_die(tmp, 0x22334455, "error: misaligned IO/MEM load shouldn't touch regfile\n"); - */ - - // check misaligned border from MEM to IO - __asm__ volatile("sw %0, -4(%1)" : : "r"(0xAAAAAAAA), "r"(IO_ADDR)); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xBBBBBBBB), "r"(IO_ADDR)); - __asm__ volatile("li t0, 0x33445566"); - provoke(load_misaligned_memio); - __asm__ volatile("mv %0, t0" : "=r"(tmp)); - /* TODO enable when RTL is implemented - assert_or_die(tmp, 0x33445566, "error: misaligned MEM/IO load shouldn't touch regfile\n"); - */ - - // TODO can one programmatically confirm that these addresses are indeed in such regions as intended? +// ----------------------------------------------------------------------------- + +uint32_t non_natural_aligned_loads_from_io(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t io_addr = 0x1a110810; + volatile uint32_t mem_addr = 0x80; + volatile uint32_t tmp = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_test_num = index; + *g_exp_fault = 0; + + // Sanity, aligned loads should be OK + __asm__ volatile (R"( + lw %[tmp], 0(%[addr]) + )" : [tmp] "=r"(tmp) + : [addr] "r"(io_addr) + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + // Check that misaligned load will except + *g_exp_fault = 1; + + __asm__ volatile (R"( + lw %[tmp], 5(%[addr]) + )" : [tmp] "=r"(tmp) + : [addr] "r"(io_addr) + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != MCAUSE_LOAD_FAULT; + test_fail += *g_mepc == 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + // check that misaligned to MAIN does not fail + *g_exp_fault = 0; + + __asm__ volatile (R"( + lw %[tmp], 3(%[addr]) + )" : [tmp] "=r"(tmp) + : [addr] "r"(mem_addr) + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; } -static void check_zce_push(void) { - uint32_t defaults[] = {0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD}; - uint32_t sp; - uint32_t ra; - uint32_t tmp; - - // Prologue - __asm__ volatile("mv %0, sp" : "=r"(sp)); // Saving "sp", for we shall tamper with it - - // Setup preparations - __asm__ volatile("mv sp, %0" : : "r"(MEM_ADDR_1 + 4)); // Set "sp" to have room for 1 MEM before entering IO - __asm__ volatile("mv %0, ra" : "=r"(ra)); // Saving "ra" for later use - __asm__ volatile("sw %0, 0(%1)" : : "r"(defaults[0]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -4(%1)" : : "r"(defaults[1]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -8(%1)" : : "r"(defaults[2]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -12(%1)" : : "r"(defaults[3]), "r"(MEM_ADDR_1)); - - // Run the push stimuli - /* TODO enabled when RTL is implemented - __asm__ volatile(".word 0x000240AB"); // TODO "push {ra, s0-s1}, -16" - */ - - // Epilogue - __asm__ volatile("mv sp, %0" : : "r"(sp)); // Better restore this quickly - - // Assert results - /* TODO enabled when RTL is implemented - assert_or_die(mcause, EXCEPTION_STOREAMO_ACCESS_FAULT, "error: bad push should except\n"); - assert_or_die(mepc, (MEM_ADDR_1 - 4), "error: bad push, unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: bad push, unexpected mtval\n"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, ra, "error: PUSH to MEM should SW successfully\n"); - */ - __asm__ volatile("lw %0, -4(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, defaults[1], "error: PUSH to IO should not SW\n"); - __asm__ volatile("lw %0, -8(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, defaults[2], "error: Trailing PUSHes to IO should not SW\n"); +// ----------------------------------------------------------------------------- + +uint32_t misaligned_fault_nochange_regfile(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t io_addr = 0x1a110810; + volatile uint32_t tmp = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_test_num = index; + + *g_exp_fault = 0; + // Store data to check address + __asm__ volatile (R"( + li %[tmp], 0xaaaaaaaa + sw %[tmp], 0(%[addr]) + li %[tmp], 0xbbbbbbbb + sw %[tmp], 4(%[addr]) + )" + : [tmp] "+r"(tmp) + : [addr] "r"(io_addr) + : "memory" + ); + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + tmp = 0xcafeabba; + // Read misaligned + *g_exp_fault = 1; + + __asm__ volatile (R"( + # need to use explicit register to prevent the compiler from backing up + add t0, %[tmp], zero + # should never execute + lw t0, 3(%[addr]) + + add %[tmp], t0, zero + )" + : [tmp] "+r"(tmp) + : [addr] "r"(io_addr) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xcafeabba; + test_fail += g_mcause->raw != MCAUSE_LOAD_FAULT; + test_fail += *g_mepc == 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + + // Read aligned + *g_exp_fault = 0; + + __asm__ volatile (R"( + lw %[tmp], 0(%[addr]) + )" + : [tmp] "=r"(tmp) + : [addr] "r"(io_addr) + : + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xaaaaaaaa; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; } -static void check_zce_pop(void) { - uint32_t defaults[] = {0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD}; - register uint32_t sp asm ("s8"); // (ask C to not use the registers needed for testing) - register uint32_t s0 asm ("s9"); - register uint32_t s1 asm ("s10"); - register uint32_t ra asm ("s11"); // Hereby pledge to not intentionally use s11, to prevent ra getting corrupted - uint32_t tmp; - - // Prologue - __asm__ volatile("mv %0, sp" : "=r"(sp)); // Saving "sp", for we shall tamper with it - __asm__ volatile("mv %0, ra" : "=r"(ra)); // Saving "ra", for we shall tamper with it - - // Setup - __asm__ volatile("mv sp, %0" : : "r"(MEM_ADDR_1 + 4 - 16)); // Set previous "sp" to have room for 1 MEM before entering IO - __asm__ volatile("sw %0, 0(%1)" : : "r"(defaults[0]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -4(%1)" : : "r"(defaults[1]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -8(%1)" : : "r"(defaults[2]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -12(%1)" : : "r"(defaults[3]), "r"(MEM_ADDR_1)); - __asm__ volatile("mv %0, s0" : "=r"(s0)); // Will check against this later - __asm__ volatile("mv %0, s1" : "=r"(s1)); // Will check against this later - - // Run the instruction - /* TODO enable when RTL is implemented - __asm__ volatile("pop {ra, s0-s1}, 16"); - */ - - // Epilogue 1/2 - __asm__ volatile("mv sp, %0" : : "r"(sp)); - - // Assert results - /* TODO enable when RTL is implemented - assert_or_die(mcause, EXCEPTION_LOAD_ACCESS_FAULT, "error: bad pop should except\n"); - assert_or_die(mepc, (MEM_ADDR_1 - 4), "error: bad pop, unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: bad pop, unexpected mtval\n"); - __asm__ volatile("mv %0, ra" : "=r"(tmp)); - assert_or_die(tmp, defaults[0], "error: POP from MEM should LW ra successfully\n"); - */ - __asm__ volatile("mv %0, s0" : "=r"(tmp)); - assert_or_die(tmp, s0, "error: POP from IO should not LW\n"); - __asm__ volatile("mv %0, s1" : "=r"(tmp)); - assert_or_die(tmp, s1, "error: POP from IO should not continue LWing\n"); - //TODO are assertions good enough that C accidentally using the same registers will either be caught or not be a problem? - - // Epilogue 2/2 - __asm__ volatile("mv ra, %0" : : "r"(ra)); +uint32_t misaligned_border_io_to_mem(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t mem_addr_1 = 0x1a111000; + volatile uint32_t tmp = 0x0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_test_num = index; + + *g_exp_fault = 1; + __asm__ volatile(R"( + # store reference values + li %[tmp], 0xaaaaaaaa + sw %[tmp], -4(%[addr]) + li %[tmp], 0xbbbbbbbb + sw %[tmp], 0(%[addr]) + + # misaligned load + # need to use explicit register to prevent the compiler from backing up + add t0, %[tmp], zero + # should not execute + lw t0, -2(%[addr]) + + add %[tmp], t0, zero + )" + : [tmp] "+r"(tmp) + : [addr] "r"(mem_addr_1) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xbbbbbbbb; + test_fail += g_mcause->raw != MCAUSE_LOAD_FAULT; + test_fail += *g_mepc == 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + + *g_exp_fault = 0; + tmp = 0; + __asm__ volatile(R"( + # halfword load not crossing boundary + lh %[tmp], -2(%[addr]) + )" + : [tmp] "+r"(tmp) + : [addr] "r"(mem_addr_1) + : "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xffffaaaa; // f's due to sign extension + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; } -static int fail_first_tblj(void) { - int mepc = -1; +// ----------------------------------------------------------------------------- + +uint32_t misaligned_border_mem_to_io(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t io_addr = 0x1a110810; + volatile uint32_t tmp = 0x0; - /* TODO enable when RTL is implemented - // TODO make sure the target address is non-executable, so we can check if mtval matches first fetch - __asm__ volatile("c.tbljal 0"); - */ - __asm__ volatile("auipc %0, 0" : "=r"(mepc)); - mepc -= 4; + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } - return mepc; + *g_test_num = index; + + *g_exp_fault = 1; + + __asm__ volatile(R"( + # store reference values + li %[tmp], 0xaaaaaaaa + sw %[tmp], -4(%[addr]) + li %[tmp], 0xbbbbbbbb + sw %[tmp], 0(%[addr]) + + # Misaligned, boundary crossing load + # need to use explicit register to prevent the compiler from backing up + add t0, %[tmp], zero + # should not execute + lw t0, -1(%[addr]) + + add %[tmp], t0, zero + )" + : [tmp] "+r"(tmp) + : [addr] "r"(io_addr) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xbbbbbbbb; + test_fail += g_mcause->raw != MCAUSE_LOAD_FAULT; + test_fail += *g_mepc == 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + tmp = 0; + + *g_exp_fault = 0; + // Sanity, aligned + __asm__ volatile(R"( + # aligned load + lb %[tmp], -1(%[addr]) + )" + : [tmp] "+r"(tmp) + : [addr] "r"(io_addr) + : "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xffffffaa; // f's due to sign extension + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; } -int main(void) { - uint32_t tmp; +// ----------------------------------------------------------------------------- - printf("\nHello, PMA test!\n\n"); - assert_or_die(mcause, 0, "error: mcause variable should initially be 0\n"); - assert_or_die(mepc, 0, "error: mepc variable should initially be 0\n"); - assert_or_die(mtval, 0, "error: mtval variable should initially be 0\n"); +uint32_t misalign_store_fault_no_bus_access_second(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t io_addr = 0x1a110810; + volatile uint32_t tmp = 0x0; - // TODO "mtval" should in the future not be read-only read-zero. + SET_FUNC_INFO + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } - // Exec should only work for "main memory" regions + *g_test_num = index; - reset_volatiles(); - provoke(instr_access_fault); - assert_or_die(mcause, EXCEPTION_INSN_ACCESS_FAULT, "error: expected instruction access fault\n"); - assert_or_die(mepc, IO_ADDR, "error: expected different mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: expected different mtval\n"); + // Check first access fail + *g_exp_fault = 1; + tmp = 0; + __asm__ volatile(R"( + # store reference values + li t0, 0xaaaaaaaa + sw t0, 0(%[addr]) + li t0, 0xbbbbbbbb + sw t0, 4(%[addr]) + + # Misaligned, boundary crossing store + li t0, 0x11223344 + sw t0, 2(%[addr]) + )" + : + : [addr] "r"(io_addr) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != MCAUSE_STORE_FAULT; + test_fail += *g_mepc == 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + __asm__ volatile(R"( + # Check if first store op reached bus + lw t0, 0(%[addr]) + add %[tmp], t0, zero + )" + : [tmp] "=r"(tmp) + : [addr] "r"(io_addr) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xaaaaaaaa; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + tmp = 0; - // Non-naturally aligned stores to I/O regions + *g_exp_fault = 0; + + __asm__ volatile(R"( + # Check if second store op reached bus + lw %[tmp], 4(%[addr]) + )" + : [tmp] "+r"(tmp) + : [addr] "r"(io_addr) + : "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xbbbbbbbb; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- - // sanity check that aligned stores are ok - reset_volatiles(); - tmp = 0xAAAAAAAA; - __asm__ volatile("sw %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, -1, "error: aligned store should not change mcause\n"); - assert_or_die(mepc, -1, "error: aligned store should not change mepc\n"); - assert_or_die(mtval, -1, "error: aligned store should not change mtval\n"); +uint32_t misalign_store_fault_io_no_bus_access_first(uint32_t index, uint8_t report_name) { + volatile uint32_t test_fail = 0; + volatile uint32_t mem_addr_1 = 0x1a111000; + volatile uint32_t tmp = 0x0; - // check that misaligned stores except - reset_volatiles(); - provoke(misaligned_store); - assert_or_die(mcause, EXCEPTION_STOREAMO_ACCESS_FAULT, "error: misaligned store unexpected mcause\n"); - //TODO:ropeders fix: assert_or_die(mepc, (IO_ADDR + 1), "error: misaligned store unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: misaligned store unexpected mtval\n"); + SET_FUNC_INFO - // check that misaligned store to MEM is alright - reset_volatiles(); - tmp = 0xCCCCCCCC; - __asm__ volatile("sw %0, -9(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, -1, "error: misaligned store to main affected mcause\n"); - assert_or_die(mepc, -1, "error: misaligned store to main affected mepc\n"); - assert_or_die(mtval, -1, "error: misaligned store to main affected mtval\n"); + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + *g_test_num = index; - // Non-naturally aligned loads within I/O regions + // Check first access fail + *g_exp_fault = 1; - // sanity check that aligned load is no problem - reset_volatiles(); tmp = 0; - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); // Depends on "store" test filling memory first - assert_or_die(!tmp, 0, "error: load should not yield zero\n"); // TODO ensure memory content matches - assert_or_die(mcause, -1, "error: natty access should not change mcause\n"); - assert_or_die(mepc, -1, "error: natty access should not change mepc\n"); - assert_or_die(mtval, -1, "error: natty access should not change mtval\n"); - - // check that misaligned load will except - /* TODO enable when RTL is implemented - reset_volatiles(); - __asm__ volatile("lw %0, 5(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, EXCEPTION_LOAD_ACCESS_FAULT, "error: misaligned IO load should except\n"); - assert_or_die(mepc, (IO_ADDR + 5), "error: misaligned IO load unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: misaligned IO load unexpected mtval\n"); - */ - // TODO more kinds of |addr[0:1]? Try LH too? - - // check that misaligned to MEM does not fail - reset_volatiles(); + __asm__ volatile(R"( + # store reference values + li t0, 0xaaaaaaaa + sw t0, -4(%[addr]) + li t0, 0xbbbbbbbb + sw t0, 0(%[addr]) + + # Misaligned, boundary crossing store + li t0, 0x22334455 + sw t0, -2(%[addr]) + )" + : + : [addr] "r"(mem_addr_1) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += g_mcause->raw != MCAUSE_STORE_FAULT; + test_fail += *g_mepc == 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + + *g_exp_fault = 0; + + __asm__ volatile(R"( + # Check if first store op reached bus + lw t0, -4(%[addr]) + add %[tmp], t0, zero + )" + : [tmp] "=r"(tmp) + : [addr] "r"(mem_addr_1) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xaaaaaaaa; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + tmp = 0; - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(0x80)); - assert_or_die(!tmp, 0, "error: load from main should not yield zero\n"); - assert_or_die(mcause, -1, "error: main access should not change mcause\n"); - assert_or_die(mepc, -1, "error: main access should not change mepc\n"); - assert_or_die(mtval, -1, "error: main access should not change mtval\n"); - - - // Misaligned load fault shouldn't touch regfile - - // check that various split load access fault leaves regfile untouched - check_load_vs_regfile(); - - - // Misaligned store fault shouldn't reach bus in second access - - // check IO store failing in first access - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xAAAAAAAA), "r"(IO_ADDR)); - __asm__ volatile("sw %0, 4(%1)" : : "r"(0xBBBBBBBB), "r"(IO_ADDR)); - provoke(store_first_access); - /* TODO enable when RTL is implemented - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(tmp, 0xAAAAAAAA, "error: misaligned first store entered bus\n"); - __asm__ volatile("lw %0, 4(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(tmp, 0xBBBBBBBB, "error: misaligned second store entered bus\n"); - */ - // TODO how to programmatically confirm that these region settings match as intended? - - // check IO to MEM store failing in first access - __asm__ volatile("sw %0, -4(%1)" : : "r"(0xAAAAAAAA), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xBBBBBBBB), "r"(MEM_ADDR_1)); - provoke(store_second_access); - /* TODO enable when RTL is implemented - __asm__ volatile("lw %0, -4(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, 0xAAAAAAAA, "error: misaligned IO/MEM first store entered bus\n"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, 0xBBBBBBBB, "error: misaligned IO/MEM second store entered bus\n"); - */ - // TODO how to programmatically confirm that these region settings match as intended? - - - // Atomics should work only where it is allowed - - // Sanity check that atomic ops (lr/sc) to allowed regions is ok - reset_volatiles(); - /* TODO enable when RTL is implemented - __asm__ volatile("lr.w %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - __asm__ volatile("sc.w %0, %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - */ - assert_or_die(mcause, -1, "error: atomics to legal region should not except\n"); - assert_or_die(mepc, -1, "error: atomics to legal region unexpected mepc\n"); - assert_or_die(mtval, -1, "error: atomics to legal region unexpected mtval\n"); - - // Load-reserved to disallowed regions raises precise exception - reset_volatiles(); - /* TODO enable when RTL is implemented - __asm__ volatile("lr.w %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, EXCEPTION_LOAD_ACCESS_FAULT, "error: load-reserved to non-atomic should except\n"); - assert_or_die(mepc, IO_ADDR, "error: load-reserved to non-atomic unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: load-reserved to non-atomic unexpected mtval\n"); - */ - - // Store-conditional to disallowed regions raises precise exception - reset_volatiles(); - /* TODO enable when RTL is implemented - __asm__ volatile("sc.w %0, %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, EXCEPTION_STOREAMO_ACCESS_FAULT, "error: store-conditional to non-atomic should except\n"); - assert_or_die(mepc, IO_ADDR, "error: store-conditional to non-atomic unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: store-conditional to non-atomic unexpected mtval\n"); - */ - - - // Check Zce-related PMA features - - // Push instrs should fault to IO but pass for MEM - check_zce_push(); - - // Pop instrs should fault to IO but pass for MEM - check_zce_pop(); - - // Table jump failing first fetch should be the fault of the table jump - reset_volatiles(); - tmp = fail_first_tblj(); - /* TODO enable when RTL is implemented - assert_or_die(mcause, EXCEPTION_INSN_ACCESS_FAULT, "error: tblj failing first should instruction access fault\n"); - assert_or_die(mepc, tmp, "error: tblj first expected different mepc\n"); - assert_or_die(mtval, MTBLJALVEC, "error: tblj first expected different mtval\n"); - */ - - // Table jump failing second fetch should be the fault of the target - reset_volatiles(); - /* TODO enable when RTL is implemented - make sure table is executable but target is not - __asm__ volatile("c.tbljal 1"); - assert_or_die(mcause, EXCEPTION_INSN_ACCESS_FAULT, "error: tblj failing second should instruction access fault\n"); - assert_or_die(mepc, TBLJ_TARGET_ADDR, "error: tblj second expected different mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: tblj second expected different mtval\n"); - */ - - - printf("\nGoodbye, PMA test!\n\n"); - return EXIT_SUCCESS; + + *g_exp_fault = 0; + + __asm__ volatile(R"( + # Check if second store op reached bus + lw t0, 0(%[addr]) + add %[tmp], t0, zero + )" + : [tmp] "+r"(tmp) + : [addr] "r"(mem_addr_1) + : "t0", "memory" + ); + + test_fail += *g_exp_fault; + test_fail += tmp != 0xbbbbbbbb; + test_fail += g_mcause->raw != 0; + test_fail += *g_mepc != 0; + test_fail += *g_mtval != 0; + clear_status_csrs(); + cvprintf(V_DEBUG, "Tmp: %08lx\n", tmp); + + if (test_fail) { + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_LOW, "\nTest: \"%s\" OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +// TODO: implement the following for 40X: +// Plan: Detect 40s/40x by checking csrs (avoid ifdefs) +// +// printf("pma: 6. Atomics should work only where it is allowed\n"); +// +// printf("pma: Sanity check that atomic ops (lr/sc) to allowed regions is ok\n"); +// reset_volatiles(); +// __asm__ volatile("lr.w %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); +// __asm__ volatile("sc.w %0, %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); +// assert_or_die(g_mcause, -1, "error: atomics to legal region should not except\n"); +// assert_or_die(g_mepc, -1, "error: atomics to legal region unexpected mepc\n"); +// assert_or_die(g_mtval, -1, "error: atomics to legal region unexpected mtval\n"); +// +// printf("pma: Load-reserved to disallowed regions raises precise exception\n"); +// reset_volatiles(); +// __asm__ volatile("lr.w %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); +// assert_or_die(g_mcause, EXCEPTION_LOAD_ACCESS_FAULT, "error: load-reserved to non-atomic should except\n"); +// assert_or_die(g_mepc, IO_ADDR, "error: load-reserved to non-atomic unexpected mepc\n"); +// assert_or_die(g_mtval, MTVAL_READ, "error: load-reserved to non-atomic unexpected mtval\n"); +// +// printf("pma: Store-conditional to disallowed regions raises precise exception\n"); +// reset_volatiles(); +// __asm__ volatile("sc.w %0, %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); +// assert_or_die(g_mcause, EXCEPTION_STOREAMO_ACCESS_FAULT, "error: store-conditional to non-atomic should except\n"); +// assert_or_die(g_mepc, IO_ADDR, "error: store-conditional to non-atomic unexpected mepc\n"); +// assert_or_die(g_mtval, MTVAL_READ, "error: store-conditional to non-atomic unexpected mtval\n"); + +// ----------------------------------------------------------------------------- + +// New tests here... + +// ----------------------------------------------------------------------------- + +void clear_status_csrs(void) { + g_mcause->raw = 0; + *g_mepc = 0; + *g_mtval = 0; +} + +// ----------------------------------------------------------------------------- + +void increment_mepc(volatile uint32_t incr_val) { + volatile uint32_t mepc = 0; + + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + )" : [mepc] "=r"(mepc)); + + if (incr_val == 0) { + // No increment specified, check *mepc instruction + if (((*(uint32_t *)mepc) & 0x3UL) == 0x3UL) { + // non-compressed + mepc += 4; + } else { + // compressed + mepc += 2; + } + } else { + // explicitly requested increment + mepc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, mepc, %[mepc] + )" :: [mepc] "r"(mepc)); +} + +// ----------------------------------------------------------------------------- + +void setup_clic(void) { + if (*g_has_clic == 1) { + __asm__ volatile ( R"( + csrrw zero, 0x307, %[mtvt_table] + )" :: [mtvt_table] "r"(&mtvt_table)); + } +} + +// ----------------------------------------------------------------------------- + +// Template for mtvt code, this may need adaptation if you want to support +// interrupts with ids in the indices below that are populated by zeros +void __attribute__((naked)) mtvt_code(void) { + __asm__ volatile ( R"( + .global mtvt_table + .align 7 + mtvt_table: .long . + 4096 + mtvt_table_1: .long . + 4092 + mtvt_table_2: .long . + 4088 + mtvt_table_3: .long . + 4084 + mtvt_table_4: .long . + 4080 + .space 100, 0x0 + mtvt_table_30: .long . + 3976 + mtvt_table_31: .long . + 3972 + mtvt_table_32: .long . + 3968 + .space 3952, 0x0 + mtvt_table_1021: .long . + 12 + mtvt_table_1022: .long . + 8 + mtvt_table_1023: .long . + 4 + jal zero, m_fast14_irq_handler + )"); + +} + +// ----------------------------------------------------------------------------- + +uint32_t detect_irq_mode(void) { + volatile uint32_t mtvec = 0; + volatile uint32_t is_clic = 0; + + __asm__ volatile ( R"( + csrrs %[mtvec], mtvec, zero + )" : [mtvec] "=r"(mtvec)); + + if ((mtvec & 0x3) == 0x3) { + is_clic = 1; + } + + return is_clic; +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) u_sw_irq_handler(void) { + __asm__ volatile (R"( + .extern u_sw_irq_handler_normal + cm.push {ra, s0-s11}, -112 + addi sp, sp, -12 + + # Save argument registers to stack + # as we want to be able to call C-functions + # from debug + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw a3, 12(sp) + sw a4, 16(sp) + sw a5, 20(sp) + sw a6, 24(sp) + sw a7, 28(sp) + + # Back up remaining temporaries + sw tp, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + + sw gp, 64(sp) + + lw t0, g_recovery_ptr + sw ra, 0(t0) + + jal ra, u_sw_irq_handler_normal + + lw t0, g_recovery_ptr + lw ra, 0(t0) + + ## restore stack + lw gp, 64(sp) + + # Restore temporary registers + lw t6, 60(sp) + lw t5, 56(sp) + lw t4, 52(sp) + lw t3, 48(sp) + lw t2, 44(sp) + lw t1, 40(sp) + lw t0, 36(sp) + lw tp, 32(sp) + + # Restore argument registers + lw a7, 28(sp) + lw a6, 24(sp) + lw a5, 20(sp) + lw a4, 16(sp) + lw a3, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + + # Restore stack ptr + addi sp, sp, 12 + cm.pop {ra, s0-s11}, 112 + mret + )"); + +} + +void u_sw_irq_handler_normal(void) { + volatile uint32_t ra = 0; + + __asm__ volatile( R"( + add %[ra], ra, zero + csrrs %[mcause], mcause, zero + csrrs %[mepc], mepc, zero + csrrs %[mtval], mtval, zero + )" + : [ra] "=r"(ra), + [mcause] "=r"(g_mcause->raw), + [mepc] "=r"(*g_mepc), + [mtval] "=r"(*g_mtval) + : + : "memory" + ); + + if (*g_test_num == 1) { + *g_exp_fault = 0; + __asm__ volatile ( R"( + lw t0, g_recovery_ptr + lw t0, 0(t0) + csrrw zero, mepc, t0 + )" ::: "t0", "memory"); + } + else if (*g_test_num >= 2 && *g_test_num <= 9) { + increment_mepc(0); + if (*g_exp_fault) { + *g_exp_fault = 0; + } else { + *g_exp_fault = 1; + } + } + return; } +// ----------------------------------------------------------------------------- diff --git a/cv32e40s/tests/programs/custom/pma_0reg/README.md b/cv32e40s/tests/programs/custom/pma_0reg/README.md index 188a647772..b843e566b0 100644 --- a/cv32e40s/tests/programs/custom/pma_0reg/README.md +++ b/cv32e40s/tests/programs/custom/pma_0reg/README.md @@ -1,3 +1,3 @@ -Here is a directed test for covering the default PMA behavior when PMA_NUM_REGIONS=0. -When running, the default config (`make` without specifying `CFG=...`) shold be appropriate. -If any defaults are later changed, the important part is that PMA_NUM_REGIONS must be 0. +Directed test for default PMA behavior when PMA_NUM_REGIONS=0. + +Requires `CFG=...` with 0 PMA regions. diff --git a/cv32e40s/tests/programs/custom/pma_0reg/pma_0reg.c b/cv32e40s/tests/programs/custom/pma_0reg/pma_0reg.c index 2b8731ffb2..52188bb231 100644 --- a/cv32e40s/tests/programs/custom/pma_0reg/pma_0reg.c +++ b/cv32e40s/tests/programs/custom/pma_0reg/pma_0reg.c @@ -16,6 +16,7 @@ // SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 #include +#include #include #define ADDR 0x1A110800 // Repurposing the dbg section because it is otherwise not occupied in this test @@ -40,7 +41,7 @@ int main(void) { __asm__ volatile("sw %0, 9(%1)" : "=r"(tmp) : "r"(ADDR)); - // Atomics should pass + // Atomics should pass //TODO:silabs-robin Should _fail_? // Load-reserved should pass /* TODO enable when RTL is implemented diff --git a/cv32e40s/tests/programs/custom/pma_debug/README.md b/cv32e40s/tests/programs/custom/pma_debug/README.md index 54cac9b6dc..b23ef26495 100644 --- a/cv32e40s/tests/programs/custom/pma_debug/README.md +++ b/cv32e40s/tests/programs/custom/pma_debug/README.md @@ -1,2 +1,3 @@ -This is a test for the debug-related aspects of the pma. -Run with CFG on command line `make ... CFG=pma_debug`. +Tests debug-related aspects of the pma. + +Requires `CFG=pma_debug`. diff --git a/cv32e40s/tests/programs/custom/pma_debug/pma_debug.c b/cv32e40s/tests/programs/custom/pma_debug/pma_debug.c index 2fc73952aa..5dcd90a19c 100644 --- a/cv32e40s/tests/programs/custom/pma_debug/pma_debug.c +++ b/cv32e40s/tests/programs/custom/pma_debug/pma_debug.c @@ -17,8 +17,10 @@ #include #include +#include +#include -#define DEBUG_REQ_CONTROL_REG *(volatile int *) CV_VP_DEBUG_CONTROL_BASE) +#define DEBUG_REQ_CONTROL_REG *((volatile int *) CV_VP_DEBUG_CONTROL_BASE) #define DBG_ADDR 0x1A110800 #define IO_ADDR (DBG_ADDR - 16) diff --git a/cv32e40s/tests/programs/custom/pmp/DefaultFull.c b/cv32e40s/tests/programs/custom/pmp/DefaultFull.c new file mode 100644 index 0000000000..871ff10339 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/DefaultFull.c @@ -0,0 +1,48 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +// Feature Description: "can revoke permissions from M-mode, which by default has full permissions" +// Verification Goal: Check that, out of/ after reset, given no extraordinary reset values, and given no change to the pmp csrs, then M-mode has full access permissions. + +#include "pmp.h" +#define RANDOM_REG 0x00800040 + +void default_full() +{ + printf("\n\t--------\n\tDefaultFull test\n"); + + volatile uint32_t temp[64] = {0}; + + // get random address value + __asm__ volatile("lw %0, 0(%1)" + : "=r"(temp[63]) + : "r"(RANDOM_REG)); + + // store an arbitrary value to an arbitrary address + store2addr(13, (uint32_t *)temp[63]); + load4addr((uint32_t *)&temp[0], (uint32_t *)temp[63]); + + if (temp[0] == 13) + { + printf("\tDefaultFull pass\n"); + } + else + { + printf("\tRAM values are not as expected\n"); + exit(EXIT_FAILURE); + } +} diff --git a/cv32e40s/tests/programs/custom/pmp/DefaultNone.c b/cv32e40s/tests/programs/custom/pmp/DefaultNone.c new file mode 100644 index 0000000000..8711c1e22f --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/DefaultNone.c @@ -0,0 +1,83 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "pmp.h" + +// Verification Goal: Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then U-mode has no access permissions. +// Feature Description: "PMP can grant permissions to S and U modes, which by default have none" + +void default_none() +{ + uint32_t mcause = 11111; // set an arbitrary value + + printf("\n\t--------\n\tDefaultNone test\n"); + + // execution permission test + umode(); + // this line is supposed to trap + asm volatile("addi t0, t1, 0x12"); // 0x12 as arbitary value + + printf("\tM-mode\n"); + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 1) + { + printf("\tExecution permission pass\n"); + } + else + { + printf("\tExecution permission fail\n"); + exit(EXIT_FAILURE); + } + + // store permission test + umode(); + // this line is supposed to trap + asm volatile("sw t0, 0(t1)"); // to be improve: using a random value to replace t1 + + printf("\tM-mode\n"); + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 1) + { + printf("\tStore permission pass\n"); + } + else + { + printf("\tStore permission fail\n"); + exit(EXIT_FAILURE); + } + + // load permission test + umode(); + // this line is supposed to trap + asm volatile("lw t0, 0(t1)"); // to be improve: using a random value to replace t1 + printf("\tM-mode\n"); + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + + if (mcause == 1) + { + printf("\tLoad permission pass\n"); + } + else + { + printf("\tLoad permission fail\n"); + exit(EXIT_FAILURE); + } + printf("\tDefaultNone pass\n"); +} diff --git a/cv32e40s/tests/programs/custom/pmp/MmodeOnly.c b/cv32e40s/tests/programs/custom/pmp/MmodeOnly.c new file mode 100644 index 0000000000..5ee7831bb2 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/MmodeOnly.c @@ -0,0 +1,234 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "pmp.h" + +// Feature Description: "PMP CSRs are only accessible to M-mode." +// Verification Goal: Try to access any of the pmp CSRs from U-mode, ensure that it always gives "illegal instruction exception" and that the CSRs are not updated. + +void pmpcfgxtest() +{ + volatile uint32_t temp[64] = {0}; + volatile uint32_t pmpcfgx_before_test; + volatile uint32_t pmpcfgx_after_test; + uint32_t mcause = 11111; // set an arbitrary value other than mcause defaults + volatile int illegal_count = 0; + + printf("\n\tU mode pmpcfg test\n"); + + // load content from pmpcfgx and store in variable + asm volatile("csrrs %0, 0x3A9, x0" + : "=r"(pmpcfgx_before_test)); + + // get random value to temp[63] + __asm__ volatile("lw %0, 0(%1)" + : "=r"(temp[63]) + : "r"(RANDOM_REG)); + + // change to Umode and try to write to csr, should trap + umode(); + asm volatile("csrrw x0, 0x3a9, %0" ::"r"(temp[63])); + // trap end the first time + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 2) + { + illegal_count += 1; + } + // change to Umode and try to read to csr, should trap + umode(); + asm volatile("csrrs %0, 0x3a9, x0" + : "=r"(temp[62])); + // trap end the second time + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 2) + { + illegal_count += 1; + } + + printf("\tBack in M mode\n"); + if (illegal_count != 2) + { + printf("\tExpected trap count = 2, but read as %d\n", illegal_count); + exit(EXIT_FAILURE); + } + if (mcause == 2) + { + asm volatile("csrrs %0, 0x3A9, x0" + : "=r"(pmpcfgx_after_test)); + + if (pmpcfgx_after_test != pmpcfgx_before_test) + { + printf("\tpmpcfg value overwritten, test failed\n"); + exit(EXIT_FAILURE); + } + else + { + printf("\tU mode pmpcfg test pass\n"); + } + } + else + { + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + printf("\tmcause read as 0x%lx != 0x2\n", mcause); + exit(EXIT_FAILURE); + } +} + +void pmpaddrxtest() +{ + uint32_t pmpaddrx_before_test; + uint32_t pmpaddrx_after_test; + uint32_t temp[64] = {0}; + uint32_t mcause = 11111; // set an arbitrary value + volatile int illegal_count = 0; + printf("\tU mode pmpaddr test\n"); + + asm volatile("csrrs %0, 0x3Ba, x0\n" + : "=r"(pmpaddrx_before_test)); + + // change to Umode and try to write to csr, should trap + umode(); + asm volatile("csrrw x0, 0x3ba, %0" ::"r"(temp[63])); + // trap end the first time + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 2) + { + illegal_count += 1; + } + // change to Umode and try to read to csr, should trap + umode(); + asm volatile("csrrs %0, 0x3ba, x0" + : "=r"(temp[62])); + // trap end the second time + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 2) + { + illegal_count += 1; + } + + printf("\tM-mode\n"); + if (illegal_count != 2) + { + printf("\tExpected trap count = 2, but read as %d\n", illegal_count); + exit(EXIT_FAILURE); + } + if (mcause == 2) + { + asm volatile("csrrs %0, 0x3Ba, x0" + : "=r"(pmpaddrx_after_test)); + if (pmpaddrx_before_test != pmpaddrx_after_test) + { + printf("\tpmpaddr value overwritten, test failed\n"); + exit(EXIT_FAILURE); + } + else + { + printf("\tU mode pmpaddr test pass\n"); + } + } + else + { + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + printf("\tmcause read as 0x%lx != 0x2\n", mcause); + exit(EXIT_FAILURE); + } +} + +void mseccfgtest() +{ + uint32_t mseccfg_before_test; + uint32_t mseccfg_after_test; + uint32_t temp[64] = {0}; + uint32_t mcause = 11111; // set an arbitrary value + volatile int illegal_count = 0; + // read the mseccfg(0x747) value before test and then to compare + printf("\tU mode mseccfg check\n"); + asm volatile("csrrs %0, 0x747, x0" + : "=r"(mseccfg_before_test)); + + // change to Umode and try to write to csr, should trap + umode(); + asm volatile("csrrs x0, 0x747, %0" ::"r"(temp[63])); + // trap end the first time + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 2) + { + illegal_count += 1; + } + // change to Umode and try to read to csr, should trap + umode(); + asm volatile("csrrs %0, 0x747, x0" + : "=r"(temp[62])); + // trap end the second time + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 2) + { + illegal_count += 1; + } + + printf("\tM-mode\n"); + if (illegal_count != 2) + { + printf("\tExpected trap count = 2, but read as %d\n", illegal_count); + exit(EXIT_FAILURE); + } + if (mcause == 2) + { + asm volatile("csrrs %0, 0x747, x0" + : "=r"(mseccfg_after_test)); + if (mseccfg_after_test != mseccfg_before_test) + { + printf("\tmseccfg values overwritten, test failed\n"); + exit(EXIT_FAILURE); + } + else + { + printf("\tU mode mseccfg test pass\n"); + } + } + else + { + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + printf("\tmcause read as 0x%lx != 0x2\n", mcause); + exit(EXIT_FAILURE); + } +} + +void mmode_only() +{ + printf("\n\t--------\n\tMmodeOnly test\n"); + // set pmp addr to 0xffff-ffff + asm volatile( + "li t0, 0xFFFFFFFF\n" + "csrrw x0, pmpaddr0, t0\n" + "li t0, 0xf\n" + "csrrw x0, 0x3a0, t0\n"); + + pmpcfgxtest(); + pmpaddrxtest(); + mseccfgtest(); + printf("\tMmodeOnly test pass\n"); +} diff --git a/cv32e40s/tests/programs/custom/pmp/README.md b/cv32e40s/tests/programs/custom/pmp/README.md new file mode 100644 index 0000000000..1f3250f58e --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/README.md @@ -0,0 +1,21 @@ + + + +This folder has direct tests for default PMP behavior when PMP_NUM_REGIONS=64. + +`make <...> CFG=pmp`. diff --git a/cv32e40s/tests/programs/custom/pmp/ResetRegisters.c b/cv32e40s/tests/programs/custom/pmp/ResetRegisters.c new file mode 100644 index 0000000000..41fa1a2964 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/ResetRegisters.c @@ -0,0 +1,60 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +// Feature Description: "Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers’ A and L fields." +// Verification Goal: Read the A and L values right after reset, check that the default reset values are 0. Note: Should also be visible on rvfi without specifically using csr instructions. +// extended test is to read all 8 bits for pmpxcfg + +#include "pmp.h" + +#define PMPCFGX 16 + +void reset_registers() +{ + printf("\n\t--------\n\tResetRegisters test\n"); + uint32_t pmpcfg[PMPCFGX]; + + // read out pmpcfg register values with given address from 0x3a - 0x3af + __asm__ volatile("csrr %0, 0x3A0" : "=r"(pmpcfg[0])); + __asm__ volatile("csrr %0, 0x3A1" : "=r"(pmpcfg[1])); + __asm__ volatile("csrr %0, 0x3A2" : "=r"(pmpcfg[2])); + __asm__ volatile("csrr %0, 0x3A3" : "=r"(pmpcfg[3])); + __asm__ volatile("csrr %0, 0x3A4" : "=r"(pmpcfg[4])); + __asm__ volatile("csrr %0, 0x3A5" : "=r"(pmpcfg[5])); + __asm__ volatile("csrr %0, 0x3A6" : "=r"(pmpcfg[6])); + __asm__ volatile("csrr %0, 0x3A7" : "=r"(pmpcfg[7])); + __asm__ volatile("csrr %0, 0x3A8" : "=r"(pmpcfg[8])); + __asm__ volatile("csrr %0, 0x3A9" : "=r"(pmpcfg[9])); + __asm__ volatile("csrr %0, 0x3Aa" : "=r"(pmpcfg[10])); + __asm__ volatile("csrr %0, 0x3Ab" : "=r"(pmpcfg[11])); + __asm__ volatile("csrr %0, 0x3Ac" : "=r"(pmpcfg[12])); + __asm__ volatile("csrr %0, 0x3Ad" : "=r"(pmpcfg[13])); + __asm__ volatile("csrr %0, 0x3Ae" : "=r"(pmpcfg[14])); + __asm__ volatile("csrr %0, 0x3Af" : "=r"(pmpcfg[15])); + + // check for the specific bits + for (int i = 0; i < PMPCFGX; i++) + { + if (pmpcfg[i] != 0) + { + printf("\n\tERROR: pmpcfg[%d] read as 0x%x != 0x0, test failed\n", i, (unsigned int)pmpcfg[i]); + exit(EXIT_FAILURE); + } + } + + printf("\tResetRegisters pass\n"); +} diff --git a/cv32e40s/tests/programs/custom/pmp/TorNomatch.c b/cv32e40s/tests/programs/custom/pmp/TorNomatch.c new file mode 100644 index 0000000000..6c73bfdb47 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/TorNomatch.c @@ -0,0 +1,138 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "pmp.h" + +// Feature Description: "If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses." +// Verification Goal: Set up tor regions where the addresses are not in increasing order, try accesses on or within the designated "reverse" regions, ensure that they are treated as if there is no match. + +void tor_nomatch() +{ + volatile uint32_t temp[64] = {0}; + uint32_t mcause = 11111; + uint32_t upperaddr; + uint32_t loweraddr; + uint32_t res0; + uint32_t res1; + + + printf("\n\t--------\n\tTorNomatch test\n"); + + + // Init + + // to make sure temp values are not the same. + for (int i = 0; i < 64; i++) + { + temp[i] = i + 1; + } + + // designate "orderly" region up through first half of "temp[]", "torXWR" + upperaddr = ((uint32_t)(&temp[31])) >> 2; + loweraddr = 0; + asm volatile("csrw pmpaddr4, %0" : : "r"(upperaddr)); + asm volatile("csrw pmpaddr3, %0" : : "r"(loweraddr)); + asm volatile("csrw pmpcfg1, %0" : : "r"(0xF)); // Entry 4 + + // designate "reverse" region for second half of "temp[]", "torXWR" + upperaddr = ((uint32_t)(&temp[32])) >> 2; // Upper addr is "below" lower addr + loweraddr = ((uint32_t)(&temp[63])) >> 2; + asm volatile("csrw pmpaddr1, %0" ::"r"(upperaddr)); + asm volatile("csrw pmpaddr0, %0" ::"r"(loweraddr)); + asm volatile("csrw pmpcfg0, %0" ::"r"(0xF00)); // Entry 1 + + // designate "orderly" region after second half of "temp[]" and up, "torXWR" + upperaddr = 0xFFFFffff; + loweraddr = ((uint32_t)(&temp[64])) >> 2; + __asm__ volatile("csrw 0x3EF, %0" : : "r"(upperaddr)); // 0x3EF=pmpaddr63 + __asm__ volatile("csrw 0x3EE, %0" : : "r"(loweraddr)); + __asm__ volatile("csrw 0x3AF, %0" : : "r"(0x0f000000)); // TOR+XWR on entry 63, 0x3AF=pmpcfg15 + + + // try to access orderly region + + glb_csrs.mcause = 0; + + umode(); + asm volatile("nop"); + if (glb_csrs.mcause) { + printf("\n\t unexpected trap, in 'orderly' test after umode\n"); + exit(EXIT_FAILURE); + } + + store2addr(13, (uint32_t *)&temp[1]); + if (glb_csrs.mcause) { + printf("\n\t store should not except\n"); + exit(EXIT_FAILURE); + } + load4addr((uint32_t *)&temp[2], (uint32_t *)&temp[1]); + if (glb_csrs.mcause) { + printf("\n\t loadstore should not except\n"); + exit(EXIT_FAILURE); + } + + // to trap and bring back to M mode + asm volatile("ecall"); + if (glb_csrs.mcause != 8) { // Environment call from U-Mode (ECALL) + printf("\n\t unexpected trap, in 'orderly' test after ecall\n"); + exit(EXIT_FAILURE); + } + + // to read from 0xfff1 + if (temp[0] == temp[1]) { + printf("\n\t badly initialized test, temp0==temp1\n"); + exit(EXIT_FAILURE); + } + asm volatile("lw %0, 0(%1)" + : "=r"(res0) + : "r"(temp[1])); + asm volatile("lw %0, 0(%1)" + : "=r"(res1) + : "r"(temp[2])); + if (temp[1] == temp[2]) { + printf("\n\t orderly region access test pass "); + printf("\n\t Back in M mode "); + } else { + printf("\n\t 'orderly' test, unexpected results\n"); + exit(EXIT_FAILURE); + } + + + // try to access reversed region 0xffff_ff-0xffff_f + + glb_csrs.mcause = 0; + + umode(); + asm volatile("nop"); + if (glb_csrs.mcause) { + printf("\n\t unexpected trap, in 'reverse' test after umode\n"); + exit(EXIT_FAILURE); + } + + // this should trap and bring to M mode + store2addr(13, (uint32_t *)&temp[33]); + + asm volatile("csrrs %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 7) { // Store/AMO access fault + printf("\n\t reverse region access denied, test pass "); + printf("\n\t Back in M mode "); + } else { + printf("\n\t 'reverse' test, unexpected results\n"); + exit(EXIT_FAILURE); + } +} diff --git a/cv32e40s/tests/programs/custom/pmp/TorZero.c b/cv32e40s/tests/programs/custom/pmp/TorZero.c new file mode 100644 index 0000000000..73c7c7cd34 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/TorZero.c @@ -0,0 +1,80 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "pmp.h" + +// stay away from 0x0-0xFFF, addresses close to your stack pointer, and within 0x1000-0x40_0000 and not 0x1A11_0800-0x1A11_1800 (Debug) +// Feature Description: "If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr0." +// Verification Goal: Configure entry 0 as tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges. + +#define RAMSPACE 0X100000000 +// #define ARBITARY 0XFFFF + +// used to split address, lower half to be included in region0, upper to be included in region1 +uint32_t split_addr[64] = {0}; + +void tor_zero() +{ + // int value = 4; // used to add to value for disdinguishing from 0 + uint32_t mcause = 1111; + uint32_t mepc = 0; + + printf("\n\t--------\n\tTorZero test\n"); + // array split_addr is splitted into region0 and region1 at split_addr[30] + uint32_t out_region0_addr = (uint32_t)(split_addr + 31); + + // designate a range for addr0, out_region0_addr + asm volatile("csrrw x0, 0x3b0, %0" ::"r"(out_region0_addr >> 2)); + asm volatile("csrrw x0, 0x3b1, %0" ::"r"((RAMSPACE >> 2))); + + asm volatile("csrrw x0, 0x3a0, %0" ::"r"(0xf0b)); + + // Try exec outside of region0 (should NOT trap) + // alternative: split_addr[31] = 0x ? ? ? ? ? ? ? ? ; + umode_jmp(&split_addr[31]); + printf("\tback in M mode\n"); + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + asm volatile("csrrw %0, mepc, x0" + : "=r"(mepc)); + if ((mcause == 1) && (mepc != (uint32_t)&split_addr[31])) + { + printf("\toutside region0 access permission test pass\n"); + } + else + { + exit(EXIT_FAILURE); + } + + // Try exec inside of region0 (should trap) + umode(); + asm volatile("nop"); + + printf("\tback in M mode\n"); + asm volatile("csrrw %0, mcause, x0" + : "=r"(mcause)); + if (mcause == 1) + { + printf("\tinside region0 access permission test pass\n"); + } + else + { + exit(EXIT_FAILURE); + } + + // TODO: try different pmpaddr0 sizes +} diff --git a/cv32e40s/tests/programs/custom/pmp/helper.S b/cv32e40s/tests/programs/custom/pmp/helper.S new file mode 100644 index 0000000000..0a4c480fd1 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/helper.S @@ -0,0 +1,103 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +.section .text + +.global change_mode +.global umode +.global umode_jmp + +.global load4addr +.global store2addr + +// changes modes +change_mode: +// changes to User mode +umode: + // set mstatus to U mode + li t0, 0x1800 + // mstatus = 0x300 + csrrc x0, 0x300, t0 + // assing ra to mepc + csrrw x0, 0x341, ra + la a0, umode_msg + jal ra, puts + + // return to next line in main and complete switch to Umode + mret + +// load4addr(int toread/ output, uint32_t addr) +load4addr: +// setup stack + addi sp, sp, -8 + sw ra, 4(sp) + + // write to argument a0 from addr a1 + // load content from address a1 to t0 + lw t0, 0(a1) + // store t0 to address a0 (argument) + sw t0, 0(a0) + +// pop stack + lw ra,4(sp) + addi sp,sp,8 + ret + +// store2addr(int towrite/ input, uint32_t addr) +store2addr: +// setup stack + addi sp, sp, -8 + sw ra, 4(sp) + + // write argument to address + sw a0, 0(a1) + +// pop stack + addi x0, x0, 0 //mret in intr jmps to the next line + lw ra,4(sp) + addi sp,sp,8 + ret + + +// void umode_jmp(uint32_t *addr) +umode_jmp: + csrrw x0, mepc, a0 + + // set mstatus to U mode + li t0, 0x1800 + // mstatus = 0x300 + csrrc x0, 0x300, t0 + + // Put a jump instr in *addr + la t1, myjal + lw t1, 0(t1) + sw t1, 0(a0) + + la t0, myret + mret + +// jumps to myret +myjal: + jalr x0, t0 + +myret: + nop // this line should trap + ret // return to the C file after the umode_jmp + +.section .rodata +umode_msg: + .string "\tU-mode\n" diff --git a/cv32e40s/tests/programs/custom/pmp/intr.c b/cv32e40s/tests/programs/custom/pmp/intr.c new file mode 100644 index 0000000000..6106cf39dc --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/intr.c @@ -0,0 +1,103 @@ +// Copyright 2021 OpenHW Group +// Copyright 2021 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "pmp.h" + +volatile CSRS glb_csrs; // only used for exception check + +// volatile int glb_trap_expected = 0; + +__attribute__((interrupt("machine"))) void u_sw_irq_handler(void) +{ + uint32_t instr_word; + printf("\tu_sw_irq_handler\n"); + __asm__ volatile("csrrs %0, mcause, x0" + : "=r"(glb_csrs.mcause)); + + if (glb_csrs.mcause == 0) + { + printf("\tInstruction address misaligned\n"); + } + else if (glb_csrs.mcause == 1) + { + printf("\tInstruction access fault\n"); + } + else if (glb_csrs.mcause == 2) + { + printf("\tIllegal instruction\n"); + } + else if (glb_csrs.mcause == 3) + { + printf("\tBreakpoint\n"); + } + else if (glb_csrs.mcause == 4) + { + printf("\tLoad address misaligned\n"); + } + else if (glb_csrs.mcause == 5) + { + printf("\tLoad access fault\n"); + } + else if (glb_csrs.mcause == 6) + { + printf("\tStore/AMO address misaligned\n"); + } + else if (glb_csrs.mcause == 7) + { + printf("\tStore/AMO access fault\n"); + } + else if (glb_csrs.mcause == 8) + { + printf("\tEnvironment call from U-Mode (ECALL)\n"); + } + else if (glb_csrs.mcause == 11) + { + printf("\tEnvironment call from M-Mode (ECALL)\n"); + } + else + { + printf("\t(some other mcause reason, %lu)\n", glb_csrs.mcause); + } + + // Increment "mepc" + __asm__ volatile("csrrw %0, mepc, x0" + : "=r"(glb_csrs.mepc)); + instr_word = *(uint32_t *)glb_csrs.mepc; + if ((instr_word & 3) == 3) + { + glb_csrs.mepc += 4; + } + else + { + glb_csrs.mepc += 2; + } + + __asm__ volatile("csrrw x0, mepc, %0" + : + : "r"(glb_csrs.mepc)); + + // Set mmode again + __asm__ volatile("csrrw %0, mstatus, x0" + : "=r"(glb_csrs.mstatus)); + // mstatus |= (3 << 11); + glb_csrs.mstatus = 0x1800; + __asm__ volatile("csrrw x0, mstatus, %0" + : + : "r"(glb_csrs.mstatus)); + + return; +} diff --git a/cv32e40s/tests/programs/custom/pmp/pmp.c b/cv32e40s/tests/programs/custom/pmp/pmp.c new file mode 100644 index 0000000000..6baf21fe61 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/pmp.c @@ -0,0 +1,35 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "pmp.h" + +int main(int argc, char *argv[]) +{ + // out of reset tests + reset_registers(); + default_full(); + default_none(); + + // First time changing CSRs + mmode_only(); + + // matching tests have sticky bits + tor_zero(); + tor_nomatch(); + + exit(EXIT_SUCCESS); +} diff --git a/cv32e40s/tests/programs/custom/pmp/pmp.h b/cv32e40s/tests/programs/custom/pmp/pmp.h new file mode 100644 index 0000000000..40225c84fb --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp/pmp.h @@ -0,0 +1,73 @@ +// Copyright 2022 OpenHW Group +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#ifndef PMP_H +#define PMP_H + +#include +#include +#include +#include +#include + +#define RANDOM_REG 0x00800040 + +// vplan tests +void reset_registers(); +void default_full(); +void default_none(); +void mmode_only(); +void napot_matching(); +void tor_macthing(); +void tor_zero(); +void tor_nomatch(); +void tor_nomatch(); + +// helper +void change_mode(); +void umode(); +void load4addr(uint32_t *output_addr, uint32_t *addr); +void store2addr(int input, uint32_t *addr); +uint32_t lcg_parkmiller(uint32_t *state); +void umode_jmp(uint32_t *addr); + +typedef struct CSRS_STUCT +{ + // Machine Status (lower 32 bits). 0x300 + volatile uint32_t mstatus; + + // PMP Configuration (pmpcfg0-pmpcfg15) + // CSR Address: 0x3A0 - 0x3AF, 32bit each + volatile uint32_t *pmpcfgx; + + // PMP Address (pmpaddr0 - pmpaddr63) 64 in total + // CSR Address: 0x3B0 - 0x3EF + volatile uint32_t *pmpaddrx; + volatile uint32_t mcause; + volatile uint32_t mepc; + // low 32bits + volatile uint32_t mseccfg; + // high 32bits + volatile uint32_t mseccfgh; +} CSRS; + +// globals +extern volatile CSRS glb_csrs; +// flag to check exception +extern volatile int glb_trap_expected; + +#endif diff --git a/cv32e40x/tests/programs/custom/fencei/test.yaml b/cv32e40s/tests/programs/custom/pmp/test.yaml similarity index 58% rename from cv32e40x/tests/programs/custom/fencei/test.yaml rename to cv32e40s/tests/programs/custom/pmp/test.yaml index b9484668ae..f95f6397ce 100644 --- a/cv32e40x/tests/programs/custom/fencei/test.yaml +++ b/cv32e40s/tests/programs/custom/pmp/test.yaml @@ -1,4 +1,4 @@ -name: fencei +name: pmp uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > - Simple fencei sanity test + Directed tests for the PMP. diff --git a/cv32e40s/tests/programs/custom/pmp_csr_access_test/pmp_csr_access_test.c b/cv32e40s/tests/programs/custom/pmp_csr_access_test/pmp_csr_access_test.c new file mode 100644 index 0000000000..9ae82039c1 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp_csr_access_test/pmp_csr_access_test.c @@ -0,0 +1,431 @@ +// +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran +// +// PMP CSR access test +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 2 +// Set which test index to start testing at (for quickly running specific tests during development) +#define START_TEST_IDX 0 + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + +typedef union { + struct { + volatile uint32_t opcode : 7; + volatile uint32_t rd : 5; + volatile uint32_t funct3 : 3; + volatile uint32_t rs1_uimm : 5; + volatile uint32_t csr : 12; + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) csr_instr_t; + +// Matches funct3 values for CSR instructions +typedef enum { + CSRRW = 1, + CSRRS = 2, + CSRRC = 3, + CSRRWI = 5, + CSRRSI = 6, + CSRRCI = 7 +} csr_instr_access_t; + +typedef enum { + PMPMODE_OFF = 0, + PMPMODE_TOR = 1, + PMPMODE_NA4 = 2, + PMPMODE_NAPOT = 3 +} pmp_mode_t; + +// --------------------------------------------------------------- +// Convenience macros for bit fields +// --------------------------------------------------------------- +#define OPCODE_SYSTEM 0x73 +#define PMPCFG_BASE 0x3a0 +#define PMPADDR_BASE 0x3b0 +#define MSECCFG_BASE 0x747 + +// Verbosity levels (Akin to the uvm verbosity concept) +typedef enum { + V_OFF = 0, + V_LOW = 1, + V_MEDIUM = 2, + V_HIGH = 3, + V_DEBUG = 4 +} verbosity_t; + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +volatile uint32_t * volatile g_csr_instr; +volatile uint32_t * volatile g_csr_instr_rd_val; +volatile uint32_t * volatile g_csr_instr_rs1_val; +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t pmp_write_addr_regs(uint32_t index, uint8_t report_name); +uint32_t pmp_write_cfg_regs(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...); + +/* + * call_word_instr + * + * Sets up the system to execute a 32bit word as an instruction + * and return to the regular execution flow + */ +void call_word_instr(uint32_t instr_word); + +/* + * csr_instr + * + * Execute a csr access instruction + * + * - funct3: CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI + * - addr: csr register address (numeric) + * - rs1_uimm_val: rs1/uimm _value_ to supply to instruction + * - return value contains value read from csr + * + */ +uint32_t csr_instr(csr_instr_access_t funct3, uint32_t addr, uint32_t rs1_uimm_val); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + g_csr_instr = calloc(1, sizeof(uint32_t)); + g_csr_instr_rd_val = calloc(1, sizeof(uint32_t)); + g_csr_instr_rs1_val = calloc(1, sizeof(uint32_t)); + + // Add function pointers to new tests here + tests[0] = pmp_write_addr_regs; + tests[1] = pmp_write_cfg_regs; + + // Run all tests in list above + cvprintf(V_LOW, "\nPMP CSR Test start\n\n"); + for (volatile int i = START_TEST_IDX; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + free((void *)g_csr_instr ); + free((void *)g_csr_instr_rd_val ); + free((void *)g_csr_instr_rs1_val ); + return retval; // Nonzero for failing tests +} + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_IDX; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) call_word_instr(uint32_t instr_word){ + __asm__ volatile ( R"( + .global ptr_loc + addi sp, sp, -8 + sw a0, 0(sp) + sw s0, 4(sp) + + la s0, ptr_loc + sw a0, 0(s0) + fence.i + # ensure that we have a location to write our pointer + ptr_loc: .word(0x00000000) + + lw s0, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + ret + )"); +} + +// ----------------------------------------------------------------------------- + +uint32_t csr_instr(csr_instr_access_t funct3, uint32_t addr, uint32_t rs1_uimm_val) { + volatile csr_instr_t csr_instr = { 0 }; + + *g_csr_instr_rd_val = 0; + *g_csr_instr_rs1_val = rs1_uimm_val; + + switch (funct3) { + case CSRRW: + case CSRRS: + case CSRRC: + csr_instr = (csr_instr_t){ + .fields.opcode = OPCODE_SYSTEM, + .fields.rd = 11, // a1 reg + .fields.funct3 = funct3, + .fields.rs1_uimm = (rs1_uimm_val == 0) ? 0 : 12, // a2 reg unless zero specified + .fields.csr = addr + }; + break; + case CSRRWI: + case CSRRSI: + case CSRRCI: + csr_instr = (csr_instr_t){ + .fields.opcode = OPCODE_SYSTEM, + .fields.rd = 11, // a1 reg + .fields.funct3 = funct3, + .fields.rs1_uimm = rs1_uimm_val, + .fields.csr = addr + }; + break; + default: return 0; + } + + *g_csr_instr = csr_instr.raw; + + __asm__ volatile ( R"( + addi sp, sp, -16 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw ra, 12(sp) + + lw a0, g_csr_instr + lw a0, 0(a0) + lw a2, g_csr_instr_rs1_val + lw a2, 0(a2) + jal ra, call_word_instr + lw a2, g_csr_instr_rd_val + sw a1, 0(a2) + + lw ra, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 16 + )"); + + return *g_csr_instr_rd_val; +} + +// ----------------------------------------------------------------------------- + +uint32_t pmp_write_addr_regs(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + for (int i = 0; i < 64; i++) { + (void)csr_instr(CSRRW, PMPADDR_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRW, PMPADDR_BASE + i, 0x00000000UL); + (void)csr_instr(CSRRS, PMPADDR_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRC, PMPADDR_BASE + i, 0xffffffffUL); + test_fail = 63 - i; // fail test if we somehow did not run through the entire loop + } + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t pmp_write_cfg_regs(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Set rlb in mseccfg to enable us to revert changes to pmp regions + (void)csr_instr(CSRRS, MSECCFG_BASE, 4UL); + + // Set all addr regs to top of memory (unused) to avoid lockout + for (int i = 0; i < 64; i++) { + (void)csr_instr(CSRRW, PMPADDR_BASE + i, 0xffffffffUL); + } + + // Set/clear all cfg reg bits to 1 + for (int i = 0; i < 16; i++) { + (void)csr_instr(CSRRW, PMPCFG_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRW, PMPCFG_BASE + i, 0x00000000UL); + (void)csr_instr(CSRRS, PMPCFG_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRC, PMPCFG_BASE + i, 0xffffffffUL); + test_fail = 15 - i; // fail test if we somehow did not run through the entire loop + } + + // Clear all addr reg bits + for (int i = 0; i < 64; i++) { + (void)csr_instr(CSRRCI, PMPADDR_BASE + i, 0x00000000UL); + } + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + diff --git a/cv32e40s/tests/programs/custom/pmp_csr_access_test/test.yaml b/cv32e40s/tests/programs/custom/pmp_csr_access_test/test.yaml new file mode 100644 index 0000000000..9c31162c82 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp_csr_access_test/test.yaml @@ -0,0 +1,7 @@ +name: pmp_csr_access_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + PMP csr access directed test +plusargs: > +cflags: > + -mno-relax diff --git a/cv32e40s/tests/programs/custom/privilege_test/README.md b/cv32e40s/tests/programs/custom/privilege_test/README.md new file mode 100644 index 0000000000..a9455e4849 --- /dev/null +++ b/cv32e40s/tests/programs/custom/privilege_test/README.md @@ -0,0 +1,3 @@ +Tests checking privilege mode (U and M) accesses and csr behavior. + +Needs `CFG=pmp` for allowing U-mode to run. diff --git a/cv32e40s/tests/programs/custom/privilege_test/privilege_test.S b/cv32e40s/tests/programs/custom/privilege_test/privilege_test.S new file mode 100644 index 0000000000..e131c2a78c --- /dev/null +++ b/cv32e40s/tests/programs/custom/privilege_test/privilege_test.S @@ -0,0 +1,73 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly functions to help the tests in the privilege_tests.c source file. +** +******************************************************************************* +*/ + + +.section .text + + +// imported variable +.global reg_input + +// Functions +.global change_exec_mode +.global setup_pmp +.global set_u_mode + + +change_exec_mode: + // setup the return adress to stack. + addi sp, sp, -4 + // store the ra to the stack pointer. + sw ra, 0(sp) + + // Zero "mstatus" to set MPP=umode + li t0, 0x1800 + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrs x0, mstatus, a0 // set the incoming bits to the mpp. + + // set mepc to point to ecall + la t0, set_ecall //this will pouint to the label below. + csrrw x0, mepc, t0 + + mret // call the mret to execute mode change. + +set_ecall: + ecall // cause an exception + + // return to main + lw ra, 0(sp) + addi sp, sp, 4 + jalr x0, 0(ra) + +setup_pmp: + // Set pmp addr to 0xFFFF_FFFF + li t0, 0xFFFFFFFF + csrrw x0, pmpaddr0, t0 + + // Set pmp region TOR and read/write/execute + li t0, ((1 << 3) + (7 << 0)) + csrrw x0, pmpcfg0, t0 + + // Return to caller + jalr x0, 0(ra) + +set_u_mode: // puts the core in usermode. + // Zero "mstatus" to set MPP=umode + li t0, 0x1800 + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrw x0, mepc, ra + mret \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/privilege_test/privilege_test.c b/cv32e40s/tests/programs/custom/privilege_test/privilege_test.c new file mode 100644 index 0000000000..7cd97bc107 --- /dev/null +++ b/cv32e40s/tests/programs/custom/privilege_test/privilege_test.c @@ -0,0 +1,545 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Several tests checking different privilege mode (U and M) accesses and csr behavior. +** +******************************************************************************* +*/ + + +#include +#include +#include +#include "corev_uvmt.h" + + + +// Declaration of assert +static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { + if (actual != expect) { + printf(msg); + printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); + exit(EXIT_FAILURE); + } +} + +/* +Retuns specific bit-field from [bit_indx_low : bit_indx_high] in register x +*/ +unsigned int get_field(unsigned int x, int bit_indx_low, int bit_indx_high){ + int field = ( 1 << ( (bit_indx_high - bit_indx_low) + 1) ) - 1; + x = (x & (field << bit_indx_low) ) >> bit_indx_low; + return x; +} + + + +// Assembly function to setup a generous PMP-region for user mode. +extern volatile void setup_pmp(); +// Assembly function to change privilege-mode based on input (0, 1, 2, 3) +extern volatile void change_exec_mode(int); +// Assembly function to set privilege-mode to user-mode +extern volatile void set_u_mode(); +// global values to hold registers for tests +volatile uint32_t mstatus, mscratchg, mie, mip, mcause; +// MPP bit-field +int MPP_FIELD [2] = {11, 12}; +// Illegal instruction bit-field +int ILL_ACC_FIELD [2] = {0, 1}; +// Tracks the number of trapped executions. +volatile uint32_t NUM_TRAP_EXECUTIONS; + +typedef enum { + + READ_MIP, + EXPECTED_TRAP, + M_MODE_BEH, + MSCRATCH_TEST_BEH, + PRIVILEGE_TEST_BEH, + TRAP_INCR_BEH +} trap_behavior_t; +// trap handler behavior definitions +volatile trap_behavior_t trap_handler_beh; +// standard value for the mstatus register +#define MSTATUS_STD_VAL 0x1800 +// MPRV bit +#define MPRV_BIT 17 +// machine mode bit-code b'11 +#define M_MODE 0x3 +//user mode bit-code b'00 +#define U_MODE 0x0 +// misa.N bit +#define N_BIT 13 +// misa.U bit +#define U_BIT 20 +//XS bit in the mstatus register +#define XS_BIT 15 +//FS bit in the mstatus register +#define FS_BIT 13 +//SD bit in the mstatus register +#define SD_BIT 31 +// misa.SPP bit-field +#define SPP_BIT 18 +// mstatus.TW bit +#define TW_BIT 21 +// mcause ecall code bit-range +#define ECALL_BIT 3 +// mcause instruction access fault bit +#define INSN_ACC_BIT 0 +// mcause instruction access fault code +#define INSN_ACC_CODE 0x2 + + + +/* Checks the mepc for compressed instructions and increments appropriately */ +void increment_mepc(void){ + volatile unsigned int insn, mepc; + + __asm__ volatile("csrrs %0, mepc, x0" : "=r"(mepc)); // read the mepc + __asm__ volatile("lw %0, 0(%1)" : "=r"(insn) : "r"(mepc)); // read the contents of the mepc pc. + if ((insn & 0x3) == 0x3) { // check for compressed instruction before increment. + mepc += 4; + } else { + mepc += 2; + } + __asm__ volatile("csrrw x0, mepc, %0" :: "r"(mepc)); // write to the mepc +} + +// Rewritten interrupt handler +__attribute__ ((interrupt ("machine"))) +void u_sw_irq_handler(void) { + unsigned int mepc, tmstatus; + + switch(trap_handler_beh) { + + + case READ_MIP : // read mip, mie, and move on (6) + __asm__ volatile("csrrs %0, mip, x0" : "=r"(mip)); + __asm__ volatile("csrrs %0, mie, x0" : "=r"(mie)); + + increment_mepc(); + break; + + + case EXPECTED_TRAP : // trapping is expected behavior, increment mepc and move on (5) + increment_mepc(); + break; + + + case M_MODE_BEH : // set Machine mode in the trap handler (4) + __asm__ volatile("csrrs x0, mstatus, %0" :: "r"(MSTATUS_STD_VAL)); + increment_mepc(); + break; + + + case MSCRATCH_TEST_BEH : // mscratch_reliable_check test behavior (2) + __asm__ volatile("csrrs %0, mscratch, x0" : "=r"(mscratchg)); + __asm__ volatile("csrrs x0, mstatus, %0" :: "r"(MSTATUS_STD_VAL)); // set machine mode + increment_mepc(); + break; + + + case PRIVILEGE_TEST_BEH : // privilege_test test behavior (0) + __asm__ volatile("csrrs %0, mcause, x0" : "=r"(mcause)); // read the mcause register + __asm__ volatile("csrrs %0, mstatus, x0" : "=r"(mstatus)); // read the mstatus register + __asm__ volatile("csrrs x0, mstatus, %0" :: "r"(MSTATUS_STD_VAL)); // set machine mode + increment_mepc(); + break; + + + case TRAP_INCR_BEH : // csr_privilege_loop behavior (1) + NUM_TRAP_EXECUTIONS += 1; + increment_mepc(); + break; + } + +} + +/* Changes the handler functionality, and then calls an exception to change into m-mode. */ +void set_m_mode(void) { + trap_handler_beh = M_MODE_BEH; + __asm__ volatile("ecall"); +} + + + +/* + * Loops through the different spec modes (00, 01, 10, 11) and asserts that only the implemented modes User (00) and Machine (11) are entered. + * vplan:SupportedLevels + */ +void privilege_test(void){ + int input_mode = 0; + trap_handler_beh = PRIVILEGE_TEST_BEH; + + for (int i = 0; i <= 3; i++){ + input_mode = i << 11; + + change_exec_mode(input_mode); + uint32_t MPP = get_field(mstatus, MPP_FIELD[0], MPP_FIELD[1]); + if (i == 3) { + assert_or_die(MPP, M_MODE, "error: core did not enter privilege mode as expected\n"); + }else { + assert_or_die(MPP, U_MODE, "error: core did not enter privilege mode as expected\n"); + }; + }; + +} + +/* + * To satisfy the testing criteria this test must run first + * this is to ensure 'Ensure that M-mode is the first mode entered after reset. + * vplan:ResetMode + */ +void reset_mode(void){ + __asm__ volatile("csrrs %0, mstatus, x0" : "=r"(mstatus)); // read the mstatus register + assert_or_die(mstatus, MSTATUS_STD_VAL, "error: core did not enter M-mode after reset\n"); +} + + +/* + * Try all kinds of access to all implemented U- and M-mode CSR registers while in U- and M-mode (cross), ensure appropriate access grant/deny. (Caveat) There is only one register, JVT. + * vplan:??? + */ +void JVT_cross_privilege(void) { + + NUM_TRAP_EXECUTIONS = 0; + trap_handler_beh = TRAP_INCR_BEH; + set_u_mode(); + unsigned int utest; + __asm__ volatile("csrrs %0, 0x017, x0" : "=r"(utest)); // read + __asm__ volatile("csrrw x0, 0x017, %0" :: "r"(utest)); // read-modify-write + __asm__ volatile("csrrs x0, 0x017, %0" :: "r"(utest)); // set + __asm__ volatile("csrrc x0, 0x017, %0" :: "r"(utest)); // clear + __asm__ volatile("csrrw x0, 0x017, %0" :: "r"(utest)); // write again to 'reset' the initial value of the register before moving to another test + assert_or_die(NUM_TRAP_EXECUTIONS, 0, "Some tests seem to have triggered the exception handler, user should have access to this register\n"); + +} + + +/* + * Read misa and assert that "U" bit-field is high and "N" bit-field is low. + * vplan:MisaU + * vplan:MisaN + */ +void misa_check(void) { + + set_m_mode(); + unsigned int misa; + __asm__ volatile("csrrw %0, misa, x0" : "=r"(misa)); + int umode = get_field(misa, U_BIT, U_BIT); + int reserved = get_field(misa, N_BIT, N_BIT); + assert_or_die(umode, 1, "error: User-mode not set in the misa register\n"); + assert_or_die(reserved, 0, "error: N-bit set in the misa register\n"); + +} + + +/* + * F-extension, S-mode are not supported on the platform, FS and XS should therefore be 0, and if both of those are 0 then the SD field should also be 0. + * vplan:UserExtensions + */ +void mstatus_implement_check(void){ + + unsigned int mstatus, XS, FS, SD; + __asm__ volatile("csrrw %0, mstatus, x0" : "=r"(mstatus)); + XS = get_field(mstatus, XS_BIT, XS_BIT); + FS = get_field(mstatus, FS_BIT, FS_BIT); + SD = get_field(mstatus, SD_BIT, SD_BIT); + assert_or_die(XS, 0x0, "error: XS set in the mstatus register\n"); + assert_or_die(FS, 0x0, "error: FS set in the mstatus register\n"); + assert_or_die(SD, 0x0, "error: SD set in the mstatus register\n"); +} + + +/* + * Check that mscratch never changes in U-mode. + * change to u-mode, attempt to write to mscratch, trap and assert that mscratch is the same. + * vplan:MscratchReliable + */ +void mscratch_reliable_check(void){ + + trap_handler_beh = MSCRATCH_TEST_BEH; // set the exception handler behavior. + volatile unsigned int mscratch, + mscratchg = 0; // zero global mscratch value + + __asm__ volatile("csrrs %0, mscratch, x0" : "=r"(mscratch)); + set_u_mode(); + __asm__ volatile("csrrw x0, mscratch, %0" :: "r"(MSTATUS_STD_VAL)); // write to the mscratch (in user mode) (dummy value) + // mscratchg is read from the trap handler. + assert_or_die(mscratch, mscratchg, "error: mscratch register changed after attempted user mode read\n"); + +} + +/* + * Catch-all function for registers which should not exist according to the intern v-plan (Summer 2022) for the cv32e40s core. + * vplan:NExt + * vplan:Mcounteren + * vplan:MedelegMideleg + */ +void csr_should_not_exist_check(void) { + + uint32_t csr_acc, s_mode_bit, misa; + csr_acc = MSTATUS_STD_VAL; // some std value + set_m_mode(); + trap_handler_beh = EXPECTED_TRAP; // sets the behavior of the exception handler. + __asm__ volatile("csrrw %0, misa, x0" : "=r"(misa)); + s_mode_bit = get_field(misa, SPP_BIT, SPP_BIT); + assert_or_die(s_mode_bit, 0, "error: Supervisor-mode should not be set in the misa register\n"); + + + trap_handler_beh = TRAP_INCR_BEH; // setting the trap handler behaviour + NUM_TRAP_EXECUTIONS = 0; // resetting the trap handler count + + //TODO: attempts to Read, Write, Set and Clear all th register + + // mcounteren should exist + __asm__ volatile("csrrs %0, mcounteren, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, mcounteren, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, mcounteren, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, mcounteren, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, mcounteren, %0" : "=r"(csr_acc)); // write the value back + assert_or_die(NUM_TRAP_EXECUTIONS, 0, "error: reading the mcounteren register should not trap in M-mode\n"); + + /*csrrs t0, 0x100, x0 Read + csrrw x0, 0x100, t0 Write + csrrs x0, 0x100, t0 Set + csrrc x0, 0x100, t0 Clear */ + + // mideleg and medeleg register should not be implemented + __asm__ volatile("csrrs %0, mideleg, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, mideleg, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, mideleg, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, mideleg, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, medeleg, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, medeleg, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, medeleg, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, medeleg, %0" : "=r"(csr_acc)); + + + //various N-mode register should not exist anymore. + __asm__ volatile("csrrs %0, ustatus, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, ustatus, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, ustatus, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, ustatus, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, uie, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, uie, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, uie, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, uie, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, utvec, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, utvec, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, utvec, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, utvec, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, uscratch, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, uscratch, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, uscratch, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, uscratch, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, uepc, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, uepc, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, uepc, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, uepc, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, ucause, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, ucause, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, ucause, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, ucause, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, utval, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, utval, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, utval, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, utval, %0" : "=r"(csr_acc)); + + __asm__ volatile("csrrs %0, uip, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw x0, uip, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrs x0, uip, %0" : "=r"(csr_acc)); + __asm__ volatile("csrrc x0, uip, %0" : "=r"(csr_acc)); + + // 10 registers and 4 operations per register + assert_or_die(NUM_TRAP_EXECUTIONS, 40, "error: some of the unimplemented registers did not trap on instrs attempt\n"); +} + +/* + * U-mode interrupts are not supported. The 'zero-bits' in the 'mip' and 'mie' should remain zero. + * vplan:SoftwareInterrupts + */ +void no_u_traps(void) { + unsigned int mask, garb, mipr, mier; + mip = 1; // dummy values for the mip and mie + mie = 1; // these are both read by the trap handler + + mask = 0xF777; // bit_mask for the mip zero-bits + trap_handler_beh = READ_MIP; // set trap handler behaviour + + // Core is expected to trap when u-mode tries to read mstatus + set_u_mode(); + __asm__ volatile("csrrs %0, mstatus, x0" : "=r"(garb)); // illegal read + mip = mip & mask; // And over the Hardcoded zero bit-fields + // mie register is supposed to be 0 + assert_or_die(mie, 0x0, "error: zero-fields in the mier changed after interrrupts\n"); + assert_or_die(mip, 0x0, "error: zero-fields in the mipr changed after interrupts\n"); + +} + + +/* + * Assert that U-mode is set in the MPP after returning from M-mode. + * vplan:MretLeastPrivileged + */ +void proper_ret_priv(void) { + + uint32_t MPP, MPRV; + trap_handler_beh = PRIVILEGE_TEST_BEH; + set_u_mode(); + __asm__ volatile("mret"); + __asm__ volatile("csrrs %0, mstatus, x0" : "=r"(mstatus)); + MPP = get_field(mstatus, MPP_FIELD[0], MPP_FIELD[1]); + assert_or_die(MPP, 0x0, "error: MPP is not set to least privileged mode after executing mret\n"); + MPRV = get_field(mstatus, MPRV_BIT, MPRV_BIT); + assert_or_die(MPRV, 0x0, "error: MPRV is not set to 0 after executing mret\n"); +} + + +/* + * When in U-mode and TW=1 in mstatus, executing a WFI should trap to an illegal exception. + * vplan:WfiIllegal + */ +void check_wfi_trap(void) { + + trap_handler_beh = PRIVILEGE_TEST_BEH; + uint32_t set_tw, pmstatus; + set_tw = 0x200000; // mask for mstatus.TW bit + set_m_mode(); + + //Read add and write back mstatus with the TW bit set high + __asm__ volatile("csrrs %0, mstatus, x0" : "=r"(mstatus)); + pmstatus = mstatus | set_tw; + __asm__ volatile("csrrw x0, mstatus, %0" :: "r"(pmstatus)); + + // Initiate the trap + set_u_mode(); + __asm__ volatile("wfi"); + + //Assert proper mcause + int cause = get_field(mcause, 0, 1); + assert_or_die(cause, 0x2, "error: mcause not showing illegal insn exception after TW WFI trap.\n"); +} + + + +/* + * Be in U-mode, execute ecall, ensure that an exception is taken and mcause is set correctly. + * vplan:Ecall + */ +void correct_ecall(void) { + + trap_handler_beh = PRIVILEGE_TEST_BEH; + uint32_t cause; + set_u_mode(); + __asm__ volatile("ecall"); + cause = get_field(mcause, ECALL_BIT, ECALL_BIT); + // ECALL_BIT is expected to be high (1) + assert_or_die(cause, 1, "error: mcause not showing ecall code after U-mode ecall.\n"); + +} + + +/* + * Be in U-mode, execute MRET, ensure that it does not execute like it does in M-mode: Raise illegal exception, priv mode goes to M and not MPP, MPP becomes U, MPRV is unchanged. + * vplan:Mret + */ +void correct_xret(void) { + + trap_handler_beh = PRIVILEGE_TEST_BEH; + volatile int MPRV_from_M_mode, mcode, MPP, MPRV_from_U_mode; + + //CHeck MPRV bit while in Machine mode + __asm__ volatile("csrrw %0, mstatus, x0" : "=r"(mstatus)); + MPRV_from_M_mode = get_field(mstatus, MPRV_BIT, MPRV_BIT); + + // Call an illegal MRET + set_u_mode(); + __asm__ volatile("mret"); + __asm__ volatile("csrrw %0, mstatus, x0" : "=r"(mstatus)); + + // Get the MPP and MPRV value after the illegal MRET + MPP = get_field(mstatus, MPP_FIELD[0], MPP_FIELD[1]); + MPRV_from_U_mode = get_field(mstatus, MPRV_BIT, MPRV_BIT); + __asm__ volatile("csrrw %0, mcause, x0" : "=r"(mcause)); + mcode = get_field(mcause, ILL_ACC_FIELD[0], ILL_ACC_FIELD[1]); + + // Assert core behaved like vplan expects + assert_or_die(MPRV_from_U_mode, MPRV_from_M_mode, "error: MPRV changed state after illegal mret\n"); + assert_or_die(mcode, INSN_ACC_CODE, "error: mcause did not report illegal instruction\n"); + assert_or_die(MPP, 0x0, "error: MPP not set to U-mode after illegal insn.\n"); + +} + +/* + * Executing uret should give an illegal instruction exception. + * vplan:Uret + */ +void check_uret(){ + trap_handler_beh = PRIVILEGE_TEST_BEH; + uint32_t mcode; + __asm__ volatile("uret"); + mcode = get_field(mcause, ILL_ACC_FIELD[0], ILL_ACC_FIELD[1]); + assert_or_die(mcode, INSN_ACC_CODE, "error: mcause did not report illegal instrunction after 'uret' call\n"); +} + + +/* + * Access to all trigger registers should be illegal while the core is in usermode. + * vplan:TriggersAccess + */ +void access_trigger(){ + trap_handler_beh = TRAP_INCR_BEH; + NUM_TRAP_EXECUTIONS = 0; + uint32_t csr_acc; // dummy value holder + + set_u_mode(); + __asm__ volatile("csrrw %0, tselect, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, tdata1, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, tdata2, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, tdata3, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, etrigger, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, tinfo, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, tcontrol, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, tinfo, x0" : "=r"(csr_acc)); + __asm__ volatile("csrrw %0, tcontrol, x0" : "=r"(csr_acc)); + // there are 9 registers checked + assert_or_die(NUM_TRAP_EXECUTIONS, 9, "error: not all u-mode attempts to access trigger registers trapped\n"); +} + +int main(void){ + + setup_pmp(); + + reset_mode(); + privilege_test(); + // sr_cross_privilege(); // TODO: This test will fail until the JVT-register is implemented. + misa_check(); + mstatus_implement_check(); + mscratch_reliable_check(); + csr_should_not_exist_check(); + no_u_traps(); + proper_ret_priv(); + check_wfi_trap(); + correct_ecall(); + correct_xret(); + check_uret(); + + return EXIT_SUCCESS; +} diff --git a/cv32e40s/tests/programs/custom/privilege_test/test.yaml b/cv32e40s/tests/programs/custom/privilege_test/test.yaml new file mode 100644 index 0000000000..589ef23686 --- /dev/null +++ b/cv32e40s/tests/programs/custom/privilege_test/test.yaml @@ -0,0 +1,4 @@ +name: privilege_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Assortment of tests checking the 32e40s privilege \ No newline at end of file diff --git a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c new file mode 100644 index 0000000000..caca09f4a8 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c @@ -0,0 +1,287 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you +// may not use this file except in compliance with the License, or, at your +// option, the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include +#include +#include + +#include "bsp.h" +#include "corev_uvmt.h" + + +volatile uint32_t g_debug_entered = 0; +volatile uint32_t g_debug_expected = 0; +volatile uint32_t g_debug_function_incr_dpc = 0; +volatile uint32_t g_debug_function_setup_triggers = 0; + +volatile uint32_t g_exception_expected = 0; + +volatile uint32_t g_pushpop_area [32]; + + +__attribute__((interrupt("machine"))) +void u_sw_irq_handler(void){ + if (! g_exception_expected) { + printf("error: exception handler entered unexpectedly\n"); + exit(EXIT_FAILURE); + } + + g_exception_expected = 0; +} + +__attribute__((section(".debugger"), naked)) +void debug_start(void) { + __asm__ volatile (R"( + # Backup "sp", use debug's own stack + csrw dscratch0, sp + la sp, __debugger_stack_start + + # Backup all GPRs + sw a0, -4(sp) + sw a1, -8(sp) + sw a2, -12(sp) + sw a3, -16(sp) + sw a4, -20(sp) + sw a5, -24(sp) + sw a6, -28(sp) + sw a7, -32(sp) + sw t0, -36(sp) + sw t1, -40(sp) + sw t2, -44(sp) + sw t3, -48(sp) + sw t4, -52(sp) + sw t5, -56(sp) + sw t6, -60(sp) + addi sp, sp, -64 + cm.push {ra, s0-s11}, -64 + + # Call the handler actual + call ra, debug_handler + + # Restore all GPRs + cm.pop {ra, s0-s11}, 64 + addi sp, sp, 64 + lw a0, -4(sp) + lw a1, -8(sp) + lw a2, -12(sp) + lw a3, -16(sp) + lw a4, -20(sp) + lw a5, -24(sp) + lw a6, -28(sp) + lw a7, -32(sp) + lw t0, -36(sp) + lw t1, -40(sp) + lw t2, -44(sp) + lw t3, -48(sp) + lw t4, -52(sp) + lw t5, -56(sp) + lw t6, -60(sp) + + # Restore "sp" + csrr sp, dscratch0 + + # Done + dret + )"); +} + +static void setup_triggers(void){ + mcontrol6_t mcontrol6; + uint32_t trigger_addr; + + mcontrol6.raw = 0x00000000; + mcontrol6.fields.load = 1; + mcontrol6.fields.store = 1; + mcontrol6.fields.m = 1; + mcontrol6.fields.match = 0; // (match exact address) + mcontrol6.fields.type = 6; + + trigger_addr = (uint32_t) &(g_pushpop_area[2]); // (arbitrary index) + + __asm__ volatile( + R"( + # Use trigger 0 + csrwi tselect, 0 + + # Disable trigger + csrwi tdata1, 0 + + # Set trigger address + csrw tdata2, %[trigger_addr] + + # Configure trigger + csrw tdata1, %[mcontrol6] + )" + : + : [mcontrol6] "r" (mcontrol6.raw), + [trigger_addr] "r" (trigger_addr) + ); +} + +static void incr_dpc(void){ + uint32_t dpc; + uint32_t instr_word; + + __asm__ volatile( + "csrr %[dpc], dpc" + : [dpc] "=r" (dpc) + ); + + instr_word = *(uint32_t *)dpc; + + if ((instr_word & 0x3) == 0x3) { + dpc += 4; + } else { + dpc += 2; + } + + __asm__ volatile( + "csrw dpc, %[dpc]" + : : [dpc] "r" (dpc) + ); +} + +void debug_handler(void){ + g_debug_entered = 1; + printf("debug handler entered\n"); + + if (! g_debug_expected) { + printf("error: debug entered unexpectedly\n"); + exit(EXIT_FAILURE); + } + g_debug_expected = 0; + + if (g_debug_function_setup_triggers) { + g_debug_function_setup_triggers = 0; + setup_triggers(); + return; + } + if (g_debug_function_incr_dpc) { + g_debug_function_incr_dpc = 0; + incr_dpc(); + return; + } + + printf("error: debug handler function not specified\n"); + exit(EXIT_FAILURE); +} + +__attribute__((naked)) +static void push_debug_trigger(void){ + __asm__ volatile( + R"( + # Save old "sp" + mv t0, sp + + # Setup temporary "sp" + la sp, g_pushpop_area + addi sp, sp, 16 + + # Push to temporary "sp" + cm.push {x1, x8-x9}, -16 + + # Restore old "sp" + mv sp, t0 + + ret + )" + ); +} + +__attribute__((naked)) +static void pop_debug_trigger(void){ + __asm__ volatile( + R"( + # Save old "sp" and GPRs + cm.push {x1, x8-x9}, -16 + mv t0, sp + + # Setup temporary "sp" + la sp, g_pushpop_area + + # Pop from temporary "sp" + cm.pop {x1, x8-x9}, 16 + + # Restore old "sp" and GPRs + mv sp, t0 + cm.pop {x1, x8-x9}, 16 + + ret + )" + ); +} + +static void let_dmode_setup_triggers(void){ + printf("setup trigs\n"); + + g_debug_expected = 1; + g_debug_entered = 0; + g_debug_function_setup_triggers = 1; + + CV_VP_DEBUG_CONTROL = ( + CV_VP_DEBUG_CONTROL_DBG_REQ (1) | + CV_VP_DEBUG_CONTROL_REQ_MODE (1) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION (8) | + CV_VP_DEBUG_CONTROL_START_DELAY (0) + ); + + while (! g_debug_entered) { + ; + } +} + +static void test_push_debug_trigger(void){ + printf("push trigger\n"); + + g_debug_expected = 1; + g_debug_function_incr_dpc = 1; + g_debug_entered = 0; + + push_debug_trigger(); + + if (! g_debug_entered) { + printf("error: push should trigger debug\n"); + exit(EXIT_FAILURE); + } +} + +static void test_pop_debug_trigger(void){ + printf("pop trigger\n"); + + g_debug_expected = 1; + g_debug_function_incr_dpc = 1; + g_debug_entered = 0; + + pop_debug_trigger(); + + if (! g_debug_entered) { + printf("error: pop should trigger debug\n"); + exit(EXIT_FAILURE); + } + + return; +} + +int main(int argc, char **argv){ + let_dmode_setup_triggers(); + test_push_debug_trigger(); + test_pop_debug_trigger(); + + return EXIT_SUCCESS; +} diff --git a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/test.yaml b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/test.yaml new file mode 100644 index 0000000000..f92d937bcb --- /dev/null +++ b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/test.yaml @@ -0,0 +1,5 @@ +name: pushpop_debug_triggers +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +program: pushpop_debug_triggers +description: > + Let Zc push/pop watchpoint triggers cause debug entry. diff --git a/cv32e40s/tests/programs/custom/requested_csr_por/requested_csr_por.c b/cv32e40s/tests/programs/custom/requested_csr_por/requested_csr_por.c index 4d49bd7d62..5de0d2bd68 100644 --- a/cv32e40s/tests/programs/custom/requested_csr_por/requested_csr_por.c +++ b/cv32e40s/tests/programs/custom/requested_csr_por/requested_csr_por.c @@ -30,34 +30,27 @@ #include #include +#include -#define EXP_MISA 0x40101104 +#define EXP_MISA 0x40901104 int main(int argc, char *argv[]) { - // User CSRs - // Not in RM - // unsigned int fflags_rval, frm_rval, fcsr_rval; - // User Custom CSRs - // Not in RM - // unsigned int lpstart0_rval, lpend0_rval, lpcount0_rval, lpstart1_rval, lpend1_rval, lpcount1_rval; - // unsigned int fprec_rval, privlv_rval, uhartid_rval; - // Machine CSRs - unsigned int mstatus_rval, misa_rval, mie_rval, mtvec_rval; - unsigned int mcounteren_rval, mcountinhibit_rval, mphmevent_rval[32]; - unsigned int mscratch_rval, mepc_rval, mcause_rval, mtval_rval, mip_rval; - unsigned int tselect_rval, tdata1_rval, tdata2_rval, tdata3_rval, tinfo_rval; - unsigned int mcontext_rval, scontext_rval, dcsr_rval, dpc_rval, dscratch0_rval, dscratch1_rval; - unsigned int mcycle_rval, minstret_rval, mhpmcounter_rval[32], mcycleh_rval; - unsigned int minstreth_rval, mhpmcounterh[32]; - unsigned int mvendorid_rval, marchid_rval, mimpid_rval, mhartid_rval; + // CSRs + uint32_t mstatus_rval, misa_rval, mie_rval, mtvec_rval; + uint32_t mcounteren_rval, mcountinhibit_rval, mphmevent_rval[32]; + uint32_t mscratch_rval, mepc_rval, mcause_rval, mtval_rval, mip_rval; + uint32_t tselect_rval, tdata1_rval, tdata2_rval, tinfo_rval; + uint32_t mcycle_rval, minstret_rval, mhpmcounter_rval[32], mcycleh_rval; + uint32_t minstreth_rval, mhpmcounterh[32]; + uint32_t mvendorid_rval, marchid_rval, mimpid_rval, mhartid_rval; int err_cnt, sum; err_cnt = 0; sum = 0; - printf("\n\n"); + printf("\n\n"); __asm__ volatile("csrr %0, 0x300" : "=r"(mstatus_rval)); __asm__ volatile("csrr %0, 0x301" : "=r"(misa_rval)); @@ -81,66 +74,56 @@ int main(int argc, char *argv[]) ++err_cnt; } - // This doesn't work because __asm__ is a macro (sigh) - //num = (int)strtol(addr, NULL, 16); - //for (int i=3; i<32; i++) { - // n = sprintf(string, "csrr %%0, 0x%0x", num++); - // printf("%s\n",string); - // __asm__ volatile(string : "=r"(mphmevent_rval[i])); - //} __asm__ volatile("csrr %0, 0x323" : "=r"(mphmevent_rval[3])); - //__asm__ volatile("csrr %0, 0x324" : "=r"(mphmevent_rval[4])); - //__asm__ volatile("csrr %0, 0x325" : "=r"(mphmevent_rval[5])); - //__asm__ volatile("csrr %0, 0x326" : "=r"(mphmevent_rval[6])); - //__asm__ volatile("csrr %0, 0x327" : "=r"(mphmevent_rval[7])); - //__asm__ volatile("csrr %0, 0x328" : "=r"(mphmevent_rval[8])); - //__asm__ volatile("csrr %0, 0x329" : "=r"(mphmevent_rval[9])); - //__asm__ volatile("csrr %0, 0x32A" : "=r"(mphmevent_rval[10])); - //__asm__ volatile("csrr %0, 0x32B" : "=r"(mphmevent_rval[11])); - //__asm__ volatile("csrr %0, 0x32C" : "=r"(mphmevent_rval[12])); - //__asm__ volatile("csrr %0, 0x32D" : "=r"(mphmevent_rval[13])); - //__asm__ volatile("csrr %0, 0x32E" : "=r"(mphmevent_rval[14])); - //__asm__ volatile("csrr %0, 0x32F" : "=r"(mphmevent_rval[15])); - //__asm__ volatile("csrr %0, 0x330" : "=r"(mphmevent_rval[16])); - //__asm__ volatile("csrr %0, 0x331" : "=r"(mphmevent_rval[17])); - //__asm__ volatile("csrr %0, 0x332" : "=r"(mphmevent_rval[18])); - //__asm__ volatile("csrr %0, 0x333" : "=r"(mphmevent_rval[19])); - //__asm__ volatile("csrr %0, 0x334" : "=r"(mphmevent_rval[20])); - //__asm__ volatile("csrr %0, 0x335" : "=r"(mphmevent_rval[21])); - //__asm__ volatile("csrr %0, 0x336" : "=r"(mphmevent_rval[22])); - //__asm__ volatile("csrr %0, 0x337" : "=r"(mphmevent_rval[23])); - //__asm__ volatile("csrr %0, 0x338" : "=r"(mphmevent_rval[24])); - //__asm__ volatile("csrr %0, 0x339" : "=r"(mphmevent_rval[25])); - //__asm__ volatile("csrr %0, 0x33A" : "=r"(mphmevent_rval[26])); - //__asm__ volatile("csrr %0, 0x33B" : "=r"(mphmevent_rval[27])); - //__asm__ volatile("csrr %0, 0x33C" : "=r"(mphmevent_rval[28])); - //__asm__ volatile("csrr %0, 0x33D" : "=r"(mphmevent_rval[29])); - //__asm__ volatile("csrr %0, 0x33E" : "=r"(mphmevent_rval[30])); - //__asm__ volatile("csrr %0, 0x33F" : "=r"(mphmevent_rval[31])); - - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { + __asm__ volatile("csrr %0, 0x324" : "=r"(mphmevent_rval[4])); + __asm__ volatile("csrr %0, 0x325" : "=r"(mphmevent_rval[5])); + __asm__ volatile("csrr %0, 0x326" : "=r"(mphmevent_rval[6])); + __asm__ volatile("csrr %0, 0x327" : "=r"(mphmevent_rval[7])); + __asm__ volatile("csrr %0, 0x328" : "=r"(mphmevent_rval[8])); + __asm__ volatile("csrr %0, 0x329" : "=r"(mphmevent_rval[9])); + __asm__ volatile("csrr %0, 0x32A" : "=r"(mphmevent_rval[10])); + __asm__ volatile("csrr %0, 0x32B" : "=r"(mphmevent_rval[11])); + __asm__ volatile("csrr %0, 0x32C" : "=r"(mphmevent_rval[12])); + __asm__ volatile("csrr %0, 0x32D" : "=r"(mphmevent_rval[13])); + __asm__ volatile("csrr %0, 0x32E" : "=r"(mphmevent_rval[14])); + __asm__ volatile("csrr %0, 0x32F" : "=r"(mphmevent_rval[15])); + __asm__ volatile("csrr %0, 0x330" : "=r"(mphmevent_rval[16])); + __asm__ volatile("csrr %0, 0x331" : "=r"(mphmevent_rval[17])); + __asm__ volatile("csrr %0, 0x332" : "=r"(mphmevent_rval[18])); + __asm__ volatile("csrr %0, 0x333" : "=r"(mphmevent_rval[19])); + __asm__ volatile("csrr %0, 0x334" : "=r"(mphmevent_rval[20])); + __asm__ volatile("csrr %0, 0x335" : "=r"(mphmevent_rval[21])); + __asm__ volatile("csrr %0, 0x336" : "=r"(mphmevent_rval[22])); + __asm__ volatile("csrr %0, 0x337" : "=r"(mphmevent_rval[23])); + __asm__ volatile("csrr %0, 0x338" : "=r"(mphmevent_rval[24])); + __asm__ volatile("csrr %0, 0x339" : "=r"(mphmevent_rval[25])); + __asm__ volatile("csrr %0, 0x33A" : "=r"(mphmevent_rval[26])); + __asm__ volatile("csrr %0, 0x33B" : "=r"(mphmevent_rval[27])); + __asm__ volatile("csrr %0, 0x33C" : "=r"(mphmevent_rval[28])); + __asm__ volatile("csrr %0, 0x33D" : "=r"(mphmevent_rval[29])); + __asm__ volatile("csrr %0, 0x33E" : "=r"(mphmevent_rval[30])); + __asm__ volatile("csrr %0, 0x33F" : "=r"(mphmevent_rval[31])); + + for (int i=3; i<32; i++) { sum += mphmevent_rval[i]; } if (sum) { - //printf("ERROR: CSR MPHMEVENT[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MPHMEVENT[3] not 0x0!\n\n"); + printf("ERROR: CSR MPHMEVENT[3..31] not 0x0!\n\n"); ++err_cnt; } - __asm__ volatile("csrr %0, 0x7A0" : "=r"(tselect_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A1" : "=r"(tdata1_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A2" : "=r"(tdata2_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A3" : "=r"(tdata3_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A4" : "=r"(tinfo_rval)); // unimplemented in model + __asm__ volatile("csrr %0, 0x7A0" : "=r"(tselect_rval)); + __asm__ volatile("csrr %0, 0x7A1" : "=r"(tdata1_rval)); + __asm__ volatile("csrr %0, 0x7A2" : "=r"(tdata2_rval)); + __asm__ volatile("csrr %0, 0x7A4" : "=r"(tinfo_rval)); if (tselect_rval != 0x0) { printf("ERROR: CSR TSELECT not zero!\n\n"); ++err_cnt; } - if (tdata1_rval != 0x28001040) { - printf("ERROR: CSR TDATA1 not 0x28001040!\n\n"); + if (tdata1_rval != 0x28001000) { + printf("ERROR: CSR TDATA1 not 0x28001000!\n\n"); ++err_cnt; } @@ -149,53 +132,11 @@ int main(int argc, char *argv[]) ++err_cnt; } - if (tdata3_rval != 0x0) { - printf("ERROR: CSR TDATA3 not 0x0!\n\n"); + if (tinfo_rval != 0x01008064) { + printf("ERROR: CSR TINFO not 0x01008064!\n\n"); ++err_cnt; } - if (tinfo_rval != 0x4) { - printf("ERROR: CSR TINFO not 0x4!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0x7A8" : "=r"(mcontext_rval)); // unimplemented in model - __asm__ volatile("csrr %0, 0x7AA" : "=r"(scontext_rval)); // unimplemented in model - // IMPERAS - Debug mode enabled - //__asm__ volatile("csrr %0, 0x7B0" : "=r"(dcsr_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B1" : "=r"(dpc_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B2" : "=r"(dscratch0_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B3" : "=r"(dscratch1_rval)); // only accessible in Debug mode - - if (mcontext_rval != 0x0) { - printf("ERROR: CSR MCONTEXT not 0x0!\n\n"); - ++err_cnt; - } - - if (scontext_rval != 0x0) { - printf("ERROR: CSR SCONTEXT not 0x0!\n\n"); - ++err_cnt; - } - - //if (dcsr_rval != 0x0) { - // printf("ERROR: CSR DCSR not 0x0!\n\n"); - // ++err_cnt; - //} - - //if (dpc_rval != 0x0) { - // printf("ERROR: CSR DPC not 0x0!\n\n"); - // ++err_cnt; - //} - - //if (dscratch0_rval != 0x0) { - // printf("ERROR: CSR DSCRATCH0 not 0x0!\n\n"); - // ++err_cnt; - //} - - //if (dscratch1_rval != 0x0) { - // printf("ERROR: CSR DSCRATCH1 not 0x0!\n\n"); - // ++err_cnt; - //} __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_rval)); // CSR unimplemented in the model __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // CSR unimplmented in the model @@ -211,43 +152,41 @@ int main(int argc, char *argv[]) } __asm__ volatile("csrr %0, 0xB03" : "=r"(mhpmcounter_rval[3])); - //__asm__ volatile("csrr %0, 0xB04" : "=r"(mhpmcounter_rval[4])); - //__asm__ volatile("csrr %0, 0xB05" : "=r"(mhpmcounter_rval[5])); - //__asm__ volatile("csrr %0, 0xB06" : "=r"(mhpmcounter_rval[6])); - //__asm__ volatile("csrr %0, 0xB07" : "=r"(mhpmcounter_rval[7])); - //__asm__ volatile("csrr %0, 0xB08" : "=r"(mhpmcounter_rval[8])); - //__asm__ volatile("csrr %0, 0xB09" : "=r"(mhpmcounter_rval[9])); - //__asm__ volatile("csrr %0, 0xB0A" : "=r"(mhpmcounter_rval[10])); - //__asm__ volatile("csrr %0, 0xB0B" : "=r"(mhpmcounter_rval[11])); - //__asm__ volatile("csrr %0, 0xB0C" : "=r"(mhpmcounter_rval[12])); - //__asm__ volatile("csrr %0, 0xB0D" : "=r"(mhpmcounter_rval[13])); - //__asm__ volatile("csrr %0, 0xB0E" : "=r"(mhpmcounter_rval[14])); - //__asm__ volatile("csrr %0, 0xB0F" : "=r"(mhpmcounter_rval[15])); - //__asm__ volatile("csrr %0, 0xB10" : "=r"(mhpmcounter_rval[16])); - //__asm__ volatile("csrr %0, 0xB11" : "=r"(mhpmcounter_rval[17])); - //__asm__ volatile("csrr %0, 0xB12" : "=r"(mhpmcounter_rval[18])); - //__asm__ volatile("csrr %0, 0xB13" : "=r"(mhpmcounter_rval[19])); - //__asm__ volatile("csrr %0, 0xB14" : "=r"(mhpmcounter_rval[20])); - //__asm__ volatile("csrr %0, 0xB15" : "=r"(mhpmcounter_rval[21])); - //__asm__ volatile("csrr %0, 0xB16" : "=r"(mhpmcounter_rval[22])); - //__asm__ volatile("csrr %0, 0xB17" : "=r"(mhpmcounter_rval[23])); - //__asm__ volatile("csrr %0, 0xB18" : "=r"(mhpmcounter_rval[24])); - //__asm__ volatile("csrr %0, 0xB19" : "=r"(mhpmcounter_rval[25])); - //__asm__ volatile("csrr %0, 0xB1A" : "=r"(mhpmcounter_rval[26])); - //__asm__ volatile("csrr %0, 0xB1B" : "=r"(mhpmcounter_rval[27])); - //__asm__ volatile("csrr %0, 0xB1C" : "=r"(mhpmcounter_rval[28])); - //__asm__ volatile("csrr %0, 0xB1D" : "=r"(mhpmcounter_rval[29])); - //__asm__ volatile("csrr %0, 0xB1E" : "=r"(mhpmcounter_rval[30])); - //__asm__ volatile("csrr %0, 0xB1F" : "=r"(mhpmcounter_rval[31])); + __asm__ volatile("csrr %0, 0xB04" : "=r"(mhpmcounter_rval[4])); + __asm__ volatile("csrr %0, 0xB05" : "=r"(mhpmcounter_rval[5])); + __asm__ volatile("csrr %0, 0xB06" : "=r"(mhpmcounter_rval[6])); + __asm__ volatile("csrr %0, 0xB07" : "=r"(mhpmcounter_rval[7])); + __asm__ volatile("csrr %0, 0xB08" : "=r"(mhpmcounter_rval[8])); + __asm__ volatile("csrr %0, 0xB09" : "=r"(mhpmcounter_rval[9])); + __asm__ volatile("csrr %0, 0xB0A" : "=r"(mhpmcounter_rval[10])); + __asm__ volatile("csrr %0, 0xB0B" : "=r"(mhpmcounter_rval[11])); + __asm__ volatile("csrr %0, 0xB0C" : "=r"(mhpmcounter_rval[12])); + __asm__ volatile("csrr %0, 0xB0D" : "=r"(mhpmcounter_rval[13])); + __asm__ volatile("csrr %0, 0xB0E" : "=r"(mhpmcounter_rval[14])); + __asm__ volatile("csrr %0, 0xB0F" : "=r"(mhpmcounter_rval[15])); + __asm__ volatile("csrr %0, 0xB10" : "=r"(mhpmcounter_rval[16])); + __asm__ volatile("csrr %0, 0xB11" : "=r"(mhpmcounter_rval[17])); + __asm__ volatile("csrr %0, 0xB12" : "=r"(mhpmcounter_rval[18])); + __asm__ volatile("csrr %0, 0xB13" : "=r"(mhpmcounter_rval[19])); + __asm__ volatile("csrr %0, 0xB14" : "=r"(mhpmcounter_rval[20])); + __asm__ volatile("csrr %0, 0xB15" : "=r"(mhpmcounter_rval[21])); + __asm__ volatile("csrr %0, 0xB16" : "=r"(mhpmcounter_rval[22])); + __asm__ volatile("csrr %0, 0xB17" : "=r"(mhpmcounter_rval[23])); + __asm__ volatile("csrr %0, 0xB18" : "=r"(mhpmcounter_rval[24])); + __asm__ volatile("csrr %0, 0xB19" : "=r"(mhpmcounter_rval[25])); + __asm__ volatile("csrr %0, 0xB1A" : "=r"(mhpmcounter_rval[26])); + __asm__ volatile("csrr %0, 0xB1B" : "=r"(mhpmcounter_rval[27])); + __asm__ volatile("csrr %0, 0xB1C" : "=r"(mhpmcounter_rval[28])); + __asm__ volatile("csrr %0, 0xB1D" : "=r"(mhpmcounter_rval[29])); + __asm__ volatile("csrr %0, 0xB1E" : "=r"(mhpmcounter_rval[30])); + __asm__ volatile("csrr %0, 0xB1F" : "=r"(mhpmcounter_rval[31])); sum = 0; - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { + for (int i=3; i<32; i++) { sum += mhpmcounter_rval[i]; } if (sum) { - //printf("ERROR: CSR MHPMCOUNTER[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MHPMCOUNTER[3] not 0x0!\n\n"); + printf("ERROR: CSR MHPMCOUNTER[3..31] not 0x0!\n\n"); ++err_cnt; } @@ -266,43 +205,41 @@ int main(int argc, char *argv[]) } __asm__ volatile("csrr %0, 0xB83" : "=r"(mhpmcounterh[3])); - //__asm__ volatile("csrr %0, 0xB84" : "=r"(mhpmcounterh[4])); - //__asm__ volatile("csrr %0, 0xB85" : "=r"(mhpmcounterh[5])); - //__asm__ volatile("csrr %0, 0xB86" : "=r"(mhpmcounterh[6])); - //__asm__ volatile("csrr %0, 0xB87" : "=r"(mhpmcounterh[7])); - //__asm__ volatile("csrr %0, 0xB88" : "=r"(mhpmcounterh[8])); - //__asm__ volatile("csrr %0, 0xB89" : "=r"(mhpmcounterh[9])); - //__asm__ volatile("csrr %0, 0xB8A" : "=r"(mhpmcounterh[10])); - //__asm__ volatile("csrr %0, 0xB8B" : "=r"(mhpmcounterh[11])); - //__asm__ volatile("csrr %0, 0xB8C" : "=r"(mhpmcounterh[12])); - //__asm__ volatile("csrr %0, 0xB8D" : "=r"(mhpmcounterh[13])); - //__asm__ volatile("csrr %0, 0xB8E" : "=r"(mhpmcounterh[14])); - //__asm__ volatile("csrr %0, 0xB8F" : "=r"(mhpmcounterh[15])); - //__asm__ volatile("csrr %0, 0xB90" : "=r"(mhpmcounterh[16])); - //__asm__ volatile("csrr %0, 0xB91" : "=r"(mhpmcounterh[17])); - //__asm__ volatile("csrr %0, 0xB92" : "=r"(mhpmcounterh[18])); - //__asm__ volatile("csrr %0, 0xB93" : "=r"(mhpmcounterh[19])); - //__asm__ volatile("csrr %0, 0xB94" : "=r"(mhpmcounterh[20])); - //__asm__ volatile("csrr %0, 0xB95" : "=r"(mhpmcounterh[21])); - //__asm__ volatile("csrr %0, 0xB96" : "=r"(mhpmcounterh[22])); - //__asm__ volatile("csrr %0, 0xB97" : "=r"(mhpmcounterh[23])); - //__asm__ volatile("csrr %0, 0xB98" : "=r"(mhpmcounterh[24])); - //__asm__ volatile("csrr %0, 0xB99" : "=r"(mhpmcounterh[25])); - //__asm__ volatile("csrr %0, 0xB9A" : "=r"(mhpmcounterh[26])); - //__asm__ volatile("csrr %0, 0xB9B" : "=r"(mhpmcounterh[27])); - //__asm__ volatile("csrr %0, 0xB9C" : "=r"(mhpmcounterh[28])); - //__asm__ volatile("csrr %0, 0xB9D" : "=r"(mhpmcounterh[29])); - //__asm__ volatile("csrr %0, 0xB9E" : "=r"(mhpmcounterh[30])); - //__asm__ volatile("csrr %0, 0xB9F" : "=r"(mhpmcounterh[31])); + __asm__ volatile("csrr %0, 0xB84" : "=r"(mhpmcounterh[4])); + __asm__ volatile("csrr %0, 0xB85" : "=r"(mhpmcounterh[5])); + __asm__ volatile("csrr %0, 0xB86" : "=r"(mhpmcounterh[6])); + __asm__ volatile("csrr %0, 0xB87" : "=r"(mhpmcounterh[7])); + __asm__ volatile("csrr %0, 0xB88" : "=r"(mhpmcounterh[8])); + __asm__ volatile("csrr %0, 0xB89" : "=r"(mhpmcounterh[9])); + __asm__ volatile("csrr %0, 0xB8A" : "=r"(mhpmcounterh[10])); + __asm__ volatile("csrr %0, 0xB8B" : "=r"(mhpmcounterh[11])); + __asm__ volatile("csrr %0, 0xB8C" : "=r"(mhpmcounterh[12])); + __asm__ volatile("csrr %0, 0xB8D" : "=r"(mhpmcounterh[13])); + __asm__ volatile("csrr %0, 0xB8E" : "=r"(mhpmcounterh[14])); + __asm__ volatile("csrr %0, 0xB8F" : "=r"(mhpmcounterh[15])); + __asm__ volatile("csrr %0, 0xB90" : "=r"(mhpmcounterh[16])); + __asm__ volatile("csrr %0, 0xB91" : "=r"(mhpmcounterh[17])); + __asm__ volatile("csrr %0, 0xB92" : "=r"(mhpmcounterh[18])); + __asm__ volatile("csrr %0, 0xB93" : "=r"(mhpmcounterh[19])); + __asm__ volatile("csrr %0, 0xB94" : "=r"(mhpmcounterh[20])); + __asm__ volatile("csrr %0, 0xB95" : "=r"(mhpmcounterh[21])); + __asm__ volatile("csrr %0, 0xB96" : "=r"(mhpmcounterh[22])); + __asm__ volatile("csrr %0, 0xB97" : "=r"(mhpmcounterh[23])); + __asm__ volatile("csrr %0, 0xB98" : "=r"(mhpmcounterh[24])); + __asm__ volatile("csrr %0, 0xB99" : "=r"(mhpmcounterh[25])); + __asm__ volatile("csrr %0, 0xB9A" : "=r"(mhpmcounterh[26])); + __asm__ volatile("csrr %0, 0xB9B" : "=r"(mhpmcounterh[27])); + __asm__ volatile("csrr %0, 0xB9C" : "=r"(mhpmcounterh[28])); + __asm__ volatile("csrr %0, 0xB9D" : "=r"(mhpmcounterh[29])); + __asm__ volatile("csrr %0, 0xB9E" : "=r"(mhpmcounterh[30])); + __asm__ volatile("csrr %0, 0xB9F" : "=r"(mhpmcounterh[31])); sum = 0; - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { + for (int i=3; i<32; i++) { sum += mhpmcounterh[i]; } if (sum) { - //printf("ERROR: CSR MHPMCOUNTERH[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MHPMCOUNTERH[3] not 0x0!\n\n"); + printf("ERROR: CSR MHPMCOUNTERH[3..31] not 0x0!\n\n"); ++err_cnt; } @@ -333,17 +270,17 @@ int main(int argc, char *argv[]) __asm__ volatile("csrr %0, 0x320" : "=r"(mcountinhibit_rval)); - if (mcountinhibit_rval != 0xD) { - printf("ERROR: CSR MCOUNTINHIBIT not 0xD!\n\n"); + if (mcountinhibit_rval != 0x5) { + printf("ERROR: CSR MCOUNTINHIBIT not 0x5!\n\n"); ++err_cnt; } - //__asm__ volatile("csrr %0, 0x306" : "=r"(mcounteren_rval)); // Not currently modeled + __asm__ volatile("csrr %0, 0x306" : "=r"(mcounteren_rval)); - //if (mcounteren_rval != 0x0) { - // printf("ERROR: CSR MCOUNTEREN not 0x0!\n\n"); - // ++err_cnt; - //} + if (mcounteren_rval != 0x0) { + printf("ERROR: CSR MCOUNTEREN not 0x0!\n\n"); + ++err_cnt; + } ///////////////////////////////////////////////////////////////////////////// // These are read last because there should not have been any events which @@ -383,59 +320,41 @@ int main(int argc, char *argv[]) ///////////////////////////////////////////////////////////////////////////// // Print a summary to stdout printf("\nCSR PoR Test\n"); - //printf("\tfflags = 0x%0x\n", fflags_rval); - //printf("\tfrm = 0x%0x\n", frm_rval); - //printf("\tfcsr = 0x%0x\n", fcsr_rval); - //printf("\tlpstart0 = 0x%0x\n", lpstart0_rval); - //printf("\tlpend0 = 0x%0x\n", lpend0_rval); - //printf("\tlpcount0 = 0x%0x\n", lpcount0_rval); - //printf("\tlpstart1 = 0x%0x\n", lpstart1_rval); - //printf("\tlpend1 = 0x%0x\n", lpend1_rval); - //printf("\tlpcount1 = 0x%0x\n", lpcount1_rval); - //printf("\tprivlv = 0x%0x\n", privlv_rval); - //printf("\tuhartid = 0x%0x\n", uhartid_rval); - printf("\tmstatus = 0x%0x\n", mstatus_rval); - printf("\tmisa = 0x%0x\n", misa_rval); - printf("\tmie = 0x%0x\n", mie_rval); - printf("\tmtvec = 0x%0x\n", mtvec_rval); - //printf("\tmcounteren = 0x%0x\n", mcounteren_rval); - printf("\tmcountinhibit = 0x%0x\n", mcountinhibit_rval); - printf("\tmphmevent3 = 0x%0x\n", mphmevent_rval[3]); - //printf("\tmphmevent31 = 0x%0x\n", mphmevent_rval[31]); - printf("\tmscratch = 0x%0x\n", mscratch_rval); - printf("\tmepc = 0x%0x\n", mepc_rval); - printf("\tmcause = 0x%0x\n", mcause_rval); - printf("\tmtval = 0x%0x\n", mtval_rval); - printf("\tmip = 0x%0x\n", mip_rval); - printf("\ttselect = 0x%0x\n", tselect_rval); - printf("\ttdata1 = 0x%0x\n", tdata1_rval); - printf("\ttdata2 = 0x%0x\n", tdata2_rval); - printf("\ttdata3 = 0x%0x\n", tdata3_rval); - printf("\ttinfo = 0x%0x\n", tinfo_rval); - printf("\tmcontext = 0x%0x\n", mcontext_rval); - printf("\tscontext = 0x%0x\n", scontext_rval); - //printf("\tdcsr = 0x%0x\n", dcsr_rval); - //printf("\tdpc = 0x%0x\n", dpc_rval); - //printf("\tdscratch0 = 0x%0x\n", dscratch0_rval); - //printf("\tdscratch1 = 0x%0x\n", dscratch1_rval); - printf("\tmcycle = 0x%0x\n", mcycle_rval); - printf("\tminstret = 0x%0x\n", minstret_rval); - printf("\tmhpmcounter3 = 0x%0x\n", mhpmcounter_rval[3]); - //printf("\tmhpmcounter31 = 0x%0x\n", mhpmcounter_rval[31]); - printf("\tmcycleh = 0x%0x\n", mcycleh_rval); - printf("\tminstreth = 0x%0x\n", minstreth_rval); - printf("\tmhpmcounterh3 = 0x%0x\n", mhpmcounterh[3]); - //printf("\tmhpmcounterh31= 0x%0x\n", mhpmcounterh[31]); - printf("\tmvendorid = 0x%0x\n", mvendorid_rval); - printf("\tmmarchid = 0x%0x\n", marchid_rval); - printf("\tmimpid = 0x%0x\n", mimpid_rval); - printf("\tmhartid = 0x%0x\n", mhartid_rval); - printf("\n\n"); - - if (!err_cnt) { + printf("\tmstatus = 0x%0lx\n", mstatus_rval); + printf("\tmisa = 0x%0lx\n", misa_rval); + printf("\tmie = 0x%0lx\n", mie_rval); + printf("\tmtvec = 0x%0lx\n", mtvec_rval); + printf("\tmcounteren = 0x%0lx\n", mcounteren_rval); + printf("\tmcountinhibit = 0x%0lx\n", mcountinhibit_rval); + printf("\tmphmevent3 = 0x%0lx\n", mphmevent_rval[3]); + printf("\tmphmevent31 = 0x%0lx\n", mphmevent_rval[31]); + printf("\tmscratch = 0x%0lx\n", mscratch_rval); + printf("\tmepc = 0x%0lx\n", mepc_rval); + printf("\tmcause = 0x%0lx\n", mcause_rval); + printf("\tmtval = 0x%0lx\n", mtval_rval); + printf("\tmip = 0x%0lx\n", mip_rval); + printf("\ttselect = 0x%0lx\n", tselect_rval); + printf("\ttdata1 = 0x%0lx\n", tdata1_rval); + printf("\ttdata2 = 0x%0lx\n", tdata2_rval); + printf("\ttinfo = 0x%0lx\n", tinfo_rval); + printf("\tmcycle = 0x%0lx\n", mcycle_rval); + printf("\tminstret = 0x%0lx\n", minstret_rval); + printf("\tmhpmcounter3 = 0x%0lx\n", mhpmcounter_rval[3]); + printf("\tmhpmcounter31 = 0x%0lx\n", mhpmcounter_rval[31]); + printf("\tmcycleh = 0x%0lx\n", mcycleh_rval); + printf("\tminstreth = 0x%0lx\n", minstreth_rval); + printf("\tmhpmcounterh3 = 0x%0lx\n", mhpmcounterh[3]); + printf("\tmhpmcounterh31= 0x%0lx\n", mhpmcounterh[31]); + printf("\tmvendorid = 0x%0lx\n", mvendorid_rval); + printf("\tmmarchid = 0x%0lx\n", marchid_rval); + printf("\tmimpid = 0x%0lx\n", mimpid_rval); + printf("\tmhartid = 0x%0lx\n", mhartid_rval); + printf("\n\n"); + + if (!err_cnt) { return EXIT_SUCCESS; - } else { + } else { return EXIT_FAILURE; - } + } } diff --git a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S index d0cc94486c..14dc76e195 100644 --- a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S +++ b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S @@ -9,7 +9,6 @@ .include "user_define.h" .section .text.start .globl _start -.section .text .type _start, @function @@ -11961,9 +11960,10 @@ mmode_intr_vector_15: j mmode_intr_handler 1: j test_done -.align 2 +.align 7 mtvec_handler: - .option norvc; + .option push + .option norvc j mmode_exception_handler j mmode_intr_vector_1 j mmode_intr_vector_2 @@ -11980,7 +11980,7 @@ mtvec_handler: j mmode_intr_vector_13 j mmode_intr_vector_14 j mmode_intr_vector_15 - .option rvc; + .option pop mmode_exception_handler: csrrw x12, 0x340, x12 diff --git a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/test.yaml b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/test.yaml index a208d186f5..52bed8b970 100644 --- a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/test.yaml +++ b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_0/test.yaml @@ -2,3 +2,4 @@ name: riscv_arithmetic_basic_test_0 uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Basic sanity arithmetic test 0 +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S index cd7b8c5455..4ea2f36d1f 100644 --- a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S +++ b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S @@ -10,7 +10,6 @@ .include "user_define.h" .section .text.start .globl _start -.section .text .type _start, @function _start: @@ -12007,8 +12006,9 @@ mmode_intr_vector_15: j mmode_intr_handler 1: j test_done -.align 2 +.align 7 mtvec_handler: + .option push .option norvc; j mmode_exception_handler j mmode_intr_vector_1 @@ -12026,7 +12026,7 @@ mtvec_handler: j mmode_intr_vector_13 j mmode_intr_vector_14 j mmode_intr_vector_15 - .option rvc; + .option pop mmode_exception_handler: csrrw x15, 0x340, x15 diff --git a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/test.yaml b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/test.yaml index e954a5a9db..055f29ccd2 100644 --- a/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/test.yaml +++ b/cv32e40s/tests/programs/custom/riscv_arithmetic_basic_test_1/test.yaml @@ -2,3 +2,4 @@ name: riscv_arithmetic_basic_test_1 uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > Basic sanity arithmetic test 1 +cflags: -mno-relax diff --git a/cv32e40s/tests/programs/custom/riscv_ebreak_test_0/test.yaml b/cv32e40s/tests/programs/custom/riscv_ebreak_test_0/test.yaml index e0332befd2..1e928dce7c 100644 --- a/cv32e40s/tests/programs/custom/riscv_ebreak_test_0/test.yaml +++ b/cv32e40s/tests/programs/custom/riscv_ebreak_test_0/test.yaml @@ -1,4 +1,5 @@ name: riscv_ebreak_test_0 uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > - Static EBREAK test generated from riscv-dv \ No newline at end of file + Static EBREAK test generated from riscv-dv +cflags: -mno-relax diff --git a/cv32e40x/tests/programs/custom/csr_instructions/test.yaml b/cv32e40s/tests/programs/custom/test_m/test.yaml similarity index 55% rename from cv32e40x/tests/programs/custom/csr_instructions/test.yaml rename to cv32e40s/tests/programs/custom/test_m/test.yaml index 145cde7120..37374a3578 100644 --- a/cv32e40x/tests/programs/custom/csr_instructions/test.yaml +++ b/cv32e40s/tests/programs/custom/test_m/test.yaml @@ -1,4 +1,4 @@ -name: csr_instructions +name: test_m uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > - CSR instruction test + Simple test for M extension. diff --git a/cv32e40s/tests/programs/custom/test_m/test_m.c b/cv32e40s/tests/programs/custom/test_m/test_m.c new file mode 100644 index 0000000000..fad834cb52 --- /dev/null +++ b/cv32e40s/tests/programs/custom/test_m/test_m.c @@ -0,0 +1,205 @@ +// +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran and Ingrid Haahjem +// +// Tests multiplication and division instructions +// +///////////////////////////////////////////////////////////////////////////////// + + +#include +#include +#include + +unsigned int test; + + +int test_mul(void); +int test_mulh(void); +int test_mulhsu(void); +int test_mulhu(void); +int test_div(void); +int test_divu(void); +int test_rem(void); +int test_remu(void); + +int main(int argc, char *argv[]) +{ + int failures=0; + failures += test_mul(); + failures += test_mulh(); + failures += test_mulhsu(); + failures += test_mulhu(); + failures += test_div(); + failures += test_divu(); + failures += test_rem(); + failures += test_remu(); + + if(failures == 0){ + return EXIT_SUCCESS; + } + else { + return EXIT_FAILURE; + } +} + + +int test_mul(void){ + int failures = 0; + + __asm__ volatile("addi t3, zero, 3"); // Store 3 in t3 + __asm__ volatile("addi t4, zero, 2"); // Store 2 in t4 + __asm__ volatile("mul t5, t3, t4"); // Multiply t3 and t4. Store result in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 6 ) { + printf("ERROR, MUL result not as expected\n"); + failures++; + } + + return failures; +} + +int test_mulh(void){ + int failures = 0; + + __asm__ volatile("lui t3, 16"); // Store 16 in the upper 20 bits of t3 + __asm__ volatile("lui t4, 16"); // Store 16 in the upper 20 bits of t4 + __asm__ volatile("mulh t5, t3, t4"); // Multiply st3 and st4 and return the upper 32 bits of the full product. Store result in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 1 ) { + printf("ERROR, MULH result not as expected\n"); + failures++; + } + + return failures; +} + +int test_mulhsu(void){ + int failures = 0; + + __asm__ volatile("lui t3, 16"); // Store 16 in the upper 20 bits of t3 + __asm__ volatile("lui t4, 16"); // Store 16 in the upper 20 bits of t4 + __asm__ volatile("mulhsu t5, t3, t4"); // Multiply st3 and ut4 and return the upper 32 bits of the full product. Store result in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 1 ) { + printf("ERROR, MULHSU result not as expected\n"); + failures++; + } + + return failures; +} + +int test_mulhu(void){ + int failures = 0; + + __asm__ volatile("lui t3, 16"); // Store 16 in the upper 20 bits of t3 + __asm__ volatile("lui t4, 16"); // Store 16 in the upper 20 bits of t4 + __asm__ volatile("mulhu t5, t3, t4"); // Multiply ut3 and ut4 and return the upper 32 bits of the full product. Store result in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 1 ) { + printf("ERROR, MULHU result not as expected\n"); + failures++; + } + + return failures; +} + +int test_div(void){ + int failures = 0; + + __asm__ volatile("addi t3, zero, 4"); // Store 4 in t3 + __asm__ volatile("addi t4, zero, 2"); // Store 2 in t4 + __asm__ volatile("div t5, t3, t4"); // Divide st4 by st3 and store in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 2 ) { + printf("ERROR, DIV result not as expected\n"); + failures++; + } + + return failures; +} + + +int test_divu(void){ + int failures = 0; + + __asm__ volatile("addi t3, zero, 4"); // Store 4 in t3 + __asm__ volatile("addi t4, zero, 2"); // Store 2 in t4 + __asm__ volatile("divu t5, t3, t4"); // Divide ut4 by ut3 and store in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 2 ) { + printf("ERROR, DIVU result not as expected\n"); + failures++; + } + + return failures; +} + +int test_rem(void){ + int failures = 0; + + __asm__ volatile("addi t3, zero, 4"); // Store 4 in t3 + __asm__ volatile("addi t4, zero, 3"); // Store 3 in t4 + __asm__ volatile("rem t5, t3, t4"); // Reminder of st3 divided by st4 and store in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 1 ) { + printf("ERROR, REM result not as expected\n"); + failures++; + } + + return failures; +} + +int test_remu(void){ + int failures = 0; + + __asm__ volatile("addi t3, zero, 4"); // Store 4 in t3 + __asm__ volatile("addi t4, zero, 3"); // Store 3 in t4 + __asm__ volatile("remu t5, t3, t4"); // Reminder of ut3 divided by ut4 and store in t5. + __asm__ volatile("sw t5, test, t0"); // Store t5 to test + + if (test != 1 ) { + printf("ERROR, REMU result not as expected\n"); + failures++; + } + + return failures; +} + + + + + + + + + + + + + + + + diff --git a/cv32e40s/tests/programs/custom/wfe_test/test.yaml b/cv32e40s/tests/programs/custom/wfe_test/test.yaml new file mode 100644 index 0000000000..16aba6e7c6 --- /dev/null +++ b/cv32e40s/tests/programs/custom/wfe_test/test.yaml @@ -0,0 +1,9 @@ +name: wfe_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + WFE directed test +plusargs: > + +clic_irq_clear_on_ack=0 + +gen_wfe_wu_noise=1 +cflags: > + -mno-relax diff --git a/cv32e40s/tests/programs/custom/wfe_test/wfe_test.c b/cv32e40s/tests/programs/custom/wfe_test/wfe_test.c new file mode 100644 index 0000000000..1546f316b7 --- /dev/null +++ b/cv32e40s/tests/programs/custom/wfe_test/wfe_test.c @@ -0,0 +1,884 @@ +// +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran +// +// WFE directed test +// Also includes test for wfi + mstatus.tw = 1 => illegal instruction in U-mode +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 3 +// Set which test index to start testing at (for quickly running specific tests during development) +#define START_TEST_IDX 0 + +#define WFE_INSTR 0x8c000073 + +#define MARCHID_CV32E40X 0x14 +#define MARCHID_CV32E40S 0x15 + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + +typedef union { + struct { + volatile uint32_t uie : 1; // 0 + volatile uint32_t sie : 1; // 1 + volatile uint32_t wpri : 1; // 2 + volatile uint32_t mie : 1; // 3 + volatile uint32_t upie : 1; // 4 + volatile uint32_t spie : 1; // 5 + volatile uint32_t wpri0 : 1; // 6 + volatile uint32_t mpie : 1; // 7 + volatile uint32_t spp : 1; // 8 + volatile uint32_t wpri1 : 2; // 10: 9 + volatile uint32_t mpp : 2; // 12:11 + volatile uint32_t fs : 2; // 14:13 + volatile uint32_t xs : 2; // 16:15 + volatile uint32_t mprv : 1; // 17 + volatile uint32_t sum : 1; // 18 + volatile uint32_t mxr : 1; // 19 + volatile uint32_t tvm : 1; // 20 + volatile uint32_t tw : 1; // 21 + volatile uint32_t tsr : 1; // 22 + volatile uint32_t wpri3 : 8; // 30:23 + volatile uint32_t sd : 1; // 31 + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mstatus_t; + +typedef union { + struct { + volatile uint32_t mml : 1; + volatile uint32_t mmwp : 1; + volatile uint32_t rlb : 1; + volatile uint32_t reserved_31_3 : 29; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} mseccfg_t; + +typedef union { + struct { + volatile uint32_t r : 1; + volatile uint32_t w : 1; + volatile uint32_t x : 1; + volatile uint32_t a : 1; + volatile uint32_t reserved_6_5 : 2; + volatile uint32_t l : 1; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 8; +} __attribute__((packed)) pmpsubcfg_t; + +typedef union { + struct { + volatile uint32_t cfg : 8; + } __attribute__((packed)) volatile reg_idx[4]; + volatile uint32_t raw : 32; +} __attribute__((packed)) pmpcfg_t; + +typedef enum { + PMPMODE_OFF = 0, + PMPMODE_TOR = 1, + PMPMODE_NA4 = 2, + PMPMODE_NAPOT = 3 +} pmp_mode_t; + +// --------------------------------------------------------------- +// Convenience macros for bit fields +// --------------------------------------------------------------- + +// Verbosity levels (Akin to the uvm verbosity concept) +typedef enum { + V_OFF = 0, + V_LOW = 1, + V_MEDIUM = 2, + V_HIGH = 3, + V_DEBUG = 4 +} verbosity_t; + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +volatile uint32_t * volatile g_illegal_instr_exp; +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t wfe_wakeup(uint32_t index, uint8_t report_name); +uint32_t wfe_wakeup_umode(uint32_t index, uint8_t report_name); +uint32_t wfi_mstatus_tw_umode_illegal(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...); + +/* + * set_mseccfg + * + * Sets up mseccfg with the provided + * mseccfg_t object + */ +void set_mseccfg(mseccfg_t mseccfg); + +/* + * set_pmpcfg + * + * Sets up pmp configuration for a given region + * (defined in pmpcfg_t object) + */ +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no); + +/* + * increment_mepc + * + * Increments mepc, + * incr_val 0 = auto detect + * 2 = halfword + * 4 = word + */ +void increment_mepc(volatile uint32_t incr_val); + +/* + * has_pmp_configured + * + * Returns 1 if pmp is enabled/supported else returns 0 + */ +uint32_t has_pmp_configured(void); + +/* + * Non-standard illegal instruction and ecall handlers + */ +void handle_illegal_insn(void); +void handle_ecall(void); +void handle_ecall_u(void); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + g_illegal_instr_exp = calloc(1, sizeof(uint32_t)); + + // Add function pointers to new tests here + tests[0] = wfe_wakeup; + tests[1] = wfe_wakeup_umode; + tests[2] = wfi_mstatus_tw_umode_illegal; + + // Run all tests in list above + cvprintf(V_LOW, "\nWFE Test start\n\n"); + for (volatile int i = START_TEST_IDX; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + free((void *)g_illegal_instr_exp ); + return retval; // Nonzero for failing tests +} + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_IDX; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } +} + +// ----------------------------------------------------------------------------- + +uint32_t has_pmp_configured(void) { + volatile uint32_t pmpaddr0 = 0xffffffff; + volatile uint32_t pmpaddr0_backup = 0; + volatile uint32_t marchid = 0x0; + + __asm__ volatile (R"( + csrrs %[marchid], marchid, zero + )":[marchid] "=r"(marchid)); + + // CV32E40X does not support PMP, skip + switch (marchid) { + case (MARCHID_CV32E40X): + return 0; + break; + case (MARCHID_CV32E40S): + ;; // Do nothing and continue execution + break; + } + + __asm__ volatile (R"( + csrrw %[pmpaddr0_backup] , pmpaddr0, %[pmpaddr0] + csrrw %[pmpaddr0], pmpaddr0, %[pmpaddr0_backup] + )" :[pmpaddr0_backup] "+r"(pmpaddr0_backup), + [pmpaddr0] "+r"(pmpaddr0)); + + return (pmpaddr0 != 0); +} + +// ----------------------------------------------------------------------------- + +void set_mseccfg(mseccfg_t mseccfg){ + + __asm__ volatile ( R"( + csrrs x0, mseccfg, %[cfg_vec] + )" + : + : [cfg_vec] "r"(mseccfg.raw) + :); + + cvprintf(V_DEBUG, "Wrote mseccfg: 0x%08lx\n", mseccfg.raw); +} + +// ----------------------------------------------------------------------------- + +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no){ + volatile pmpcfg_t temp = { 0 }; + volatile pmpcfg_t pmpcfg = { 0 }; + + pmpcfg.reg_idx[reg_no % 4].cfg = pmpsubcfg.raw; + + temp.reg_idx[reg_no % 4].cfg = 0xff; + + switch (reg_no / 4) { + case 0: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg0, t0 + csrrs zero, pmpcfg0, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 1: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg1, t0 + csrrs zero, pmpcfg1, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 2: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg2, t0 + csrrs zero, pmpcfg2, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 3: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg3, t0 + csrrs zero, pmpcfg3, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 4: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg4, t0 + csrrs zero, pmpcfg4, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + case 5: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg5, t0 + csrrs zero, pmpcfg5, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 6: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg6, t0 + csrrs zero, pmpcfg6, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 7: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg7, t0 + csrrs zero, pmpcfg7, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 8: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg8, t0 + csrrs zero, pmpcfg8, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 9: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg9, t0 + csrrs zero, pmpcfg9, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 10: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg10, t0 + csrrs zero, pmpcfg10, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 11: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg11, t0 + csrrs zero, pmpcfg11, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 12: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg12, t0 + csrrs zero, pmpcfg12, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 13: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg13, t0 + csrrs zero, pmpcfg13, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 14: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg14, t0 + csrrs zero, pmpcfg14, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 15: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg15, t0 + csrrs zero, pmpcfg15, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + } + + cvprintf(V_DEBUG, "Set pmpcfg_vector: 0x%08lx\n", pmpcfg.raw); + return; +} + +// ----------------------------------------------------------------------------- + +void increment_mepc(volatile uint32_t incr_val) { + volatile uint32_t mepc = 0; + + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + )" : [mepc] "=r"(mepc)); + + if (incr_val == 0) { + // No increment specified, check *mepc instruction + if (((*(uint32_t *)mepc) & 0x3UL) == 0x3UL) { + // non-compressed + mepc += 4; + } else { + // compressed + mepc += 2; + } + } else { + // explicitly requested increment + mepc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, mepc, %[mepc] + )" :: [mepc] "r"(mepc)); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_ecall(void){ + __asm__ volatile ( R"( + j handle_ecall_u + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_ecall_u(void){ + __asm__ volatile ( R"( + ## handle_ecall_u swaps privilege level, + ## if in M-mode -> mret to U + ## else U-mode -> mret to M + + addi sp, sp, -12 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + + # Get current priv-mode + csrrs a2, mstatus, zero + + # clear out non-mpp bits and set up a2 to update mpp + lui a1, 2 + addi a1, a1, -2048 + and a2, a2, a1 + + # check if we trapped from U or M-mode + beq a1, a2, 1f + j 2f + + # mpp = M-mode -> U-mode + 1: + csrrc zero, mstatus, a1 + j 3f + + # mpp = U-mode -> M-mode + 2: + csrrs zero, mstatus, a1 + + 3: + # Set 0 as argument for increment_mepc + addi a0, zero, 0 + call increment_mepc + + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 12 + + # return to regular bsp handler flow + j end_handler_ret + + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_illegal_insn(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw s0, 0(sp) + sw s1, 4(sp) + + # Decrement *g_illegal_instr_exp + lw s0, g_illegal_instr_exp + lw s1, 0(s0) + addi s1, s1, -1 + sw s1, 0(s0) + + lw s1, 4(sp) + lw s0, 0(sp) + addi sp, sp, 8 + + j end_handler_incr_mepc + )"); +} + +// ----------------------------------------------------------------------------- + +uint32_t wfe_wakeup(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mstatus_t mstatus = { 0 }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + *g_illegal_instr_exp = 0; + + // Execute wfe instructions and wait for wfe noise gen to wake core up + // Expected to be checked by ISS + __asm__ volatile (R"( + #back to back + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + )"::[wfe] "i"(WFE_INSTR)); + + // print string to execute many instructions + cvprintf(V_LOW, "1234567890\n"); + __asm__ volatile (R"( + .word(%[wfe]) + )"::[wfe] "i"(WFE_INSTR)); + + // print another string to execute many instructions + cvprintf(V_LOW, "abcdefghijklmnopqrstuvwxyz\n"); + __asm__ volatile (R"( + .word(%[wfe]) + )"::[wfe] "i"(WFE_INSTR)); + + // Set timeout wait (mstatus.tw) + mstatus.fields.tw = 1; + __asm__ volatile ( R"( + csrrs zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + __asm__ volatile (R"( + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + )"::[wfe] "i"(WFE_INSTR)); + + __asm__ volatile ( R"( + csrrc zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + test_fail = (*g_illegal_instr_exp != 0); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t wfe_wakeup_umode(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile uint32_t pmpaddr = 0xffffffff; + volatile mstatus_t mstatus = { 0 }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Check if there user mode support + if (!has_pmp_configured()) { + cvprintf(V_LOW, "Skipping test: User mode/PMP not supported\n"); + return 0; + } + + // Setup PMP access for u-mode (otherwise all deny) + set_mseccfg((mseccfg_t){ + .fields.mml = 0, + .fields.mmwp = 0, + .fields.rlb = 1, + }); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + __asm__ volatile ( R"( + csrrw zero, pmpaddr0, %[pmpaddr] + )":: [pmpaddr] "r"(pmpaddr)); + + *g_illegal_instr_exp = 0; + __asm__ volatile ( R"( + ecall + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + ecall + # add safe return location + nop + )"::[wfe] "i"(WFE_INSTR)); + + test_fail = (*g_illegal_instr_exp != 0); + + // Set timeout wait (mstatus.tw) + mstatus.fields.tw = 1; + __asm__ volatile ( R"( + csrrs zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + *g_illegal_instr_exp = 6; + __asm__ volatile ( R"( + ecall + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + ecall + # add safe return location + nop + )"::[wfe] "i"(WFE_INSTR)); + + __asm__ volatile ( R"( + csrrc zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + test_fail = (*g_illegal_instr_exp != 0); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t wfi_mstatus_tw_umode_illegal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mstatus_t mstatus = { 0 }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Check if there user mode support + if (!has_pmp_configured()) { + cvprintf(V_LOW, "Skipping test: User mode/pmp not supported\n"); + return 0; + } + + // Set timeout wait (mstatus.tw) + mstatus.fields.tw = 1; + __asm__ volatile ( R"( + csrrs zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + *g_illegal_instr_exp = 6; + __asm__ volatile ( R"( + ecall + wfi + wfi + wfi + wfi + wfi + wfi + ecall + # add safe return location + nop + )":::); + + __asm__ volatile ( R"( + csrrc zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + test_fail = (*g_illegal_instr_exp != 0); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + + +// ----------------------------------------------------------------------------- diff --git a/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c b/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c index b543492552..8a2e247f25 100644 --- a/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c +++ b/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c @@ -1,46 +1,232 @@ +// Copyright 2022 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you +// may not use this file except in compliance with the License, or, at your +// option, the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + #include #include +#include + +#include "bsp.h" -#define CPUADDR_CPUCTRL 0xBF0 -#define CPUADDR_SECURESEED0 0xBF9 -#define CPUADDR_SECURESEED1 0xBFA -#define CPUADDR_SECURESEED2 0xBFC +#define CSRADDR_CPUCTRL 0xBF0 +#define CSRADDR_SECURESEED0 0xBF9 +#define CSRADDR_SECURESEED1 0xBFA +#define CSRADDR_SECURESEED2 0xBFC // Macros for using defines in inline asm #define S(x) #x #define STR(s) S(s) -int main(void) { + +volatile uint32_t g_got_illegal_instruction_exception; +volatile uint32_t g_got_trap; + + +__attribute__((interrupt("machine"))) +void u_sw_irq_handler(void){ + uint32_t exccode; + uint32_t instr_word; + uint32_t mcause; + uint32_t ret_addr; + uint32_t *mepc; + + + // Read CSRs + + __asm__ volatile( + "csrr %[mcause], mcause" + : [mcause] "=r" (mcause) + ); + + exccode = mcause & 0xFFF; + + + // Handle causes + + g_got_trap = 1; + + if (exccode == EXC_CAUSE_ILLEGAL_INSTR) { + g_got_illegal_instruction_exception = 1; + } + + + // Setup mepc + + __asm__ volatile( + "csrr %[mepc], mepc" + : [mepc] "=r" (mepc) + ); + + instr_word = *mepc; + + if ((instr_word & 0x3) == 0x3) { + ret_addr = ((uint32_t)mepc) + 4; + } else { + ret_addr = ((uint32_t)mepc) + 2; + } + + __asm__ volatile( + "csrw mepc, %[ret_addr]" + : : [ret_addr] "r" (ret_addr) + ); + + return; +} + +static void turn_on_dummies(void){ + // "cpuctrl.rnddummy" + __asm__ volatile( "csrrs x0, 0xBF0, 2" ); +} + +static void test_csr_accesses(void) { uint32_t rd; const uint32_t rs1 = 0xFFFFFFFF; printf("Test cpuctrl\n"); - __asm__ volatile("csrr %0, " STR(CPUADDR_CPUCTRL) : "=r"(rd)); - __asm__ volatile("csrwi " STR(CPUADDR_CPUCTRL) ", 0xF"); - __asm__ volatile("csrrs %0, " STR(CPUADDR_CPUCTRL) ", %1" : "=r"(rd) : "r"(rs1)); - __asm__ volatile("csrrc %0, " STR(CPUADDR_CPUCTRL) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrr %0, " STR(CSRADDR_CPUCTRL) : "=r"(rd)); + __asm__ volatile("csrwi " STR(CSRADDR_CPUCTRL) ", 0xF"); + __asm__ volatile("csrrs %0, " STR(CSRADDR_CPUCTRL) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrrc %0, " STR(CSRADDR_CPUCTRL) ", %1" : "=r"(rd) : "r"(rs1)); printf("Test secureseed0\n"); - __asm__ volatile("csrr %0, " STR(CPUADDR_SECURESEED0) : "=r"(rd)); - __asm__ volatile("csrwi " STR(CPUADDR_SECURESEED0) ", 0xF"); - __asm__ volatile("csrrs %0, " STR(CPUADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(rs1)); - __asm__ volatile("csrrc %0, " STR(CPUADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrr %0, " STR(CSRADDR_SECURESEED0) : "=r"(rd)); + __asm__ volatile("csrwi " STR(CSRADDR_SECURESEED0) ", 0xF"); + __asm__ volatile("csrrs %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrrc %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(rs1)); printf("Test secureseed1\n"); - __asm__ volatile("csrr %0, " STR(CPUADDR_SECURESEED1) : "=r"(rd)); - __asm__ volatile("csrwi " STR(CPUADDR_SECURESEED1) ", 0xF"); - __asm__ volatile("csrrs %0, " STR(CPUADDR_SECURESEED1) ", %1" : "=r"(rd) : "r"(rs1)); - __asm__ volatile("csrrc %0, " STR(CPUADDR_SECURESEED1) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrr %0, " STR(CSRADDR_SECURESEED1) : "=r"(rd)); + __asm__ volatile("csrwi " STR(CSRADDR_SECURESEED1) ", 0xF"); + __asm__ volatile("csrrs %0, " STR(CSRADDR_SECURESEED1) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrrc %0, " STR(CSRADDR_SECURESEED1) ", %1" : "=r"(rd) : "r"(rs1)); printf("Test secureseed2\n"); - __asm__ volatile("csrr %0, " STR(CPUADDR_SECURESEED2) : "=r"(rd)); - __asm__ volatile("csrwi " STR(CPUADDR_SECURESEED2) ", 0xF"); - __asm__ volatile("csrrs %0, " STR(CPUADDR_SECURESEED2) ", %1" : "=r"(rd) : "r"(rs1)); - __asm__ volatile("csrrc %0, " STR(CPUADDR_SECURESEED2) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrr %0, " STR(CSRADDR_SECURESEED2) : "=r"(rd)); + __asm__ volatile("csrwi " STR(CSRADDR_SECURESEED2) ", 0xF"); + __asm__ volatile("csrrs %0, " STR(CSRADDR_SECURESEED2) ", %1" : "=r"(rd) : "r"(rs1)); + __asm__ volatile("csrrc %0, " STR(CSRADDR_SECURESEED2) ", %1" : "=r"(rd) : "r"(rs1)); +} - // Test the one particular line that first caught a problem +static void test_previous_issues(void) { + // This particular line has previously caught a problem __asm__ volatile("csrwi 0xBF0, 0x2"); +} + +static void test_lfsr_lockup(void){ + volatile uint32_t zero = 0; + + turn_on_dummies(); + + + // "secureseed0" (Have to copy-paste because csr instr...) + + g_got_trap = 0; + + __asm__ volatile( + "csrrw x0, 0xBF9, %[zero]" + : : [zero] "r" (zero) + ); + + if (g_got_trap) { + printf("error: writing 0 to secureseed0 shouldn't trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed1" + + g_got_trap = 0; + + __asm__ volatile( + "csrrw x0, 0xBFA, %[zero]" + : : [zero] "r" (zero) + ); + + if (g_got_trap) { + printf("error: writing 0 to secureseed1 shouldn't trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed2" + + g_got_trap = 0; + + __asm__ volatile( + "csrrw x0, 0xBFC, %[zero]" + : : [zero] "r" (zero) + ); + + if (g_got_trap) { + printf("error: writing 0 to secureseed2 shouldn't trap\n"); + exit(EXIT_FAILURE); + } + + + // These checks of LFSR lockups could include an additional check that a + // minor alert gets signaled on each lockup. + // (E.g. make a new virtual peripheral for it.) + // It is not done now, as the primary goal is only to close a coverage hole. +} + +static void test_secureseed_rs1_x0(void){ + // "secureseed0" (Have to copy-paste because csr instr...) + + g_got_illegal_instruction_exception = 0; + + __asm__ volatile( "csrrw x0, 0xBF9, x0" ); + + if (g_got_illegal_instruction_exception == 0) { + printf("error: 'secureseed0' access w/ rs1=x0 should trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed1" + + g_got_illegal_instruction_exception = 0; + + __asm__ volatile( "csrrw x0, 0xBFA, x0" ); + + if (g_got_illegal_instruction_exception == 0) { + printf("error: 'secureseed1' access w/ rs1=x0 should trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed2" + + g_got_illegal_instruction_exception = 0; + + __asm__ volatile( "csrrw x0, 0xBFC, x0" ); + + if (g_got_illegal_instruction_exception == 0) { + printf("error: 'secureseed2' access w/ rs1=x0 should trap\n"); + exit(EXIT_FAILURE); + } +} + +int main(void) { + test_csr_accesses(); + test_previous_issues(); + test_lfsr_lockup(); + test_secureseed_rs1_x0(); - printf("Test xsecure_csrs done\n"); + printf("Test 'xsecure_csrs' done\n"); return EXIT_SUCCESS; } diff --git a/cv32e40s/tests/programs/custom/xsecure_test/test.yaml b/cv32e40s/tests/programs/custom/xsecure_test/test.yaml new file mode 100644 index 0000000000..2d631f2569 --- /dev/null +++ b/cv32e40s/tests/programs/custom/xsecure_test/test.yaml @@ -0,0 +1,5 @@ +name: xsecure_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Directed test for xsecure features + Require pmp config because it utilize the mret instruction diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_dut_chk.sv b/cv32e40s/tests/programs/custom/xsecure_test/xsecure_test.S similarity index 50% rename from cv32e40x/tb/uvmt/uvmt_cv32e40x_dut_chk.sv rename to cv32e40s/tests/programs/custom/xsecure_test/xsecure_test.S index 4b7347ae99..c88ef6aeeb 100644 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_dut_chk.sv +++ b/cv32e40s/tests/programs/custom/xsecure_test/xsecure_test.S @@ -1,6 +1,4 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -14,27 +12,32 @@ // See the License for the specific language governing permissions and // limitations under the License. // +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - -`ifndef __UVMT_CV32E40X_DUT_CHK_SV__ -`define __UVMT_CV32E40X_DUT_CHK_SV__ +.section .text -/** - * Module encapsulating assertions for CV32E40X RTL DUT wrapper. - * All ports are SV interfaces. - */ -module uvmt_cv32e40x_dut_chk( - uvma_debug_if debug_if -); +// Functions +.global setup_pmp +.global set_u_mode - `pragma protect begin - // TODO Add assertions to uvmt_cv32e40x_dut_chk +setup_pmp: + // Set pmp addr to 0xFFFF_FFFF + li t0, 0xFFFFFFFF + csrrw x0, pmpaddr0, t0 - `pragma protect end + // Set pmp region TOR and read/write/execute + li t0, ((1 << 3) + (7 << 0)) + csrrw x0, pmpcfg0, t0 -endmodule : uvmt_cv32e40x_dut_chk + // Return to caller + jalr x0, 0(ra) -`endif // __UVMT_CV32E40X_DUT_CHK_SV__ +set_u_mode: // puts the core in usermode. + // Zero "mstatus" to set MPP=umode + li t0, 0x1800 + csrrc x0, mstatus, t0 // clear the mstatus (mpp -> User mode). + csrrw x0, mepc, ra + mret diff --git a/cv32e40s/tests/programs/custom/xsecure_test/xsecure_test.c b/cv32e40s/tests/programs/custom/xsecure_test/xsecure_test.c new file mode 100644 index 0000000000..65d8b2e324 --- /dev/null +++ b/cv32e40s/tests/programs/custom/xsecure_test/xsecure_test.c @@ -0,0 +1,379 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +#ifndef __XSECURE_TEST_H__ +#define __XSECURE_TEST_H__ + +#include +#include +#include +#include "corev_uvmt.h" + +//TODO: functions are copied or based the privilege test code. +//If these functions end up in a common function file, we should adopt this file to use the common functions. + + +#define CSRADDR_CPUCTRL 0xBF0 +#define CSRADDR_SECURESEED0 0xBF9 +#define CSRADDR_SECURESEED1 0xBFA +#define CSRADDR_SECURESEED2 0xBFC +#define CSRADDR_CPUCTRL 0xBF0 +#define CSRADDR_SECURESEED0 0xBF9 +#define CSRADDR_SECURESEED1 0xBFA +#define CSRADDR_SECURESEED2 0xBFC +#define PMPCFG0 0x3A0 +#define PMPADDR0 0x3B0 + + +#define CSRADDR_HPMCOUNTER \ +X("0xC03") \ +X("0xC04") \ +X("0xC05") \ +X("0xC06") \ +X("0xC07") \ +X("0xC08") \ +X("0xC09") \ +X("0xC0A") \ +X("0xC0B") \ +X("0xC0C") \ +X("0xC0D") \ +X("0xC0E") \ +X("0xC0F") \ +X("0xC10") \ +X("0xC11") \ +X("0xC12") \ +X("0xC13") \ +X("0xC14") \ +X("0xC15") \ +X("0xC16") \ +X("0xC17") \ +X("0xC18") \ +X("0xC19") \ +X("0xC1A") \ +X("0xC1B") \ +X("0xC1C") \ +X("0xC1D") \ +X("0xC1E") \ +X("0xC1F") + +#define CSRADDR_HPMCOUNTERH \ +X("0xC83") \ +X("0xC84") \ +X("0xC85") \ +X("0xC86") \ +X("0xC87") \ +X("0xC88") \ +X("0xC89") \ +X("0xC8A") \ +X("0xC8B") \ +X("0xC8C") \ +X("0xC8D") \ +X("0xC8E") \ +X("0xC8F") \ +X("0xC90") \ +X("0xC91") \ +X("0xC92") \ +X("0xC93") \ +X("0xC94") \ +X("0xC95") \ +X("0xC96") \ +X("0xC97") \ +X("0xC98") \ +X("0xC99") \ +X("0xC9A") \ +X("0xC9B") \ +X("0xC9C") \ +X("0xC9D") \ +X("0xC9E") \ +X("0xC9F") + +// macros for using defines in inline asm +#define S(x) #x +#define STR(s) S(s) + +void test_ctrlcpu_and_secureseeds_accessable_in_machine_mode_only(void); +void test_secureseeds_show_zero_at_reads(void); +void csr_should_be_present(void); +void csr_should_not_be_present(void); + +// assembly function to setup a generous PMP-region for user mode. +extern volatile void setup_pmp(); +// assembly function to set privilege-mode to user-mode +extern volatile void set_u_mode(); + +// standard value for the mstatus register +#define MSTATUS_STD_VAL 0x1800 + +typedef enum { + M_MODE_BEH, + TRAP_INCR_BEH, + UNEXPECTED_IRQ_BEH +} trap_behavior_t; + +// trap handler behavior definitions +volatile trap_behavior_t trap_handler_beh = UNEXPECTED_IRQ_BEH; + +volatile uint32_t num_trap_executions; +volatile uint32_t unexpected_irq_beh = 0; + +// Utility functions: + + +uint32_t random_num32() { + volatile uint32_t num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); + return num; +} + +// Declaration of assert +static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { + if (actual != expect) { + printf(msg); + printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); + exit(EXIT_FAILURE); + } +} + + +// Changes the handler functionality, and then calls an exception to change into m-mode. +void set_m_mode(void) { + trap_handler_beh = M_MODE_BEH; + __asm__ volatile("ecall"); +} + + +// Checks the mepc for compressed instructions and increments appropriately +void increment_mepc(void){ + volatile unsigned int insn, mepc; + + // read the mepc + __asm__ volatile("csrrs %0, mepc, x0" : "=r"(mepc)); + + // read the contents of the mepc pc. + __asm__ volatile("lw %0, 0(%1)" : "=r"(insn) : "r"(mepc)); + + // check for compressed instruction before increment. + if ((insn & 0x3) == 0x3) { + mepc += 4; + } else { + mepc += 2; + } + + // write to the mepc + __asm__ volatile("csrrw x0, mepc, %0" :: "r"(mepc)); +} + +// Rewritten interrupt handler +__attribute__ ((interrupt ("machine"))) +void u_sw_irq_handler(void) { + + switch(trap_handler_beh) { + + // set Machine mode in the trap handler + case M_MODE_BEH : + __asm__ volatile("csrrs x0, mstatus, %0" :: "r"(MSTATUS_STD_VAL)); + increment_mepc(); + break; + + // csr_privilege_loop behavior + case TRAP_INCR_BEH : + num_trap_executions += 1; + increment_mepc(); + break; + + // unexpected handler irq (UNEXPECTED_IRQ_BEH and more) + default: + unexpected_irq_beh += 1; + } + +} + +// Test functions: + +void csr_should_be_present(void){ + + uint32_t rd; + + trap_handler_beh = TRAP_INCR_BEH; // setting the trap handler behaviour + num_trap_executions = 0; // resetting the trap handler count + + __asm__ volatile("csrr %0, mcounteren" : "=r"(rd)); //Read to csr_acc + __asm__ volatile("csrw mcounteren, %0" :: "r"(random_num32())); //Write csr_acc + __asm__ volatile("csrwi mcounteren, 0xF"); //Write immediate value + + __asm__ volatile("csrr %0, mcycle" : "=r"(rd)); + __asm__ volatile("csrw mcycle, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi mcycle, 0xF"); + + __asm__ volatile("csrr %0, mcycleh" : "=r"(rd)); + __asm__ volatile("csrw mcycleh, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi mcycleh, 0xF"); + + __asm__ volatile("csrr %0, minstret" : "=r"(rd)); + __asm__ volatile("csrw minstret, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi minstret, 0xF"); + + __asm__ volatile("csrr %0, minstreth" : "=r"(rd)); + __asm__ volatile("csrw minstreth, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi minstreth, 0xF"); + + + assert_or_die(num_trap_executions, 0, "error: reading the mcounteren, mcycle, mcycleh, minstret or minstreth register\n"); + + // set the trap handler to go into default mode + trap_handler_beh = UNEXPECTED_IRQ_BEH; + +} + + +void csr_should_not_be_present(void) { + + uint32_t rd; + + trap_handler_beh = TRAP_INCR_BEH; // setting the trap handler behaviour + num_trap_executions = 0; // resetting the trap handler count + + + #define X(addr) __asm__ volatile("csrr %0, " addr : "=r"(rd)); \ + __asm__ volatile("csrw " addr ", %0" :: "r"(random_num32())); \ + __asm__ volatile("csrwi " addr ", 0xF"); + CSRADDR_HPMCOUNTER + CSRADDR_HPMCOUNTERH + #undef X + + // test that unimplemented registers results in illegal instructions + __asm__ volatile("csrr %0, cycle" : "=r"(rd)); + __asm__ volatile("csrw cycle, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi cycle, 0xF"); + + __asm__ volatile("csrr %0, cycleh" : "=r"(rd)); + __asm__ volatile("csrw cycleh, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi cycleh, 0xF"); + + __asm__ volatile("csrr %0, instret" : "=r"(rd)); + __asm__ volatile("csrw instret, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi instret, 0xF"); + + __asm__ volatile("csrr %0, instreth" : "=r"(rd)); + __asm__ volatile("csrw instreth, %0" :: "r"(random_num32())); + __asm__ volatile("csrwi instreth, 0xF"); + + assert_or_die(num_trap_executions, 3*4 + 3*2*(32-3), "error: some of the unimplemented registers did not trap on instrs attempt\n"); + + // set the trap handler to go into default mode + trap_handler_beh = UNEXPECTED_IRQ_BEH; +} + + +void test_secureseeds_show_zero_at_reads(void){ + uint32_t rd; + + // setting the trap handler behaviour + trap_handler_beh = M_MODE_BEH; + + // resetting the trap handler count + num_trap_executions = 0; + + // enter machine mode: + set_m_mode(); + + + // read secureseed: + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(random_num32())); + assert_or_die(rd, 0, "error: secureseed0 is not read as zero\n"); + + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED1) ", %1" : "=r"(rd) : "r"(random_num32())); + assert_or_die(rd, 0, "error: secureseed1 is not read as zero\n"); + + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED2) ", %1" : "=r"(rd) : "r"(random_num32())); + assert_or_die(rd, 0, "error: secureseed2 is not read as zero\n"); + + // set the trap handler to go into default mode + trap_handler_beh = UNEXPECTED_IRQ_BEH; + +} + + +void test_ctrlcpu_and_secureseeds_accessable_in_machine_mode_only(void){ + uint32_t rd; + + // setting the trap handler behaviour + trap_handler_beh = TRAP_INCR_BEH; + + // resetting the trap handler count + num_trap_executions = 0; + + // enter user mode: + set_u_mode(); + + // read ctrlcpu and secureseed in user mode (which should not be successful): + __asm__ volatile("csrrw %0, " STR(CSRADDR_CPUCTRL) ", x0" : "=r"(rd)); + __asm__ volatile("csrrs %0, " STR(CSRADDR_CPUCTRL) ", x0" : "=r"(rd)); + __asm__ volatile("csrrc %0, " STR(CSRADDR_CPUCTRL) ", x0" : "=r"(rd)); + + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(random_num32())); + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(random_num32())); + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(random_num32())); + + // number of exceptions should equal number of acesses + assert_or_die(num_trap_executions, 3+3, "error: accessing cpuctrl or secureseed_ in usermode does not cause a trap\n"); + + // resetting the trap handler count + num_trap_executions = 0; + + // enter machine mode: + set_m_mode(); + + // read ctrlcpu and secureseed in machine mode (which should be successful): + + __asm__ volatile("csrrw %0, " STR(CSRADDR_CPUCTRL) ", x0" : "=r"(rd)); + __asm__ volatile("csrrs %0, " STR(CSRADDR_CPUCTRL) ", x0" : "=r"(rd)); + __asm__ volatile("csrrc %0, " STR(CSRADDR_CPUCTRL) ", x0" : "=r"(rd)); + + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(random_num32())); + + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(random_num32())); + + __asm__ volatile("csrrw %0, " STR(CSRADDR_SECURESEED0) ", %1" : "=r"(rd) : "r"(random_num32())); + + // number of exceptions should equal number of acesses + assert_or_die(num_trap_executions, 0, "error: accessing cpuctrl or secureseed_ in machine mode cause a trap\n"); + + // set the trap handler to go into default mode + trap_handler_beh = UNEXPECTED_IRQ_BEH; + +} + + + +int main(void){ + + unexpected_irq_beh = 0; + + csr_should_be_present(); + csr_should_not_be_present(); + + setup_pmp(); + + test_secureseeds_show_zero_at_reads(); + test_ctrlcpu_and_secureseeds_accessable_in_machine_mode_only(); + + // check if there was an unexpected irq handler req + assert_or_die(unexpected_irq_beh, 0, "ASSERT ERROR: unexpected irq handler\n"); + + return EXIT_SUCCESS; +} + +#endif diff --git a/cv32e40s/tests/programs/custom/zc_test/test.yaml b/cv32e40s/tests/programs/custom/zc_test/test.yaml new file mode 100644 index 0000000000..3ff08322c1 --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/test.yaml @@ -0,0 +1,6 @@ +name: zc_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + Directed test for Zc extension +plusargs: > + +rand_stall_obi_disable diff --git a/cv32e40s/tests/programs/custom/zc_test/test_gen/asm_manual_func.s b/cv32e40s/tests/programs/custom/zc_test/test_gen/asm_manual_func.s new file mode 100644 index 0000000000..895db1cf4d --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/test_gen/asm_manual_func.s @@ -0,0 +1,76 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly functions to help the tests in the zc_tests.c source file. +** +******************************************************************************* +*/ + +// _GEN END OF HEADER GEN_ + +// Funtions +enable_all_irq: + //set all fields of mie, hardwired are ignored (WARL) + li t0, 0xFFFFFFFF + csrrw x0, mie, t0 + + li t0, 0x00000008 + csrrs x0, mstatus, t0 + + jalr x0, 0(ra) + +trigger_irq: + // trigger irq + li t0, 0x00800140 + la t1, glb_irq_line + lw t2, 0(t1) + la t1, glb_irq_delay + lw t3, 0(t1) + sw t2, 0(t0) + sw t3, 4(t0) + + //return to caller + jalr x0, 0(ra) + + /* + ** The rest of this file consist of generated functions that work in the following manner: + ** interrupt_push_pop: + ** input value determines which rlist to test (case statement) + ** jump to interrupt trigger routine + ** - sets an interrupt to hit the atomic part of the following instruction, + ** - set up from C test by global variables + ** run push instruction to test + ** jump to interrupt trigger routine + ** run pop instruction to test + ** + ** interrupt_popret/popretz + ** input value determines which rlist to test (case statement) + ** load ra with the address for thenext instruction after the popret + ** to enable the popret to return to the program + ** make a push to keep the stack pointer valid after the function call + ** jump to interrupt trigger routine + ** run popret/z instruction to test + ** + ** interrupt mvsa + ** input value determines which sreg combination to test (case statement) + ** populate registers with random data + ** jump to interrupt trigger routine + ** run mvsa01 instruction to test + ** + ** + ** interrupt mvsa + ** input value determines which sreg combination to test (case statement) + ** populate registers with random data + ** jump to interrupt trigger routine + ** run mva01s instruction to test + ** + */ diff --git a/cv32e40s/tests/programs/custom/zc_test/test_gen/asm_manual_top.s b/cv32e40s/tests/programs/custom/zc_test/test_gen/asm_manual_top.s new file mode 100644 index 0000000000..3e0a7551d4 --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/test_gen/asm_manual_top.s @@ -0,0 +1,33 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly functions to help the tests in the zc_tests.c source file. +** +******************************************************************************* +*/ + +.section .data +glb_irq_line: + .word 0 +glb_irq_delay: + .word 0 +stored_ra: + .word 0 + +.section .text + +.global glb_irq_line +.global glb_irq_delay + +// Functions +.global enable_all_irq + diff --git a/cv32e40s/tests/programs/custom/zc_test/test_gen/h_manual_top.h b/cv32e40s/tests/programs/custom/zc_test/test_gen/h_manual_top.h new file mode 100644 index 0000000000..66f7971ab9 --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/test_gen/h_manual_top.h @@ -0,0 +1,77 @@ +/* +** +** Copyright 2020 OpenHW Group +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +** +******************************************************************************* +** +** Directed test for Zc extension exersizes instructions and scenarios +** not likely to becovered by randomly +** generated tests. +** +******************************************************************************* +*/ + + +#ifndef __ZC_TEST_H__ +#define __ZC_TEST_H__ + +#include +#include +#include "corev_uvmt.h" +// Enable debug messages, note that this will change test timing +//#define DEBUG_MSG + +#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE)) +#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE + 4)) +#define EX_IRQ_LINE 11 + + +#define PUSH_RLIST_MIN 4 +#define PUSH_RLIST_MAX 15 + +enum ttype{ + pushpop, + popret, + popretz, + mvsa, + mvas +}; + + +// Global Variables // +volatile uint32_t ex_traps_entered; +volatile enum ttype test_active; +volatile uint32_t test_instr_num; +volatile uint32_t exp_irq; +volatile uint32_t failureCount; +volatile uint32_t rnd0; +volatile uint32_t rnd1; +volatile uint32_t iteratorVault; +extern volatile uint32_t glb_irq_line; +extern volatile uint32_t glb_irq_delay; + + +// Functions from Assebly file // + +// Assembly function to enable interrupts +extern volatile void enable_all_irq(); + +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay); +uint32_t vp_random_num(uint32_t upper_bound, uint32_t lower_bound); + +__attribute__((interrupt ("machine"))) void m_external_irq_handler(void); + +// End of manual section // + diff --git a/cv32e40s/tests/programs/custom/zc_test/test_gen/zc_gen.py b/cv32e40s/tests/programs/custom/zc_test/test_gen/zc_gen.py new file mode 100644 index 0000000000..2edef2e54f --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/test_gen/zc_gen.py @@ -0,0 +1,451 @@ +#zc directed test generator + +asmFile = open("../zc_test.S", "w") +asmInputTop = open("asm_manual_top.s", "r") +asmInputFunc = open("asm_manual_func.s", "r") + +asmFuncTemp = [] + +hFile = open("../zc_test.h", "w") +hInputTop = open("h_manual_top.h", "r") + +# code lists +pushPopRlists = [ "ra", \ + "ra, s0", \ + "ra, s0-s1", \ + "ra, s0-s2", \ + "ra, s0-s3", \ + "ra, s0-s4", \ + "ra, s0-s5", \ + "ra, s0-s6", \ + "ra, s0-s7", \ + "ra, s0-s8", \ + "ra, s0-s9", \ + "ra, s0-s11" \ + ] + +#randomly selected sreg values to avoid full set +sreg1List = ["s2", "s4", "s5", "s7"] +sreg2List = ["s6", "s3", "s1", "s0"] + + +# "Defines" +PUSH_POP_RLIST_LOW = 4 + +funcTags = ["interrupt_push_pop", "interrupt_popret", "interrupt_popretz", "interrupt_mvsa", "interrupt_mvas"] + +#Generate push/pop test function +pushTagCount = 0 +pushPopTags = [] + +print("\nGenerating push/pop test function") + +asmFuncTemp.append(funcTags[0]+":\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" sw ra, 0(t0)\n") + +for i in range(0, len(pushPopRlists)): + print("generating case for rlist: "+str(PUSH_POP_RLIST_LOW+i)) + + #case tag and branch + asmFuncTemp.append("\n\n pp_case_"+str(PUSH_POP_RLIST_LOW+i)+":\n") + asmFuncTemp.append(" li t1, "+str(PUSH_POP_RLIST_LOW+i)+"\n") + if i == len(pushPopRlists)-1: + asmFuncTemp.append(" bne a0, t1, pp_case_end\n") + else: + asmFuncTemp.append(" bne a0, t1, pp_case_"+str(PUSH_POP_RLIST_LOW+i+1)+"\n") + + + #Set up interrupt + asmFuncTemp.append(" jal ra, trigger_irq\n") + + #Generate push tag + + tag = "push_"+str(pushTagCount) + asmFuncTemp.append(" "+tag+":\n") + #save for list generation + pushPopTags.append(tag) + + #Generate instruction for test + asmFuncTemp.append(" cm.push {"+pushPopRlists[i]+"}, -64\n") + asmFuncTemp.append(" nop\n nop\n\n") + + #Set up interrupt + asmFuncTemp.append(" jal ra, trigger_irq\n") + + + #Generate push tag + + tag = "pop_"+str(pushTagCount) + asmFuncTemp.append(" "+tag+":\n") + #save for list generation + pushPopTags.append(tag) + + #Generate instruction for test + asmFuncTemp.append(" cm.pop {"+pushPopRlists[i]+"}, 64\n") + asmFuncTemp.append(" nop\n nop\n") + asmFuncTemp.append(" j pp_case_end\n\n") + + pushTagCount += 1 + +#End of function +asmFuncTemp.append("\n\n pp_case_end:\n") +asmFuncTemp.append(" //return to caller\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" lw ra, 0(t0)\n") +asmFuncTemp.append(" jalr x0, 0(ra)\n\n\n\n") + +# END Generate push/pop test function + + +#Generate popret test function +popretTagCount = 0 +popretTags = [] + +print("\nGenerating popret test function") + +asmFuncTemp.append(funcTags[1]+":\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" sw ra, 0(t0)\n") + +for i in range(0, len(pushPopRlists)): + print("generating case for rlist: "+str(PUSH_POP_RLIST_LOW+i)) + + #case tag and branch + asmFuncTemp.append("\n\n pr_case_"+str(PUSH_POP_RLIST_LOW+i)+":\n") + asmFuncTemp.append(" li t1, "+str(PUSH_POP_RLIST_LOW+i)+"\n") + if i == len(pushPopRlists)-1: + asmFuncTemp.append(" bne a0, t1, pr_case_end\n") + else: + asmFuncTemp.append(" bne a0, t1, pr_case_"+str(PUSH_POP_RLIST_LOW+i+1)+"\n") + + + + #Generate pop tag + tag = "popret_"+str(popretTagCount) + #set up RA to target the next instruction + asmFuncTemp.append(" la ra, "+tag+"_ret\n") + + #Push instruction to set stack frame + asmFuncTemp.append(" cm.push {"+pushPopRlists[i]+"}, -64\n") + + #Set up interrupt + asmFuncTemp.append(" jal ra, trigger_irq\n") + + + + + asmFuncTemp.append(" "+tag+":\n") + #save for list generation + popretTags.append(tag) + + #Generate instruction for test + asmFuncTemp.append(" cm.popret {"+pushPopRlists[i]+"}, 64\n") + + asmFuncTemp.append(" "+tag+"_ret:\n") + asmFuncTemp.append(" nop\n nop\n") + asmFuncTemp.append(" j pr_case_end\n\n") + + popretTagCount += 1 + +#End of function +asmFuncTemp.append("\n\n pr_case_end:\n") +asmFuncTemp.append(" //return to caller\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" lw ra, 0(t0)\n") +asmFuncTemp.append(" jalr x0, 0(ra)\n") + +# END Generate popret test function + +#Generate popretz test function +popretzTagCount = 0 +popretzTags = [] + +print("\nGenerating popretz test function") + + +asmFuncTemp.append(funcTags[2]+":\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" sw ra, 0(t0)\n") + +for i in range(0, len(pushPopRlists)): + print("generating case for rlist: "+str(PUSH_POP_RLIST_LOW+i)) + + #case tag and branch + asmFuncTemp.append("\n\n prz_case_"+str(PUSH_POP_RLIST_LOW+i)+":\n") + asmFuncTemp.append(" li t1, "+str(PUSH_POP_RLIST_LOW+i)+"\n") + if i == len(pushPopRlists)-1: + asmFuncTemp.append(" bne a0, t1, prz_case_end\n") + else: + asmFuncTemp.append(" bne a0, t1, prz_case_"+str(PUSH_POP_RLIST_LOW+i+1)+"\n") + + + + #Generate pop tag + tag = "popretz_"+str(popretzTagCount) + #set up RA to target the next instruction + asmFuncTemp.append(" la ra, "+tag+"_ret\n") + + #Push instruction to set stack frame + asmFuncTemp.append(" cm.push {"+pushPopRlists[i]+"}, -64\n") + + #Set up interrupt + asmFuncTemp.append(" jal ra, trigger_irq\n") + + + + + asmFuncTemp.append(" "+tag+":\n") + #save for list generation + popretzTags.append(tag) + + #Generate instruction for test + asmFuncTemp.append(" cm.popretz {"+pushPopRlists[i]+"}, 64\n") + + asmFuncTemp.append(" "+tag+"_ret:\n") + asmFuncTemp.append(" nop\n nop\n") + asmFuncTemp.append(" j prz_case_end\n\n") + + popretzTagCount += 1 + +#End of function +asmFuncTemp.append("\n\n prz_case_end:\n") +asmFuncTemp.append(" //return to caller\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" lw ra, 0(t0)\n") +asmFuncTemp.append(" jalr x0, 0(ra)\n") + +# END Generate popretz test function + + +#Generate mvsa01 test function +print("\nGenerating mvsa01 test function") +mvsaTagCount = 0 +mvsaTags = [] + +asmFuncTemp.append(funcTags[3]+":\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" sw ra, 0(t0)\n") + +for s1 in sreg1List: + for s2 in sreg2List: + print("generating case: " +str(mvsaTagCount) + " for sregs: " + s1 + ", " + s2) + + + #case tag and branch + asmFuncTemp.append("\n\n sa_case_"+str(mvsaTagCount)+":\n") + asmFuncTemp.append(" li t1, "+str(mvsaTagCount)+"\n") + if mvsaTagCount == len(sreg1List)*len(sreg2List)-1: + asmFuncTemp.append(" bne a0, t1, sa_case_end\n") + else: + asmFuncTemp.append(" bne a0, t1, sa_case_"+str(mvsaTagCount+1)+"\n") + + #Populate sregs with random data + asmFuncTemp.append(" mv " + s1 + ", a2\n") + asmFuncTemp.append(" mv " + s2 + ", a3\n") + #Set up interrupt + asmFuncTemp.append(" jal ra, trigger_irq\n") + + #Generate push tag + + tag = "mvsa_"+str(mvsaTagCount) + asmFuncTemp.append(" "+tag+":\n") + #save for list generation + mvsaTags.append(tag) + + #Generate instruction for test + asmFuncTemp.append(" cm.mvsa01 "+s1+", "+s2+"\n") + asmFuncTemp.append(" nop\n nop\n") + asmFuncTemp.append(" j sa_case_end\n\n") + + mvsaTagCount += 1 + +#End of function +asmFuncTemp.append("\n\n sa_case_end:\n") +asmFuncTemp.append(" //return to caller\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" lw ra, 0(t0)\n") +asmFuncTemp.append(" jalr x0, 0(ra)\n\n\n\n") + +# END Generate mvsa test function + +#Generate mva01s test function +print("\nGenerating mva01s test function") +mvasTagCount = 0 +mvasTags = [] + +asmFuncTemp.append(funcTags[4]+":\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" sw ra, 0(t0)\n") + +for s1 in sreg1List: + for s2 in sreg2List: + print("generating case: " +str(mvasTagCount) + " for sregs: " + s1 + ", " + s2) + + + #case tag and branch + asmFuncTemp.append("\n\n as_case_"+str(mvasTagCount)+":\n") + asmFuncTemp.append(" li t1, "+str(mvasTagCount)+"\n") + if mvasTagCount == len(sreg1List)*len(sreg2List)-1: + asmFuncTemp.append(" bne a0, t1, as_case_end\n") + else: + asmFuncTemp.append(" bne a0, t1, as_case_"+str(mvasTagCount+1)+"\n") + + #Populate sregs with random data + asmFuncTemp.append(" mv " + s1 + ", a2\n") + asmFuncTemp.append(" mv " + s2 + ", a3\n") + #Set up interrupt + asmFuncTemp.append(" jal ra, trigger_irq\n") + + #Generate push tag + + tag = "mvas_"+str(mvasTagCount) + asmFuncTemp.append(" "+tag+":\n") + #save for list generation + mvasTags.append(tag) + + #Generate instruction for test + asmFuncTemp.append(" cm.mva01s "+s1+", "+s2+"\n") + asmFuncTemp.append(" nop\n nop\n") + asmFuncTemp.append(" j as_case_end\n\n") + + mvasTagCount += 1 + +#End of function +asmFuncTemp.append("\n\n as_case_end:\n") +asmFuncTemp.append(" //return to caller\n") +asmFuncTemp.append(" la t0, stored_ra\n") +asmFuncTemp.append(" lw ra, 0(t0)\n") +asmFuncTemp.append(" jalr x0, 0(ra)\n\n\n\n") + +# END Generate mvas test function + +#Generate asmfile +for line in asmInputTop: + asmFile.write(line) + +#Generate list of tags +asmFile.write("//Generated Functions\n") +for func in funcTags: + asmFile.write(".global "+func+"\n") + +asmFile.write("\n\n") + +asmFile.write("//instruction tags\n") +for tag in pushPopTags: + asmFile.write(".global "+tag+"\n") +for tag in popretTags: + asmFile.write(".global "+tag+"\n") +for tag in popretzTags: + asmFile.write(".global "+tag+"\n") +for tag in mvsaTags: + asmFile.write(".global "+tag+"\n") +for tag in mvasTags: + asmFile.write(".global "+tag+"\n") + +#discard header in functions file +for line in asmInputFunc: + if "_GEN END OF HEADER GEN_" in line: + break + +for line in asmInputFunc: + asmFile.write(line) + +asmFile.write("\n\n") +asmFile.write("//Generated Functions\n") +for line in asmFuncTemp: + asmFile.write(line) + + +#Generate H file: +for line in hInputTop: + hFile.write(line) + + +hFile.write("//Generated test functions\n") +hFile.write("//functions time interrupts to hit atomic part of named instruction type\n") +for func in funcTags: + if (func == "interrupt_mvsa") or (func == "interrupt_mvas"): + hFile.write("extern volatile void "+func+"(uint32_t, uint32_t, uint32_t);\n") + else: + hFile.write("extern volatile void "+func+"(uint32_t);\n") +#pushpop +hFile.write("\n\n//Generated list of push/pop instr addresses\n") +hFile.write("#define PUSHPOP_INSTR_SIZE " + str(len(pushPopTags)) + "\n\n") +for tag in pushPopTags: + hFile.write("extern uint32_t " + tag + ";\n") + +hFile.write("\nuint32_t pushpop_instr_list[PUSHPOP_INSTR_SIZE] = {\n") +for tag in pushPopTags: + if tag == pushPopTags[len(pushPopTags)-1]: + hFile.write(" (uint32_t)&" + tag + "\n") + else: + hFile.write(" (uint32_t)&" + tag + ",\n") +hFile.write("};\n") + +#popret +hFile.write("//Generated list of popret instr addresses\n") +hFile.write("#define POPRET_INSTR_SIZE " + str(len(popretTags)) + "\n\n") +for tag in popretTags: + hFile.write("extern uint32_t " + tag + ";\n") + +hFile.write("\nuint32_t popret_instr_list[POPRET_INSTR_SIZE] = {\n") +for tag in popretTags: + if tag == popretTags[len(popretTags)-1]: + hFile.write(" (uint32_t)&" + tag + "\n") + else: + hFile.write(" (uint32_t)&" + tag + ",\n") +hFile.write("};\n") + +#popretz +hFile.write("//Generated list of popretz instr addresses\n") +hFile.write("#define POPRETZ_INSTR_SIZE " + str(len(popretzTags)) + "\n\n") +for tag in popretzTags: + hFile.write("extern uint32_t " + tag + ";\n") + +hFile.write("\nuint32_t popretz_instr_list[POPRET_INSTR_SIZE] = {\n") +for tag in popretzTags: + if tag == popretzTags[len(popretzTags)-1]: + hFile.write(" (uint32_t)&" + tag + "\n") + else: + hFile.write(" (uint32_t)&" + tag + ",\n") +hFile.write("};\n") + +#mvsa +hFile.write("//Generated list of mvsa instr addresses\n") +hFile.write("#define MVSA_INSTR_SIZE " + str(len(mvsaTags)) + "\n\n") +for tag in mvsaTags: + hFile.write("extern uint32_t " + tag + ";\n") + +hFile.write("\nuint32_t mvsa_instr_list[MVSA_INSTR_SIZE] = {\n") +for tag in mvsaTags: + if tag == mvsaTags[len(mvsaTags)-1]: + hFile.write(" (uint32_t)&" + tag + "\n") + else: + hFile.write(" (uint32_t)&" + tag + ",\n") +hFile.write("};\n") + +#mvas +hFile.write("//Generated list of mvas instr addresses\n") +hFile.write("#define MVAS_INSTR_SIZE " + str(len(mvasTags)) + "\n\n") +for tag in mvasTags: + hFile.write("extern uint32_t " + tag + ";\n") + +hFile.write("\nuint32_t mvas_instr_list[MVAS_INSTR_SIZE] = {\n") +for tag in mvasTags: + if tag == mvasTags[len(mvasTags)-1]: + hFile.write(" (uint32_t)&" + tag + "\n") + else: + hFile.write(" (uint32_t)&" + tag + ",\n") +hFile.write("};\n") + + + +hFile.write("#endif\n\n") + +#close files +asmFile.close() +asmInputTop.close() +asmInputFunc.close() +hFile.close() +hInputTop.close() diff --git a/cv32e40s/tests/programs/custom/zc_test/zc_test.S b/cv32e40s/tests/programs/custom/zc_test/zc_test.S new file mode 100644 index 0000000000..6df4a37408 --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/zc_test.S @@ -0,0 +1,1266 @@ +/* +** Copyright 2022 OpenHW Group +** +** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +** Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance +** with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at +** https://solderpad.org/licenses/SHL-2.1/ +** Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on +** an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the +** specific language governing permissions and limitations under the License. +******************************************************************************* +** +** Assembly functions to help the tests in the zc_tests.c source file. +** +******************************************************************************* +*/ + +.section .data +glb_irq_line: + .word 0 +glb_irq_delay: + .word 0 +stored_ra: + .word 0 + +.section .text + +.global glb_irq_line +.global glb_irq_delay + +// Functions +.global enable_all_irq + +//Generated Functions +.global interrupt_push_pop +.global interrupt_popret +.global interrupt_popretz +.global interrupt_mvsa +.global interrupt_mvas + + +//instruction tags +.global push_0 +.global pop_0 +.global push_1 +.global pop_1 +.global push_2 +.global pop_2 +.global push_3 +.global pop_3 +.global push_4 +.global pop_4 +.global push_5 +.global pop_5 +.global push_6 +.global pop_6 +.global push_7 +.global pop_7 +.global push_8 +.global pop_8 +.global push_9 +.global pop_9 +.global push_10 +.global pop_10 +.global push_11 +.global pop_11 +.global popret_0 +.global popret_1 +.global popret_2 +.global popret_3 +.global popret_4 +.global popret_5 +.global popret_6 +.global popret_7 +.global popret_8 +.global popret_9 +.global popret_10 +.global popret_11 +.global popretz_0 +.global popretz_1 +.global popretz_2 +.global popretz_3 +.global popretz_4 +.global popretz_5 +.global popretz_6 +.global popretz_7 +.global popretz_8 +.global popretz_9 +.global popretz_10 +.global popretz_11 +.global mvsa_0 +.global mvsa_1 +.global mvsa_2 +.global mvsa_3 +.global mvsa_4 +.global mvsa_5 +.global mvsa_6 +.global mvsa_7 +.global mvsa_8 +.global mvsa_9 +.global mvsa_10 +.global mvsa_11 +.global mvsa_12 +.global mvsa_13 +.global mvsa_14 +.global mvsa_15 +.global mvas_0 +.global mvas_1 +.global mvas_2 +.global mvas_3 +.global mvas_4 +.global mvas_5 +.global mvas_6 +.global mvas_7 +.global mvas_8 +.global mvas_9 +.global mvas_10 +.global mvas_11 +.global mvas_12 +.global mvas_13 +.global mvas_14 +.global mvas_15 + +// Funtions +enable_all_irq: + //set all fields of mie, hardwired are ignored (WARL) + li t0, 0xFFFFFFFF + csrrw x0, mie, t0 + + li t0, 0x00000008 + csrrs x0, mstatus, t0 + + jalr x0, 0(ra) + +trigger_irq: + // trigger irq + li t0, 0x00800140 + la t1, glb_irq_line + lw t2, 0(t1) + la t1, glb_irq_delay + lw t3, 0(t1) + sw t2, 0(t0) + sw t3, 4(t0) + + //return to caller + jalr x0, 0(ra) + + /* + ** The rest of this file consist of generated functions that work in the following manner: + ** interrupt_push_pop: + ** input value determines which rlist to test (case statement) + ** jump to interrupt trigger routine + ** - sets an interrupt to hit the atomic part of the following instruction, + ** - set up from C test by global variables + ** run push instruction to test + ** jump to interrupt trigger routine + ** run pop instruction to test + ** + ** interrupt_popret/popretz + ** input value determines which rlist to test (case statement) + ** load ra with the address for thenext instruction after the popret + ** to enable the popret to return to the program + ** make a push to keep the stack pointer valid after the function call + ** jump to interrupt trigger routine + ** run popret/z instruction to test + ** + ** interrupt mvsa + ** input value determines which sreg combination to test (case statement) + ** populate registers with random data + ** jump to interrupt trigger routine + ** run mvsa01 instruction to test + ** + ** + ** interrupt mvsa + ** input value determines which sreg combination to test (case statement) + ** populate registers with random data + ** jump to interrupt trigger routine + ** run mva01s instruction to test + ** + */ + + +//Generated Functions +interrupt_push_pop: + la t0, stored_ra + sw ra, 0(t0) + + + pp_case_4: + li t1, 4 + bne a0, t1, pp_case_5 + jal ra, trigger_irq + push_0: + cm.push {ra}, -64 + nop + nop + + jal ra, trigger_irq + pop_0: + cm.pop {ra}, 64 + nop + nop + j pp_case_end + + + + pp_case_5: + li t1, 5 + bne a0, t1, pp_case_6 + jal ra, trigger_irq + push_1: + cm.push {ra, s0}, -64 + nop + nop + + jal ra, trigger_irq + pop_1: + cm.pop {ra, s0}, 64 + nop + nop + j pp_case_end + + + + pp_case_6: + li t1, 6 + bne a0, t1, pp_case_7 + jal ra, trigger_irq + push_2: + cm.push {ra, s0-s1}, -64 + nop + nop + + jal ra, trigger_irq + pop_2: + cm.pop {ra, s0-s1}, 64 + nop + nop + j pp_case_end + + + + pp_case_7: + li t1, 7 + bne a0, t1, pp_case_8 + jal ra, trigger_irq + push_3: + cm.push {ra, s0-s2}, -64 + nop + nop + + jal ra, trigger_irq + pop_3: + cm.pop {ra, s0-s2}, 64 + nop + nop + j pp_case_end + + + + pp_case_8: + li t1, 8 + bne a0, t1, pp_case_9 + jal ra, trigger_irq + push_4: + cm.push {ra, s0-s3}, -64 + nop + nop + + jal ra, trigger_irq + pop_4: + cm.pop {ra, s0-s3}, 64 + nop + nop + j pp_case_end + + + + pp_case_9: + li t1, 9 + bne a0, t1, pp_case_10 + jal ra, trigger_irq + push_5: + cm.push {ra, s0-s4}, -64 + nop + nop + + jal ra, trigger_irq + pop_5: + cm.pop {ra, s0-s4}, 64 + nop + nop + j pp_case_end + + + + pp_case_10: + li t1, 10 + bne a0, t1, pp_case_11 + jal ra, trigger_irq + push_6: + cm.push {ra, s0-s5}, -64 + nop + nop + + jal ra, trigger_irq + pop_6: + cm.pop {ra, s0-s5}, 64 + nop + nop + j pp_case_end + + + + pp_case_11: + li t1, 11 + bne a0, t1, pp_case_12 + jal ra, trigger_irq + push_7: + cm.push {ra, s0-s6}, -64 + nop + nop + + jal ra, trigger_irq + pop_7: + cm.pop {ra, s0-s6}, 64 + nop + nop + j pp_case_end + + + + pp_case_12: + li t1, 12 + bne a0, t1, pp_case_13 + jal ra, trigger_irq + push_8: + cm.push {ra, s0-s7}, -64 + nop + nop + + jal ra, trigger_irq + pop_8: + cm.pop {ra, s0-s7}, 64 + nop + nop + j pp_case_end + + + + pp_case_13: + li t1, 13 + bne a0, t1, pp_case_14 + jal ra, trigger_irq + push_9: + cm.push {ra, s0-s8}, -64 + nop + nop + + jal ra, trigger_irq + pop_9: + cm.pop {ra, s0-s8}, 64 + nop + nop + j pp_case_end + + + + pp_case_14: + li t1, 14 + bne a0, t1, pp_case_15 + jal ra, trigger_irq + push_10: + cm.push {ra, s0-s9}, -64 + nop + nop + + jal ra, trigger_irq + pop_10: + cm.pop {ra, s0-s9}, 64 + nop + nop + j pp_case_end + + + + pp_case_15: + li t1, 15 + bne a0, t1, pp_case_end + jal ra, trigger_irq + push_11: + cm.push {ra, s0-s11}, -64 + nop + nop + + jal ra, trigger_irq + pop_11: + cm.pop {ra, s0-s11}, 64 + nop + nop + j pp_case_end + + + + pp_case_end: + //return to caller + la t0, stored_ra + lw ra, 0(t0) + jalr x0, 0(ra) + + + +interrupt_popret: + la t0, stored_ra + sw ra, 0(t0) + + + pr_case_4: + li t1, 4 + bne a0, t1, pr_case_5 + la ra, popret_0_ret + cm.push {ra}, -64 + jal ra, trigger_irq + popret_0: + cm.popret {ra}, 64 + popret_0_ret: + nop + nop + j pr_case_end + + + + pr_case_5: + li t1, 5 + bne a0, t1, pr_case_6 + la ra, popret_1_ret + cm.push {ra, s0}, -64 + jal ra, trigger_irq + popret_1: + cm.popret {ra, s0}, 64 + popret_1_ret: + nop + nop + j pr_case_end + + + + pr_case_6: + li t1, 6 + bne a0, t1, pr_case_7 + la ra, popret_2_ret + cm.push {ra, s0-s1}, -64 + jal ra, trigger_irq + popret_2: + cm.popret {ra, s0-s1}, 64 + popret_2_ret: + nop + nop + j pr_case_end + + + + pr_case_7: + li t1, 7 + bne a0, t1, pr_case_8 + la ra, popret_3_ret + cm.push {ra, s0-s2}, -64 + jal ra, trigger_irq + popret_3: + cm.popret {ra, s0-s2}, 64 + popret_3_ret: + nop + nop + j pr_case_end + + + + pr_case_8: + li t1, 8 + bne a0, t1, pr_case_9 + la ra, popret_4_ret + cm.push {ra, s0-s3}, -64 + jal ra, trigger_irq + popret_4: + cm.popret {ra, s0-s3}, 64 + popret_4_ret: + nop + nop + j pr_case_end + + + + pr_case_9: + li t1, 9 + bne a0, t1, pr_case_10 + la ra, popret_5_ret + cm.push {ra, s0-s4}, -64 + jal ra, trigger_irq + popret_5: + cm.popret {ra, s0-s4}, 64 + popret_5_ret: + nop + nop + j pr_case_end + + + + pr_case_10: + li t1, 10 + bne a0, t1, pr_case_11 + la ra, popret_6_ret + cm.push {ra, s0-s5}, -64 + jal ra, trigger_irq + popret_6: + cm.popret {ra, s0-s5}, 64 + popret_6_ret: + nop + nop + j pr_case_end + + + + pr_case_11: + li t1, 11 + bne a0, t1, pr_case_12 + la ra, popret_7_ret + cm.push {ra, s0-s6}, -64 + jal ra, trigger_irq + popret_7: + cm.popret {ra, s0-s6}, 64 + popret_7_ret: + nop + nop + j pr_case_end + + + + pr_case_12: + li t1, 12 + bne a0, t1, pr_case_13 + la ra, popret_8_ret + cm.push {ra, s0-s7}, -64 + jal ra, trigger_irq + popret_8: + cm.popret {ra, s0-s7}, 64 + popret_8_ret: + nop + nop + j pr_case_end + + + + pr_case_13: + li t1, 13 + bne a0, t1, pr_case_14 + la ra, popret_9_ret + cm.push {ra, s0-s8}, -64 + jal ra, trigger_irq + popret_9: + cm.popret {ra, s0-s8}, 64 + popret_9_ret: + nop + nop + j pr_case_end + + + + pr_case_14: + li t1, 14 + bne a0, t1, pr_case_15 + la ra, popret_10_ret + cm.push {ra, s0-s9}, -64 + jal ra, trigger_irq + popret_10: + cm.popret {ra, s0-s9}, 64 + popret_10_ret: + nop + nop + j pr_case_end + + + + pr_case_15: + li t1, 15 + bne a0, t1, pr_case_end + la ra, popret_11_ret + cm.push {ra, s0-s11}, -64 + jal ra, trigger_irq + popret_11: + cm.popret {ra, s0-s11}, 64 + popret_11_ret: + nop + nop + j pr_case_end + + + + pr_case_end: + //return to caller + la t0, stored_ra + lw ra, 0(t0) + jalr x0, 0(ra) +interrupt_popretz: + la t0, stored_ra + sw ra, 0(t0) + + + prz_case_4: + li t1, 4 + bne a0, t1, prz_case_5 + la ra, popretz_0_ret + cm.push {ra}, -64 + jal ra, trigger_irq + popretz_0: + cm.popretz {ra}, 64 + popretz_0_ret: + nop + nop + j prz_case_end + + + + prz_case_5: + li t1, 5 + bne a0, t1, prz_case_6 + la ra, popretz_1_ret + cm.push {ra, s0}, -64 + jal ra, trigger_irq + popretz_1: + cm.popretz {ra, s0}, 64 + popretz_1_ret: + nop + nop + j prz_case_end + + + + prz_case_6: + li t1, 6 + bne a0, t1, prz_case_7 + la ra, popretz_2_ret + cm.push {ra, s0-s1}, -64 + jal ra, trigger_irq + popretz_2: + cm.popretz {ra, s0-s1}, 64 + popretz_2_ret: + nop + nop + j prz_case_end + + + + prz_case_7: + li t1, 7 + bne a0, t1, prz_case_8 + la ra, popretz_3_ret + cm.push {ra, s0-s2}, -64 + jal ra, trigger_irq + popretz_3: + cm.popretz {ra, s0-s2}, 64 + popretz_3_ret: + nop + nop + j prz_case_end + + + + prz_case_8: + li t1, 8 + bne a0, t1, prz_case_9 + la ra, popretz_4_ret + cm.push {ra, s0-s3}, -64 + jal ra, trigger_irq + popretz_4: + cm.popretz {ra, s0-s3}, 64 + popretz_4_ret: + nop + nop + j prz_case_end + + + + prz_case_9: + li t1, 9 + bne a0, t1, prz_case_10 + la ra, popretz_5_ret + cm.push {ra, s0-s4}, -64 + jal ra, trigger_irq + popretz_5: + cm.popretz {ra, s0-s4}, 64 + popretz_5_ret: + nop + nop + j prz_case_end + + + + prz_case_10: + li t1, 10 + bne a0, t1, prz_case_11 + la ra, popretz_6_ret + cm.push {ra, s0-s5}, -64 + jal ra, trigger_irq + popretz_6: + cm.popretz {ra, s0-s5}, 64 + popretz_6_ret: + nop + nop + j prz_case_end + + + + prz_case_11: + li t1, 11 + bne a0, t1, prz_case_12 + la ra, popretz_7_ret + cm.push {ra, s0-s6}, -64 + jal ra, trigger_irq + popretz_7: + cm.popretz {ra, s0-s6}, 64 + popretz_7_ret: + nop + nop + j prz_case_end + + + + prz_case_12: + li t1, 12 + bne a0, t1, prz_case_13 + la ra, popretz_8_ret + cm.push {ra, s0-s7}, -64 + jal ra, trigger_irq + popretz_8: + cm.popretz {ra, s0-s7}, 64 + popretz_8_ret: + nop + nop + j prz_case_end + + + + prz_case_13: + li t1, 13 + bne a0, t1, prz_case_14 + la ra, popretz_9_ret + cm.push {ra, s0-s8}, -64 + jal ra, trigger_irq + popretz_9: + cm.popretz {ra, s0-s8}, 64 + popretz_9_ret: + nop + nop + j prz_case_end + + + + prz_case_14: + li t1, 14 + bne a0, t1, prz_case_15 + la ra, popretz_10_ret + cm.push {ra, s0-s9}, -64 + jal ra, trigger_irq + popretz_10: + cm.popretz {ra, s0-s9}, 64 + popretz_10_ret: + nop + nop + j prz_case_end + + + + prz_case_15: + li t1, 15 + bne a0, t1, prz_case_end + la ra, popretz_11_ret + cm.push {ra, s0-s11}, -64 + jal ra, trigger_irq + popretz_11: + cm.popretz {ra, s0-s11}, 64 + popretz_11_ret: + nop + nop + j prz_case_end + + + + prz_case_end: + //return to caller + la t0, stored_ra + lw ra, 0(t0) + jalr x0, 0(ra) +interrupt_mvsa: + la t0, stored_ra + sw ra, 0(t0) + + + sa_case_0: + li t1, 0 + bne a0, t1, sa_case_1 + mv s2, a2 + mv s6, a3 + jal ra, trigger_irq + mvsa_0: + cm.mvsa01 s2, s6 + nop + nop + j sa_case_end + + + + sa_case_1: + li t1, 1 + bne a0, t1, sa_case_2 + mv s2, a2 + mv s3, a3 + jal ra, trigger_irq + mvsa_1: + cm.mvsa01 s2, s3 + nop + nop + j sa_case_end + + + + sa_case_2: + li t1, 2 + bne a0, t1, sa_case_3 + mv s2, a2 + mv s1, a3 + jal ra, trigger_irq + mvsa_2: + cm.mvsa01 s2, s1 + nop + nop + j sa_case_end + + + + sa_case_3: + li t1, 3 + bne a0, t1, sa_case_4 + mv s2, a2 + mv s0, a3 + jal ra, trigger_irq + mvsa_3: + cm.mvsa01 s2, s0 + nop + nop + j sa_case_end + + + + sa_case_4: + li t1, 4 + bne a0, t1, sa_case_5 + mv s4, a2 + mv s6, a3 + jal ra, trigger_irq + mvsa_4: + cm.mvsa01 s4, s6 + nop + nop + j sa_case_end + + + + sa_case_5: + li t1, 5 + bne a0, t1, sa_case_6 + mv s4, a2 + mv s3, a3 + jal ra, trigger_irq + mvsa_5: + cm.mvsa01 s4, s3 + nop + nop + j sa_case_end + + + + sa_case_6: + li t1, 6 + bne a0, t1, sa_case_7 + mv s4, a2 + mv s1, a3 + jal ra, trigger_irq + mvsa_6: + cm.mvsa01 s4, s1 + nop + nop + j sa_case_end + + + + sa_case_7: + li t1, 7 + bne a0, t1, sa_case_8 + mv s4, a2 + mv s0, a3 + jal ra, trigger_irq + mvsa_7: + cm.mvsa01 s4, s0 + nop + nop + j sa_case_end + + + + sa_case_8: + li t1, 8 + bne a0, t1, sa_case_9 + mv s5, a2 + mv s6, a3 + jal ra, trigger_irq + mvsa_8: + cm.mvsa01 s5, s6 + nop + nop + j sa_case_end + + + + sa_case_9: + li t1, 9 + bne a0, t1, sa_case_10 + mv s5, a2 + mv s3, a3 + jal ra, trigger_irq + mvsa_9: + cm.mvsa01 s5, s3 + nop + nop + j sa_case_end + + + + sa_case_10: + li t1, 10 + bne a0, t1, sa_case_11 + mv s5, a2 + mv s1, a3 + jal ra, trigger_irq + mvsa_10: + cm.mvsa01 s5, s1 + nop + nop + j sa_case_end + + + + sa_case_11: + li t1, 11 + bne a0, t1, sa_case_12 + mv s5, a2 + mv s0, a3 + jal ra, trigger_irq + mvsa_11: + cm.mvsa01 s5, s0 + nop + nop + j sa_case_end + + + + sa_case_12: + li t1, 12 + bne a0, t1, sa_case_13 + mv s7, a2 + mv s6, a3 + jal ra, trigger_irq + mvsa_12: + cm.mvsa01 s7, s6 + nop + nop + j sa_case_end + + + + sa_case_13: + li t1, 13 + bne a0, t1, sa_case_14 + mv s7, a2 + mv s3, a3 + jal ra, trigger_irq + mvsa_13: + cm.mvsa01 s7, s3 + nop + nop + j sa_case_end + + + + sa_case_14: + li t1, 14 + bne a0, t1, sa_case_15 + mv s7, a2 + mv s1, a3 + jal ra, trigger_irq + mvsa_14: + cm.mvsa01 s7, s1 + nop + nop + j sa_case_end + + + + sa_case_15: + li t1, 15 + bne a0, t1, sa_case_end + mv s7, a2 + mv s0, a3 + jal ra, trigger_irq + mvsa_15: + cm.mvsa01 s7, s0 + nop + nop + j sa_case_end + + + + sa_case_end: + //return to caller + la t0, stored_ra + lw ra, 0(t0) + jalr x0, 0(ra) + + + +interrupt_mvas: + la t0, stored_ra + sw ra, 0(t0) + + + as_case_0: + li t1, 0 + bne a0, t1, as_case_1 + mv s2, a2 + mv s6, a3 + jal ra, trigger_irq + mvas_0: + cm.mva01s s2, s6 + nop + nop + j as_case_end + + + + as_case_1: + li t1, 1 + bne a0, t1, as_case_2 + mv s2, a2 + mv s3, a3 + jal ra, trigger_irq + mvas_1: + cm.mva01s s2, s3 + nop + nop + j as_case_end + + + + as_case_2: + li t1, 2 + bne a0, t1, as_case_3 + mv s2, a2 + mv s1, a3 + jal ra, trigger_irq + mvas_2: + cm.mva01s s2, s1 + nop + nop + j as_case_end + + + + as_case_3: + li t1, 3 + bne a0, t1, as_case_4 + mv s2, a2 + mv s0, a3 + jal ra, trigger_irq + mvas_3: + cm.mva01s s2, s0 + nop + nop + j as_case_end + + + + as_case_4: + li t1, 4 + bne a0, t1, as_case_5 + mv s4, a2 + mv s6, a3 + jal ra, trigger_irq + mvas_4: + cm.mva01s s4, s6 + nop + nop + j as_case_end + + + + as_case_5: + li t1, 5 + bne a0, t1, as_case_6 + mv s4, a2 + mv s3, a3 + jal ra, trigger_irq + mvas_5: + cm.mva01s s4, s3 + nop + nop + j as_case_end + + + + as_case_6: + li t1, 6 + bne a0, t1, as_case_7 + mv s4, a2 + mv s1, a3 + jal ra, trigger_irq + mvas_6: + cm.mva01s s4, s1 + nop + nop + j as_case_end + + + + as_case_7: + li t1, 7 + bne a0, t1, as_case_8 + mv s4, a2 + mv s0, a3 + jal ra, trigger_irq + mvas_7: + cm.mva01s s4, s0 + nop + nop + j as_case_end + + + + as_case_8: + li t1, 8 + bne a0, t1, as_case_9 + mv s5, a2 + mv s6, a3 + jal ra, trigger_irq + mvas_8: + cm.mva01s s5, s6 + nop + nop + j as_case_end + + + + as_case_9: + li t1, 9 + bne a0, t1, as_case_10 + mv s5, a2 + mv s3, a3 + jal ra, trigger_irq + mvas_9: + cm.mva01s s5, s3 + nop + nop + j as_case_end + + + + as_case_10: + li t1, 10 + bne a0, t1, as_case_11 + mv s5, a2 + mv s1, a3 + jal ra, trigger_irq + mvas_10: + cm.mva01s s5, s1 + nop + nop + j as_case_end + + + + as_case_11: + li t1, 11 + bne a0, t1, as_case_12 + mv s5, a2 + mv s0, a3 + jal ra, trigger_irq + mvas_11: + cm.mva01s s5, s0 + nop + nop + j as_case_end + + + + as_case_12: + li t1, 12 + bne a0, t1, as_case_13 + mv s7, a2 + mv s6, a3 + jal ra, trigger_irq + mvas_12: + cm.mva01s s7, s6 + nop + nop + j as_case_end + + + + as_case_13: + li t1, 13 + bne a0, t1, as_case_14 + mv s7, a2 + mv s3, a3 + jal ra, trigger_irq + mvas_13: + cm.mva01s s7, s3 + nop + nop + j as_case_end + + + + as_case_14: + li t1, 14 + bne a0, t1, as_case_15 + mv s7, a2 + mv s1, a3 + jal ra, trigger_irq + mvas_14: + cm.mva01s s7, s1 + nop + nop + j as_case_end + + + + as_case_15: + li t1, 15 + bne a0, t1, as_case_end + mv s7, a2 + mv s0, a3 + jal ra, trigger_irq + mvas_15: + cm.mva01s s7, s0 + nop + nop + j as_case_end + + + + as_case_end: + //return to caller + la t0, stored_ra + lw ra, 0(t0) + jalr x0, 0(ra) + + + diff --git a/cv32e40s/tests/programs/custom/zc_test/zc_test.c b/cv32e40s/tests/programs/custom/zc_test/zc_test.c new file mode 100644 index 0000000000..3bac064f27 --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/zc_test.c @@ -0,0 +1,231 @@ +/* +** +** Copyright 2020 OpenHW Group +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +** +******************************************************************************* +** +** Directed test for Zc extension exersizes instructions and scenarios +** not likely to becovered by randomly +** generated tests. +** +******************************************************************************* +*/ + +#include +#include + +#include "zc_test.h" + +#define DEBUG_PRINT false + +// Program Functions // + +//trigger interrupt +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay) { + *TIMER_REG_ADDR = mask; + *TIMER_VAL_ADDR = 1 + cycle_delay; +} + +uint32_t vp_random_num(uint32_t upper_bound, uint32_t lower_bound) { + + if ((upper_bound == 0xFFFFFFFF) && (lower_bound == 0)) { + printf("ERROR: Illegal input value for function vp_random_num\n"); + printf("upper_bound = 0xFFFFFFFF and lower_bound = 0x0 causes overflow\n"); + exit(EXIT_FAILURE); + } + + uint32_t random_num = *((volatile uint32_t *) CV_VP_RANDOM_NUM_BASE); + uint32_t num = (random_num % (upper_bound - lower_bound + 1)) + lower_bound; + return num; +} + + +// Interrupt Handler // + +// external interrupt handler +__attribute__((interrupt ("machine"))) +void m_external_irq_handler(void) { + volatile uint32_t mepc = 0; + uint32_t ref = 0; + //fetching reference + switch (test_active) + { + case pushpop: + ref = pushpop_instr_list[test_instr_num]; + break; + + case popret: + ref = popret_instr_list[test_instr_num]; + break; + + case popretz: + ref = popretz_instr_list[test_instr_num]; + break; + + case mvsa: + ref = mvsa_instr_list[test_instr_num]; + break; + + case mvas: + ref = mvas_instr_list[test_instr_num]; + break; + + default: + printf("\tERROR: unrecognised test_active"); + failureCount += 1; + break; + } + test_instr_num += 1; + + if(DEBUG_PRINT){ + printf("external interrupt encountered\n"); + } + ex_traps_entered += 1; + + __asm__ volatile("csrrs %0, mepc, x0" : "=r"(mepc)); + if(DEBUG_PRINT){ + printf("returning to mepc: 0x%x \n", (unsigned int)mepc); + printf("comparing to: 0x%x \n", (unsigned int)ref); + } + + if(mepc == ref){ + printf("ERROR: illegal interrupt detected on mepc: 0x%x\n", (unsigned int)mepc); + failureCount += 1; + } else if(mepc != ref+2){ + printf("ERROR: testbench error detected on mepc: 0x%x\n", (unsigned int)mepc); + failureCount += 1; + } + +} + + + +int main(int argc, char *argv[]) +{ + exp_irq = 0; + failureCount = 0; + ex_traps_entered = 0; + test_instr_num = 0; + + + printf("Enabling irq. \n"); + + enable_all_irq(); + + printf("\n\nTesting push/pop instructions. \n"); + test_active = pushpop; + + for (int i = PUSH_RLIST_MIN; i <= PUSH_RLIST_MAX; i++) + { + glb_irq_line = 0x1 << EX_IRQ_LINE; + glb_irq_delay = vp_random_num(i-1, 2); + if(DEBUG_PRINT){ + printf("\n\ntesting rlist %d, with a delay of %u cycles \n", i, (unsigned int)glb_irq_delay); + } + exp_irq += 2; + interrupt_push_pop(i); + } + + printf("\n\nTesting popret instructions. \n"); + test_active = popret; + test_instr_num = 0; + + + for (int i = PUSH_RLIST_MIN; i <= PUSH_RLIST_MAX; i++) + { + glb_irq_line = 0x1 << EX_IRQ_LINE; + glb_irq_delay = vp_random_num(i-1, 2); + if(DEBUG_PRINT){ + printf("\n\ntesting rlist %d, with a delay of %u cycles \n", i, (unsigned int)glb_irq_delay); + } + exp_irq += 1; + interrupt_popret(i); + } + + printf("\n\nTesting popretz instructions. \n"); + test_active = popretz; + test_instr_num = 0; + + + for (int i = PUSH_RLIST_MIN; i <= PUSH_RLIST_MAX; i++) + { + glb_irq_line = 0x1 << EX_IRQ_LINE; + glb_irq_delay = vp_random_num(i-1, 2); + if(DEBUG_PRINT){ + printf("\n\ntesting rlist %d, with a delay of %u cycles \n", i, (unsigned int)glb_irq_delay); + } + exp_irq += 1; + interrupt_popretz(i); + } + + + printf("\n\nTesting mvsa01 instructions. \n"); + test_active = mvsa; + test_instr_num = 0; + //creating random values for the target registers + rnd0 = vp_random_num(0xFFFFFFFE, 0x0); + rnd1 = vp_random_num(0xFFFFFFFE, 0x0); + for (int i = 0; i < MVSA_INSTR_SIZE; i++) + { + glb_irq_line = 0x1 << EX_IRQ_LINE; + glb_irq_delay = 3; + if(DEBUG_PRINT){ + printf("\n\ntesting mvsa case %d, with a delay of %u cycles \n", i, (unsigned int)glb_irq_delay); + } + + exp_irq += 1; + iteratorVault = i; + interrupt_mvsa(i, rnd0, rnd1); + i = iteratorVault; + } + + printf("\n\nTesting mva01s instructions. \n"); + test_active = mvas; + test_instr_num = 0; + //creating random values for the target registers + rnd0 = vp_random_num(0xFFFFFFFE, 0x0); + rnd1 = vp_random_num(0xFFFFFFFE, 0x0); + for (int i = 0; i < MVAS_INSTR_SIZE; i++) + { + glb_irq_line = 0x1 << EX_IRQ_LINE; + glb_irq_delay = 3; + if(DEBUG_PRINT){ + printf("\n\ntesting mvsa case %d, with a delay of %u cycles \n", i, (unsigned int)glb_irq_delay); + } + + exp_irq += 1; + iteratorVault = i; + interrupt_mvas(i, rnd0, rnd1); + i = iteratorVault; + } + + + if(exp_irq != ex_traps_entered) { + printf("\tERROR: %u interrupts taken, expected %u", (unsigned int)ex_traps_entered, (unsigned int)exp_irq); + failureCount += 1; + } + else { + printf("%0u interrupts taken \n", (unsigned int)ex_traps_entered); + } + + if (failureCount) { + printf("\tERROR: %0u failures detected!\n\n", (unsigned int)failureCount); + return EXIT_FAILURE; + } + else { + printf("\n"); + return EXIT_SUCCESS; + } +} diff --git a/cv32e40s/tests/programs/custom/zc_test/zc_test.h b/cv32e40s/tests/programs/custom/zc_test/zc_test.h new file mode 100644 index 0000000000..ae2e2be8bf --- /dev/null +++ b/cv32e40s/tests/programs/custom/zc_test/zc_test.h @@ -0,0 +1,278 @@ +/* +** +** Copyright 2020 OpenHW Group +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +** +******************************************************************************* +** +** Directed test for Zc extension exersizes instructions and scenarios +** not likely to becovered by randomly +** generated tests. +** +******************************************************************************* +*/ + + +#ifndef __ZC_TEST_H__ +#define __ZC_TEST_H__ + +#include +#include +#include "corev_uvmt.h" +// Enable debug messages, note that this will change test timing +//#define DEBUG_MSG + +#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE)) +#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE + 4)) +#define EX_IRQ_LINE 11 + + +#define PUSH_RLIST_MIN 4 +#define PUSH_RLIST_MAX 15 + +enum ttype{ + pushpop, + popret, + popretz, + mvsa, + mvas +}; + + +// Global Variables // +volatile uint32_t ex_traps_entered; +volatile enum ttype test_active; +volatile uint32_t test_instr_num; +volatile uint32_t exp_irq; +volatile uint32_t failureCount; +volatile uint32_t rnd0; +volatile uint32_t rnd1; +volatile uint32_t iteratorVault; +extern volatile uint32_t glb_irq_line; +extern volatile uint32_t glb_irq_delay; + + +// Functions from Assebly file // + +// Assembly function to enable interrupts +extern volatile void enable_all_irq(); + +void vp_assert_irq(uint32_t mask, uint32_t cycle_delay); +uint32_t vp_random_num(uint32_t upper_bound, uint32_t lower_bound); + +__attribute__((interrupt ("machine"))) void m_external_irq_handler(void); + +// End of manual section // + +//Generated test functions +//functions time interrupts to hit atomic part of named instruction type +extern volatile void interrupt_push_pop(uint32_t); +extern volatile void interrupt_popret(uint32_t); +extern volatile void interrupt_popretz(uint32_t); +extern volatile void interrupt_mvsa(uint32_t, uint32_t, uint32_t); +extern volatile void interrupt_mvas(uint32_t, uint32_t, uint32_t); + + +//Generated list of push/pop instr addresses +#define PUSHPOP_INSTR_SIZE 24 + +extern uint32_t push_0; +extern uint32_t pop_0; +extern uint32_t push_1; +extern uint32_t pop_1; +extern uint32_t push_2; +extern uint32_t pop_2; +extern uint32_t push_3; +extern uint32_t pop_3; +extern uint32_t push_4; +extern uint32_t pop_4; +extern uint32_t push_5; +extern uint32_t pop_5; +extern uint32_t push_6; +extern uint32_t pop_6; +extern uint32_t push_7; +extern uint32_t pop_7; +extern uint32_t push_8; +extern uint32_t pop_8; +extern uint32_t push_9; +extern uint32_t pop_9; +extern uint32_t push_10; +extern uint32_t pop_10; +extern uint32_t push_11; +extern uint32_t pop_11; + +uint32_t pushpop_instr_list[PUSHPOP_INSTR_SIZE] = { + (uint32_t)&push_0, + (uint32_t)&pop_0, + (uint32_t)&push_1, + (uint32_t)&pop_1, + (uint32_t)&push_2, + (uint32_t)&pop_2, + (uint32_t)&push_3, + (uint32_t)&pop_3, + (uint32_t)&push_4, + (uint32_t)&pop_4, + (uint32_t)&push_5, + (uint32_t)&pop_5, + (uint32_t)&push_6, + (uint32_t)&pop_6, + (uint32_t)&push_7, + (uint32_t)&pop_7, + (uint32_t)&push_8, + (uint32_t)&pop_8, + (uint32_t)&push_9, + (uint32_t)&pop_9, + (uint32_t)&push_10, + (uint32_t)&pop_10, + (uint32_t)&push_11, + (uint32_t)&pop_11 +}; +//Generated list of popret instr addresses +#define POPRET_INSTR_SIZE 12 + +extern uint32_t popret_0; +extern uint32_t popret_1; +extern uint32_t popret_2; +extern uint32_t popret_3; +extern uint32_t popret_4; +extern uint32_t popret_5; +extern uint32_t popret_6; +extern uint32_t popret_7; +extern uint32_t popret_8; +extern uint32_t popret_9; +extern uint32_t popret_10; +extern uint32_t popret_11; + +uint32_t popret_instr_list[POPRET_INSTR_SIZE] = { + (uint32_t)&popret_0, + (uint32_t)&popret_1, + (uint32_t)&popret_2, + (uint32_t)&popret_3, + (uint32_t)&popret_4, + (uint32_t)&popret_5, + (uint32_t)&popret_6, + (uint32_t)&popret_7, + (uint32_t)&popret_8, + (uint32_t)&popret_9, + (uint32_t)&popret_10, + (uint32_t)&popret_11 +}; +//Generated list of popretz instr addresses +#define POPRETZ_INSTR_SIZE 12 + +extern uint32_t popretz_0; +extern uint32_t popretz_1; +extern uint32_t popretz_2; +extern uint32_t popretz_3; +extern uint32_t popretz_4; +extern uint32_t popretz_5; +extern uint32_t popretz_6; +extern uint32_t popretz_7; +extern uint32_t popretz_8; +extern uint32_t popretz_9; +extern uint32_t popretz_10; +extern uint32_t popretz_11; + +uint32_t popretz_instr_list[POPRET_INSTR_SIZE] = { + (uint32_t)&popretz_0, + (uint32_t)&popretz_1, + (uint32_t)&popretz_2, + (uint32_t)&popretz_3, + (uint32_t)&popretz_4, + (uint32_t)&popretz_5, + (uint32_t)&popretz_6, + (uint32_t)&popretz_7, + (uint32_t)&popretz_8, + (uint32_t)&popretz_9, + (uint32_t)&popretz_10, + (uint32_t)&popretz_11 +}; +//Generated list of mvsa instr addresses +#define MVSA_INSTR_SIZE 16 + +extern uint32_t mvsa_0; +extern uint32_t mvsa_1; +extern uint32_t mvsa_2; +extern uint32_t mvsa_3; +extern uint32_t mvsa_4; +extern uint32_t mvsa_5; +extern uint32_t mvsa_6; +extern uint32_t mvsa_7; +extern uint32_t mvsa_8; +extern uint32_t mvsa_9; +extern uint32_t mvsa_10; +extern uint32_t mvsa_11; +extern uint32_t mvsa_12; +extern uint32_t mvsa_13; +extern uint32_t mvsa_14; +extern uint32_t mvsa_15; + +uint32_t mvsa_instr_list[MVSA_INSTR_SIZE] = { + (uint32_t)&mvsa_0, + (uint32_t)&mvsa_1, + (uint32_t)&mvsa_2, + (uint32_t)&mvsa_3, + (uint32_t)&mvsa_4, + (uint32_t)&mvsa_5, + (uint32_t)&mvsa_6, + (uint32_t)&mvsa_7, + (uint32_t)&mvsa_8, + (uint32_t)&mvsa_9, + (uint32_t)&mvsa_10, + (uint32_t)&mvsa_11, + (uint32_t)&mvsa_12, + (uint32_t)&mvsa_13, + (uint32_t)&mvsa_14, + (uint32_t)&mvsa_15 +}; +//Generated list of mvas instr addresses +#define MVAS_INSTR_SIZE 16 + +extern uint32_t mvas_0; +extern uint32_t mvas_1; +extern uint32_t mvas_2; +extern uint32_t mvas_3; +extern uint32_t mvas_4; +extern uint32_t mvas_5; +extern uint32_t mvas_6; +extern uint32_t mvas_7; +extern uint32_t mvas_8; +extern uint32_t mvas_9; +extern uint32_t mvas_10; +extern uint32_t mvas_11; +extern uint32_t mvas_12; +extern uint32_t mvas_13; +extern uint32_t mvas_14; +extern uint32_t mvas_15; + +uint32_t mvas_instr_list[MVAS_INSTR_SIZE] = { + (uint32_t)&mvas_0, + (uint32_t)&mvas_1, + (uint32_t)&mvas_2, + (uint32_t)&mvas_3, + (uint32_t)&mvas_4, + (uint32_t)&mvas_5, + (uint32_t)&mvas_6, + (uint32_t)&mvas_7, + (uint32_t)&mvas_8, + (uint32_t)&mvas_9, + (uint32_t)&mvas_10, + (uint32_t)&mvas_11, + (uint32_t)&mvas_12, + (uint32_t)&mvas_13, + (uint32_t)&mvas_14, + (uint32_t)&mvas_15 +}; +#endif + diff --git a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test.sv b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test.sv index 493b3bd26a..0a58519062 100644 --- a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test.sv +++ b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test.sv @@ -41,7 +41,7 @@ class uvmt_cv32e40s_base_test_c extends uvm_test; uvme_cv32e40s_vsqr_c vsequencer; // Handles testbench interfaces - virtual uvmt_cv32e40s_vp_status_if vp_status_vif; // virtual peripheral status + virtual uvmt_cv32e40s_vp_status_if_t vp_status_vif; // virtual peripheral status // Default sequences rand uvme_cv32e40s_reset_vseq_c reset_vseq; @@ -199,7 +199,6 @@ class uvmt_cv32e40s_base_test_c extends uvm_test; endclass : uvmt_cv32e40s_base_test_c - function uvmt_cv32e40s_base_test_c::new(string name="uvmt_cv32e40s_base_test", uvm_component parent=null); super.new(name, parent); @@ -246,7 +245,6 @@ function void uvmt_cv32e40s_base_test_c::connect_phase(uvm_phase phase); endfunction : connect_phase function void uvmt_cv32e40s_base_test_c::end_of_elaboration_phase(uvm_phase phase); - super.end_of_elaboration_phase(phase); `uvm_info("BASE TEST", $sformatf("Top-level environment configuration:\n%s", env_cfg.sprint()), UVM_NONE) @@ -254,18 +252,16 @@ function void uvmt_cv32e40s_base_test_c::end_of_elaboration_phase(uvm_phase phas endfunction : end_of_elaboration_phase - task uvmt_cv32e40s_base_test_c::run_phase(uvm_phase phase); - super.run_phase(phase); watchdog_timer(); endtask : run_phase - task uvmt_cv32e40s_base_test_c::reset_phase(uvm_phase phase); + virtual uvmt_imperas_dv_if_t imperas_dv_if; super.reset_phase(phase); phase.raise_objection(this); @@ -276,6 +272,13 @@ task uvmt_cv32e40s_base_test_c::reset_phase(uvm_phase phase); reset_vseq.start(vsequencer); `uvm_info("BASE TEST", $sformatf("Finished reset virtual sequence:\n%s", reset_vseq.sprint()), UVM_NONE) + if(!(uvm_config_db#(virtual uvmt_imperas_dv_if_t)::get(.cntxt(null), .inst_name("uvm_test_top"), .field_name("idv_support_vif"), .value(imperas_dv_if)))) begin + `uvm_error("BASE TEST", "imperas_dv_if instance not found in uvm_config_db"); + end + if ($test$plusargs("USE_ISS")) begin + imperas_dv_if.ref_init(); + end + phase.drop_objection(this); endtask : reset_phase @@ -363,14 +366,14 @@ endfunction : post_randomize function void uvmt_cv32e40s_base_test_c::retrieve_vifs(); - if (!uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if)::get(this, "", "vp_status_vif", vp_status_vif)) begin + if (!uvm_config_db#(virtual uvmt_cv32e40s_vp_status_if_t)::get(this, "", "vp_status_vif", vp_status_vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vp_status_vif handle of type %s in uvm_config_db", $typename(vp_status_vif))) end else begin `uvm_info("VIF", $sformatf("Found vp_status_vif handle of type %s in uvm_config_db", $typename(vp_status_vif)), UVM_DEBUG) end - if (!uvm_config_db#(virtual uvme_cv32e40s_core_cntrl_if)::get(this, "", "core_cntrl_vif", env_cntxt.core_cntrl_cntxt.core_cntrl_vif)) begin + if (!uvm_config_db#(virtual uvme_cv32e40s_core_cntrl_if_t)::get(this, "", "core_cntrl_vif", env_cntxt.core_cntrl_cntxt.core_cntrl_vif)) begin `uvm_fatal("VIF", $sformatf("Could not find core_cntrl_vif handle of type %s in uvm_config_db", $typename(env_cntxt.core_cntrl_cntxt.core_cntrl_vif))) end else begin diff --git a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_constants.sv b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_constants.sv new file mode 100644 index 0000000000..2feb828cc4 --- /dev/null +++ b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_constants.sv @@ -0,0 +1,436 @@ +// +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +`ifndef __UVMT_CV32E40S_BASE_TEST_CONSTANTS_SV__ +`define __UVMT_CV32E40S_BASE_TEST_CONSTANTS_SV__ + + parameter uvme_cv32e40s_sys_default_clk_period = 1_500; // 10ns + parameter uvme_cv32e40s_debug_default_clk_period = 10_000; // 10ns + + // For RVFI/RVVI + parameter XLEN = 32; + parameter ILEN = 32; + parameter RVFI_NRET = 1; + + // For OBI + parameter ENV_PARAM_INSTR_ADDR_WIDTH = 32; + parameter ENV_PARAM_INSTR_DATA_WIDTH = 32; + parameter ENV_PARAM_INSTR_ACHK_WIDTH = 13; + parameter ENV_PARAM_INSTR_RCHK_WIDTH = 5; + parameter ENV_PARAM_DATA_ADDR_WIDTH = 32; + parameter ENV_PARAM_DATA_DATA_WIDTH = 32; + parameter ENV_PARAM_DATA_ACHK_WIDTH = 13; + parameter ENV_PARAM_DATA_RCHK_WIDTH = 5; + parameter ENV_PARAM_RAM_ADDR_WIDTH = 22; + + parameter ENV_PARAM_INSTR_AUSER_WIDTH = 0;//`UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH; + parameter ENV_PARAM_INSTR_WUSER_WIDTH = 0;//`UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH; + parameter ENV_PARAM_INSTR_RUSER_WIDTH = 0;//`UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH; + parameter ENV_PARAM_INSTR_ID_WIDTH = 0;//`UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH; + + parameter ENV_PARAM_DATA_AUSER_WIDTH = 0;//`UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH; + parameter ENV_PARAM_DATA_WUSER_WIDTH = 0;//`UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH; + parameter ENV_PARAM_DATA_RUSER_WIDTH = 0;//`UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH; + parameter ENV_PARAM_DATA_ID_WIDTH = 0;//`UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH; + // Control how often to print core scoreboard checked heartbeat messages + parameter PC_CHECKED_HEARTBEAT = 10_000; + + // Map the virtual peripheral registers + parameter CV_VP_REGISTER_BASE = 32'h0080_0000; + parameter CV_VP_REGISTER_SIZE = 32'h0000_1000; + + parameter CV_VP_VIRTUAL_PRINTER_OFFSET = 32'h0000_0000; + parameter CV_VP_RANDOM_NUM_OFFSET = 32'h0000_0040; + parameter CV_VP_CYCLE_COUNTER_OFFSET = 32'h0000_0080; + parameter CV_VP_STATUS_FLAGS_OFFSET = 32'h0000_00c0; + parameter CV_VP_FENCEI_TAMPER_OFFSET = 32'h0000_0100; + parameter CV_VP_INTR_TIMER_OFFSET = 32'h0000_0140; + parameter CV_VP_DEBUG_CONTROL_OFFSET = 32'h0000_0180; + parameter CV_VP_OBI_SLV_RESP_OFFSET = 32'h0000_01c0; + parameter CV_VP_SIG_WRITER_OFFSET = 32'h0000_0200; + + parameter CV_VP_VIRTUAL_PRINTER_BASE = CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET; + parameter CV_VP_RANDOM_NUM_BASE = CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET; + parameter CV_VP_CYCLE_COUNTER_BASE = CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET; + parameter CV_VP_STATUS_FLAGS_BASE = CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET; + parameter CV_VP_INTR_TIMER_BASE = CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET; + parameter CV_VP_DEBUG_CONTROL_BASE = CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET; + parameter CV_VP_OBI_SLV_RESP_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET; + parameter CV_VP_SIG_WRITER_BASE = CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET; + parameter CV_VP_FENCEI_TAMPER_BASE = CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET; + +`ifdef PARAM_SET_0 + `include "cvverif_param_set_0.svh" +`elsif PARAM_SET_1 + `include "cvverif_param_set_1.svh" +`endif + + +// Debug + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`elsif DBG_NUM_TRIG_0 + parameter CORE_PARAM_DBG_NUM_TRIGGERS = 0; +`elsif DBG_NUM_TRIG_1 + parameter CORE_PARAM_DBG_NUM_TRIGGERS = 1; +`elsif DBG_NUM_TRIG_2 + parameter CORE_PARAM_DBG_NUM_TRIGGERS = 2; +`elsif DBG_NUM_TRIG_3 + parameter CORE_PARAM_DBG_NUM_TRIGGERS = 3; +`elsif DBG_NUM_TRIG_4 + parameter CORE_PARAM_DBG_NUM_TRIGGERS = 4; +`else + parameter CORE_PARAM_DBG_NUM_TRIGGERS = 1; +`endif + +// CLIC + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`elsif CLIC_EN + parameter int CORE_PARAM_CLIC = 1; +`else + parameter int CORE_PARAM_CLIC = 0; +`endif +parameter logic CLIC = CORE_PARAM_CLIC; + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`else + parameter int CORE_PARAM_CLIC_ID_WIDTH = 5; +`endif + + +// B-ext + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`elsif ZBA_ZBB_ZBS + parameter cv32e40s_pkg::b_ext_e CORE_PARAM_B_EXT = cv32e40s_pkg::ZBA_ZBB_ZBS; +`elsif ZBA_ZBB_ZBC_ZBS + parameter cv32e40s_pkg::b_ext_e CORE_PARAM_B_EXT = cv32e40s_pkg::ZBA_ZBB_ZBC_ZBS; +`else + parameter cv32e40s_pkg::b_ext_e CORE_PARAM_B_EXT = cv32e40s_pkg::B_NONE; +`endif + + +// M-ext + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`else + parameter cv32e40s_pkg::m_ext_e CORE_PARAM_M_EXT = cv32e40s_pkg::M; +`endif + + +// I-base & E-base + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`elsif RV32E + parameter cv32e40s_pkg::rv32_e CORE_PARAM_RV32 = cv32e40s_pkg::RV32E; + parameter CORE_PARAM_REGFILE_NUM_WORDS = 16; +`else + parameter cv32e40s_pkg::rv32_e CORE_PARAM_RV32 = cv32e40s_pkg::RV32I; + parameter CORE_PARAM_REGFILE_NUM_WORDS = 32; +`endif + + +// Xsecure + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`elsif LFSR_CFG_0 + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR0_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h80000057, default_seed : 32'habbacafe }; + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR1_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h80000062, default_seed : 32'hbeef1234 }; + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR2_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h8000007a, default_seed : 32'ha5a5a5a5 }; +`else + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR0_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h80000057, default_seed : 32'habbacafe }; + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR1_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h80000062, default_seed : 32'hbeef1234 }; + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR2_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h8000007a, default_seed : 32'ha5a5a5a5 }; +`endif + + +`ifdef INTEGRITY_ERRORS_ENABLED + parameter logic INTEGRITY_ERRORS_ENABLED = 1; +`else + parameter logic INTEGRITY_ERRORS_ENABLED = 0; +`endif + + + +// PMP + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`elsif PMP_ENABLE_2 + parameter int CORE_PARAM_PMP_GRANULARITY = 0; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 2; +`elsif PMP_ENABLE_64 + parameter int CORE_PARAM_PMP_GRANULARITY = 0; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 64; +`elsif PMP_G0R0 + parameter int CORE_PARAM_PMP_GRANULARITY = 0; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 0; +`elsif PMP_G0R16 + parameter int CORE_PARAM_PMP_GRANULARITY = 0; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 16; +`elsif PMP_G1R5 + parameter int CORE_PARAM_PMP_GRANULARITY = 1; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 5; +`elsif PMP_G2R6 + parameter int CORE_PARAM_PMP_GRANULARITY = 2; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 6; +`elsif PMP_G3R3 + parameter int CORE_PARAM_PMP_GRANULARITY = 3; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 3; +`elsif PMP_G27R64 + parameter int CORE_PARAM_PMP_GRANULARITY = 27; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 64; +`else + parameter int CORE_PARAM_PMP_GRANULARITY = 0; + parameter int CORE_PARAM_PMP_NUM_REGIONS = 0; +`endif + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`else + parameter cv32e40s_pkg::mseccfg_t CORE_PARAM_PMP_MSECCFG_RV = cv32e40s_pkg::MSECCFG_DEFAULT; +`endif + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`else + parameter cv32e40s_pkg::pmpncfg_t CORE_PARAM_PMP_PMPNCFG_RV [CORE_PARAM_PMP_NUM_REGIONS-1:0] = '{ + default: cv32e40s_pkg::PMPNCFG_DEFAULT + }; +`endif + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`else + parameter logic [31:0] CORE_PARAM_PMP_PMPADDR_RV[CORE_PARAM_PMP_NUM_REGIONS-1:0] = '{ + default: 32'h 0 + }; +`endif + + +// PMA + +parameter int PMA_MAX_REGIONS = 16; + +`ifdef PARAM_SET_0 + // Sat from the include file +`elsif PARAM_SET_1 + // Sat from the include file +`elsif PMA_CUSTOM_CFG + const string pma_cfg_name = "pma_custom_cfg"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 3; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ + // Overlap "shadow" of main code (.text), for testing overlap priority + cv32e40s_pkg::pma_cfg_t'{ + word_addr_low : '0, + word_addr_high : ('h 1a11_0800 + 'd 16) >> 2, // should be identical to the prioritized region below + main : 0, // Would stop all execution, but should be overruled + bufferable : 0, + cacheable : 0, + integrity : 0}, + // Main code (.text) is executable up til into dbg region + cv32e40s_pkg::pma_cfg_t'{ + word_addr_low : '0, + word_addr_high : ('h 1a11_0800 + 'd 16) >> 2, // "dbg" address plus arbitrary offset to have a known usable area + main : 1, + bufferable : 1, + cacheable : 1, + integrity : 0}, + // Second portion of dbg up til end is exec + cv32e40s_pkg::pma_cfg_t'{ + word_addr_low : 'h 1A11_1000 >> 2, // after ".debugger" + word_addr_high : 'h FFFF_FFFF, + main : 1, + bufferable : 0, + cacheable : 0, + integrity : 0} + }; +`elsif PMA_DEBUG_CFG + const string pma_cfg_name = "pma_debug_cfg"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 2; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ + // Everything is initially executable + cv32e40s_pkg::pma_cfg_t'{ + word_addr_low : '0, + word_addr_high : 'h FFFF_FFFF, + main : 1, + bufferable : 0, + cacheable : 0, + integrity : 0}, + // A small region below "dbg" is forbidden to facilitate pma exception testing + cv32e40s_pkg::pma_cfg_t'{ + word_addr_low : ('h 1a11_0800 - 'd 16) >> 2, + word_addr_high : 'h 1a11_0800 >> 2, + main : 0, + bufferable : 0, + cacheable : 0, + integrity : 0} + }; +`elsif PMA_TEST_CFG_1 + const string pma_cfg_name = "pma_test_cfg_1"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 1; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[0:CORE_PARAM_PMA_NUM_REGIONS-1] = '{ + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h7FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b0} + }; +`elsif PMA_TEST_CFG_2 + const string pma_cfg_name = "pma_test_cfg_2"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 7; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ + '{word_addr_low : 32'hE010_0000>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b1}, + '{word_addr_low : 32'hE000_0000>>2, word_addr_high : 32'hE00F_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hA000_0000>>2, word_addr_high : 32'hDFFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h6000_0000>>2, word_addr_high : 32'h9FFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h4000_0000>>2, word_addr_high : 32'h5FFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h2000_0000>>2, word_addr_high : 32'h3FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h1FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b0} + }; +`elsif PMA_TEST_CFG_3 + const string pma_cfg_name = "pma_test_cfg_3"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ + '{word_addr_low : 32'h0000_A000>>2, word_addr_high : 32'hFFFE_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b1}, + '{word_addr_low : 32'h0200_0000>>2, word_addr_high : 32'hEFFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0500_0000>>2, word_addr_high : 32'h8459_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h1000_00F1>>2, word_addr_high : 32'h82FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h13AC_AA55>>2, word_addr_high : 32'h7FFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h2000_0000>>2, word_addr_high : 32'h63FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h2340_000A>>2, word_addr_high : 32'h600F_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h2A00_0000>>2, word_addr_high : 32'h56FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h2C5A_3200>>2, word_addr_high : 32'h52FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h3000_1353>>2, word_addr_high : 32'h5140_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h3100_FCAB>>2, word_addr_high : 32'h5000_BCCA>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h3420_C854>>2, word_addr_high : 32'h5000_ABFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h3600_A000>>2, word_addr_high : 32'h4F99_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h3ACE_0000>>2, word_addr_high : 32'h4ABC_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h4400_0000>>2, word_addr_high : 32'h4BFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h4800_0000>>2, word_addr_high : 32'h49FF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0} + }; +`elsif PMA_TEST_CFG_4 + const string pma_cfg_name = "pma_test_cfg_4"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h3201_0000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h3201_1000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ + '{word_addr_low : 32'hE700_EF00>>2, word_addr_high : 32'hE9FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b1}, + '{word_addr_low : 32'hC000_0000>>2, word_addr_high : 32'hDFFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hBC00_0000>>2, word_addr_high : 32'hBCFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hA000_0000>>2, word_addr_high : 32'hAFFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h6300_0000>>2, word_addr_high : 32'h6700_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h5400_0000>>2, word_addr_high : 32'h5FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h5100_0000>>2, word_addr_high : 32'h52FF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h4D00_5555>>2, word_addr_high : 32'h4FFF_ABCD>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h4AAA_F000>>2, word_addr_high : 32'h4C00_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h3440_0000>>2, word_addr_high : 32'h3800_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h3100_A000>>2, word_addr_high : 32'h32FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h2020_0010>>2, word_addr_high : 32'h2FFF_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h1800_1234>>2, word_addr_high : 32'h18FF_AB21>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h1000_0000>>2, word_addr_high : 32'h1001_0000>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0030_0000>>2, word_addr_high : 32'h04FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h0001_0000>>2, word_addr_high : 32'h001F_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0} + }; +`elsif PMA_TEST_CFG_5 + const string pma_cfg_name = "pma_test_cfg_5"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h0030_1000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h0030_2000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, integrity : 1'b1}, + '{word_addr_low : 32'h1249_2492>>2, word_addr_high : 32'h1249_2492>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hDB6D_B6DB>>2, word_addr_high : 32'hDB6D_B6DB>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h9249_2492>>2, word_addr_high : 32'h9249_2492>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hFFFF_FFFF>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hE38E_E38E>>2, word_addr_high : 32'hE38E_E38E>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hCCCC_CCCC>>2, word_addr_high : 32'hCCCC_CCCC>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'hAAAA_AAAA>>2, word_addr_high : 32'hAAAA_AAAA>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h5555_5555>>2, word_addr_high : 32'h5555_5555>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0}, + '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, integrity : 1'b0} + }; +`elsif PMA_TEST_CFG_X1 // Used for memory layout generator debug + const string pma_cfg_name = "pma_test_cfg_x1"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h0030_1000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h0030_2000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 5; + + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ + '{word_addr_low : 32'h00000000>>2, word_addr_high : 32'h20000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h30000000>>2, word_addr_high : 32'h40000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h50000000>>2, word_addr_high : 32'h60000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h70000000>>2, word_addr_high : 32'h80000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0}, + '{word_addr_low : 32'h00000000>>2, word_addr_high : 32'hF0000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, integrity : 1'b0} + }; +`else + const string pma_cfg_name = "pma_noregion"; + parameter logic [31:0] CORE_PARAM_DM_REGION_START = 32'h1A11_0000; + parameter logic [31:0] CORE_PARAM_DM_REGION_END = 32'h1A11_1000; + parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 0; + parameter cv32e40s_pkg::pma_cfg_t CORE_PARAM_PMA_CFG[-1:0] = '{default:cv32e40s_pkg::PMA_R_DEFAULT}; +`endif + +`endif //__UVMT_CV32E40S_BASE_TEST_CONSTANTS_SV__ + diff --git a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_pkg.sv b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_pkg.sv new file mode 100644 index 0000000000..6b117a534b --- /dev/null +++ b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_pkg.sv @@ -0,0 +1,34 @@ +// +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +`ifndef __UVMT_CV32E40S_BASE_TEST_PKG_SV__ +`define __UVMT_CV32E40S_BASE_TEST_PKG_SV__ + +// Pre-processor macros +`include "uvmt_cv32e40s_macros.sv" + +package uvmt_cv32e40s_base_test_pkg; + + import cv32e40s_pkg::*; + import uvm_pkg::*; + + `include "uvmt_cv32e40s_base_test_constants.sv" + `include "uvmt_cv32e40s_base_test_tdefs.sv" + +endpackage : uvmt_cv32e40s_base_test_pkg + +`endif // __UVMT_CV32E40S_BASE_TEST_PKG_SV__ + diff --git a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_tdefs.sv b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_tdefs.sv new file mode 100644 index 0000000000..e64405f7f3 --- /dev/null +++ b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_tdefs.sv @@ -0,0 +1,142 @@ +// +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMT_CV32E40S_BASE_TEST_TDEFS_SV__ +`define __UVMT_CV32E40S_BASE_TEST_TDEFS_SV__ + + +/** + * Test Program Type. See the Verification Strategy for a discussion of this. + */ +typedef enum { + PREEXISTING_SELFCHECKING, + PREEXISTING_NOTSELFCHECKING, + GENERATED_SELFCHECKING, + GENERATED_NOTSELFCHECKING, + NO_TEST_PROGRAM +} test_program_type; + +typedef enum { + FETCH_CONSTANT, + FETCH_INITIAL_DELAY_CONSTANT, + FETCH_RANDOM_TOGGLE +} fetch_toggle_t; + + +/** + * PMP reasons for accepting a request + */ +typedef struct packed { + logic r_mmode_r; + logic r_mmode_lr; + logic w_mmode_w; + logic w_mmode_lw; + logic x_mmode_x; + logic x_mmode_lx; + + logic r_umode_r; + logic w_umode_w; + logic x_umode_x; + + logic r_umode_mml_w; + logic r_umode_mml_wx; + logic r_umode_mml_r; + logic r_umode_mml_rx; + logic r_umode_mml_rw; + logic r_umode_mml_rwx; + logic r_umode_mml_lrwx; + + logic r_mmode_mml_w; + logic r_mmode_mml_wx; + logic r_mmode_mml_lwx; + logic r_mmode_mml_lr; + logic r_mmode_mml_lrx; + logic r_mmode_mml_lrw; + logic r_mmode_mml_lrwx; + + logic w_umode_mml_wx; + logic w_umode_mml_rw; + logic w_umode_mml_rwx; + + logic w_mmode_mml_w; + logic w_mmode_mml_wx; + logic w_mmode_mml_lrw; + + logic x_mmode_mml_lx; + logic x_mmode_mml_lw; + logic x_mmode_mml_lwx; + logic x_mmode_mml_lrx; + + logic x_umode_mml_x; + logic x_umode_mml_rx; + logic x_umode_mml_rwx; + logic x_umode_mml_lw; + logic x_umode_mml_lwx; + + logic r_mmode_nomatch_nommwp_r; + logic w_mmode_nomatch_nommwp_w; + logic x_mmode_nomatch_nommwp_x; +} access_rsn_t; + + +/** + * PMP matching status + */ +typedef struct packed { + logic is_access_allowed; + logic is_access_allowed_no_match; + logic is_any_locked; + logic is_dm_override; + logic is_locked; + logic is_matched; + logic is_rwx_ok; + access_rsn_t val_access_allowed_reason; + logic[$clog2(PMP_MAX_REGIONS)-1:0] val_index; +} match_status_t; + + +/** + * PMA Status + */ +typedef struct packed { + logic allow; + logic main; + logic bufferable; + logic cacheable; + logic integrity; + logic override_dm; + logic [PMA_MAX_REGIONS-1:0] match_list; + logic [31:0] match_idx; + logic have_match; + logic accesses_dmregion; + logic accesses_jvt; +} pma_status_t; + +typedef struct packed { + obi_data_req_t req; + obi_data_resp_t resp; + logic valid; +} obi_data_packet_t; + +typedef struct packed { + obi_inst_req_t req; + obi_inst_resp_t resp; + logic valid; +} obi_instr_packet_t; + + +`endif // __UVMT_CV32E40S_BASE_TEST_TDEFS_SV__ diff --git a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_test_cfg.sv b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_test_cfg.sv index 64f79ad2ec..8fdc661207 100644 --- a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_test_cfg.sv +++ b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_test_cfg.sv @@ -17,7 +17,7 @@ `ifndef __UVMT_CV32E40S_TEST_CFG_SV__ `define __UVMT_CV32E40S_TEST_CFG_SV__ - +import uvmt_cv32e40s_base_test_pkg::*; /** * Configuration object for testcases */ diff --git a/cv32e40s/tests/uvmt/compliance-tests/uvmt_cv32e40s_firmware_test.sv b/cv32e40s/tests/uvmt/compliance-tests/uvmt_cv32e40s_firmware_test.sv index f7a34a9d1b..8030c38955 100644 --- a/cv32e40s/tests/uvmt/compliance-tests/uvmt_cv32e40s_firmware_test.sv +++ b/cv32e40s/tests/uvmt/compliance-tests/uvmt_cv32e40s_firmware_test.sv @@ -34,11 +34,11 @@ */ class uvmt_cv32e40s_firmware_test_c extends uvmt_cv32e40s_base_test_c; - //constraint env_cfg_cons { - // env_cfg.enabled == 1; - // env_cfg.is_active == UVM_ACTIVE; - // env_cfg.trn_log_enabled == 1; - //} + constraint env_cfg_cons { + env_cfg.enabled == 1; + env_cfg.is_active == UVM_ACTIVE; + env_cfg.trn_log_enabled == 1; + } constraint test_type_cons { test_cfg.tpt == PREEXISTING_SELFCHECKING; @@ -79,6 +79,28 @@ class uvmt_cv32e40s_firmware_test_c extends uvmt_cv32e40s_base_test_c; */ extern virtual task irq_noise(); + /** + * Start the clic interrupt sequencer to apply random clic interrupts during test + */ + extern virtual task clic_noise(); + + /** + * Start the wfe wakeup sequencer to apply random wfe events during test + */ + extern virtual task wfe_wu_noise(); + + /** + * Start the nmi timeout watchdog to terminate tests a certain number of + * instructions after an nmi + */ + extern virtual task nmi_timeout(); + + /** + * Start the irq single-step timeout watchdog to terminate tests after + * a certain number of irqs and single step instructions has occurred + */ + extern virtual task irq_single_step_timeout(); + endclass : uvmt_cv32e40s_firmware_test_c @@ -116,10 +138,17 @@ task uvmt_cv32e40s_firmware_test_c::run_phase(uvm_phase phase); if ($test$plusargs("gen_irq_noise")) begin fork + clic_noise(); irq_noise(); join_none end + if ($test$plusargs("gen_wfe_wu_noise")) begin + fork + wfe_wu_noise(); + join_none + end + if ($test$plusargs("reset_debug")) begin fork reset_debug(); @@ -131,6 +160,18 @@ task uvmt_cv32e40s_firmware_test_c::run_phase(uvm_phase phase); join_none end + if (env.cfg.nmi_timeout_instr > 0) begin + fork + nmi_timeout(); + join_none + end + + if (env.cfg.irq_single_step_threshold > 0) begin + fork + irq_single_step_timeout(); + join_none + end + phase.raise_objection(this); @(posedge env_cntxt.clknrst_cntxt.vif.reset_n); repeat (33) @(posedge env_cntxt.clknrst_cntxt.vif.clk); @@ -174,30 +215,69 @@ task uvmt_cv32e40s_firmware_test_c::bootset_debug(); endtask task uvmt_cv32e40s_firmware_test_c::random_debug(); + uvme_cv32e40s_random_debug_c debug_vseq; `uvm_info("TEST", "Starting random debug in thread UVM test", UVM_NONE); - while (1) begin - uvme_cv32e40s_random_debug_c debug_vseq; - repeat (100) @(env_cntxt.debug_cntxt.vif.mon_cb); - debug_vseq = uvme_cv32e40s_random_debug_c::type_id::create("random_debug_vseqr"); - void'(debug_vseq.randomize()); - debug_vseq.start(vsequencer); - break; - end + repeat (100) @(env_cntxt.debug_cntxt.vif.mon_cb); + + debug_vseq = uvme_cv32e40s_random_debug_c::type_id::create("random_debug_vseqr"); + + void'(debug_vseq.randomize()); + debug_vseq.start(vsequencer); endtask : random_debug task uvmt_cv32e40s_firmware_test_c::irq_noise(); + uvme_cv32e40s_interrupt_noise_c interrupt_noise_vseq; `uvm_info("TEST", "Starting IRQ Noise thread in UVM test", UVM_NONE); - while (1) begin - uvme_cv32e40s_interrupt_noise_c interrupt_noise_vseq; - - interrupt_noise_vseq = uvme_cv32e40s_interrupt_noise_c::type_id::create("interrupt_noise_vseqr"); - assert(interrupt_noise_vseq.randomize() with { - reserved_irq_mask == 32'h0; - }); - interrupt_noise_vseq.start(vsequencer); - break; - end + + interrupt_noise_vseq = uvme_cv32e40s_interrupt_noise_c::type_id::create("interrupt_noise_vseqr"); + + assert(interrupt_noise_vseq.randomize() with { + reserved_irq_mask == 32'h0; + }); + interrupt_noise_vseq.start(vsequencer); endtask : irq_noise +task uvmt_cv32e40s_firmware_test_c::clic_noise(); + uvme_cv32e40s_clic_noise_c clic_noise_vseq; + `uvm_info("TEST", "Starting CLIC Noise thread in UVM test", UVM_NONE); + + clic_noise_vseq = uvme_cv32e40s_clic_noise_c::type_id::create("clic_noise_vseqr"); + + assert(clic_noise_vseq.randomize() with { }); + clic_noise_vseq.start(vsequencer); + +endtask : clic_noise + +task uvmt_cv32e40s_firmware_test_c::wfe_wu_noise(); + uvme_cv32e40s_wu_wfe_noise_vseq_c wfe_wu_noise_vseq; + `uvm_info("TEST", "Starting WFE Wake-up noise thread in UVM test", UVM_NONE); + + wfe_wu_noise_vseq = uvme_cv32e40s_wu_wfe_noise_vseq_c::type_id::create("wfe_wu_noise_vseqr"); + + assert(wfe_wu_noise_vseq.randomize() with { }); + wfe_wu_noise_vseq.start(vsequencer); + +endtask : wfe_wu_noise + +task uvmt_cv32e40s_firmware_test_c::nmi_timeout(); + uvme_cv32e40s_nmi_timeout_vseq_c nmi_timeout_vseq; + `uvm_info("TEST", "Starting NMI timeout watchdog in UVM test", UVM_NONE); + + nmi_timeout_vseq = uvme_cv32e40s_nmi_timeout_vseq_c::type_id::create("nmi_timout_vseqr"); + + assert(nmi_timeout_vseq.randomize() with {}); + nmi_timeout_vseq.start(vsequencer); +endtask : nmi_timeout + +task uvmt_cv32e40s_firmware_test_c::irq_single_step_timeout(); + uvme_cv32e40s_irq_ss_timeout_vseq_c irq_ss_timeout_vseq; + `uvm_info("TEST", "Starting IRQ/Single step timeout watchdog in UVM test", UVM_NONE); + + irq_ss_timeout_vseq = uvme_cv32e40s_irq_ss_timeout_vseq_c::type_id::create("irq_ss_timout_vseqr"); + + assert(irq_ss_timeout_vseq.randomize() with {}); + irq_ss_timeout_vseq.start(vsequencer); +endtask : irq_single_step_timeout + `endif // __UVMT_CV32E40S_FIRMWARE_TEST_SV__ diff --git a/cv32e40s/tests/uvmt/test-programs/vectors.S b/cv32e40s/tests/uvmt/test-programs/vectors.S index 8a177a6918..fb51dd9f77 100644 --- a/cv32e40s/tests/uvmt/test-programs/vectors.S +++ b/cv32e40s/tests/uvmt/test-programs/vectors.S @@ -15,6 +15,7 @@ */ .section .vectors, "ax" +.option push .option norvc vector_table: j sw_irq_handler @@ -58,6 +59,9 @@ new vector table (which is at mtvec) */ /* j __no_irq_handler */ /* j __no_irq_handler */ +.option pop + + .section .text.vecs /* exception handling */ __no_irq_handler: diff --git a/cv32e40s/vendor_lib/verilab/svlib_dpi.so b/cv32e40s/vendor_lib/verilab/svlib_dpi.so index c88d8ce14b..336c7c6168 100755 Binary files a/cv32e40s/vendor_lib/verilab/svlib_dpi.so and b/cv32e40s/vendor_lib/verilab/svlib_dpi.so differ diff --git a/cv32e40x/README.md b/cv32e40x/README.md index e36ced1a92..67a10a6f85 100644 --- a/cv32e40x/README.md +++ b/cv32e40x/README.md @@ -1,11 +1,8 @@ -# CV32E40X: Verification Environment for the CV32E40X CORE-V processor core. +The verification specifics for core cv32e40x are in a separate repository, (https://github.com/openhwgroup/cv32e40x-dv). To download the repository, do the following: -## Directories: -- **bsp**: the "board support package" for test-programs compiled/assembled/linked for the CV32E40X. This BSP is used by both the `core` testbench and the `uvmt` UVM verification environment. -- **env**: the UVM environment class and its associated infrastrucutre. -- **sim**: directory where you run the simulations. -- **tb**: the Testbench module that instanitates the core. -- **tests**: this is where all the testcases are. - -There are README files in each directory with additional information. +1) Make sure your pwd end folder is core-v-verif: +pwd = (...)/core-v-verif +2) Run the clonetb script from the bin folder with the x agrument as shown: +./bin/clonetb -x +The bin/clonetb script populates the cv32e40x folder with the content of cv32e40x-dv on a stable hash. Use git status to check the hash. diff --git a/cv32e40x/bsp/.gitignore b/cv32e40x/bsp/.gitignore deleted file mode 100644 index c0a1f349c4..0000000000 --- a/cv32e40x/bsp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -libcv-verif.a diff --git a/cv32e40x/bsp/Makefile b/cv32e40x/bsp/Makefile deleted file mode 100644 index a0e37bb77a..0000000000 --- a/cv32e40x/bsp/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -CV_SW_TOOLCHAIN ?= /opt/riscv -RISCV ?= $(CV_SW_TOOLCHAIN) -RISCV_EXE_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf- -RISCV_CC ?= gcc -RISCV_GCC = $(RISCV_EXE_PREFIX)$(RISCV_CC) -RISCV_AR = $(RISCV_EXE_PREFIX)ar -RISCV_MARCH ?= rv32imc -SRC = crt0.S handlers.S syscalls.c vectors.S -OBJ = crt0.o handlers.o syscalls.o vectors.o -LIBCV-VERIF = libcv-verif.a -CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(RISCV_MARCH) -Wall -pedantic $(RISCV_CFLAGS) - -all: $(LIBCV-VERIF) - -$(LIBCV-VERIF): $(OBJ) - $(RISCV_AR) rcs $@ $(OBJ) - -%.o : %.c - $(RISCV_GCC) $(CFLAGS) -c $< -o $@ - -%.o : %.S - $(RISCV_GCC) $(CFLAGS) -c $< -o $@ - -clean: - rm -f $(OBJ) $(LIBCV-VERIF) - - -vars: - @echo "make bsp variables:" - @echo " CV_SW_TOOLCHAIN = $(CV_SW_TOOLCHAIN)" - @echo " RISCV = $(RISCV)" - @echo " RISCV_EXE_PREFIX = $(RISCV_EXE_PREFIX)" - @echo " RISCV_GCC = $(RISCV_GCC)" - @echo " RISCV_MARCH = $(RISCV_MARCH)" - @echo " RISCV_CFLAGS = $(RISCV_CFLAGS)" - @echo " CFLAGS = $(CFLAGS)" diff --git a/cv32e40x/bsp/README.md b/cv32e40x/bsp/README.md deleted file mode 100644 index 2a86d5bf98..0000000000 --- a/cv32e40x/bsp/README.md +++ /dev/null @@ -1,166 +0,0 @@ -Board Support Package (BSP) for CV32E40X Verification -================================================= - -This BSP provides the code to support running programs on the CV32E40X verification -target. It performs initialization tasks (`crt0.S`), handles -interrupts/exceptions (`vectors.S`, `handlers.S`), provides syscall -implementations (`syscalls.c`) and includes a linker script (`link.ld`) to -control the placement of sections in the binary. - -Each file is described in more detail below followed by instructions for -building and using the BSP. - -C Runtime Initialization ------------------------- - -The C Runtime file `crt0.S` provides the `_start` function which is the entry -point of the program and performs the following tasks: - * Initialize global and stack pointer. - * Store the address of `vector_table` in `mtvec`, setting the lower two bits - to `0x2` to select vectored interrupt mode. - * Zero the BSS section. - * Invoke initialization of C constructors and set destructors to be called on - exit. - * Zero `argc` and `argv` (the stack is not initialized, so these are zeroed - to prevent uninitialized values causing a mismatch against the reference - result). - * Call `main`. - * If `main` returns, call `exit` with its return code. - -Interrupt and Exception Handling --------------------------------- - -When a RISC-V core traps on an interrupt/exception, the `pc` is stored in `mepc` -and the reason for the trap is stored in `mcause`. The `MSB` of `mcause` -is set to `0` for an exception and `1` for an interrupt; the remaining bits -`mcause[MXLEN-2:0]` contain the exception code. The table of `mcause` values is -defined in Table 3.6 of the [RISC-V Instruction Set Manual Volume II: Privileged -Architecture Version 20190608-Priv-MSU-Ratified](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf). - -The core jumps to a location in the vector table according to the `BASE` address -of the vector table stored in `mtvec` and the value of the exception code in -`mcause`. In vectored mode, all exceptions jump to `BASE` and interrupts jump to -`BASE+4*mcause[XLEN-2:0]`. Note that because user software interrupts have -exception code `0`, they jump to the same location as exceptions, therefore the -user software interrupt handler must also handle exceptions. - -The vector table is defined in `vectors.S` and may jump to one of the -following interrupt request handlers in `handlers.S`: - * `u_sw_irq_handler` - handles user software interrupts and all exceptions. - Saves all caller saved registers then checks `mcause` and jumps to the - appropriate handler as follows: - - Breakpoint: jump to `handle_ebreak`. - - Illegal instruction: jump to `handle_illegal`. - - Environment call from M-mode: jump to `handle_ecall`. - - Any other exception or user software interrupt: jump to `handle_unknown`. - * `m_software_irq_handler` - handles machine-mode software interrupts - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_timer_irq_handler` - handles machine-mode timer interrupts - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_external_irq_handler` - handles machine-mode external interrupts - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast0_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast1_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast2_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast3_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast4_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast5_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast6_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast7_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast8_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast9_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast10_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast11_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast12_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast13_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast14_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `m_fast15_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) - - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. - * `__no_irq_handler` - loops printing "no exception handler installed". - -The following exception handlers may be called from `u_sw_irq_handler`: - * `handle_ecall` - calls `handle_syscall` which checks the syscall number and - calls the corresponding syscall function. - * `handle_ebreak` - currently just prints "ebreak exception handler entered" - * `handle_illegal_insn` - prints "illegal instruction exception handler - entered" - * `unknown_handler` - called when there is no handler for the interrupt/ - exception. This is the only case where `mepc` is not incremented, because we - do not know the appropiate action to take. - -Returning from the `u_sw_irq_handler`. All handlers called by `u_sw_irq_handler` -increment `mepc` before calling `mret`, except for `unknown_handler`. Handlers -that require `mepc` to be incremented jump to `end_handler_incr_mepc` otherwise -they jump to `end_handler_ret`. All caller saved registers are restored before -finally calling `mret`. - -Some test cases require the ability to override the default handlers. In future, -these handlers will be made overridable by defining their labels as `.weak` -symbols. Test cases can then provide their own handlers where necessary. - -System Calls ------------- - -On a bare-metal system there is no OS to handle system calls, therefore, we -define our own system calls in `syscalls.c`. For example, the implementation of -`_write` outputs a byte at a time to the virtual printer peripheral. Many of the -functions provide minimal implementations that simply fail gracefully due to -lack of necessary OS support e.g. no file system. - -The [RISC-V Instruction Set Manual Volume I: Unprivileged ISA Version 20191213]( -https://content.riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf) states that -for an `ecall` the "ABI for the system will define how parameters for the -environment request are passed". This BSP follows the convention used for RISC-V -in `newlib`. Parameters are passed in registers `a0` to `a5` and system call ID -in `a7` (`t0` on RV32E). When handling an `ecall`, `handle_ecall` calls -`handle_syscall` which then calls the appropriate function that implements the -system call, passing parameters as necessary. - -Linker Script -------------- - -The linker script defines the memory layout and controls the mapping of input -sections from object files to output sections in the output binary. - -The `link.ld` script is based on the standard upstream RV32 linker script, with -some changes required for CV32E40X: - * Memory layout is defined as follows: - * `ram` start=0x0, length=4MB - * `dbg` start=0x1A110800, length=2KB - * Changes to output section placement are as follows: - - `.vectors` start=ORIGIN(`ram`) - - `.init` start=0x80 - - `.heap` starts at end of data and grows upwards - - `.stack` starts at the end of `ram` and grows downwards - - `.debugger` start=ORIGIN(`dbg`) - - `.debugger_exception` start=0x1A110C00 - - `.debugger_stack` follows `.debugger_exception` - -Building and using the BSP Library ----------------------------------- - -The BSP can be built in this directory as follows: -``` -make -``` -This produces libcv-verif.a which can then be linked with a test program as -follows: - -``` -gcc test-program.c -nostartfiles -T/path/to/bsp/link.ld -L/path/to/bsp/ -lcv-verif -``` diff --git a/cv32e40x/bsp/corev_uvmt.h b/cv32e40x/bsp/corev_uvmt.h deleted file mode 100644 index 30e460bb5a..0000000000 --- a/cv32e40x/bsp/corev_uvmt.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef __COREV_UVMT_H__ -#define __COREV_UVMT_H__ - -/* -** -** Copyright 2021 OpenHW Group -** Copyright 2021 Silicon Labs -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** CORE-V UVM Testbench (UVMT) defines -******************************************************************************* -*/ - -#define CV_VP_REGISTER_BASE 0x00800000 - -#define CV_VP_VIRTUAL_PRINTER_OFFSET 0x00000000 -#define CV_VP_RANDOM_NUM_OFFSET 0x00000040 -#define CV_VP_CYCLE_COUNTER_OFFSET 0x00000080 -#define CV_VP_STATUS_FLAGS_OFFSET 0x000000c0 -#define CV_VP_FENCEI_TAMPER_OFFSET 0x00000100 -#define CV_VP_INTR_TIMER_OFFSET 0x00000140 -#define CV_VP_DEBUG_CONTROL_OFFSET 0x00000180 -#define CV_VP_OBI_SLV_RESP_OFFSET 0x000001c0 -#define CV_VP_SIG_WRITER_OFFSET 0x00000200 - -#define CV_VP_VIRTUAL_PRINTER_BASE (CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET) -#define CV_VP_RANDOM_NUM_BASE (CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET) -#define CV_VP_CYCLE_COUNTER_BASE (CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET) -#define CV_VP_STATUS_FLAGS_BASE (CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET) -#define CV_VP_INTR_TIMER_BASE (CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET) -#define CV_VP_DEBUG_CONTROL_BASE (CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET) -#define CV_VP_OBI_SLV_RESP_BASE (CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET) -#define CV_VP_SIG_WRITER_BASE (CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET) -#define CV_VP_FENCEI_TAMPER_BASE (CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET) - -// -------------------------------------------------------------------------- -// Registers inside the OBI_SLV_RESP VP -// -------------------------------------------------------------------------- -#define CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MIN ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 4*0)) -#define CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MAX ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 4*1)) -#define CV_VP_OBI_SLV_RESP_I_ERR_VALID ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 4*2)) -#define CV_VP_OBI_SLV_RESP_I_EXOKAY_ADDR_MIN ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 4*3)) -#define CV_VP_OBI_SLV_RESP_I_EXOKAY_ADDR_MAX ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 4*4)) -#define CV_VP_OBI_SLV_RESP_I_EXOKAY_VALID ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 4*5)) - -#define CV_VP_OBI_SLV_RESP_D_ERR_ADDR_MIN ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*0)) -#define CV_VP_OBI_SLV_RESP_D_ERR_ADDR_MAX ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*1)) -#define CV_VP_OBI_SLV_RESP_D_ERR_VALID ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*2)) -#define CV_VP_OBI_SLV_RESP_D_EXOKAY_ADDR_MIN ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*3)) -#define CV_VP_OBI_SLV_RESP_D_EXOKAY_ADDR_MAX ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*4)) -#define CV_VP_OBI_SLV_RESP_D_EXOKAY_VALID ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*5)) - -// Bitfields for Debug Control VP register -#define CV_VP_DEBUG_CONTROL_DBG_REQ(i) ((i) << 31) -#define CV_VP_DEBUG_CONTROL_REQ_MODE(i) ((i) << 30) -#define CV_VP_DEBUG_CONTROL_RAND_PULSE_DURATION(i) ((i) << 29) -#define CV_VP_DEBUG_CONTROL_PULSE_DURATION(i) ((i) << 16) -#define CV_VP_DEBUG_CONTROL_RAND_START_DELAY(i) ((i) << 15) -#define CV_VP_DEBUG_CONTROL_START_DELAY(i) ((i) << 0) - -#endif diff --git a/cv32e40x/bsp/handlers.S b/cv32e40x/bsp/handlers.S deleted file mode 100644 index 9b3d56b82e..0000000000 --- a/cv32e40x/bsp/handlers.S +++ /dev/null @@ -1,321 +0,0 @@ -/* -* Copyright 2019 ETH Zürich and University of Bologna -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/* Exception codes */ -#define EXCEPTION_INSN_ACCESS_FAULT 1 -#define EXCEPTION_ILLEGAL_INSN 2 -#define EXCEPTION_BREAKPOINT 3 -#define EXCEPTION_LOAD_ACCESS_FAULT 5 -#define EXCEPTION_STORE_ACCESS_FAULT 7 -#define EXCEPTION_ECALL_M 11 -#define EXCEPTION_INSN_BUS_FAULT 48 - -/* NMI interrupt codes */ -#define INTERRUPT_LOAD_BUS_FAULT (128 | (0x1 << 31)) -#define INTERRUPT_STORE_BUS_FAULT (129 | (0x1 << 31)) - -.section .text.handlers -.global __no_irq_handler -.global u_sw_irq_handler -.global m_software_irq_handler -.global m_timer_irq_handler -.global m_external_irq_handler -.global m_fast0_irq_handler -.global m_fast1_irq_handler -.global m_fast2_irq_handler -.global m_fast3_irq_handler -.global m_fast4_irq_handler -.global m_fast5_irq_handler -.global m_fast6_irq_handler -.global m_fast7_irq_handler -.global m_fast8_irq_handler -.global m_fast9_irq_handler -.global m_fast10_irq_handler -.global m_fast11_irq_handler -.global m_fast12_irq_handler -.global m_fast13_irq_handler -.global m_fast14_irq_handler -.global m_fast15_irq_handler -.global end_handler_ret - -.weak __no_irq_handler -.weak u_sw_irq_handler -.weak m_software_irq_handler -.weak m_timer_irq_handler -.weak m_external_irq_handler -.weak m_fast0_irq_handler -.weak m_fast1_irq_handler -.weak m_fast2_irq_handler -.weak m_fast3_irq_handler -.weak m_fast4_irq_handler -.weak m_fast5_irq_handler -.weak m_fast6_irq_handler -.weak m_fast7_irq_handler -.weak m_fast8_irq_handler -.weak m_fast9_irq_handler -.weak m_fast10_irq_handler -.weak m_fast11_irq_handler -.weak m_fast12_irq_handler -.weak m_fast13_irq_handler -.weak m_fast14_irq_handler -.weak m_fast15_irq_handler - -.weak handle_insn_access_fault -.weak handle_insn_bus_fault - -/* exception handling */ -__no_irq_handler: - la a0, no_exception_handler_msg - jal ra, puts - j __no_irq_handler - -m_software_irq_handler: - j __no_irq_handler - -m_timer_irq_handler: - j __no_irq_handler - -m_external_irq_handler: - j __no_irq_handler - -m_fast0_irq_handler: - j __no_irq_handler - -m_fast1_irq_handler: - j __no_irq_handler - -m_fast2_irq_handler: - j __no_irq_handler - -m_fast3_irq_handler: - j __no_irq_handler - -m_fast4_irq_handler: - j __no_irq_handler - -m_fast5_irq_handler: - j __no_irq_handler - -m_fast6_irq_handler: - j __no_irq_handler - -m_fast7_irq_handler: - j __no_irq_handler - -m_fast8_irq_handler: - j __no_irq_handler - -m_fast9_irq_handler: - j __no_irq_handler - -m_fast10_irq_handler: - j __no_irq_handler - -m_fast11_irq_handler: - j __no_irq_handler - -m_fast12_irq_handler: - j __no_irq_handler - -m_fast13_irq_handler: - j __no_irq_handler - -m_fast14_irq_handler: - j __no_irq_handler - -m_fast15_irq_handler: - j __no_irq_handler - -u_sw_irq_handler: - /* While we are still using puts in handlers, save all caller saved - regs. Eventually, some of these saves could be deferred. */ - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr t0, mcause - li t1, EXCEPTION_INSN_ACCESS_FAULT - beq t0, t1, handle_insn_access_fault - li t1, EXCEPTION_ILLEGAL_INSN - beq t0, t1, handle_illegal_insn - li t1, EXCEPTION_ECALL_M - beq t0, t1, handle_ecall - li t1, EXCEPTION_BREAKPOINT - beq t0, t1, handle_ebreak - li t1, EXCEPTION_INSN_BUS_FAULT - beq t0, t1, handle_insn_bus_fault - j handle_unknown - -handle_ecall: - jal ra, handle_syscall - j end_handler_incr_mepc - -handle_ebreak: - /* TODO support debug handling requirements. */ - la a0, ebreak_msg - jal ra, puts - j end_handler_incr_mepc - -handle_illegal_insn: - la a0, illegal_insn_msg - jal ra, puts - j end_handler_incr_mepc - -handle_insn_access_fault: - la a0, insn_access_fault_msg - jal ra, puts - j end_handler_incr_mepc - -handle_insn_bus_fault: - la a0, insn_bus_fault_msg - jal ra, puts - /* Do not advnace the mepc, tests should handle this appropriately */ - j end_handler_ret - -handle_unknown: - la a0, unknown_msg - jal ra, puts - /* We don't know what interrupt/exception is being handled, so don't - increment mepc. */ - j end_handler_ret - -end_handler_incr_mepc: - csrr t0, mepc - lb t1, 0(t0) - li a0, 0x3 - and t1, t1, a0 - /* Increment mepc by 2 or 4 depending on whether the instruction at mepc - is compressed or not. */ - bne t1, a0, end_handler_incr_mepc2 - addi t0, t0, 2 -end_handler_incr_mepc2: - addi t0, t0, 2 - csrw mepc, t0 -end_handler_ret: - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret - -.weak handle_data_load_bus_fault -.weak handle_data_store_bus_fault - -.section .nmi, "ax" -.global nmi_handler -.global nmi_end_handler_ret - -nmi_handler: - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr t0, mcause - li t1, INTERRUPT_LOAD_BUS_FAULT - beq t0, t1, handle_data_load_bus_fault - li t1, INTERRUPT_STORE_BUS_FAULT - beq t0, t1, handle_data_store_bus_fault - - j nmi_end_handler_ret - -handle_data_load_bus_fault: - la a0, data_load_bus_fault_msg - jal ra, puts - j nmi_end_handler_ret - -handle_data_store_bus_fault: - la a0, data_store_bus_fault_msg - jal ra, puts - j nmi_end_handler_ret - -nmi_end_handler_ret: - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret - -.section .rodata -data_load_bus_fault_msg: - .string "CV32E40X BSP: data load bus fault exception handler entered\n" -data_store_bus_fault_msg: - .string "CV32E40X BSP: data store bus fault exception handler entered\n" -insn_access_fault_msg: - .string "CV32E40X BSP: instruction access fault exception handler entered\n" -insn_bus_fault_msg: - .string "CV32E40X BSP: instruction bus fault exception handler entered\n" -illegal_insn_msg: - .string "CV32E40X BSP: illegal instruction exception handler entered\n" -ecall_msg: - .string "CV32E40X BSP: ecall exception handler entered\n" -ebreak_msg: - .string "CV32E40X BSP: ebreak exception handler entered\n" -unknown_msg: - .string "CV32E40X BSP: unknown exception handler entered\n" -no_exception_handler_msg: - .string "CV32E40X BSP: no exception handler installed\n" diff --git a/cv32e40x/bsp/link.ld b/cv32e40x/bsp/link.ld deleted file mode 100644 index e765bf77bb..0000000000 --- a/cv32e40x/bsp/link.ld +++ /dev/null @@ -1,324 +0,0 @@ -/* Script for -z combreloc */ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. - Copyright (C) 2019 ETH Zürich and University of Bologna - Copyright (C) 2020 OpenHW Group - Copying and distribution of this script, with or without modification, - are permitted in any medium without royalty provided the copyright - notice and this notice are preserved. */ - -/* This linker script is adapted from the default linker script for upstream - RISC-V GCC. It has been modified for use in verification of CORE-V cores. -*/ - -OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", - "elf32-littleriscv") -OUTPUT_ARCH(riscv) -ENTRY(_start) - -/* CORE-V */ -MEMORY -{ - /* Our testbench is a bit weird in that we initialize the RAM (thus - allowing initialized sections to be placed there). Infact we dump all - sections to ram. */ - - ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 - dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000 -} - -SECTIONS -{ - /* CORE-V Debugger Code: This section address must be the same as the - DM_HaltAddress parameter in the RTL */ - .debugger (ORIGIN(dbg)): - { - KEEP(*(.debugger)); - } >dbg - .debugger_exception (0x1A111000): - { - KEEP(*(.debugger_exception)); - } >dbg - /* Debugger Stack*/ - .debugger_stack : ALIGN(16) - { - PROVIDE(__debugger_stack_start = .); - . = 0x80; - } >dbg - - - /* NMI interrupt handler fixed entry point */ - PROVIDE(__nmi_address = 0x100000); - - .nmi (__nmi_address): - { - KEEP(*(.nmi)); - } >ram - - /* CORE-V: we want a fixed entry point */ - PROVIDE(__boot_address = 0x80); - - /* CORE-V: interrupt vectors */ - .vectors (ORIGIN(ram)): - { - PROVIDE(__vector_start = .); - KEEP(*(.vectors)); - } >ram - - /* CORE-V: crt0 init code */ - .init (__boot_address): - { - KEEP (*(SORT_NONE(.init))) - KEEP (*(.text.start)) - } >ram - - - /* Read-only sections, merged into text segment: */ - PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS; - .interp : { *(.interp) } >ram - .note.gnu.build-id : { *(.note.gnu.build-id) } >ram - .hash : { *(.hash) } >ram - .gnu.hash : { *(.gnu.hash) } >ram - .dynsym : { *(.dynsym) } >ram - .dynstr : { *(.dynstr) } >ram - .gnu.version : { *(.gnu.version) } >ram - .gnu.version_d : { *(.gnu.version_d) } >ram - .gnu.version_r : { *(.gnu.version_r) } >ram - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - PROVIDE_HIDDEN (__rela_iplt_start = .); - *(.rela.iplt) - PROVIDE_HIDDEN (__rela_iplt_end = .); - } >ram - .rela.plt : - { - *(.rela.plt) - } >ram - - .plt : { *(.plt) } - .iplt : { *(.iplt) } - .text : - { - *(.text.unlikely .text.*_unlikely .text.unlikely.*) - *(.text.exit .text.exit.*) - *(.text.startup .text.startup.*) - *(.text.hot .text.hot.*) - *(SORT(.text.sorted.*)) - *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf.em. */ - *(.gnu.warning) - } >ram - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >ram - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram - .rodata1 : { *(.rodata1) } >ram - .sdata2 : - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } >ram - .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram - .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >ram - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram - .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >ram - .gnu_extab : ONLY_IF_RO { *(.gnu_extab*) } >ram - /* These sections are generated by the Sun/Oracle C++ compiler. */ - .exception_ranges : ONLY_IF_RO { *(.exception_ranges*) } - /* Adjust the address for the data segment. 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IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, - * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM - * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR - * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "corev_uvmt.h" -#undef errno -extern int errno; - -/* write to this reg for outputting strings */ -#define STDOUT_REG CV_VP_VIRTUAL_PRINTER_BASE -/* write test result of program to this reg */ -#define RESULT_REG (CV_VP_STATUS_FLAGS_BASE) -/* write exit value of program to this reg */ -#define EXIT_REG (CV_VP_STATUS_FLAGS_BASE + 4) - -#define STDOUT_FILENO 1 - -/* It turns out that older newlib versions use different symbol names which goes - * against newlib recommendations. Anyway this is fixed in later version. - */ -#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5 -#define _sbrk sbrk -#define _write write -#define _close close -#define _lseek lseek -#define _read read -#define _fstat fstat -#define _isatty isatty -#endif -/* Upstream newlib now defines this in libgloss/riscv/internal_syscall.h. */ -long -__syscall_error(long a0) -{ - errno = -a0; - return -1; -} - -void unimplemented_syscall() -{ - const char *p = "BSP: Unimplemented system call called!\n"; - while (*p) - *(volatile int *)STDOUT_REG = *(p++); -} - -int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) -{ - errno = ENOSYS; - return -1; -} - -int _access(const char *file, int mode) -{ - errno = ENOSYS; - return -1; -} - -int _chdir(const char *path) -{ - errno = ENOSYS; - return -1; -} - -int _chmod(const char *path, mode_t mode) -{ - errno = ENOSYS; - return -1; -} - -int _chown(const char *path, uid_t owner, gid_t group) -{ - errno = ENOSYS; - return -1; -} - -int _close(int file) -{ - return -1; -} - -int _execve(const char *name, char *const argv[], char *const env[]) -{ - errno = ENOMEM; - return -1; -} - -void _exit(int exit_status) -{ - *(volatile int *)EXIT_REG = exit_status; - __asm__ volatile("wfi"); - /* _exit should not return */ - while (1) {}; -} - -int _faccessat(int dirfd, const char *file, int mode, int flags) -{ - errno = ENOSYS; - return -1; -} - -int _fork(void) -{ - errno = EAGAIN; - return -1; -} - -int _fstat(int file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; - // errno = -ENOSYS; - // return -1; -} - -int _fstatat(int dirfd, const char *file, struct stat *st, int flags) -{ - errno = ENOSYS; - return -1; -} - -int _ftime(struct timeb *tp) -{ - errno = ENOSYS; - return -1; -} - -char *_getcwd(char *buf, size_t size) -{ - errno = -ENOSYS; - return NULL; -} - -int _getpid() -{ - return 1; -} - -int _gettimeofday(struct timeval *tp, void *tzp) -{ - errno = -ENOSYS; - return -1; -} - -int _isatty(int file) -{ - return (file == STDOUT_FILENO); -} - -int _kill(int pid, int sig) -{ - errno = EINVAL; - return -1; -} - -int _link(const char *old_name, const char *new_name) -{ - errno = EMLINK; - return -1; -} - -off_t _lseek(int file, off_t ptr, int dir) -{ - return 0; -} - -int _lstat(const char *file, struct stat *st) -{ - errno = ENOSYS; - return -1; -} - -int _open(const char *name, int flags, int mode) -{ - return -1; -} - -int _openat(int dirfd, const char *name, int flags, int mode) -{ - errno = ENOSYS; - return -1; -} - -ssize_t _read(int file, void *ptr, size_t len) -{ - return 0; -} - -int _stat(const char *file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; - // errno = ENOSYS; - // return -1; -} - -long _sysconf(int name) -{ - - return -1; -} - -clock_t _times(struct tms *buf) -{ - return -1; -} - -int _unlink(const char *name) -{ - errno = ENOENT; - return -1; -} - -int _utime(const char *path, const struct utimbuf *times) -{ - errno = ENOSYS; - return -1; -} - -int _wait(int *status) -{ - errno = ECHILD; - return -1; -} - -ssize_t _write(int file, const void *ptr, size_t len) -{ - const char *cptr = (char *)ptr; - if (file != STDOUT_FILENO) - { - errno = ENOSYS; - return -1; - } - - const void *eptr = cptr + len; - while (cptr != eptr) - *(volatile int *)STDOUT_REG = *cptr++; - return len; -} - -extern char __heap_start[]; -extern char __heap_end[]; -static char *brk = __heap_start; - -int _brk(void *addr) -{ - brk = addr; - return 0; -} - -void *_sbrk(ptrdiff_t incr) -{ - char *old_brk = brk; - volatile uint32_t sp; - - char *new_brk = brk += incr; - __asm__ volatile("mv %0, x2" : "=r"(sp) : : ); - - if (new_brk < (char *) sp && new_brk < __heap_end) - { - brk = new_brk; - - return old_brk; - } - else - { - errno = ENOMEM; - return (void *) -1; - } -} - -void handle_syscall (long a0, - long a1, - long a2, - long a3, - __attribute__((unused)) long a4, - __attribute__((unused)) long a5, - __attribute__((unused)) long a6, - long a7) { - #ifdef __riscv_32e - register long syscall_id asm("t0"); - #else - long syscall_id = a7; - #endif - - switch (syscall_id) { - case SYS_exit: - _exit (a0); - break; - case SYS_read: - _read (a0, (void *) a1, a2); - break; - case SYS_write: - _write (a0, (const void *) a1, a2); - break; - case SYS_getpid: - _getpid (); - break; - case SYS_kill: - _kill (a0, a1); - break; - case SYS_open: - _open ((const char *) a0, a1, a2); - break; - case SYS_openat: - _openat (a0, (const char *) a1, a2, a3); - break; - case SYS_close: - _close (a0); - break; - case SYS_lseek: - _lseek (a0, a1, a2); - break; - case SYS_brk: - _brk ((void *) a0); - break; - case SYS_link: - _link ((const char *) a0, (const char *) a1); - break; - case SYS_unlink: - _unlink ((const char *) a0); - break; - case SYS_chdir: - _chdir ((const char *) a0); - break; - case SYS_getcwd: - _getcwd ((char *) a0, a1); - break; - case SYS_stat: - _stat ((const char *) a0, (struct stat *) a1); - break; - case SYS_fstat: - _fstat (a0, (struct stat *) a1); - break; - case SYS_lstat: - _lstat ((const char *) a0, (struct stat *) a1); - break; - case SYS_fstatat: - _fstatat (a0, (const char *) a1, (struct stat *) a2, a3); - break; - case SYS_access: - _access ((const char *) a0, a1); - break; - case SYS_faccessat: - _faccessat (a0, (const char *) a1, a2, a3); - break; - case SYS_gettimeofday: - _gettimeofday ((struct timeval *) a0, (void *) a1); - break; - case SYS_times: - _times ((struct tms *) a0); - break; - default: - unimplemented_syscall (); - break; - } -} diff --git a/cv32e40x/bsp/vectors.S b/cv32e40x/bsp/vectors.S deleted file mode 100644 index 08af4128ae..0000000000 --- a/cv32e40x/bsp/vectors.S +++ /dev/null @@ -1,54 +0,0 @@ -/* -* Copyright 2019 ETH Zürich and University of Bologna -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -.section .vectors, "ax" -.option norvc -.global vector_table - -vector_table: - j u_sw_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_software_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_timer_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_external_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_fast0_irq_handler - j m_fast1_irq_handler - j m_fast2_irq_handler - j m_fast3_irq_handler - j m_fast4_irq_handler - j m_fast5_irq_handler - j m_fast6_irq_handler - j m_fast7_irq_handler - j m_fast8_irq_handler - j m_fast9_irq_handler - j m_fast10_irq_handler - j m_fast11_irq_handler - j m_fast12_irq_handler - j m_fast13_irq_handler - j m_fast14_irq_handler - j m_fast15_irq_handler - diff --git a/cv32e40x/docs/VerifPlans/Formal/base_instruction_set/.gitkeep b/cv32e40x/docs/VerifPlans/Formal/base_instruction_set/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/cv32e40x/docs/VerifPlans/README.md b/cv32e40x/docs/VerifPlans/README.md deleted file mode 100644 index 16af6e07d0..0000000000 --- a/cv32e40x/docs/VerifPlans/README.md +++ /dev/null @@ -1,48 +0,0 @@ - -This is the root directory of the CV32E40X Verification Plan (aka Test Plan). -Each sub-directory is the verification plan for a specific CV32E40X high-level feature of the same name. - -Use the provided CORE-V_Simulation VerifPlan_Template.xlsx spreadsheet as your template to capture a Verification Plan. - -## Verification Plan Status - -The tables below capture the current status of the Verification Plan for the CV32E40P by high-level feature. Under the heading `Review` is one of following: -* **Ready for Review**: Vplan has been captured and is awaiting review. -* **Reviewed**: Vplan has been reviewed, and is waiting for updates to address review feedback. -* **Waiting for Signoff**: Vplan has been reviewed and review comments addressed by the author. Document is now waiting for reviewers to signoff on the post-review updates. -* **Complete**: Post-preview updates have been signed-off. - -### Base instruction set plus standard instruction extensions - -_Refer to the VerifPlans/ISA/RV32/Simulation directory for specific Verification Plan status for each supported extension._ -### Interrupts - -| Feature | Capture | Review | Comment | -|---------|---------|--------|---------| -| CLINT | Incomplete | Incomplete | | - -### Debug & Trigger - -| Feature | Capture | Review | Comment | -|---------|---------|--------|---------| -| Debug | Incomplete | Incomplete | | -| Trigger module | Incomplete | Incomplete | | - -### Privileged spec - -| Feature | Capture | Review | Comment | -|---------|---------|--------|---------| -| CSRs | Incomplete | Incomplete | | -| PMA | Complete | Ready For Review | | -| User mode | N/A| N/A | Not a CV32E40X Feature | - -### Micro-architecure - -| Feature | Capture | Review | Comment | -|---------|---------|--------|---------| -| OBI | Inomplete | Incomplete | | -| Sleep Unit | Incomplete | Incomplete | | -| Pipelines | Incomplete | Incomplete | | -| Bus errors | Complete | Complete || -| Bus errors | Complete | Complete | Reviewed and Interated on 8/27/21 | - diff --git a/cv32e40x/docs/VerifPlans/Simulation/VplanStatusReviews.xlsx b/cv32e40x/docs/VerifPlans/Simulation/VplanStatusReviews.xlsx deleted file mode 100644 index e802c8e2c0..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/VplanStatusReviews.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/bus_error/CV32E40X_VerifPlan_Bus_Error.xlsx b/cv32e40x/docs/VerifPlans/Simulation/bus_error/CV32E40X_VerifPlan_Bus_Error.xlsx deleted file mode 100755 index b69626b8e5..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/bus_error/CV32E40X_VerifPlan_Bus_Error.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/custom_circuitry/README.md b/cv32e40x/docs/VerifPlans/Simulation/custom_circuitry/README.md deleted file mode 100644 index 596a91f4ae..0000000000 --- a/cv32e40x/docs/VerifPlans/Simulation/custom_circuitry/README.md +++ /dev/null @@ -1,2 +0,0 @@ -Placeholder directory for a specific CV32E40X high-level feature. -The Verification Plan (aka Test Plan) for this feature will be committed here as soon as is available. diff --git a/cv32e40x/docs/VerifPlans/Simulation/debug-trace/CV32E40X_debug.xlsx b/cv32e40x/docs/VerifPlans/Simulation/debug-trace/CV32E40X_debug.xlsx deleted file mode 100755 index 3b597192c5..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/debug-trace/CV32E40X_debug.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/debug-trace/CV32E40X_external-debugger.xlsx b/cv32e40x/docs/VerifPlans/Simulation/debug-trace/CV32E40X_external-debugger.xlsx deleted file mode 100644 index 57c01e095d..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/debug-trace/CV32E40X_external-debugger.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/debug-trace/README.md b/cv32e40x/docs/VerifPlans/Simulation/debug-trace/README.md deleted file mode 100644 index dd9b7ff5e3..0000000000 --- a/cv32e40x/docs/VerifPlans/Simulation/debug-trace/README.md +++ /dev/null @@ -1,2 +0,0 @@ -Directory for the CV32E40X Verification Plan for Debug and associated documentation. -Note that only `CV32E40X_Debug` is relevant to the current release of CV32E40X. diff --git a/cv32e40x/docs/VerifPlans/Simulation/interrupts/CV32E40X_interrupts.xlsx b/cv32e40x/docs/VerifPlans/Simulation/interrupts/CV32E40X_interrupts.xlsx deleted file mode 100755 index 41cd5d46f6..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/interrupts/CV32E40X_interrupts.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/interrupts/README.md b/cv32e40x/docs/VerifPlans/Simulation/interrupts/README.md deleted file mode 100644 index e6f21bf044..0000000000 --- a/cv32e40x/docs/VerifPlans/Simulation/interrupts/README.md +++ /dev/null @@ -1 +0,0 @@ -Directory for the CV32E40X Verification Plan for Interrupts and associated documentation. diff --git a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_Instruction_Groups.xlsx b/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_Instruction_Groups.xlsx deleted file mode 100755 index d360a5b0ac..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_Instruction_Groups.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_OBI_VerifPlan.xlsx b/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_OBI_VerifPlan.xlsx deleted file mode 100755 index 48ecd40d50..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_OBI_VerifPlan.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_Pipeline_Sleep.xlsx b/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_Pipeline_Sleep.xlsx deleted file mode 100644 index ebbc3cb577..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_Pipeline_Sleep.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_fencei.xlsx b/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_fencei.xlsx deleted file mode 100755 index 0f70da15fa..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/CV32E40X_fencei.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/README.md b/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/README.md deleted file mode 100644 index 36f04baa24..0000000000 --- a/cv32e40x/docs/VerifPlans/Simulation/micro_architecture/README.md +++ /dev/null @@ -1 +0,0 @@ -Verification Plans for CV32E40X micro-architecture and physical interfaces. diff --git a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md b/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md deleted file mode 100644 index 74aaf75000..0000000000 --- a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md +++ /dev/null @@ -1,160 +0,0 @@ - -# *Note that this is copied from the CV32E40P. It has not been ported to CV32E40X as of yet* - -## Functional verification of CSRs in a RISC-V core -The Controll and Status Registers in a RISC-V core are distinct from CSRs in -non-processor ASIC/FPGA RTL in ways that have a direct impact on RTL -verification. Here, we discuss the problem in detail, using select RISC-V -standard CSRs as examples. - -This document serves two purposes. The first purpose is a general discussion -and tutorial on the topic of CSR verification in general and RISC-V CSR -verification in particular. Its second purpose is form the Verification Plan -(also known as a Testplan) for the CV32E40P CSRs. Note that this Vplan does -not follow the same spreadsheet style template that is used for other CV32E40P -Vplans. The reason for this will become apparent as you read the document. - -### Power-on-Reset Values - -Many (all?) RISC-V CSRs are expected to have a known value once the core comes -out of hardware reset. Testing these values is typically straightforward and -is done in a way that is familiar to anyone who has done this for non-processor -ASIC/FPGA RTL. In both cases, care must be taken to read the value of a status -register before the device-under-test experiences an event that causes an update -to the register. For example, accessing a non-existant CSR should raise an -illegal instruction exception which should, in turn, update the value of MCAUSE. -Therefore a test that checks the PoR value of MCAUSE must not access a non-existant -CSR before reading MCAUSE. - -### Access Mode Behavior - -Here, we are trying to answer the question, "how does the CSR behave when it is -accessed (written to, or read from)?". In RISC-V cores, CSRs are accessed using -the `CSRRC`, `CSRRCI`, `CSRRS`, `CSRRSI`, `CSRRW` and `CSRRWI` instructions. Note -that there are also seven pseudoinstructions that will expand into one of these -instructions. While in the general case a core may provide alternative means to -access CSRs, in the CV32E40P, these instructions are the only access method available. - -Note that when verifying access mode behavior we are not (yet) concerned about -what the core will do when a given CSR has a specific value. - -In RISC-V cores, access mode behavior has four dimensions: access mode, -privilege, existance and field specification. These are discussed in turn, -with emphasis placed on pre-silicon functional verification (as opposed to -post-silicon use by software). - -#### Access Mode - -Access modes in RISC-V cores are simple and familar to those with prior experience -with non-processor core ASIC/FPGA RTL. In fact, there are only two access modes -to worry about: RW and RO: - -1. RW: all bits of a RW field must be writable and must return the last written -value upon a read. -2. RO: no bit of a RO field may be writable and must return the previous value upon -read, event after being written to by either 0 or 1. - -#### Privilege - -Of course, nothing is ever _that_ simple with RISC-V. A core's privilege mode adds -a second dimension to access mode. Is it often the case that a CSR that is -accessible in a high privilege mode does not exist in lower modes. This must also -be verified. - -For the purposes of CSR verification, it is permissible to consider Debug Mode as -the highest privilege level. - -CV32E40P only supports Machine mode, which greatly simplifies the problem. - -#### Existance - -CSR "existance" is a concept unique to processor core and is not generally seen in -non-processor ASIC/FPGA RTL designs. The RISC-V privileged and debug specifications -define a set of CSRs, including both "required" and "optional" CSRs. Accessing an -optional CSR may result in an illegal instruction (which must be veified). A -complicating factor is that CSR existance may also be dependent on privlege level. -For example reading a Debug CSR when the core is not in debug mode results in an -illegal instruction exception while reading the same register in debug mode -returns a value. - -#### Field Specification - -Although the "field specification" may sound familiar to those with a -non-processor RTL background, the term is used differently in RISC-V where -"field specification" refers to how software is expected to interact with -specific fields of specific CSRs. This has a material impact on the strategy -used for RTL verification of CSRs. There are three field specification types: - -1. **WPRI**: this field specification defines how software should interact -with specific "protected" fields. This software action is wholly independent of RTL -logic behavior, so WPRI fields may be treated as RO for the purposes of RTL -functional verification of their access behavior. -2. **WLRL**: once again, this field specification refers to how software should -interact with specific RW fields. The difference is that reads will only return -_legal_ values on reads, acting as a mask on return values of a RW test. In all -other respects, WLRL fields may be treated as RW for the purposes of RTL -functional verification of their access behavior. -3. **WARL**: fields may be treated as RW (with read masking) for the purposes of RTL functional -verification of their access behavior. - - -### Control Actions - -CSRs are called Control and Status Registers for a reason. Control registers will -change (control) the operation of the device under test in measureable ways and functional -verification must coverage all legal values (or in some cases, important ranges of -values) and then check that these values have the desired affect. A good example -is ensuring that interrupts are asserted when MSTATUS[MIE] is both 0/1 and ensuring -that interrupts are ignored or responded to, as appropriate. - -Control register verification of RISC-V cores is not conceptually different than -control register verification of non-processor ASIC/FPGA RTL. One difference is -that in non-processor RTL, the control path (reading the writing the CSRs) is -typically independent of the data path (events that are affected by control -register values). In processor cores a program executing on the core acts as both -the control path (by executing CSR access instructions) and the data path (by -executing code that is affected by the CSRs). - -### Status Capture - -Certain external and/or program events will be recorded in status registers. -This sub-section will be updated at a later date. - -## CV32E40P CSR Verification Plan - -| Testcase | Targeted Aspect | Type | Reference | Status | -|----------|-----------------|------|-----------|--------| -| por\_csr.c | Power-on-Reset values | Manually written, directed | [1](#1) | Complete | -| por\_debug\_csr.c | Power-on-Reset values for Debug CSRs | Manually written, directed | [2](#2) | | -| csr\_existance.c | Illegal instruction exception for non-existant CSRs | Manually written, directed | [3](#3) | | -| cv32e40p_csr\_access_test.c | Combined access mode behavior and field specification tests for all CSRs | Generated | [4](#4) | Under development | -| csr\_privlege.c | Debug mode can access all CSRs | Manually written, directed | [5](#5) | | - -### ToDo: - -* Verification of status fields. -* Verification of control fields. - -### 1 -At the time of this writting (2020-10-07), this is implemented as two tests, `modeled_csr_por` and `requested_csr_por`. In the near (?) future these will be combined into a single test. For each machine-mode CSR in CV32E40P: -- read current value -- compare to documented PoR value in User Manual - -Failure conditions: -- any read value does not match documented PoR -- any illegal instruction exceptions - -### 2 -Same as [1](#1) but first enter debug mode and then attempt to read all -machine-mode and debug-mode registers - -### 3 -Similar to [1](#1) with added accesses between address ranges of existing -machine-mode CSRs. For example, address range 0x307 : 0x33F between Machine -Trap Setup CSRs and Machine Trap Handling CSRs. - -### 4 -Access mode test of all CSRs. This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/master/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml). - -### 5 -Same as [4](#4), run in Debug mode. Add access mode testing of Debug CSRs. diff --git a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_Counters.xlsx b/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_Counters.xlsx deleted file mode 100755 index 644ecb948c..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_Counters.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_Exceptions.xlsx b/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_Exceptions.xlsx deleted file mode 100755 index b9ee9f697b..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_Exceptions.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_PMA_VerifPlan.xlsx b/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_PMA_VerifPlan.xlsx deleted file mode 100755 index 42cdebee53..0000000000 Binary files a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/CV32E40X_PMA_VerifPlan.xlsx and /dev/null differ diff --git a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/README.md b/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/README.md deleted file mode 100644 index 4de3f472e2..0000000000 --- a/cv32e40x/docs/VerifPlans/Simulation/privileged_spec/README.md +++ /dev/null @@ -1 +0,0 @@ -The Verification Plan (aka Test Plan) documents for CV32E40X features related to the [RISC-V Privleged Specification](https://riscv.org/specifications/privileged-isa/). diff --git a/cv32e40x/env/corev-dv/README.md b/cv32e40x/env/corev-dv/README.md deleted file mode 100644 index db43ff9238..0000000000 --- a/cv32e40x/env/corev-dv/README.md +++ /dev/null @@ -1,12 +0,0 @@ -## corev-dv -This directory contains core-v-verif extensions to [riscv-dv](https://github.com/google/riscv-dv). The cloned code from Google is not locally -modified, and as much as is possible we attempt to use the latest-and-greatest from Google. Any core-v-verif -specializations are implemented as either replacements (e.g the manifest) or extensions of specific SV classes. -

-Compile logs, runtime logs and the generated programs are placed here in the same `out_` directory used by riscv-dv. -
-TODO: re-direct the generated assembly language tests-programs to a central location. -

-The UVM environments in core-v-verif do not use the `run.py` python script to run the generator (although no changes are -made preventing _you_ from doing so). Check out the appropriate Makefile(s) (e.g. `$PROJ_ROOT/cv32/sim/uvmt_cv32/Makefile`) -for an exmaple of how core-v-verif runs the generator. diff --git a/cv32e40x/env/corev-dv/cv32e40x_asm_program_gen.sv b/cv32e40x/env/corev-dv/cv32e40x_asm_program_gen.sv deleted file mode 100644 index a3adafeea8..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_asm_program_gen.sv +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Copyright 2018 Google LLC - * Copyright 2020 Andes Technology Co., Ltd. - * Copyright 2020 OpenHW Group - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//----------------------------------------------------------------------------------------- -// CV32E40X CORE-V assembly program generator - extension of the RISC-V assembly program generator. -// -// Overrides gen_program_header() and gen_test_done() -//----------------------------------------------------------------------------------------- - -class cv32e40x_asm_program_gen extends corev_asm_program_gen; - - `uvm_object_utils(cv32e40x_asm_program_gen) - - function new (string name = ""); - super.new(name); - endfunction - - virtual function void gen_illegal_instr_handler(int hart); - string instr[$]; - string load_instr = (XLEN == 32) ? "lw" : "ld"; - gen_signature_handshake(instr, CORE_STATUS, ILLEGAL_INSTR_EXCEPTION); - gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); - instr = {instr, - // Get the stack pointer from the scratch register - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.sp, MSCRATCH, cfg.sp), - $sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[1], 0 * (XLEN/8), cfg.sp), - // if zero, jump to end - $sformatf("beq x%0d, x%0d, non_pma_handler_illegal_instr", cfg.gpr[1], 0), - // else get the other (potential) pc_value from stack - $sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[0], 1 * (XLEN/8), cfg.sp), - // check if these are equal (nonzero implied from check above) - $sformatf("bne x%0d, x%0d, non_pma_handler_illegal_instr", cfg.gpr[1], cfg.gpr[0]), - $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[1]), - $sformatf("la x%0d, pop_gpr_illegal_instr_handler", cfg.gpr[0]), - $sformatf("jalr x%0d, x%0d", 0, cfg.gpr[0]), - - // original handler code start - $sformatf("non_pma_handler_illegal_instr: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), - $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), - $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]), - // original handler code end - - $sformatf("pop_gpr_illegal_instr_handler:"), - // Swap back stack pointer to restore condition prior to handler - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.sp, MSCRATCH, cfg.sp) - }; - - pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); - instr.push_back("mret"); - gen_section(get_label("illegal_instr_handler", hart), instr); - endfunction - - virtual function void gen_instr_fault_handler(int hart); - string instr[$]; - string load_instr = (XLEN == 32) ? "lw" : "ld"; - gen_signature_handshake(instr, CORE_STATUS, INSTR_FAULT_EXCEPTION); - gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); - //if (cfg.pmp_cfg.enable_pmp_exception_handler) begin - // cfg.pmp_cfg.gen_pmp_exception_routine({cfg.gpr, cfg.scratch_reg, cfg.pmp_reg}, - // INSTRUCTION_ACCESS_FAULT, - // instr); - //end - instr = {instr, - // Get the stack pointer from the scratch register - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.sp, MSCRATCH, cfg.sp), - $sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[1], 0 * (XLEN/8), cfg.sp), - // if zero, jump to end - $sformatf("beq x%0d, x%0d, non_pma_handler_instr_fault", cfg.gpr[1], 0), - // else get the other (potential) pc_value from stack - $sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[0], 1 * (XLEN/8), cfg.sp), - // check if these are equal (nonzero implied from check above) - $sformatf("bne x%0d, x%0d, non_pma_handler_instr_fault", cfg.gpr[1], cfg.gpr[0]), - $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[1]), - $sformatf("la x%0d, pop_gpr_instr_fault_handler", cfg.gpr[0]), - $sformatf("jalr x%0d, x%0d", 0, cfg.gpr[0]), - - // original handler code start - $sformatf("non_pma_handler_instr_fault: csrr x%0d, 0x%0x", cfg.gpr[0], MEPC), - $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), - $sformatf("csrw 0x%0x, x%0d", MEPC, cfg.gpr[0]), - // original handler code end - - $sformatf("pop_gpr_instr_fault_handler:"), - // Swap back stack pointer to restore condition prior to handler - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.sp, MSCRATCH, cfg.sp) - }; - pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); - instr.push_back("mret"); - gen_section(get_label("instr_fault_handler", hart), instr); - endfunction - - // TODO: handshake correct csr based on delegation - virtual function void gen_load_fault_handler(int hart); - string instr[$]; - gen_signature_handshake(instr, CORE_STATUS, LOAD_FAULT_EXCEPTION); - gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); - //if (cfg.pmp_cfg.enable_pmp_exception_handler) begin - // cfg.pmp_cfg.gen_pmp_exception_routine({cfg.gpr, cfg.scratch_reg, cfg.pmp_reg}, - // LOAD_ACCESS_FAULT, - // instr); - //end - // Increase mepc by 4 - instr = { instr, - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.gpr[0], MEPC, cfg.gpr[0]), - $sformatf("addi x%0d, x%0d, %0d", cfg.gpr[0], cfg.gpr[0], (XLEN/8)), - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.gpr[0], MEPC, cfg.gpr[0]) - }; - pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); - instr.push_back("mret"); - gen_section(get_label("load_fault_handler", hart), instr); - endfunction - - // TODO: handshake correct csr based on delegation - virtual function void gen_store_fault_handler(int hart); - string instr[$]; - gen_signature_handshake(instr, CORE_STATUS, STORE_FAULT_EXCEPTION); - gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); - //if (cfg.pmp_cfg.enable_pmp_exception_handler) begin - // cfg.pmp_cfg.gen_pmp_exception_routine({cfg.gpr, cfg.scratch_reg, cfg.pmp_reg}, - // STORE_AMO_ACCESS_FAULT, - // instr); - //end - instr = { instr, - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.gpr[0], MEPC, cfg.gpr[0]), - $sformatf("addi x%0d, x%0d, %0d", cfg.gpr[0], cfg.gpr[0], (XLEN/8)), - $sformatf("csrrw x%0d, 0x%0x, x%0d", cfg.gpr[0], MEPC, cfg.gpr[0]) - }; - pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); - instr.push_back("mret"); - gen_section(get_label("store_fault_handler", hart), instr); - endfunction - - virtual function void gen_interrupt_vector_table(int hart, - string mode, - privileged_reg_t status, - privileged_reg_t cause, - privileged_reg_t ie, - privileged_reg_t ip, - privileged_reg_t scratch, - ref string instr[$]); - // In vector mode, the BASE address is shared between interrupt 0 and exception handling. - // When vectored interrupts are enabled, interrupt cause 0, which corresponds to user-mode - // software interrupts, are vectored to the same location as synchronous exceptions. This - // ambiguity does not arise in practice, since user-mode software interrupts are either - // disabled or delegated - cv32e40x_instr_gen_config corev_cfg; - `DV_CHECK_FATAL($cast(corev_cfg, cfg), "Could not cast cfg into corev_cfg") - - instr = {instr, ".option norvc;", - $sformatf("j %0s%0smode_exception_handler", hart_prefix(hart), mode)}; - // Redirect the interrupt to the corresponding interrupt handler - for (int i = 1; i < max_interrupt_vector_num; i++) begin - instr.push_back($sformatf("j %0s%0smode_intr_vector_%0d", hart_prefix(hart), mode, i)); - end - if (!cfg.disable_compressed_instr) begin - instr = {instr, ".option rvc;"}; - end - for (int i = 1; i < max_interrupt_vector_num; i++) begin - string intr_handler[$]; - - if (corev_cfg.use_fast_intr_handler[i]) begin - // Emit fast interrupt handler since cv32e40x has hardware interrupt ack - // If WFIs allow, randomly insert wfi as well - if (!cfg.no_wfi) begin - randcase - 2: intr_handler.push_back("wfi"); - 4: begin /* insert nothing */ end - endcase - end - intr_handler.push_back("mret"); - end - else begin - // Standard full-stack-save interrupt handler - push_gpr_to_kernel_stack(status, scratch, cfg.mstatus_mprv, cfg.sp, cfg.tp, intr_handler); - gen_signature_handshake(.instr(intr_handler), .signature_type(CORE_STATUS), - .core_status(HANDLING_IRQ)); - intr_handler = {intr_handler, - $sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[0], cause, cause.name()), - // Terminate the test if xCause[31] != 0 (indicating exception) - $sformatf("srli x%0d, x%0d, 0x%0x", cfg.gpr[0], cfg.gpr[0], XLEN-1), - $sformatf("beqz x%0d, 1f", cfg.gpr[0])}; - gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(status)); - gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(cause)); - gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(ie)); - gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(ip)); - // Jump to commmon interrupt handling routine - intr_handler = {intr_handler, - $sformatf("j %0s%0smode_intr_handler", hart_prefix(hart), mode), - $sformatf("1: la x%0d, test_done", cfg.scratch_reg), - $sformatf("jalr x%0d, 0", cfg.scratch_reg)}; - end - - gen_section(get_label($sformatf("%0smode_intr_vector_%0d", mode, i), hart), intr_handler); - end - endfunction : gen_interrupt_vector_table - - // Setup EPC before entering target privileged mode - virtual function void setup_epc(int hart); - string instr[$]; - string mode_name; - instr = {$sformatf("la x%0d, %0sinit", cfg.gpr[0], hart_prefix(hart))}; - if(cfg.virtual_addr_translation_on) begin - // For supervisor and user mode, use virtual address instead of physical address. - // Virtual address starts from address 0x0, here only the lower 12 bits are kept - // as virtual address offset. - instr = {instr, - $sformatf("slli x%0d, x%0d, %0d", cfg.gpr[0], cfg.gpr[0], XLEN - 12), - $sformatf("srli x%0d, x%0d, %0d", cfg.gpr[0], cfg.gpr[0], XLEN - 12)}; - end - mode_name = cfg.init_privileged_mode.name(); - instr.push_back($sformatf("csrw mepc, x%0d", cfg.gpr[0])); - gen_section(get_label("mepc_setup", hart), instr); - endfunction - - // Interrupt handler routine - // Override from risc-dv: - // 1. Remove MIP read, since interrupts are auto-cleared, mip will not track through the ISS - // to GPR properly with autoclear - virtual function void gen_interrupt_handler_section(privileged_mode_t mode, int hart); - string mode_prefix; - string ls_unit; - privileged_reg_t status, ip, ie, scratch; - string interrupt_handler_instr[$]; - - ls_unit = (XLEN == 32) ? "w" : "d"; - if (mode < cfg.init_privileged_mode) return; - if (mode == USER_MODE && !riscv_instr_pkg::support_umode_trap) return; - case(mode) - MACHINE_MODE: begin - mode_prefix = "m"; - status = MSTATUS; - ip = MIP; - ie = MIE; - scratch = MSCRATCH; - end - SUPERVISOR_MODE: begin - mode_prefix = "s"; - status = SSTATUS; - ip = SIP; - ie = SIE; - scratch = SSCRATCH; - end - USER_MODE: begin - mode_prefix = "u"; - status = USTATUS; - ip = UIP; - ie = UIE; - scratch = USCRATCH; - end - default: `uvm_fatal(get_full_name(), $sformatf("Unsupported mode: %0s", mode.name())) - endcase - - // If nested interrupts are enabled, set xSTATUS.xIE in the interrupt handler - // to re-enable interrupt handling capabilities - if (cfg.enable_nested_interrupt) begin - string store_instr = (XLEN == 32) ? "sw" : "sd"; - - // kernel stack point is already in sp, mscratch already has stored stack pointer - interrupt_handler_instr.push_back($sformatf("1: addi x%0d, x%0d, -%0d", cfg.sp, cfg.sp, 4 * (XLEN/8))); - - // Push MIE, MEPC and MSTATUS to stack - interrupt_handler_instr.push_back($sformatf("csrr x%0d, mie", cfg.gpr[0])); - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, cfg.gpr[0], 1 * (XLEN/8), cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrr x%0d, mepc", cfg.gpr[0])); - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, cfg.gpr[0], 2 * (XLEN/8), cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrr x%0d, mstatus", cfg.gpr[0])); - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, cfg.gpr[0], 3 * (XLEN/8), cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrr x%0d, mscratch", cfg.gpr[0])); - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, cfg.gpr[0], 4 * (XLEN/8), cfg.sp)); - - // Move SP to TP and restore TP - interrupt_handler_instr.push_back($sformatf("add x%0d, x%0d, zero", cfg.tp, cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrrw x%0d, mscratch, x%0d", cfg.sp, cfg.sp)); - - // Re-enable interrupts - case (status) - MSTATUS: begin - interrupt_handler_instr.push_back($sformatf("csrsi 0x%0x, 0x%0x", status, 8)); - end - SSTATUS: begin - interrupt_handler_instr.push_back($sformatf("csrsi 0x%0x, 0x%0x", status, 2)); - end - USTATUS: begin - interrupt_handler_instr.push_back($sformatf("csrsi 0x%0x, 0x%0x", status, 1)); - end - default: `uvm_fatal(`gfn, $sformatf("Unsupported status %0s", status)) - endcase - end - - // Read back interrupt related privileged CSR - // The value of these CSR are checked by comparing with spike simulation result. - interrupt_handler_instr = { - interrupt_handler_instr, - $sformatf("csrr x%0d, 0x%0x # %0s;", cfg.gpr[0], status, status.name()), - $sformatf("csrr x%0d, 0x%0x # %0s;", cfg.gpr[0], ie, ie.name()) - }; - gen_plic_section(interrupt_handler_instr); - - if (cfg.enable_nested_interrupt) begin - string load_instr = (XLEN == 32) ? "lw" : "ld"; - - // If in nested interrupts, the restoration of all GPRs and interrupt registers from stack - // are considered a critical section - // Re-disable interrupts - case (status) - MSTATUS: begin - interrupt_handler_instr.push_back($sformatf("csrci 0x%0x, 0x%0x", status, 8)); - end - SSTATUS: begin - interrupt_handler_instr.push_back($sformatf("csrci 0x%0x, 0x%0x", status, 2)); - end - USTATUS: begin - interrupt_handler_instr.push_back($sformatf("csrci 0x%0x, 0x%0x", status, 1)); - end - default: `uvm_fatal(`gfn, $sformatf("Unsupported status %0s", status)) - endcase - - // Save SP to scratch and move TP to SP - interrupt_handler_instr.push_back($sformatf("csrrw x%0d, mscratch, x%0d", cfg.sp, cfg.sp)); - interrupt_handler_instr.push_back($sformatf("add x%0d, x%0d, zero", cfg.sp, cfg.tp)); - - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[0], 1 * (XLEN/8), cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrw mie, x%0d", cfg.gpr[0])); - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[0], 2 * (XLEN/8), cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrw mepc, x%0d", cfg.gpr[0])); - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[0], 3 * (XLEN/8), cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrw mstatus, x%0d", cfg.gpr[0])); - interrupt_handler_instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg.gpr[0], 4 * (XLEN/8), cfg.sp)); - interrupt_handler_instr.push_back($sformatf("csrw mscratch, x%0d", cfg.gpr[0])); - - interrupt_handler_instr.push_back($sformatf("addi x%0d, x%0d, %0d", cfg.sp, cfg.sp, 4 * (XLEN/8))); - end - - // Restore user mode GPR value from kernel stack before return - pop_gpr_from_kernel_stack(status, scratch, cfg.mstatus_mprv, - cfg.sp, cfg.tp, interrupt_handler_instr); - // Emit fast interrupt handler since cv32e40x has hardware interrupt ack - - interrupt_handler_instr = {interrupt_handler_instr, - $sformatf("%0sret;", mode_prefix) - }; - if (SATP_MODE != BARE) begin - // The interrupt handler will use one 4KB page - instr_stream.push_back(".align 12"); - end else begin - instr_stream.push_back(".align 2"); - end - gen_section(get_label($sformatf("%0smode_intr_handler", mode_prefix), hart), - interrupt_handler_instr); - - gen_nmi_handler_section(hart); - - endfunction : gen_interrupt_handler_section - - // Override gen_stack_section to add debugger stack generation section - // Implmeneted as a post-step to super.gen_stack_section() - virtual function void gen_stack_section(int hart); - super.gen_stack_section(hart); - - if (SATP_MODE != BARE) begin - instr_stream.push_back(".align 12"); - end else begin - instr_stream.push_back(".align 2"); - end - instr_stream.push_back(get_label("debugger_stack_start:", hart)); - instr_stream.push_back($sformatf(".rept %0d", cfg.stack_len - 1)); - instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8)); - instr_stream.push_back(".endr"); - instr_stream.push_back(get_label("debugger_stack_end:", hart)); - instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8)); - - endfunction : gen_stack_section - - // Override of init_gpr to remove cfg.dp from initiailization if a debug section is generated - virtual function void init_gpr(); - string str; - bit [DATA_WIDTH-1:0] reg_val; - cv32e40x_instr_gen_config cfg_corev; - - `DV_CHECK($cast(cfg_corev, cfg)) - // Init general purpose registers with random values - for(int i = 0; i < NUM_GPR; i++) begin - if (i inside {cfg.sp, cfg.tp}) continue; - if (cfg.gen_debug_section && (i inside {cfg_corev.dp})) continue; - - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(reg_val, - reg_val dist { - 'h0 :/ 1, - 'h8000_0000 :/ 1, - ['h1 : 'hF] :/ 1, - ['h10 : 'hEFFF_FFFF] :/ 1, - ['hF000_0000 : 'hFFFF_FFFF] :/ 1 - };) - str = $sformatf("%0sli x%0d, 0x%0x", indent, i, reg_val); - instr_stream.push_back(str); - end - endfunction - - // generate NMI handler. - // will be placed at a fixed address in memory, set in linker file - //TODO: verify correct functionality when NMI test capability is ready - virtual function void gen_nmi_handler_section(int hart); - string nmi_handler_instr[$]; - - // Insert section info so linker can place - // debug code at the correct adress - instr_stream.push_back(".section .nmi, \"ax\""); - - // read relevant csr's - nmi_handler_instr.push_back($sformatf("csrr x%0d, mepc", cfg.gpr[0])); - nmi_handler_instr.push_back($sformatf("csrr x%0d, mcause", cfg.gpr[0])); - nmi_handler_instr.push_back($sformatf("csrr x%0d, mtval", cfg.gpr[0])); - nmi_handler_instr.push_back($sformatf("csrr x%0d, mie", cfg.gpr[0])); - - nmi_handler_instr.push_back($sformatf("la x%0d, test_done", cfg.scratch_reg)); - nmi_handler_instr.push_back($sformatf("jr x%0d", cfg.scratch_reg)); - - gen_section(get_label($sformatf("nmi_handler"), hart), - nmi_handler_instr); - endfunction : gen_nmi_handler_section - -endclass : cv32e40x_asm_program_gen diff --git a/cv32e40x/env/corev-dv/cv32e40x_compressed_instr.sv b/cv32e40x/env/corev-dv/cv32e40x_compressed_instr.sv deleted file mode 100644 index b1abe65ac7..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_compressed_instr.sv +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2018 Google LLC - * Copyright 2020 OpenHW Group - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//------------------------------------------------------------------------------ -// CORE-V compressed_instruction class -// Addresses issues with random constraints in riscv-dv -// -// The base test Uses the factory to replace riscv_privil_reg with corev_privil_reg -//------------------------------------------------------------------------------ - -class cv32e40x_C_LUI_instr extends riscv_C_LUI_instr; - - // Fix an issue with constraints nzimm6 for C_LUI instructions - // The original definition is in riscv_compressed_instr.sv - - constraint imm_val_c { - if(imm_type inside {NZIMM, NZUIMM}) { - imm[5:0] != 0; - if (instr_name == C_LUI) { - // Original: imm[31:5] == 0; - imm[31:6] == 0; - } - if (instr_name inside {C_SRAI, C_SRLI, C_SLLI}) { - imm[31:5] == 0; - } - } - if (instr_name == C_ADDI4SPN) { - imm[1:0] == 0; - } - } - - `uvm_object_utils(cv32e40x_C_LUI_instr) - - function new(string name=""); - super.new(name); - endfunction : new - - virtual function void extend_imm(); - bit sign; - - imm = imm << (32 - imm_len); - sign = imm[31]; - imm = imm >> (32 - imm_len); - imm_mask = imm_mask << imm_len; - if (sign) begin - imm |= imm_mask; - end - endfunction : extend_imm - - virtual function void update_imm_str(); - if ($signed(imm) < 0) begin - // GNU Assembler will not accept negative values for LUI even thought actuall nzimm6 range is [-32, 31] - // Must encode as a hex value to be loaded into upper 20 bits of rd - // See https://github.com/riscv/riscv-tools/issues/182 - imm_str = $sformatf("0x%x", imm[19:0]); - end - else begin - super.update_imm_str(); - end - endfunction : update_imm_str - -endclass : cv32e40x_C_LUI_instr diff --git a/cv32e40x/env/corev-dv/cv32e40x_csr_template.yaml b/cv32e40x/env/corev-dv/cv32e40x_csr_template.yaml deleted file mode 100644 index 233e80eddb..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_csr_template.yaml +++ /dev/null @@ -1,1029 +0,0 @@ -# Copyright 2020 OpenHW Group -# Copyright 2019 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -################################################################################ -# -# CSR definitions for the CV32E40X CORE-V proessor core (an RV32IMCZ machine). -# -# This file can be used as input to "gen_csr_test.py" delivered as part of -# Google's riscv-dv project. Assuming you are running this from -# core-v-verif/vendor_lib/google/corev-dv and you've cloned riscv-dv, then the -# following command-line should work for you: -# -# python3 ../riscv-dv/scripts/gen_csr_test.py \ -# --csr_file cv32e40x_csr_template.yaml \ -# --xlen 32 -# -# Source document is the CV32E40X user Manual: -# https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40x_um/en/latest/index.html -# Revision 62f0d86b -# -# Assumptions: -# 1. Configuration core input mtvec_addr_i == 32'h0000_0000 -# 2. Configuration core input mhartid_i == 32'h0000_0000 -# 3. Configuration core input mimpid_i == 32'h0000_0000 -# 4. Core RTL parameters set as per User Manual defaults. -################################################################################ -#- csr: CSR_NAME -# description: > -# BRIEF_DESCRIPTION -# address: 0x### -# privilege_mode: MODE (D/M/S/H/U) -# rv32: -# - MSB_FIELD_NAME: -# - description: > -# BRIEF_DESCRIPTION -# - type: TYPE (WPRI/WLRL/WARL/R) -# - reset_val: RESET_VAL -# - msb: MSB_POS -# - lsb: LSB_POS -# - ... -# - ... -# - LSB_FIELD_NAME: -# - description: ... -# - type: ... -# - ... -# rv64: -# - MSB_FIELD_NAME: -# - description: > -# BRIEF_DESCRIPTION -# - type: TYPE (WPRI/WLRL/WARL/R) -# - reset_val: RESET_VAL -# - msb: MSB_POS -# - lsb: LSB_POS -# - ... -# - ... -# - LSB_FIELD_NAME: -# - description: ... -# - type: ... -# - ... - -# User CSRs not implemented for first release of CV32E40X -#- csr: cycle -# description: > -# (HPM) Cycle Counter -# address: 0xC00 -# privilege_mode: M -# rv32: -# - field_name: cycle -# description: > -# Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode cycle counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: instret -# description: > -# (HPM) Instruction-Retired Counter -# address: 0xC02 -# privilege_mode: M -# rv32: -# - field_name: instret -# description: > -# Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode instruction retired counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: hpmcounter3 -# description: > -# (HPM) Performance-Monitoring Counter3 -# address: 0xC03 -# privilege_mode: M -# rv32: -# - field_name: counter3 -# description: > -# Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine performance counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: cycleh -# description: > -# (HPM) Upper 32 Cycle Counter -# address: 0xC80 -# privilege_mode: M -# rv32: -# - field_name: cycleh -# description: > -# Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode cycle counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: instreth -# description: > -# (HPM) Upper 32 Instruction-Retired Counter -# address: 0xC82 -# privilege_mode: M -# rv32: -# - field_name: instreth -# description: > -# Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode instruction retired counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: hpmcounter3h -# description: > -# (HPM) Upper 32 Performance-Monitoring Counter3 -# address: 0xC83 -# privilege_mode: M -# rv32: -# - field_name: counter3h -# description: > -# Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine performance counter. -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 - -# User Custom CSRs not verified for first release of CV32E40X - -# Machine CSRs - -# mcycle(h) and minstret(h) are done here because out of reset mcountinhibit -# will disable cycle and instruction retirement counts. These access tests -# will not work if this counting is enabled. -- csr: mcycle - description: > - Lower 32 Machine Cycle Counter - address: 0xB00 - privilege_mode: M - rv32: - - field_name: Count - description: > - Lower 32-bits of 64-bit machine cycle counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mcycleh - description: > - Upper 32 Machine Cycle Counter - address: 0xB80 - privilege_mode: M - rv32: - - field_name: Count - description: > - Upper 32-bits of 64-bit machine cycle counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: minstret - description: > - Lower 32 Machine Instructions-Retired Counter - address: 0xB02 - privilege_mode: M - rv32: - - field_name: Count - description: > - Lower 32-bits of 64-bit machine instructions retired counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: minstreth - description: > - Upper 32 Machine Instructions-Retired Counter - address: 0xB82 - privilege_mode: M - rv32: - - field_name: Count - description: > - Upper 32-bits of 64-bit machine instructions retired counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter3 - description: > - Lower 32-bit Machine Performance Monitoring Counter - address: 0xB03 - privilege_mode: M - rv32: - - field_name: Count - description: > - Lower 32-bits of 64-bit machine performance-monitoring counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter3h - description: > - Upper 32-bit Machine Performance Monitoring Counter - address: 0xB83 - privilege_mode: M - rv32: - - field_name: Count - description: > - Upper 32-bits of 64-bit machine performance-monitoring counter - type: RW - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mstatus - description: > - Machine ISA Register - address: 0x300 - privilege_mode: M - rv32: - - field_name: MPP - description: > - Machine Previous Privilege mode, hardwired to 3'b11 when User mode not enabled - type: R - reset_val: 3 - msb: 12 - lsb: 11 - - field_name: PMIE - description: > - Previous Machine Interrupt Enable - type: WARL - reset_val: 0 - msb: 7 - lsb: 7 - - field_name: PUIE - description: > - Previous User Interrupt Enable - type: R - reset_val: 0 - msb: 4 - lsb: 4 - - field_name: MIE - description: > - Machine Interrupt Enable - type: WARL - reset_val: 0 - msb: 3 - lsb: 3 - - field_name: UIE - description: > - User Interrupt Enable - type: R - reset_val: 0 - msb: 0 - lsb: 0 -- csr: misa - description: > - Machine ISA Register - address: 0x301 - privilege_mode: M - rv32: - - field_name: MXL - description: > - Encodes native base ISA width - type: R - reset_val: 1 - msb: 31 - lsb: 30 - - field_name: Extensions - description: > - Encodes all supported ISA extensions - type: R - reset_val: 0x001104 - msb: 25 - lsb: 0 -- csr: mie - description: > - Machine Interrupt Enable - address: 0x304 - privilege_mode: M - rv32: - - field_name: MFIE - description: > - Machine Fast Interrupt Enables - type: WARL - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: MEIE - description: > - Machine External Interrupt Enable - type: WARL - reset_val: 0 - msb: 11 - lsb: 11 - - field_name: MTIE - description: > - Machine Timer Interrupt Enable - type: WARL - reset_val: 0 - msb: 7 - lsb: 7 - - field_name: MSIE - description: > - Machine Software Interrupt Enable - type: WARL - reset_val: 0 - msb: 3 - lsb: 3 -- csr: mtvec - description: > - Machine Trap-Vector Base Address - address: 0x305 - privilege_mode: M - rv32: - - field_name: BASE[31:8] - description: > - Trap-handler base address, always aligned to 256 bytes - type: WARL - reset_val: 0 # assumes mtvec_i == 0 - msb: 31 - lsb: 8 - - field_name: BASE[7:2] - description: > - Trap-handler base address, always aligned to 256 bytes - type: R - reset_val: 0 - msb: 7 - lsb: 2 - - field_name: MODE[1] - description: > - Always 0 - type: R - reset_val: 0 - msb: 1 - lsb: 1 - - field_name: MODE[0] - description: > - 0 = Direct mode, 1 = vectored mode - type: WARL - reset_val: 1 - msb: 0 - lsb: 0 - -### Not supported in CV32E40X ### -#- csr: menvcfg -# description: > -# Machine Environment Configuration Register -# address: 0x30A -# privilege_mode: M -# rv32: -# - field_name: FIOM -# description: > -# Fence of IO Implies Memory -# type: RW -# reset_val: 0 -# msb: 0 -# lsb: 0 -# - field_name: CBIE -# description: > -# Cache Block Invalidate Instruction Enable -# type: RW -# reset_val: 0 -# msb: 5 -# lsb: 4 -# - field_name: CBCFE -# description: > -# Cache Block Clean and Flush Instruction Enable -# type: RW -# reset_val: 0 -# msb: 6 -# lsb: 6 -# - field_name: CBZE -# description: > -# Cache Block Zero Instruction Enable -# type: RW -# reset_val: 0 -# msb: 7 -# lsb: 7 - -- csr: mstatush - description: > - Machine ISA register - address: 0x310 - privilege_mode: M - rv32: - - field_name: SBE - description: > - Supervisor Big Endian Memory Access (Always zero) - type: R - reset_val: 0 - msb: 4 - lsb: 4 - - field_name: MBE - description: > - Machine Mode Big Endian Memory Access (Always zero) - type: R - reset_val: 0 - msb: 5 - lsb: 5 - -### Not supported in CV32E40x ### -#- csr: menvcfgh -# description: > -# Machine Environment Configuration (h) -# address: 0x31A -# privilege_mode: M -# rv32: -# - field_name: STCE -# description: > -# STimecmp Enable -# type: RW -# reset_val: 0 -# msb: 31 -# lsb: 31 - -- csr: mcountinhibit - description: > - Machine Counter-Inhibit - address: 0x320 - privilege_mode: M - rv32: - - field_name: Selectors 31..4 - description: > - Selectors for mhpmcounter31..4 inhibit (assuming NUM_MHPMCOUNTER set to 1) - type: R - reset_val: 0 - msb: 31 - lsb: 4 - - field_name: Selectors 3 - description: > - Selectors for mhpmcounter3 inhibit (assuming NUM_MHPMCOUNTER set to 1) - type: WARL - reset_val: 1 - msb: 3 - lsb: 3 - - field_name: minstret inhibit - description: > - Inhibit minstret counting - type: WARL - reset_val: 1 - msb: 2 - lsb: 2 - - field_name: zero - description: > - Zero - type: R - reset_val: 0 - msb: 1 - lsb: 1 - - field_name: mcycle inhibit - description: > - Inhibit mcycle counting - type: WARL - reset_val: 1 - msb: 0 - lsb: 0 -# MHPMEVENT4..31 not full modeled by RM -- csr: mhpmevent3 - description: > - (HPM) Machine Performance-Monitoring Event Selector 3 - address: 0x323 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mscratch - description: > - Machine Scratch-pad Register - address: 0x340 - privilege_mode: M - rv32: - - field_name: MXL - description: > - Scratch-pad - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mepc - description: > - Machine Exception Program Counter - address: 0x341 - privilege_mode: M - rv32: - - field_name: EPC - description: > - Exception PC[31:1] - type: WARL - reset_val: 0 - msb: 31 - lsb: 1 - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 0 - lsb: 0 -- csr: mcause - description: > - Machine Exception Cause - address: 0x342 - privilege_mode: M - rv32: - - field_name: Interrupt - description: > - Set when exception triggered by interrupt - type: WARL - reset_val: 0 - msb: 31 - lsb: 31 - - field_name: zero - description: > - Always zero - type: R - reset_val: 0 - msb: 30 - lsb: 8 - - field_name: ecode - description: > - Exception Code - type: WARL - reset_val: 0 - msb: 7 - lsb: 0 -- csr: mtval - description: > - Machine Trap Value - address: 0x343 - privilege_mode: M - rv32: - - field_name: Trap value - description: > - Machine Trap Value - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mip - description: > - Machine Interrupt Pending - address: 0x344 - privilege_mode: M - rv32: - - field_name: Fast - description: > - Fast Interrupts Pending - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: zero - description: > - Always zero - type: R - reset_val: 0 - msb: 15 - lsb: 12 - - field_name: External - description: > - Machine External Interrupt Pending - type: R - reset_val: 0 - msb: 11 - lsb: 11 - - field_name: Timer - description: > - Machine Timer Interrupt Pending - type: R - reset_val: 0 - msb: 7 - lsb: 7 - - field_name: Software - description: > - Machine Software Interrupt Pending - type: R - reset_val: 0 - msb: 3 - lsb: 3 - -### Not Supported in CV32E40X ### -#- csr: henvcfg -# description: > -# Hypervisor Environment Configuration Register -# address: 0x61A -# privilege_mode: M -# rv32: -# - field_name: FIOM -# description: > -# Fence of IO Implies Memory -# type: R -# reset_val: 0 -# msb: 0 -# lsb: 0 -# - field_name: CBIE -# description: > -# Cache Block Invalidate Instruction Enable -# type: R -# reset_val: 0 -# msb: 5 -# lsb: 4 -# - field_name: CBCFE -# description: > -# Cache Block Clean and Flush Instruction Enable -# type: R -# reset_val: 0 -# msb: 6 -# lsb: 6 -# - field_name: CBZE -# description: > -# Cache Block Zero Instruction Enable -# type: R -# reset_val: 0 -# msb: 7 -# lsb: 7 - -### Not Supported in CV32E40X ### -#- csr: henvcfgh -# description: > -# Hypervisor Environment Configuration (h) -# address: 0x31A -# privilege_mode: M -# rv32: -# - field_name: STCE -# description: > -# STimecmp Enable -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 31 - -### Not Supported in CV32E40X ### -#- csr: mseccfg -# description: > -# Machine Security Configuration -# address: 0x747 -# privilege_mode: M -# rv32: -# - field_name: MML -# description: > -# Machine Mode Lockdown -# type: RW -# reset_val: 0 -# msb: 0 -# lsb: 0 -# - field_name: MMWP -# description: > -# Machine Mode Whitelist Policy -# type: RW -# reset_val: 0 -# msb: 1 -# lsb: 1 -# - field_name: RLB -# description: > -# Rule Locking Bypass -# type: RW -# reset_val: 0 -# msb: 2 -# lsb: 2 -# - field_name: USEED -# description: > -# User Mode Seed Access (Always Zero on cv32e40x) -# type: R -# reset_val: 0 -# msb: 8 -# lsb: 8 -# - field_name: SSEED -# description: > -# Supervisor Mode Seed Access (Always zero on cv32e40x) -# type: R -# reset_val: 0 -# msb: 9 -# lsb: 9 - -### Not supported in CV32E40X ### -#- csr: mseccfgh -# description: > -# Machine Security Configuration (h) -# address: 0x757 -# privilege_mode: M -# rv32: -# - field_name: Zero -# description: > -# Always zero -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 - -- csr: tselect - description: > - Trigger Select Register - address: 0x7A0 - privilege_mode: M - rv32: - - field_name: Trigger - description: > - Trigger select field - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: tdata1 - description: > - Trigger Data Register 1 - address: 0x7A1 - privilege_mode: M - rv32: - - field_name: Type - description: > - Address/data match trigger type - type: R - reset_val: 2 - msb: 31 - lsb: 28 - - field_name: dmode - description: > - Only debug mode can write tdata registers - type: R - reset_val: 1 - msb: 27 - lsb: 27 - - field_name: MaskMax - description: > - Only exact matching supported - type: R - reset_val: 0 - msb: 26 - lsb: 21 - - field_name: Hit - description: > - Hit indication not supported - type: R - reset_val: 0 - msb: 20 - lsb: 20 - - field_name: Select - description: > - Only address matching is supported - type: R - reset_val: 0 - msb: 19 - lsb: 19 - - field_name: Timing - description: > - Break before the instruction at the specified address - type: R - reset_val: 0 - msb: 18 - lsb: 18 - - field_name: Sizelo - description: > - Match accesses of any size - type: R - reset_val: 0 - msb: 17 - lsb: 16 - - field_name: Action - description: > - Enter debug mode on match - type: R - reset_val: 1 - msb: 15 - lsb: 12 - - field_name: Chain - description: > - Chaining not supported - type: R - reset_val: 0 - msb: 11 - lsb: 11 - - field_name: Match - description: > - Match the whole address - type: R - reset_val: 0 - msb: 10 - lsb: 7 - - field_name: m - description: > - Match in M-mode - type: R - reset_val: 1 - msb: 6 - lsb: 6 - - field_name: zero - description: > - Always zero - type: R - reset_val: 0 - msb: 5 - lsb: 5 - - field_name: s - description: > - S-mode not supported - type: R - reset_val: 0 - msb: 4 - lsb: 4 - - field_name: u - description: > - U-mode not supported - type: R - reset_val: 0 - msb: 3 - lsb: 3 - - field_name: execute - description: > - Enable matching on instruction address. Only writeable in Debug mode. - type: R - reset_val: 0 - msb: 2 - lsb: 2 - - field_name: store - description: > - Store address/data matching not supported - type: R - reset_val: 0 - msb: 1 - lsb: 1 - - field_name: load - description: > - Load address/data matching not supported - type: R - reset_val: 0 - msb: 0 - lsb: 0 -- csr: tdata2 - description: > - Trigger Data Register 2 - address: 0x7A2 - privilege_mode: M - rv32: - - field_name: Data - description: > - Native triggers are not supported, so writes to this register from M-Mode will be ignored. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: tdata3 - description: > - Trigger Data Register 3 - address: 0x7A3 - privilege_mode: M - rv32: - - field_name: Zero - description: > - CV32E40X does not support the features requiring this register. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: tinfo - description: > - Trigger Info - address: 0x7A4 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Info - description: > - Only type 2 supported - type: R - reset_val: 4 - msb: 15 - lsb: 0 -- csr: mcontext - description: > - Machine Context Register - address: 0x7A8 - privilege_mode: M - rv32: - - field_name: Zero - description: > - CV32E40X does not support the features requiring this register. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mscontext - description: > - Supervisor Context Register - address: 0x7AA - privilege_mode: M - rv32: - - field_name: Zero - description: > - CV32E40X does not support the features requiring this register. - type: R - reset_val: 0 - msb: 31 - lsb: 0 -- csr: tcontrol - description: > - Trigger control - address: 0x7A5 - privilege_mode: M - rv32: - - field_name: zero (reserved) - description: > - Always return zero - type: R - reset_val: 0 - msb: 31 - lsb: 0 -############################################################################### -# mvendorid, marchid, mimpid, mhartid and mconfigptr are temporarily -# excluded from auto-generation of access testing as all bits in these CSRs are -# RO, so any attempt to write them causes an illegal instruction exception. -# Access modes to these CSRs is tested in a separate, manually written test- -# program. -# -#- csr: mvendorid -# description: > -# Machine Vendor ID -# address: 0xF11 -# privilege_mode: M -# rv32: -# - field_name: Bank -# description: > -# Number of continuation codes in JEDEC manufacturer ID -# type: R -# reset_val: 12 -# msb: 31 -# lsb: 7 -# - field_name: ID -# description: > -# Final byte of JEDEC manufacturer ID, discarding the parity bit. -# type: R -# reset_val: 2 -# msb: 6 -# lsb: 0 -#- csr: marchid -# description: > -# Machine Architecture ID -# address: 0xF12 -# privilege_mode: M -# rv32: -# - field_name: ID -# description: > -# Machine Architecture ID of CV32E40X is 4 -# type: R -# reset_val: 4 -# msb: 31 -# lsb: 0 -#- csr: mimpid -# description: > -# Machine Implementation ID -# address: 0xF13 -# privilege_mode: M -# rv32: -# - field_name: ID -# description: > -# Machine Implementation ID -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: mhartid -# description: > -# Machine Hart ID -# address: 0xF14 -# privilege_mode: M -# rv32: -# - field_name: Hart -# description: > -# mhartid_i -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 -#- csr: mconfigptr -# description: > -# Machine configuration pointer -# address: 0xF15 -# privilege_mode: M -# rv32: -# -field_name: zero (reserved) -# description: > -# Always return zero -# type: R -# reset_val: 0 -# msb: 31 -# lsb: 0 diff --git a/cv32e40x/env/corev-dv/cv32e40x_debug_rom_gen.sv b/cv32e40x/env/corev-dv/cv32e40x_debug_rom_gen.sv deleted file mode 100644 index ba1b8aa9b9..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_debug_rom_gen.sv +++ /dev/null @@ -1,177 +0,0 @@ -//Copyright 2020 Silicon Labs, Inc. - -//This file, and derivatives thereof are licensed under the -//Solderpad License, Version 2.0 (the "License"); -//Use of this file means you agree to the terms and conditions -//of the license and are in full compliance with the License. -//You may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.0/ -// -//Unless required by applicable law or agreed to in writing, software -//and hardware implementations thereof -//distributed under the License is distributed on an "AS IS" BASIS, -//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. -//See the License for the specific language governing permissions and -//limitations under the License. -// -// -class cv32e40x_debug_rom_gen extends riscv_debug_rom_gen; - string debug_dret[$]; - - `uvm_object_utils(cv32e40x_debug_rom_gen) - - function new (string name = ""); - super.new(name); - endfunction - - virtual function void gen_program(); - string sub_program_name[$] = {}; - cv32e40x_instr_gen_config cfg_corev; - - // CORE-V Addition - // Insert section info so linker can place - // debug code at the correct adress - instr_stream.push_back(".section .debugger, \"ax\""); - - // CORE-V Addition - // Cast CORE-V derived handle to enable fetching core-v config fields - `DV_CHECK($cast(cfg_corev, cfg)) - - // Randomly add a WFI at start of ddebug rom - // This will be treaed as a NOP always, but added here to close instructon - // combination coverage (i.e. ebreak->wfi) - if (!cfg.no_wfi) begin - randcase - 1: debug_main.push_back("wfi"); - 4: begin /* insert nothing */ end - endcase - end - - // The following is directly copied from riscv_debug_rom_gen.sv - // Changes: - // - Altering the stack push/pop to use custom debugger stack - if (!cfg.gen_debug_section) begin - // If the debug section should not be generated, we just populate it - // with a dret instruction. - debug_main = {dret}; - gen_section($sformatf("%0sdebug_rom", hart_prefix(hart)), debug_main); - end else begin - // Check the debugger stack pointer to check for a null pointer in cfg.dp - // and initialize - debug_main.push_back($sformatf("bne x%0d, zero, dp_init_done # One time initialization of the debug pointer (x%0d)", cfg_corev.dp, cfg_corev.dp)); - debug_main.push_back($sformatf("la x%0d, debugger_stack_end", cfg_corev.dp)); - debug_main.push_back($sformatf("dp_init_done:")); - - if (cfg.enable_ebreak_in_debug_rom) begin - debug_main.push_back("# This ebreak header will ensure that re-entry of debug handler will not re-push stack"); - debug_main.push_back("# If dscratch0 is non-zero then jump directly to debug_end to pop stack and end then dret"); - gen_ebreak_header(); - end - // Need to save off GPRs to avoid modifying program flow - push_gpr_to_debugger_stack(cfg_corev, debug_main); - // Signal that the core entered debug rom only if the rom is actually - // being filled with random instructions to prevent stress tests from - // having to execute unnecessary push/pop of GPRs on the stack ever - // time a debug request is sent - gen_signature_handshake(debug_main, CORE_STATUS, IN_DEBUG_MODE); - if (cfg.enable_ebreak_in_debug_rom) begin - // send dpc and dcsr to testbench, as this handshake will be - // executed twice due to the ebreak loop, there should be no change - // in their values as by the Debug Mode Spec Ch. 4.1.8 - gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DCSR)); - gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DPC)); - end - if (cfg.set_dcsr_ebreak) begin - // We want to set dcsr.ebreak(m/s/u) to 1'b1, depending on what modes - // are available. - // TODO(udinator) - randomize the dcsr.ebreak setup - gen_dcsr_ebreak(); - end - if (cfg.enable_debug_single_step) begin - gen_single_step_logic(); - end - gen_dpc_update(); - // write DCSR to the testbench for any analysis - gen_signature_handshake(.instr(debug_main), .signature_type(WRITE_CSR), .csr(DCSR)); - if (cfg.enable_ebreak_in_debug_rom || cfg.set_dcsr_ebreak) begin - gen_increment_ebreak_counter(); - end - format_section(debug_main); - gen_sub_program(hart, sub_program[hart], sub_program_name, - cfg.num_debug_sub_program, 1'b1, "debug_sub"); - main_program[hart] = riscv_instr_sequence::type_id::create("debug_program"); - main_program[hart].instr_cnt = cfg.debug_program_instr_cnt; - main_program[hart].is_debug_program = 1; - main_program[hart].cfg = cfg; - `DV_CHECK_RANDOMIZE_FATAL(main_program[hart]) - main_program[hart].gen_instr(.is_main_program(1'b1), .no_branch(cfg.no_branch_jump)); - gen_callstack(main_program[hart], sub_program[hart], sub_program_name, - cfg.num_debug_sub_program); - main_program[hart].post_process_instr(); - main_program[hart].generate_instr_stream(.no_label(1'b1)); - insert_sub_program(sub_program[hart], debug_main); - debug_main = {debug_main, main_program[hart].instr_string_list}; - - - // Create the ebreak end - if (cfg.enable_ebreak_in_debug_rom) begin - gen_ebreak_footer(); - end - pop_gpr_from_debugger_stack(cfg_corev, debug_end); - if (cfg.enable_ebreak_in_debug_rom) begin - gen_restore_ebreak_scratch_reg(); - end - - // Create the debug_dret section - //pop_gpr_from_debugger_stack(cfg_corev, debug_dret); - //debug_dret = {debug_dret, dret}; - - //format_section(debug_end); - gen_section($sformatf("%0sdebug_rom", hart_prefix(hart)), debug_main); - - // Randomly add a WFI at end of debug rom - // This will be treaed as a NOP always, but added here to close instructon - // combination coverage (i.e. ebreak->wfi) - if (!cfg.no_wfi) begin - randcase - 1: debug_end.push_back("wfi"); - 4: begin /* insert nothing */ end - endcase - end - - debug_end = {debug_end, dret}; - - gen_section($sformatf("%0sdebug_end", hart_prefix(hart)), debug_end); - end - gen_debug_exception_handler(); - endfunction : gen_program - - virtual function void gen_debug_exception_handler(); - - cv32e40x_instr_gen_config cfg_corev; - - // CORE-V Addition - // Cast CORE-V derived handle to enable fetching core-v config fields - `DV_CHECK($cast(cfg_corev, cfg)) - - // Insert section info so linker can place - // debug exception code at the correct adress - instr_stream.push_back(".section .debugger_exception, \"ax\""); - - if (cfg_corev.exit_on_debug_exception) begin - str = {"la x1, test_done", "jr x1"}; - end - else begin - str = {"ebreak"}; - end - - gen_section($sformatf("%0sdebug_exception", hart_prefix(hart)), str); - - // Insert section info to place remaining code in the - // original section - instr_stream.push_back(".section text"); - endfunction : gen_debug_exception_handler - -endclass : cv32e40x_debug_rom_gen - diff --git a/cv32e40x/env/corev-dv/cv32e40x_fencei_instr_lib.sv b/cv32e40x/env/corev-dv/cv32e40x_fencei_instr_lib.sv deleted file mode 100644 index c2252ff014..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_fencei_instr_lib.sv +++ /dev/null @@ -1,525 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - - -// store_fencei_load: -// Run a store, then a fencei, and finally load from the same address as the store. -// Even though fencei meddles with the pipeline, the stores shall come through. -class corev_store_fencei_load_instr_stream extends riscv_load_store_rand_instr_stream; - - `uvm_object_utils(corev_store_fencei_load_instr_stream) - - function new(string name = ""); - super.new(name); - endfunction : new - - function void post_randomize(); - riscv_instr instr; - riscv_instr instr_list_new[$]; - int idx_insert; - - // Generate a default big chunk of instructions as a "substrate" to work on - super.post_randomize(); - - // The following instrs add to "instr_list_new", to be merged into "instr_list" later - - // Store - instr = riscv_instr::get_rand_instr(.include_instr({SW, SH, SB})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name inside {SW, SH, SB}; - rs1 == rs1_reg; - imm == offset[0]; - , "failed to randomize store" - ) - instr.comment = "store_fencei_load: store"; - instr_list_new.push_back(instr); - - // Fence.i - instr = riscv_instr::get_instr(FENCE_I); - instr.comment = "store_fencei_load: fencei"; - instr_list_new.push_back(instr); - - // Load - instr = riscv_instr::get_rand_instr(.include_instr({LW, LH, LHU, LB, LBU})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name inside {LW, LH, LHU, LB, LBU}; - rs1 == rs1_reg; - imm == offset[0]; - rd != rs1_reg; - !(rd inside {cfg.reserved_regs}); - , "failed to randomize load" - ) - instr.comment = "store_fencei_load: load"; - instr_list_new.push_back(instr); - - // Combine the final instr list - idx_insert = $urandom_range(1, instr_list.size() - 1); // Not before the LA - instr_list = {instr_list[0:idx_insert-1], instr_list_new, instr_list[idx_insert:$]}; - - // Get a nice enumeration label for anything not labeled - foreach (instr_list[i]) begin - instr_list[i].atomic = 1; - if (instr_list[i].label == "") begin - instr_list[i].label = $sformatf("%0d", i); - end - end - endfunction : post_randomize - -endclass : corev_store_fencei_load_instr_stream - - -// store_fencei_exec: -// The main instructions are [SW, FENCE_I, (random1), (random2)]. -// Before that SW is some setup code. -// The SW overwrites the data of random1 with the data from random2. -// Hence, one shall never see random1 execute, but rather 2 consecutive random2. -class corev_store_fencei_exec_instr_stream extends riscv_load_store_rand_instr_stream; - - static int idx_label; - - rand riscv_reg_t addr_reg; - rand riscv_reg_t data_reg; - - constraint dont_overwrite_data_reg { - addr_reg != data_reg; // Don't overwrite the data that is to be written - } - constraint dont_pollute_reserved_regs { - !(addr_reg inside {cfg.reserved_regs}); - !(data_reg inside {cfg.reserved_regs}); - } - constraint dont_store_in_x0 { - addr_reg != ZERO; - data_reg != ZERO; - } - - `uvm_object_utils(corev_store_fencei_exec_instr_stream) - - function new(string name = ""); - super.new(name); - endfunction : new - - function void post_randomize(); - riscv_instr instr; - riscv_pseudo_instr pseudo; - corev_directive_instr directive; - string label_exec; - string label_dummy; - - // Calculate labels with right index - label_exec = $sformatf("store_fencei_exec__exec_%0d", idx_label); - label_dummy = $sformatf("store_fencei_exec__dummy_%0d", idx_label); - idx_label++; - - // Load address of dummy instruction - pseudo = riscv_pseudo_instr::type_id::create("LA"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LA; - rd == addr_reg; - , "failed to randomize LA for dummy instr" - ) - pseudo.imm_str = label_dummy; - pseudo.comment = "store_fencei_exec: la dummy"; - instr_list.push_back(pseudo); - - // Load data of dummy instruction - instr = riscv_instr::get_instr(LW); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LW; - rs1 == addr_reg; - imm == 0; - rd == data_reg; - , "failed to randomize LW for dummy instruction" - ) - instr.comment = "store_fencei_exec: lw dummy"; - instr_list.push_back(instr); - - // Load address of exec instruction - pseudo = riscv_pseudo_instr::type_id::create("LA"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LA; - rd == addr_reg; - , "failed to randomize LA for exec instruction" - ) - pseudo.imm_str = label_exec; - pseudo.comment = "store_fencei_exec: la exec"; - instr_list.push_back(pseudo); - - // Store - instr = riscv_instr::get_instr(SW); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == SW; - rs1 == addr_reg; - imm == 0; - rs2 == data_reg; - , "failed to randomize store" - ) - instr.comment = "store_fencei_exec: store"; - instr_list.push_back(instr); - - // Fencei - instr = riscv_instr::get_instr(FENCE_I); - instr.comment = "store_fencei_exec: fencei"; - instr_list.push_back(instr); - - // Add norvc/rvc guards around the instr after fencei - directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option push"; - instr_list.push_back(directive); - directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option norvc"; - instr_list.push_back(directive); - - // Exec - instr = riscv_instr::get_rand_instr(.exclude_instr({NOP}), .exclude_group({RV32C})); - instr.imm.rand_mode(0); - `DV_CHECK_RANDOMIZE_FATAL(instr, "failed to randomize exec instruction" - ) - case (instr.instr_name) - JAL: begin - instr.imm_str = "1b"; - end - BEQ, BNE, BLT, BGE, BLTU, BGEU: begin - instr.imm_str = "1b"; - instr.branch_assigned = 1'b1; - end - endcase - instr.comment = "store_fencei_exec: exec"; - instr.label = label_exec; - instr_list.push_back(instr); - - // Dummy, for replacing exec - instr = riscv_instr::get_rand_instr( - .include_category({LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}), - .exclude_group({RV32C})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - (category inside {LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}); - // Note: Several of the constraints could be relaxed, but it turns really complicated - !(rd inside {cfg.reserved_regs}); - !((rd == ZERO) && (instr_name inside {ADDI, C_ADDI})); - , "failed to randomize dummy instruction" - ) - - // restore compiler options - instr.comment = "store_fencei_exec: dummy"; - instr.label = label_dummy; - instr_list.push_back(instr); - - directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option pop"; - instr_list.push_back(directive); - - // Get a nice enumeration label for anything not labeled - foreach (instr_list[i]) begin - instr_list[i].atomic = 1; - if (instr_list[i].label == "") begin - instr_list[i].label = $sformatf("%0d", i); - end - end - endfunction : post_randomize - -endclass : corev_store_fencei_exec_instr_stream - - -// vp_fencei_exec: -// 1) Configures and enables the fencei-triggered memory-changing vp (instr_list_pre). -// 2) Runs a bunch of random instruction with a fence.i somewhere in between (instr_list). -// 3) (Lets vp do its thing). -// 4) Disables vp (instr_list_post). -class corev_vp_fencei_exec_instr_stream extends riscv_load_store_rand_instr_stream; - - static int idx_label; - rand riscv_reg_t vp_reg; - rand riscv_reg_t tmp_reg; - riscv_instr instr_list_pre[$]; - riscv_instr instr_list_post[$]; - - localparam CV_VP_REGISTER_BASE = 32'h 00800000; - localparam CV_VP_FENCEI_TAMPER_OFFSET = 32'h 00000100; - localparam CV_VP_FENCEI_TAMPER_BASE = (CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET); - // Note: Would preferably be from uvme_cv32e40x_pkg, which is seemingly not easily available in core-v compilation - - constraint dont_overwrite_regs { - vp_reg != tmp_reg; // Don't overwrite the data that is to be written - } - constraint dont_pollute_reserved_regs { - !(vp_reg inside {cfg.reserved_regs, reserved_rd}); - !(tmp_reg inside {cfg.reserved_regs, reserved_rd}); - } - constraint dont_store_in_x0 { - vp_reg != ZERO; - tmp_reg != ZERO; - } - - `uvm_object_utils(corev_vp_fencei_exec_instr_stream) - - function new(string name = ""); - super.new(name); - endfunction : new - - function void post_randomize(); - riscv_instr instr; - riscv_pseudo_instr pseudo; - corev_directive_instr directive; - string label_fencei; - string label_dummy; - int idx_fencei; - - // Calculate labels with right index - label_fencei = $sformatf("vp_fencei_exec__fencei_%0d", idx_label); - label_dummy = $sformatf("vp_fencei_exec__dummy_%0d", idx_label); - idx_label++; - - - // Generate the random code to be executed - - // Generate a default big chunk of instructions as a "substrate" to work on - super.post_randomize(); - - // Add a fence.i to a random location, and label it - instr = riscv_instr::get_instr(FENCE_I); - instr.comment = "vp_fencei_exec: fencei"; - instr.label = label_fencei; - idx_fencei = $urandom_range(0, instr_list.size() - 1); - while(!is_ok_target(instr_list[idx_fencei])) begin - idx_fencei++; - if (idx_fencei == instr_list.size()) begin - idx_fencei = 0; - end - end - instr_list.insert(idx_fencei, instr); - // Add norvc/rvc guards around the instr after fencei - directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option norvc"; - instr_list.insert(idx_fencei + 1, directive); - directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option rvc"; - instr_list.insert(idx_fencei + 3, directive); - - // Add a dummy instr at the top - instr = riscv_instr::get_rand_instr( - .exclude_instr({NOP}), - .include_category({LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}), - .exclude_group({RV32C})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - (category inside {LOAD, SHIFT, ARITHMETIC, LOGICAL, COMPARE, SYNCH}); - // Note: Several of the constraints could be relaxed, but it turns really complicated - !(rd inside {cfg.reserved_regs, reserved_rd}); - !((rd == ZERO) && (instr_name inside {ADDI, C_ADDI})); - instr_name != NOP; - , "failed to randomize dummy instruction" - ) - instr.comment = "vp_fencei_exec: dummy"; - instr.label = label_dummy; - // Add rvc (nb, reverse order, 3/3) - directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option rvc"; - instr_list.push_front(directive); - // Add instr (nb, reverse order, 2/3) - instr_list.push_front(instr); - // Add norvc (nb, reverse order, 1/3) - directive = corev_directive_instr::type_id::create("corev_directive_instr"); - directive.directive = ".option norvc"; - instr_list.push_front(directive); - - - // Configure the vp addr register - - // Load addr of fencei - pseudo = riscv_pseudo_instr::type_id::create("LA"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LA; - rd == tmp_reg; - , "failed to randomize LA" - ) - pseudo.imm_str = label_fencei; - pseudo.comment = "vp_fencei_exec: la fencei"; - instr_list_pre.push_back(pseudo); - - // Add 4 to get the addr of the instr following fencei - instr = riscv_instr::get_instr(ADDI); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == ADDI; - rs1 == tmp_reg; - rd == tmp_reg; - imm == 4; - , "failed to randomize addi 4" - ) - instr.comment = "vp_fencei_exec: +4"; - instr_list_pre.push_back(instr); - - // Load the addr of the vp's register base - pseudo = riscv_pseudo_instr::type_id::create("LI"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LI; - rd == vp_reg; - , "failed to randomize LI" - ) - pseudo.imm_str = $sformatf("0x%08x", CV_VP_FENCEI_TAMPER_BASE); - pseudo.comment = "vp_fencei_exec: LI vp addr reg addr"; - instr_list_pre.push_back(pseudo); - - // Store the addr in the vp's addr register - instr = riscv_instr::get_instr(SW); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == SW; - rs1 == vp_reg; // addr of mem to put in - rs2 == tmp_reg; // data to put in mem - imm == 4; // 4, to access reg 1 of vp, namely "addr" - , "failed to randomize SW" - ) - instr.comment = "vp_fencei_exec: fencei+4 -> vpaddr"; - instr_list_pre.push_back(instr); - - - // Configure the vp data register - - // Load address of dummy instruction - pseudo = riscv_pseudo_instr::type_id::create("LA"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LA; - rd == tmp_reg; - , "failed to randomize LA, dummy" - ) - pseudo.imm_str = label_dummy; - pseudo.comment = "vp_fencei_exec: la dummy"; - instr_list_pre.push_back(pseudo); - - // Load data of dummy instruction - instr = riscv_instr::get_instr(LW); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LW; - rs1 == tmp_reg; - imm == 0; - rd == tmp_reg; - , "failed to randomize LW for dummy instruction" - ) - instr.comment = "vp_fencei_exec: lw dummy"; - instr_list_pre.push_back(instr); - - // Load the addr of the vp's register base - pseudo = riscv_pseudo_instr::type_id::create("LI"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LI; - rd == vp_reg; - , "failed to randomize LI, data" - ) - pseudo.imm_str = $sformatf("0x%08x", CV_VP_FENCEI_TAMPER_BASE); - pseudo.comment = "vp_fencei_exec: LI vp reg base"; - instr_list_pre.push_back(pseudo); - - // Store the data in the vp's data register - instr = riscv_instr::get_instr(SW); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == SW; - rs1 == vp_reg; // addr of mem to put in - rs2 == tmp_reg; // data to put in mem - imm == 8; // 8, to access reg 2 of vp, namely "data" - , "failed to randomize SW" - ) - instr.comment = "vp_fencei_exec: dummy -> vpdata"; - instr_list_pre.push_back(instr); - - - // Enable vp before running the random instructions - - // Load immediate 1 - pseudo = riscv_pseudo_instr::type_id::create("LI"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LI; - rd == tmp_reg; - , "failed to randomize LI, 1" - ) - pseudo.imm_str = "1"; - pseudo.comment = "vp_fencei_exec: LI 1"; - instr_list_pre.push_back(pseudo); - - // Load the addr of the vp's register base - pseudo = riscv_pseudo_instr::type_id::create("LI"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LI; - rd == vp_reg; - , "failed to randomize LI, enab" - ) - pseudo.imm_str = $sformatf("0x%08x", CV_VP_FENCEI_TAMPER_BASE); - pseudo.comment = "vp_fencei_exec: LI vp reg base"; - instr_list_pre.push_back(pseudo); - - // Store the 1 in the vp's enabled register - instr = riscv_instr::get_instr(SW); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == SW; - rs1 == vp_reg; // addr of mem to put in - rs2 == tmp_reg; // data to put in mem - imm == 0; // 0, to access reg 0 of vp, namely "enabled" - , "failed to randomize SW" - ) - instr.comment = "vp_fencei_exec: enabled"; - instr_list_pre.push_back(instr); - - - // Disable vp when done - - // Load the addr of the vp's register base - pseudo = riscv_pseudo_instr::type_id::create("LI"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(pseudo, - pseudo_instr_name == LI; - rd == vp_reg; - , "failed to randomize LI, disab" - ) - pseudo.imm_str = $sformatf("0x%08x", CV_VP_FENCEI_TAMPER_BASE); - pseudo.comment = "vp_fencei_exec: LI vp reg base"; - instr_list_post.push_back(pseudo); - - // Store a 0 in the vp's enabled register - instr = riscv_instr::get_instr(SW); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == SW; - rs1 == vp_reg; // addr of mem to put in - rs2 == ZERO; // data to put in mem - imm == 0; // 0, to access reg 0 of vp, namely "enabled" - , "failed to randomize SW" - ) - instr.comment = "vp_fencei_exec: disabled"; - instr_list_post.push_back(instr); - - - // Combine the final instr list - - instr_list = {instr_list_pre, instr_list, instr_list_post}; - - - // Get a nice enumeration label for anything not labeled - - foreach (instr_list[i]) begin - instr_list[i].atomic = 1; - if (instr_list[i].label == "") begin - instr_list[i].label = $sformatf("%0d", i); - end - end - endfunction : post_randomize - - function logic is_ok_target(riscv_instr instr); - // Note: Could allow 16bit instrs, but that requires more accommodations - return ( - (instr.group != RV32C) - && (instr.instr_name != NOP) - && !((instr.rd == ZERO) && (instr.instr_name inside {ADDI, C_ADDI})) - && !(instr.rd inside {cfg.reserved_regs, reserved_rd}) - ); - endfunction : is_ok_target - -endclass : corev_vp_fencei_exec_instr_stream diff --git a/cv32e40x/env/corev-dv/cv32e40x_instr_base_test.sv b/cv32e40x/env/corev-dv/cv32e40x_instr_base_test.sv deleted file mode 100644 index 36bac6610c..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_instr_base_test.sv +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2018 Google LLC - * Copyright 2020 OpenHW Group - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//------------------------------------------------------------------------------ -// CORE-V instruction generator base test: -// - extension of the RISC-V instruction generator base test. -// -//------------------------------------------------------------------------------ - -class cv32e40x_instr_base_test extends corev_instr_base_test; - - cv32e40x_pma_cfg pma_cfg; - bit enable_pma; - - `uvm_component_utils(cv32e40x_instr_base_test) - - - function new(string name="", uvm_component parent=null); - super.new(name, parent); - endfunction - - virtual function void build_phase(uvm_phase phase); - cv32e40x_ldgen_c linker_generator; - override_asm_program_gen(); - override_gen_config(); - override_compressed_instr(); - override_privil_reg(); - override_privil_common_seq(); - override_debug_rom_gen(); - super.build_phase(phase); - linker_generator = new(); - linker_generator.gen_pma_linker_scripts(); - endfunction - - virtual function void override_asm_program_gen(); - uvm_factory::get().set_type_override_by_type(corev_asm_program_gen::get_type(), - cv32e40x_asm_program_gen::get_type()); - endfunction - - virtual function void override_gen_config(); - uvm_factory::get().set_type_override_by_type(riscv_instr_gen_config::get_type(), - cv32e40x_instr_gen_config::get_type()); - endfunction - - virtual function void override_compressed_instr(); - uvm_factory::get().set_type_override_by_type(riscv_C_LUI_instr::get_type(), - cv32e40x_C_LUI_instr::get_type()); - endfunction - - virtual function void override_privil_reg(); - uvm_factory::get().set_type_override_by_type(riscv_privil_reg::get_type(), - cv32e40x_privil_reg::get_type()); - endfunction - - virtual function void override_privil_common_seq(); - uvm_factory::get().set_type_override_by_type(riscv_privileged_common_seq::get_type(), - cv32e40x_privileged_common_seq::get_type()); - endfunction - - virtual function void override_debug_rom_gen(); - uvm_factory::get().set_type_override_by_type(riscv_debug_rom_gen::get_type(), - cv32e40x_debug_rom_gen::get_type()); - endfunction - - virtual function void apply_directed_instr(); - endfunction - -endclass : cv32e40x_instr_base_test diff --git a/cv32e40x/env/corev-dv/cv32e40x_instr_gen_config.sv b/cv32e40x/env/corev-dv/cv32e40x_instr_gen_config.sv deleted file mode 100644 index fb8095a963..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_instr_gen_config.sv +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2018 Google LLC - * Copyright 2020 OpenHW Group - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//------------------------------------------------------------------------------ -// CORE-V instruction generator configuration class: -// - extension of the RISC-V instruction generator base test. -// -// The base test Uses the factory to replace riscv_instr_gen_config with corev_instr_gen_config -//------------------------------------------------------------------------------ - -class cv32e40x_instr_gen_config extends riscv_instr_gen_config; - - // External config control (plusarg) to enable/disable fast_interrupt handlers - bit enable_fast_interrupt_handler; - bit enable_pma; - bit exit_on_debug_exception; - cv32e40x_pma_cfg pma_cfg; - - // Knob to set zero fast interrupt handler - // Knob is needed because FIXED MTVEC mode won't work with fast interrupt handlers - rand bit knob_zero_fast_intr_handlers; - - // Mask for using a fast interrupt handler (mret only), relying on h/W interrupt ack mechanism - rand bit [31:0] use_fast_intr_handler; - - // Random register for debug stack pointer - rand riscv_reg_t dp; - - mem_region_t mem_region_override[$]; - - constraint dp_c { - // Debug pointer may not be the return address, stack pointer, nor thread pointer - if (!gen_debug_section) { - dp == ZERO; - } else { - !(dp inside {sp, tp, ra, scratch_reg, GP, RA, ZERO}); - foreach (gpr[i]) { - !(gpr[i] inside {dp}); - } - } - } - - // CV32E40X requires the MTVEC table to be aligned to 256KB boundaries - constraint mtvec_c { - tvec_alignment == 8; - } - - // Constrain fast interrupt handler - constraint knob_zero_fast_intr_dist_c { - solve knob_zero_fast_intr_handlers before use_fast_intr_handler; - knob_zero_fast_intr_handlers dist { - 0 :/ 8, - 1 :/ 2 - }; - } - - constraint fast_intr_handler_c { - if (!enable_fast_interrupt_handler) { - knob_zero_fast_intr_handlers == 1; - } - - // Nver use fast handler for exceptions (interrupt 0) - use_fast_intr_handler[0] == 0; - - knob_zero_fast_intr_handlers -> !use_fast_intr_handler; - - // VECTORED mode required for any fast interrupts - if (use_fast_intr_handler) { - mtvec_mode == VECTORED; - } - } - - `uvm_object_utils_begin(cv32e40x_instr_gen_config) - `uvm_field_enum(mtvec_mode_t, mtvec_mode, UVM_DEFAULT) - `uvm_field_enum(riscv_reg_t, dp, UVM_DEFAULT) - `uvm_field_enum(riscv_reg_t, scratch_reg, UVM_DEFAULT) - `uvm_field_int(knob_zero_fast_intr_handlers, UVM_DEFAULT) - `uvm_field_int(enable_fast_interrupt_handler, UVM_DEFAULT) - `uvm_field_int(use_fast_intr_handler, UVM_DEFAULT) - `uvm_field_int(enable_pma, UVM_DEFAULT) - `uvm_field_int(exit_on_debug_exception, UVM_DEFAULT) - `uvm_object_utils_end - - function new(string name=""); - super.new(name); - - get_bool_arg_value("+enable_fast_interrupt_handler=", enable_fast_interrupt_handler); - get_bool_arg_value("+enable_pma=", enable_pma); - get_bool_arg_value("+exit_on_debug_exception=", exit_on_debug_exception); - - if (enable_pma) begin - pma_cfg = cv32e40x_pma_cfg::type_id::create("pma_cfg"); - foreach (pma_cfg.regions[i]) begin - if (pma_cfg.regions[i].main) begin - int size; - int min_size; - - size = (pma_cfg.regions[i].word_addr_high - pma_cfg.regions[i].word_addr_low) * 4; - min_size = (size < 4096*16) ? size : (4096*16); - mem_region_override.push_back('{name:$sformatf("region_%0d", i), size_in_bytes: min_size, xwr: 3'b111}); - end - end - super.mem_region = this.mem_region_override; - end // if (enable_pma) - - endfunction : new - - function void post_randomize(); - super.post_randomize(); - - // Add in the debug pointer to reserved registers if we are using it - if (gen_debug_section) begin - reserved_regs = {tp, sp, scratch_reg, dp}; - end - - // In the debug ROM some combinations are not valid because they use the same register (dscratch0) - if (gen_debug_section) begin - if ((enable_ebreak_in_debug_rom || set_dcsr_ebreak) && - enable_debug_single_step) begin - `uvm_fatal("CVINSTGENCFG", - $sformatf("Illegal combination of debug plusargs: enable_ebreak_in_debug_rom = %0d, set_dcsr_ebreakl = %0d, enable_debug_single_step = %0d", - enable_ebreak_in_debug_rom, set_dcsr_ebreak, enable_debug_single_step)) - end - end - endfunction : post_randomize - -endclass : cv32e40x_instr_gen_config diff --git a/cv32e40x/env/corev-dv/cv32e40x_instr_gen_tb_top.sv b/cv32e40x/env/corev-dv/cv32e40x_instr_gen_tb_top.sv deleted file mode 100644 index f3469f1fb6..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_instr_gen_tb_top.sv +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2018 Google LLC - * Copyright 2020 OpenHW Group - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//----------------------------------------------------------------------------- -// Copy/Modify version of riscv-dv/tests/riscv_instr_gen_tb_top.sv to add the -// corev specific tests. -//----------------------------------------------------------------------------- -module cv32e40x_instr_gen_tb_top; - - import uvm_pkg::*; - import riscv_instr_test_pkg::*; - import corev_instr_test_pkg::*; - import cv32e40x_instr_test_pkg::*; - - initial begin - run_test(); - end - -endmodule : cv32e40x_instr_gen_tb_top diff --git a/cv32e40x/env/corev-dv/cv32e40x_instr_test_pkg.sv b/cv32e40x/env/corev-dv/cv32e40x_instr_test_pkg.sv deleted file mode 100644 index 84a50f26b5..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_instr_test_pkg.sv +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2020 OpenHW Group - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -package cv32e40x_instr_test_pkg; - - import uvm_pkg::*; - import riscv_instr_pkg::*; - import riscv_instr_test_pkg::*; - import riscv_signature_pkg::*; - import corev_instr_test_pkg::*; - - import cv32e40x_pkg::pma_region_t; - - `include "uvmt_cv32e40x_constants.sv" - `include "pma_adapted_mem_region_gen.sv" - `include "cv32e40x_ldgen.sv" - - // Instruction streams specific to CV32E40X - - // RISCV-DV class override definitions - `include "cv32e40x_pma_cfg.sv" - `include "cv32e40x_compressed_instr.sv" - `include "cv32e40x_privil_reg.sv" - `include "cv32e40x_privileged_common_seq.sv" - `include "cv32e40x_instr_gen_config.sv" - `include "cv32e40x_debug_rom_gen.sv" - `include "cv32e40x_asm_program_gen.sv" - `include "cv32e40x_instr_base_test.sv" - `include "cv32e40x_pma_instr_lib.sv" - `include "cv32e40x_fencei_instr_lib.sv" - - // Push general purpose register to the debugger stack - function automatic void push_gpr_to_debugger_stack(cv32e40x_instr_gen_config cfg_corev, - ref string instr[$]); - string store_instr = (XLEN == 32) ? "sw" : "sd"; - // Reserve space from kernel stack to save all 32 GPR except for x0 - instr.push_back($sformatf("1: addi x%0d, x%0d, -%0d", cfg_corev.dp, cfg_corev.dp, 31 * (XLEN/8))); - // Push all GPRs to kernel stack - for(int i = 1; i < 32; i++) begin - if (i == cfg_corev.dp) continue; - if (i == cfg_corev.sp) continue; - if (i == cfg_corev.tp) continue; - instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, i, i * (XLEN/8), cfg_corev.dp)); - end - endfunction : push_gpr_to_debugger_stack - - // Pop general purpose register from debugger stack - function automatic void pop_gpr_from_debugger_stack(cv32e40x_instr_gen_config cfg_corev, - ref string instr[$]); - string load_instr = (XLEN == 32) ? "lw" : "ld"; - // Pop user mode GPRs from kernel stack - for(int i = 1; i < 32; i++) begin - if (i == cfg_corev.dp) continue; - if (i == cfg_corev.sp) continue; - if (i == cfg_corev.tp) continue; - instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, i, i * (XLEN/8), cfg_corev.dp)); - end - // Restore debugger stack pointer - instr.push_back($sformatf("addi x%0d, x%0d, %0d", cfg_corev.dp, cfg_corev.dp, 31 * (XLEN/8))); - endfunction : pop_gpr_from_debugger_stack - -endpackage : cv32e40x_instr_test_pkg; diff --git a/cv32e40x/env/corev-dv/cv32e40x_pma_cfg.sv b/cv32e40x/env/corev-dv/cv32e40x_pma_cfg.sv deleted file mode 100644 index eec3524ef7..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_pma_cfg.sv +++ /dev/null @@ -1,43 +0,0 @@ -// -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may -// not use this file except in compliance with the License, or, at your option, -// the Apache License version 2.0. You may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// - -class cv32e40x_pma_cfg extends uvm_object; - pma_region_t regions[$]; - - constraint attr_comb_c { - foreach (regions[i]) { - regions[i].cacheable == 1'b1 -> regions[i].main == 1'b1; - regions[i].main == 1'b1 -> regions[i].atomic == 1'b1; - } - } - - // This variable refers to generated number of regions, not CORE_PARAM_PMA_NUM_REGIONS - int pma_num_regions = 0; - - `uvm_object_utils(cv32e40x_pma_cfg) - - function new(string name="cv32e40x_pma_cfg"); - pma_adapted_memory_regions_c pma_memory; - super.new(name); - pma_memory = new(CORE_PARAM_PMA_CFG); - foreach (pma_memory.region[i]) begin - regions.push_back(pma_memory.region[i].cfg); - pma_num_regions = pma_num_regions + 1; - end - endfunction : new -endclass : cv32e40x_pma_cfg diff --git a/cv32e40x/env/corev-dv/cv32e40x_pma_instr_lib.sv b/cv32e40x/env/corev-dv/cv32e40x_pma_instr_lib.sv deleted file mode 100644 index d1df01038e..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_pma_instr_lib.sv +++ /dev/null @@ -1,1030 +0,0 @@ - /* - * Copyright 2020 OpenHW Group - * Copyright 2020 Silicon Labs, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -// ############################################################################# -// -// Section 1: Load/Store test streams -// -// ############################################################################# - -// ----------------------------------------------------------------------------- -// -// corev_load_store_pma_base_stream -// -// Directed test to generate random load instruction to random pma_region -// ----------------------------------------------------------------------------- -virtual class corev_load_store_pma_base_stream extends riscv_load_store_rand_instr_stream; - cv32e40x_pma_cfg pma_cfg; - rand int unsigned load_cnt; - rand int unsigned store_cnt; - rand riscv_reg_t protected_reg[]; - rand riscv_reg_t addr_reg; - rand bit [31:0] addr; - rand bit use_compressed; - rand int index; - rand bit region_access_only; - rand bit non_region_access_only; - - constraint valid_addr_reg_c { - use_compressed -> (addr_reg inside {[S0:A5]}); - !use_compressed -> (addr_reg inside {[T0:T6]}); - } - - constraint valid_index_c { - index inside {[0 : pma_cfg.pma_num_regions - 1]}; - } - - constraint non_region_access_only_c { - non_region_access_only == 1 -> region_access_only == 0; - } - - constraint only_valid_region_c { - region_access_only == 1; - non_region_access_only == 0; - } - - constraint valid_region_c { - if (region_access_only == 1) { - addr inside {[pma_cfg.regions[index].word_addr_low<<2:pma_cfg.regions[index].word_addr_high<<2]}; - } - if (non_region_access_only == 1) { - foreach (pma_cfg.regions[i]) { - !(addr inside {[pma_cfg.regions[i].word_addr_low<<2:pma_cfg.regions[i].word_addr_high<<2]}); - } - } - } - - constraint load_cnt_c { - load_cnt inside { [ 3:10 ] }; - store_cnt inside { [ 3:10 ] }; - } - - function new(string name = ""); - super.new(name); - pma_cfg = cv32e40x_pma_cfg::type_id::create("pma_cfg"); - endfunction : new - - -endclass : corev_load_store_pma_base_stream - -// ----------------------------------------------------------------------------- -// -// corev_load_pma_instr_stream -// -// FIXME silabs-hfegran: This stream appears to generate an extra load store sequence -// ----------------------------------------------------------------------------- -class corev_load_pma_instr_stream extends corev_load_store_pma_base_stream; - rand riscv_reg_t dest_reg; - - constraint valid_rd_c { - use_compressed -> (dest_reg inside {[S0:A5]}); - !use_compressed -> (dest_reg inside {[T0:T6]}); - dest_reg != addr_reg; - } - - `uvm_object_utils(corev_load_pma_instr_stream) - - function new(string name = ""); - super.new(name); - endfunction : new - - virtual function void add_mixed_instr(int instr_cnt); - riscv_reg_t all_regs; - riscv_reg_t nonprotected_regs[$]; - - do begin - if ((all_regs.name != addr_reg.name) && (all_regs >= T0)) begin - nonprotected_regs.push_back(all_regs); - end - all_regs = all_regs.next; - end while (all_regs != all_regs.first); - super.avail_regs = nonprotected_regs; - - add_pma_load(load_cnt); - super.add_mixed_instr(instr_cnt); - endfunction : add_mixed_instr - - virtual function void add_pma_load(int unsigned cnt); - riscv_instr instr; - - instr = riscv_instr::get_rand_instr(.include_instr({LUI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LUI; - rd == addr_reg; - imm == addr[31:12]; - , "Failed randomizing LUI" - ) - instr.comment = $sformatf("start corev_load_pma_instr (imm: %0x, region: %0d)", instr.imm, index); - insert_instr(instr, 0); - - for (int i = 1; i <= cnt; i++) begin - instr = riscv_instr::get_rand_instr(.include_instr({LB, LH, LW, LBU, LHU})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name inside { LB, LH, LW, LBU, LHU }; - rd == dest_reg; - rs1 == addr_reg; - if (region_access_only == 1) { - (addr + imm) inside { [ pma_cfg.regions[index].word_addr_low<<2:pma_cfg.regions[index].word_addr_high<<2 ] } - }; - , $sformatf("Failed randomizing %0s", instr.instr_name) - ) - instr.comment = $sformatf("corev-dv: corev_load_pma_instr_stream: addr: %0x, imm: %0x", this.addr, instr.imm); - insert_instr(instr, i); - end - endfunction : add_pma_load - - function void post_randomize(); - // Cannot call super.randomize() because the parent class will add more instructions - // that can corrupt this stream, this is a replication of the base class post_randomze() - // This needs a better solution, file Issue on this - add_mixed_instr(num_mixed_instr); - - foreach(instr_list[i]) begin - instr_list[i].has_label = 1'b0; - instr_list[i].atomic = 1'b1; - end - instr_list[0].comment = $sformatf("Start %0s", get_name()); - instr_list[$].comment = $sformatf("End %0s", get_name()); - if(label!= "") begin - instr_list[0].label = label; - instr_list[0].has_label = 1'b1; - end - - endfunction : post_randomize - -endclass : corev_load_pma_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_store_pma_instr_stream -// -// Multiple writes to same address range -// -// ----------------------------------------------------------------------------- -class corev_store_pma_instr_stream extends corev_load_store_pma_base_stream; - - `uvm_object_utils(corev_store_pma_instr_stream) - - function new(string name = ""); - super.new(name); - endfunction : new - - virtual function void add_mixed_instr(int instr_cnt); - riscv_reg_t all_regs; - riscv_reg_t nonprotected_regs[$]; - - do begin - if ((all_regs.name != addr_reg.name) && (all_regs >= T0)) begin - nonprotected_regs.push_back(all_regs); - end - all_regs = all_regs.next; - end while (all_regs != all_regs.first); - super.avail_regs = nonprotected_regs; - - add_pma_store(store_cnt); - super.add_mixed_instr(instr_cnt); - endfunction : add_mixed_instr - - virtual function void add_pma_store(int unsigned cnt); - riscv_instr instr; - instr = riscv_instr::get_rand_instr(.include_instr({LUI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LUI; - rd == addr_reg; - imm == addr[31:12]; - , "Failed randomizing LUI" - ) - instr.comment = $sformatf("start corev_store_pma_instr (Reg: %0s, Imm: %0x)", instr.rd.name, instr.imm); - insert_instr(instr, 0); - - for (int i = 1; i <= cnt; i++) begin - instr = riscv_instr::get_rand_instr(.include_instr({SB, SH, SW})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name inside {SB, SH, SW}; - rs1 == addr_reg; - (addr + imm) inside { [pma_cfg.regions[index].word_addr_low<<2:pma_cfg.regions[index].word_addr_high<<2 ] }; - , $sformatf("Failed randomizing %0s", instr.instr_name) - ) - instr.comment = $sformatf("corev-dv: corev_store_pma_instr_stream: addr: %0x, imm: %0x", this.addr, instr.imm); - insert_instr(instr, i); - end - endfunction : add_pma_store - -endclass : corev_store_pma_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_load_store_pma_mixed_instr_stream -// -// Mixed reads and writes from same address range -// -// ----------------------------------------------------------------------------- -class corev_load_store_pma_mixed_instr_stream extends corev_load_store_pma_base_stream; - - rand riscv_reg_t dest_reg; - rand int cnt; - - constraint valid_cnt_c { - cnt inside {[5:30]}; - } - - constraint valid_rd_c { - use_compressed -> (dest_reg inside {[S0:A5]}); - !use_compressed -> (dest_reg inside {[T0:T6]}); - dest_reg != addr_reg; - } - - `uvm_object_utils(corev_load_store_pma_mixed_instr_stream) - - function new(string name = ""); - super.new(name); - endfunction : new - - virtual function void add_mixed_instr(int instr_cnt); - riscv_reg_t all_regs; - riscv_reg_t nonprotected_regs[$]; - - do begin - if ((all_regs.name != addr_reg.name) && (all_regs >= T0)) begin - nonprotected_regs.push_back(all_regs); - end - all_regs = all_regs.next; - end while (all_regs != all_regs.first); - super.avail_regs = nonprotected_regs; - - super.add_mixed_instr(instr_cnt); - - endfunction : add_mixed_instr - - virtual function void add_pma_load_store_mixed(int unsigned cnt); - riscv_instr instr; - instr = riscv_instr::get_rand_instr(.include_instr({LUI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LUI; - rd == addr_reg; - imm == addr[31:12]; - , "Failed randomizing LUI" - ) - instr.comment = $sformatf("start corev_load_store_pma_mixed_instr_stream"); - insert_instr(instr, 0); - - for (int i = 1; i <= cnt; i++) begin - instr = riscv_instr::get_rand_instr(.include_instr({ SB, SH, SW, LB, LH, LW, LBU, LHU })); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name inside { SB, SH, SW, LB, LH, LW, LBU, LHU }; - instr_name inside { LB, LH, LW, LBU, LHU } -> rd == dest_reg; - rs1 == addr_reg; - if (region_access_only) { - (addr + imm) inside { [pma_cfg.regions[index].word_addr_low<<2:pma_cfg.regions[index].word_addr_high<<2] }; - } - , $sformatf("Failed randomizing %0s", instr.instr_name) - ) - instr.comment = $sformatf("corev-dv: corev_load_store_pma_mixed_instr_stream: addr: %0x, imm: %0x", this.addr, instr.imm);; - insert_instr(instr, i); - end - endfunction : add_pma_load_store_mixed - - - function void post_randomize(); - // Cannot call super.randomize() because the parent class will add more instructions - // that can corrupt this stream, this is a replication of the base class post_randomze() - // This needs a better solution, file Issue on this - - randomize_offset(); - // rs1 cannot be modified by other instructions - if(!(rs1_reg inside {reserved_rd})) begin - reserved_rd = {reserved_rd, rs1_reg}; - end - add_pma_load_store_mixed(cnt); - add_mixed_instr(num_mixed_instr); - add_rs1_init_la_instr(rs1_reg, data_page_id, base); - - foreach(instr_list[i]) begin - instr_list[i].has_label = 1'b0; - instr_list[i].atomic = 1'b1; - end - instr_list[0].comment = $sformatf("Start %0s", get_name()); - instr_list[$].comment = $sformatf("End %0s", get_name()); - if(label!= "") begin - instr_list[0].label = label; - instr_list[0].has_label = 1'b1; - end - - endfunction - -endclass : corev_load_store_pma_mixed_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_load_store_pma_misaligned_instr_stream -// -// ----------------------------------------------------------------------------- -class corev_load_store_pma_misaligned_instr_stream extends corev_load_store_pma_mixed_instr_stream; - - `uvm_object_utils(corev_load_store_pma_misaligned_instr_stream) - - constraint only_valid_region_c { - } - - function new(string name = ""); - super.new(name); - endfunction : new - - virtual function void add_pma_load_store_mixed(int unsigned cnt); - riscv_instr instr; - instr = riscv_instr::get_rand_instr(.include_instr({LUI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LUI; - rd == addr_reg; - imm == addr[31:12]; - , "Failed randomizing LUI" - ) - instr.comment = $sformatf("start %m"); - insert_instr(instr, 0); - - for (int i = 1; i <= cnt; i++) begin - instr = riscv_instr::get_rand_instr(.include_instr({ SH, SW, LH, LW, LHU })); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name inside { SH, SW, LH, LW, LHU }; - instr_name inside { LH, LW, LHU } -> rd == dest_reg; - rs1 == addr_reg; - if (region_access_only) { - (addr + imm) inside { [pma_cfg.regions[index].word_addr_low<<2:pma_cfg.regions[index].word_addr_high<<2] } - }; - (addr + imm % 4) != 0; - , $sformatf("Failed randomizing %0s", instr.instr_name) - ) - instr.comment = $sformatf("corev-dv: corev_load_store_pma_misaligned_instr_stream: addr: %0x, imm: %0x", this.addr, instr.imm);; - insert_instr(instr, i); - end - endfunction : add_pma_load_store_mixed - - function void post_randomize(); - // Cannot call super.randomize() because the parent class will add more instructions - // that can corrupt this stream, this is a replication of the base class post_randomze() - // This needs a better solution, file Issue on this - - randomize_offset(); - // rs1 cannot be modified by other instructions - if(!(rs1_reg inside {reserved_rd})) begin - reserved_rd = {reserved_rd, rs1_reg}; - end - add_pma_load_store_mixed(cnt); - add_mixed_instr(num_mixed_instr); - add_rs1_init_la_instr(rs1_reg, data_page_id, base); - - foreach(instr_list[i]) begin - instr_list[i].has_label = 1'b0; - instr_list[i].atomic = 1'b1; - end - instr_list[0].comment = $sformatf("Start %0s", get_name()); - instr_list[$].comment = $sformatf("End %0s", get_name()); - if(label!= "") begin - instr_list[0].label = label; - instr_list[0].has_label = 1'b1; - end - endfunction - -endclass : corev_load_store_pma_misaligned_instr_stream - -// ############################################################################# -// -// Section 2: Jump/Branch test streams -// -// ############################################################################# - -// ----------------------------------------------------------------------------- -// -// corev_jalr_pma_instr -// -// Jump to random address in random defined memory region -// -// ----------------------------------------------------------------------------- -class corev_jalr_pma_instr extends riscv_jal_instr; - cv32e40x_pma_cfg pma_cfg; - rand riscv_reg_t fwd_addr_reg; - rand bit use_compressed; - rand bit [31:0] fwd_addr; - rand int index; - static int jmp_label_idx; - string jmp_label; - - int ram_region; - - constraint valid_reg_c { - !(fwd_addr_reg inside {cfg.reserved_regs}); - fwd_addr_reg != cfg.gpr[2]; - fwd_addr_reg != cfg.gpr[3]; - fwd_addr_reg != cfg.sp; - fwd_addr_reg != cfg.tp; - // Always use compressed instruction targetable register - use_compressed -> (fwd_addr_reg inside {[S0:A5]}); - !use_compressed -> (fwd_addr_reg inside {[T0:T6]}); - } - - // Don't jump to addresses with executable code (potential infinite loop problems) - constraint valid_index_c { - index inside {[0 : pma_cfg.pma_num_regions - 1]}; - index != ram_region; - } - - constraint valid_region_c { - fwd_addr inside {[(pma_cfg.regions[index].word_addr_low)<<2:pma_cfg.regions[index].word_addr_high<<2]}; - - } - - constraint fwd_addr_max_c { - // OVPSim cannot fetch instructions at end of its memory - fwd_addr <= 32'hffff_fff0; - } - - constraint instr_c { - num_of_jump_instr == 0; - } - - `uvm_object_utils(corev_jalr_pma_instr) - - function new(string name = ""); - super.new(name); - pma_cfg = cv32e40x_pma_cfg::type_id::create("pma_cfg"); - // find region containing RAM - foreach (pma_cfg.regions[i]) begin - if (pma_cfg.regions[i].main == 1) begin - ram_region = i; - break; - end - end - endfunction : new - - virtual function void add_load_pma_main_addr_instr(); - riscv_instr instr; - riscv_pseudo_instr la_instr; - riscv_instr_name_t store_instr = (XLEN == 32) ? SW : SD; - riscv_instr_name_t load_instr = (XLEN == 32) ? LW : LD; - automatic bit [11:0] fwd_addr_modif = { fwd_addr[11], 13'h1000 + signed'(fwd_addr[11:0]) }; - - // Create recovery mechanism for invalid instruction - // at destination, we need to be able to resusme - // execution at jump origin after potential traps - - // Make space on stack for signatures and backup - instr = riscv_instr::get_rand_instr(.include_instr({ADDI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == ADDI; - rd == cfg.sp; - rs1 == cfg.sp; - imm == -4*(XLEN/8); - , "Failed randomizing ADDI" - ) - insert_instr(instr, 0); - - // Save Original T3 and T4 on stack - instr = riscv_instr::get_rand_instr(.include_instr({store_instr})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == store_instr; - rs1 == cfg.sp; - rs2 == cfg.gpr[2]; - imm == 3*(XLEN/8); - , {"Failed randomizing ", store_instr.name } - ) - insert_instr(instr, 1); - - instr = riscv_instr::get_rand_instr(.include_instr({store_instr})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == store_instr; - rs1 == cfg.sp; - rs2 == cfg.gpr[3]; - imm == 2*(XLEN/8); - , {"Failed randomizing ", store_instr.name } - ) - insert_instr(instr, 2); - - jmp_label = $sformatf("jmp_mret_loc_%0d", jmp_label_idx++); - // Store future PC (at JALR instrution) - la_instr = riscv_pseudo_instr::type_id::create("LA"); - `DV_CHECK_RANDOMIZE_WITH_FATAL(la_instr, - pseudo_instr_name == LA; - rd == cfg.gpr[2]; - , "Failed randomizing LA" - ) - la_instr.imm_str = jmp_label; - la_instr.comment = $sformatf("STORE FUTURE PC T3"); - insert_instr(la_instr, 3); - - // Store future PC (at JALR instrution) - instr = riscv_instr::get_rand_instr(.include_instr({ADDI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == ADDI; - rd == cfg.gpr[3]; - rs1 == cfg.gpr[2]; - imm == 0; - , "Failed randomizing ADDI" - ) - instr.comment = $sformatf("STORE FUTURE PC T4"); - insert_instr(instr, 4); - - // Save values on stack - instr = riscv_instr::get_rand_instr(.include_instr({store_instr})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == store_instr; - rs2 == cfg.gpr[2]; - rs1 == cfg.sp; - imm == 0*(XLEN/8); - , {"Failed randomizing ", store_instr.name } - ) - insert_instr(instr, 5); - - instr = riscv_instr::get_rand_instr(.include_instr({store_instr})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == store_instr; - rs2 == cfg.gpr[3]; - rs1 == cfg.sp; - imm == 1*(XLEN/8); - , {"Failed randomizing ", store_instr.name } - ) - insert_instr(instr, 6); - - // Prepare jump - instr = riscv_instr::get_rand_instr(.include_instr({LUI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LUI; - rd == fwd_addr_reg; - fwd_addr[11] -> imm == (fwd_addr[31:12] + 1); - !fwd_addr[11] -> imm == fwd_addr[31:12]; - , "Failed randomizing LUI" - ) - instr.comment = $sformatf("start corev_jalr_pma_instr (imm: %0x, region: %0d)", instr.imm, index); - insert_instr(instr, 7); - - instr = riscv_instr::get_rand_instr(.include_instr({JALR})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == JALR; - rs1 == fwd_addr_reg; - // don't overwrite protected regs - rd != cfg.sp; - rd != cfg.tp; - rd != cfg.gpr[2]; - rd != cfg.gpr[3]; - fwd_addr[11] -> imm == fwd_addr_modif; - !fwd_addr[11] -> imm == fwd_addr[11:0]; - , "Failed randomizing JALR" - ) - insert_instr(instr, 8); - - // Restore t4 and t3 - instr = riscv_instr::get_rand_instr(.include_instr({load_instr})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == load_instr; - rd == cfg.gpr[3]; - rs1 == cfg.sp; - imm == 2*(XLEN/8); - , "Failed randomizing ADDI" - ) - instr.atomic = 1; - instr.label = jmp_label; - insert_instr(instr, 9); - - instr = riscv_instr::get_rand_instr(.include_instr({load_instr})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == load_instr; - rd == cfg.gpr[2]; - rs1 == cfg.sp; - imm == 3*(XLEN/8); - , "Failed randomizing ADDI" - ) - insert_instr(instr, 10); - - // Cleanup stack - instr = riscv_instr::get_rand_instr(.include_instr({ADDI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == ADDI; - rd == cfg.sp; - rs1 == cfg.sp; - imm == 4*(XLEN/8); - , "Failed randomizing ADDI" - ) - insert_instr(instr, 11); - - endfunction : add_load_pma_main_addr_instr - - function void post_randomize(); - reserved_rd = { reserved_rd, cfg.gpr[2], cfg.gpr[3], cfg.tp, cfg.sp }; - add_load_pma_main_addr_instr(); - foreach (instr_list[i]) begin - instr_list[i].atomic = 1; - if (instr_list[i].label == "") begin - instr_list[i].label = $sformatf("%0d", i); - end - end - endfunction : post_randomize -endclass : corev_jalr_pma_instr - -// ----------------------------------------------------------------------------- -// -// corev_jalr_pma_cacheable_instr -// -// Absolute jump to pma-region defined as cacheable -// -// ----------------------------------------------------------------------------- -class corev_jalr_pma_cacheable_instr extends corev_jalr_pma_instr; - constraint valid_index_in_cacheable_region_c { - pma_cfg.regions[index].cacheable == 1'b1; - } - - `uvm_object_utils(corev_jalr_pma_cacheable_instr) - function new(string name = ""); - super.new(name); - endfunction : new - - function void post_randomize(); - super.post_randomize(); - for (int i = 0; i < 2; i++) begin - if (instr_list[i].instr_name == LUI) begin - instr_list[i].comment = $sformatf("corev_jalr_pma_cacheable_instr: region: %0d", index); - end - end - endfunction : post_randomize -endclass : corev_jalr_pma_cacheable_instr - -// ----------------------------------------------------------------------------- -// -// corev_jalr_pma_bufferable_instr -// -// Absolute jump to pma-region defined as bufferable -// -// ----------------------------------------------------------------------------- -class corev_jalr_pma_bufferable_instr extends corev_jalr_pma_instr; - constraint valid_index_in_bufferable_region_c { - pma_cfg.regions[index].bufferable == 1'b1; - } - - `uvm_object_utils(corev_jalr_pma_bufferable_instr) - - function new(string name = ""); - super.new(name); - endfunction : new - - function void post_randomize(); - super.post_randomize(); - for (int i = 0; i < 2; i++) begin - if (instr_list[i].instr_name == LUI) begin - instr_list[i].comment = $sformatf("corev_jalr_pma_bufferable_instr: region: %0d", index); - end - end - endfunction : post_randomize -endclass : corev_jalr_pma_bufferable_instr - -// ----------------------------------------------------------------------------- -// -// corev_jalr_pma_undefined_region_instr -// -// Absolute jump to memory area not covered by any pma-region -// -// ----------------------------------------------------------------------------- -class corev_jalr_pma_undefined_region_instr extends corev_jalr_pma_instr; - - constraint valid_region_c { - foreach (pma_cfg.regions[i]) { - !(fwd_addr inside {[pma_cfg.regions[i].word_addr_low<<2:pma_cfg.regions[i].word_addr_high<<2]}); - } - } - - `uvm_object_utils(corev_jalr_pma_undefined_region_instr) - - function new(string name =""); - super.new(name); - endfunction : new - - function void post_randomize(); - super.post_randomize(); - for (int i = 0; i < 2; i++) begin - if (instr_list[i].instr_name == LUI) begin - instr_list[i].comment = $sformatf("corev_jalr_pma_undefined_region_instr: address: %0x", fwd_addr); - end - end - endfunction : post_randomize -endclass : corev_jalr_pma_undefined_region_instr - -// ############################################################################# -// -// Section 3: Atomic operations test streams -// -// Note : amo-tests require A-extension enabled in config -// -// ############################################################################# - -// ----------------------------------------------------------------------------- -// -// corev_pma_atomic_instr_stream_base -// -// ----------------------------------------------------------------------------- -class corev_pma_atomic_instr_stream_base extends riscv_directed_instr_stream; - cv32e40x_pma_cfg pma_cfg; - mem_region_t data_page[$]; - int max_data_page_id; - rand riscv_reg_t fwd_addr_reg[]; - rand bit [31:0] fwd_addr; - rand int num_mixed_instr; - rand int num_amo_instr; - rand int num_fwd_addr_reg; - rand int index; - - constraint num_fwd_addr_reg_c { - num_fwd_addr_reg == 1; - } - - constraint fwd_addr_reg_c { - solve num_fwd_addr_reg before fwd_addr_reg; - fwd_addr_reg.size() == num_fwd_addr_reg; - foreach (fwd_addr_reg[i]) { - !(fwd_addr_reg[i] inside {cfg.reserved_regs, reserved_rd, ZERO}); - } - unique {fwd_addr_reg}; - } - - // Inside region constraint - override if need to hit undefined regions - constraint valid_region_c { - fwd_addr inside {[pma_cfg.regions[index].word_addr_low<<2:pma_cfg.regions[index].word_addr_high<<2]}; - } - - constraint valid_index_c { - index inside {[0 : pma_cfg.pma_num_regions - 1]}; - } - - `uvm_object_utils(corev_pma_atomic_instr_stream_base) - - function new(string name = ""); - super.new(name); - pma_cfg = cv32e40x_pma_cfg::type_id::create("pma_cfg"); - endfunction : new - - function void pre_randomize(); - data_page = cfg.mem_region; - max_data_page_id = data_page.size(); - super.pre_randomize(); - endfunction : pre_randomize - - function void post_randomize(); - gen_amo_instr(); - reserved_rd = { reserved_rd, fwd_addr_reg }; - add_mixed_instr(num_mixed_instr); - super.post_randomize(); - endfunction : post_randomize - - // Mix in some other instructions - virtual function void add_mixed_instr(int instr_cnt); - riscv_instr instr; - setup_allowed_instr(1, 1); - for(int i = 0; i < instr_cnt; i ++) begin - instr = riscv_instr::type_id::create("instr"); - randomize_instr(instr); - insert_instr(instr); - end - endfunction - - virtual function void load_target_addr(); - riscv_instr instr; - instr = riscv_instr::get_rand_instr(.include_instr({LUI})); - foreach (fwd_addr_reg[i]) begin - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == LUI; - rd == fwd_addr_reg[i]; - fwd_addr[11] -> imm == (fwd_addr[31:12] + 1); - !fwd_addr[11] -> imm == fwd_addr[31:12]; - , "Failed randomizing LUI" - ) - instr.comment = $sformatf("Loading upper bits of addr: %0x (imm: %0x, region: %0d)", fwd_addr, instr.imm, index); - insert_instr(instr, 0); - - instr = riscv_instr::get_rand_instr(.include_instr({ADDI})); - `DV_CHECK_RANDOMIZE_WITH_FATAL(instr, - instr_name == ADDI; - rs1 == fwd_addr_reg[i]; - rd == fwd_addr_reg[i]; - imm == fwd_addr[11:0]; - , "Failed randomizing ADDI" - ) - instr.comment = $sformatf("end load_target_addr: %0x, %0s", fwd_addr, fwd_addr_reg[i].name()); - insert_instr(instr, 1); - end - endfunction : load_target_addr - - virtual function void gen_amo_instr(); - endfunction : gen_amo_instr - -endclass : corev_pma_atomic_instr_stream_base - -// ----------------------------------------------------------------------------- -// -// corev_pma_atomic_random_instr_stream -// -// ----------------------------------------------------------------------------- -class corev_pma_atomic_random_instr_stream extends corev_pma_atomic_instr_stream_base; - riscv_instr lr_instr; - riscv_instr sc_instr; - - constraint legal_c { - num_amo_instr == 1; - num_mixed_instr inside {[0:14]}; - } - - `uvm_object_utils(corev_pma_atomic_random_instr_stream) - - function new(string name = ""); - super.new(name); - endfunction : new - - virtual function void gen_amo_instr(); - riscv_instr_name_t allowed_lr_instr[]; - riscv_instr_name_t allowed_sc_instr[]; - allowed_lr_instr = {LR_W}; - allowed_sc_instr = {SC_W}; - foreach (fwd_addr_reg[i]) begin - lr_instr = riscv_instr::get_rand_instr(.include_instr({ allowed_lr_instr })); - sc_instr = riscv_instr::get_rand_instr(.include_instr({ allowed_sc_instr })); - `DV_CHECK_RANDOMIZE_WITH_FATAL(lr_instr, - rs1 == fwd_addr_reg[i]; - if (reserved_rd.size() > 0) { - !(rd inside { reserved_rd }); - } - if (cfg.reserved_regs.size() > 0) { - !(rd inside { cfg.reserved_regs }); - } - rd != fwd_addr_reg[i]; - ) - lr_instr.comment = "LR"; - `DV_CHECK_RANDOMIZE_WITH_FATAL(sc_instr, - rs1 == fwd_addr_reg[i]; - if (reserved_rd.size() > 0) { - !(rd inside { reserved_rd }); - } - if (cfg.reserved_regs.size() > 0) { - !(rd inside { cfg.reserved_regs }); - } - rd != fwd_addr_reg[i]; - ) - sc_instr.comment = "SC"; - instr_list.push_back(lr_instr); - instr_list.push_back(sc_instr); - end - endfunction : gen_amo_instr - - // section 8.3 Eventual Success of Store-Conditional Instructions - // An LR/SC sequence begins with an LR instruction and ends with an SC instruction. - // The dynamic code executed between the LR and SC instructions can only contain - // instructions from the base “I” instruction set, excluding loads, stores, backward - // jumps, taken backward branches, JALR, FENCE, and SYSTEM instructions. If the “C” - // extension is supported, then compressed forms of the aforementioned “I” instructions - // are also permitted. - virtual function void add_mixed_instr(int instr_cnt); - riscv_instr instr; - int i; - setup_allowed_instr(.no_branch(1), .no_load_store(1)); - while (i < instr_cnt) begin - instr = riscv_instr::type_id::create("instr"); - randomize_instr(instr, .include_group({RV32I, RV32C})); - if (!(instr.category inside {SYNCH, SYSTEM})) begin - insert_instr(instr); - i++; - end - end - endfunction - - function void pre_randomize(); - super.pre_randomize(); - endfunction : pre_randomize - - function void post_randomize(); - load_target_addr(); - super.post_randomize(); - endfunction : post_randomize - -endclass : corev_pma_atomic_random_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_pma_atomic_amo_instr_stream -// -// ----------------------------------------------------------------------------- -class corev_pma_atomic_amo_instr_stream extends corev_pma_atomic_instr_stream_base; - riscv_instr amo_instr[]; - - constraint reasonable_c { - solve num_amo_instr before num_mixed_instr; - num_amo_instr inside {[1 : 10]}; - num_mixed_instr inside {[0 : num_amo_instr]}; - } - - constraint num_fwd_addr_reg_c { - solve num_amo_instr before num_fwd_addr_reg; - num_fwd_addr_reg inside {[1 : num_amo_instr]}; - num_fwd_addr_reg < 5; - } - - `uvm_object_utils(corev_pma_atomic_amo_instr_stream) - `uvm_object_new - - virtual function void gen_amo_instr(); - amo_instr = new[num_amo_instr]; - foreach (amo_instr[i]) begin - amo_instr[i] = riscv_instr::get_rand_instr(.include_category({ AMO })); - amo_instr[i].print(); - `DV_CHECK_RANDOMIZE_WITH_FATAL(amo_instr[i], - //rs1 == fwd_addr_reg[i]; - if (reserved_rd.size() > 0) { - !(rd inside {reserved_rd}); - } - if (cfg.reserved_regs.size() > 0) { - !(rd inside {cfg.reserved_regs}); - } - rs1 inside { fwd_addr_reg }; - !(rd inside { fwd_addr_reg }); - , $sformatf("rs1: %0d, fwd_addr_reg[i]: %0d, i: %0d", amo_instr[i].rs1, fwd_addr_reg[i], i) - ) - instr_list.push_front(amo_instr[i]); - end // foreach (amo_instr[i]) - endfunction : gen_amo_instr - -endclass : corev_pma_atomic_amo_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_pma_atomic_aligned_instr_stream -// -// ----------------------------------------------------------------------------- -class corev_pma_atomic_aligned_instr_stream extends corev_pma_atomic_random_instr_stream; - - constraint aligned_addr_c { - (fwd_addr % 4) == 0; - } - - `uvm_object_utils(corev_pma_atomic_aligned_instr_stream) - `uvm_object_new - -endclass : corev_pma_atomic_aligned_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_pma_atomic_misaligned_instr_stream -// -// ----------------------------------------------------------------------------- -class corev_pma_atomic_misaligned_instr_stream extends corev_pma_atomic_random_instr_stream; - - constraint aligned_addr_c { - (fwd_addr % 4) != 0; - } - - `uvm_object_utils(corev_pma_atomic_misaligned_instr_stream) - `uvm_object_new - -endclass : corev_pma_atomic_misaligned_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_pma_atomic_allowed_instr_stream -// -// ----------------------------------------------------------------------------- -class corev_pma_atomic_allowed_instr_stream extends corev_pma_atomic_random_instr_stream; - - constraint atomic_allowed_c { - pma_cfg.regions[index].atomic == 1'b1; - } - - `uvm_object_utils(corev_pma_atomic_allowed_instr_stream) - `uvm_object_new - -endclass : corev_pma_atomic_allowed_instr_stream - -// ----------------------------------------------------------------------------- -// -// corev_pma_atomic_disallowed_instr_stream -// -// ----------------------------------------------------------------------------- -class corev_pma_atomic_disallowed_instr_stream extends corev_pma_atomic_random_instr_stream; - - constraint atomic_disallowed_c { - pma_cfg.regions[index].atomic == 1'b0; - } - - `uvm_object_utils(corev_pma_atomic_disallowed_instr_stream) - `uvm_object_new - -endclass : corev_pma_atomic_disallowed_instr_stream - - - diff --git a/cv32e40x/env/corev-dv/cv32e40x_privil_reg.sv b/cv32e40x/env/corev-dv/cv32e40x_privil_reg.sv deleted file mode 100644 index 002ea7f603..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_privil_reg.sv +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2018 Google LLC - * Copyright 2020 OpenHW Group - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//------------------------------------------------------------------------------ -// CORE-V privileged register class -// Extends privilege registers for CORE-V core platform extensions -// -// The base test Uses the factory to replace riscv_privil_reg with corev_privil_reg -//------------------------------------------------------------------------------ - -class cv32e40x_privil_reg extends riscv_privil_reg; - - `uvm_object_utils(cv32e40x_privil_reg); - - function new(string name=""); - super.new(name); - endfunction - - // Add fields in privileged registers - function void init_reg(REG_T reg_name); - super.init_reg(reg_name); - - case(reg_name) inside - MSTATUS: begin - fld.delete(); - add_field("WPRI0", 3, WPRI); - add_field("MIE", 1, WARL); - add_field("WPRI1", 3, WPRI); - add_field("MPIE", 1, WARL); - add_field("WPRI2", 3, WPRI); - add_field("MPP", 2, WARL); - add_field("WPRI3", 3, WPRI); - add_field("MPRV", 2, WARL); - add_field("WPRI4", 14, WPRI); - end - // Machine interrupt-enable register - MIE: begin - fld.delete(); - - add_field("WPRI0", 3, WARL); - add_field("MSIE", 1, WARL); - add_field("WPRI1", 3, WPRI); - add_field("MTIE", 1, WARL); - add_field("WPRI2", 3, WPRI); - add_field("MEIE", 1, WARL); - add_field("WPRI3", 4, WPRI); - for (int i = 0; i < 16; i++) begin - add_field($sformatf("FIE%0d", i), 1, WARL); - end - end - MIP: begin - fld.delete(); - - add_field("WPRI0", 3, WPRI); - add_field("MSIP", 1, WARL); - add_field("WPRI1", 3, WPRI); - add_field("MTIP", 1, WARL); - add_field("WPRI2", 3, WPRI); - add_field("MEIP", 1, WARL); - add_field("WPRI3", 4, WPRI); - for (int i = 0; i < 16; i++) begin - add_field($sformatf("FIP%0d", i), 1, WARL); - end - end - endcase - endfunction : init_reg - -endclass : cv32e40x_privil_reg diff --git a/cv32e40x/env/corev-dv/cv32e40x_privileged_common_seq.sv b/cv32e40x/env/corev-dv/cv32e40x_privileged_common_seq.sv deleted file mode 100644 index 0bdc5d7bde..0000000000 --- a/cv32e40x/env/corev-dv/cv32e40x_privileged_common_seq.sv +++ /dev/null @@ -1,44 +0,0 @@ -class cv32e40x_privileged_common_seq extends riscv_privileged_common_seq; - - `uvm_object_utils(cv32e40x_privileged_common_seq) - - function new(string name = "", uvm_component parent = null); - super.new(name); - endfunction : new - - virtual function void setup_mmode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]); - mstatus = riscv_privil_reg::type_id::create("mstatus"); - mstatus.init_reg(MSTATUS); - if (cfg.randomize_csr) begin - mstatus.set_val(cfg.mstatus); - end - mstatus.set_field("MPRV", cfg.mstatus_mprv); - // Set the previous privileged mode as the target mode - mstatus.set_field("MPP", mode); - // Enable interrupt - mstatus.set_field("MPIE", cfg.enable_interrupt); - // MIE is set when returning with mret, avoids trapping before returning - mstatus.set_field("MIE", 0); - // Zero out the remaining fields to avoid issues with unimplemented features - mstatus.set_field("WPRI0", 0); - mstatus.set_field("WPRI1", 0); - mstatus.set_field("WPRI2", 0); - mstatus.set_field("WPRI3", 0); - mstatus.set_field("WPRI4", 0); - - `uvm_info(`gfn, $sformatf("mstatus_val: 0x%0x", mstatus.get_val()), UVM_LOW) - regs.push_back(mstatus); - // Enable external and timer interrupt - if (MIE inside {implemented_csr}) begin - mie = riscv_privil_reg::type_id::create("mie"); - mie.init_reg(MIE); - if (cfg.randomize_csr) begin - mie.set_val(cfg.mie); - end - mie.set_field("MEIE", cfg.enable_interrupt); - mie.set_field("MSIE", cfg.enable_interrupt); - mie.set_field("MTIE", cfg.enable_interrupt & cfg.enable_timer_irq); - regs.push_back(mie); - end - endfunction -endclass : cv32e40x_privileged_common_seq diff --git a/cv32e40x/env/corev-dv/instr_lib/.gitkeep b/cv32e40x/env/corev-dv/instr_lib/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/cv32e40x/env/corev-dv/ldgen/cv32e40x_ldgen.sv b/cv32e40x/env/corev-dv/ldgen/cv32e40x_ldgen.sv deleted file mode 100644 index dcd35f52fb..0000000000 --- a/cv32e40x/env/corev-dv/ldgen/cv32e40x_ldgen.sv +++ /dev/null @@ -1,500 +0,0 @@ -/* - * Copyright 2021 Silicon Labs, Inc. - * - * This file, and derivatives thereof are licensed under the - * Solderpad License, Version 2.0 (the "License"); - * Use of this file means you agree to the terms and conditions - * of the license and are in full compliance with the License. - * You may obtain a copy of the License at - * - * https://solderpad.org/licenses/SHL-2.0/ - * - * Unless required by applicable law or agreed to in writing, software - * and hardware implementations thereof - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * provide UVM environment entry and exit points. - */ -import cv32e40x_pkg::pma_region_t; - - class cv32e40x_ldgen_c; - - // Output file names - parameter string MEMORY_LAYOUT_FILE = "linkcmds.memory"; - parameter string SECTIONS_PMA_FILE = "linkcmds.pmasec"; - parameter string SECTIONS_DEBUG_FILE = "linkcmds.dbgsec"; - parameter string FIXED_ADDR_FILE = "linkcmds.fixadd"; - - // Num regions = 0 |-> pma disabled |-> default corev-dv behavior of 2 PMA regions - parameter PMA_NUM_REGIONS = CORE_PARAM_PMA_NUM_REGIONS ? CORE_PARAM_PMA_NUM_REGIONS : 2; - - // indentation level widths - parameter L1 = 3; - parameter L2 = 6; - - // Memory support - when enabled, the linker script gets code regions set to their - // full extent specified by the PMA configuration - alternatively this can be disabled - // to restrict memory regions to a certain size (4096*64 bytes per region default) - parameter LARGE_MEMORY_SUPPORT = 0; - parameter SMALL_MEM_LIMIT = 'h12_0000; - - // Default addresses - parameter RAM_ORIGIN = 32'h0000_0000; - parameter RAM_LENGTH = 32'h40_0000; - parameter BOOT_ADDR = 32'h80; - parameter NMI_ADDR = 32'h0010_0000; - parameter MTVEC_ADDR = 32'h0000_0000; - parameter DEBUG_ORIGIN = 32'h1A11_0800; - parameter DEBUG_EXCEPTION_ADDR = 32'h1A11_1000; - parameter DEBUG_STACK_OFFSET = 32'h80; - - // Disable default regions - disabled ram is the default, as we alias another executable - // region to take its place. - parameter DISABLE_DEFAULT_RAM_REGION = 1; - parameter DISABLE_DEFAULT_DBG_REGION = 0; - - static string info_tag = "ldgen"; - static string default_attributes = "(rwxai)"; - - // Path handles - string ldfiles_path; - - bit disable_default_ram_region; - bit disable_default_dbg_region; - bit enable_large_mem_support; - bit nmi_separate_region; - - int disable_section_write_boot = 0; - int disable_section_write_nmi = 0; - int region_length; - string nmi_memory_area; - string mtvec_memory_area; - string region_attributes; - string section_location; - - // Fixed addresses - int unsigned boot_addr; - int unsigned nmi_addr; - int unsigned mtvec_addr; - int unsigned dbg_origin_addr; - int unsigned dbg_exception_addr; - int unsigned dbg_stack_offset; - - // Test parameters (for multi-generation passes) - bit start_idx_valid; - int start_idx; - int num_of_tests; - - // File handles - int fhandle_mem; - int fhandle_pma; - int fhandle_dbg; - int fhandle_fix; - - pma_region_t regions[PMA_NUM_REGIONS][$]; - pma_region_t temp_region; - int temp_region_ctr; - pma_adapted_memory_regions_c pma_adapted_memory; - - extern function string indent(int num_indent); - extern function void create_memory_layout_file(string filepath); - extern function void create_pma_section_file(string filepath); - extern function void create_dbg_section_file(string filepath); - extern function void create_fixed_addr_section_file(string filepath); - extern function void gen_pma_linker_scripts(); - extern function void display_fatal(string text); - extern function void display_message(string text); - - function new(); - pma_adapted_memory = new(CORE_PARAM_PMA_CFG); - pma_adapted_memory.check_regions; - - // Use defaults if not overridden by plusargs - if (!($value$plusargs("boot_addr=0x%x", boot_addr))) begin - boot_addr = BOOT_ADDR; - end - if (!($value$plusargs("nmi_addr=0x%x", nmi_addr))) begin - nmi_addr = NMI_ADDR; - end - if (!($value$plusargs("mtvec_addr=0x%x", mtvec_addr))) begin - mtvec_addr = MTVEC_ADDR; - end - if (!($value$plusargs("dm_halt_addr=0x%x", dbg_origin_addr))) begin - dbg_origin_addr = DEBUG_ORIGIN; - end - if (!($value$plusargs("dm_exception_addr=0x%x", dbg_exception_addr))) begin - dbg_exception_addr = DEBUG_EXCEPTION_ADDR; - end - if (!($value$plusargs("debug_stack_offset=0x%x", dbg_stack_offset))) begin - dbg_stack_offset = DEBUG_STACK_OFFSET; - end - if (!($value$plusargs("disable_default_ram_region=%d", disable_default_ram_region))) begin - disable_default_ram_region = CORE_PARAM_PMA_NUM_REGIONS ? DISABLE_DEFAULT_RAM_REGION : 0; - end - if (!($value$plusargs("disable_default_dbg_region=%d", disable_default_dbg_region))) begin - disable_default_dbg_region = DISABLE_DEFAULT_DBG_REGION; - end - if (!($value$plusargs("enable_large_mem_support=%d", enable_large_mem_support))) begin - enable_large_mem_support = LARGE_MEMORY_SUPPORT; - end - - if ($value$plusargs("ldgen_cp_test_path=%s", ldfiles_path)) begin - if ($value$plusargs("start_idx=%d", start_idx)) begin - start_idx_valid = 1; - if (!$value$plusargs("num_of_tests=%d", num_of_tests)) begin - display_fatal("Must specify +num_of_tests with +start_idx and +ldgen_cp_test_path"); - end - end - end - - endfunction : new - -endclass : cv32e40x_ldgen_c - -//-------------------------------------------------------------------------------- - -function void cv32e40x_ldgen_c::display_fatal(string text); - `ifdef uvm_fatal - `uvm_fatal(info_tag, text) - `else - $fatal(1, { "[", info_tag, "] ", text }); - `endif -endfunction : display_fatal - -//-------------------------------------------------------------------------------- - -function void cv32e40x_ldgen_c::display_message(string text); - `ifdef uvm_info - `uvm_info(info_tag, text, UVM_LOW) - `else - $display({ "[", info_tag, "] ", text }); - `endif -endfunction : display_message - -//-------------------------------------------------------------------------------- - -function void cv32e40x_ldgen_c::gen_pma_linker_scripts(); - - // If no ldfiles path was configured then emit files to simulation run directory - if (ldfiles_path == "") begin - create_fixed_addr_section_file(FIXED_ADDR_FILE); - create_memory_layout_file(MEMORY_LAYOUT_FILE); - create_pma_section_file(SECTIONS_PMA_FILE); - create_dbg_section_file(SECTIONS_DEBUG_FILE); - end - else if (start_idx_valid) begin - // Iteratively generate the files to indexed directories - // Yes, this is wasteful but overall ldgen is fast so we can live with this - for (int idx = start_idx; idx < start_idx + num_of_tests; idx++) begin - string fixed_addr_file = $sformatf("%s/%0d/test_program/%s", ldfiles_path, idx, FIXED_ADDR_FILE); - string memory_layout_file = $sformatf("%s/%0d/test_program/%s", ldfiles_path, idx, MEMORY_LAYOUT_FILE); - string sections_pma_file = $sformatf("%s/%0d/test_program/%s", ldfiles_path, idx, SECTIONS_PMA_FILE); - string sections_debug_file = $sformatf("%s/%0d/test_program/%s", ldfiles_path, idx, SECTIONS_DEBUG_FILE); - - create_fixed_addr_section_file(fixed_addr_file); - create_memory_layout_file(memory_layout_file); - create_pma_section_file(sections_pma_file); - create_dbg_section_file(sections_debug_file); - end - end - else begin - // Emit files to fixed path - string fixed_addr_file = $sformatf("%s/%s", ldfiles_path, FIXED_ADDR_FILE); - string memory_layout_file = $sformatf("%s/%s", ldfiles_path, MEMORY_LAYOUT_FILE); - string sections_pma_file = $sformatf("%s/%s", ldfiles_path, SECTIONS_PMA_FILE); - string sections_debug_file = $sformatf("%s/%s", ldfiles_path, SECTIONS_DEBUG_FILE); - - create_fixed_addr_section_file(fixed_addr_file); - create_memory_layout_file(memory_layout_file); - create_pma_section_file(sections_pma_file); - create_dbg_section_file(sections_debug_file); - end - display_message("Linker scripts gen complete"); -endfunction : gen_pma_linker_scripts - -//-------------------------------------------------------------------------------- - -function string cv32e40x_ldgen_c::indent(int num_indent); - string indent_val; - indent_val.itoa(num_indent); - return $sformatf( { "%-", indent_val , "s" } , " " ); -endfunction : indent - -//-------------------------------------------------------------------------------- - -function void cv32e40x_ldgen_c::create_memory_layout_file(string filepath); - automatic int nmi_region = -1; - automatic int boot_region = -1; - - fhandle_mem = $fopen(filepath, "w"); - if (!fhandle_mem) begin - display_fatal($sformatf("Unable to open %s", filepath)); - end - - $fdisplay(fhandle_mem, "MEMORY"); - $fdisplay(fhandle_mem, "{"); - - // Optionally disable default ram region definition - if (!disable_default_ram_region) begin - $fdisplay(fhandle_mem, { indent(L1), $sformatf("ram (rwxai) : ORIGIN = 0x%08x, LENGTH = 0x%6x", RAM_ORIGIN, RAM_LENGTH) }); - end - - if (!disable_default_dbg_region) begin - // Debug is not aliased to some other region, so we need to make sure this code is only in place if debug is enabled - $fdisplay(fhandle_mem, { indent(L1), $sformatf("dbg (rwxai) : ORIGIN = 0x%08x, LENGTH = 0x1000", dbg_origin_addr) }); - end - - if (nmi_separate_region) begin - // Separate nmi region if not enclosed by any other region - $fdisplay(fhandle_mem, { indent(L1), $sformatf("nmi (rwxai) : ORIGIN = 0x%08x, LENGTH = 0x1000", nmi_addr) }); - end - - //if (CORE_PARAM_PMA_NUM_REGIONS > 0) begin - if (pma_adapted_memory.region.size > 0) begin - foreach (pma_adapted_memory.region[i]) begin - - if (boot_addr inside { [pma_adapted_memory.region[i].cfg.word_addr_low << 2 : pma_adapted_memory.region[i].cfg.word_addr_high << 2] }) begin - if (pma_adapted_memory.region[i].cfg.main != 1) begin - display_fatal($sformatf("Boot address is not in executable region!")); - end - boot_region = i; - disable_section_write_boot = i; - end - if (LARGE_MEMORY_SUPPORT) begin - if (nmi_addr inside { [pma_adapted_memory.region[i].cfg.word_addr_low << 2: pma_adapted_memory.region[i].cfg.word_addr_high << 2] }) begin - nmi_region = i; - disable_section_write_nmi = i; - end - end else begin - if (nmi_addr inside { [pma_adapted_memory.region[i].cfg.word_addr_low << 2: pma_adapted_memory.region[i].cfg.word_addr_high << 2] }) begin - disable_section_write_nmi = i; - nmi_region = i; - end - end - - if (!(pma_adapted_memory.region[i].cfg.main)) begin - region_attributes = "(!i)"; - end else begin - region_attributes = default_attributes; - end - - // Allow large memory regions if enabled, otherwise restrict to max SMALL_MEM_LIMIT - if (enable_large_mem_support) begin - region_length = (pma_adapted_memory.region[i].cfg.word_addr_high << 2) - (pma_adapted_memory.region[i].cfg.word_addr_low << 2); - end else begin - if ((pma_adapted_memory.region[i].cfg.word_addr_high << 2) - (pma_adapted_memory.region[i].cfg.word_addr_low << 2) <= SMALL_MEM_LIMIT) begin - region_length = (pma_adapted_memory.region[i].cfg.word_addr_high << 2) - (pma_adapted_memory.region[i].cfg.word_addr_low << 2); - end else begin - region_length = SMALL_MEM_LIMIT; - end - end - - // Write to memory.ld - $fdisplay(fhandle_mem, { indent(L1), $sformatf("region_%0d %-7s : ORIGIN = 0x%08x, LENGTH = 0x%08x", - i, region_attributes, pma_adapted_memory.region[i].cfg.word_addr_low<<2, region_length) }); - end // foreach - - // Check for invalid configurations, e.g. boot address not executable or nmi-address not in any memory region (code will not be linkable) - if (boot_region == -1) begin - display_fatal($sformatf("Boot address (0x%08x) is not in any region, regions not covered by PMA are not executable!", boot_addr)); - end - if (nmi_region == -1) begin - display_fatal($sformatf("NMI address (0x%08x) is not in any region, this will cause linker failure!", nmi_addr)); - end - end - - $fdisplay(fhandle_mem, "}"); - - // if the default ram region is enabled, we alias the lowest numbered executable pma region to ram (boot address needs to be set accordingly) - if (disable_default_ram_region) begin - $fdisplay(fhandle_mem, { "REGION_ALIAS(\"ram\", region_", $sformatf("%0d", boot_region), ");" }); - end - - $fclose(fhandle_mem); - display_message({ filepath, " generated" }); - -endfunction : create_memory_layout_file - -//-------------------------------------------------------------------------------- - -function void cv32e40x_ldgen_c::create_pma_section_file(string filepath); - - fhandle_pma = $fopen(filepath, "w"); - if (!fhandle_pma) begin - display_fatal($sformatf("Unable to open %s", filepath)); - end - - // Include all valid regions in memory layout, set non-executable regions as noload for simplicity - if (CORE_PARAM_PMA_NUM_REGIONS > 1 || (CORE_PARAM_PMA_NUM_REGIONS == 1 && !disable_default_ram_region)) begin - $fdisplay(fhandle_pma, "SECTIONS"); - $fdisplay(fhandle_pma, "{"); - - foreach (pma_adapted_memory.region[i]) begin - - if (!(pma_adapted_memory.region[i].cfg.main)) begin - section_location = "(NOLOAD)"; - end else begin - section_location = $sformatf("(ORIGIN(region_%0d))", i); - end - - // Write to section_extra.ld, special case for aliased region, will cause overlap if explicitly created - if (!((disable_section_write_boot == i) || - (disable_section_write_nmi == i))) begin - $fdisplay(fhandle_pma, { indent(L1), ".region_", $sformatf("%0d %0s", i, section_location), ":" }); - $fdisplay(fhandle_pma, { indent(L1), "{" }); - $fdisplay(fhandle_pma, { indent(L2), "KEEP(*(.region_", $sformatf("%0d", i), "));" }); - $fdisplay(fhandle_pma, { indent(L1), "}"}); - end - end - $fdisplay(fhandle_pma, "}"); - end - - $fclose(fhandle_pma); - display_message({ filepath, " generated" }); - -endfunction : create_pma_section_file - -//-------------------------------------------------------------------------------- - -function void cv32e40x_ldgen_c::create_dbg_section_file(string filepath); - int dbg_exception_addr_region = -1; - int dbg_origin_addr_region = -1; - - fhandle_dbg = $fopen(filepath, "w"); - if (!fhandle_dbg) begin - display_fatal($sformatf("Unable to open %s", filepath)); - end - - // Conditionally create the contents of the debug.ld file, otherwise it will be overwritten with an empty file - if (!disable_default_dbg_region) begin - - foreach (pma_adapted_memory.region[i]) begin - if (dbg_exception_addr inside {[pma_adapted_memory.region[i].cfg.word_addr_low<<2:pma_adapted_memory.region[i].cfg.word_addr_high<<2]}) begin - if (pma_adapted_memory.region[i].cfg.main == 1) begin - dbg_exception_addr_region = i; - end - end - if (dbg_origin_addr inside {[pma_adapted_memory.region[i].cfg.word_addr_low<<2:pma_adapted_memory.region[i].cfg.word_addr_high<<2]}) begin - if (pma_adapted_memory.region[i].cfg.main == 1) begin - dbg_origin_addr_region = i; - end - end - end - - if (dbg_exception_addr_region == -1 && CORE_PARAM_PMA_NUM_REGIONS > 0) begin - display_fatal($sformatf("dm_exception_addr (0x%08x) is not within an executable region!", dbg_exception_addr)); - end - if (dbg_origin_addr_region == -1 && CORE_PARAM_PMA_NUM_REGIONS > 0) begin - display_fatal($sformatf("dm_halt_addr (0x%08x) is not within an executable region!", dbg_origin_addr)); - end - - $fdisplay(fhandle_dbg, "SECTIONS"); - $fdisplay(fhandle_dbg, "{"); - //$fdisplay(fhandle_fix, { indent(L1), "debug_rom = ABSOLUTE(", $sformatf("0x%08x", nmi_addr), ");" }); - $fdisplay(fhandle_dbg, { indent(L1), "debug_rom = ABSOLUTE(", $sformatf("0x%08x", dbg_origin_addr), ");" }); - $fdisplay(fhandle_dbg, { indent(L1), "debug_exception = ABSOLUTE(", $sformatf("0x%08x", dbg_exception_addr), ");" }); - - $fdisplay(fhandle_dbg, { indent(L1), ".debugger (ORIGIN(dbg)):" }); - $fdisplay(fhandle_dbg, { indent(L1), "{" }); - $fdisplay(fhandle_dbg, { indent(L2), "KEEP(*(.debugger));" }); - $fdisplay(fhandle_dbg, { indent(L1), "} > dbg" }); - - $fdisplay(fhandle_dbg, { indent(L1), ".debugger_exception ", $sformatf("(0x%08x):", dbg_exception_addr) }); - $fdisplay(fhandle_dbg, { indent(L1), "{" }); - $fdisplay(fhandle_dbg, { indent(L2), "KEEP(*(.debugger_exception));" }); - $fdisplay(fhandle_dbg, { indent(L1), "} > dbg" }); - - $fdisplay(fhandle_dbg, { indent(L1), ".debugger_stack : ALIGN(16)" }); - $fdisplay(fhandle_dbg, { indent(L1), "{" }); - $fdisplay(fhandle_dbg, { indent(L2), "PROVIDE(__debugger_stack_start = .);" }); - $fdisplay(fhandle_dbg, { indent(L2), ". = ", $sformatf("0x%2x;", dbg_stack_offset) }); - $fdisplay(fhandle_dbg, { indent(L1), "} > dbg" }); - $fdisplay(fhandle_dbg, "}"); - end - - $fclose(fhandle_dbg); - display_message({ filepath, " generated" }); -endfunction - -//-------------------------------------------------------------------------------- - -function void cv32e40x_ldgen_c::create_fixed_addr_section_file(string filepath); - automatic int nmi_region = -1; - automatic int boot_region = -1; - automatic int mtvec_region = -1; - automatic int nmi_region_half_length; - - fhandle_fix = $fopen(filepath, "w"); - if (!fhandle_fix) begin - display_fatal($sformatf("Unable to open %s", filepath)); - end - if (pma_adapted_memory.region.size == 0) begin - nmi_separate_region = 1; - end - - foreach (pma_adapted_memory.region[i]) begin - if (mtvec_addr inside { [pma_adapted_memory.region[i].cfg.word_addr_low << 2 : pma_adapted_memory.region[i].cfg.word_addr_high << 2] }) begin - if ((!enable_large_mem_support && ((pma_adapted_memory.region[i].cfg.word_addr_low << 2) + mtvec_addr < SMALL_MEM_LIMIT)) || - enable_large_mem_support) begin - mtvec_region = i; - end - end - if (boot_addr inside { [pma_adapted_memory.region[i].cfg.word_addr_low << 2 : pma_adapted_memory.region[i].cfg.word_addr_high << 2] }) begin - if ((!enable_large_mem_support && ((pma_adapted_memory.region[i].cfg.word_addr_low << 2) + boot_addr < SMALL_MEM_LIMIT)) || - enable_large_mem_support) begin - boot_region = i; - end - end - if (nmi_addr inside { [pma_adapted_memory.region[i].cfg.word_addr_low << 2: pma_adapted_memory.region[i].cfg.word_addr_high << 2] }) begin - if ((!enable_large_mem_support && (nmi_addr - (pma_adapted_memory.region[i].cfg.word_addr_low << 2) < SMALL_MEM_LIMIT)) || - enable_large_mem_support) begin - nmi_region = i; - end else begin - nmi_separate_region = 1; - end - end - end //foreach - - if (mtvec_region != -1) begin - mtvec_memory_area = $sformatf(" > region_%0d", mtvec_region); - end else begin - mtvec_memory_area = ""; - end - - if (nmi_region != -1) begin - nmi_memory_area = $sformatf(" > region_%0d", nmi_region); - // Find which part of region the fixed handlers reside, this is to ensure that we have space to place the remaining section code - nmi_region_half_length = ((pma_adapted_memory.region[nmi_region].cfg.word_addr_high << 2) - (pma_adapted_memory.region[nmi_region].cfg.word_addr_low << 2)) / 2; - end else if (nmi_separate_region) begin - nmi_memory_area = " > nmi"; - end else begin - nmi_memory_area = ""; - end - - $fdisplay(fhandle_fix, "SECTIONS"); - $fdisplay(fhandle_fix, "{"); - $fdisplay(fhandle_fix, { indent(L1), "/* CORE-V: interrupt vectors */" }); - $fdisplay(fhandle_fix, { indent(L1), "PROVIDE(__vector_start = ", $sformatf("0x%08x", mtvec_addr), ");" }); - $fdisplay(fhandle_fix, { indent(L1), ".mtvec_bootstrap (__vector_start) :" }); - $fdisplay(fhandle_fix, { indent(L1), "{" }); - $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.mtvec_bootstrap));" }); - $fdisplay(fhandle_fix, { indent(L1), "}", mtvec_memory_area, "\n" }); - $fdisplay(fhandle_fix, { indent(L1), "/* CORE-V: we want a fixed entry point */" }); - $fdisplay(fhandle_fix, { indent(L1), "PROVIDE(__boot_address = ", $sformatf("0x%08x", boot_addr), ");\n" }); - $fdisplay(fhandle_fix, { indent(L1), "/* NMI interrupt handler fixed entry point */" }); - $fdisplay(fhandle_fix, { indent(L1), "nmi_handler = ABSOLUTE(", $sformatf("0x%08x", nmi_addr), ");" }); - $fdisplay(fhandle_fix, { indent(L1), ".nmi (", $sformatf("0x%08x", nmi_addr), ") :" }); - $fdisplay(fhandle_fix, { indent(L1), "{" }); - $fdisplay(fhandle_fix, { indent(L2), "KEEP(*(.nmi));" }); - $fdisplay(fhandle_fix, { indent(L1), "}", nmi_memory_area }); - $fdisplay(fhandle_fix, "}"); - - $fclose(fhandle_fix); - display_message({ filepath, " generated" }); - -endfunction : create_fixed_addr_section_file diff --git a/cv32e40x/env/corev-dv/mhpmcounter.yaml b/cv32e40x/env/corev-dv/mhpmcounter.yaml deleted file mode 100644 index 250b8ffb05..0000000000 --- a/cv32e40x/env/corev-dv/mhpmcounter.yaml +++ /dev/null @@ -1,1408 +0,0 @@ -# Copyright 2020 OpenHW Group -# Copyright 2019 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -################################################################################ -# -# CSR definitions for the CV32E40X CORE-V proessor core (an RV32IMCZ machine). -# -# This file can be used as input to "gen_csr_test.py" delivered as part of -# Google's riscv-dv project. Assuming you are running this from -# core-v-verif/vendor_lib/google/corev-dv and you've cloned riscv-dv, then the -# following command-line should work for you: -# -# python3 ../riscv-dv/scripts/gen_csr_test.py \ -# --csr_file \ -# --xlen 32 -# -# Source document is the CV32E40X user Manual: -# https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40x_um/en/latest/index.html -# Revision 62f0d86b -# -# Assumptions: -# 1. Core RTL parameter NUM_MHPMCOUNTERS is set to 29. -################################################################################ -#- csr: CSR_NAME -# description: > -# BRIEF_DESCRIPTION -# address: 0x### -# privilege_mode: MODE (D/M/S/H/U) -# rv32: -# - MSB_FIELD_NAME: -# - description: > -# BRIEF_DESCRIPTION -# - type: TYPE (WPRI/WLRL/WARL/R) -# - reset_val: RESET_VAL -# - msb: MSB_POS -# - lsb: LSB_POS -# - ... -# - ... -# - LSB_FIELD_NAME: -# - description: ... -# - type: ... -# - ... -# rv64: -# - MSB_FIELD_NAME: -# - description: > -# BRIEF_DESCRIPTION -# - type: TYPE (WPRI/WLRL/WARL/R) -# - reset_val: RESET_VAL -# - msb: MSB_POS -# - lsb: LSB_POS -# - ... -# - ... -# - LSB_FIELD_NAME: -# - description: ... -# - type: ... -# - ... -############################################################################### -- csr: mhpmevent3 - description: > - (HPM) Machine Performance-Monitoring Event Selector 3 - address: 0x323 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent4 - description: > - (HPM) Machine Performance-Monitoring Event Selector 4 - address: 0x324 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent5 - description: > - (HPM) Machine Performance-Monitoring Event Selector 5 - address: 0x325 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent6 - description: > - (HPM) Machine Performance-Monitoring Event Selector 6 - address: 0x326 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent7 - description: > - (HPM) Machine Performance-Monitoring Event Selector 7 - address: 0x327 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent8 - description: > - (HPM) Machine Performance-Monitoring Event Selector 8 - address: 0x328 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent9 - description: > - (HPM) Machine Performance-Monitoring Event Selector 9 - address: 0x329 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent10 - description: > - (HPM) Machine Performance-Monitoring Event Selector 10 - address: 0x32a - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent11 - description: > - (HPM) Machine Performance-Monitoring Event Selector 11 - address: 0x32b - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent12 - description: > - (HPM) Machine Performance-Monitoring Event Selector 12 - address: 0x32c - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent13 - description: > - (HPM) Machine Performance-Monitoring Event Selector 13 - address: 0x32d - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent14 - description: > - (HPM) Machine Performance-Monitoring Event Selector 14 - address: 0x32e - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent15 - description: > - (HPM) Machine Performance-Monitoring Event Selector 15 - address: 0x32f - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent16 - description: > - (HPM) Machine Performance-Monitoring Event Selector 16 - address: 0x330 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent17 - description: > - (HPM) Machine Performance-Monitoring Event Selector 17 - address: 0x331 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent18 - description: > - (HPM) Machine Performance-Monitoring Event Selector 18 - address: 0x332 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent19 - description: > - (HPM) Machine Performance-Monitoring Event Selector 19 - address: 0x333 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent20 - description: > - (HPM) Machine Performance-Monitoring Event Selector 20 - address: 0x334 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent21 - description: > - (HPM) Machine Performance-Monitoring Event Selector 21 - address: 0x335 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent22 - description: > - (HPM) Machine Performance-Monitoring Event Selector 22 - address: 0x336 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent23 - description: > - (HPM) Machine Performance-Monitoring Event Selector 23 - address: 0x337 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent24 - description: > - (HPM) Machine Performance-Monitoring Event Selector 24 - address: 0x338 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent25 - description: > - (HPM) Machine Performance-Monitoring Event Selector 25 - address: 0x339 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent26 - description: > - (HPM) Machine Performance-Monitoring Event Selector 26 - address: 0x33a - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent27 - description: > - (HPM) Machine Performance-Monitoring Event Selector 27 - address: 0x33b - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent28 - description: > - (HPM) Machine Performance-Monitoring Event Selector 28 - address: 0x33c - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent29 - description: > - (HPM) Machine Performance-Monitoring Event Selector 29 - address: 0x33d - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent30 - description: > - (HPM) Machine Performance-Monitoring Event Selector 30 - address: 0x33e - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -- csr: mhpmevent31 - description: > - (HPM) Machine Performance-Monitoring Event Selector 31 - address: 0x33f - privilege_mode: M - rv32: - - field_name: Zero - description: > - Always zero - type: R - reset_val: 0 - msb: 31 - lsb: 16 - - field_name: Selectors - description: > - Event selector - type: WARL - reset_val: 0 - msb: 15 - lsb: 0 -############################################################################### -- csr: mhpmcounter3 - description: > - (HPM) Machine Performance-Monitoring Counter 3 - address: 0xB03 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter4 - description: > - (HPM) Machine Performance-Monitoring Counter 14 - address: 0xB04 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter5 - description: > - (HPM) Machine Performance-Monitoring Counter 15 - address: 0xB05 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter6 - description: > - (HPM) Machine Performance-Monitoring Counter 16 - address: 0xB06 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter7 - description: > - (HPM) Machine Performance-Monitoring Counter 17 - address: 0xB07 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter8 - description: > - (HPM) Machine Performance-Monitoring Counter 18 - address: 0xB08 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter9 - description: > - (HPM) Machine Performance-Monitoring Counter 19 - address: 0xB09 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter10 - description: > - (HPM) Machine Performance-Monitoring Counter 10 - address: 0xB0A - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter11 - description: > - (HPM) Machine Performance-Monitoring Counter 11 - address: 0xB0B - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter12 - description: > - (HPM) Machine Performance-Monitoring Counter 12 - address: 0xB0C - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter13 - description: > - (HPM) Machine Performance-Monitoring Counter 13 - address: 0xB0D - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter14 - description: > - (HPM) Machine Performance-Monitoring Counter 14 - address: 0xB0E - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter15 - description: > - (HPM) Machine Performance-Monitoring Counter 15 - address: 0xB0F - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter16 - description: > - (HPM) Machine Performance-Monitoring Counter 16 - address: 0xB10 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter17 - description: > - (HPM) Machine Performance-Monitoring Counter 17 - address: 0xB11 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter18 - description: > - (HPM) Machine Performance-Monitoring Counter 18 - address: 0xB12 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter19 - description: > - (HPM) Machine Performance-Monitoring Counter 19 - address: 0xB13 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter20 - description: > - (HPM) Machine Performance-Monitoring Counter 20 - address: 0xB14 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter21 - description: > - (HPM) Machine Performance-Monitoring Counter 21 - address: 0xB15 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter22 - description: > - (HPM) Machine Performance-Monitoring Counter 22 - address: 0xB16 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter23 - description: > - (HPM) Machine Performance-Monitoring Counter 23 - address: 0xB17 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter24 - description: > - (HPM) Machine Performance-Monitoring Counter 24 - address: 0xB18 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter25 - description: > - (HPM) Machine Performance-Monitoring Counter 25 - address: 0xB19 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter26 - description: > - (HPM) Machine Performance-Monitoring Counter 26 - address: 0xB1A - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter27 - description: > - (HPM) Machine Performance-Monitoring Counter 27 - address: 0xB1B - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter28 - description: > - (HPM) Machine Performance-Monitoring Counter 28 - address: 0xB1C - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter29 - description: > - (HPM) Machine Performance-Monitoring Counter 29 - address: 0xB1D - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter30 - description: > - (HPM) Machine Performance-Monitoring Counter 30 - address: 0xB1E - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounter31 - description: > - (HPM) Machine Performance-Monitoring Counter 31 - address: 0xB1F - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 31 to 0 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -############################################################################### -- csr: mhpmcounterh3 - description: > - (HPM) Machine Performance-Monitoring Counter 3 - address: 0xB83 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh4 - description: > - (HPM) Machine Performance-Monitoring Counter 14 - address: 0xB84 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh5 - description: > - (HPM) Machine Performance-Monitoring Counter 15 - address: 0xB85 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh6 - description: > - (HPM) Machine Performance-Monitoring Counter 16 - address: 0xB86 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh7 - description: > - (HPM) Machine Performance-Monitoring Counter 17 - address: 0xB87 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh8 - description: > - (HPM) Machine Performance-Monitoring Counter 18 - address: 0xB88 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh9 - description: > - (HPM) Machine Performance-Monitoring Counter 19 - address: 0xB89 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh10 - description: > - (HPM) Machine Performance-Monitoring Counter 10 - address: 0xB8A - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh11 - description: > - (HPM) Machine Performance-Monitoring Counter 11 - address: 0xB8B - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh12 - description: > - (HPM) Machine Performance-Monitoring Counter 12 - address: 0xB8C - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh13 - description: > - (HPM) Machine Performance-Monitoring Counter 13 - address: 0xB8D - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh14 - description: > - (HPM) Machine Performance-Monitoring Counter 14 - address: 0xB8E - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh15 - description: > - (HPM) Machine Performance-Monitoring Counter 15 - address: 0xB8F - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh16 - description: > - (HPM) Machine Performance-Monitoring Counter 16 - address: 0xB90 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh17 - description: > - (HPM) Machine Performance-Monitoring Counter 17 - address: 0xB91 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh18 - description: > - (HPM) Machine Performance-Monitoring Counter 18 - address: 0xB92 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh19 - description: > - (HPM) Machine Performance-Monitoring Counter 19 - address: 0xB93 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh20 - description: > - (HPM) Machine Performance-Monitoring Counter 20 - address: 0xB94 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh21 - description: > - (HPM) Machine Performance-Monitoring Counter 21 - address: 0xB95 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh22 - description: > - (HPM) Machine Performance-Monitoring Counter 22 - address: 0xB96 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh23 - description: > - (HPM) Machine Performance-Monitoring Counter 23 - address: 0xB97 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh24 - description: > - (HPM) Machine Performance-Monitoring Counter 24 - address: 0xB98 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh25 - description: > - (HPM) Machine Performance-Monitoring Counter 25 - address: 0xB99 - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh26 - description: > - (HPM) Machine Performance-Monitoring Counter 26 - address: 0xB9A - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh27 - description: > - (HPM) Machine Performance-Monitoring Counter 27 - address: 0xB9B - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh28 - description: > - (HPM) Machine Performance-Monitoring Counter 28 - address: 0xB9C - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh29 - description: > - (HPM) Machine Performance-Monitoring Counter 29 - address: 0xB9D - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh30 - description: > - (HPM) Machine Performance-Monitoring Counter 30 - address: 0xB9E - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -- csr: mhpmcounterh31 - description: > - (HPM) Machine Performance-Monitoring Counter 31 - address: 0xB9F - privilege_mode: M - rv32: - - field_name: Zero - description: > - Counter bits 63 to 32 - type: WARL - reset_val: 0 - msb: 31 - lsb: 0 -####end######end###### diff --git a/cv32e40x/env/corev-dv/target/cv32e40x/riscv_core_setting.sv b/cv32e40x/env/corev-dv/target/cv32e40x/riscv_core_setting.sv deleted file mode 100644 index 058b2fea7e..0000000000 --- a/cv32e40x/env/corev-dv/target/cv32e40x/riscv_core_setting.sv +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright 2019 Google LLC - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//----------------------------------------------------------------------------- -// Processor feature configuration -//----------------------------------------------------------------------------- -// XLEN -parameter int XLEN = 32; - -// Parameter for SATP mode, set to BARE if address translation is not supported -parameter satp_mode_t SATP_MODE = BARE; - -// Supported Privileged mode -privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE}; - -// Unsupported instructions -riscv_instr_name_t unsupported_instr[]; - -// ISA supported by the processor -riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32ZBA, RV32ZBB, RV32ZBC, RV32ZBS}; - -// Interrupt mode support -mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; - -// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is -// supported -int max_interrupt_vector_num = 32; - -// Valid CLINT interrupts -bit [31:0] valid_interrupt_mask = 32'hffff_0888; - -// Physical memory protection support -bit support_pmp = 0; - -// Debug mode support -bit support_debug_mode = 1; - -// Support delegate trap to user mode -bit support_umode_trap = 0; - -// Support sfence.vma instruction -bit support_sfence = 0; - -// Support unaligned load/store -bit support_unaligned_load_store = 1'b1; - -// GPR setting -parameter int NUM_FLOAT_GPR = 32; -parameter int NUM_GPR = 32; -parameter int NUM_VEC_GPR = 32; - -// ---------------------------------------------------------------------------- -// Vector extension configuration -// ---------------------------------------------------------------------------- - -// Parameter for vector extension -parameter int VECTOR_EXTENSION_ENABLE = 0; - -parameter int VLEN = 512; - -// Maximum size of a single vector element -parameter int ELEN = 32; - -// Minimum size of a sub-element, which must be at most 8-bits. -parameter int SELEN = 8; - -// Maximum size of a single vector element (encoded in vsew format) -parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3; - -// Maxium LMUL supported by the core -parameter int MAX_LMUL = 8; - -// ---------------------------------------------------------------------------- -// Multi-harts configuration -// ---------------------------------------------------------------------------- - -// Number of harts -parameter int NUM_HARTS = 1; - -// ---------------------------------------------------------------------------- -// Privileged CSR implementation -// ---------------------------------------------------------------------------- - -// Implemented privileged CSR list -`ifdef DSIM -privileged_reg_t implemented_csr[] = { -`else -const privileged_reg_t implemented_csr[] = { -`endif - // Machine mode mode CSR - MSTATUS, // Machine status - MISA, // ISA and extensions - MIE, // Machine interrupt-enable register - MTVEC, // Machine trap-handler base address - //MTVT, // Machine Trap-Handler Vector Table Base Address (CLIC=1) - MSTATUSH, // Machine Status (upper 32 bits). - MCOUNTINHIBIT, // Machine Counter-Inhibit Register - MHPMEVENT3, // Machine Performance-Monitoring Event Selector 3 - MHPMEVENT4, // Machine Performance-Monitoring Event Selector 4 - MHPMEVENT5, // Machine Performance-Monitoring Event Selector 5 - MHPMEVENT6, // Machine Performance-Monitoring Event Selector 6 - MHPMEVENT7, // Machine Performance-Monitoring Event Selector 7 - MHPMEVENT8, // Machine Performance-Monitoring Event Selector 8 - MHPMEVENT9, // Machine Performance-Monitoring Event Selector 9 - MHPMEVENT10, // Machine Performance-Monitoring Event Selector 10 - MHPMEVENT11, // Machine Performance-Monitoring Event Selector 11 - MHPMEVENT12, // Machine Performance-Monitoring Event Selector 12 - MHPMEVENT13, // Machine Performance-Monitoring Event Selector 13 - MHPMEVENT14, // Machine Performance-Monitoring Event Selector 14 - MHPMEVENT15, // Machine Performance-Monitoring Event Selector 15 - MHPMEVENT16, // Machine Performance-Monitoring Event Selector 16 - MHPMEVENT17, // Machine Performance-Monitoring Event Selector 17 - MHPMEVENT18, // Machine Performance-Monitoring Event Selector 18 - MHPMEVENT19, // Machine Performance-Monitoring Event Selector 19 - MHPMEVENT20, // Machine Performance-Monitoring Event Selector 20 - MHPMEVENT21, // Machine Performance-Monitoring Event Selector 21 - MHPMEVENT22, // Machine Performance-Monitoring Event Selector 22 - MHPMEVENT23, // Machine Performance-Monitoring Event Selector 23 - MHPMEVENT24, // Machine Performance-Monitoring Event Selector 24 - MHPMEVENT25, // Machine Performance-Monitoring Event Selector 25 - MHPMEVENT26, // Machine Performance-Monitoring Event Selector 26 - MHPMEVENT27, // Machine Performance-Monitoring Event Selector 27 - MHPMEVENT28, // Machine Performance-Monitoring Event Selector 28 - MHPMEVENT29, // Machine Performance-Monitoring Event Selector 29 - MHPMEVENT30, // Machine Performance-Monitoring Event Selector 30 - MHPMEVENT31, // Machine Performance-Monitoring Event Selector 31 - MSCRATCH, // Scratch register for machine trap handlers - MEPC, // Machine exception program counter - MCAUSE, // Machine trap cause - MTVAL, // Machine bad address or instruction - MIP, // Machine interrupt pending - //MNXTI, // Interrupt handler address and enable modifier (CLIC=1) - //MINTSTATUS, // Current interrupt levels (CLIC=1) - //MINTTHRESH, // Interrupt-level threshold (CLIC=1) - //MSCRATCHCSW, // Conditional scratch swap on priv mode change (CLIC=1) - //MSCRATCHCSWL, // Conditional scratch swap on level change (CLIC=1) - TSELECT, // Trigger Select Register - TDATA1, // Trigger Data Register 1 - TDATA2, // Trigger Data Register 2 - TDATA3, // Trigger Data Register 3 - TINFO, // Trigger Info - TCONTROL, // Trigger Control - MCONTEXT, // Machine Context - MSCONTEXT, // Machine Supervisor Context - MCYCLE, // Machine Instructions-Retired Counter - MHPMCOUNTER3, // Machine Performance-Monitoring Counter 3 - MHPMCOUNTER4, // Machine Performance-Monitoring Counter 4 - MHPMCOUNTER5, // Machine Performance-Monitoring Counter 5 - MHPMCOUNTER6, // Machine Performance-Monitoring Counter 6 - MHPMCOUNTER7, // Machine Performance-Monitoring Counter 7 - MHPMCOUNTER8, // Machine Performance-Monitoring Counter 8 - MHPMCOUNTER9, // Machine Performance-Monitoring Counter 9 - MHPMCOUNTER10, // Machine Performance-Monitoring Counter 10 - MHPMCOUNTER11, // Machine Performance-Monitoring Counter 11 - MHPMCOUNTER12, // Machine Performance-Monitoring Counter 12 - MHPMCOUNTER13, // Machine Performance-Monitoring Counter 13 - MHPMCOUNTER14, // Machine Performance-Monitoring Counter 14 - MHPMCOUNTER15, // Machine Performance-Monitoring Counter 15 - MHPMCOUNTER16, // Machine Performance-Monitoring Counter 16 - MHPMCOUNTER17, // Machine Performance-Monitoring Counter 17 - MHPMCOUNTER18, // Machine Performance-Monitoring Counter 18 - MHPMCOUNTER19, // Machine Performance-Monitoring Counter 19 - MHPMCOUNTER20, // Machine Performance-Monitoring Counter 20 - MHPMCOUNTER21, // Machine Performance-Monitoring Counter 21 - MHPMCOUNTER22, // Machine Performance-Monitoring Counter 22 - MHPMCOUNTER23, // Machine Performance-Monitoring Counter 23 - MHPMCOUNTER24, // Machine Performance-Monitoring Counter 24 - MHPMCOUNTER25, // Machine Performance-Monitoring Counter 25 - MHPMCOUNTER26, // Machine Performance-Monitoring Counter 26 - MHPMCOUNTER27, // Machine Performance-Monitoring Counter 27 - MHPMCOUNTER28, // Machine Performance-Monitoring Counter 28 - MHPMCOUNTER29, // Machine Performance-Monitoring Counter 29 - MHPMCOUNTER30, // Machine Performance-Monitoring Counter 30 - MHPMCOUNTER31, // Machine Performance-Monitoring Counter 31 - MCYCLEH, // Upper 32 Machine Cycle Counter - MINSTRETH, // Upper 32 Machine Instructions-Retired Counter - MHPMCOUNTER3H, // Upper Machine Performance-Monitoring Counter 3 - MHPMCOUNTER4H, // Upper Machine Performance-Monitoring Counter 4 - MHPMCOUNTER5H, // Upper Machine Performance-Monitoring Counter 5 - MHPMCOUNTER6H, // Upper Machine Performance-Monitoring Counter 6 - MHPMCOUNTER7H, // Upper Machine Performance-Monitoring Counter 7 - MHPMCOUNTER8H, // Upper Machine Performance-Monitoring Counter 8 - MHPMCOUNTER9H, // Upper Machine Performance-Monitoring Counter 9 - MHPMCOUNTER10H, // Upper Machine Performance-Monitoring Counter 10 - MHPMCOUNTER11H, // Upper Machine Performance-Monitoring Counter 11 - MHPMCOUNTER12H, // Upper Machine Performance-Monitoring Counter 12 - MHPMCOUNTER13H, // Upper Machine Performance-Monitoring Counter 13 - MHPMCOUNTER14H, // Upper Machine Performance-Monitoring Counter 14 - MHPMCOUNTER15H, // Upper Machine Performance-Monitoring Counter 15 - MHPMCOUNTER16H, // Upper Machine Performance-Monitoring Counter 16 - MHPMCOUNTER17H, // Upper Machine Performance-Monitoring Counter 17 - MHPMCOUNTER18H, // Upper Machine Performance-Monitoring Counter 18 - MHPMCOUNTER19H, // Upper Machine Performance-Monitoring Counter 19 - MHPMCOUNTER20H, // Upper Machine Performance-Monitoring Counter 20 - MHPMCOUNTER21H, // Upper Machine Performance-Monitoring Counter 21 - MHPMCOUNTER22H, // Upper Machine Performance-Monitoring Counter 22 - MHPMCOUNTER23H, // Upper Machine Performance-Monitoring Counter 23 - MHPMCOUNTER24H, // Upper Machine Performance-Monitoring Counter 24 - MHPMCOUNTER25H, // Upper Machine Performance-Monitoring Counter 25 - MHPMCOUNTER26H, // Upper Machine Performance-Monitoring Counter 26 - MHPMCOUNTER27H, // Upper Machine Performance-Monitoring Counter 27 - MHPMCOUNTER28H, // Upper Machine Performance-Monitoring Counter 28 - MHPMCOUNTER29H, // Upper Machine Performance-Monitoring Counter 29 - MHPMCOUNTER30H, // Upper Machine Performance-Monitoring Counter 30 - MHPMCOUNTER31H, // Upper Machine Performance-Monitoring Counter 31 - MVENDORID, // Vendor ID - MARCHID, // Architecture ID - MIMPID, // Implementation ID - MHARTID, // Hardware thread ID - MCONFIGPTR // Machine Configuration Pointer -}; - -`ifdef DSIM - bit [11:0] custom_csr[] = { -`elsif _VCP - bit [11:0] custom_csr[] = { -`else - const bit [11:0] custom_csr[] = { -`endif -}; - -// ---------------------------------------------------------------------------- -// Supported interrupt/exception setting, used for functional coverage -// ---------------------------------------------------------------------------- - -`ifdef DSIM -interrupt_cause_t implemented_interrupt[] = { -`else -const interrupt_cause_t implemented_interrupt[] = { -`endif - M_SOFTWARE_INTR, - M_TIMER_INTR, - M_EXTERNAL_INTR -}; - -`ifdef DSIM -exception_cause_t implemented_exception[] = { -`else -const exception_cause_t implemented_exception[] = { -`endif - INSTRUCTION_ACCESS_FAULT, - ILLEGAL_INSTRUCTION, - BREAKPOINT, - LOAD_ADDRESS_MISALIGNED, - LOAD_ACCESS_FAULT, - ECALL_MMODE -}; diff --git a/cv32e40x/env/uvme/cov/uvme_counters_covg.sv b/cv32e40x/env/uvme/cov/uvme_counters_covg.sv deleted file mode 100644 index 6f07cc4b31..0000000000 --- a/cv32e40x/env/uvme/cov/uvme_counters_covg.sv +++ /dev/null @@ -1,194 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - - -covergroup cg_counters (int num_mhpmcounters) - with function sample(uvma_isacov_mon_trn_c isacov); - - `per_instance_fcov - - cp_inhibit_mcycle : coverpoint isacov.instr.rvfi.csrs["mcountinhibit"].get_csr_retirement_data()[0]; - cp_inhibit_minstret : coverpoint isacov.instr.rvfi.csrs["mcountinhibit"].get_csr_retirement_data()[2]; - cp_is_csr_read : coverpoint (isacov.instr.group == CSR_GROUP) && (isacov.instr.rd != 0) { - bins is_csr_read = {1}; - } - cp_is_dbg_mode : coverpoint isacov.instr.rvfi.dbg_mode { - bins dbg_mode = {1}; - } - cp_mcycle : coverpoint (isacov.instr.csr == uvma_isacov_pkg::MCYCLE); - cp_minstret : coverpoint (isacov.instr.csr == uvma_isacov_pkg::MINSTRET); - cp_num_mhpmcounters : coverpoint num_mhpmcounters { - bins min = {0}; - bins def = {1}; - bins any = {[2:28]}; - bins max = {29}; - } - - cross_check_mcycle : cross cp_inhibit_mcycle, cp_is_csr_read, cp_mcycle { - option.at_least = 2; - } - cross_check_minstret : cross cp_inhibit_minstret, cp_is_csr_read, cp_minstret { - option.at_least = 2; - } - cross_mcycle_in_dbg : cross cp_is_dbg_mode, cp_inhibit_mcycle, cp_is_csr_read, cp_mcycle { - option.at_least = 2; - ignore_bins ig = binsof(cp_inhibit_mcycle) intersect {1} || binsof(cp_mcycle) intersect {0}; - } - cross_minstret_in_dbg : cross cp_is_dbg_mode, cp_inhibit_mcycle, cp_is_csr_read, cp_minstret { - option.at_least = 2; - ignore_bins ig = binsof(cp_inhibit_mcycle) intersect {1} || binsof(cp_minstret) intersect {0}; - } -endgroup : cg_counters - - - -covergroup cg_mhpm (int idx) - with function sample(uvma_isacov_mon_trn_c isacov); - - `per_instance_fcov - - cp_inhibit : coverpoint isacov.instr.rvfi.csrs["mcountinhibit"].get_csr_retirement_data()[idx] { - bins inhibit = {1}; - bins no_inhibit = {0}; - } - cp_event : coverpoint isacov.instr.rvfi.csrs[$sformatf("mhpmevent%0d", idx)].get_csr_retirement_data() { - bins events = {[1:$]}; - bins no_events = {0}; - } - cp_is_csr_read : coverpoint (isacov.instr.group == CSR_GROUP) && (isacov.instr.rd != 0) { - bins is_csr_read = {1}; - } - cp_is_mhpm_idx : coverpoint (isacov.instr.csr == (uvma_isacov_pkg::MCYCLE + idx)) { - bins mhpm_idx = {1}; - } - cp_is_mhpm_idx_h : coverpoint (isacov.instr.csr == (uvma_isacov_pkg::MCYCLEH + idx)) { - bins mhpm_idx_h = {1}; - } - cp_is_dbg_mode : coverpoint isacov.instr.rvfi.dbg_mode { - bins dbg_mode = {1}; - } - - cross_check_mhpm : cross cp_inhibit, cp_event, cp_is_csr_read, cp_is_mhpm_idx { - option.at_least = 2; - } - cross_check_mhpm_h : cross cp_inhibit, cp_event, cp_is_csr_read, cp_is_mhpm_idx_h { - option.at_least = 2; - } - cross_mhpm_in_dbg: cross cp_is_dbg_mode, cp_inhibit, cp_event, cp_is_csr_read, cp_is_mhpm_idx { - option.at_least = 2; - ignore_bins ig = binsof(cp_inhibit) intersect {1} || binsof(cp_event) intersect{0}; - } - -endgroup : cg_mhpm - - -covergroup cg_inhibit_mix (int idx) - with function sample(uvma_isacov_mon_trn_c isacov); - - `per_instance_fcov - - cp_inhibit_mcycle : coverpoint isacov.instr.rvfi.csrs["mcountinhibit"].get_csr_retirement_data()[0]; - cp_inhibit_minstret : coverpoint isacov.instr.rvfi.csrs["mcountinhibit"].get_csr_retirement_data()[2]; - cp_is_csr_read : coverpoint (isacov.instr.group == CSR_GROUP) && (isacov.instr.rd != 0) { - bins is_csr_read = {1}; - } - cp_is_event_cycles : coverpoint isacov.instr.rvfi.csrs[$sformatf("mhpmevent%0d", idx)].get_csr_retirement_data() { - bins event_cycles = {1}; // selector CYCLES is bit 0 - } - cp_is_event_instr : coverpoint isacov.instr.rvfi.csrs[$sformatf("mhpmevent%0d", idx)].get_csr_retirement_data() { - bins event_instr = {2}; // selector INSTR is bit 1 - } - cp_is_mhpm_idx : coverpoint (isacov.instr.csr == (uvma_isacov_pkg::MCYCLE + idx)) { - bins mhpm_idx = {1}; - } - - cross_check_mcycle : cross cp_inhibit_mcycle, cp_is_csr_read, cp_is_event_cycles, cp_is_mhpm_idx { - option.at_least = 2; - } - cross_check_minstret : cross cp_inhibit_minstret, cp_is_csr_read, cp_is_event_instr, cp_is_mhpm_idx { - option.at_least = 2; - } - -endgroup : cg_inhibit_mix - - - -class cg_idx_wrapper extends uvm_component; - - cg_mhpm mhpm_cg; - cg_inhibit_mix inhibit_mix_cg; - - function new(string name = "cg_mhpm_wrapper", uvm_component parent = null, int idx); - super.new(name, parent); - this.mhpm_cg = new(idx); - this.inhibit_mix_cg = new(idx); - endfunction : new - - function sample(uvma_isacov_mon_trn_c isacov); - mhpm_cg.sample(isacov); - inhibit_mix_cg.sample(isacov); - endfunction : sample - -endclass : cg_idx_wrapper - - -class uvme_counters_covg extends uvm_component; - - `uvm_analysis_imp_decl(_isacov) - - cg_counters counters_cg; - cg_idx_wrapper idx_cgs[3:31]; - uvm_analysis_imp_isacov#(uvma_isacov_mon_trn_c, uvme_counters_covg) isacov_mon_export; - uvma_core_cntrl_cfg_c cfg; - - `uvm_component_utils(uvme_counters_covg); - - extern function new(string name = "counters_covg", uvm_component parent = null); - extern function void build_phase(uvm_phase phase); - extern function void write_isacov(uvma_isacov_mon_trn_c trn); - -endclass : uvme_counters_covg - - -function uvme_counters_covg::new(string name = "counters_covg", uvm_component parent = null); - - super.new(name, parent); - - isacov_mon_export = new("isacov_mon_export", this); - -endfunction : new - - -function void uvme_counters_covg::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvma_core_cntrl_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) `uvm_fatal("COUNTERSCOVG", "Configuration handle is null") - - counters_cg = new(cfg.num_mhpmcounters); - for (int i = 3; i <=31; i++) idx_cgs[i] = new(.name($sformatf("cg_idx_wrapper_%02d", i)), .parent(this), .idx(i)); - -endfunction : build_phase - - -function void uvme_counters_covg::write_isacov(uvma_isacov_mon_trn_c trn); - - counters_cg.sample(trn); - for (int i = 0; i < cfg.num_mhpmcounters; i++) void'(idx_cgs[i + 3].sample(trn)); - -endfunction : write_isacov diff --git a/cv32e40x/env/uvme/cov/uvme_cv32e40x_cov_model.sv b/cv32e40x/env/uvme/cov/uvme_cv32e40x_cov_model.sv deleted file mode 100644 index 76a8b753f6..0000000000 --- a/cv32e40x/env/uvme/cov/uvme_cv32e40x_cov_model.sv +++ /dev/null @@ -1,111 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - -`ifndef __UVME_CV32E40X_COV_MODEL_SV__ -`define __UVME_CV32E40X_COV_MODEL_SV__ - - -/** - * Component encapsulating CV32E40X environment's functional coverage model. - */ -class uvme_cv32e40x_cov_model_c extends uvm_component; - - // Objects - uvme_cv32e40x_cfg_c cfg; - uvme_cv32e40x_cntxt_c cntxt; - - uvme_interrupt_covg interrupt_covg; - uvme_debug_covg debug_covg; - uvme_exceptions_covg exceptions_covg; - uvme_counters_covg counters_covg; - - `uvm_component_utils_begin(uvme_cv32e40x_cov_model_c) - `uvm_field_object(cfg , UVM_DEFAULT) - `uvm_field_object(cntxt, UVM_DEFAULT) - `uvm_component_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_cov_model", uvm_component parent=null); - - /** - * Ensures cfg & cntxt handles are not null. - */ - extern virtual function void build_phase(uvm_phase phase); - - /** - * Connects ISA coverage model to interrupt coverage model - */ - extern virtual function void connect_phase(uvm_phase phase); - - /** - * Describe uvme_cv32e40x_cov_model_c::run_phase() - */ - extern virtual task run_phase(uvm_phase phase); - -endclass : uvme_cv32e40x_cov_model_c - - -function uvme_cv32e40x_cov_model_c::new(string name="uvme_cv32e40x_cov_model", uvm_component parent=null); - - super.new(name, parent); - -endfunction : new - -function void uvme_cv32e40x_cov_model_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvme_cv32e40x_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) begin - `uvm_fatal("CFG", "Configuration handle is null") - end - - void'(uvm_config_db#(uvme_cv32e40x_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (!cntxt) begin - `uvm_fatal("CNTXT", "Context handle is null") - end - - interrupt_covg = uvme_interrupt_covg::type_id::create("interrupt_covg", this); - uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "interrupt_covg", "cfg", cfg); - - debug_covg = uvme_debug_covg::type_id::create("debug_covg", this); - uvm_config_db#(uvme_cv32e40x_cntxt_c)::set(this, "debug_covg", "cntxt", cntxt); - - exceptions_covg = uvme_exceptions_covg::type_id::create("exceptions_covg", this); - - counters_covg = uvme_counters_covg::type_id::create("counters_covg", this); - uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "counters_covg", "cfg", cfg); - -endfunction : build_phase - -function void uvme_cv32e40x_cov_model_c::connect_phase(uvm_phase phase); - - super.connect_phase(phase); - -endfunction : connect_phase - -task uvme_cv32e40x_cov_model_c::run_phase(uvm_phase phase); - - super.run_phase(phase); - -endtask : run_phase - - -`endif // __UVME_CV32E40X_COV_MODEL_SV__ diff --git a/cv32e40x/env/uvme/cov/uvme_debug_covg.sv b/cv32e40x/env/uvme/cov/uvme_debug_covg.sv deleted file mode 100644 index b2ea9ded1d..0000000000 --- a/cv32e40x/env/uvme/cov/uvme_debug_covg.sv +++ /dev/null @@ -1,508 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright 2020 OpenHW Group -// Copyright 2020 BTA Design Services -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// -/////////////////////////////////////////////////////////////////////////////// - - -class uvme_debug_covg extends uvm_component; - - /* - * Class members - */ - uvme_cv32e40x_cntxt_c cntxt; - - - `uvm_component_utils(uvme_debug_covg); - - extern function new(string name = "debug_covg", uvm_component parent = null); - extern function void build_phase(uvm_phase phase); - extern task run_phase(uvm_phase phase); - - extern task sample_clk_i(); - extern task sample_debug_req_i(); - - /* - * Covergroups - */ - - covergroup cg_debug_mode_ext ; - `per_instance_fcov - state: coverpoint cntxt.debug_cov_vif.mon_cb.ctrl_fsm_cs{ - } - endgroup : cg_debug_mode_ext - - // Cover that we execute ebreak with dcsr.ebreakm==1 - covergroup cg_ebreak_execute_with_ebreakm; - `per_instance_fcov - ex: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { - bins active = {1}; - } - ebreakm_set: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { - bins active = {1}; - } - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins active = {1}; - } - ebreak_with_ebreakm: cross ex, ebreakm_set; - ebreak_in_debug : cross ex, dm; - endgroup - - // Cover that we execute c.ebreak with dcsr.ebreakm==1 - covergroup cg_cebreak_execute_with_ebreakm; - `per_instance_fcov - ex: coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { - bins active = {1}; - } - ebreakm_set: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { - bins active = {1}; - } - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins active = {1}; - } - cebreak_with_ebreakm: cross ex, ebreakm_set; - cebreak_in_debug : cross ex, dm; - endgroup - - // Cover that we execute ebreak with dcsr.ebreakm==0 - covergroup cg_ebreak_execute_without_ebreakm; - `per_instance_fcov - ex: coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { - bins active = {1}; - } - ebreakm_clear: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { - bins active = {0}; - } - step: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] { - bins active = {1}; - } - nostep: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] { - bins active = {0}; - } - ebreak_regular_nodebug: cross ex, ebreakm_clear, nostep; - ebreak_step_nodebug : cross ex, ebreakm_clear, step; - endgroup - - // Cover that we execute c.ebreak with dcsr.ebreakm==0 - covergroup cg_cebreak_execute_without_ebreakm; - `per_instance_fcov - ex: coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { - bins active = {1}; - } - ebreakm_clear: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[15] { - bins active = {0}; - } - step: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] { - bins active = {1}; - } - nostep: coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] { - bins active = {0}; - } - cebreak_regular_nodebug: cross ex, ebreakm_clear, nostep; - cebreak_step_nodebug : cross ex, ebreakm_clear, step; - endgroup - - // Cover that we hit a trigger match - covergroup cg_trigger_match; - `per_instance_fcov - en : coverpoint cntxt.debug_cov_vif.mon_cb.tdata1[2] { - bins active = {1}; - } - match: coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_in_wb { - //TODO:ropeders should use the wb_valid-qualified "is_trigger_match"? - bins hit = {1}; - } - ok_match: cross en, match; - endgroup - - // cover that we hit pc==tdata2 without having enabled trigger in m/d-mode - // cover hit in d-mode with trigger enabled (no action) - covergroup cg_trigger_match_disabled; - `per_instance_fcov - dis : coverpoint cntxt.debug_cov_vif.mon_cb.tdata1[2] { - bins hit = {0}; - } - en : coverpoint cntxt.debug_cov_vif.mon_cb.tdata1[2] { - bins hit = {1}; - } - match: coverpoint cntxt.debug_cov_vif.mon_cb.addr_match { - bins hit = {1}; - } - mmode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins m = {0}; - } - dmode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins m = {1}; - } - m_match_without_en : cross dis, match, mmode; - d_match_without_en : cross dis, match, dmode; - d_match_with_en : cross en, match, dmode; - endgroup - - // Cover that we hit an exception during debug mode - covergroup cg_debug_mode_exception; - `per_instance_fcov - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins hit = {1}; - } - ill : coverpoint (cntxt.debug_cov_vif.mon_cb.illegal_insn_i && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; - } - ex_in_debug : cross dm, ill; - endgroup - - // Cover that we hit an ecall during debug mode - covergroup cg_debug_mode_ecall; - `per_instance_fcov - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins hit = {1}; - } - ill : coverpoint cntxt.debug_cov_vif.mon_cb.sys_ecall_insn_i { - bins hit = {1}; - } - ex_in_debug : cross dm, ill; - endgroup - - // Cover that we get interrupts while in debug mode - covergroup cg_irq_in_debug; - `per_instance_fcov - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins hit = {1}; - } - irq : coverpoint |cntxt.debug_cov_vif.mon_cb.irq_i { - bins hit = {1}; - } - ex_in_debug : cross dm, irq; - endgroup - - // Cover that hit a WFI insn in debug mode - covergroup cg_wfi_in_debug; - `per_instance_fcov - iswfi : coverpoint cntxt.debug_cov_vif.mon_cb.is_wfi { - bins hit = {1}; - } - dm : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins hit = {1}; - } - dm_wfi : cross iswfi, dm; - endgroup - - // Cover that we get a debug_req while in wfi - covergroup cg_wfi_debug_req; - `per_instance_fcov - inwfi : coverpoint cntxt.debug_cov_vif.mon_cb.in_wfi { - bins hit = {1}; - } - dreq: coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { - bins hit = {1}; - } - dm_wfi : cross inwfi, dreq; - endgroup - - // Cover that we perform single stepping - covergroup cg_single_step; - `per_instance_fcov - step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] { - bins en = {1}; - } - mmode: coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins hit = {0}; - } - trigger : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_in_wb { - bins hit = {1}; - } - wfi : coverpoint cntxt.debug_cov_vif.mon_cb.is_wfi { - bins hit = {1}; - } - ill : coverpoint (cntxt.debug_cov_vif.mon_cb.illegal_insn_i && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; - } - pc_will_trig : coverpoint cntxt.debug_cov_vif.mon_cb.dpc_will_hit { - bins hit = {1}; - } - stepie : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[11]; - mmode_step : cross step, mmode; - mmode_step_trigger_match : cross step, mmode, trigger; - mmode_step_wfi : cross step, mmode, wfi; - mmode_step_stepie : cross step, mmode, stepie; - mmode_step_illegal : cross step, mmode, ill; - mmode_step_next_pc_will_match : cross step, mmode, pc_will_trig; - endgroup - - // Cover dret is executed in machine mode - covergroup cg_mmode_dret; - `per_instance_fcov - mmode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q; - dret_ins : coverpoint cntxt.debug_cov_vif.mon_cb.is_dret { - bins hit = {1}; - } - dret_ex : cross mmode, dret_ins; - endgroup - - // Cover debug_req and irq asserted on same cycle - covergroup cg_irq_dreq; - `per_instance_fcov - dreq : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { - bins trans_active = (1'b0 => 1'b1); - } - irq : coverpoint |cntxt.debug_cov_vif.mon_cb.irq_i { - bins trans_active = (1'b0 => 1'b1); - } - trigger : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_in_wb { - bins hit = {1}; - } - ill : coverpoint (cntxt.debug_cov_vif.mon_cb.illegal_insn_i && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; - } - ebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { - bins active= {1'b1}; - } - cebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { - bins active= {1'b1}; - } - branch : coverpoint cntxt.debug_cov_vif.mon_cb.branch_in_ex { - bins active= {1'b1}; - } - mulhsu : coverpoint cntxt.debug_cov_vif.mon_cb.is_mulhsu { - bins active= {1'b1}; - } - dreq_and_ill : cross dreq, ill; - irq_and_dreq : cross dreq, irq; - irq_dreq_trig_ill : cross dreq, irq, trigger, ill; - irq_dreq_trig_cebreak : cross dreq, irq, trigger, cebreak; - irq_dreq_trig_ebreak : cross dreq, irq, trigger, ebreak; - irq_dreq_trig_branch : cross dreq, irq, trigger, branch; - irq_dreq_trig_multicycle : cross dreq, irq, trigger, mulhsu; - endgroup - - // Cover access to dcsr, dpc and dscratch0/1 in D-mode - covergroup cg_debug_regs_d_mode; - `per_instance_fcov - mode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins M = {1}; - } - access : coverpoint (cntxt.debug_cov_vif.mon_cb.csr_access && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; - } - op : coverpoint cntxt.debug_cov_vif.mon_cb.csr_op { - bins read = {'h0}; - bins write = {'h1}; - // TODO:ropeders also SET and CLEAR? - } - addr : coverpoint cntxt.debug_cov_vif.mon_cb.wb_stage_instr_rdata_i[31:20] { // csr addr not updated if illegal access - bins dcsr = {'h7B0}; - bins dpc = {'h7B1}; - bins dscratch0 = {'h7B2}; - bins dscratch1 = {'h7B3}; - } - dregs_access : cross mode, access, op, addr; - endgroup - - // Cover access to dcsr, dpc and dscratch0/1 in M-mode - covergroup cg_debug_regs_m_mode; - `per_instance_fcov - mode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins M = {0}; - } - access : coverpoint (cntxt.debug_cov_vif.mon_cb.csr_access && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; - } - op : coverpoint cntxt.debug_cov_vif.mon_cb.csr_op { - bins read = {1'h0}; - bins write = {1'h1}; - // TODO:ropeders also SET and CLEAR? - } - addr : coverpoint cntxt.debug_cov_vif.mon_cb.wb_stage_instr_rdata_i[31:20] { // csr addr not updated if illegal access - bins dcsr = {'h7B0}; - bins dpc = {'h7B1}; - bins dscratch0 = {'h7B2}; - bins dscratch1 = {'h7B3}; - } - dregs_access : cross mode, access, op, addr; - endgroup - - // Cover access to trigger registers - // TODO Do we need to cover all READ/WRITE/SET/CLEAR from m-mode? - covergroup cg_trigger_regs; - `per_instance_fcov - mode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q; // Only M and D supported - access : coverpoint (cntxt.debug_cov_vif.mon_cb.csr_access && cntxt.debug_cov_vif.mon_cb.wb_valid) { - bins hit = {1}; - } - op : coverpoint cntxt.debug_cov_vif.mon_cb.csr_op { - bins read = {'h0}; - bins write = {'h1}; - } - addr : coverpoint cntxt.debug_cov_vif.mon_cb.wb_stage_instr_rdata_i[31:20] { // csr addr not updated if illegal access - bins tsel = {'h7A0}; - bins tdata1 = {'h7A1}; - bins tdata2 = {'h7A2}; - bins tdata3 = {'h7A3}; - bins tinfo = {'h7A4}; - } - tregs_access : cross mode, access, op, addr; - endgroup - - // Cover that we run with counters mcycle and minstret enabled - covergroup cg_counters_enabled; - `per_instance_fcov - mcycle_en : coverpoint cntxt.debug_cov_vif.mon_cb.mcountinhibit_q[0]; - minstret_en : coverpoint cntxt.debug_cov_vif.mon_cb.mcountinhibit_q[2]; - endgroup - - // Cover that we get a debug_req_i while in RESET state - covergroup cg_debug_at_reset; - `per_instance_fcov - state : coverpoint cntxt.debug_cov_vif.mon_cb.ctrl_fsm_cs { - bins reset= {cv32e40x_pkg::RESET}; - } - dbg : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { - bins active= {1'b1}; - } - dbg_at_reset : cross state, dbg; - endgroup - - // Cover that we execute fence and fence.i in debug mode - covergroup cg_fence_in_debug; - `per_instance_fcov - mode : coverpoint cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins debug= {1'b1}; - } - fence : coverpoint cntxt.debug_cov_vif.mon_cb.sys_fence_insn_i { - bins active= {1'b1}; - } - fence_in_debug : cross mode, fence; - endgroup - - // Cover that we get all combinations of debug causes - covergroup cg_debug_causes; - `per_instance_fcov - tmatch : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_in_wb { - bins match= {1'b1}; - } - tnomatch : coverpoint cntxt.debug_cov_vif.mon_cb.trigger_match_in_wb { - bins nomatch= {1'b0}; - } - ebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_ebreak { - bins active= {1'b1}; - } - cebreak : coverpoint cntxt.debug_cov_vif.mon_cb.is_cebreak { - bins active= {1'b1}; - } - dbg_req : coverpoint cntxt.debug_cov_vif.mon_cb.debug_req_i { - bins active= {1'b1}; - } - step : coverpoint cntxt.debug_cov_vif.mon_cb.dcsr_q[2] & !cntxt.debug_cov_vif.mon_cb.debug_mode_q { - bins active= {1'b1}; - } - trig_vs_ebreak : cross tmatch, ebreak; - trig_vs_cebreak : cross tmatch, cebreak; - trig_vs_dbg_req : cross tmatch, dbg_req; - trig_vs_step : cross tmatch, step; - // Excluding trigger match to check 'lower' priority causes - ebreak_vs_req : cross ebreak, dbg_req, tnomatch; - cebreak_vs_req : cross cebreak, dbg_req, tnomatch; - ebreak_vs_step : cross ebreak, step; - cebreak_cs_step : cross cebreak, step; - dbg_req_vs_step : cross dbg_req, step; - endgroup - -endclass : uvme_debug_covg - -function uvme_debug_covg::new(string name = "debug_covg", uvm_component parent = null); - super.new(name, parent); - - cg_debug_mode_ext = new(); - cg_ebreak_execute_with_ebreakm = new(); - cg_cebreak_execute_with_ebreakm = new(); - cg_ebreak_execute_without_ebreakm = new(); - cg_cebreak_execute_without_ebreakm = new(); - cg_trigger_match = new(); - cg_trigger_match_disabled = new(); - cg_debug_mode_exception = new(); - cg_debug_mode_ecall = new(); - cg_irq_in_debug = new(); - cg_wfi_in_debug = new(); - cg_wfi_debug_req = new(); - cg_single_step = new(); - cg_mmode_dret = new(); - cg_irq_dreq = new(); - cg_debug_regs_d_mode = new(); - cg_debug_regs_m_mode = new(); - cg_trigger_regs = new(); - cg_counters_enabled = new(); - cg_debug_at_reset = new(); - cg_fence_in_debug = new(); - cg_debug_causes = new(); -endfunction : new - -function void uvme_debug_covg::build_phase(uvm_phase phase); - super.build_phase(phase); - - void'(uvm_config_db#(uvme_cv32e40x_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (cntxt == null) begin - `uvm_fatal("DEBUGCOVG", "No cntxt object passed to model"); - end -endfunction : build_phase - -task uvme_debug_covg::run_phase(uvm_phase phase); - super.run_phase(phase); - - `uvm_info("DEBUGCOVG", "The debug coverage model is running", UVM_LOW); - - fork - sample_debug_req_i(); - sample_clk_i(); - join_none -endtask : run_phase - -task uvme_debug_covg::sample_debug_req_i(); - while(1) begin - @(posedge cntxt.debug_cov_vif.mon_cb.debug_req_i); - - cg_debug_mode_ext.sample(); - end -endtask : sample_debug_req_i - -task uvme_debug_covg::sample_clk_i(); - while (1) begin - @(cntxt.debug_cov_vif.mon_cb); - - cg_ebreak_execute_with_ebreakm.sample(); - cg_cebreak_execute_with_ebreakm.sample(); - cg_ebreak_execute_without_ebreakm.sample(); - cg_cebreak_execute_without_ebreakm.sample(); - cg_trigger_match.sample(); - cg_trigger_match_disabled.sample(); - cg_debug_mode_exception.sample(); - cg_debug_mode_ecall.sample(); - cg_irq_in_debug.sample(); - cg_wfi_in_debug.sample(); - cg_wfi_debug_req.sample(); - cg_single_step.sample(); - cg_mmode_dret.sample(); - cg_irq_dreq.sample(); - cg_debug_regs_d_mode.sample(); - cg_debug_regs_m_mode.sample(); - cg_trigger_regs.sample(); - cg_counters_enabled.sample(); - cg_debug_at_reset.sample(); - cg_fence_in_debug.sample(); - cg_debug_causes.sample(); - end -endtask : sample_clk_i diff --git a/cv32e40x/env/uvme/cov/uvme_exceptions_covg.sv b/cv32e40x/env/uvme/cov/uvme_exceptions_covg.sv deleted file mode 100644 index 710a4e9aa9..0000000000 --- a/cv32e40x/env/uvme/cov/uvme_exceptions_covg.sv +++ /dev/null @@ -1,116 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - - -covergroup cg_exceptions - with function sample(uvma_isacov_mon_trn_c isacov); - - `per_instance_fcov - - cp_trap : coverpoint isacov.instr.rvfi.trap { - bins trap = {1}; - } - cp_intr : coverpoint isacov.instr.rvfi.intr { - bins intr = {1}; - } - cp_imm12 : coverpoint isacov.instr.csr_val { - bins imm12[16] = {[0:$]}; - bins msb = {12'h 800}; - bins lsb = {12'h 001}; - } - cp_is_csr : coverpoint (isacov.instr.group == CSR_GROUP) { - bins is_csr = {1}; - } - cp_is_ebreak : coverpoint (isacov.instr.name inside {EBREAK, C_EBREAK}) { - bins is_ebreak = {1}; - } - cp_no_ebreakm : coverpoint (isacov.instr.rvfi.csrs["dcsr"].get_csr_retirement_data()[15]) { - bins no_ebreakm = {0}; - } - cp_mcause : coverpoint isacov.instr.rvfi.csrs["mcause"].get_csr_retirement_data() { - bins reset = {0}; - bins ins_acc_fault = {1}; - bins illegal_ins = {2}; - bins breakpoint = {3}; - bins load_acc_fault = {5}; - bins store_amo_acc_fault = {7}; - bins ecall = {11}; - bins ins_bus_fault = {48}; - } - cp_pcr_mtvec : coverpoint (isacov.instr.rvfi.pc_rdata[31:2] == isacov.instr.rvfi.csrs["mtvec"].get_csr_retirement_data()[31:2]) { - bins one = {1}; - } - cp_pcw_mtvec : coverpoint (isacov.instr.rvfi.pc_wdata[31:2] == isacov.instr.rvfi.csrs["mtvec"].get_csr_retirement_data()[31:2]) { - bins one = {1}; - } - - cross_all_csrs : cross cp_imm12, cp_is_csr; // CSR instructions shall try all 2^12 existing/nonexisting CSRs - cross_trap_to_mtvec : cross cp_trap, cp_pcw_mtvec; // Trap going to mtvec.base - cross_trap_in_mtvec : cross cp_intr, cp_pcr_mtvec; // Trap executing at mtvec.base - cross_ebreak_trap : cross cp_is_ebreak, cp_no_ebreakm, cp_trap, cp_mcause { - ignore_bins ig = ! binsof(cp_mcause) intersect {3}; // Shall hit specifically mcause == breakpoint - } - // TODO:ropeders cross mcause==3 and cp for instr/data trigger match with action==0 - cross_trap_mcause : cross cp_trap, cp_mcause { - ignore_bins ig = binsof(cp_mcause) intersect {0}; // Can't trap with mcause == reset value - } - cross_intr_mcause : cross cp_intr, cp_mcause { - ignore_bins ig = binsof(cp_mcause) intersect {0}; // Can't trap with mcause == reset value - } - -endgroup : cg_exceptions - - -class uvme_exceptions_covg extends uvm_component; - - `uvm_analysis_imp_decl(_isacov) - - cg_exceptions exceptions_cg; - uvm_analysis_imp_isacov#(uvma_isacov_mon_trn_c, uvme_exceptions_covg) isacov_mon_export; - - `uvm_component_utils(uvme_exceptions_covg); - - extern function new(string name = "exceptions_covg", uvm_component parent = null); - extern function void build_phase(uvm_phase phase); - extern function void write_isacov(uvma_isacov_mon_trn_c isacov); - -endclass : uvme_exceptions_covg - - -function uvme_exceptions_covg::new(string name = "exceptions_covg", uvm_component parent = null); - - super.new(name, parent); - - isacov_mon_export = new("isacov_mon_export", this); - -endfunction : new - - -function void uvme_exceptions_covg::build_phase(uvm_phase phase); - - super.build_phase(phase); - - exceptions_cg = new(); - -endfunction : build_phase - - -function void uvme_exceptions_covg::write_isacov(uvma_isacov_mon_trn_c isacov); - - exceptions_cg.sample(isacov); - -endfunction : write_isacov diff --git a/cv32e40x/env/uvme/cov/uvme_interrupt_covg.sv b/cv32e40x/env/uvme/cov/uvme_interrupt_covg.sv deleted file mode 100644 index 7ecb188faa..0000000000 --- a/cv32e40x/env/uvme/cov/uvme_interrupt_covg.sv +++ /dev/null @@ -1,232 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// Copyright 2020 OpenHW Group -// Copyright 2020 BTA Design Services -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// -/////////////////////////////////////////////////////////////////////////////// - -`uvm_analysis_imp_decl(_interrupt) -`uvm_analysis_imp_decl(_instr) - -/* -* Covergroups -*/ -covergroup cg_irq_entry(string name, - bit ext_m_supported, - bit ext_c_supported, - bit ext_zba_supported, - bit ext_zbb_supported, - bit ext_zbc_supported, - bit ext_zbs_supported, - bit ext_a_supported) -with function sample(uvma_isacov_instr_c instr); - option.name = name; - `per_instance_fcov - cp_irq : coverpoint(instr.name) { - `ISACOV_IGN_BINS - // These instructions will enter the exception handler which will gate off any interrupts - // by disabling MSIE immediately upon execution - ignore_bins ebreak_excp = { EBREAK }; - ignore_bins c_ebreak_excp = { C_EBREAK }; - ignore_bins ecal_excp = { ECALL }; - } -endgroup : cg_irq_entry - -covergroup cg_wfi_entry(string name, - bit ext_m_supported, - bit ext_c_supported, - bit ext_zba_supported, - bit ext_zbb_supported, - bit ext_zbc_supported, - bit ext_zbs_supported, - bit ext_a_supported) -with function sample(uvma_isacov_instr_c instr); - option.name = name; - `per_instance_fcov - cp_wfi : coverpoint instr.name { - `ISACOV_IGN_BINS - } -endgroup : cg_wfi_entry - -covergroup cg_irq_exit(string name, - bit ext_m_supported, - bit ext_c_supported, - bit ext_zba_supported, - bit ext_zbb_supported, - bit ext_zbc_supported, - bit ext_zbs_supported, - bit ext_a_supported) -with function sample(uvma_isacov_instr_c instr); - option.name = name; - `per_instance_fcov - cp_irq : coverpoint instr.name { - `ISACOV_IGN_BINS - // Should not exit an IRQ into an MRET (usually interrupts are disabled at end of ISR) - ignore_bins mret_excp = { MRET }; - // Should not exit an IRQ into a DRET - ignore_bins dret_excp = { DRET }; - } -endgroup : cg_irq_exit - -covergroup cg_wfi_exit(string name, - bit ext_m_supported, - bit ext_c_supported, - bit ext_zba_supported, - bit ext_zbb_supported, - bit ext_zbc_supported, - bit ext_zbs_supported, - bit ext_a_supported) -with function sample(uvma_isacov_instr_c instr); - option.name = name; - `per_instance_fcov - cp_wfi : coverpoint instr.name { - `ISACOV_IGN_BINS - } -endgroup : cg_wfi_exit - -class uvme_interrupt_covg extends uvm_component; - - /* - * Class members - */ - - uvma_core_cntrl_cfg_c cfg; - - int unsigned irq_nested_count; // Count interrupt entry count for functional coverage - - uvma_isacov_mon_trn_c last_instr_trn; - - cg_irq_entry irq_entry_cg; - cg_wfi_entry wfi_entry_cg; - cg_irq_exit irq_exit_cg; - cg_wfi_exit wfi_exit_cg; - - uvm_analysis_imp_interrupt#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN), uvme_interrupt_covg) interrupt_mon_export; - uvm_analysis_imp_instr#(uvma_isacov_mon_trn_c, uvme_interrupt_covg) instr_mon_export; - - `uvm_component_utils(uvme_interrupt_covg); - - extern function new(string name = "interrupt_covg", uvm_component parent = null); - extern function void build_phase(uvm_phase phase); - extern task run_phase(uvm_phase phase); - - extern function void write_interrupt(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) trn); - extern function void write_instr(uvma_isacov_mon_trn_c trn); - -endclass : uvme_interrupt_covg - -function uvme_interrupt_covg::new(string name = "interrupt_covg", uvm_component parent = null); - - super.new(name, parent); - - irq_nested_count = 0; - - - interrupt_mon_export = new("interrupt_mon_export", this); - instr_mon_export = new("instr_mon_export", this); - -endfunction : new - -function void uvme_interrupt_covg::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvma_core_cntrl_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) begin - `uvm_fatal("CFG", "Configuration handle is null") - end - - irq_entry_cg = new("irq_entry", - .ext_m_supported(cfg.ext_m_supported), - .ext_c_supported(cfg.ext_c_supported), - .ext_zba_supported(cfg.ext_zba_supported), - .ext_zbb_supported(cfg.ext_zbb_supported), - .ext_zbc_supported(cfg.ext_zbc_supported), - .ext_zbs_supported(cfg.ext_zbs_supported), - .ext_a_supported(cfg.ext_a_supported)); - - wfi_entry_cg = new("wfi_entry", - .ext_m_supported(cfg.ext_m_supported), - .ext_c_supported(cfg.ext_c_supported), - .ext_zba_supported(cfg.ext_zba_supported), - .ext_zbb_supported(cfg.ext_zbb_supported), - .ext_zbc_supported(cfg.ext_zbc_supported), - .ext_zbs_supported(cfg.ext_zbs_supported), - .ext_a_supported(cfg.ext_a_supported)); - - irq_exit_cg = new("irq_exit", - .ext_m_supported(cfg.ext_m_supported), - .ext_c_supported(cfg.ext_c_supported), - .ext_zba_supported(cfg.ext_zba_supported), - .ext_zbb_supported(cfg.ext_zbb_supported), - .ext_zbc_supported(cfg.ext_zbc_supported), - .ext_zbs_supported(cfg.ext_zbs_supported), - .ext_a_supported(cfg.ext_a_supported)); - - wfi_exit_cg = new("wfi_exit", - .ext_m_supported(cfg.ext_m_supported), - .ext_c_supported(cfg.ext_c_supported), - .ext_zba_supported(cfg.ext_zba_supported), - .ext_zbb_supported(cfg.ext_zbb_supported), - .ext_zbc_supported(cfg.ext_zbc_supported), - .ext_zbs_supported(cfg.ext_zbs_supported), - .ext_a_supported(cfg.ext_a_supported)); - -endfunction : build_phase - -task uvme_interrupt_covg::run_phase(uvm_phase phase); - - super.run_phase(phase); - - `uvm_info("INTERRUPTCOVG", "The interrupt coverage model is running", UVM_LOW); - -endtask : run_phase - -function void uvme_interrupt_covg::write_interrupt(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) trn); - - if (trn.intr == 1 && last_instr_trn != null) begin - `uvm_info("INTERRUPTCOVG", $sformatf("IRQ entered from %s", last_instr_trn.instr.name.name()), UVM_DEBUG) - irq_entry_cg.sample(last_instr_trn.instr); - irq_nested_count++; - end - -endfunction : write_interrupt - -function void uvme_interrupt_covg::write_instr(uvma_isacov_mon_trn_c trn); - - // If this is a WFI, then sample the last instruction - if (trn.instr.name == WFI && last_instr_trn != null) begin - wfi_entry_cg.sample(last_instr_trn.instr); - end - - // If last instruction was WFI, then sample exit WFI coverage - if (last_instr_trn != null && last_instr_trn.instr.name == WFI) begin - `uvm_info("INTERRUPTCOVG", $sformatf("WFI Exit: instruction is %s", trn.instr.name.name()), UVM_DEBUG) - wfi_exit_cg.sample(trn.instr); - end - - // For each mret decrement the interrupt count - if (last_instr_trn != null && last_instr_trn.instr.name == MRET && irq_nested_count) begin - `uvm_info("INTERRUPTCOVG", $sformatf("IRQ exited to %s", trn.instr.name.name()), UVM_DEBUG) - irq_exit_cg.sample(trn.instr); - irq_nested_count--; - end - - // When an instruction is sampled, just save the handle here - // It will be sampled when an interrupt or wfi event occurs - last_instr_trn = trn; - -endfunction : write_instr diff --git a/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_agent.sv b/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_agent.sv deleted file mode 100644 index 40bd7a9534..0000000000 --- a/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_agent.sv +++ /dev/null @@ -1,117 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - -`ifndef __UVMA_CV32E40X_CORE_CNTRL_AGENT_SV__ -`define __UVMA_CV32E40X_CORE_CNTRL_AGENT_SV__ - -/** - * Core control agent defined for the CV32E40X - */ -class uvma_cv32e40x_core_cntrl_agent_c extends uvma_core_cntrl_agent_c; - - - string log_tag = "CV32E40XCORECTRLAGT"; - - `uvm_component_utils_begin(uvma_cv32e40x_core_cntrl_agent_c) - `uvm_component_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvma_cv32e40x_core_cntrl_agent", uvm_component parent=null); - - /** - * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. - */ - extern virtual function void get_and_set_cntxt(); - - /** - * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this - * agent. - */ - extern virtual function void retrieve_vif(); - - /** - * Spawn active sequnces - */ - extern virtual task run_phase(uvm_phase phase); - - /** - * Spawn fetch enable control sequence - */ - extern virtual task start_fetch_toggle_seq(); - -endclass : uvma_cv32e40x_core_cntrl_agent_c - -function uvma_cv32e40x_core_cntrl_agent_c::new(string name="uvma_cv32e40x_core_cntrl_agent", uvm_component parent=null); - - super.new(name, parent); - - set_inst_override_by_type("driver", uvma_core_cntrl_drv_c::get_type(), uvma_cv32e40x_core_cntrl_drv_c::get_type()); - -endfunction : new - -function void uvma_cv32e40x_core_cntrl_agent_c::retrieve_vif(); - - uvma_cv32e40x_core_cntrl_cntxt_c e40x_cntxt; - - $cast(e40x_cntxt, cntxt); - - // Core control interface - if (!uvm_config_db#(virtual uvme_cv32e40x_core_cntrl_if)::get(this, "", $sformatf("core_cntrl_vif"), e40x_cntxt.core_cntrl_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", - $typename(e40x_cntxt.core_cntrl_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", - $typename(e40x_cntxt.core_cntrl_vif)), UVM_DEBUG) - end -endfunction : retrieve_vif - -function void uvma_cv32e40x_core_cntrl_agent_c::get_and_set_cntxt(); - - void'(uvm_config_db#(uvma_core_cntrl_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (!cntxt) begin - `uvm_info(log_tag, "Context handle is null; creating", UVM_LOW); - cntxt = uvma_cv32e40x_core_cntrl_cntxt_c::type_id::create("cntxt"); - end - - uvm_config_db#(uvma_core_cntrl_cntxt_c)::set(this, "*", "cntxt", cntxt); - -endfunction : get_and_set_cntxt - -task uvma_cv32e40x_core_cntrl_agent_c::run_phase(uvm_phase phase); - - if (cfg.is_active) begin - fork - start_fetch_toggle_seq(); - join_none - end - -endtask : run_phase - -task uvma_cv32e40x_core_cntrl_agent_c::start_fetch_toggle_seq(); - - uvme_cv32e40x_fetch_toggle_seq_c fetch_toggle_seq = uvme_cv32e40x_fetch_toggle_seq_c::type_id::create("fetch_toggle_seq"); - void'(fetch_toggle_seq.randomize()); - fetch_toggle_seq.start(this.sequencer); - -endtask : start_fetch_toggle_seq - -`endif // __UVMA_CV32E40X_CORE_CNTRL_AGENT_SV__ diff --git a/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_drv.sv b/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_drv.sv deleted file mode 100644 index fe0cf6cea3..0000000000 --- a/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_drv.sv +++ /dev/null @@ -1,63 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -`ifndef __UVMA_CV32E40X_CORE_CNTRL_DRV_SV__ -`define __UVMA_CV32E40X_CORE_CNTRL_DRV_SV__ - -/** - * Component driving bootstrap pins and other misecllaneous I/O for cv32e40x core - */ -class uvma_cv32e40x_core_cntrl_drv_c extends uvma_core_cntrl_drv_c; - - `uvm_component_utils_begin(uvma_cv32e40x_core_cntrl_drv_c) - `uvm_component_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvma_cv32e40x_core_cntrl_drv", uvm_component parent=null); - - extern task drive_bootstrap(); - -endclass : uvma_cv32e40x_core_cntrl_drv_c - -function uvma_cv32e40x_core_cntrl_drv_c::new(string name="uvma_cv32e40x_core_cntrl_drv", uvm_component parent=null); - - super.new(name, parent); - -endfunction : new - -task uvma_cv32e40x_core_cntrl_drv_c::drive_bootstrap(); - - uvma_cv32e40x_core_cntrl_cntxt_c e40x_cntxt; - - $cast(e40x_cntxt, cntxt); - - e40x_cntxt.core_cntrl_vif.boot_addr = cfg.boot_addr; - e40x_cntxt.core_cntrl_vif.nmi_addr = cfg.nmi_addr; - e40x_cntxt.core_cntrl_vif.mtvec_addr = cfg.mtvec_addr; - e40x_cntxt.core_cntrl_vif.dm_halt_addr = cfg.dm_halt_addr; - e40x_cntxt.core_cntrl_vif.dm_exception_addr = cfg.dm_exception_addr; - e40x_cntxt.core_cntrl_vif.mhartid = cfg.mhartid; - e40x_cntxt.core_cntrl_vif.mimpid = cfg.mimpid; - e40x_cntxt.core_cntrl_vif.fetch_en = 1'b0; - e40x_cntxt.core_cntrl_vif.scan_cg_en = 1'b0; - -endtask : drive_bootstrap - -`endif // __UVMA_CV32E40X_CORE_CNTRL_DRV_SV__ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_buserr_sb.sv b/cv32e40x/env/uvme/uvme_cv32e40x_buserr_sb.sv deleted file mode 100644 index 93ae803b61..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_buserr_sb.sv +++ /dev/null @@ -1,294 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - - -`ifndef __UVME_CV32E40X_BUSERR_SB_SV__ -`define __UVME_CV32E40X_BUSERR_SB_SV__ - - -`uvm_analysis_imp_decl(_obid) // D-side OBI -`uvm_analysis_imp_decl(_obii) // I-side OBI -`uvm_analysis_imp_decl(_rvfi) - - -// Class: uvme_cv32e40x_buserr_sb_c -// A scoreboard to check that OBI "err" bus faults arrive at the RVFI. -// For I-side "err"s, the main mode of checking is to store every err-flagged -// OBI transaction in a queue, and then compare the PC addresses of RVFI -// retires to see that they have the expected impact. -// For D-side "err"s, the main mode of checking is to watch for the first "err" -// (in, potentially, a series of "err"s) and demand that no more than two -// RVFI retires (non-debug/step) happen before we must enter the NMI handler. -// There are also a couple of other checks to see if all counts are as expected. -class uvme_cv32e40x_buserr_sb_c extends uvm_scoreboard; - - string info_tag = "BUSERRSB"; - - uvm_analysis_imp_obid#(uvma_obi_memory_mon_trn_c, uvme_cv32e40x_buserr_sb_c) obid; - uvm_analysis_imp_obii#(uvma_obi_memory_mon_trn_c, uvme_cv32e40x_buserr_sb_c) obii; - uvm_analysis_imp_rvfi#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN), uvme_cv32e40x_buserr_sb_c) rvfi; - - // OBI D-side variables: - int cnt_obid_trn; // Count of all obi d-side transactions - int cnt_obid_err; // Count of all d-side "err" transactions - int cnt_obid_firsterr; // Count of all first d-side "err", in case of multiple "err" before handler "taken" - // OBI I-side variables: - int cnt_obii_trn; // Count of all obi i-side transactions - int cnt_obii_err; // Count of all i-side "err" transactions - // RVFI variables: - int cnt_rvfi_trn; // Count of all rvfi transactions - int cnt_rvfi_nmihandl; // Count of all nmi handler entries - int cnt_rvfi_ifaulthandl; // Count of all instr bus fault handler entries - int cnt_rvfi_errmatch; // Count of all retires matched with expected I-side "err" - int cnt_rvfi_errmatch_debug; // Count of all errmatch that happens under debug - // Expectations variables: - bit pending_nmi; // Whether nmi happened and handler is expected - int late_retires; // Number of non-debug/step/handler retires since "pending_nmi" - uvma_obi_memory_mon_trn_c obii_err_queue[$]; // All I-side OBI trns last seen with "err" - - `uvm_component_utils(uvme_cv32e40x_buserr_sb_c) - - extern function new(string name="uvme_cv32e40x_buserr_sb", uvm_component parent=null); - extern virtual function void write_obid(uvma_obi_memory_mon_trn_c trn); - extern virtual function void write_obii(uvma_obi_memory_mon_trn_c trn); - extern virtual function void write_rvfi(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) trn); - extern virtual function void build_phase(uvm_phase phase); - extern virtual function void check_phase(uvm_phase phase); - extern function bit should_instr_err(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_trn); - extern function void remove_from_err_queue(uvma_obi_memory_mon_trn_c trn); - extern function void add_to_err_queue(uvma_obi_memory_mon_trn_c trn); - -endclass : uvme_cv32e40x_buserr_sb_c - - -function uvme_cv32e40x_buserr_sb_c::new(string name="uvme_cv32e40x_buserr_sb", uvm_component parent=null); - - super.new(name, parent); - -endfunction : new - - -function void uvme_cv32e40x_buserr_sb_c::write_obid(uvma_obi_memory_mon_trn_c trn); - - cnt_obid_trn++; - - if (trn.err) begin - cnt_obid_err++; - - if (!pending_nmi) begin - cnt_obid_firsterr++; - pending_nmi = 1; - end - end - -endfunction : write_obid - - -function void uvme_cv32e40x_buserr_sb_c::write_obii(uvma_obi_memory_mon_trn_c trn); - - cnt_obii_trn++; - - if (trn.err) begin - cnt_obii_err++; - add_to_err_queue(trn); - end else begin - // Acquit this address, as it was (re)fetched wo/ err - remove_from_err_queue(trn); - end - -endfunction : write_obii - - -function void uvme_cv32e40x_buserr_sb_c::write_rvfi(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) trn); - - bit [31:0] mcause = trn.csrs["mcause"].rdata; - bit [31:0] dcsr = trn.csrs["dcsr"].get_csr_retirement_data; - bit step = dcsr[2]; - bit stepie = dcsr[11]; - - cnt_rvfi_trn++; - - // Expected ifault retires - if (should_instr_err(trn)) begin - cnt_rvfi_errmatch++; - - //TODO:mateilga remove this separate counter when RVFI is updated with an intr cause field - if (trn.dbg_mode) begin - cnt_rvfi_errmatch_debug++; - end - - assert (trn.trap) - else `uvm_error(info_tag, $sformatf("retire at 0x%08x (expected 'err') lacks 'rvfi_trap'", trn.pc_rdata)); - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) - cnt_rvfi_ifaulthandl <= 1) - else `uvm_error(info_tag, "too many err retires without ifault handling"); - end - - // D-side NMI handler - //TODO:mateilga update this to check the new intr cause field when RVFI is updated - if (trn.intr && mcause[31] && (mcause[30:0] inside {128, 129})) begin - cnt_rvfi_nmihandl++; - - assert (pending_nmi) - else `uvm_error(info_tag, "nmi handlered entered without sb having seen an 'err' on d-bus"); - pending_nmi = 0; - - assert (cnt_obid_firsterr == cnt_rvfi_nmihandl) - else `uvm_error(info_tag, "expected D-bus 'err' count equal to handler entry count"); - end - - // I-side exception handler - //TODO:mateilga update this to check the new intr cause field when RVFI is updated. This will allow for counting handler entries during debug - if (trn.intr && !mcause[31] && (mcause[31:0] == 48)) begin - cnt_rvfi_ifaulthandl++; - - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) == cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, "ifault handler entered without matching an ifault retirement"); - end - - // Retires after D-side "first err" - if (pending_nmi && !trn.dbg_mode && !(step && !stepie)) begin - late_retires++; - assert (late_retires <= 2 + 1) // "+1" is for the "rvfi_valid" that belongs to before the nmi - else `uvm_error(info_tag, "more than 2 instructions retired before the nmi was taken"); - end - if (!pending_nmi) begin - late_retires = 0; - end - -endfunction : write_rvfi - - -function void uvme_cv32e40x_buserr_sb_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - obid = new("obid", this); - obii = new("obii", this); - rvfi = new("rvfi", this); - -endfunction : build_phase - - -function void uvme_cv32e40x_buserr_sb_c::check_phase(uvm_phase phase); - - super.check_phase(phase); - - // Check OBI D-side - assert (cnt_obid_trn > 0) - else `uvm_warning(info_tag, "zero D-side OBI transactions received"); - assert (cnt_obid_trn >= cnt_obid_err) - else `uvm_error(info_tag, "obid 'err' transactions counted wrong"); - assert (cnt_obid_trn != cnt_obid_err) - else `uvm_warning(info_tag, "all the D-side OBI transactions were errs"); - assert (cnt_obid_err >= cnt_obid_firsterr) - else `uvm_error(info_tag, "obid 'first' transactions counted wrong"); - assert (!(cnt_obid_err && !cnt_obid_firsterr)) - else `uvm_error(info_tag, "'first' errs counted wrong"); - - // Check RVFI D-side - assert (cnt_rvfi_trn >= cnt_rvfi_nmihandl) - else `uvm_error(info_tag, "rvfi 'nmi' transactions counted wrong"); - assert (cnt_rvfi_trn != cnt_rvfi_nmihandl) - else `uvm_error(info_tag, "all the rvfi transactions where nmi entries"); - - // Check OBI D-side vs RVFI - assert (cnt_obid_firsterr inside {cnt_rvfi_nmihandl, cnt_rvfi_nmihandl + 1}) - else `uvm_error(info_tag, $sformatf("more/less 'err' (%0d) than nmi handling (%0d)", cnt_obid_firsterr, cnt_rvfi_nmihandl)); - - // Check OBI I-side - assert (cnt_obii_trn > 0) - else `uvm_warning(info_tag, "zero I-side OBI transactions received"); - assert (cnt_obii_trn >= cnt_obii_err) - else `uvm_error(info_tag, "obii 'err' transactions counted wrong"); - assert (cnt_obii_trn != cnt_obii_err) - else `uvm_warning(info_tag, "all the I-side OBI transactions were errs"); - - // Check RVFI I-side - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) >= cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, "more instr fault handler than actual err retirements"); - assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) == cnt_rvfi_ifaulthandl) - else `uvm_warning(info_tag, $sformatf("err retires (%0d) != handler entries (%0d)", (cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug), cnt_rvfi_ifaulthandl)); - - // Check OBI I-side vs RVFI - assert (cnt_obii_err >= cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, $sformatf("less I-side err (%0d) than exception handling (%0d)", cnt_obii_err, cnt_rvfi_ifaulthandl)); - assert (cnt_obii_err >= cnt_rvfi_errmatch) - else `uvm_warning(info_tag, "more retired errs than fetches"); - - // Check RVFI (just a sanity check) - assert (cnt_rvfi_trn > 0) - else `uvm_warning(info_tag, "zero rvfi transactions received"); - - // Inform about the end state - `uvm_info(info_tag, $sformatf("received %0d D-side 'err' transactions", cnt_obid_err), UVM_NONE) - `uvm_info(info_tag, $sformatf("received %0d D-side 'first err' transactions", cnt_obid_firsterr), UVM_NONE) - `uvm_info(info_tag, $sformatf("observed %0d rvfi nmi handler entries", cnt_rvfi_nmihandl), UVM_NONE) - `uvm_info(info_tag, $sformatf("received %0d I-side 'err' transactions", cnt_obii_err), UVM_NONE) - `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions", cnt_rvfi_errmatch), UVM_NONE) - `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions during debug", cnt_rvfi_errmatch_debug), UVM_NONE) - `uvm_info(info_tag, $sformatf("observed %0d rvfi ifault handler entries", cnt_rvfi_ifaulthandl), UVM_NONE) - -endfunction : check_phase - - -function bit uvme_cv32e40x_buserr_sb_c::should_instr_err(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_trn); - - uvma_obi_memory_addr_l_t err_addrs[$]; - bit [31:0] rvfi_addr = rvfi_trn.pc_rdata; - - // Extract all addrs from queue of I-side OBI "err" transactions - foreach (obii_err_queue[i]) begin - err_addrs[i] = obii_err_queue[i].address; - end - - foreach (err_addrs[i]) begin - bit compressed = - (rvfi_trn.insn[1:0] != 2'b 11) - && !({rvfi_addr[31:2], 2'b 00} inside {err_addrs}); - bit [31:0] hi_addr = err_addrs[i] + 4; - bit [31:0] lo_addr = err_addrs[i] - (compressed ? 2 : 4); - - if ((lo_addr < rvfi_addr) && (rvfi_addr < hi_addr)) begin - return 1; - end - end - return 0; // No match found, rvfi trn not expected to have "err" - -endfunction : should_instr_err - - -function void uvme_cv32e40x_buserr_sb_c::remove_from_err_queue(uvma_obi_memory_mon_trn_c trn); - - foreach (obii_err_queue[i]) begin - if (obii_err_queue[i].address == trn.address) begin - obii_err_queue.delete(i); - return; - end - end - -endfunction : remove_from_err_queue - - -function void uvme_cv32e40x_buserr_sb_c::add_to_err_queue(uvma_obi_memory_mon_trn_c trn); - - remove_from_err_queue(trn); // (In case of old entry w/ same addr) - obii_err_queue.push_back(trn); - -endfunction : add_to_err_queue - - -`endif // __UVME_CV32E40X_BUSERR_SB_SV__ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_cfg.sv b/cv32e40x/env/uvme/uvme_cv32e40x_cfg.sv deleted file mode 100644 index bd2b7a7bae..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_cfg.sv +++ /dev/null @@ -1,436 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_CFG_SV__ -`define __UVME_CV32E40X_CFG_SV__ - - -/** - * Object encapsulating all parameters for creating, connecting and running - * CV32E40X environment (uvme_cv32e40x_env_c) components. - */ -class uvme_cv32e40x_cfg_c extends uvma_core_cntrl_cfg_c; - - // Integrals - rand int unsigned sys_clk_period; - cv32e40x_pkg::b_ext_e b_ext; - bit obi_memory_instr_random_err_enabled = 0; - bit obi_memory_instr_one_shot_err_enabled = 0; - bit obi_memory_data_random_err_enabled = 0; - bit obi_memory_data_one_shot_err_enabled = 0; - rand bit buserr_scoreboarding_enabled = 1; - - // Agent cfg handles - rand uvma_isacov_cfg_c isacov_cfg; - rand uvma_clknrst_cfg_c clknrst_cfg; - rand uvma_interrupt_cfg_c interrupt_cfg; - rand uvma_debug_cfg_c debug_cfg; - rand uvma_obi_memory_cfg_c obi_memory_instr_cfg; - rand uvma_obi_memory_cfg_c obi_memory_data_cfg; - rand uvma_fencei_cfg_c fencei_cfg; - rand uvma_rvfi_cfg_c#(ILEN,XLEN) rvfi_cfg; - rand uvma_rvvi_cfg_c#(ILEN,XLEN) rvvi_cfg; - rand uvma_pma_cfg_c#(ILEN,XLEN) pma_cfg; - - `uvm_object_utils_begin(uvme_cv32e40x_cfg_c) - `uvm_field_int ( enabled , UVM_DEFAULT ) - `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT ) - `uvm_field_int ( cov_model_enabled , UVM_DEFAULT ) - `uvm_field_int ( trn_log_enabled , UVM_DEFAULT ) - `uvm_field_int ( buserr_scoreboarding_enabled, UVM_DEFAULT ) - `uvm_field_int ( sys_clk_period , UVM_DEFAULT | UVM_DEC) - `uvm_field_enum (cv32e40x_pkg::b_ext_e, b_ext , UVM_DEFAULT ) - `uvm_field_int ( obi_memory_instr_random_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_instr_one_shot_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_data_random_err_enabled, UVM_DEFAULT ) - `uvm_field_int ( obi_memory_data_one_shot_err_enabled, UVM_DEFAULT ) - - `uvm_field_object(isacov_cfg , UVM_DEFAULT) - `uvm_field_object(clknrst_cfg , UVM_DEFAULT) - `uvm_field_object(interrupt_cfg , UVM_DEFAULT) - `uvm_field_object(debug_cfg , UVM_DEFAULT) - `uvm_field_object(obi_memory_instr_cfg , UVM_DEFAULT) - `uvm_field_object(obi_memory_data_cfg , UVM_DEFAULT) - `uvm_field_object(rvfi_cfg , UVM_DEFAULT) - `uvm_field_object(rvvi_cfg , UVM_DEFAULT) - `uvm_field_object(fencei_cfg , UVM_DEFAULT) - `uvm_field_object(pma_cfg , UVM_DEFAULT) - `uvm_object_utils_end - - - constraint defaults_cons { - soft enabled == 0; - soft is_active == UVM_PASSIVE; - soft scoreboarding_enabled == 1; - soft cov_model_enabled == 1; - soft trn_log_enabled == 1; - soft sys_clk_period == uvme_cv32e40x_sys_default_clk_period; // see uvme_cv32e40x_constants.sv - soft buserr_scoreboarding_enabled == 1; - } - - constraint cv32e40x_riscv_cons { - xlen == uvma_core_cntrl_pkg::MXL_32; - ilen == 32; - - ext_i_supported == 1; - ext_c_supported == 1; - ext_m_supported == 1; - ext_zifencei_supported == 1; - ext_zicsr_supported == 1; - ext_a_supported == 0; - ext_p_supported == 0; - ext_v_supported == 0; - ext_f_supported == 0; - ext_d_supported == 0; - - if (b_ext == cv32e40x_pkg::B_NONE) { - ext_zba_supported == 0; - ext_zbb_supported == 0; - ext_zbc_supported == 0; - ext_zbs_supported == 0; - } else if (b_ext == cv32e40x_pkg::ZBA_ZBB_ZBS) { - ext_zba_supported == 1; - ext_zbb_supported == 1; - ext_zbc_supported == 0; - ext_zbs_supported == 1; - } else if (b_ext == cv32e40x_pkg::ZBA_ZBB_ZBC_ZBS) { - ext_zba_supported == 1; - ext_zbb_supported == 1; - ext_zbc_supported == 1; - ext_zbs_supported == 1; - } - ext_zbe_supported == 0; - ext_zbf_supported == 0; - ext_zbm_supported == 0; - ext_zbp_supported == 0; - ext_zbr_supported == 0; - ext_zbt_supported == 0; - - mode_s_supported == 0; - mode_u_supported == 0; - pmp_supported == 0; - debug_supported == 1; - - unaligned_access_supported == 1; - unaligned_access_amo_supported == 1; - - bitmanip_version == BITMANIP_VERSION_1P00; - priv_spec_version == PRIV_VERSION_MASTER; - endianness == ENDIAN_LITTLE; - - boot_addr_valid == 1; - mtvec_addr_valid == 1; - dm_halt_addr_valid == 1; - dm_exception_addr_valid == 1; - nmi_addr_valid == 1; - } - - constraint default_cv32e40x_boot_cons { - (!mhartid_plusarg_valid) -> (mhartid == 'h0000_0000); - (!mimpid_plusarg_valid) -> (mimpid == 'h0000_0000); - (!boot_addr_plusarg_valid) -> (boot_addr == 'h0000_0080); - (!mtvec_addr_plusarg_valid) -> (mtvec_addr == 'h0000_0000); - (!nmi_addr_plusarg_valid) -> (nmi_addr == 'h0010_0000); - (!dm_halt_addr_plusarg_valid) -> (dm_halt_addr == 'h1a11_0800); - (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h1a11_1000); - } - - constraint agent_cfg_cons { - if (enabled) { - clknrst_cfg.enabled == 1; - interrupt_cfg.enabled == 1; - debug_cfg.enabled == 1; - rvfi_cfg.enabled == 1; - rvvi_cfg.enabled == use_iss; - obi_memory_instr_cfg.enabled == 1; - obi_memory_data_cfg.enabled == 1; - fencei_cfg.enabled == 1; - } - - obi_memory_instr_cfg.version == UVMA_OBI_MEMORY_VERSION_1P2; - obi_memory_instr_cfg.drv_mode == UVMA_OBI_MEMORY_MODE_SLV; - obi_memory_instr_cfg.write_enabled == 0; - obi_memory_instr_cfg.addr_width == XLEN; - obi_memory_instr_cfg.data_width == XLEN; - obi_memory_instr_cfg.id_width == 0; - obi_memory_instr_cfg.achk_width == 0; - obi_memory_instr_cfg.rchk_width == 0; - obi_memory_instr_cfg.auser_width == 0; - obi_memory_instr_cfg.ruser_width == 0; - obi_memory_instr_cfg.wuser_width == 0; - soft obi_memory_instr_cfg.drv_slv_gnt_random_latency_max <= 3; - soft obi_memory_instr_cfg.drv_slv_rvalid_random_latency_max <= 6; - - obi_memory_data_cfg.version == UVMA_OBI_MEMORY_VERSION_1P2; - obi_memory_data_cfg.drv_mode == UVMA_OBI_MEMORY_MODE_SLV; - obi_memory_data_cfg.addr_width == XLEN; - obi_memory_data_cfg.data_width == XLEN; - obi_memory_data_cfg.id_width == 0; - obi_memory_data_cfg.achk_width == 0; - obi_memory_data_cfg.rchk_width == 0; - obi_memory_data_cfg.auser_width == 0; - obi_memory_data_cfg.ruser_width == 0; - obi_memory_data_cfg.wuser_width == 0; - soft obi_memory_data_cfg.drv_slv_gnt_random_latency_max <= 3; - soft obi_memory_data_cfg.drv_slv_rvalid_random_latency_max <= 6; - - isacov_cfg.enabled == 1; - isacov_cfg.seq_instr_group_x2_enabled == 1; - isacov_cfg.seq_instr_group_x3_enabled == 1; - isacov_cfg.seq_instr_group_x4_enabled == 0; - isacov_cfg.seq_instr_x2_enabled == 1; - isacov_cfg.reg_crosses_enabled == 0; - isacov_cfg.reg_hazards_enabled == 1; - - rvfi_cfg.nret == uvme_cv32e40x_pkg::RVFI_NRET; - rvfi_cfg.nmi_load_fault_enabled == 1; - rvfi_cfg.nmi_load_fault_cause == cv32e40x_pkg::INT_CAUSE_LSU_LOAD_FAULT; - rvfi_cfg.nmi_store_fault_enabled == 1; - rvfi_cfg.nmi_store_fault_cause == cv32e40x_pkg::INT_CAUSE_LSU_STORE_FAULT; - rvfi_cfg.insn_bus_fault_enabled == 1; - rvfi_cfg.insn_bus_fault_cause == cv32e40x_pkg::EXC_CAUSE_INSTR_BUS_FAULT; - - if (is_active == UVM_ACTIVE) { - isacov_cfg.is_active == UVM_PASSIVE; - clknrst_cfg.is_active == UVM_ACTIVE; - interrupt_cfg.is_active == UVM_ACTIVE; - debug_cfg.is_active == UVM_ACTIVE; - obi_memory_instr_cfg.is_active == UVM_ACTIVE; - obi_memory_data_cfg.is_active == UVM_ACTIVE; - rvfi_cfg.is_active == UVM_PASSIVE; - rvvi_cfg.is_active == UVM_ACTIVE; - fencei_cfg.is_active == UVM_ACTIVE; - } - - if (trn_log_enabled) { - // Setting a reasonable set of logs - clknrst_cfg.trn_log_enabled == 0; - debug_cfg.trn_log_enabled == 0; - interrupt_cfg.trn_log_enabled == 0; - isacov_cfg.trn_log_enabled == 0; - obi_memory_data_cfg.trn_log_enabled == 1; - obi_memory_instr_cfg.trn_log_enabled == 1; - rvfi_cfg.trn_log_enabled == 1; - rvvi_cfg.trn_log_enabled == 1; - } else { - clknrst_cfg.trn_log_enabled == 0; - debug_cfg.trn_log_enabled == 0; - interrupt_cfg.trn_log_enabled == 0; - isacov_cfg.trn_log_enabled == 0; - obi_memory_data_cfg.trn_log_enabled == 0; - obi_memory_instr_cfg.trn_log_enabled == 0; - rvfi_cfg.trn_log_enabled == 0; - rvvi_cfg.trn_log_enabled == 0; - } - - if (cov_model_enabled) { - isacov_cfg.cov_model_enabled == 1; - debug_cfg.cov_model_enabled == 1; - pma_cfg.cov_model_enabled == 1; - obi_memory_instr_cfg.cov_model_enabled == 1; - obi_memory_data_cfg.cov_model_enabled == 1; - } - - if (!scoreboarding_enabled) { - buserr_scoreboarding_enabled == 0; - pma_cfg.scoreboard_enabled == 0; - } - } - - constraint obi_memory_instr_fault_cons { - if (!obi_memory_instr_random_err_enabled) { - obi_memory_instr_cfg.drv_slv_err_mode == UVMA_OBI_MEMORY_DRV_SLV_ERR_MODE_OK; - } else { - obi_memory_instr_cfg.drv_slv_err_mode == UVMA_OBI_MEMORY_DRV_SLV_ERR_MODE_RANDOM; - obi_memory_instr_cfg.drv_slv_err_ok_wgt inside {[10:200]}; - obi_memory_instr_cfg.drv_slv_err_fault_wgt == 1; - } - - obi_memory_instr_cfg.drv_slv_err_one_shot_mode == obi_memory_instr_one_shot_err_enabled; - } - - constraint obi_memory_data_fault_cons { - if (!obi_memory_data_random_err_enabled) { - obi_memory_data_cfg.drv_slv_err_mode == UVMA_OBI_MEMORY_DRV_SLV_ERR_MODE_OK; - } else { - obi_memory_data_cfg.drv_slv_err_mode == UVMA_OBI_MEMORY_DRV_SLV_ERR_MODE_RANDOM; - obi_memory_data_cfg.drv_slv_err_ok_wgt inside {[10:200]}; - obi_memory_data_cfg.drv_slv_err_fault_wgt == 1; - } - - obi_memory_data_cfg.drv_slv_err_one_shot_mode == obi_memory_data_one_shot_err_enabled; - } - - /** - * Creates sub-configuration objects. - */ - extern function new(string name="uvme_cv32e40x_cfg"); - - /** - * Run before randomizing this class - */ - extern function void pre_randomize(); - - /** - * Run after randomizing this class - */ - extern function void post_randomize(); - - /** - * Sample the parameters of the DUT via the virtual interface in a context - */ - extern virtual function void sample_parameters(uvma_core_cntrl_cntxt_c cntxt); - - /** - * Detect if a CSR check is disabled - */ - extern virtual function bit is_csr_check_disabled(string name); - - /** - * Configure CSR checks in the scoreboard - */ - extern virtual function void configure_disable_csr_checks(); - -endclass : uvme_cv32e40x_cfg_c - -function uvme_cv32e40x_cfg_c::new(string name="uvme_cv32e40x_cfg"); - - super.new(name); - - core_name = "CV32E40X"; - - if ($test$plusargs("USE_ISS")) - use_iss = 1; - if ($test$plusargs("trn_log_disabled")) begin - trn_log_enabled = 0; - trn_log_enabled.rand_mode(0); - end - if ($test$plusargs("buserr_sb_disabled")) begin - buserr_scoreboarding_enabled = 0; - buserr_scoreboarding_enabled.rand_mode(0); - end - - if ($test$plusargs("obi_memory_instr_random_err")) - obi_memory_instr_random_err_enabled = 1; - if ($test$plusargs("obi_memory_instr_one_shot_err")) - obi_memory_instr_one_shot_err_enabled = 1; - if ($test$plusargs("obi_memory_data_random_err")) - obi_memory_data_random_err_enabled = 1; - if ($test$plusargs("obi_memory_data_one_shot_err")) - obi_memory_data_one_shot_err_enabled = 1; - - isacov_cfg = uvma_isacov_cfg_c::type_id::create("isacov_cfg"); - clknrst_cfg = uvma_clknrst_cfg_c::type_id::create("clknrst_cfg"); - interrupt_cfg = uvma_interrupt_cfg_c::type_id::create("interrupt_cfg"); - debug_cfg = uvma_debug_cfg_c ::type_id::create("debug_cfg"); - obi_memory_instr_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_instr_cfg"); - obi_memory_data_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_data_cfg" ); - rvfi_cfg = uvma_rvfi_cfg_c#(ILEN,XLEN)::type_id::create("rvfi_cfg"); - rvvi_cfg = uvma_rvvi_ovpsim_cfg_c#(ILEN,XLEN)::type_id::create("rvvi_cfg"); - fencei_cfg = uvma_fencei_cfg_c::type_id::create("fencei_cfg"); - pma_cfg = uvma_pma_cfg_c#(ILEN,XLEN)::type_id::create("pma_cfg"); - - obi_memory_instr_cfg.mon_logger_name = "OBII"; - obi_memory_data_cfg.mon_logger_name = "OBID"; - - isacov_cfg.core_cfg = this; - rvfi_cfg.core_cfg = this; - rvvi_cfg.core_cfg = this; - -endfunction : new - -function void uvme_cv32e40x_cfg_c::pre_randomize(); - - `uvm_info("CFG", $sformatf("Pre-randomize num_mhpmcounters = %0d", num_mhpmcounters), UVM_LOW); - -endfunction : pre_randomize - -function void uvme_cv32e40x_cfg_c::post_randomize(); - - super.post_randomize(); - - rvfi_cfg.instr_name[0] = "INSTR"; - - // Set volatile locations for virtual peripherals - rvvi_cfg.add_volatile_mem_addr_range(CV_VP_REGISTER_BASE, CV_VP_REGISTER_BASE + CV_VP_REGISTER_SIZE - 1); - - // Disable some CSR checks from all tests - configure_disable_csr_checks(); - -endfunction : post_randomize - -function void uvme_cv32e40x_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt); - - uvma_cv32e40x_core_cntrl_cntxt_c e40x_cntxt; - - if (!$cast(e40x_cntxt, cntxt)) begin - `uvm_fatal("SAMPLECNTXT", "Could not cast cntxt to uvma_cv32e40x_core_cntrl_cntxt_c"); - end - - num_mhpmcounters = e40x_cntxt.core_cntrl_vif.num_mhpmcounters; - pma_regions = new[e40x_cntxt.core_cntrl_vif.pma_cfg.size()]; - b_ext = e40x_cntxt.core_cntrl_vif.b_ext; - - foreach (pma_regions[i]) begin - pma_regions[i] = uvma_core_cntrl_pma_region_c::type_id::create($sformatf("pma_region%0d", i)); - pma_regions[i].word_addr_low = e40x_cntxt.core_cntrl_vif.pma_cfg[i].word_addr_low; - pma_regions[i].word_addr_high = e40x_cntxt.core_cntrl_vif.pma_cfg[i].word_addr_high; - pma_regions[i].main = e40x_cntxt.core_cntrl_vif.pma_cfg[i].main; - pma_regions[i].bufferable = e40x_cntxt.core_cntrl_vif.pma_cfg[i].bufferable; - pma_regions[i].cacheable = e40x_cntxt.core_cntrl_vif.pma_cfg[i].cacheable; - pma_regions[i].atomic = e40x_cntxt.core_cntrl_vif.pma_cfg[i].atomic; - end - - // Copy to the pma_configuration - pma_cfg.regions = new[pma_regions.size()]; - foreach (pma_cfg.regions[i]) - pma_cfg.regions[i] = pma_regions[i]; - -endfunction : sample_parameters - -function bit uvme_cv32e40x_cfg_c::is_csr_check_disabled(string name); - - // Fatal error if passed a CSR check which is non-existent - if (!csr_name2addr.exists(name)) begin - `uvm_fatal("CV32E40XCFG", $sformatf("CSR [%s] does not exist", name)); - end - - return disable_csr_check_mask[csr_name2addr[name]]; - -endfunction : is_csr_check_disabled - -function void uvme_cv32e40x_cfg_c::configure_disable_csr_checks(); - - // Not possible to test on a cycle-by-cycle basis - disable_csr_check("mip"); - - // These are not implemented in the ISS - disable_csr_check("mcycle"); - disable_csr_check("mcycleh"); - disable_csr_check("mtval"); - - for (int i = 3; i < 32; i++) begin - disable_csr_check($sformatf("mhpmcounter%0d", i)); - disable_csr_check($sformatf("mhpmcounter%0dh", i)); - disable_csr_check($sformatf("mhpmevent%0d", i)); - end -endfunction : configure_disable_csr_checks - - -`endif // __UVME_CV32E40X_CFG_SV__ - - diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_cntxt.sv b/cv32e40x/env/uvme/uvme_cv32e40x_cntxt.sv deleted file mode 100644 index ea04a58b52..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_cntxt.sv +++ /dev/null @@ -1,102 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_CNTXT_SV__ -`define __UVME_CV32E40X_CNTXT_SV__ - - -/** - * Object encapsulating all state variables for CV32E40X environment - * (uvme_cv32e40x_env_c) components. - */ -class uvme_cv32e40x_cntxt_c extends uvm_object; - - // Virtual interface for Debug coverage - virtual uvmt_cv32e40x_debug_cov_assert_if debug_cov_vif; - virtual uvmt_cv32e40x_vp_status_if vp_status_vif; ///< Virtual interface for Virtual Peripherals - virtual uvma_interrupt_if intr_vif ; ///< Virtual interface for interrupts - virtual uvma_debug_if debug_vif ; ///< Virtual interface for debug - - // Agent context handles - uvma_cv32e40x_core_cntrl_cntxt_c core_cntrl_cntxt; - uvma_clknrst_cntxt_c clknrst_cntxt; - uvma_interrupt_cntxt_c interrupt_cntxt; - uvma_debug_cntxt_c debug_cntxt; - uvma_obi_memory_cntxt_c obi_memory_instr_cntxt; - uvma_obi_memory_cntxt_c obi_memory_data_cntxt; - uvma_rvfi_cntxt_c#(ILEN,XLEN) rvfi_cntxt; - uvma_rvvi_cntxt_c#(ILEN,XLEN) rvvi_cntxt; - uvma_fencei_cntxt_c fencei_cntxt; - - // Memory modelling - rand uvml_mem_c mem; - - // Events - uvm_event sample_cfg_e; - uvm_event sample_cntxt_e; - - `uvm_object_utils_begin(uvme_cv32e40x_cntxt_c) - `uvm_field_object(core_cntrl_cntxt, UVM_DEFAULT) - `uvm_field_object(clknrst_cntxt, UVM_DEFAULT) - `uvm_field_object(interrupt_cntxt, UVM_DEFAULT) - `uvm_field_object(debug_cntxt , UVM_DEFAULT) - `uvm_field_object(obi_memory_instr_cntxt, UVM_DEFAULT) - `uvm_field_object(obi_memory_data_cntxt , UVM_DEFAULT) - `uvm_field_object(rvfi_cntxt, UVM_DEFAULT) - `uvm_field_object(rvvi_cntxt, UVM_DEFAULT) - `uvm_field_object(mem, UVM_DEFAULT) - - `uvm_field_event(sample_cfg_e , UVM_DEFAULT) - `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) - `uvm_object_utils_end - - constraint mem_cfg_cons { - mem.mem_default == MEM_DEFAULT_0; - } - - /** - * Builds events and sub-context objects. - */ - extern function new(string name="uvme_cv32e40x_cntxt"); - -endclass : uvme_cv32e40x_cntxt_c - - -function uvme_cv32e40x_cntxt_c::new(string name="uvme_cv32e40x_cntxt"); - - super.new(name); - - clknrst_cntxt = uvma_clknrst_cntxt_c::type_id::create("clknrst_cntxt"); - core_cntrl_cntxt = uvma_cv32e40x_core_cntrl_cntxt_c::type_id::create("core_cntrl_cntxt"); - debug_cntxt = uvma_debug_cntxt_c::type_id::create("debug_cntxt"); - fencei_cntxt = uvma_fencei_cntxt_c::type_id::create("fencei_cntxt"); - interrupt_cntxt = uvma_interrupt_cntxt_c::type_id::create("interrupt_cntxt"); - obi_memory_data_cntxt = uvma_obi_memory_cntxt_c::type_id::create("obi_memory_data_cntxt" ); - obi_memory_instr_cntxt = uvma_obi_memory_cntxt_c::type_id::create("obi_memory_instr_cntxt"); - rvfi_cntxt = uvma_rvfi_cntxt_c#(ILEN,XLEN)::type_id::create("rvfi_cntxt"); - rvvi_cntxt = uvma_rvvi_ovpsim_cntxt_c#(ILEN,XLEN)::type_id::create("rvvi_cntxt"); - - mem = uvml_mem_c#(XLEN)::type_id::create("mem"); - - sample_cfg_e = new("sample_cfg_e" ); - sample_cntxt_e = new("sample_cntxt_e"); - -endfunction : new - - -`endif // __UVME_CV32E40X_CNTXT_SV__ - diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_constants.sv b/cv32e40x/env/uvme/uvme_cv32e40x_constants.sv deleted file mode 100644 index 48c79e642c..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_constants.sv +++ /dev/null @@ -1,59 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_CONSTANTS_SV__ -`define __UVME_CV32E40X_CONSTANTS_SV__ - - -parameter uvme_cv32e40x_sys_default_clk_period = 1_500; // 10ns -parameter uvme_cv32e40x_debug_default_clk_period = 10_000; // 10ns - -// For RVFI/RVVI -parameter ILEN = 32; -parameter XLEN = 32; -parameter RVFI_NRET = 1; - -// Control how often to print core scoreboard checked heartbeat messages -parameter PC_CHECKED_HEARTBEAT = 10_000; - -// Map the virtual peripheral registers -parameter CV_VP_REGISTER_BASE = 32'h0080_0000; -parameter CV_VP_REGISTER_SIZE = 32'h0000_1000; - -parameter CV_VP_VIRTUAL_PRINTER_OFFSET = 32'h0000_0000; -parameter CV_VP_RANDOM_NUM_OFFSET = 32'h0000_0040; -parameter CV_VP_CYCLE_COUNTER_OFFSET = 32'h0000_0080; -parameter CV_VP_STATUS_FLAGS_OFFSET = 32'h0000_00c0; -parameter CV_VP_FENCEI_TAMPER_OFFSET = 32'h0000_0100; -parameter CV_VP_INTR_TIMER_OFFSET = 32'h0000_0140; -parameter CV_VP_DEBUG_CONTROL_OFFSET = 32'h0000_0180; -parameter CV_VP_OBI_SLV_RESP_OFFSET = 32'h0000_01c0; -parameter CV_VP_SIG_WRITER_OFFSET = 32'h0000_0200; - -parameter CV_VP_VIRTUAL_PRINTER_BASE = CV_VP_REGISTER_BASE + CV_VP_VIRTUAL_PRINTER_OFFSET; -parameter CV_VP_RANDOM_NUM_BASE = CV_VP_REGISTER_BASE + CV_VP_RANDOM_NUM_OFFSET; -parameter CV_VP_CYCLE_COUNTER_BASE = CV_VP_REGISTER_BASE + CV_VP_CYCLE_COUNTER_OFFSET; -parameter CV_VP_STATUS_FLAGS_BASE = CV_VP_REGISTER_BASE + CV_VP_STATUS_FLAGS_OFFSET; -parameter CV_VP_INTR_TIMER_BASE = CV_VP_REGISTER_BASE + CV_VP_INTR_TIMER_OFFSET; -parameter CV_VP_DEBUG_CONTROL_BASE = CV_VP_REGISTER_BASE + CV_VP_DEBUG_CONTROL_OFFSET; -parameter CV_VP_OBI_SLV_RESP_BASE = CV_VP_REGISTER_BASE + CV_VP_OBI_SLV_RESP_OFFSET; -parameter CV_VP_SIG_WRITER_BASE = CV_VP_REGISTER_BASE + CV_VP_SIG_WRITER_OFFSET; -parameter CV_VP_FENCEI_TAMPER_BASE = CV_VP_REGISTER_BASE + CV_VP_FENCEI_TAMPER_OFFSET; - -`endif // __UVME_CV32E40X_CONSTANTS_SV__ - - - diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_core_cntrl_if.sv b/cv32e40x/env/uvme/uvme_cv32e40x_core_cntrl_if.sv deleted file mode 100644 index 5076241710..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_core_cntrl_if.sv +++ /dev/null @@ -1,32 +0,0 @@ -/** - * Quasi-static core control signals. - */ -interface uvme_cv32e40x_core_cntrl_if - import uvm_pkg::*; - import cv32e40x_pkg::*; - (); - - logic clk; - logic fetch_en; - - logic scan_cg_en; - logic [31:0] boot_addr; - logic [31:0] mtvec_addr; - logic [31:0] dm_halt_addr; - logic [31:0] dm_exception_addr; - logic [31:0] nmi_addr; - logic [31:0] mhartid; - logic [31:0] mimpid; - - logic [31:0] num_mhpmcounters; - pma_region_t pma_cfg[]; - cv32e40x_pkg::b_ext_e b_ext; - - // Testcase asserts this to load memory (not really a core control signal) - logic load_instr_mem; - - clocking drv_cb @(posedge clk); - output fetch_en; - endclocking : drv_cb - -endinterface : uvme_cv32e40x_core_cntrl_if diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_core_sb.sv b/cv32e40x/env/uvme/uvme_cv32e40x_core_sb.sv deleted file mode 100644 index 2f92e24383..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_core_sb.sv +++ /dev/null @@ -1,387 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_CORE_SB_SV__ -`define __UVME_CV32E40X_CORE_SB_SV__ - -`uvm_analysis_imp_decl(_core_sb_rvfi_instr) -`uvm_analysis_imp_decl(_core_sb_rvvi_state) - -class uvme_cv32e40x_core_sb_c extends uvm_scoreboard; - - // Fail-safe to kill the test with fatal error if the reorder queue gets to a certain size - localparam RVFI_INSTR_REORDER_QUEUE_SIZE_LIMIT = 2; - localparam RVFI_INSTR_QUEUE_SIZE_LIMIT = 2; - - // Objects - uvme_cv32e40x_cfg_c cfg; - uvme_cv32e40x_cntxt_c cntxt; - - // State queues - uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr_q[$]; - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state_q[$]; - uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr_reorder_q[bit[uvma_rvfi_pkg::ORDER_WL-1:0]]; - - // State variables - int unsigned next_rvfi_order = 1; - int unsigned next_rvvi_order = 1; - - // Maintain copy of GPRs updated by RVFI, workaround for limitiation of RVVI to only - // report changed register writes (misses writes that do not actually change a value) - bit[XLEN-1:0] x[32]; - - // Check counters - int unsigned pc_checked_cnt; - int unsigned gpr_checked_cnt; - int unsigned csr_checked_cnt; - - // Analysis exports - uvm_analysis_imp_core_sb_rvfi_instr#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN), uvme_cv32e40x_core_sb_c) rvfi_instr_export; - uvm_analysis_imp_core_sb_rvvi_state#(uvma_rvvi_state_seq_item_c#(ILEN,XLEN), uvme_cv32e40x_core_sb_c) rvvi_state_export; - - `uvm_component_utils_begin(uvme_cv32e40x_core_sb_c) - `uvm_field_object(cfg , UVM_DEFAULT) - `uvm_field_object(cntxt, UVM_DEFAULT) - `uvm_component_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_core_sb", uvm_component parent=null); - - /** - * Create and configures sub-scoreboards via: - * 1. assign_cfg() - * 2. assign_cntxt() - * 3. create_sbs() - */ - extern virtual function void build_phase(uvm_phase phase); - - /** - * Main thread for the core scoreboard - */ - extern task run_phase(uvm_phase phase); - - /** - * Final state check for scoreboard - */ - extern function void check_phase(uvm_phase phase); - - /** - * Print out checked counters - */ - extern function void report_phase(uvm_phase phase); - - /** - * Print out checked counters when aborting test due to fatal or too many errors - */ - extern function void pre_abort(); - - /** - * Analysis port write from RVFI instruction retirement monitor - */ - extern virtual function void write_core_sb_rvfi_instr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr); - - /** - * Analysis port write from RVVI state monitor - */ - extern virtual function void write_core_sb_rvvi_state(uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - - /** - * Check a retired instruction from RVVI against RVFI - */ - extern virtual function void check_instr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - - /** - * Check a GPR - */ - extern virtual function void check_gpr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - - /** - * Check a CSR - */ - extern virtual function void check_csr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - - extern virtual function void check_instr_queue(); - - extern virtual function void print_instr_checked_stats(); - -endclass : uvme_cv32e40x_core_sb_c - - -function uvme_cv32e40x_core_sb_c::new(string name="uvme_cv32e40x_core_sb", uvm_component parent=null); - - super.new(name, parent); - - rvfi_instr_export = new("rvfi_instr_export", this); - rvvi_state_export = new("rvvi_state_export", this); -endfunction : new - -function void uvme_cv32e40x_core_sb_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvme_cv32e40x_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) begin - `uvm_fatal("CFG", "Configuration handle is null") - end - - void'(uvm_config_db#(uvme_cv32e40x_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (!cntxt) begin - `uvm_fatal("CNTXT", "Context handle is null") - end - -endfunction : build_phase - -task uvme_cv32e40x_core_sb_c::run_phase(uvm_phase phase); - -endtask : run_phase - -function void uvme_cv32e40x_core_sb_c::check_phase(uvm_phase phase); - - // RVFI Reorder Instruction queue must be complete at the end of the test - if (rvfi_instr_reorder_q.size()) begin - `uvm_error("CORESB", $sformatf("RVFI reorder instruction queue is not empty at end of test (size: %0d)", - rvfi_instr_reorder_q.size())); - end - - // RVFI Instruction and RVVI instruction queues must be complete at the end of the test - // Allow case where only single RVFI exists but RVVI has not finished yet - if (!(rvfi_instr_q.size() == 1 && rvvi_state_q.size() == 0)) begin - if (rvfi_instr_q.size()) begin - `uvm_error("CORESB", $sformatf("RVFI expected instruction queue is not empty at end of test (size: %0d)", - rvfi_instr_q.size())); - end - - // RVVI Instruction queue must be complete at the end of the test - if (rvvi_state_q.size()) begin - `uvm_error("CORESB", $sformatf("RVVI expected instruction queue is not empty at end of test (size: %0d)", - rvvi_state_q.size())); - end - end - -endfunction : check_phase - -function void uvme_cv32e40x_core_sb_c::report_phase(uvm_phase phase); - print_instr_checked_stats(); -endfunction : report_phase - -function void uvme_cv32e40x_core_sb_c::pre_abort(); - print_instr_checked_stats(); -endfunction : pre_abort - -function void uvme_cv32e40x_core_sb_c::print_instr_checked_stats(); - `uvm_info("CORESB", $sformatf("checked %0d instruction retirements", pc_checked_cnt), UVM_NONE); - `uvm_info("CORESB", $sformatf("checked %0d GPR updates", gpr_checked_cnt), UVM_NONE); - `uvm_info("CORESB", $sformatf("checked %0d CSRs", csr_checked_cnt), UVM_NONE); -endfunction : print_instr_checked_stats - -function void uvme_cv32e40x_core_sb_c::write_core_sb_rvfi_instr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr); - - // Skip if scoreboard disabled - if (!cfg.scoreboarding_enabled) - return; - - // If the next instruction's order field goes backward, then signal an error - if (rvfi_instr.order < next_rvfi_order) begin - `uvm_error("CORE_SB", $sformatf("Receied RVFI instruction with order fields less than expected, exp: %0d, insn.order: %0d", - next_rvfi_order, rvfi_instr.order)); - return; - end - - // If the next instruction's order field matches expected order, then add to queue - if (rvfi_instr.order == next_rvfi_order) begin - rvfi_instr_q.push_back(rvfi_instr); - next_rvfi_order++; - end - // Add to the reordering queue - else begin - // Error if the order entry already exists - if (rvfi_instr_reorder_q.exists(rvfi_instr.order)) begin - `uvm_error("CORE_SB", $sformatf("Received RVFI instruction %0d out of order, but reorder queue entry already exists", - rvfi_instr.order)); - return; - end - - rvfi_instr_reorder_q[rvfi_instr.order] = rvfi_instr; - end - - // Check if the hext ordered instruction is in the reorder queue - while (rvfi_instr_reorder_q.exists(next_rvfi_order)) begin - rvfi_instr_q.push_back(rvfi_instr_reorder_q[next_rvfi_order]); - rvfi_instr_reorder_q.delete(next_rvfi_order); - next_rvfi_order++; - end - - // Fatal check for reorder size limit - if (rvfi_instr_reorder_q.size() >= RVFI_INSTR_REORDER_QUEUE_SIZE_LIMIT) begin - `uvm_error("CORE_SB", $sformatf("The RVFI reorder instruction queue is too large, size: %0d, next_rvfi_order: %0d", - rvfi_instr_reorder_q.size(), next_rvfi_order)); - end - - // Fatal check for rvfi queue size limit - if (rvfi_instr_q.size() >= RVFI_INSTR_QUEUE_SIZE_LIMIT) begin - `uvm_error("CORE_SB", $sformatf("The RVFI instruction queue is too large, size: %0d, next_rvfi_order: %0d", - rvfi_instr_q.size(), next_rvfi_order)); - end - - check_instr_queue(); -endfunction : write_core_sb_rvfi_instr - -function void uvme_cv32e40x_core_sb_c::write_core_sb_rvvi_state(uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - if (!cfg.scoreboarding_enabled) - return; - - // Discard invalid RVVI state updates - if (!rvvi_state.valid) - return; - - // Validate against expected order - if (rvvi_state.order != next_rvvi_order) begin - `uvm_error("CORESB", $sformatf("Received RVVI out of order: %0d, exp_order, %0d", - rvvi_state.order, next_rvvi_order)); - return; - end - next_rvvi_order++; - - rvvi_state_q.push_back(rvvi_state); - - check_instr_queue(); - -endfunction : write_core_sb_rvvi_state - -function void uvme_cv32e40x_core_sb_c::check_instr_queue(); - - while (rvvi_state_q.size() && rvfi_instr_q.size()) begin - uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr = rvfi_instr_q.pop_front(); - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state = rvvi_state_q.pop_front(); - - // First check instruction - check_instr(rvfi_instr, rvvi_state); - - // Now check GPR state - check_gpr(rvfi_instr, rvvi_state); - - // Check CSRs - if (!cfg.disable_all_csr_checks) - check_csr(rvfi_instr, rvvi_state); - end - -endfunction : check_instr_queue - -function void uvme_cv32e40x_core_sb_c::check_instr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - - `uvm_info("CORE_SB", $sformatf("Check PC: %0d RVFI.size() = %0d, RVVI.size() = %0d", - pc_checked_cnt, rvfi_instr_q.size(), rvvi_state_q.size()), UVM_HIGH); - pc_checked_cnt++; - - - // CHECK: ORDER - if (rvfi_instr.order != rvvi_state.order) begin - `uvm_error("CORESB", $sformatf("ORDER mismatch, rvfi.order = %0d, rvvi.order = %0d", - rvfi_instr.order, rvvi_state.order)); - end - - // CHECK: PC - if (rvfi_instr.pc_rdata != rvvi_state.pc) begin - `uvm_error("CORESB", $sformatf("PC Mismatch, rvfi_order: %0d, rvvi_order: %0d, rvfi.pc = 0x%08x, rvvi.pc = 0x%08x", - rvfi_instr.order, rvvi_state.order, rvfi_instr.pc_rdata, rvvi_state.pc)); - end - - // CHECK: insn - if (!rvfi_instr.trap) begin - if (rvfi_instr.insn != rvvi_state.insn) begin - `uvm_error("CORESB", $sformatf("INSN Mismatch, order: %0d, rvfi.pc = 0x%08x, rvfi.insn = 0x%08x, rvvi.insn = 0x%08x", - rvfi_instr.order, rvfi_instr.pc_rdata, rvfi_instr.insn, rvvi_state.insn)); - end - end - - // Heartbeat message - if (pc_checked_cnt && ((pc_checked_cnt % PC_CHECKED_HEARTBEAT)== 0)) begin - `uvm_info("CORE_SB", $sformatf("Compared %0d instructions", pc_checked_cnt), UVM_LOW); - end - -endfunction : check_instr - -function void uvme_cv32e40x_core_sb_c::check_gpr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - - // gpt_checked_cnt represents the GPR "updates" checked, so skip writes to x0 - if (rvfi_instr.rd1_addr !=0 || rvfi_instr.rd2_addr != 0) - gpr_checked_cnt++; - - // Update the local register map - if (rvfi_instr.rd1_addr != 0) - x[rvfi_instr.rd1_addr] = rvfi_instr.rd1_wdata; - if (rvfi_instr.rd2_addr != 0) - x[rvfi_instr.rd2_addr] = rvfi_instr.rd2_wdata; - - for (int i = 0; i < 32; i++) begin - if (x[i] != rvvi_state.x[i]) begin - `uvm_error("CORESB", $sformatf("GPR Mismatch, order: %0d, pc: 0x%08x, rvfi_x[%0d] = 0x%08x, rvvi_x[%0d] = 0x%08x", - rvfi_instr.order, - rvfi_instr.pc_rdata, - i, x[i], - i, rvvi_state.x[i])); - end - end - -endfunction : check_gpr - -function void uvme_cv32e40x_core_sb_c::check_csr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr, - uvma_rvvi_state_seq_item_c#(ILEN,XLEN) rvvi_state); - - foreach (rvfi_instr.csrs[i]) begin - bit[XLEN-1:0] exp_csr_value; - bit[XLEN-1:0] csr_mask = {XLEN{1'b1}}; - string csr = rvfi_instr.csrs[i].csr; - - // Skip disabled CSR checks from configuration object - if (cfg.is_csr_check_disabled(csr)) continue; - - // Ensure that CSR from RVFI exists in the RVVI state object - if (!rvvi_state.csr.exists(csr)) begin - `uvm_fatal("CORESB", $sformatf("CSR %s from RVFI does not exist in RVVI state interface", csr)); - end - - // Adjust CSR mask - // Skip dcsr.nmip check in non-debug mode - if (csr == "dcsr" && !rvfi_instr.dbg_mode) begin - csr_mask[3] = 0; - end - - csr_checked_cnt++; - - exp_csr_value = rvfi_instr.csrs[i].get_csr_retirement_data(); - - if ((exp_csr_value & csr_mask) != rvvi_state.csr[csr]) begin - `uvm_error("CORESB", $sformatf("CSR Mismatch, order: %0d, pc: 0x%08x, csr: %s, rvfi = 0x%08x, rvvi = 0x%08x, mask = 0x%08x", - rvfi_instr.order, - rvfi_instr.pc_rdata, - csr, - exp_csr_value, - rvvi_state.csr[csr], - csr_mask)); - end - end - -endfunction : check_csr - -`endif // __UVME_CV32E40X_CORE_SB_SV_ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_env.sv b/cv32e40x/env/uvme/uvme_cv32e40x_env.sv deleted file mode 100644 index beed1211fb..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_env.sv +++ /dev/null @@ -1,511 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_ENV_SV__ -`define __UVME_CV32E40X_ENV_SV__ - - -/** - * Top-level component that encapsulates, builds and connects all other - * CV32E40X environment components. - */ -class uvme_cv32e40x_env_c extends uvm_env; - - // Objects - uvme_cv32e40x_cfg_c cfg; - uvme_cv32e40x_cntxt_c cntxt; - - // Components - uvme_cv32e40x_cov_model_c cov_model; - uvme_cv32e40x_prd_c predictor; - uvme_cv32e40x_sb_c sb; - uvme_cv32e40x_core_sb_c core_sb; - uvme_cv32e40x_buserr_sb_c buserr_sb; - uvme_cv32e40x_vsqr_c vsequencer; - - // Agents - uvma_cv32e40x_core_cntrl_agent_c core_cntrl_agent; - uvma_isacov_agent_c#(ILEN,XLEN) isacov_agent; - uvma_clknrst_agent_c clknrst_agent; - uvma_interrupt_agent_c interrupt_agent; - uvma_debug_agent_c debug_agent; - uvma_obi_memory_agent_c obi_memory_instr_agent; - uvma_obi_memory_agent_c obi_memory_data_agent ; - uvma_rvfi_agent_c#(ILEN,XLEN) rvfi_agent; - uvma_rvvi_agent_c#(ILEN,XLEN) rvvi_agent; - uvma_fencei_agent_c fencei_agent; - uvma_pma_agent_c#(ILEN,XLEN) pma_agent; - - `uvm_component_utils_begin(uvme_cv32e40x_env_c) - `uvm_field_object(cfg , UVM_DEFAULT) - `uvm_field_object(cntxt, UVM_DEFAULT) - `uvm_component_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_env", uvm_component parent=null); - - /** - * 1. Ensures cfg & cntxt handles are not null - * 2. Assigns cfg and cntxt handles via assign_cfg() & assign_cntxt() - * 3. Builds all components via create_() - */ - extern virtual function void build_phase(uvm_phase phase); - - /** - * 1. Connects agents to predictor via connect_predictor() - * 3. Connects predictor & agents to scoreboard via connect_scoreboard() - * 4. Assembles virtual sequencer handles via assemble_vsequencer() - * 5. Connects agents to coverage model via connect_coverage_model() - */ - extern virtual function void connect_phase(uvm_phase phase); - - /** - * Print out final elaboration - */ - extern virtual function void end_of_elaboration_phase(uvm_phase phase); - - /** - * Creates and starts the instruction and virtual peripheral sequences in active mode. - */ - extern virtual task run_phase(uvm_phase phase); - - /** - * Get virtual interface handles from UVM Configuration Database. - */ - extern virtual function void retrieve_vifs(); - - /** - * Assigns configuration handles to components using UVM Configuration Database. - */ - extern virtual function void assign_cfg(); - - /** - * Assigns context handles to components using UVM Configuration Database. - */ - extern virtual function void assign_cntxt(); - - /** - * Creates agent components. - */ - extern virtual function void create_agents(); - - /** - * Creates additional (non-agent) environment components (and objects). - */ - extern virtual function void create_env_components(); - - /** - * Creates environment's virtual sequencer. - */ - extern virtual function void create_vsequencer(); - - /** - * Creates environment's coverage model. - */ - extern virtual function void create_cov_model(); - - /** - * Connects agents to predictor. - */ - extern virtual function void connect_predictor(); - - /** - * Connects the RVFI to the RVVI for step and compare feedback - */ - extern virtual function void connect_rvfi_rvvi(); - - /** - * Connects scoreboards components to agents/predictor. - */ - extern virtual function void connect_scoreboard(); - - /** - * Connects environment coverage model to agents/scoreboards/predictor. - */ - extern virtual function void connect_coverage_model(); - - /** - * Assembles virtual sequencer from agent sequencers. - */ - extern virtual function void assemble_vsequencer(); - - /** - * Install virtual peripheral sequences to the OBI data slave sequence - */ - extern virtual function void install_vp_register_seqs(uvma_obi_memory_slv_seq_c data_slv_seq); - -endclass : uvme_cv32e40x_env_c - - -function uvme_cv32e40x_env_c::new(string name="uvme_cv32e40x_env", uvm_component parent=null); - - super.new(name, parent); - -endfunction : new - - -function void uvme_cv32e40x_env_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvme_cv32e40x_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) begin - `uvm_fatal("CFG", "Configuration handle is null") - end - else begin - `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) - end - - if (cfg.enabled) begin - void'(uvm_config_db#(uvme_cv32e40x_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (!cntxt) begin - `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) - cntxt = uvme_cv32e40x_cntxt_c::type_id::create("cntxt"); - end - - cntxt.obi_memory_instr_cntxt.mem = cntxt.mem; - cntxt.obi_memory_data_cntxt.mem = cntxt.mem; - - retrieve_vifs (); - assign_cfg (); - assign_cntxt (); - create_agents (); - create_env_components(); - - if (cfg.is_active) begin - create_vsequencer(); - end - - if (cfg.cov_model_enabled) begin - create_cov_model(); - end - end - -endfunction : build_phase - -function void uvme_cv32e40x_env_c::connect_phase(uvm_phase phase); - - super.connect_phase(phase); - - if (cfg.enabled) begin - if (cfg.rvvi_cfg.is_active == UVM_ACTIVE) begin - uvma_rvvi_ovpsim_agent_c rvvi_ovpsim_agent; - - connect_rvfi_rvvi(); - if (!$cast(rvvi_ovpsim_agent, rvvi_agent)) begin - `uvm_fatal("UVMECV32E40XENV", "Could not cast agent to rvvi_ovpsim_agent"); - end - rvvi_ovpsim_agent.set_clknrst_sequencer(clknrst_agent.sequencer); - end - - if (cfg.scoreboarding_enabled) begin - connect_predictor (); - connect_scoreboard(); - end - - if (cfg.is_active) begin - assemble_vsequencer(); - end - - if (cfg.cov_model_enabled) begin - connect_coverage_model(); - end - end - -endfunction: connect_phase - - -function void uvme_cv32e40x_env_c::end_of_elaboration_phase(uvm_phase phase); - - super.end_of_elaboration_phase(phase); - -endfunction : end_of_elaboration_phase - -task uvme_cv32e40x_env_c::run_phase(uvm_phase phase); - - uvma_obi_memory_fw_preload_seq_c fw_preload_seq; - uvma_obi_memory_slv_seq_c instr_slv_seq; - uvma_obi_memory_slv_seq_c data_slv_seq; - - if (cfg.is_active) begin - fork - begin : spawn_obi_instr_fw_preload_thread - fw_preload_seq = uvma_obi_memory_fw_preload_seq_c::type_id::create("fw_preload_seq"); - void'(fw_preload_seq.randomize()); - fw_preload_seq.start(obi_memory_instr_agent.sequencer); - end - - begin : obi_instr_slv_thread - instr_slv_seq = uvma_obi_memory_slv_seq_c::type_id::create("instr_slv_seq"); - void'(instr_slv_seq.randomize()); - instr_slv_seq.start(obi_memory_instr_agent.sequencer); - end - - begin : obi_data_slv_thread - data_slv_seq = uvma_obi_memory_slv_seq_c::type_id::create("data_slv_seq"); - - install_vp_register_seqs(data_slv_seq); - - void'(data_slv_seq.randomize()); - data_slv_seq.start(obi_memory_data_agent.sequencer); - end - join_none - end - -endtask : run_phase - - -function void uvme_cv32e40x_env_c::retrieve_vifs(); - - if (!uvm_config_db#(virtual uvmt_cv32e40x_vp_status_if)::get(this, "", "vp_status_vif", cntxt.vp_status_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find vp_status_vif handle of type %s in uvm_config_db", $typename(cntxt.vp_status_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found vp_status_vif handle of type %s in uvm_config_db", $typename(cntxt.vp_status_vif)), UVM_DEBUG) - end - - if (!uvm_config_db#(virtual uvma_interrupt_if)::get(this, "", "intr_vif", cntxt.intr_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find intr_vif handle of type %s in uvm_config_db", $typename(cntxt.intr_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found intr_vif handle of type %s in uvm_config_db", $typename(cntxt.intr_vif)), UVM_DEBUG) - end - - if (!uvm_config_db#(virtual uvma_debug_if)::get(this, "", "debug_vif", cntxt.debug_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find debug_vif handle of type %s in uvm_config_db", $typename(cntxt.debug_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found debug_vif handle of type %s in uvm_config_db", $typename(cntxt.debug_vif)), UVM_DEBUG) - end - - void'(uvm_config_db#(virtual uvmt_cv32e40x_debug_cov_assert_if)::get(this, "", "debug_cov_vif", cntxt.debug_cov_vif)); - if (cntxt.debug_cov_vif == null) begin - `uvm_fatal("CNTXT", $sformatf("No uvmt_cv32e40x_debug_cov_assert_if found in config database")) - end - -endfunction: retrieve_vifs - -function void uvme_cv32e40x_env_c::assign_cfg(); - - uvm_config_db#(uvme_cv32e40x_cfg_c)::set(this, "*", "cfg", cfg); - - uvm_config_db#(uvma_clknrst_cfg_c)::set(this, "*clknrst_agent", "cfg", cfg.clknrst_cfg); - uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "*core_cntrl_agent", "cfg", cfg); - uvm_config_db#(uvma_debug_cfg_c)::set(this, "debug_agent", "cfg", cfg.debug_cfg); - uvm_config_db#(uvma_fencei_cfg_c)::set(this, "fencei_agent", "cfg", cfg.fencei_cfg); - uvm_config_db#(uvma_interrupt_cfg_c)::set(this, "*interrupt_agent", "cfg", cfg.interrupt_cfg); - uvm_config_db#(uvma_isacov_cfg_c)::set(this, "*isacov_agent", "cfg", cfg.isacov_cfg); - uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "obi_memory_data_agent", "cfg", cfg.obi_memory_data_cfg); - uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "obi_memory_instr_agent", "cfg", cfg.obi_memory_instr_cfg); - uvm_config_db#(uvma_pma_cfg_c)::set(this, "pma_agent", "cfg", cfg.pma_cfg); - uvm_config_db#(uvma_rvfi_cfg_c#(ILEN,XLEN))::set(this, "rvfi_agent", "cfg", cfg.rvfi_cfg); - uvm_config_db#(uvma_rvvi_cfg_c#(ILEN,XLEN))::set(this, "rvvi_agent", "cfg", cfg.rvvi_cfg); - -endfunction: assign_cfg - - -function void uvme_cv32e40x_env_c::assign_cntxt(); - - uvm_config_db#(uvme_cv32e40x_cntxt_c)::set(this, "*", "cntxt", cntxt); - - uvm_config_db#(uvma_clknrst_cntxt_c)::set(this, "clknrst_agent", "cntxt", cntxt.clknrst_cntxt); - //TODO core_cntrl_cntxt? - uvm_config_db#(uvma_debug_cntxt_c)::set(this, "debug_agent", "cntxt", cntxt.debug_cntxt); - uvm_config_db#(uvma_fencei_cntxt_c)::set(this, "fencei_agent", "cntxt", cntxt.fencei_cntxt); - uvm_config_db#(uvma_interrupt_cntxt_c)::set(this, "interrupt_agent", "cntxt", cntxt.interrupt_cntxt); - uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "obi_memory_data_agent", "cntxt", cntxt.obi_memory_data_cntxt); - uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "obi_memory_instr_agent", "cntxt", cntxt.obi_memory_instr_cntxt); - uvm_config_db#(uvma_rvfi_cntxt_c#(ILEN,XLEN))::set(this, "rvfi_agent", "cntxt", cntxt.rvfi_cntxt); - uvm_config_db#(uvma_rvvi_cntxt_c#(ILEN,XLEN))::set(this, "rvvi_agent", "cntxt", cntxt.rvvi_cntxt); - -endfunction: assign_cntxt - - -function void uvme_cv32e40x_env_c::create_agents(); - - core_cntrl_agent = uvma_cv32e40x_core_cntrl_agent_c::type_id::create("core_cntrl_agent", this); - isacov_agent = uvma_isacov_agent_c#(ILEN,XLEN)::type_id::create("isacov_agent", this); - clknrst_agent = uvma_clknrst_agent_c::type_id::create("clknrst_agent", this); - interrupt_agent = uvma_interrupt_agent_c::type_id::create("interrupt_agent", this); - debug_agent = uvma_debug_agent_c::type_id::create("debug_agent", this); - obi_memory_instr_agent = uvma_obi_memory_agent_c::type_id::create("obi_memory_instr_agent", this); - obi_memory_data_agent = uvma_obi_memory_agent_c::type_id::create("obi_memory_data_agent", this); - rvfi_agent = uvma_rvfi_agent_c#(ILEN,XLEN)::type_id::create("rvfi_agent", this); - rvvi_agent = uvma_rvvi_ovpsim_agent_c#(ILEN,XLEN)::type_id::create("rvvi_agent", this); - fencei_agent = uvma_fencei_agent_c::type_id::create("fencei_agent", this); - pma_agent = uvma_pma_agent_c#(ILEN,XLEN)::type_id::create("pma_agent", this); - -endfunction: create_agents - - -function void uvme_cv32e40x_env_c::create_env_components(); - - if (cfg.scoreboarding_enabled) begin - predictor = uvme_cv32e40x_prd_c::type_id::create("predictor", this); - sb = uvme_cv32e40x_sb_c::type_id::create("sb" , this); - core_sb = uvme_cv32e40x_core_sb_c::type_id::create("core_sb", this); - end - - if (cfg.buserr_scoreboarding_enabled) begin - buserr_sb = uvme_cv32e40x_buserr_sb_c::type_id::create("buserr_sb", this); - end - -endfunction: create_env_components - - -function void uvme_cv32e40x_env_c::create_vsequencer(); - - vsequencer = uvme_cv32e40x_vsqr_c::type_id::create("vsequencer", this); - -endfunction: create_vsequencer - -function void uvme_cv32e40x_env_c::create_cov_model(); - - cov_model = uvme_cv32e40x_cov_model_c::type_id::create("cov_model", this); - -endfunction: create_cov_model - - -function void uvme_cv32e40x_env_c::connect_predictor(); - -endfunction: connect_predictor - -function void uvme_cv32e40x_env_c::connect_rvfi_rvvi(); - - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(rvvi_agent.sequencer.rvfi_instr_export); - end - -endfunction : connect_rvfi_rvvi - -function void uvme_cv32e40x_env_c::connect_scoreboard(); - - // Connect the CORE Scoreboard (but only if the ISS is running) - if (cfg.use_iss) begin - rvvi_agent.state_mon_ap.connect(core_sb.rvvi_state_export); - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(core_sb.rvfi_instr_export); - end - end - - // Connect the bus error scoreboard - if (cfg.buserr_scoreboarding_enabled) begin - obi_memory_data_agent.mon_ap.connect(buserr_sb.obid); - obi_memory_instr_agent.mon_ap.connect(buserr_sb.obii); - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(buserr_sb.rvfi); - end - end - - // Connect the PMA scoreboard - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(pma_agent.scoreboard.rvfi_instr_export); - end - obi_memory_instr_agent.mon_ap.connect(pma_agent.scoreboard.obi_i_export); - obi_memory_data_agent.mon_ap.connect(pma_agent.scoreboard.obi_d_export); - -endfunction: connect_scoreboard - - -function void uvme_cv32e40x_env_c::connect_coverage_model(); - - isacov_agent.monitor.ap.connect(cov_model.exceptions_covg.isacov_mon_export); - isacov_agent.monitor.ap.connect(cov_model.counters_covg.isacov_mon_export); - - obi_memory_data_agent.mon_ap.connect(pma_agent.monitor.obi_d_export); - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(isacov_agent.monitor.rvfi_instr_export); - rvfi_agent.instr_mon_ap[i].connect(cov_model.interrupt_covg.interrupt_mon_export); - rvfi_agent.instr_mon_ap[i].connect(pma_agent.monitor.rvfi_instr_export); - end - -endfunction: connect_coverage_model - - -function void uvme_cv32e40x_env_c::assemble_vsequencer(); - - vsequencer.clknrst_sequencer = clknrst_agent.sequencer; - vsequencer.interrupt_sequencer = interrupt_agent.sequencer; - vsequencer.debug_sequencer = debug_agent.sequencer; - vsequencer.obi_memory_instr_sequencer = obi_memory_instr_agent.sequencer; - vsequencer.obi_memory_data_sequencer = obi_memory_data_agent .sequencer; - -endfunction: assemble_vsequencer - - -function void uvme_cv32e40x_env_c::install_vp_register_seqs(uvma_obi_memory_slv_seq_c data_slv_seq); - - void'(data_slv_seq.register_vp_vseq("vp_virtual_printer", CV_VP_VIRTUAL_PRINTER_BASE, uvma_obi_memory_vp_virtual_printer_seq_c::get_type())); - - void'(data_slv_seq.register_vp_vseq("vp_rand_num", CV_VP_RANDOM_NUM_BASE, uvma_obi_memory_vp_rand_num_seq_c::get_type())); - - void'(data_slv_seq.register_vp_vseq("vp_cycle_counter", CV_VP_CYCLE_COUNTER_BASE, uvma_obi_memory_vp_cycle_counter_seq_c::get_type())); - - begin - uvma_obi_memory_vp_directed_slv_resp_seq_c#(2) vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_directed_slv_resp", CV_VP_OBI_SLV_RESP_BASE, uvma_obi_memory_vp_directed_slv_resp_seq_c#(2)::get_type()))) begin - `uvm_fatal("CV32E40XVPSEQ", $sformatf("Could not cast vp_directed_slv_resp correctly")); - end - vp_seq.obi_cfg[0] = cfg.obi_memory_instr_cfg; - vp_seq.obi_cfg[1] = cfg.obi_memory_data_cfg; - end - - begin - uvme_cv32e40x_vp_sig_writer_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_sig_writer", CV_VP_SIG_WRITER_BASE, uvme_cv32e40x_vp_sig_writer_seq_c::get_type()))) begin - `uvm_fatal("CV32E40XVPSEQ", $sformatf("Could not cast vp_sig_writes correctly")); - end - vp_seq.cv32e40x_cntxt = cntxt; - end - - begin - uvme_cv32e40x_vp_status_flags_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_status_flags", CV_VP_STATUS_FLAGS_BASE, uvme_cv32e40x_vp_status_flags_seq_c::get_type()))) begin - `uvm_fatal("CV32E40XVPSEQ", $sformatf("Could not cast vp_status_flags correctly")); - end - vp_seq.cv32e40x_cntxt = cntxt; - end - - begin - uvme_cv32e40x_vp_interrupt_timer_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_interrupt_timer", CV_VP_INTR_TIMER_BASE, uvme_cv32e40x_vp_interrupt_timer_seq_c::get_type()))) begin - `uvm_fatal("CV32E40XVPSEQ", $sformatf("Could not cast vp_interrupt_timer correctly")); - end - vp_seq.cv32e40x_cntxt = cntxt; - end - - begin - uvme_cv32e40x_vp_debug_control_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_debug_control", CV_VP_DEBUG_CONTROL_BASE, uvme_cv32e40x_vp_debug_control_seq_c::get_type()))) begin - `uvm_fatal("CV32E40XVPSEQ", $sformatf("Could not cast vp_debug_control correctly")); - end - vp_seq.cv32e40x_cntxt = cntxt; - end - - begin - uvme_cv32e40x_vp_fencei_tamper_seq_c vp_seq; - if (!$cast(vp_seq, data_slv_seq.register_vp_vseq("vp_fencei_tamper", CV_VP_FENCEI_TAMPER_BASE, uvme_cv32e40x_vp_fencei_tamper_seq_c::get_type()))) begin - `uvm_fatal("CV32E40XVPSEQ", $sformatf("Could not cast vp_fencei_tamper correctly")); - end - vp_seq.cv32e40x_cntxt = cntxt; - end - -endfunction : install_vp_register_seqs - -`endif // __UVME_CV32E40X_ENV_SV__ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_pkg.sv b/cv32e40x/env/uvme/uvme_cv32e40x_pkg.sv deleted file mode 100644 index 32fcd2a4b2..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_pkg.sv +++ /dev/null @@ -1,106 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_PKG_SV__ -`define __UVME_CV32E40X_PKG_SV__ - - -// Pre-processor macros -`include "uvm_macros.svh" -`include "uvml_hrtbt_macros.sv" -`include "uvml_sb_macros.sv" - -`include "uvma_clknrst_macros.sv" -`include "uvme_cv32e40x_macros.sv" - - - /** - * Encapsulates all the types needed for an UVM environment capable of driving/ - * monitoring and verifying the behavior of an CV32E40X design. - */ -package uvme_cv32e40x_pkg; - - import uvm_pkg ::*; - import uvml_hrtbt_pkg ::*; - import uvml_sb_pkg ::*; - import uvml_trn_pkg ::*; - import uvml_mem_pkg ::*; - import uvma_core_cntrl_pkg::*; - import uvma_isacov_pkg::*; - import uvma_clknrst_pkg::*; - import uvma_interrupt_pkg::*; - import uvma_debug_pkg::*; - import uvma_obi_memory_pkg::*; - import uvma_rvfi_pkg::*; - import uvma_rvvi_pkg::*; - import uvma_rvvi_ovpsim_pkg::*; - import uvma_fencei_pkg::*; - import uvma_pma_pkg::*; - - // Forward decls - typedef class uvme_cv32e40x_vsqr_c; - - // Constants / Structs / Enums - `include "uvme_cv32e40x_constants.sv" - `include "uvme_cv32e40x_tdefs.sv" - - // Objects - `include "uvma_cv32e40x_core_cntrl_cntxt.sv" - `include "uvme_cv32e40x_cfg.sv" - `include "uvme_cv32e40x_cntxt.sv" - - // Predictor - `include "uvme_cv32e40x_prd.sv" - - // Virtual sequences - `include "uvme_cv32e40x_base_vseq.sv" - `include "uvme_cv32e40x_reset_vseq.sv" - `include "uvme_cv32e40x_vp_debug_control_seq.sv" - `include "uvme_cv32e40x_vp_interrupt_timer_seq.sv" - `include "uvme_cv32e40x_vp_sig_writer_seq.sv" - `include "uvme_cv32e40x_vp_status_flags_seq.sv" - `include "uvme_cv32e40x_vp_fencei_tamper_seq.sv" - `include "uvme_cv32e40x_interrupt_noise_vseq.sv" - `include "uvme_cv32e40x_vseq_lib.sv" - `include "uvme_cv32e40x_core_cntrl_base_seq.sv" - `include "uvme_cv32e40x_core_cntrl_fetch_toggle_seq.sv" - `include "uvme_cv32e40x_random_debug_vseq.sv" - `include "uvme_cv32e40x_random_debug_reset_vseq.sv" - `include "uvme_cv32e40x_random_debug_bootset_vseq.sv" - - // Environment components - `include "uvma_cv32e40x_core_cntrl_drv.sv" - `include "uvma_cv32e40x_core_cntrl_agent.sv" - `include "uvme_interrupt_covg.sv" - `include "uvme_debug_covg.sv" - `include "uvme_exceptions_covg.sv" - `include "uvme_counters_covg.sv" - `include "uvme_cv32e40x_cov_model.sv" - `include "uvme_cv32e40x_sb.sv" - `include "uvme_cv32e40x_core_sb.sv" - `include "uvme_cv32e40x_buserr_sb.sv" - `include "uvme_cv32e40x_vsqr.sv" - `include "uvme_cv32e40x_env.sv" - -endpackage : uvme_cv32e40x_pkg - -// Interfaces -`include "uvme_cv32e40x_core_cntrl_if.sv" - -`endif // __UVME_CV32E40X_PKG_SV__ - - diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_prd.sv b/cv32e40x/env/uvme/uvme_cv32e40x_prd.sv deleted file mode 100644 index 06e860e7af..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_prd.sv +++ /dev/null @@ -1,163 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_PRD_SV__ -`define __UVME_CV32E40X_PRD_SV__ - - -/** - * Component implementing transaction-based software model of CV32E40X DUT. - */ -class uvme_cv32e40x_prd_c extends uvm_component; - - // Objects - uvme_cv32e40x_cfg_c cfg; - uvme_cv32e40x_cntxt_c cntxt; - - // Input TLM - uvm_analysis_export #(uvma_clknrst_mon_trn_c) clknrst_export; - uvm_tlm_analysis_fifo#(uvma_clknrst_mon_trn_c) clknrst_fifo; - //uvm_analysis_export #(uvma_debug_mon_trn_c) debug_export; - //uvm_tlm_analysis_fifo#(uvma_debug_mon_trn_c) debug_fifo; - - // Output TLM - // TODO Add TLM outputs to uvme_cv32e40x_prd_c - // Ex: uvm_analysis_port#(uvma_packet_trn_c) pkts_out_ap; - - - `uvm_component_utils_begin(uvme_cv32e40x_prd_c) - `uvm_field_object(cfg , UVM_DEFAULT) - `uvm_field_object(cntxt, UVM_DEFAULT) - `uvm_component_utils_end - - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_prd", uvm_component parent=null); - - /** - * TODO Describe uvme_cv32e40x_prd_c::build_phase() - */ - extern virtual function void build_phase(uvm_phase phase); - - /** - * TODO Describe uvme_cv32e40x_prd_c::connect_phase() - */ - extern virtual function void connect_phase(uvm_phase phase); - - /** - * TODO Describe uvme_cv32e40x_prd_c::run_phase() - */ - extern virtual task run_phase(uvm_phase phase); - - /** - * TODO Describe uvme_cv32e40x_prd_c::process_clknrst() - */ - extern task process_clknrst(); - - /** - * TODO Describe uvme_cv32e40x_prd_c::process_debug() - */ - //extern task process_debug(); - -endclass : uvme_cv32e40x_prd_c - - -function uvme_cv32e40x_prd_c::new(string name="uvme_cv32e40x_prd", uvm_component parent=null); - - super.new(name, parent); - -endfunction : new - - -function void uvme_cv32e40x_prd_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvme_cv32e40x_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) begin - `uvm_fatal("CFG", "Configuration handle is null") - end - - void'(uvm_config_db#(uvme_cv32e40x_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (!cntxt) begin - `uvm_fatal("CNTXT", "Context handle is null") - end - - // Build Input TLM objects - clknrst_export = new("clknrst_export", this); - clknrst_fifo = new("clknrst_fifo" , this); - //debug_export = new("debug_export", this); - //debug_fifo = new("debug_fifo" , this); - - // Build Output TLM objects - // TODO Create Output TLM objects for uvme_cv32e40x_prd_c - // Ex: pkts_out_ap = new("pkts_out_ap", this); - -endfunction : build_phase - - -function void uvme_cv32e40x_prd_c::connect_phase(uvm_phase phase); - - super.connect_phase(phase); - - // Connect TLM objects - clknrst_export.connect(clknrst_fifo.analysis_export); - //debug_export.connect(debug_fifo.analysis_export); - -endfunction: connect_phase - - -task uvme_cv32e40x_prd_c::run_phase(uvm_phase phase); - - super.run_phase(phase); - - fork - process_clknrst(); - //process_debug(); - join_none - -endtask: run_phase - - -task uvme_cv32e40x_prd_c::process_clknrst(); - - uvma_clknrst_mon_trn_c clknrst_trn; - - forever begin - clknrst_fifo.get(clknrst_trn); - - // TODO Implement uvme_cv32e40x_prd_c::process_clknrst() - end - -endtask : process_clknrst - - -//task uvme_cv32e40x_prd_c::process_debug(); -// -// uvma_debug_mon_trn_c debug_trn; -// -// forever begin -// debug_fifo.get(debug_trn); -// -// // TODO Implement uvme_cv32e40x_prd_c::process_debug() -// end -// -//endtask : process_debug - - -`endif // __UVME_CV32E40X_PRD_SV__ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_sb.sv b/cv32e40x/env/uvme/uvme_cv32e40x_sb.sv deleted file mode 100644 index c20531f722..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_sb.sv +++ /dev/null @@ -1,133 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_SB_SV__ -`define __UVME_CV32E40X_SB_SV__ - - -/** - * Component encapsulating scoreboards which compare CV32E40X - * DUT's expected (from predictor) vs. actual (monitored) transactions. - */ -class uvme_cv32e40x_sb_c extends uvm_scoreboard; - - // Objects - uvme_cv32e40x_cfg_c cfg; - uvme_cv32e40x_cntxt_c cntxt; - - // Components - // TODO Add sub-scoreboards - // Ex: uvme_cv32e40x_sb_simplex_c egress_sb; - // uvme_cv32e40x_sb_simplex_c ingress_sb; - - - `uvm_component_utils_begin(uvme_cv32e40x_sb_c) - `uvm_field_object(cfg , UVM_DEFAULT) - `uvm_field_object(cntxt, UVM_DEFAULT) - - // TODO Add sub-scoreboards field macros - // Ex: `uvm_field_object(egress_sb , UVM_DEFAULT) - // `uvm_field_object(ingress_sb, UVM_DEFAULT) - `uvm_component_utils_end - - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_sb", uvm_component parent=null); - - /** - * Create and configures sub-scoreboards via: - * 1. assign_cfg() - * 2. assign_cntxt() - * 3. create_sbs() - */ - extern virtual function void build_phase(uvm_phase phase); - - /** - * Assigns configuration handles. - */ - extern virtual function void assign_cfg(); - - /** - * Assigns context handles. - */ - extern virtual function void assign_cntxt(); - - /** - * Creates sub-scoreboard components. - */ - extern virtual function void create_sbs(); - -endclass : uvme_cv32e40x_sb_c - - -function uvme_cv32e40x_sb_c::new(string name="uvme_cv32e40x_sb", uvm_component parent=null); - - super.new(name, parent); - -endfunction : new - - -function void uvme_cv32e40x_sb_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvme_cv32e40x_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) begin - `uvm_fatal("CFG", "Configuration handle is null") - end - - void'(uvm_config_db#(uvme_cv32e40x_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (!cntxt) begin - `uvm_fatal("CNTXT", "Context handle is null") - end - - assign_cfg (); - assign_cntxt(); - create_sbs (); - -endfunction : build_phase - - -function void uvme_cv32e40x_sb_c::assign_cfg(); - - // TODO Implement uvme_cv32e40x_sb_c::assign_cfg() - // Ex: uvm_config_db#(uvm_sb_cfg_c)::set(this, "egress_sb" , "cfg", cfg.sb_egress_cfg ); - // uvm_config_db#(uvm_sb_cfg_c)::set(this, "ingress_sb", "cfg", cfg.sb_ingress_cfg); - -endfunction : assign_cfg - - -function void uvme_cv32e40x_sb_c::assign_cntxt(); - - // TODO Implement uvme_cv32e40x_sb_c::assign_cntxt() - // Ex: uvm_config_db#(uvme_cv32e40x_sb_cntxt_c)::set(this, "egress_sb" , "cntxt", cntxt.sb_egress_cntxt ); - // uvm_config_db#(uvme_cv32e40x_sb_cntxt_c)::set(this, "ingress_sb", "cntxt", cntxt.sb_ingress_cntxt); - -endfunction : assign_cntxt - - -function void uvme_cv32e40x_sb_c::create_sbs(); - - // TODO Implement uvme_cv32e40x_sb_c::create_sbs() - // Ex: egress_sb = uvme_cv32e40x_sb_simplex_c::type_id::create("egress_sb" , this); - // ingress_sb = uvme_cv32e40x_sb_simplex_c::type_id::create("ingress_sb", this); - -endfunction : create_sbs - - -`endif // __UVME_CV32E40X_SB_SV__ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_vsqr.sv b/cv32e40x/env/uvme/uvme_cv32e40x_vsqr.sv deleted file mode 100644 index 8087f1308d..0000000000 --- a/cv32e40x/env/uvme/uvme_cv32e40x_vsqr.sv +++ /dev/null @@ -1,83 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_VSQR_SV__ -`define __UVME_CV32E40X_VSQR_SV__ - - -/** - * Component on which all CV32E40X virtual sequences are run. - */ -class uvme_cv32e40x_vsqr_c extends uvm_sequencer#( - .REQ(uvm_sequence_item), - .RSP(uvm_sequence_item) -); - - // Objects - uvme_cv32e40x_cfg_c cfg; - uvme_cv32e40x_cntxt_c cntxt; - - // Sequencer handles - uvma_clknrst_sqr_c clknrst_sequencer; - uvma_interrupt_sqr_c interrupt_sequencer; - uvma_debug_sqr_c debug_sequencer; - uvma_obi_memory_sqr_c obi_memory_instr_sequencer; - uvma_obi_memory_sqr_c obi_memory_data_sequencer ; - - `uvm_component_utils_begin(uvme_cv32e40x_vsqr_c) - `uvm_field_object(cfg , UVM_DEFAULT) - `uvm_field_object(cntxt, UVM_DEFAULT) - `uvm_component_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_sqr", uvm_component parent=null); - - /** - * Ensures cfg & cntxt handles are not null. - */ - extern virtual function void build_phase(uvm_phase phase); - -endclass : uvme_cv32e40x_vsqr_c - - -function uvme_cv32e40x_vsqr_c::new(string name="uvme_cv32e40x_sqr", uvm_component parent=null); - - super.new(name, parent); - -endfunction : new - - -function void uvme_cv32e40x_vsqr_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - void'(uvm_config_db#(uvme_cv32e40x_cfg_c)::get(this, "", "cfg", cfg)); - if (!cfg) begin - `uvm_fatal("CFG", "Configuration handle is null") - end - - void'(uvm_config_db#(uvme_cv32e40x_cntxt_c)::get(this, "", "cntxt", cntxt)); - if (!cntxt) begin - `uvm_fatal("CNTXT", "Context handle is null") - end - -endfunction : build_phase - - -`endif // __UVME_CV32E40X_VSQR_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_base_vseq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_base_vseq.sv deleted file mode 100644 index 5c02cdd741..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_base_vseq.sv +++ /dev/null @@ -1,68 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_BASE_VSEQ_SV__ -`define __UVME_CV32E40X_BASE_VSEQ_SV__ - - -/** - * Abstract object from which all other CV32E40X virtual sequences extend. - * Does not generate any sequence items of its own. Subclasses must be run on - * CV32E40X Virtual Sequencer (uvme_cv32e40x_vsqr_c) instance. - */ -class uvme_cv32e40x_base_vseq_c extends uvm_sequence#( - .REQ(uvm_sequence_item), - .RSP(uvm_sequence_item) -); - - // Environment handles - uvme_cv32e40x_cfg_c cfg; - uvme_cv32e40x_cntxt_c cntxt; - - - `uvm_object_utils(uvme_cv32e40x_base_vseq_c) - `uvm_declare_p_sequencer(uvme_cv32e40x_vsqr_c) - - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_base_vseq"); - - /** - * Retrieve cfg and cntxt handles from p_sequencer. - */ - extern virtual task pre_start(); - -endclass : uvme_cv32e40x_base_vseq_c - - -function uvme_cv32e40x_base_vseq_c::new(string name="uvme_cv32e40x_base_vseq"); - - super.new(name); - -endfunction : new - - -task uvme_cv32e40x_base_vseq_c::pre_start(); - - cfg = p_sequencer.cfg ; - cntxt = p_sequencer.cntxt; - -endtask : pre_start - - -`endif // __UVME_CV32E40X_BASE_VSEQ_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_core_cntrl_base_seq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_core_cntrl_base_seq.sv deleted file mode 100644 index b5c37a1e7f..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_core_cntrl_base_seq.sv +++ /dev/null @@ -1,56 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_CORE_CNTRL_BASE_SEQ_C__ -`define __UVME_CV32E40X_CORE_CNTRL_BASE_SEQ_C__ - -/** - * Virtual sequence responsible for controlling fetch_en during tests - */ -class uvme_cv32e40x_core_cntrl_base_seq_c extends uvma_core_cntrl_base_seq_c; - - // Environment handles - uvme_cv32e40x_cfg_c cfg; - uvma_cv32e40x_core_cntrl_cntxt_c cntxt; - - `uvm_object_utils(uvme_cv32e40x_core_cntrl_base_seq_c) - `uvm_declare_p_sequencer(uvma_core_cntrl_sqr_c) - - extern function new(string name = ""); - - extern virtual task pre_start(); - -endclass : uvme_cv32e40x_core_cntrl_base_seq_c - -function uvme_cv32e40x_core_cntrl_base_seq_c::new(string name = ""); - - super.new(name); - -endfunction : new - -task uvme_cv32e40x_core_cntrl_base_seq_c::pre_start(); - - if (!$cast(cfg, p_sequencer.cfg)) begin - `uvm_fatal("E40XCORECNTRLSEQ", $sformatf("Could not cast p_sequencer.cfg to uvme_cv32e40x_cfg")) - end - - if (!$cast(cntxt, p_sequencer.cntxt)) begin - `uvm_fatal("E40XCORECNTRLSEQ", $sformatf("Could not cast p_sequencer.cntxt' to uvme_cv32e40x_cntxt'")) - end - -endtask : pre_start - -`endif // __UVME_CV32E40X_CORE_CNTRL_BASE_SEQ_C__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_core_cntrl_fetch_toggle_seq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_core_cntrl_fetch_toggle_seq.sv deleted file mode 100644 index 98c12516da..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_core_cntrl_fetch_toggle_seq.sv +++ /dev/null @@ -1,129 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_FETCH_TOGGLE_SEQ_C__ -`define __UVME_CV32E40X_FETCH_TOGGLE_SEQ_C__ - -/** - * Virtual sequence responsible for controlling fetch_en during tests - */ -class uvme_cv32e40x_fetch_toggle_seq_c extends uvme_cv32e40x_core_cntrl_base_seq_c; - - rand fetch_toggle_t fetch_toggle_mode; - - rand int unsigned initial_delay; - - `uvm_object_utils_begin(uvme_cv32e40x_fetch_toggle_seq_c); - `uvm_field_enum(fetch_toggle_t, fetch_toggle_mode, UVM_DEFAULT) - `uvm_field_int(initial_delay, UVM_DEFAULT) - `uvm_object_utils_end - - constraint default_mode_cons { - soft fetch_toggle_mode inside { FETCH_CONSTANT, FETCH_INITIAL_DELAY_CONSTANT }; - } - - constraint default_initial_delay { - // Wait a bit before starting - initial_delay inside {[50:200]}; - } - - extern function new(string name = ""); - - extern virtual task body(); - - extern virtual task fetch_constant(); - - extern virtual task fetch_initial_delay(); - - extern virtual task fetch_random_toggle(); - -endclass : uvme_cv32e40x_fetch_toggle_seq_c - -function uvme_cv32e40x_fetch_toggle_seq_c::new(string name = ""); - - super.new(name); - - if ($test$plusargs("fetch_initial_delay")) begin - fetch_toggle_mode = FETCH_INITIAL_DELAY_CONSTANT; - fetch_toggle_mode.rand_mode(0); - end - else if ($test$plusargs("random_fetch_toggle")) begin - fetch_toggle_mode = FETCH_RANDOM_TOGGLE; - fetch_toggle_mode.rand_mode(0); - end - else if ($test$plusargs("fetch_constant")) begin - fetch_toggle_mode = FETCH_CONSTANT; - fetch_toggle_mode.rand_mode(0); - end - -endfunction : new - -task uvme_cv32e40x_fetch_toggle_seq_c::body(); - - `uvm_info("FETCHTOGGLE", $sformatf("Driving fetch_en with mode: %s", fetch_toggle_mode.name()), UVM_LOW) - - case (fetch_toggle_mode) - FETCH_CONSTANT: fetch_constant(); - FETCH_INITIAL_DELAY_CONSTANT: fetch_initial_delay(); - FETCH_RANDOM_TOGGLE: begin - fetch_initial_delay(); - fetch_random_toggle(); - end - endcase - -endtask : body - -task uvme_cv32e40x_fetch_toggle_seq_c::fetch_constant(); - - // Start fetching as fast as possible - cntxt.core_cntrl_vif.drv_cb.fetch_en <= 1'b1; - -endtask : fetch_constant - -task uvme_cv32e40x_fetch_toggle_seq_c::fetch_initial_delay(); - - repeat (initial_delay) @(cntxt.core_cntrl_vif.drv_cb); - cntxt.core_cntrl_vif.drv_cb.fetch_en <= 1'b1; - -endtask : fetch_initial_delay - -task uvme_cv32e40x_fetch_toggle_seq_c::fetch_random_toggle(); - - while (1) begin - int unsigned fetch_assert_cycles; - int unsigned fetch_deassert_cycles; - - // Randomly assert for a random number of cycles - randcase - 9: fetch_assert_cycles = $urandom_range(100_000, 100); - 1: fetch_assert_cycles = $urandom_range(100, 1); - 1: fetch_assert_cycles = $urandom_range(3, 1); - endcase - repeat (fetch_assert_cycles) @(cntxt.core_cntrl_vif.drv_cb); - cntxt.core_cntrl_vif.drv_cb.fetch_en <= 1'b0; - - // Randomly dessert for a random number of cycles - randcase - 3: fetch_deassert_cycles = $urandom_range(100, 1); - 1: fetch_deassert_cycles = $urandom_range(3, 1); - endcase - repeat (fetch_deassert_cycles) @(cntxt.core_cntrl_vif.drv_cb); - cntxt.core_cntrl_vif.drv_cb.fetch_en <= 1'b1; - end - -endtask : fetch_random_toggle - -`endif // __UVME_CV32E40X_FETCH_TOGGLE_SEQ_C__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_bootset_vseq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_bootset_vseq.sv deleted file mode 100644 index 14e701aff4..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_bootset_vseq.sv +++ /dev/null @@ -1,45 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -`ifndef __UVME_CV32E40X_RANDOM_DEBUG_BOOTSET__ -`define __UVME_CV32E40X_RANDOM_DEBUG_BOOTSET__ - -class uvme_cv32e40x_random_debug_bootset_c extends uvme_cv32e40x_base_vseq_c; - - - `uvm_object_utils_begin(uvme_cv32e40x_random_debug_bootset_c) - `uvm_object_utils_end - - extern function new(string name="uvme_cv32e40x_random_debug_bootset"); - - extern virtual task body(); -endclass : uvme_cv32e40x_random_debug_bootset_c - -function uvme_cv32e40x_random_debug_bootset_c::new(string name="uvme_cv32e40x_random_debug_bootset"); - super.new(name); -endfunction : new - - -task uvme_cv32e40x_random_debug_bootset_c::body(); - fork - uvma_debug_seq_item_c debug_req; - `uvm_do_on_with(debug_req, p_sequencer.debug_sequencer, { - active_cycles == 1; - }); - join -endtask : body -`endif // __UVME_CV32E40X_RANDOM_DEBUG_BOOTSET__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_reset_vseq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_reset_vseq.sv deleted file mode 100644 index 24ebafcf28..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_reset_vseq.sv +++ /dev/null @@ -1,45 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -`ifndef __UVME_CV32E40X_RANDOM_DEBUG_RESET__ -`define __UVME_CV32E40X_RANDOM_DEBUG_RESET__ - -class uvme_cv32e40x_random_debug_reset_c extends uvme_cv32e40x_base_vseq_c; - - - `uvm_object_utils_begin(uvme_cv32e40x_random_debug_reset_c) - `uvm_object_utils_end - - extern function new(string name="uvme_cv32e40x_random_debug_reset"); - - extern virtual task body(); -endclass : uvme_cv32e40x_random_debug_reset_c - -function uvme_cv32e40x_random_debug_reset_c::new(string name="uvme_cv32e40x_random_debug_reset"); - super.new(name); -endfunction : new - - -task uvme_cv32e40x_random_debug_reset_c::body(); - fork - uvma_debug_seq_item_c debug_req; - `uvm_do_on_with(debug_req, p_sequencer.debug_sequencer, { - active_cycles == 50; - }); - join -endtask : body -`endif // __UVME_CV32E40X_RANDOM_DEBUG_RESET__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_vseq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_vseq.sv deleted file mode 100644 index d8c3b9a1d4..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_random_debug_vseq.sv +++ /dev/null @@ -1,50 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -`ifndef __UVME_CV32E40X_RANDOM_DEBUG__ -`define __UVME_CV32E40X_RANDOM_DEBUG__ - -class uvme_cv32e40x_random_debug_c extends uvme_cv32e40x_base_vseq_c; - - - `uvm_object_utils_begin(uvme_cv32e40x_random_debug_c) - `uvm_object_utils_end - - extern function new(string name="uvme_cv32e40x_random_debug"); - - extern virtual task body(); - extern virtual task rand_delay(); -endclass : uvme_cv32e40x_random_debug_c - -function uvme_cv32e40x_random_debug_c::new(string name="uvme_cv32e40x_random_debug"); - super.new(name); -endfunction : new - -task uvme_cv32e40x_random_debug_c::rand_delay(); - #($urandom_range(10000, 1)); -endtask : rand_delay - -task uvme_cv32e40x_random_debug_c::body(); - fork - while(1) begin - uvma_debug_seq_item_c debug_req; - `uvm_do_on_with(debug_req, p_sequencer.debug_sequencer, {}); - rand_delay(); - end - join -endtask : body -`endif // __UVME_CV32E40X_RANDOM_DEBUG__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_reset_vseq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_reset_vseq.sv deleted file mode 100644 index 6939f1c177..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_reset_vseq.sv +++ /dev/null @@ -1,98 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVME_CV32E40X_RESET_VSEQ_SV__ -`define __UVME_CV32E40X_RESET_VSEQ_SV__ - - -/** - * Virtual sequence responsible for starting the system clock and issuing - * the initial reset pulse to the DUT. - */ -class uvme_cv32e40x_reset_vseq_c extends uvme_cv32e40x_base_vseq_c; - - rand int unsigned num_clk_before_reset; ///< Number of clock cylces between start of clock and resert assert - rand int unsigned rst_deassert_period ; ///< Time delta between resert assert and de-assert, measured in picoseconds (ps) - rand int unsigned post_rst_wait ; ///< Time delta between resert de-assert and end of virtual sequence, measured in picoseconds (ps) - - - `uvm_object_utils_begin(uvme_cv32e40x_reset_vseq_c) - `uvm_field_int(num_clk_before_reset, UVM_DEFAULT + UVM_DEC) - `uvm_field_int(rst_deassert_period , UVM_DEFAULT + UVM_DEC) - `uvm_field_int(post_rst_wait , UVM_DEFAULT + UVM_DEC) - `uvm_object_utils_end - - - constraint defaults_cons { - soft num_clk_before_reset == 50; - soft rst_deassert_period == 7_400; // 7.4 ns - soft post_rst_wait == 7_400; // 7.4 ns - } - - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_reset_vseq"); - - /** - * Starts the clock, waits, then resets the DUT. - */ - extern virtual task body(); - -endclass : uvme_cv32e40x_reset_vseq_c - - -function uvme_cv32e40x_reset_vseq_c::new(string name="uvme_cv32e40x_reset_vseq"); - - super.new(name); - -endfunction : new - - -task uvme_cv32e40x_reset_vseq_c::body(); - - uvma_clknrst_seq_item_c clk_start_req; - uvma_clknrst_seq_item_c reset_assrt_req; - - // Define the clock before applying reset - #1; - cntxt.clknrst_cntxt.vif.clk = 0; - #1; - - `uvm_info("RST_VSEQ", $sformatf("Asserting reset for %0t", (rst_deassert_period * 1ps)), UVM_LOW) - `uvm_do_on_with(reset_assrt_req, p_sequencer.clknrst_sequencer, { - action == UVMA_CLKNRST_SEQ_ITEM_ACTION_ASSERT_RESET; - initial_value == UVMA_CLKNRST_SEQ_ITEM_INITIAL_VALUE_1 ; - rst_deassert_period == local::rst_deassert_period; - }) - - `uvm_info("RST_VSEQ", $sformatf("Done reset, waiting %0t for DUT to stabilize", (post_rst_wait * 1ps)), UVM_LOW) - #(post_rst_wait * 1ps); - - `uvm_info("RST_VSEQ", $sformatf("Starting clock with period of %0t", (cfg.sys_clk_period * 1ps)), UVM_LOW) - `uvm_do_on_with(clk_start_req, p_sequencer.clknrst_sequencer, { - action == UVMA_CLKNRST_SEQ_ITEM_ACTION_START_CLK; - initial_value == UVMA_CLKNRST_SEQ_ITEM_INITIAL_VALUE_0; - //clk_period == local::cfg.sys_clk_period; - clk_period == cfg.sys_clk_period; - //clk_period == uvme_cv32e40x_sys_default_clk_period; - }) - -endtask : body - - -`endif // __UVME_CV32E40X_RESET_VSEQ_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_debug_control_seq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_debug_control_seq.sv deleted file mode 100644 index d6e864c13c..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_debug_control_seq.sv +++ /dev/null @@ -1,67 +0,0 @@ -// -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may -// not use this file except in compliance with the License, or, at your option, -// the Apache License version 2.0. You may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// - -`ifndef __UVME_CV32E40X_VP_DEBUG_CONTROL_SEQ_SV__ -`define __UVME_CV32E40X_VP_DEBUG_CONTROL_SEQ_SV__ - -/** - * Sequence implementing the virtual status flags decoding - */ -class uvme_cv32e40x_vp_debug_control_seq_c extends uvma_obi_memory_vp_debug_control_seq_c; - - uvme_cv32e40x_cntxt_c cv32e40x_cntxt; - - `uvm_object_utils_begin(uvme_cv32e40x_vp_debug_control_seq_c) - `uvm_object_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_vp_debug_control_seq_c"); - - /** - * Wait for clocks - */ - extern virtual task wait_n_clocks(int unsigned n); - - /** - * Asserts the actual interrupt wires - */ - extern virtual task set_debug_req(bit debug_req); - -endclass : uvme_cv32e40x_vp_debug_control_seq_c - -function uvme_cv32e40x_vp_debug_control_seq_c::new(string name="uvme_cv32e40x_vp_debug_control_seq_c"); - - super.new(name); - -endfunction : new - -task uvme_cv32e40x_vp_debug_control_seq_c::wait_n_clocks(int unsigned n); - - repeat (n) @(cv32e40x_cntxt.debug_vif.mon_cb); - -endtask : wait_n_clocks - -task uvme_cv32e40x_vp_debug_control_seq_c::set_debug_req(bit debug_req); - - cv32e40x_cntxt.debug_vif.drv_cb.debug_drv <= debug_req; - -endtask : set_debug_req - -`endif // __UVME_CV32E40X_VP_DEBUG_CONTROL_SEQ_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_fencei_tamper_seq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_fencei_tamper_seq.sv deleted file mode 100644 index 8d84f181d7..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_fencei_tamper_seq.sv +++ /dev/null @@ -1,165 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may -// not use this file except in compliance with the License, or, at your option, -// the Apache License version 2.0. You may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. - - -`ifndef __UVME_CV32E40X_VP_FENCEI_TAMPER_SEQ_SV__ -`define __UVME_CV32E40X_VP_FENCEI_TAMPER_SEQ_SV__ - - -class uvme_cv32e40x_vp_fencei_tamper_seq_c extends uvma_obi_memory_vp_base_seq_c; - - uvme_cv32e40x_cntxt_c cv32e40x_cntxt; - uvma_rvvi_ovpsim_cntxt_c rvvi_ovpsim_cntxt; - - bit enabled = 0; - bit [31:0] addr; - bit [31:0] data; - - `uvm_object_utils(uvme_cv32e40x_vp_fencei_tamper_seq_c) - - extern function new(string name="uvme_cv32e40x_vp_fencei_tamper_seq_c"); - extern virtual task vp_body(uvma_obi_memory_mon_trn_c mon_trn); - extern virtual function int unsigned get_num_words(); - extern virtual task body(); - extern function void write_rtl_mem(); - extern function void write_iss_mem(); - -endclass : uvme_cv32e40x_vp_fencei_tamper_seq_c - - -function uvme_cv32e40x_vp_fencei_tamper_seq_c::new(string name="uvme_cv32e40x_vp_fencei_tamper_seq_c"); - - super.new(name); - -endfunction : new - - -task uvme_cv32e40x_vp_fencei_tamper_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_trn); - - uvma_obi_memory_slv_seq_item_c slv_rsp; - - `uvm_create(slv_rsp) - slv_rsp.orig_trn = mon_trn; - slv_rsp.err = 1'b0; - - if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin - case (get_vp_index(mon_trn)) - 0: enabled = | mon_trn.data; - 1: addr = mon_trn.data; - 2: data = mon_trn.data; - endcase - end - - add_r_fields(mon_trn, slv_rsp); - slv_rsp.set_sequencer(p_sequencer); - `uvm_send(slv_rsp) - -endtask : vp_body - - -function int unsigned uvme_cv32e40x_vp_fencei_tamper_seq_c::get_num_words(); - - return 3; - -endfunction : get_num_words - - -task uvme_cv32e40x_vp_fencei_tamper_seq_c::body(); - - if (cv32e40x_cntxt == null) begin - `uvm_fatal("E40XVPSTATUS", "Must initialize cv32e40x_cntxt in virtual peripheral"); - end - if (cv32e40x_cntxt.fencei_cntxt == null) begin - `uvm_fatal("E40XVPSTATUS", "Must initialize fencei_cntxt in virtual peripheral"); - end - if (cv32e40x_cntxt.fencei_cntxt.fencei_vif == null) begin - `uvm_fatal("E40XVPSTATUS", "Must initialize fencei_vif in virtual peripheral"); - end - if (cv32e40x_cntxt.rvvi_cntxt == null) begin - `uvm_fatal("E40XVPSTATUS", "Must initialize rvvi_cntxt in virtual peripheral"); - end - if (!$cast(rvvi_ovpsim_cntxt, cv32e40x_cntxt.rvvi_cntxt)) begin - `uvm_fatal("E40XVPSTATUS", "Could not cast rvvi_cntxt to rvvi_ovpsim_cntxt"); - end - - fork - while (1) begin - @(posedge cv32e40x_cntxt.fencei_cntxt.fencei_vif.flush_req); - if (enabled) begin - write_rtl_mem(); - write_iss_mem(); - end - end - join_none - - super.body(); - -endtask : body - - -function void uvme_cv32e40x_vp_fencei_tamper_seq_c::write_rtl_mem(); - - cntxt.mem.write((addr + 0), data[ 7: 0]); - cntxt.mem.write((addr + 1), data[15: 8]); - cntxt.mem.write((addr + 2), data[23:16]); - cntxt.mem.write((addr + 3), data[31:24]); - -endfunction : write_rtl_mem - - -function void uvme_cv32e40x_vp_fencei_tamper_seq_c::write_iss_mem(); - - logic [31:0] addr_lo; - logic [31:0] addr_hi; - int shamt_lo; - int shamt_hi; - logic [31:0] shdata_lo; - logic [31:0] shdata_hi; - logic [31:0] issmask_lo; - logic [31:0] issmask_hi; - logic [31:0] issdata_lo; - logic [31:0] issdata_hi; - logic [31:0] data_lo; - logic [31:0] data_hi; - - // Calculate iss ram addresses - addr_lo = addr >> 2; - addr_hi = (addr + 4) >> 2; - - // Shift the data to be written - shamt_lo = addr[1:0] * 8; - shamt_hi = (4 * 8) - shamt_lo; - shdata_lo = data << shamt_lo; - shdata_hi = data >> shamt_hi; - - // Mask the existing data - issmask_lo = 32'h FFFF_FFFF >> shamt_hi; - issmask_hi = 32'h FFFF_FFFF << shamt_lo; - issdata_lo = rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_lo] & issmask_lo; - issdata_hi = rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_hi] & issmask_hi; - - // Calculate iss ram data - data_lo = shdata_lo | issdata_lo; - data_hi = shdata_hi | issdata_hi; - - // Write to iss ram - rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_lo] = data_lo; - rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[addr_hi] = data_hi; - -endfunction : write_iss_mem - - -`endif // __UVME_OBI_MEMORY_VP_FENCEI_TAMPER_SEQ_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_interrupt_timer_seq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_interrupt_timer_seq.sv deleted file mode 100644 index f61e01bdca..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_interrupt_timer_seq.sv +++ /dev/null @@ -1,56 +0,0 @@ -// -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may -// not use this file except in compliance with the License, or, at your option, -// the Apache License version 2.0. You may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// - -`ifndef __UVME_CV32E40X_VP_INTERRUPT_TIMER_SEQ_SV__ -`define __UVME_CV32E40X_VP_INTERRUPT_TIMER_SEQ_SV__ - -/** - * Sequence implementing the virtual status flags decoding - */ -class uvme_cv32e40x_vp_interrupt_timer_seq_c extends uvma_obi_memory_vp_interrupt_timer_seq_c; - - uvme_cv32e40x_cntxt_c cv32e40x_cntxt; - - `uvm_object_utils_begin(uvme_cv32e40x_vp_interrupt_timer_seq_c) - `uvm_object_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_vp_interrupt_timer_seq_c"); - - /** - * Asserts the actual interrupt wires - */ - extern virtual task set_interrupt(); - -endclass : uvme_cv32e40x_vp_interrupt_timer_seq_c - -function uvme_cv32e40x_vp_interrupt_timer_seq_c::new(string name="uvme_cv32e40x_vp_interrupt_timer_seq_c"); - - super.new(name); - -endfunction : new - -task uvme_cv32e40x_vp_interrupt_timer_seq_c::set_interrupt(); - - cv32e40x_cntxt.interrupt_cntxt.vif.drv_cb.irq_drv <= interrupt_value; - -endtask : set_interrupt - -`endif // __UVME_CV32E40X_VP_INTERRUPT_TIMER_SEQ_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_sig_writer_seq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_sig_writer_seq.sv deleted file mode 100644 index 51774f3abe..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_sig_writer_seq.sv +++ /dev/null @@ -1,73 +0,0 @@ -// -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may -// not use this file except in compliance with the License, or, at your option, -// the Apache License version 2.0. You may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// - -`ifndef __UVME_CV32E40X_VP_SIG_WRITE_SEQ_SV__ -`define __UVME_CV32E40X_VP_SIG_WRITE_SEQ_SV__ - - -/** - * Sequence implementing the virtual status flags decoding - */ -class uvme_cv32e40x_vp_sig_writer_seq_c extends uvma_obi_memory_vp_sig_writer_seq_c; - - uvme_cv32e40x_cntxt_c cv32e40x_cntxt; - - `uvm_object_utils_begin(uvme_cv32e40x_vp_sig_writer_seq_c) - `uvm_object_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_vp_sig_writer_seq_c"); - - /** - * Implement a body to pre-validate some configuration before allowing parent class body to run - */ - extern virtual task body(); - - /** - * Set virtual exit in core - */ - extern virtual task set_exit_valid(); - -endclass : uvme_cv32e40x_vp_sig_writer_seq_c - -function uvme_cv32e40x_vp_sig_writer_seq_c::new(string name="uvme_cv32e40x_vp_sig_writer_seq_c"); - - super.new(name); - -endfunction : new - -task uvme_cv32e40x_vp_sig_writer_seq_c::body(); - - if (cv32e40x_cntxt == null) begin - `uvm_fatal("E40XVPSTATUS", "Must initialize cv32e40x_cntxt in virtual peripheral") - end - - super.body(); - -endtask : body - -task uvme_cv32e40x_vp_sig_writer_seq_c::set_exit_valid(); - - cv32e40x_cntxt.vp_status_vif.exit_valid = 1; - cv32e40x_cntxt.vp_status_vif.exit_value = 0; - -endtask : set_exit_valid - -`endif // __UVME_CV32E40X_VP_SIG_WRITER_SEQ_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_status_flags_seq.sv b/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_status_flags_seq.sv deleted file mode 100644 index 6b152866ec..0000000000 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vp_status_flags_seq.sv +++ /dev/null @@ -1,121 +0,0 @@ -// -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may -// not use this file except in compliance with the License, or, at your option, -// the Apache License version 2.0. You may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// - -`ifndef __UVME_CV32E40X_VP_STATUS_FLAGS_SEQ_SV__ -`define __UVME_CV32E40X_VP_STATUS_FLAGS_SEQ_SV__ - - -/** - * Sequence implementing the virtual status flags decoding - */ -class uvme_cv32e40x_vp_status_flags_seq_c extends uvma_obi_memory_vp_base_seq_c; - - localparam NUM_WORDS = 2; - - uvme_cv32e40x_cntxt_c cv32e40x_cntxt; - - `uvm_object_utils_begin(uvme_cv32e40x_vp_status_flags_seq_c) - `uvm_object_utils_end - - /** - * Default constructor. - */ - extern function new(string name="uvme_cv32e40x_vp_status_flags_seq_c"); - - /** - * Implement number of peripherals - */ - extern virtual function int unsigned get_num_words(); - - /** - * Implement sequence that will return a random number - */ - extern virtual task vp_body(uvma_obi_memory_mon_trn_c mon_trn); - - /** - * Implement a body to pre-validate some configuration before allowing parent class body to run - */ - extern virtual task body(); - -endclass : uvme_cv32e40x_vp_status_flags_seq_c - -function uvme_cv32e40x_vp_status_flags_seq_c::new(string name="uvme_cv32e40x_vp_status_flags_seq_c"); - - super.new(name); - -endfunction : new - -task uvme_cv32e40x_vp_status_flags_seq_c::body(); - - if (cv32e40x_cntxt == null) begin - `uvm_fatal("E40XVPSTATUS", "Must initialize cv32e40x_cntxt in virtual peripheral") - end - - super.body(); - -endtask : body - -function int unsigned uvme_cv32e40x_vp_status_flags_seq_c::get_num_words(); - - return NUM_WORDS; - -endfunction : get_num_words - -task uvme_cv32e40x_vp_status_flags_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_trn); - - uvma_obi_memory_slv_seq_item_c slv_rsp; - - `uvm_create(slv_rsp) - slv_rsp.orig_trn = mon_trn; - slv_rsp.err = 1'b0; - - if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin - `uvm_info("VP_VSEQ", $sformatf("Call to virtual peripheral 'vp_status_flags':\n%s", mon_trn.sprint()), UVM_DEBUG) - - case (get_vp_index(mon_trn)) - 0: begin - if (mon_trn.data == 'd123456789) begin - `uvm_info("VP_VSEQ", "virtual peripheral: TEST PASSED", UVM_DEBUG) - cv32e40x_cntxt.vp_status_vif.tests_passed = 1; - cv32e40x_cntxt.vp_status_vif.exit_valid = 1; - cv32e40x_cntxt.vp_status_vif.exit_value = 0; - end - else if (mon_trn.data == 'd1) begin - cv32e40x_cntxt.vp_status_vif.tests_failed = 1; - cv32e40x_cntxt.vp_status_vif.exit_valid = 1; - cv32e40x_cntxt.vp_status_vif.exit_value = 1; - end - end - 1: begin - `uvm_info("VP_VSEQ", "virtual peripheral: END OF SIM", UVM_DEBUG) - cv32e40x_cntxt.vp_status_vif.exit_valid = 1; - cv32e40x_cntxt.vp_status_vif.exit_value = mon_trn.data; - end - endcase - end - else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin - slv_rsp.rdata = 0; - end - - add_r_fields(mon_trn, slv_rsp); - slv_rsp.set_sequencer(p_sequencer); - `uvm_send(slv_rsp) - -endtask : vp_body - -`endif // __UVME_OBI_MEMORY_VP_STATUS_FLAGS_SEQ_SV__ diff --git a/cv32e40x/regress/cv32e40x_ci_check.yaml b/cv32e40x/regress/cv32e40x_ci_check.yaml deleted file mode 100644 index 11982b54ee..0000000000 --- a/cv32e40x/regress/cv32e40x_ci_check.yaml +++ /dev/null @@ -1,103 +0,0 @@ -# YAML file to specify the ci_check regression testlist. -name: cv32e40x_ci_check -description: Commit sanity for the cv32e40x - -builds: - clone_riscv-dv: - cmd: make clone_riscv-dv - dir: cv32e40x/sim/uvmt - - clone_svlib: - cmd: make clone_svlib - dir: cv32e40x/sim/uvmt - - clone_cv_core_rtl: - cmd: make clone_cv_core_rtl - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x: - cmd: make comp_corev-dv comp - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_1: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_1 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_2: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_2 - dir: cv32e40x/sim/uvmt - -tests: - hello-world: - build: uvmt_cv32e40x - description: UVM Hello World Test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hello-world - - interrupt_test: - build: uvmt_cv32e40x - description: Interrupt directed test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=interrupt_test - - corev_rand_interrupt: - build: uvmt_cv32e40x - description: Interrupt random test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt - num: 2 - - illegal: - build: uvmt_cv32e40x - dir: cv32e40x/sim/uvmt - cmd: make test TEST=illegal - -# FIXME: temporarily remove this test from ci_check: see issue #1031. -# debug_test: -# build: uvmt_cv32e40x -# dir: cv32e40x/sim/uvmt -# cmd: make test TEST=debug_test -# makearg: USER_RUN_FLAGS=+rand_stall_obi_disable - - csr_instructions: - build: uvmt_cv32e40x - description: CSR Instruction Test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=csr_instructions - - riscv_arithmetic_basic_test_0: - build: uvmt_cv32e40x - description: Static riscv-dv arithmetic test 0 - dir: cv32e40x/sim/uvmt - cmd: make test TEST=riscv_arithmetic_basic_test_0 - - corev_rand_arithmetic_base_test: - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - description: Generated corev-dv random arithmetic test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test - num: 1 - - corev_rand_instr_test: - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - description: Generated corev-dv random instruction test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_test - num: 1 - - corev_rand_jump_stress_test: - build: uvmt_cv32e40x - description: Generated corev-dv jump stress test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test - num: 2 - - diff --git a/cv32e40x/regress/cv32e40x_compliance.yaml b/cv32e40x/regress/cv32e40x_compliance.yaml deleted file mode 100644 index bb1f623922..0000000000 --- a/cv32e40x/regress/cv32e40x_compliance.yaml +++ /dev/null @@ -1,645 +0,0 @@ -# YAML file to specify a regression testlist ---- -# Header -name: cv32_compliance -description: Runs all RISCV compliance tests on the CV32E40X - -# List of builds -builds: - uvmt_cv32e40x: - cmd: make comp - cfg: no_bitmanip - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_compliance_build: - cmd: make all_compliance - cfg: no_bitmanip - dir: cv32e40x/sim/uvmt - -# List of tests -tests: - # ------------------------------------------------------------------------- - # RV32IMC tests - # ------------------------------------------------------------------------- - C-ADD: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-ADD - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADD - results: rv32imc/C-ADD - - C-ADDI: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-ADDI - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADDI - results: rv32imc/C-ADDI - - C-ADDI16SP: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-ADDI16SP - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADDI16SP - results: rv32imc/C-ADDI16SP - - C-ADDI4SPN: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-ADDI4SPN - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ADDI4SPN - results: rv32imc/C-ADDI4SPN - - C-AND: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-AND - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-AND - results: rv32imc/C-AND - - C-ANDI: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-ANDI - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-ANDI - results: rv32imc/C-ANDI - - C-BEQZ: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-BEQZ - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-BEQZ - results: rv32imc/C-BEQZ - - C-BNEZ: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-BNEZ - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-BNEZ - results: rv32imc/C-BNEZ - - C-J: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-J - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-J - results: rv32imc/C-J - - C-JAL: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-JAL - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-JAL - results: rv32imc/C-JAL - - C-JALR: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-JALR - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-JALR - results: rv32imc/C-JALR - - C-JR: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-JR - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-JR - results: rv32imc/C-JR - - C-LI: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-LI - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LI - results: rv32imc/C-LI - - C-LUI: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-LUI - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LUI - results: rv32imc/C-LUI - - C-LW: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-LW - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LW - results: rv32imc/C-LW - - C-LWSP: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-LWSP - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-LWSP - results: rv32imc/C-LWSP - - C-MV: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-MV - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-MV - results: rv32imc/C-MV - - C-OR: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-OR - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-OR - results: rv32imc/C-OR - - C-SLLI: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-SLLI - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SLLI - results: rv32imc/C-SLLI - - C-SRAI: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-SRAI - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SRAI - results: rv32imc/C-SRAI - - C-SRLI: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-SRLI - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SRLI - results: rv32imc/C-SRLI - - C-SUB: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-SUB - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SUB - results: rv32imc/C-SUB - - C-SW: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-SW - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SW - results: rv32imc/C-SW - - C-SWSP: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-SWSP - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-SWSP - results: rv32imc/C-SWSP - - C-XOR: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_C-XOR - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32imc COMPLIANCE_PROG=C-XOR - results: rv32imc/C-XOR - - # ------------------------------------------------------------------------- - # RV32IMC tests - # ------------------------------------------------------------------------- - - I-ADD-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-ADD-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-ADD-01 - results: rv32i/I-ADD-01 - - I-ADDI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-ADDI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-ADDI-01 - results: rv32i/I-ADDI-01 - - I-AND-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-AND-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-AND-01 - results: rv32i/I-AND-01 - - I-ANDI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-ANDI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-ANDI-01 - results: rv32i/I-ANDI-01 - - I-AUIPC-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-AUIPC-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-AUIPC-01 - results: rv32i/I-AUIPC-01 - - I-BEQ-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-BEQ-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-BEQ-01 - results: rv32i/I-BEQ-01 - - I-BGE-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-BGE-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-BGE-01 - results: rv32i/I-BGE-01 - - I-BGEU-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-BGEU-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-BGEU-01 - results: rv32i/I-BGEU-01 - - I-BLT-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-BLT-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-BLT-01 - results: rv32i/I-BLT-01 - - I-BLTU-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-BLTU-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-BLTU-01 - results: rv32i/I-BLTU-01 - - I-BNE-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-BNE-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-BNE-01 - results: rv32i/I-BNE-01 - - I-DELAY_SLOTS-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-DELAY_SLOTS-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-DELAY_SLOTS-01 - results: rv32i/I-DELAY_SLOTS-01 - - # Not running for cv32e40x - # I-EBREAK-01: - # build: uvmt_cv32e40x_compliance_build - # description: RISCV_COMPLIANCE_I-EBREAK-01 - # dir: cv32e40x/sim/uvmt - # cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-EBREAK-01 - - # Not running for cv32e40x - # I-ECALL-01: - # build: uvmt_cv32e40x_compliance_build - # description: RISCV_COMPLIANCE_I-ECALL-01 - # dir: cv32e40x/sim/uvmt - # cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-ECALL-01 - - I-ENDIANESS-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-ENDIANESS-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-ENDIANESS-01 - results: rv32i/I-ENDIANESS-01 - - I-IO-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-IO-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-IO-01 - results: rv32i/I-IO-01 - - I-JAL-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-JAL-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-JAL-01 - results: rv32i/I-JAL-01 - - I-JALR-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-JALR-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-JALR-01 - results: rv32i/I-JALR-01 - - I-LB-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-LB-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-LB-01 - results: rv32i/I-LB-01 - - I-LBU-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-LBU-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-LBU-01 - results: rv32i/I-LBU-01 - - I-LH-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-LH-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-LH-01 - results: rv32i/I-LH-01 - - I-LHU-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-LHU-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-LHU-01 - results: rv32i/I-LHU-01 - - I-LUI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-LUI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-LUI-01 - results: rv32i/I-LUI-01 - - I-LW-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-LW-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-LW-01 - results: rv32i/I-LW-01 - - # Not running for cv32e40x - # I-MISALIGN_JMP-01: - # build: uvmt_cv32e40x_compliance_build - # description: RISCV_COMPLIANCE_I-MISALIGN_JMP-01 - # dir: cv32e40x/sim/uvmt - # cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-MISALIGN_JMP-01 - - # Not running for cv32e40x - # I-MISALIGN_LDST-01: - # build: uvmt_cv32e40x_compliance_build - # description: RISCV_COMPLIANCE_I-MISALIGN_LDST-01 - # dir: cv32e40x/sim/uvmt - # cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-MISALIGN_LDST-01 - - I-OR-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-OR-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-OR-01 - results: rv32i/I-OR-01 - - I-ORI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-ORI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-ORI-01 - results: rv32i/I-ORI-01 - - I-RF_size-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-RF_size-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-RF_size-01 - results: rv32i/I-RF_size-01 - - I-RF_width-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-RF_width-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-RF_width-01 - results: rv32i/I-RF_width-01 - - I-RF_x0-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-RF_x0-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-RF_x0-01 - results: rv32i/I-RF_x0-01 - - I-SB-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SB-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SB-01 - results: rv32i/I-SB-01 - - I-SH-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SH-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SH-01 - results: rv32i/I-SH-01 - - I-SLL-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SLL-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLL-01 - results: rv32i/I-SLL-01 - - I-SLLI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SLLI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLLI-01 - results: rv32i/I-SLLI-01 - - I-SLT-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SLT-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLT-01 - results: rv32i/I-SLT-01 - - I-SLTI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SLTI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLTI-01 - results: rv32i/I-SLTI-01 - - I-SLTIU-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SLTIU-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLTIU-01 - results: rv32i/I-SLTIU-01 - - I-SLTU-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SLTU-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SLTU-01 - results: rv32i/I-SLTU-01 - - I-SRA-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SRA-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRA-01 - results: rv32i/I-SRA-01 - - I-SRAI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SRAI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRAI-01 - results: rv32i/I-SRAI-01 - - I-SRL-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SRL-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRL-01 - results: rv32i/I-SRL-01 - - I-SRLI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SRLI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SRLI-01 - results: rv32i/I-SRLI-01 - - I-SUB-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SUB-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SUB-01 - results: rv32i/I-SUB-01 - - I-SW-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-SW-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-SW-01 - results: rv32i/I-SW-01 - - I-XOR-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-XOR-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-XOR-01 - results: rv32i/I-XOR-01 - - I-XORI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-XORI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32i COMPLIANCE_PROG=I-XORI-01 - results: rv32i/I-XORI-01 - - # ------------------------------------------------------------------------- - # RV32IM tests - # ------------------------------------------------------------------------- - MUL: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_MUL - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=MUL - results: rv32im/MUL - - MULH: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_MULH - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=MULH - results: rv32im/MULH - - MULHSU: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_MULHSU - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=MULHSU - results: rv32im/MULHSU - - MULHU: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_MULHU - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=MULHU - results: rv32im/MULHU - - REM: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_REM - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=REM - results: rv32im/REM - - REMU: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_REMU - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=REMU - results: rv32im/REMU - - DIV: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_DIV - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=DIV - results: rv32im/DIV - - DIVU: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_DIVU - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32im COMPLIANCE_PROG=DIVU - results: rv32im/DIVU - - # ------------------------------------------------------------------------- - # RV32ZICSR tests - # ------------------------------------------------------------------------- - I-CSRRC-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-CSRRC-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRC-01 - results: rv32Zicsr/I-CSRRC-01 - - I-CSRRCI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-CSRRCI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRCI-01 - results: rv32Zicsr/I-CSRRCI-01 - - I-CSRRS-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-CSRRS-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRS-01 - results: rv32Zicsr/I-CSRRS-01 - - I-CSRRSI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-CSRRSI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRSI-01 - results: rv32Zicsr/I-CSRRSI-01 - - I-CSRRW-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-CSRRW-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRW-01 - results: rv32Zicsr/I-CSRRW-01 - - I-CSRRWI-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-CSRRWI-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32Zicsr COMPLIANCE_PROG=I-CSRRWI-01 - results: rv32Zicsr/I-CSRRWI-01 - - # ------------------------------------------------------------------------- - # RV32ZIFENCEI tests - # ------------------------------------------------------------------------- - I-FENCE.I-01: - build: uvmt_cv32e40x_compliance_build - description: RISCV_COMPLIANCE_I-FENCE.I-01 - dir: cv32e40x/sim/uvmt - cmd: make compliance_check_sig RISCV_ISA=rv32Zifencei COMPLIANCE_PROG=I-FENCE.I-01 - results: rv32Zifencei/I-FENCE.I-01 - diff --git a/cv32e40x/regress/cv32e40x_corev_pma.yaml b/cv32e40x/regress/cv32e40x_corev_pma.yaml deleted file mode 100644 index 60114974e7..0000000000 --- a/cv32e40x/regress/cv32e40x_corev_pma.yaml +++ /dev/null @@ -1,266 +0,0 @@ -name: cv32e40x_corev_pma -description: CORE-V turnon regression across multiple PMA configurations - -builds: - corev-dv: - cmd: make comp_corev-dv - dir: cv32e40x/sim/uvmt - - corev-dv_pma_1: - cmd: make comp_corev-dv - cfg: pma_test_cfg_1 - dir: cv32e40x/sim/uvmt - - corev-dv_pma_2: - cmd: make comp_corev-dv - cfg: pma_test_cfg_2 - dir: cv32e40x/sim/uvmt - - corev-dv_pma_3: - cmd: make comp_corev-dv - cfg: pma_test_cfg_3 - dir: cv32e40x/sim/uvmt - - corev-dv_pma_4: - cmd: make comp_corev-dv - cfg: pma_test_cfg_4 - dir: cv32e40x/sim/uvmt - - corev-dv_pma_5: - cmd: make comp_corev-dv - cfg: pma_test_cfg_5 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x: - cmd: make comp - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_1: - cmd: make comp - cfg: pma_test_cfg_1 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_2: - cmd: make comp - cfg: pma_test_cfg_2 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_3: - cmd: make comp - cfg: pma_test_cfg_3 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_4: - cmd: make comp - cfg: pma_test_cfg_4 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_5: - cmd: make comp - cfg: pma_test_cfg_5 - dir: cv32e40x/sim/uvmt - -tests: - hello-world: - description: UVM Hello World Test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hello-world - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - num: 5 - - corev_rand_jump_stress_test: - description: Generated corev-dv jump stress test - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test - num: 5 - - corev_rand_arithmetic_base_test: - description: Generated corev-dv arithmetic test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_instr_test: - description: Generated corev-dv random instruction test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_test - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_instr_long_stall: - description: Generated corev-dv random instruction test with long stalls - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_long_stall - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_illegal_instr_test: - description: Generated corev-dv random instruction test with illegal instructions - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_illegal_instr_test - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_jump_stress_test: - description: Generated corev-dv jump stress test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_interrupt: - description: Generated corev-dv random interrupt test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_debug: - description: Generated corev-dv random debug test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_debug_single_step: - description: debug random test with single-stepping - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_single_step - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_debug_ebreak: - description: debug random test with ebreaks from ROM - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_ebreak - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_interrupt_wfi: - description: Generated corev-dv random interrupt WFI test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_interrupt_wfi_mem_stress: - description: Generated corev-dv random interrupt WFI test with memory stress - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi_mem_stress - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_interrupt_debug: - description: Generated corev-dv random interrupt WFI test with debug - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_debug - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_interrupt_exception: - description: Generated corev-dv random interrupt WFI test with exceptions - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_exception - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 - - corev_rand_interrupt_nested: - description: Generated corev-dv random interrupt WFI test with random nested interrupts - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_nested - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - num: 5 diff --git a/cv32e40x/regress/cv32e40x_counters_test.yaml b/cv32e40x/regress/cv32e40x_counters_test.yaml deleted file mode 100644 index abb987248f..0000000000 --- a/cv32e40x/regress/cv32e40x_counters_test.yaml +++ /dev/null @@ -1,68 +0,0 @@ -# YAML file to specify a regression testlist -# Note that the COREV=YES is set for all tests in this regression. -# This means you need to have a toolchain at COREV_SW_TOOLCHAIN (see Common.mk) ---- -# Header -name: cv32_counters -description: Performance counters test - -# List of builds -builds: - clone_cv_core_rtl: - cmd: make clone_cv_core_rtl - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x: - cmd: make bsp comp - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_num_mhpmcounter_29: - cmd: make bsp comp - cfg: num_mhpmcounter_29 - dir: cv32e40x/sim/uvmt - -# List of tests -tests: - perf_counters_instructions: - build: uvmt_cv32e40x - description: Performance counter test - dir: cv32e40x/sim/uvmt - cmd: make test COREV=YES TEST=perf_counters_instructions - num: 40 - - mhpmcounter29_csr_access_test_1: - build: uvmt_cv32e40x_num_mhpmcounter_29 - description: Hardware performance counter full access coverage test 1 - builds: [ uvmt_cv32e40x_num_mhpmcounter_29] - dir: cv32e40x/sim/uvmt - cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_1 - num: 40 - - mhpmcounter29_csr_access_test_2: - build: uvmt_cv32e40x_num_mhpmcounter_29 - description: Hardware performance counter full access coverage test 2 - builds: [ uvmt_cv32e40x_num_mhpmcounter_29] - dir: cv32e40x/sim/uvmt - cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_2 - num: 40 - - hpmcounter_basic_test: - build: uvmt_cv32e40x - description: Hardware performance counter basic test - dir: cv32e40x/sim/uvmt - cmd: make test COREV=YES TEST=hpmcounter_basic_test - num: 40 - - hpmcounter_basic_nostall_test: - build: uvmt_cv32e40x - description: Hardware performance counter basic test - no stalls - dir: cv32e40x/sim/uvmt - cmd: make test COREV=YES TEST=hpmcounter_basic_nostall_test - num: 40 - - hpmcounter_hazard_test: - build: uvmt_cv32e40x - description: Hardware performance counter hazard test - dir: cv32e40x/sim/uvmt - cmd: make test COREV=YES TEST=hpmcounter_hazard_test - num: 40 diff --git a/cv32e40x/regress/cv32e40x_debug.yaml b/cv32e40x/regress/cv32e40x_debug.yaml deleted file mode 100644 index 97ca73a43c..0000000000 --- a/cv32e40x/regress/cv32e40x_debug.yaml +++ /dev/null @@ -1,69 +0,0 @@ -# YAML file to specify a regression testlist ---- -# Header -name: cv32_debug_regression -description: Directed and random debug tests for CV32E40X - -# List of builds -builds: - corev-dv: - # required: Make the corev-dv infrastructure - cmd: make comp_corev-dv - dir: cv32e40x/sim/uvmt - cov: 0 - uvmt_cv32e40x: - # required: the make command to create the build - cmd: make comp - dir: cv32e40x/sim/uvmt - -# List of tests -tests: - debug_test: - build: uvmt_cv32e40x - description: Debug directed test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test - num: 10 - - debug_test_reset: - build: uvmt_cv32e40x - description: Debug reset test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test_reset - num: 10 - - debug_test_trigger: - build: uvmt_cv32e40x - description: Debug trigger test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test_trigger - num: 10 - - debug_test_boot_set: - build: uvmt_cv32e40x - description: Debug reset test with random boot set - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test_boot_set - num: 50 - - corev_rand_debug: - build: uvmt_cv32e40x - description: debug random test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug - num: 50 - - corev_rand_debug_single_step: - build: uvmt_cv32e40x - description: debug random test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_single_step - num: 50 - - corev_rand_debug_ebreak: - build: uvmt_cv32e40x - description: debug random test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_ebreak - num: 50 - diff --git a/cv32e40x/regress/cv32e40x_full.yaml b/cv32e40x/regress/cv32e40x_full.yaml deleted file mode 100644 index 1f005c8d9a..0000000000 --- a/cv32e40x/regress/cv32e40x_full.yaml +++ /dev/null @@ -1,431 +0,0 @@ -# YAML file to specify a regression testlist -# Note that the is set for all tests in this regression. -# This means you need to have a toolchain at COREV_SW_TOOLCHAIN (see Common.mk) ---- -# Header -name: cv32_full_covg -description: Full regression (all tests) for CV32E40X with step-and-compare against RM" - -# List of builds -builds: - clone_riscv-dv: - cmd: make clone_riscv-dv - dir: cv32e40x/sim/uvmt - - clone_svlib: - cmd: make clone_svlib - dir: cv32e40x/sim/uvmt - - clone_cv_core_rtl: - cmd: make clone_cv_core_rtl - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x: - cmd: make comp_corev-dv comp - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_b_ext_abs: - cmd: make comp_corev-dv comp - cfg: b_ext_abs - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_b_ext_all: - cmd: make comp_corev-dv comp - cfg: b_ext_all - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma: - cmd: make comp_corev-dv comp - cfg: pma - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_num_mhpmcounter_29: - cmd: make comp_corev-dv comp - cfg: num_mhpmcounter_29 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_1: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_1 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_2: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_2 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_3: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_3 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_4: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_4 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_5: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_5 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_no_bitmanip: - cmd: make comp_corev-dv comp - cfg: no_bitmanip - dir: cv32e40x/sim/uvmt - -# List of tests -tests: - hello-world: - description: uvm_hello_world_test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hello-world - - csr_instructions: - description: CSR instruction test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=csr_instructions - - generic_exception_test: - description: Generic exception test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=generic_exception_test - - illegal_instr_test: - description: Illegal instruction test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=illegal_instr_test - - branch_zero: - description: Branch test with zero offsets - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=branch_zero - - cv32e40x_csr_access_test: - description: CSR Access Mode Test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=cv32e40x_csr_access_test - - cv32e40x_readonly_csr_access_test: - description: CSR Read-only Access Mode Test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=cv32e40x_readonly_csr_access_test - - requested_csr_por: - description: CSR PoR test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=requested_csr_por - - modeled_csr_por: - description: Modeled CSR PoR test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=modeled_csr_por - - csr_instr_asm: - description: CSR instruction assembly test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=csr_instr_asm - - perf_counters_instructions: - description: Performance counter test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=perf_counters_instructions - - mhpmcounter29_csr_access_test_1: - description: Hardware performance counter full access coverage test 1 - builds: [ uvmt_cv32e40x_num_mhpmcounter_29 ] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=mhpmcounter29_csr_access_test_1 - - mhpmcounter29_csr_access_test_2: - description: Hardware performance counter full access coverage test 2 - builds: [ uvmt_cv32e40x_num_mhpmcounter_29 ] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=mhpmcounter29_csr_access_test_2 - - hpmcounter_basic_test: - description: Hardware performance counter basic test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hpmcounter_basic_test - - hpmcounter_basic_nostall_test: - description: Hardware performance counter basic test with no random stalls - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hpmcounter_basic_nostall_test - - hpmcounter_hazard_test: - description: Hardware performance counter hazard test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hpmcounter_hazard_test - - riscv_ebreak_test_0: - description: Static corev-dv ebreak - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=riscv_ebreak_test_0 - - riscv_arithmetic_basic_test_0: - description: Static riscv-dv arithmetic test 0 - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=riscv_arithmetic_basic_test_0 - num: 1 - - riscv_arithmetic_basic_test_1: - description: Static riscv-dv arithmetic test 1 - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=riscv_arithmetic_basic_test_1 - num: 1 - - corev_rand_arithmetic_base_test: - description: Generated corev-dv arithmetic test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test - num: 4 - - corev_rand_instr_test: - description: Generated corev-dv random instruction test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_test - num: 5 - - corev_rand_instr_long_stall: - description: Generated corev-dv random instruction test with long stalls - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_long_stall - num: 2 - - corev_rand_illegal_instr_test: - description: Generated corev-dv random instruction test with illegal instructions - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_illegal_instr_test - num: 5 - - corev_rand_jump_stress_test: - description: Generated corev-dv jump stress test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test - num: 5 - - corev_rand_interrupt: - description: Generated corev-dv random interrupt test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt - num: 5 - - corev_rand_debug: - description: Generated corev-dv random debug test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug - num: 5 - - corev_rand_debug_single_step: - description: debug random test with single-stepping - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_single_step - num: 5 - - corev_rand_debug_ebreak: - description: debug random test with ebreaks from ROM - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_ebreak - num: 5 - - corev_rand_interrupt_wfi: - description: Generated corev-dv random interrupt WFI test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi - num: 5 - - corev_rand_fencei: - description: Generated corev-dv random fence,i test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_fencei - num: 2 - - corev_rand_interrupt_wfi_mem_stress: - description: Generated corev-dv random interrupt WFI test with memory stress - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi_mem_stress - num: 5 - - corev_rand_interrupt_debug: - description: Generated corev-dv random interrupt WFI test with debug - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_debug - num: 5 - - corev_rand_interrupt_exception: - description: Generated corev-dv random interrupt WFI test with exceptions - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_exception - num: 5 - - corev_rand_interrupt_nested: - description: Generated corev-dv random interrupt WFI test with random nested interrupts - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_nested - num: 5 - - corev_rand_pma_test: - description: Generated corev-dv random PMA test - builds: [ uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pma_test - num: 3 - - corev_rand_instr_obi_err: - description: Random OBI instruction bus error test - builds: [ uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_obi_err - num: 6 - - corev_rand_instr_obi_err_debug: - description: Random OBI instruction bus error test with debug - builds: [ uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_obi_err_debug - num: 6 - - corev_rand_data_obi_err: - description: Random OBI data bus error test - builds: [ uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err - num: 6 - - corev_rand_data_obi_err_debug: - description: Random OBI data bus error test with debug - builds: [ uvmt_cv32e40x_pma_1, uvmt_cv32e40x_pma_2, uvmt_cv32e40x_pma_3, uvmt_cv32e40x_pma_4, uvmt_cv32e40x_pma_5, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err_debug - num: 6 - - illegal: - description: Illegal-riscv-tests - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=illegal - - fibonacci: - description: Fibonacci test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=fibonacci - - misalign: - description: Misalign test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=misalign - - dhrystone: - description: Dhrystone test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=dhrystone - - debug_test: - description: Debug Test 1 - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test - - debug_test_reset: - description: Debug reset test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test_reset - - debug_test_trigger: - description: Debug trigger test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test_trigger - - debug_test_boot_set: - description: Debug test target debug_req at BOOT_SET - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test_boot_set - num: 10 - - interrupt_bootstrap: - description: Interrupt bootstrap test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=interrupt_bootstrap - - interrupt_test: - description: Interrupt test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=interrupt_test - - isa_fcov_holes: - description: ISA function coverage test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=isa_fcov_holes - - instr_bus_error: - description: Directed instruction bus error test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=instr_bus_error - - data_bus_error: - description: Directed data bus error test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=data_bus_error - - load_store_rs1_zero: - description: Directed rs1 coverage test - builds: [ uvmt_cv32e40x, uvmt_cv32e40x_no_bitmanip] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=load_store_rs1_zero - - pma: - description: ISA function coverage test - builds: [ uvmt_cv32e40x_pma] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=isa_fcov_holes - - b_ext_test: - description: Directed Zb extension test - builds: [ uvmt_cv32e40x_b_ext_abs, uvmt_cv32e40x_b_ext_all] - dir: cv32e40x/sim/uvmt - cmd: make test TEST=b_ext_test - diff --git a/cv32e40x/regress/cv32e40x_hello_world.yaml b/cv32e40x/regress/cv32e40x_hello_world.yaml deleted file mode 100644 index a28f51e63c..0000000000 --- a/cv32e40x/regress/cv32e40x_hello_world.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# YAML file to specify the ci_check regression testlist. -name: cv32e40x_ci_check -description: Commit sanity for the cv32e40x - -builds: - corev-dv: - cmd: make comp_corev-dv - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x: - cmd: make comp - dir: cv32e40x/sim/uvmt - -tests: - hello-world: - build: uvmt_cv32e40x - description: UVM Hello World Test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hello-world - num: 100 diff --git a/cv32e40x/regress/cv32e40x_interrupt.yaml b/cv32e40x/regress/cv32e40x_interrupt.yaml deleted file mode 100644 index c68b6fa399..0000000000 --- a/cv32e40x/regress/cv32e40x_interrupt.yaml +++ /dev/null @@ -1,73 +0,0 @@ -# YAML file to specify a regression testlist ---- -# Header -name: cv32_interrupt -description: Directed and random interrupt tests for CV32E40X - -# List of builds -builds: - corev-dv: - # required: Make the corev-dv infrastructure - cmd: make comp_corev-dv - dir: cv32e40x/sim/uvmt - cov: 0 - uvmt_cv32e40x: - # required: the make command to create the build - cmd: make comp - dir: cv32e40x/sim/uvmt - -# List of tests -tests: - interrupt_test: - build: uvmt_cv32e40x - description: Interrupt directed test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=interrupt_test - - interrupt_bootstrap: - build: uvmt_cv32e40x - description: Interrupt directed bootstrap - dir: cv32e40x/sim/uvmt - cmd: make test TEST=interrupt_bootstrap - - corev_rand_interrupt: - build: uvmt_cv32e40x - description: Interrupt random test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt - num: 50 - - # corev_rand_interrupt_debug: - # build: uvmt_cv32e40x - # description: Interrupt random test with debug - # dir: cv32e40x/sim/uvmt - # cmd: make gen_corev-dv test TEST=corev_rand_interrupt_debug - # num: 50 - - # corev_rand_interrupt_exception: - # build: uvmt_cv32e40x - # description: Interrupt random test with exceptions - # dir: cv32e40x/sim/uvmt - # cmd: make gen_corev-dv test TEST=corev_rand_interrupt_exception - # num: 50 - - # corev_rand_interrupt_nested: - # build: uvmt_cv32e40x - # description: Interrupt random test with nested interrupts and WFI - # dir: cv32e40x/sim/uvmt - # cmd: make gen_corev-dv test TEST=corev_rand_interrupt_nested - # num: 50 - - corev_rand_interrupt_wfi: - build: uvmt_cv32e40x - description: Interrupt random test with WFI - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi - num: 50 - - corev_rand_interrupt_wfi_mem_stress: - build: uvmt_cv32e40x - description: Interrupt random test with WFI - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi_mem_stress - num: 50 diff --git a/cv32e40x/regress/cv32e40x_obi_bus_err.yaml b/cv32e40x/regress/cv32e40x_obi_bus_err.yaml deleted file mode 100644 index 55a7ec1a3b..0000000000 --- a/cv32e40x/regress/cv32e40x_obi_bus_err.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# YAML file to specify the ci_check regression testlist. -name: cv32e40x_obi_bus_err -description: OBI bus error regression - -builds: - corev-dv: - cmd: make comp_corev-dv - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x: - cmd: make comp - dir: cv32e40x/sim/uvmt - -tests: - corev_rand_instr_obi_err: - build: uvmt_cv32e40x - description: Random OBI instruction bus error test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_obi_err - num: 20 - - corev_rand_instr_obi_err_debug: - build: uvmt_cv32e40x - description: Random OBI instruction bus error test with debug - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_instr_obi_err_debug - num: 20 - - corev_rand_data_obi_err: - build: uvmt_cv32e40x - description: Random OBI data bus error test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err - num: 20 - - corev_rand_data_obi_err_debug: - build: uvmt_cv32e40x - description: Random OBI data bus error test with debug - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err_debug - num: 20 diff --git a/cv32e40x/regress/cv32e40x_pma.yaml b/cv32e40x/regress/cv32e40x_pma.yaml deleted file mode 100644 index c3ccf0b33b..0000000000 --- a/cv32e40x/regress/cv32e40x_pma.yaml +++ /dev/null @@ -1,31 +0,0 @@ -# YAML file to specify a regression testlist -# Note that the is set for all tests in this regression. -# This means you need to have a toolchain at COREV_SW_TOOLCHAIN (see Common.mk) ---- -# Header -name: cv32e40x_pma -description: PMA instruction stream tests - -# List of builds -builds: - clean_fw: - cmd: make clean_bsp clean_test_programs - dir: cv32e40x/sim/uvmt - - corev-dv: - cmd: make clean_riscv-dv comp_corev-dv - dir: cv32e40x/sim/uvmt - cov: 0 - uvmt_cv32e40x: - cmd: make comp - dir: cv32e40x/sim/uvmt - - -# List of tests -tests: - corev_rand_pma_test: - build: uvmt_cv32e40x - description: Generated corev-dv pma test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_pma_test - num: 20 diff --git a/cv32e40x/regress/cv32e40x_rel_check.yaml b/cv32e40x/regress/cv32e40x_rel_check.yaml deleted file mode 100644 index 79a1a41705..0000000000 --- a/cv32e40x/regress/cv32e40x_rel_check.yaml +++ /dev/null @@ -1,301 +0,0 @@ -# YAML file to specify a regression testlist ---- -# Header -name: cv32e40x_full -description: Release regression for CV32E40X - -# List of builds -builds: - clone_riscv-dv: - cmd: make clone_riscv-dv - dir: cv32e40x/sim/uvmt - - clone_svlib: - cmd: make clone_svlib - dir: cv32e40x/sim/uvmt - - clone_cv_core_rtl: - cmd: make clone_cv_core_rtl - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x: - cmd: make comp_corev-dv comp - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_1: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_1 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_2: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_2 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_3: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_3 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_4: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_4 - dir: cv32e40x/sim/uvmt - - uvmt_cv32e40x_pma_5: - cmd: make comp_corev-dv comp - cfg: pma_test_cfg_5 - dir: cv32e40x/sim/uvmt - -# List of tests -tests: - hello-world: - build: uvmt_cv32e40x - description: uvm_hello_world_test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hello-world - - csr_instructions: - build: uvmt_cv32e40x - description: CSR instruction test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=csr_instructions - - generic_exception_test: - build: uvmt_cv32e40x - description: Generic exception test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=generic_exception_test - - illegal_instr_test: - build: uvmt_cv32e40x - description: Illegal instruction test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=illegal_instr_test - - requested_csr_por: - build: uvmt_cv32e40x - description: CSR PoR test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=requested_csr_por - - modeled_csr_por: - build: uvmt_cv32e40x - description: Modeled CSR PoR test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=modeled_csr_por - - csr_instr_asm: - build: uvmt_cv32e40x - description: CSR instruction assembly test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=csr_instr_asm - - perf_counters_instructions: - build: uvmt_cv32e40x - description: Performance counter test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=perf_counters_instructions - - hpmcounter_basic_test: - build: uvmt_cv32e40x - description: Hardware performance counter basic test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hpmcounter_basic_test - makearg: USER_RUN_FLAGS=+rand_stall_obi_disable - - hpmcounter_hazard_test: - build: uvmt_cv32e40x - description: Hardware performance counter hazard test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=hpmcounter_hazard_test - makearg: USER_RUN_FLAGS=+rand_stall_obi_disable - - riscv_ebreak_test_0: - build: uvmt_cv32e40x - description: Static corev-dv ebreak - dir: cv32e40x/sim/uvmt - cmd: make test TEST=riscv_ebreak_test_0 - - riscv_arithmetic_basic_test_0: - build: uvmt_cv32e40x - description: Static riscv-dv arithmetic test 0 - dir: cv32e40x/sim/uvmt - cmd: make test TEST=riscv_arithmetic_basic_test_0 - num: 1 - - riscv_arithmetic_basic_test_1: - build: uvmt_cv32e40x - description: Static riscv-dv arithmetic test 1 - dir: cv32e40x/sim/uvmt - cmd: make test TEST=riscv_arithmetic_basic_test_1 - num: 1 - - illegal: - build: uvmt_cv32e40x - description: Illegal-riscv-tests - dir: cv32e40x/sim/uvmt - cmd: make test TEST=illegal - - fibonacci: - build: uvmt_cv32e40x - description: Fibonacci test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=fibonacci - - misalign: - build: uvmt_cv32e40x - description: Misalign test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=misalign - - dhrystone: - build: uvmt_cv32e40x - description: Dhrystone test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=dhrystone - - debug_test: - build: uvmt_cv32e40x - description: Debug Test 1 - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test - makearg: USER_RUN_FLAGS=+rand_stall_obi_disable - - debug_test_reset: - build: uvmt_cv32e40x - description: Debug reset test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=debug_test_reset - - interrupt_bootstrap: - build: uvmt_cv32e40x - description: Interrupt bootstrap test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=interrupt_bootstrap - - interrupt_test: - build: uvmt_cv32e40x - description: Interrupt test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=interrupt_test - - isa_fcov_holes: - build: uvmt_cv32e40x - description: ISA function coverage test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=isa_fcov_holes - - cv32e40x_csr_access_test: - build: uvmt_cv32e40x - description: Randomly generated CSR access test - dir: cv32e40x/sim/uvmt - cmd: make test TEST=cv32e40x_csr_access_test - - cv32e40x_readonly_csr_access_test: - build: uvmt_cv32e40x - description: Manually generated CSR access test of RO CSRs - dir: cv32e40x/sim/uvmt - cmd: make test TEST=cv32e40x_readonly_csr_access_test - - corev_rand_arithmetic_base_test: - build: uvmt_cv32e40x - description: Generated corev-dv arithmetic test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test - num: 2 - - corev_rand_instr_test: - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - description: Generated corev-dv random instruction test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_instr_test - num: 1 - - corev_rand_illegal_instr_test: - build: uvmt_cv32e40x - description: Generated corev-dv random instruction test with illegal instructions - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_illegal_instr_test - num: 2 - - corev_rand_jump_stress_test: - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - description: Generated corev-dv jump stress test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test - num: 1 - - corev_rand_interrupt: - build: uvmt_cv32e40x - description: Generated corev-dv random interrupt test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt - num: 2 - - corev_rand_debug: - builds: - - uvmt_cv32e40x - - uvmt_cv32e40x_pma_1 - - uvmt_cv32e40x_pma_2 - - uvmt_cv32e40x_pma_3 - - uvmt_cv32e40x_pma_4 - - uvmt_cv32e40x_pma_5 - description: Generated corev-dv random debug test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug - num: 1 - - corev_rand_debug_single_step: - build: uvmt_cv32e40x - description: debug random test with single-stepping - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_single_step - num: 1 - - corev_rand_debug_ebreak: - build: uvmt_cv32e40x - description: debug random test with ebreaks from ROM - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_debug_ebreak - num: 2 - - corev_rand_interrupt_wfi: - build: uvmt_cv32e40x - description: Generated corev-dv random interrupt WFI test - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi - num: 1 - - corev_rand_interrupt_debug: - build: uvmt_cv32e40x - description: Generated corev-dv random interrupt WFI test with debug - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_debug - num: 1 - - corev_rand_interrupt_exception: - build: uvmt_cv32e40x - description: Generated corev-dv random interrupt WFI test with exceptions - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_exception - num: 1 - - corev_rand_interrupt_nested: - build: uvmt_cv32e40x - description: Generated corev-dv random interrupt WFI test with random nested interrupts - dir: cv32e40x/sim/uvmt - cmd: make gen_corev-dv test TEST=corev_rand_interrupt_nested - num: 1 diff --git a/cv32e40x/sim/ExternalRepos.mk b/cv32e40x/sim/ExternalRepos.mk deleted file mode 100644 index 0d205c72d4..0000000000 --- a/cv32e40x/sim/ExternalRepos.mk +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################### -# Variables to determine the the command to clone external repositories. -# For each repo there are a set of variables: -# *_REPO: URL to the repository in GitHub. -# *_BRANCH: Name of the branch you wish to clone; -# Set to 'master' to pull the master branch. -# *_HASH: Value of the specific hash you wish to clone; -# Set to 'head' to pull the head of the branch you want. -# THe CV32E40X repo also has a variable to clone a specific tag: -# *_TAG: Value of the specific tag you wish to clone; -# Will override the HASH unless set to "none". -# - -export SHELL = /bin/bash - -CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40x -CV_CORE_BRANCH ?= master -CV_CORE_HASH ?= 1d56e0e1eae6925c62fbbf2fea8a3fe155ac802a -CV_CORE_TAG ?= none - -# RISCVDV_REPO ?= https://github.com/google/riscv-dv -# RISCVDV_BRANCH ?= master -# RISCVDV_HASH ?= 96c1ee6f371f2754c45b4831fcab95f6671689d9 - -# TODO: silabs-hfegran, remove this temporary fix when riscv-dv changes get upstreamed -RISCVDV_REPO ?= https://github.com/silabs-hfegran/riscv-dv.git -RISCVDV_BRANCH ?= dev_hf_rvdv_csr_updates -RISCVDV_HASH ?= 87d9ae2d60d928e3c6afcd6ff1aacb5298f2904b - -EMBENCH_REPO ?= https://github.com/embench/embench-iot.git -EMBENCH_BRANCH ?= master -EMBENCH_HASH ?= 6934ddd1ff445245ee032d4258fdeb9828b72af4 - -COMPLIANCE_REPO ?= https://github.com/strichmo/riscv-arch-test.git -COMPLIANCE_BRANCH ?= strichmo/pr/cv32e40x_initial_old_compliance -# 2020-08-19 -COMPLIANCE_HASH ?= cf29051b177ba61b8c39de91c33d20d202697423 - -# This Spike repo is only cloned when the DPI disassembler needs to be rebuilt -# Typically users can simply use the checked-in shared library -DPI_DASM_SPIKE_REPO ?= https://github.com/riscv/riscv-isa-sim.git -DPI_DASM_SPIKE_BRANCH ?= master -DPI_DASM_SPIKE_HASH ?= 8faa928819fb551325e76b463fc0c978e22f5be3 - -# SVLIB -SVLIB_REPO ?= https://bitbucket.org/verilab/svlib/src/master/svlib -SVLIB_BRANCH ?= master -SVLIB_HASH ?= c25509a7e54a880fe8f58f3daa2f891d6ecf6428 diff --git a/cv32e40x/sim/README.md b/cv32e40x/sim/README.md deleted file mode 100644 index 3b5b0b7929..0000000000 --- a/cv32e40x/sim/README.md +++ /dev/null @@ -1,33 +0,0 @@ -## SIM directory -The directories from which you should launch your interactive simulations and -regressions are the `core` and `uvmt` directories located here. - -### Cloning the RTL -The Makefiles will automatically clone the required RTL to `../../core-v-cores/cv32e40x`, -unless the CV_CORE_PATH parameter is set. -If the CV_CORE_PATH is set, a symlink to this path will be created in `../../core-v-cores/` instead of cloning the repo. -This allows for working on the RTL in a separate environment. -

-There are user variables -in `./ExternalRepos.mk` that control the URL, branch and hash of the cloned code - see -the comment header for examples. The defaults for these variables will clone the -most up-to-date and stable version of the RTL. Note that this is not always the -head of the master branch. - -### Simulation Directories -There is a sub-dir for each supported CV32E40X verification environment. -Each sub-dir has its specific Makefile and both include `Common.mk` from this -directory. - -#### core -The Makefile will run the SystemVerilog testbench found in `../tb/core` and -its associated tests from `../tests/core`. This testbench and tests were -inherited from the PULP-Platform team and have been modified only slightly. - -#### uvmt -The Makefile will run the SystemVerilog/UVM verification environment found in -`../tb/uvmt` and the associated tests from `../tests/uvmt`. - -#### tools -Tool specific sub-dirs for some of the tools used in the CV32E40X. -For example, Tcl control files for waveform viewing support. diff --git a/cv32e40x/sim/core/.gitignore b/cv32e40x/sim/core/.gitignore deleted file mode 100644 index 2129b33822..0000000000 --- a/cv32e40x/sim/core/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -cobj_dir -memory_dump.bin -testbench_verilator -results diff --git a/cv32e40x/sim/core/Makefile b/cv32e40x/sim/core/Makefile deleted file mode 100644 index 80d1fd4546..0000000000 --- a/cv32e40x/sim/core/Makefile +++ /dev/null @@ -1,662 +0,0 @@ -############################################################################### -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -############################################################################### -# -# Makefile for the CV_CORE "core" testbench. Substantially modified from the -# Makefile original for the RI5CY testbench. -# -############################################################################### -# -# Copyright 2019 Claire Wolf -# Copyright 2019 Robert Balas -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH -# REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY -# AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, -# INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM -# LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -# PERFORMANCE OF THIS SOFTWARE. -# -# Original Author: Robert Balas (balasr@iis.ee.ethz.ch) -# -############################################################################### - -# "Constants" -MAKE = make -MAKE_DIR = $(PWD) -MAKE_PATH := $(shell dirname $(realpath $(firstword $(MAKEFILE_LIST)))) -COREV_PROJ = cv32 -CORE_V_VERIF = $(abspath $(MAKE_PATH)/../../..) -DATE = $(shell date +%F) -WAVES = 0 - -CV_CORE ?= CV32E40X -CV_CORE_LC = $(shell echo $(CV_CORE) | tr A-Z a-z) -CV_CORE_UC = $(shell echo $(CV_CORE) | tr a-z A-Z) - -# Compile compile flags for all simulators -SV_CMP_FLAGS = - -# Default "custom test-program" -CUSTOM_PROG ?= requested_csr_por -TEST ?= hello-world - -############################################################################### -# Common Makefiles: -# -Variables for RTL and other dependencies (e.g. RISCV-DV) -include ../ExternalRepos.mk -# -Core Firmware and the RISCV GCC Toolchain (SDK) -include $(CORE_V_VERIF)/mk/Common.mk - -# vsim configuration -VVERSION = "10.7b" - -VLIB = vlib -VWORK = work - -VLOG = vlog -VLOG_FLAGS = -pedanticerrors -suppress 2577 -suppress 2583 -VLOG_LOG = vloggy - -VOPT = vopt -VOPT_FLAGS = -debugdb -fsmdebug -pedanticerrors +acc #=mnprft - -VSIM = vsim -VSIM_HOME = /usr/pack/modelsim-$(VVERSION)-kgf/questasim -VSIM_FLAGS ?= # user defined -ALL_VSIM_FLAGS = $(VSIM_FLAGS) -VSIM_DEBUG_FLAGS = -debugdb -VSIM_GUI_FLAGS = -gui -debugdb -VSIM_SCRIPT_DIR = ../tools/vsim -VSIM_SCRIPT = $(VSIM_SCRIPT_DIR)/vsim.tcl - -# vcs configuration (hopelessly out of date) -VCS_VERSION = O-2018.09-SP1-1 -VCS_HOME = /opt/synopsys/vcs-mx/$(VCS_VERSION) -VCS = vcs -VCS_FLAGS ?= # user defined -ALL_VCS_FLAGS = $(VCS_FLAGS) -VCS_SCRIPT_DIR = ../tools/vcs -VCS_SCRIPT = $(VCS_SCRIPT_DIR)/vcs_batch.tcl -VCS_SCRIPT_GUI = $(VCS_SCRIPT_DIR)/vcs.tcl -SIMV = ./simv - -# dsim is the Metrics Technologies SystemVerilog simulator (https://metrics.ca/) -DSIM = dsim -DSIM_HOME = /tools/Metrics/dsim -DSIM_CMP_FLAGS = +define+CORE_TB+COREV_ASSERT_OFF -timescale 1ns/1ps $(SV_CMP_FLAGS) -suppress MultiBlockWrite +define+CV32E40X_APU_TRACE -DSIM_RUN_FLAGS = -write-sql -DSIM_UVM_ARGS = +incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm_pkg.sv -DSIM_RESULTS ?= $(PWD)/dsim_results -DSIM_WORK ?= $(DSIM_RESULTS)/dsim_work -DSIM_IMAGE = dsim.out - -ifneq (${WAVES}, 0) - DSIM_CMP_FLAGS += +acc+b - DSIM_DMP_FILE ?= dsim.fst - DSIM_RUN_FLAGS += -waves $(DSIM_DMP_FILE) +disass +disass_display -endif - -# xrun is the Cadence xcelium SystemVerilog simulator (https://cadence.com/) -XRUN = xrun -XRUN_FLAGS = -clean -smartorder -sv -top worklib.tb_top -timescale 1ns/1ps +define+CV32E40X_APU_TRACE -uvmhome CDNS-1.2-ML -XRUN_DIR = xcelium.d - -# verilator configuration -VERILATOR = verilator -VERI_FLAGS += -VERI_COMPILE_FLAGS += -Wno-BLKANDNBLK +define+COREV_ASSERT_OFF $(SV_CMP_FLAGS) # hope this doesn't hurt us in the long run -VERI_TRACE ?= -VERI_OBJ_DIR ?= cobj_dir -VERI_LOG_DIR ?= cobj_dir/logs -VERI_CFLAGS += -O2 - -#riviera configuration - -ALIB = "vlib" -AWORK = work - -ALOG = vlog -ALOG_DEBUG = -dbg -ALOG_FLAGS = -ALOG_UVM = -uvmver 1.2 - -ASIM = vsim -ASIM_HOME = $(ALDEC_PATH) -ASIM_FLAGS ?= # user defined -ALL_ASIM_FLAGS = $(ASIM_FLAGS) -ASIM_DEBUG_FLAGS = -dbg -ASIM_GUI_FLAGS = -gui - -# TB source files for the CV32E core -TBSRC_HOME := $(CORE_V_VERIF)/$(CV_CORE_LC)/tb -TBSRC_TOP := $(TBSRC_HOME)/core/tb_top.sv -TBSRC_CORE := $(TBSRC_HOME)/core -TBSRC_PKG := $(TBSRC_CORE)/tb_riscv/include/perturbation_defines.sv -TBSRC := $(TBSRC_CORE)/tb_top.sv \ - $(TBSRC_CORE)/cv32e40x_tb_wrapper.sv \ - $(TBSRC_CORE)/mm_ram.sv \ - $(TBSRC_CORE)/dp_ram.sv \ - $(TBSRC_CORE)/tb_riscv/riscv_random_stall.sv \ - $(TBSRC_CORE)/tb_riscv/riscv_random_interrupt_generator.sv \ - $(TBSRC_CORE)/tb_riscv/riscv_rvalid_stall.sv \ - $(TBSRC_CORE)/tb_riscv/riscv_gnt_stall.sv - -#/tb_riscv/riscv_rvalid_stall.sv - -RTLSRC_VLOG_TB_TOP := $(basename $(notdir $(TBSRC_TOP))) -RTLSRC_VOPT_TB_TOP := $(addsuffix _vopt, $(RTLSRC_VLOG_TB_TOP)) - -TBSRC_VERI := $(TBSRC_CORE)/tb_top_verilator.sv \ - $(TBSRC_CORE)/cv32e40x_tb_wrapper.sv \ - $(TBSRC_CORE)/tb_riscv/riscv_rvalid_stall.sv \ - $(TBSRC_CORE)/tb_riscv/riscv_gnt_stall.sv \ - $(TBSRC_CORE)/mm_ram.sv \ - $(TBSRC_CORE)/dp_ram.sv -SIM_LIBS := $(CORE_V_VERIF)/lib/sim_libs - -# RTL source files for the CV32E core -# DESIGN_RTL_DIR is used by CV_CORE_MANIFEST file -CV_CORE_PKG := $(CORE_V_VERIF)/core-v-cores/$(CV_CORE_LC) -CV_CORE_RTLSRC_INCDIR := $(CV_CORE_PKG)/rtl/include -CV_CORE_RTLSRC_PKG := $(CV_CORE_PKG)/rtl/fpnew/src/fpnew_pkg.sv \ - $(addprefix $(CV_CORE_RTLSRC_INCDIR)/,\ - CV_CORE_apu_core_package.sv CV_CORE_defines.sv \ - CV_CORE_tracer_defines.sv) -CV_CORE_RTLSRC := $(filter-out $(CV_CORE_PKG)/rtl/$(CV_CORE_LC)_register_file_latch.sv, \ - $(wildcard $(CV_CORE_PKG)/rtl/*.sv)) -# FIXME: temporarily using a local manifest for the core. -# This is BAD PRACTICE and will be fixed with -# https://github.com/openhwgroup/CV_CORE/pull/421 is resolved. -CV_CORE_MANIFEST := $(CV_CORE_PKG)/cv32e40x_manifest.flist -export DESIGN_RTL_DIR = $(CV_CORE_PKG)/rtl - -# Shorthand rules for convience -CV_CORE_pkg: clone_$(CV_CORE_LC)_rtl - -tbsrc_pkg: $(TBSRC_PKG) - -tbsrc: $(TBSRC) - -############################################################################### - -SIMULATOR ?= vcs - -.PHONY: hello-world -hello-world: $(SIMULATOR)-hello-world - -.PHONY: cv32_riscv_tests -cv32_riscv_tests: $(SIMULATOR)-cv32_riscv_tests - -.PHONY: cv32_riscv_tests-gui -cv32_riscv_tests-gui: $(SIMULATOR)-cv32_riscv_tests-gui - -.PHONY: cv32_riscv_compliance_tests -cv32_riscv_compliance_tests: $(SIMULATOR)-cv32_riscv_compliance_tests - -.PHONY: cv32_riscv_compliance_tests-gui -cv32_riscv_compliance_tests-gui: $(SIMULATOR)-cv32_riscv_compliance_tests-gui - -.PHONY: firmware -firmware: $(SIMULATOR)-firmware - -.PHONY: firmware-gui -firmware-gui: $(SIMULATOR)-firmware-gui - -.PHONY: unit-test -unit-test: $(SIMULATOR)-unit-test - -.PHONY: unit-test-gui -unit-test-gui: $(SIMULATOR)-unit-test-gui - -# assume verilator if no target chosen -.DEFAULT_GOAL := sanity-veri-run - -all: clean_all sanity-veri-run dsim-sanity - -############################################################################### -# Metrics DSIM -.PHONY: dsim-comp dsim-comp-rtl-only - -MKDIR_P = mkdir -p - -mk_results: - $(MKDIR_P) $(DSIM_RESULTS) - $(MKDIR_P) $(DSIM_WORK) - -# Metrics dsim compile targets -dsim-comp: mk_results CV_CORE_pkg tbsrc_pkg tbsrc - cd $(DSIM_RESULTS) && \ - $(DSIM) \ - $(DSIM_CMP_FLAGS) \ - $(DSIM_UVM_ARGS) \ - -f $(CV_CORE_MANIFEST) \ - $(TBSRC_PKG) \ - $(TBSRC) \ - -work $(DSIM_WORK) \ - -genimage $(DSIM_IMAGE) - -dsim-comp-rtl-only: mk_results $(CV_CORE_PKG) - $(DSIM) \ - $(DSIM_CMP_FLAGS) \ - -f $(CV_CORE_MANIFEST) \ - -work $(DSIM_WORK) \ - -genimage $(DSIM_IMAGE) - - -# Metrics dsim simulations -.PHONY: dsim-hello-world dsim-firmware - -dsim-sanity: dsim-test - -dsim-custom: - @echo "This target is depreciated. Please use 'make dsim-test TEST='" - @echo " Example: 'make dsim-test TEST=fibonacci'" - -dsim-test: dsim-comp $(VERI_CUSTOM)/$(TEST)/$(TEST).hex - @echo "$(BANNER)" - @echo "* Running with Metrics DSIM" - @echo "$(BANNER)" - mkdir -p $(DSIM_RESULTS)/$(TEST) && cd $(DSIM_RESULTS)/$(TEST) && \ - $(DSIM) -l dsim-$(TEST).log \ - -image $(DSIM_IMAGE) \ - -work $(DSIM_WORK) \ - $(DSIM_RUN_FLAGS) \ - -sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so \ - -sv_lib $(OVP_MODEL_DPI) \ - +firmware=../../$(VERI_CUSTOM)/$(TEST)/$(TEST).hex - -# Metrics dsim cleanup -.PHONY: dsim-clean - -dsim-clean: tc-clean - rm -f dsim.log - rm -f dsim-*.log - rm -f metrics_history.db - rm -f metrics.xml - rm -f trace_core_00_0.log - rm -rf dsim_work - rm -f dsim.env - rm -f $(DSIM_IMAGE) - rm -rf $(uIM_RESULTS) - -############################################################################### -# Mentor Questasim - - -.lib-rtl: - $(VLIB) $(VWORK) - touch .lib-rtl - - -.build-rtl: .lib-rtl $(CV_CORE_PKG) $(TBSRC_PKG) $(TBSRC) - $(VLOG) \ - -work $(VWORK) \ - $(VLOG_FLAGS) \ - -f $(CV_CORE_MANIFEST) \ - $(TBSRC_PKG) $(TBSRC) - - -vsim-all: .opt-rtl - - -.opt-rtl: .build-rtl - $(VOPT) -work $(VWORK) $(VOPT_FLAGS) $(RTLSRC_VLOG_TB_TOP) -o $(RTLSRC_VOPT_TB_TOP) - touch .opt-rtl - -# run tb and exit -.PHONY: vsim-run -vsim-run: ALL_VSIM_FLAGS += -c -vsim-run: vsim-all - $(VSIM) -work $(VWORK) $(DPILIB_VSIM_OPT) $(ALL_VSIM_FLAGS)\ - $(RTLSRC_VOPT_TB_TOP) -do 'source $(VSIM_SCRIPT); exit -f' - - - -# run tb and drop into interactive shell -.PHONY: vsim-run-sh -vsim-run-sh: ALL_VSIM_FLAGS += -c -vsim-run-sh: vsim-all - $(VSIM) -work $(VWORK) $(DPILIB_VSIM_OPT) $(ALL_VSIM_FLAGS) \ - $(RTLSRC_VOPT_TB_TOP) -do $(VSIM_SCRIPT) - -# run tb with simulator gui -.PHONY: vsim-run-gui -vsim-run-gui: ALL_VSIM_FLAGS += $(VSIM_GUI_FLAGS) -vsim-run-gui: vsim-all - $(VSIM) -work $(VWORK) $(DPILIB_VSIM_OPT) $(ALL_VSIM_FLAGS) \ - $(RTLSRC_VOPT_TB_TOP) -do $(VSIM_SCRIPT) - -.PHONY: questa-custom -questa-custom: vsim-all $(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -questa-custom: ALL_VSIM_FLAGS += +firmware=$(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -questa-custom: vsim-run - -.PHONY: questa-custom-gui -questa-custom-gui: vsim-all $(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -questa-custom-gui: ALL_VSIM_FLAGS += +firmware=$(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -questa-custom-gui: vsim-run-gui - -.PHONY: questa-cv32_riscv_tests -questa-cv32_riscv_tests: vsim-all $(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -questa-cv32_riscv_tests: ALL_VSIM_FLAGS += +firmware=$(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -questa-cv32_riscv_tests: vsim-run - -.PHONY: questa-cv32_riscv_tests-gui -questa-cv32_riscv_tests-gui: vsim-all $(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -questa-cv32_riscv_tests-gui: ALL_VSIM_FLAGS += +firmware=$(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -questa-cv32_riscv_tests-gui: vsim-run-gui - -.PHONY: questa-cv32_riscv_compliance_tests -questa-cv32_riscv_compliance_tests: vsim-all $(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -questa-cv32_riscv_compliance_tests: ALL_VSIM_FLAGS += +firmware=$(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -questa-cv32_riscv_compliance_tests: vsim-run - -.PHONY: questa-cv32_riscv_compliance_tests-gui -questa-cv32_riscv_compliance_tests-gui: vsim-all $(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -questa-cv32_riscv_compliance_tests-gui: ALL_VSIM_FLAGS += +firmware=$(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -questa-cv32_riscv_compliance_tests-gui: vsim-run-gui - -.PHONY: questa-firmware -questa-firmware: vsim-all $(FIRMWARE)/firmware.hex -questa-firmware: ALL_VSIM_FLAGS += +firmware=$(FIRMWARE)/firmware.hex -questa-firmware: vsim-run - -.PHONY: questa-firmware-gui -questa-firmware-gui: vsim-all $(FIRMWARE)/firmware.hex -questa-firmware-gui: ALL_VSIM_FLAGS += +firmware=$(FIRMWARE)/firmware.hex -questa-firmware-gui: vsim-run-gui - -.PHONY: questa-unit-test -questa-unit-test: firmware-unit-test-clean -questa-unit-test: $(FIRMWARE)/firmware_unit_test.hex -questa-unit-test: ALL_VSIM_FLAGS += "+firmware=$(FIRMWARE)/firmware_unit_test.hex" -questa-unit-test: vsim-run - -.PHONY: questa-unit-test-gui -questa-unit-test-gui: firmware-unit-test-clean -questa-unit-test-gui: $(FIRMWARE)/firmware_unit_test.hex -questa-unit-test-gui: ALL_VSIM_FLAGS += "+firmware=$(FIRMWARE)/firmware_unit_test.hex" -questa-unit-test-gui: vsim-run-gui - -questa-clean: - if [ -d $(VWORK) ]; then rm -r $(VWORK); fi - rm -f transcript vsim.wlf vsim.dbg trace_core*.log \ - .build-rtl .opt-rtl .lib-rtl *.vcd objdump - -############################################################################### -# Cadence Xcelium xrun testbench compilation -.PHONY: xrun-all -xrun-all: $(CV_CORE_PKG) $(RTLSRC_PKG) $(RTLSRC) $(TBSRC_PKG) $(TBSRC) - $(XRUN) \ - $(XRUN_FLAGS) \ - -f $(CV_CORE_MANIFEST) \ - $(TBSRC_PKG) $(TBSRC) - -xrun-custom: - @echo "This target is depreciated. Please use 'make xrun-test TEST='" - @echo " Example: 'make xrun-test TEST=fibonacci'" - -.PHONY: xrun-test -xrun-test: xrun-all $(VERI_CUSTOM)/$(TEST)/$(TEST).hex - $(XRUN) \ - $(XRUN_FLAGS) \ - -f $(CV_CORE_MANIFEST) \ - $(TBSRC_PKG) $(TBSRC) \ - +firmware=$(VERI_CUSTOM)/$(TEST)/$(CUSTOM_PROG).hex - -# Cadence Xcelium xrun cleanup -.PHONY: xrun-clean xrun-clean-all -xrun-clean: - rm -vrf $(XRUN_DIR) - if [ -e xrun.history ]; then rm xrun.history; fi - if [ -e xrun.log ]; then rm xrun.log; fi - -xrun-clean-all: xrun-clean - rm -vrf $(addprefix $(FIRMWARE)/firmware., elf bin hex map) \ - $(FIRMWARE_OBJS) $(FIRMWARE_TEST_OBJS) $(COMPLIANCE_TEST_OBJS) - -############################################################################### -# Verilator - -# We first test if the user wants to to vcd dumping. This hacky part is required -# because we need to conditionally compile the testbench (-DVCD_TRACE) and pass -# the --trace flags to the verilator call -#ifeq ($(findstring +vcd,$(VERI_FLAGS)),+vcd) - -ifneq (${WAVES}, 0) -VERI_TRACE="--trace" -VERI_CFLAGS+="-DVCD_TRACE" -endif - -verilate: testbench_verilator - -sanity-veri-run: - make veri-test TEST=hello-world - -testbench_verilator: CV_CORE_pkg $(TBSRC_VERI) $(TBSRC_PKG) - @echo "$(BANNER)" - @echo "* Compiling CORE TB and CV32E40X with Verilator" - @echo "$(BANNER)" - $(VERILATOR) --cc --sv --exe \ - $(VERI_TRACE) \ - --Wno-lint --Wno-UNOPTFLAT \ - --Wno-MODDUP --top-module \ - tb_top_verilator $(TBSRC_VERI) \ - -f $(CV_CORE_MANIFEST) \ - $(CV_CORE_PKG)/bhv/$(CV_CORE_LC)_core_log.sv \ - $(TBSRC_CORE)/tb_top_verilator.cpp --Mdir $(VERI_OBJ_DIR) \ - -CFLAGS "-std=gnu++11 $(VERI_CFLAGS)" \ - $(VERI_COMPILE_FLAGS) - $(MAKE) -C $(VERI_OBJ_DIR) -f Vtb_top_verilator.mk - cp $(VERI_OBJ_DIR)/Vtb_top_verilator testbench_verilator - -veri-test: verilate $(VERI_CUSTOM)/$(TEST)/$(TEST).hex - @echo "$(BANNER)" - @echo "* Running with Verilator: logfile in $(VERI_LOG_DIR)/$(TEST).log" - @echo "$(BANNER)" - mkdir -p $(VERI_LOG_DIR) - ./testbench_verilator $(VERI_FLAGS) \ - "+firmware=$(VERI_CUSTOM)/$(TEST)/$(TEST).hex" \ - | tee $(VERI_LOG_DIR)/$(TEST).log - -# verilator specific cleanup -veri-clean: verilate-clean - -verilate-clean: tc-clean - if [ -d $(VERI_LOG_DIR) ]; then rm -r $(VERI_LOG_DIR); fi - if [ -d $(VERI_OBJ_DIR) ]; then rm -r $(VERI_OBJ_DIR); fi - rm -rf testbench_verilator - if [ -e memory_dump.bin ]; then rm memory_dump.bin; fi - - -############################################################################### -# Synopsys VCS - -vcsify: CV_CORE_pkg tbsrc_pkg tbsrc - $(VCS) +vc -sverilog -race=all -ignore unique_checks -full64 \ - -timescale=1ns/1ps \ - -assert svaext \ - -CC "-I$(VCS_HOME)/include -O3 -march=native" $(VCS_FLAGS) \ - -f $(MAKE_DIR)/$(CV_CORE_MANIFEST) \ - $(TBSRC_PKG) $(TBSRC) - -RTLSRC_TB_TOP := $(basename $(notdir $(TBSRC_TOP))) - -vcs-run: vcsify - $(SIMV) $(ALL_VCS_FLAGS) -ucli -do $(VCS_SCRIPT) - -vcs-run-gui: vcsify - $(SIMV) $(ALL_VCS_FLAGS) -gui -do $(VCS_SCRIPT_GUI) - -.PHONY: vcs-hello-world -vcs-hello-world: vcsify $(CUSTOM)/hello-world.hex -vcs-hello-world: ALL_VCS_FLAGS += +firmware=$(CUSTOM)/hello-world.hex -vcs-hello-world: vcs-run - -.PHONY: vcs-custom -vcs-custom: vcsify $(CUSTOM)/$(CUSTOM_PROG).hex -vcs-custom: ALL_VCS_FLAGS += +firmware=$(CUSTOM)/$(CUSTOM_PROG).hex -vcs-custom: vcs-run - -.PHONY: vcs-cv32_riscv_tests -vcs-cv32_riscv_tests: vcsify $(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -vcs-cv32_riscv_tests: ALL_VCS_FLAGS += +firmware=$(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -vcs-cv32_riscv_tests: vcs-run - -.PHONY: vcs-cv32_riscv_tests-gui -vcs-cv32_riscv_tests-gui: vcsify $(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -vcs-cv32_riscv_tests-gui: ALL_VCS_FLAGS += +firmware=$(CV32_RISCV_TESTS_FIRMWARE)/cv32_riscv_tests_firmware.hex -vcs-cv32_riscv_tests-gui: vcs-run-gui - -.PHONY: vcs-cv32_riscv_compliance_tests -vcs-cv32_riscv_compliance_tests: vcsify $(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -vcs-cv32_riscv_compliance_tests: ALL_VCS_FLAGS += +firmware=$(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -vcs-cv32_riscv_compliance_tests: vcs-run - -.PHONY: vcs-cv32_riscv_compliance_tests-gui -vcs-cv32_riscv_compliance_tests-gui: vcsify $(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -vcs-cv32_riscv_compliance_tests-gui: ALL_VCS_FLAGS += +firmware=$(CV32_RISCV_COMPLIANCE_TESTS_FIRMWARE)/cv32_riscv_compliance_tests_firmware.hex -vcs-cv32_riscv_compliance_tests-gui: vcs-run-gui - -.PHONY: vcs-firmware -vcs-firmware: vcsify $(FIRMWARE)/firmware.hex -vcs-firmware: ALL_VCS_FLAGS += +firmware=$(FIRMWARE)/firmware.hex -vcs-firmware: vcs-run - -.PHONY: vcs-firmware-gui -vcs-firmware-gui: vcsify $(FIRMWARE)/firmware.hex -vcs-firmware-gui: ALL_VCS_FLAGS += +firmware=$(FIRMWARE)/firmware.hex -vcs-firmware-gui: vcs-run-gui - -.PHONY: vcs-unit-test -vcs-unit-test: firmware-unit-test-clean -vcs-unit-test: $(FIRMWARE)/firmware_unit_test.hex -vcs-unit-test: ALL_VCS_FLAGS += "+firmware=$(FIRMWARE)/firmware_unit_test.hex" -vcs-unit-test: vcs-run - -.PHONY: vcs-unit-test-gui -vcs-unit-test-gui: firmware-unit-test-clean -vcs-unit-test-gui: $(FIRMWARE)/firmware_unit_test.hex -vcs-unit-test-gui: ALL_VCS_FLAGS += "+firmware=$(FIRMWARE)/firmware_unit_test.hex" -vcs-unit-test-gui: vcs-run-gui - -vcs-clean: - rm -rf simv* *.daidir *.vpd *.db csrc ucli.key vc_hdrs.h - -############################################################################### -# Aldec Riviera-PRO - -.rvrlib-rtl: - $(ALIB) $(AWORK) - touch .rvrlib-rtl - -rvr-build-rtl: .rvrlib-rtl CV_CORE_pkg tbsrc_pkg tbsrc - $(ALOG) \ - -work $(AWORK) \ - $(ALOG_FLAGS) \ - $(ALOG_UVM) \ - -f $(CV_CORE_MANIFEST) \ - $(TBSRC_PKG) $(TBSRC) - -asim-all: .rvr-build-rtl - -# run tb and exit -.PHONY: asim-run -asim-run: ALL_ASIM_FLAGS += -c -asim-run: rvr-build-rtl - $(ASIM) -lib $(AWORK) $(ALL_ASIM_FLAGS)\ - $(RTLSRC_VLOG_TB_TOP) -do "run -all; endsim; quit -force" - -# run tb and drop into interactive shell -.PHONY: asim-run-sh -asim-run-sh: ALL_ASIM_FLAGS += -c -asim-run-sh: rvr-build-rtl - $(ASIM) -lib $(AWORK) $(ALL_ASIM_FLAGS) \ - $(RTLSRC_VLOG_TB_TOP) -do "run -all" - -# run tb with simulator gui -.PHONY: asim-run-gui -asim-run-gui: ALL_ASIM_FLAGS += $(ASIM_GUI_FLAGS) -asim-run-gui: rvr-build-rtl - $(ASIM) -lib $(AWORK) $(ALL_ASIM_FLAGS) \ - $(RTLSRC_VLOG_TB_TOP) -do "run -all" - -.PHONY: riviera-hello-world -riviera-hello-world: rvr-build-rtl $(CUSTOM)/hello-world/hello-world.hex -riviera-hello-world: ALL_ASIM_FLAGS += +firmware=$(CUSTOM)/hello-world/hello-world.hex -riviera-hello-world: asim-run - -.PHONY: riviera-hello-world-gui -riviera-hello-world-gui: rvr-build-rtl $(CUSTOM)/hello-world/hello-world.hex -riviera-hello-world-gui: ALL_ASIM_FLAGS += +firmware=$(CUSTOM)/hello-world/hello-world.hex -riviera-hello-world-gui: asim-run-gui - -.PHONY: riviera-custom -riviera-custom: rvr-build-rtl $(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -riviera-custom: ALL_ASIM_FLAGS += +firmware=$(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -riviera-custom: asim-run - -.PHONY: riviera-custom-gui -riviera-custom-gui: rvr-build-rtl $(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -riviera-custom-gui: ALL_ASIM_FLAGS += +firmware=$(CUSTOM)/$(CUSTOM_PROG)/$(CUSTOM_PROG).hex -riviera-custom-gui: asim-run-gui - -riviera-clean: - if [ -d $(AWORK) ]; then rm -r $(AWORK); fi - rm -f transcript trace_core*.log \ - .build-rtl .rvrlib-rtl *.vcd objdump *.asdb *.cfg dpi_header.h - -############################################################################### -# CV_CORE RTL dependencies - -clone_$(CV_CORE_LC)_rtl: - @echo "$(BANNER)" - @echo "* Cloning CV32E40X RTL model" - @echo "$(BANNER)" - $(CLONE_CV_CORE_CMD) - - - - -############################################################################### -# general targets -.PHONY: tc-clean - -# clean up toolchain generated files -clean-test-programs: - find $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs -name *.o -exec rm {} \; - find $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs -name *.hex -exec rm {} \; - find $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs -name *.elf -exec rm {} \; - find $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs -name *.map -exec rm {} \; - find $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs -name *.readelf -exec rm {} \; - find $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs -name *.objdump -exec rm {} \; - find $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs -name corev_*.S -exec rm {} \; - -.PHONY: clean clean_all distclean -clean: clean-test-programs questa-clean verilate-clean vcs-clean firmware-clean dsim-clean xrun-clean vcs-clean clean_bsp riviera-clean - -distclean: clean - rm -rf riscv-fesvr riscv-isa-sim $(CV_CORE_PKG) work - -clean_all: distclean -#endend diff --git a/cv32e40x/sim/core/README.md b/cv32e40x/sim/core/README.md deleted file mode 100644 index 6654862143..0000000000 --- a/cv32e40x/sim/core/README.md +++ /dev/null @@ -1,111 +0,0 @@ -Simulation Directory for CV32E Core Testbench -================================== -This is the directory in which you should run all tests of the Core Testbench. -The testbench itself is located at `../../tb/core` and the test-programs are at -`../../tests`. See the README in those directories for more information. - -To run the core testbench you will need a SystemVerilog simulator and RISC-V GCC compiler. - -Supported SystemVerilog Simulators ----------------------------------- -The core testbench and associated test-programs can be run using **_Verilator_**, the Metrics -**_dsim_**, Mentor's **_Questa_**, Cadence **_Xcelium_**, Synopsys **_vcs_** and Aldec **_Riviera-PRO_** -simulators. Note that **_Icarus_** verilog cannot compile the RTL and there are no plans -to support Icarus in the future. - -RISC-V GCC Compiler "Toolchain" -------------------------------- -Pointers to the recommended toolchain for CV32E40X are in `../TOOLCHAIN`. - -Running your own C programs ---------------------- -A hello world program is available and you can run it in the CV32E Core testbench. -Invoke the `dsim-hello_world` or `hello-world-veri-run` makefile rules to run it with -`dsim` or `verilator` respectively. - -The hello world program is located in the `custom` folder. The relevant sections -in the Makefile on how to compile and link this program can be found under `Running -custom programs`. Make sure you have a working C compiler (see above) and keep in -mind that you are running on a very basic machine. - -Running the testbench with [verilator](https://www.veripool.org/wiki/verilator) ----------------------- -Point your environment variable `RISCV` to your RISC-V toolchain. Call `make` -to run the default test (hello_world). - -Running your own Assembler programs -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Admittedly, this needs work. If you have a C or assembly program in `../../tests/core/custom` -then the following will work with Verilator:
-``` -make custom CUSTOM_PROG=dhrystone -make custom CUSTOM_PROG=misalign -make custom CUSTOM_PROG=fibonacci -make custom CUSTOM_PROG=illegal -make custom CUSTOM_PROG=riscv_ebreak_test_0 -``` - -Running the testbench with Metrics [dsim](https://metrics.ca) ----------------------- -Point your environment variable `RISCV` to your RISC-V toolchain. Call -`make dsim-hello_world` to build and run the testbench with the hello_world -test in the custom directory. Other rules of interest: -* `make dsim-cv32_riscv_tests` to build and run the testbench with all the testcases in the riscv_tests directory. -* `make dsim-cv32_riscv_compliance_tests` to build and run the tests in riscv_compliance_tests. -* `make dsim-firmware` to build and run the testbench with all the testcases in the riscv_tests and riscv_compliance_tests directories. -

The Makefile now supports running individual assembler tests from either -the riscv_tests or riscv_compliance_tests directories. For example, to run the ADD IMMEDIATE test from riscv_tests: -* `make dsim-unit-test addi` -
To run I-LBU-01.S from the riscv_compliance_tests: -* `make dsim-unit-test I_LBU_01` -
You can clean up the mess you made with `make dsim-clean`. - -Running the testbench with Cadence Xcelium [xrun](https://www.cadence.com/en_US/home/tools/system-design-and-verification/simulation-and-testbench-verification/xcelium-parallel-simulator.html) ----------------------- -**Note:** This testbench is known to require Xcelium 19.09 or later. See [Issue 11](https://github.com/openhwgroup/core-v-verif/issues/11) for more info. -Point your environment variable `RISCV` to your RISC-V toolchain. Call -`make xrun-hello_world` to build and run the testbench with the hello_world -test in the custom directory. Other rules of interest: -* `make xrun-firmware` to build and run the testbench with all the testcases in the riscv_tests/ and riscv_compliance_tests/ directories. -* Clean up your mess: `make xsim-clean` (deletes xsim intermediate files) and `xrun-clean-all` (deletes xsim intermedaites and all testcase object files). - -Running the testbench with Questa (vsim) ---------------------------------------------------------- -Point your environment variable `RISCV` to your RISC-V toolchain. Call `make -firmware-vsim-run` to build the testbench and the firmware, and run it. Use -`VSIM_FLAGS` to configure the simulator e.g. `make firmware-vsim-run -VSIM_FLAGS="-gui -debugdb"`. -
The Makefile also supports running individual assembler tests from either -the riscv_tests or riscv_compliance_tests directories using vsim. For example, -to run the ADD IMMEDIATE test from riscv_tests: -* `make questa-unit-test addi` -
To run I-LBU-01.S from the riscv_compliance_tests: -* `make questa-unit-test I_LBU_01` - -Running the testbench with VCS (vcs) ----------------------- -Point your environment variable `RISCV` to your RISC-V toolchain. -Call `make firmware-vcs-run` to build the testbench and the firmware, and run it. -Use `SIMV_FLAGS` or `VCS_FLAGS` to configure the simulator and build respectively e.g. -`make firmware-vcs-run VCS_FLAGS+="-cm line+cond+fsm+tgl+branch" SIMV_FLAGS+="-cm line+cond+fsm+tgl+branch"` - -Running the testbench with Riviera-PRO (riviera) ----------------------- -Point you environment variable `RISCV` to your RISC-V toolchain. Call `make -riviera-hello-world` to build the testbench and the firmware, and run it. Use -`ASIM_FLAGS` to configure the simulator e.g. `make custom-asim-run -ASIM_FLAGS="-gui"`. - -Options -------- -A few plusarg options are supported: -* `+verbose` to show all memory read and writes and other miscellaneous information. - -* `+vcd` to produce a vcd file called `riscy_tb.vcd`. Verilator always produces - a vcd file called `verilator_tb.vcd`. - -Examples --------- -Run all riscv_tests to completion with **dsim**: -`make dsim-cv32_riscv_tests` - diff --git a/cv32e40x/sim/tools/README.md b/cv32e40x/sim/tools/README.md deleted file mode 100644 index f156b27b7d..0000000000 --- a/cv32e40x/sim/tools/README.md +++ /dev/null @@ -1,4 +0,0 @@ -## TOOLS directory -Tool-specific sub-dirs for various tools used in the CV32E40X project. -Please do **not** place these in the sim, sim/core or sim/uvmt directories. -Note that these are here for the convenience of Contributors and are not necessarily up to date. diff --git a/cv32e40x/sim/tools/dsim/ccov_scopes.txt b/cv32e40x/sim/tools/dsim/ccov_scopes.txt deleted file mode 100644 index 137f8190a2..0000000000 --- a/cv32e40x/sim/tools/dsim/ccov_scopes.txt +++ /dev/null @@ -1,15 +0,0 @@ -# -# Code Coverage Scope Specification file for DSIM -# -# Example from DSIM User Manual: path top.testbench.dut + -# -# We want to instrument and collect code coverage for the CORE and all levels -# of hierarchy below the top of the core. Also, in the DSIM compile-time args, -# top is defined as uvmt_cv32_tb, so compile-time command looks something like: -# -# dsim -top uvmt_cv32_tb \ -# -code-cov block \ -# -code-cov-scope-specs ccov_scopes.txt \ -# -f $(MANIFEST) -# -path uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i + diff --git a/cv32e40x/sim/tools/imperas/README.md b/cv32e40x/sim/tools/imperas/README.md deleted file mode 100644 index ccf431de1d..0000000000 --- a/cv32e40x/sim/tools/imperas/README.md +++ /dev/null @@ -1 +0,0 @@ -Set your shell ENV variable IMPERAS_TOOLS to point to the .ic file in this directory. diff --git a/cv32e40x/sim/tools/mcy/alu_div/Makefile b/cv32e40x/sim/tools/mcy/alu_div/Makefile deleted file mode 100644 index dbf2c1dac8..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# Copyright 2020 OpenHW Group -# Copyright 2020 Symbiotic EDA -# -# Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# - -VERI_CFLAGS += -DMCY - -include $(PROJ_ROOT_DIR)/cv32/sim/core/Makefile - -DIV_ONLY_FIRMWARE = $(CORE_TEST_DIR)/div_only_firmware -DIV_ONLY_FIRMWARE_OBJS = $(addprefix $(DIV_ONLY_FIRMWARE)/, start.o print.o stats.o) -DIV_ONLY_TEST_OBJS =$(RISCV_TESTS)/rv32um/div.o $(RISCV_TESTS)/rv32um/divu.o $(RISCV_TESTS)/rv32um/rem.o $(RISCV_TESTS)/rv32um/remu.o - -$(DIV_ONLY_FIRMWARE)/div_only_firmware.elf: $(DIV_ONLY_FIRMWARE_OBJS) $(RISCV_TESTS_OBJS) $(DIV_ONLY_FIRMWARE)/link.ld - $(RISCV_EXE_PREFIX)gcc -g -Os -march=rv32imc -ffreestanding -nostdlib -o $@ \ - $(RISCV_TEST_INCLUDES) \ - -Wl,-Bstatic,-T,$(DIV_ONLY_FIRMWARE)/link.ld,-Map,$(DIV_ONLY_FIRMWARE)/div_only_firmware.map,--strip-debug \ - $(DIV_ONLY_FIRMWARE_OBJS) $(DIV_ONLY_TEST_OBJS) -lgcc - -$(DIV_ONLY_FIRMWARE)/start.o: $(DIV_ONLY_FIRMWARE)/start.S - $(RISCV_EXE_PREFIX)gcc -c -march=rv32imc -g -o $@ $< - -$(DIV_ONLY_FIRMWARE)/%.o: $(DIV_ONLY_FIRMWARE)/%.c - $(RISCV_EXE_PREFIX)gcc -c -march=rv32ic -g -Os --std=c99 -Wall \ - $(RISCV_TEST_INCLUDES) \ - -ffreestanding -nostdlib -o $@ $< - -.PHONY: div-only-veri-run -div-only-veri-run: verilate $(DIV_ONLY_FIRMWARE)/div_only_firmware.hex - mkdir -p $(VERI_LOG_DIR) - ./testbench_verilator $(VERI_FLAGS) \ - "+firmware=$(DIV_ONLY_FIRMWARE)/div_only_firmware.hex" \ - | tee $(VERI_LOG_DIR)/div-only-veri-run.log diff --git a/cv32e40x/sim/tools/mcy/alu_div/README.md b/cv32e40x/sim/tools/mcy/alu_div/README.md deleted file mode 100644 index c374a27eff..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/README.md +++ /dev/null @@ -1,33 +0,0 @@ -Directory for MCY coverage reporting -================================== - -This is an example setup for using Mutation Cover with Yosys (MCY). -The module targeted for mutation testing is `riscv_alu_div`. There are two tests -performed on the mutated module: `test_sim` runs the verilator testbench on the -whole core, with the mutated module substituted in the ALU. `test_eq` checks if -the mutation introduces a relevant behavioral modification using a bounded model -check on a miter circuit comparing the original and mutated module. - -This assumes that the SEDA suite and the pulp-riscv-gcc can be found in the path. -Set it e.g. as follows: - - export PATH=/opt/symbiotic/bin:/opt/riscv/bin:$PATH - -Current Status / Issues / Points of relevance: ----------------------------------- - -- The verilator testbench currently contains some failing tests as well as a -fatal error if the standard riscv-gcc is used (instead of the pulp-riscv-gcc). -This should be fixed, but right now `test_sim` just suppresses the return value -and checks for the magic number of errors. -- A timeout facility was added to `test_sim.sh` because mutations can cause -deadlock (e.g. illegal instruction loop). -- `test_sim` now runs a modified version of the verilator testbench that can -test multiple mutations with a single compiled binary using a command line -argument. -- `test_sim` will also run a reduced firmware first and only run the full -firmware if the first test passes. -- Verilator does not support arbitrary expressions in events yet -(https://github.com/verilator/verilator/issues/2184), so mutations that affect -the clock or reset signal lead to compilation errors. As a workaround, -`opt_rmdff` was added to the mutation script in `test_sim.sh`. diff --git a/cv32e40x/sim/tools/mcy/alu_div/config.mcy b/cv32e40x/sim/tools/mcy/alu_div/config.mcy deleted file mode 100644 index 0f50cba8ef..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/config.mcy +++ /dev/null @@ -1,46 +0,0 @@ -[options] -size 100 -tags COVERED UNCOVERED NOCHANGE PROBE FMGAP - -[script] -verific -work fpnew_pkg -sv ../../../core-v-cores/cv32e40x/rtl/fpnew/src/fpnew_pkg.sv -verific -sv ../../../core-v-cores/cv32e40x/rtl/cv32e40x_sim_clock_gate.sv -verific -work riscv_defines -L fpnew_pkg -sv ../../../core-v-cores/cv32e40x/rtl/include/apu_core_package.sv -verific -work riscv_defines -L fpnew_pkg -sv ../../../core-v-cores/cv32e40x/rtl/include/riscv_defines.sv -verific -work riscv_defines -L fpnew_pkg -sv ../../../core-v-cores/cv32e40x/rtl/include/riscv_tracer_defines.sv -verific -L riscv_defines -L fpnew_pkg -sv ../../../core-v-cores/cv32e40x/rtl/riscv_alu_div.sv -prep -top riscv_alu_div - - -[files] -../../../core-v-cores/cv32e40x/rtl/riscv_alu_div.sv - -[logic] -if result("test_sim") == "FAIL": - tag("COVERED") - if rng(100) < 20: - tag("PROBE") - if result("test_eq") == "PASS": - tag("FMGAP") - return - -if result("test_eq") == "FAIL": - tag("UNCOVERED") - return - -tag("NOCHANGE") - -[report] -if tags("FMGAP"): - print("Found %d mutations exposing a formal gap!" % tags("FMGAP")) -if tags("COVERED")+tags("UNCOVERED"): - print("Coverage: %.2f%%" % (100.0*tags("COVERED")/(tags("COVERED")+tags("UNCOVERED")))) - -[test test_sim] -maxbatchsize 10 -expect PASS FAIL -run bash $PRJDIR/test_sim.sh - -[test test_eq] -expect PASS FAIL -run bash $PRJDIR/test_eq.sh diff --git a/cv32e40x/sim/tools/mcy/alu_div/miter.sv b/cv32e40x/sim/tools/mcy/alu_div/miter.sv deleted file mode 100644 index 1c2f37f796..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/miter.sv +++ /dev/null @@ -1,127 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Symbiotic EDA -// -// Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// - -module miter -( - input logic clk, - input logic rst_n, - // input IF - input logic [31:0] ref_OpA_DI, - input logic [31:0] ref_OpB_DI, - input logic [5:0] ref_OpBShift_DI, - input logic ref_OpBIsZero_SI, - // - input logic ref_OpBSign_SI, // gate this to 0 in case of unsigned ops - input logic [1:0] ref_OpCode_SI, // 0: udiv, 2: urem, 1: div, 3: rem - - - input logic [31:0] uut_OpA_DI, - input logic [31:0] uut_OpB_DI, - input logic [5:0] uut_OpBShift_DI, - input logic uut_OpBIsZero_SI, - // - input logic uut_OpBSign_SI, // gate this to 0 in case of unsigned ops - input logic [1:0] uut_OpCode_SI, // 0: udiv, 2: urem, 1: div, 3: rem - - // handshake - input logic in_valid, - // output IF - input logic out_ready - ); - -logic ref_valid_out; -logic uut_valid_out; -logic [31:0] ref_result_div; -logic [31:0] uut_result_div; - - riscv_alu_div ref ( - .mutsel (1'b 0), - .Clk_CI (clk), - .Rst_RBI (rst_n), - - // input IF - .OpA_DI (ref_OpA_DI), - .OpB_DI (ref_OpB_DI), - .OpBShift_DI (ref_OpBShift_DI), - .OpBIsZero_SI (ref_OpBIsZero_SI), - - .OpBSign_SI (ref_OpBSign_SI), - .OpCode_SI (ref_OpCode_SI), - - .Res_DO (ref_result_div), - - // Hand-Shake - .InVld_SI (in_valid), - .OutRdy_SI (out_ready), - .OutVld_SO (ref_valid_out) - ); - - riscv_alu_div uut ( - .mutsel (1'b 1), - .Clk_CI (clk), - .Rst_RBI (rst_n), - - // input IF - .OpA_DI (uut_OpA_DI), - .OpB_DI (uut_OpB_DI), - .OpBShift_DI (uut_OpBShift_DI), - .OpBIsZero_SI (uut_OpBIsZero_SI), - - .OpBSign_SI (uut_OpBSign_SI), - .OpCode_SI (uut_OpCode_SI), - - .Res_DO (uut_result_div), - - // Hand-Shake - .InVld_SI (in_valid), - .OutRdy_SI (out_ready), - .OutVld_SO (uut_valid_out) - ); - -logic init_cycle = 1'b1; -always @ (posedge clk) begin - init_cycle = 1'b0; -end - -always @(*) begin - if (init_cycle) assume (!rst_n); - if (rst_n) begin - assume (out_ready); //too slow with backpressure - // if (in_valid) begin - // module depends on inputs not changing even if in_valid is false: - // have to comment this out or it fails equivalence with itself - assume (ref_OpA_DI == uut_OpA_DI); - assume (ref_OpB_DI == uut_OpB_DI); - assume (ref_OpBShift_DI == uut_OpBShift_DI); - assume (ref_OpBIsZero_SI == uut_OpBIsZero_SI); - assume (ref_OpBSign_SI == uut_OpBSign_SI); - assume (ref_OpBSign_SI == uut_OpBSign_SI); - assume (ref_OpCode_SI == uut_OpCode_SI); - // end - assert (ref_valid_out == uut_valid_out); - if (ref_valid_out) begin - assert (ref_result_div == uut_result_div); - end - end -end - - - - -endmodule diff --git a/cv32e40x/sim/tools/mcy/alu_div/riscv_alu_div_mutated_wrapper.sv b/cv32e40x/sim/tools/mcy/alu_div/riscv_alu_div_mutated_wrapper.sv deleted file mode 100644 index 22b9213f05..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/riscv_alu_div_mutated_wrapper.sv +++ /dev/null @@ -1,78 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Symbiotic EDA -// -// Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// - -module riscv_alu_div - #( - parameter C_WIDTH = 32, - parameter C_LOG_WIDTH = 6 - ) - ( - input logic Clk_CI, - input logic Rst_RBI, - // input IF - input logic [C_WIDTH-1:0] OpA_DI, - input logic [C_WIDTH-1:0] OpB_DI, - input logic [C_LOG_WIDTH-1:0] OpBShift_DI, - input logic OpBIsZero_SI, - // - input logic OpBSign_SI, // gate this to 0 in case of unsigned ops - input logic [1:0] OpCode_SI, // 0: udiv, 2: urem, 1: div, 3: rem - // handshake - input logic InVld_SI, - // output IF - input logic OutRdy_SI, - output logic OutVld_SO, - output logic [C_WIDTH-1:0] Res_DO - ); - -if (C_WIDTH != 32 || C_LOG_WIDTH != 6) $error("Changing parameters for mutated modules not supported."); - -reg [7:0] mutsel = 8'h00; - -export "DPI-C" task set_mutidx; -task set_mutidx(input [7:0] idx); - mutsel = idx; -endtask - -mutated div_i - ( - .Clk_CI ( Clk_CI ), - .Rst_RBI ( Rst_RBI ), - - // input IF - .OpA_DI ( OpA_DI ), - .OpB_DI ( OpB_DI ), - .OpBShift_DI ( OpBShift_DI ), - .OpBIsZero_SI ( OpBIsZero_SI ), - - .OpBSign_SI ( OpBSign_SI ), - .OpCode_SI ( OpCode_SI ), - - .Res_DO ( Res_DO ), - - // Hand-Shake - .InVld_SI ( InVld_SI ), - .OutRdy_SI ( OutRdy_SI ), - .OutVld_SO ( OutVld_SO ), - - // mutation selection - .mutsel ( mutsel ) - ); - -endmodule diff --git a/cv32e40x/sim/tools/mcy/alu_div/test_eq.sby b/cv32e40x/sim/tools/mcy/alu_div/test_eq.sby deleted file mode 100644 index 71dffe4a25..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/test_eq.sby +++ /dev/null @@ -1,20 +0,0 @@ -[options] -mode bmc -depth 34 -expect pass,fail - -[engines] -#btor btormc -smtbmc boolector - -[script] -read_verilog -sv miter.sv -read_ilang mutated.il -prep -top miter -fmcombine miter ref uut -flatten -opt -fast - -[files] -miter.sv -mutated.il diff --git a/cv32e40x/sim/tools/mcy/alu_div/test_eq.sh b/cv32e40x/sim/tools/mcy/alu_div/test_eq.sh deleted file mode 100644 index 020b490530..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/test_eq.sh +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/bash -# -# Copyright 2020 OpenHW Group -# Copyright 2020 Symbiotic EDA -# -# Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -exec 2>&1 -set -ex - -{ - echo "read_ilang ../../database/design.il" - while read -r idx mut; do - echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" - done < input.txt - echo "pmuxtree" # workaround for possible source of fmgap - echo "write_ilang mutated.il" -} > mutate.ys - -yosys -ql mutate.log mutate.ys -ln -s ../../miter.sv ../../test_eq.sby . - -sby -f test_eq.sby -gawk "{ print 1, \$1; }" test_eq/status >> output.txt - -exit 0 diff --git a/cv32e40x/sim/tools/mcy/alu_div/test_sim.sh b/cv32e40x/sim/tools/mcy/alu_div/test_sim.sh deleted file mode 100644 index a93a8982e1..0000000000 --- a/cv32e40x/sim/tools/mcy/alu_div/test_sim.sh +++ /dev/null @@ -1,77 +0,0 @@ -#!/bin/bash - -# -# Copyright 2020 OpenHW Group -# Copyright 2020 Symbiotic EDA -# -# Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# - -exec 2>&1 -set -ex - -# create yosys script for exporting mutation -{ - echo "read_ilang ../../database/design.il" - while read -r idx mut; do - # add multiple mutations to module, selectable with 'mutsel' input - echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" - done < input.txt - echo "opt_rmdff" # workaround for verilator not supporting posedge 1'b1 - echo "rename riscv_alu_div mutated" - echo "write_verilog -attr2comment mutated.sv" -} > mutate.ys - -# export mutated.sv -yosys -ql mutate.log mutate.ys - -# locations -PROJ_ROOT_DIR=$PWD/../../../../../.. -TEST_DIR=$PROJ_ROOT_DIR/cv32/tests/core - -# create modified manifest -grep -v "riscv_alu_div.sv" $PROJ_ROOT_DIR/core-v-cores/cv32e40x/cv32e40x_manifest.flist > mutated_manifest.flist -echo "../../riscv_alu_div_mutated_wrapper.sv" >> mutated_manifest.flist -echo "mutated.sv" >> mutated_manifest.flist - -# build verilator testbench with mutated module -MAKEFLAGS="CV32E40X_MANIFEST=mutated_manifest.flist PROJ_ROOT_DIR=$PROJ_ROOT_DIR" -MAKEFILE=../../Makefile -make -f $MAKEFILE $MAKEFLAGS testbench_verilator - -# for each mutation (listed in input.txt) -while read idx mut; do - # shorter firmware first - make -f $MAKEFILE $MAKEFLAGS $TEST_DIR/div_only_firmware/div_only_firmware.hex - cp $TEST_DIR/div_only_firmware/div_only_firmware.hex div_only_firmware.hex - if ! timeout 1m ./testbench_verilator +firmware=div_only_firmware.hex --mutidx ${idx} > sim_short_${idx}.out || ! grep "PASSED" sim_short_${idx}.out - then - echo "${idx} FAIL" >> output.txt - continue - fi - - # longer firmware if short doesn't catch anything - make -f $MAKEFILE $MAKEFLAGS $TEST_DIR/firmware/firmware.hex - cp $TEST_DIR/firmware/firmware.hex firmware.hex - timeout 1m ./testbench_verilator +firmware=firmware.hex --mutidx ${idx} > sim_long_${idx}.out || true - - if [[ `grep -c "ERROR" sim_long_${idx}.out` -ne 2 ]] - then - echo "${idx} FAIL" >> output.txt - continue - fi - - echo "$idx PASS" >> output.txt -done < input.txt diff --git a/cv32e40x/sim/tools/vsim/cov.tcl b/cv32e40x/sim/tools/vsim/cov.tcl deleted file mode 100644 index f36095bb03..0000000000 --- a/cv32e40x/sim/tools/vsim/cov.tcl +++ /dev/null @@ -1 +0,0 @@ -coverage save -onexit -testname ${TEST} ${TEST}.ucdb diff --git a/cv32e40x/sim/tools/vsim/gui.tcl b/cv32e40x/sim/tools/vsim/gui.tcl deleted file mode 100644 index 850f16ed6d..0000000000 --- a/cv32e40x/sim/tools/vsim/gui.tcl +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Copyright and related rights are licensed under the Solderpad Hardware -# License, Version 0.51 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -# or agreed to in writing, software, hardware and materials distributed under -# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -# CONDITIONS OF ANY KIND, either express or implied. See the License for the -# specific language governing permissions and limitations under the License. - -# Author: Robert Balas (balasr@student.ethz.ch) -# Description: TCL scripts to facilitate simulations - -set NoQuitOnFinish 1 diff --git a/cv32e40x/sim/tools/vsim/software.tcl b/cv32e40x/sim/tools/vsim/software.tcl deleted file mode 100644 index c33ea15afa..0000000000 --- a/cv32e40x/sim/tools/vsim/software.tcl +++ /dev/null @@ -1,27 +0,0 @@ -# add fc execution trace -set rvcores [find instances -recursive -bydu riscv_core -nodu] -set fpuprivate [find instances -recursive -bydu fpu_private] - -if {$rvcores ne ""} { - - add wave -group "Software Debugging" $rvcores/clk_i - add wave -group "Software Debugging" -divider "Instructions at ID stage, sampled half a cycle later" - add wave -group "Software Debugging" $rvcores/riscv_tracer_i/insn_disas - add wave -group "Software Debugging" $rvcores/riscv_tracer_i/insn_pc - add wave -group "Software Debugging" $rvcores/riscv_tracer_i/insn_val - add wave -group "Software Debugging" -divider "Program counter at ID and IF stage" - add wave -group "Software Debugging" $rvcores/pc_id - add wave -group "Software Debugging" $rvcores/pc_if - add wave -group "Software Debugging" -divider "Register File contents" - add wave -group "Software Debugging" $rvcores/id_stage_i/register_file_i/mem - if {$fpuprivate ne ""} { - add wave -group "Software Debugging" $rvcores/id_stage_i/register_file_i/mem_fp - } - -} - -configure wave -namecolwidth 250 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -timelineunits ns diff --git a/cv32e40x/sim/tools/vsim/vsim.tcl b/cv32e40x/sim/tools/vsim/vsim.tcl deleted file mode 100644 index 75e0506428..0000000000 --- a/cv32e40x/sim/tools/vsim/vsim.tcl +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Copyright and related rights are licensed under the Solderpad Hardware -# License, Version 0.51 (the "License"); you may not use this file except in -# compliance with the License. You may obtain a copy of the License at -# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -# or agreed to in writing, software, hardware and materials distributed under -# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -# CONDITIONS OF ANY KIND, either express or implied. See the License for the -# specific language governing permissions and limitations under the License. - -# Author: Robert Balas (balasr@student.ethz.ch) -# Description: TCL scripts to facilitate simulations - -run -all -exit diff --git a/cv32e40x/sim/tools/vsim/waves.tcl b/cv32e40x/sim/tools/vsim/waves.tcl deleted file mode 100644 index e04500a9fc..0000000000 --- a/cv32e40x/sim/tools/vsim/waves.tcl +++ /dev/null @@ -1 +0,0 @@ -log -r /uvmt_cv32_tb/* \ No newline at end of file diff --git a/cv32e40x/sim/tools/xrun/README.md b/cv32e40x/sim/tools/xrun/README.md deleted file mode 100644 index 709ba66684..0000000000 --- a/cv32e40x/sim/tools/xrun/README.md +++ /dev/null @@ -1,24 +0,0 @@ -## Xcelium tools directory - -Various Xcelium-based utilities and scripts. - -### Simulator control scripts - -These TCL scripts can be passed to Xcelium by the core-v-verif Makefiles when using Xcelium. The following scripts are currently supported: - -| Script | Usage | -|--------|-------| -| probe.tcl | Generates probes for waveform database viewable with Cadence SimVision. Invoked when WAVES=1 passed to the make test command | -| indago.tcl | Generates probes for waveform database viewable with Cadence Indago. Invokedf when WAVEs=1 ADV_DEBUG=1 passed to the make test command | - -### Coverage refinement files - -These XML files should be created using coverage tools such as IMC or Vmanager. These are used to generate coverage reports that focus on necessary coverage while removing exceptions that are unhittable or not significant for the design being verified. - -*Note that some files are automatically generated and some are manually maintained. This is indicated in the table.* - -| File | Maintenance | Description | -|------|-------------|-------------| -| cv32e40x.hierarchy.vRefine | Manual | Removes hierarchies from coverage database that are not to be considered for coverage (e.g. testbench | -| cv32e40x.auto.vRefine | Automatic | Auto-generated refinements based on parameter usage for the CV32E40X without PULP extensions. *Do not manually edit* | -| cv32e40x.manual.vRefine | Manual | Manually added coverage exception based on deesign verification reviews. | diff --git a/cv32e40x/sim/tools/xrun/UserDefinedPageViews/openhw.METRIC_SUMMARY.CV32E40X.xml b/cv32e40x/sim/tools/xrun/UserDefinedPageViews/openhw.METRIC_SUMMARY.CV32E40X.xml deleted file mode 100644 index 80bda20889..0000000000 --- a/cv32e40x/sim/tools/xrun/UserDefinedPageViews/openhw.METRIC_SUMMARY.CV32E40X.xml +++ /dev/null @@ -1,223 +0,0 @@ - - - - hierarchyTree - summaryTreeTableBox - - EXCLUSION_RULE_TYPE - UNR - NAME - BLOCK_HIT - EXPRESSION_HIT - FSM_HIT - COVER_GROUP_HIT - ASSERTION_HIT - - - - 1440074364924932096 - - - - - - - - infoTabBoxItemsTable - infoTabBoxItemsTable - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - ENCLOSING_ENTITY - - - - 1440074364922335236 - - - - - - - - - - - infoTabBoxSub_ElementsTable - infoTabBoxSub_ElementsTable - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - ASSERTION_STATUS_GRADE - - - - 1440074364922335234 - - - - - - - - - - - infoTabBoxToggleTable - infoTabBoxToggleTable - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - - - - 1440074364922335239 - - - - - - - - - - - infoTabBoxFSMsTable - infoTabBoxFSMsTable - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - ENCLOSING_ENTITY - - - - 1440074364922335237 - - - - - - - - - - - infoTabBoxBinsTable - infoTabBoxBinsTable - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - COUNT - - - - 1440074364922335240 - - - - - - - - - - - infoTabBoxCover_GroupsTable - infoTabBoxCover_GroupsTable - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - ENCLOSING_ENTITY - - - - 1440074364922335235 - - - - - - - - - - - metricsTree - metricItemsTree - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - - - - 1440074364924932097 - - - - - - - - infoTabBoxAssertionsTable - infoTabBoxAssertionsTable - - EXCLUSION_RULE_TYPE - UNR - NAME - OVERALL_AVERAGE_GRADE - OVERALL_HIT - ASSERTION_STATUS_GRADE - - - - 1440074364922335238 - - - - - - - - - - 4072613415997145095 - - <__attributeDescriptor class="com.cadence.mdv.model.common.CoverageAttributes">EXCLUSION_RULE_TYPE - <__direction>ASCENDING - - - - - - CV32E40X - METRIC_SUMMARY - openhw - - openhw.METRIC_SUMMARY.CV32E40X - - 0 - false - temp - true - diff --git a/cv32e40x/sim/tools/xrun/cov_report.tcl b/cv32e40x/sim/tools/xrun/cov_report.tcl deleted file mode 100644 index 1403958aa8..0000000000 --- a/cv32e40x/sim/tools/xrun/cov_report.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright 2021 OpenHW Group -# Copyright 2021 Silicon Labs, Inc. -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# - -# OpenHW Coverage Report script for use with Cadence Integrated Metrics Center (IMC) - -# Assumed environment variables set by Makefile/environment -# CORE_V_VERIF : Root directory of the core-v-verif checkout -# CV_CORE : Core-V core being tested (e.g. CV32E40X, CV32E40S, CV32E40P) - -load -refinement $::env(CORE_V_VERIF)/$::env(CV_CORE)/sim/tools/xrun/$::env(CV_CORE).hierarchy.vRefine -load -refinement $::env(CORE_V_VERIF)/$::env(CV_CORE)/sim/tools/xrun/$::env(CV_CORE).auto.vRefine - -report_metrics \ - -detail \ - -view CV32E40X(openhw) \ - -block_view Uncovered \ - -expression_view Uncovered \ - -inst \ - -overwrite \ - -out cov_report diff --git a/cv32e40x/sim/tools/xrun/covfile.tcl b/cv32e40x/sim/tools/xrun/covfile.tcl deleted file mode 100644 index 4f5c365656..0000000000 --- a/cv32e40x/sim/tools/xrun/covfile.tcl +++ /dev/null @@ -1,54 +0,0 @@ -# ---------------------------------------------------------------------------------- -# General coverage configuration options -# ---------------------------------------------------------------------------------- - -# Setting Constant Object Marking and enabling log for it -set_com -log - -# Disable scoring of implicit else and default case blocks -set_implicit_block_scoring -off - -# Remove empty instances from coverage hierarchy -deselect_coverage -remove_empty_instances - -# Enable resilience from code changes -set_refinement_resilience - -# Improve expression coverage performance -set_optimize -vlog_prune_on - -# Set glitch strobes -set_glitch_strobe 1ps - -# ---------------------------------------------------------------------------------- -# FSM coverage configruation -# ---------------------------------------------------------------------------------- - -# Enable scoring state hold arcs in FSM -set_fsm_scoring -hold_transition - -# ---------------------------------------------------------------------------------- -# Expression coverage configuration -# ---------------------------------------------------------------------------------- - -# Setting expression scoring for all operators (not only boolean (|| &&) and VHDL (AND OR NOR NAND) -set_expr_coverable_operators -all -set_expr_coverable_statements -all - -# ---------------------------------------------------------------------------------- -# Toggle coverage configuration -# ---------------------------------------------------------------------------------- - -# Toggle coverage smart refinement (refinement for toggle with traverse hierarchy) -set_toggle_smart_refinement - -# ---------------------------------------------------------------------------------- -# Covergroup coverage configuration -# ---------------------------------------------------------------------------------- -set_covergroup -new_instance_reporting - -# ---------------------------------------------------------------------------------- -# Instances/modules to remove from coverage -# For performance and to avoid spurious warnings, remove these modules from code coverage collection -# ---------------------------------------------------------------------------------- -deselect_coverage -all -instance uvmt_cv32e40x_tb.iss_wrap... \ No newline at end of file diff --git a/cv32e40x/sim/tools/xrun/cv32e40x.Manual.vRefine b/cv32e40x/sim/tools/xrun/cv32e40x.Manual.vRefine deleted file mode 100644 index 09ccb402c1..0000000000 --- a/cv32e40x/sim/tools/xrun/cv32e40x.Manual.vRefine +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/cv32e40x/sim/tools/xrun/cv32e40x.auto.vRefine b/cv32e40x/sim/tools/xrun/cv32e40x.auto.vRefine deleted file mode 100644 index bb04da947a..0000000000 --- a/cv32e40x/sim/tools/xrun/cv32e40x.auto.vRefine +++ /dev/null @@ -1,197 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/cv32e40x/sim/tools/xrun/cv32e40x.hierarchy.vRefine b/cv32e40x/sim/tools/xrun/cv32e40x.hierarchy.vRefine deleted file mode 100644 index 43765a129f..0000000000 --- a/cv32e40x/sim/tools/xrun/cv32e40x.hierarchy.vRefine +++ /dev/null @@ -1,30 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/cv32e40x/sim/tools/xrun/indago.tcl b/cv32e40x/sim/tools/xrun/indago.tcl deleted file mode 100644 index bae978d2e7..0000000000 --- a/cv32e40x/sim/tools/xrun/indago.tcl +++ /dev/null @@ -1,23 +0,0 @@ -# Indago waveform probe script -ida_database -open -wave -ida_probe -log -wave=on -wave_probe_args="uvmt_cv32e40x_tb -depth all -all -memories -packed 8192 -unpacked 8192" -sv_all_logs - -# If the tracer exists, dump the string of the disassembled instruction -if { [find -scope uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i -instance tracer_i] != ""} { - ida_probe -wave -wave_probe_args="uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.tracer_i.insn_disas -depth 1" - ida_probe -wave -wave_probe_args="uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.tracer_i.insn_regs_write -depth 1" -} - -# If the iss_wrap exists dump the string of the ISS disassembled instruction -if { [find -scope uvmt_cv32e40x_tb -instance iss_wrap] != ""} { - ida_probe -wave -wave_probe_args="uvmt_cv32e40x_tb.iss_wrap.cpu.state.decode -depth 1" - ida_probe -wave -wave_probe_args="uvmt_cv32e40x_tb.iss_wrap.cpu.state.csr -depth 1" -} - -# Only execute if we are not in interactive mode -# When in interactive (gui) mode the env variable INDAGO_ENABLE_INTERACTIVE_DEBUG will exist -if { ![info exists ::env(INDAGO_ENABLE_INTERACTIVE_DEBUG)] } { - run - exit -} - diff --git a/cv32e40x/sim/tools/xrun/indago_mem.tcl b/cv32e40x/sim/tools/xrun/indago_mem.tcl deleted file mode 100644 index 70399f4f76..0000000000 --- a/cv32e40x/sim/tools/xrun/indago_mem.tcl +++ /dev/null @@ -1,22 +0,0 @@ -# Indago waveform probe script -ida_database -open -wave -ida_probe -log -wave=on -wave_probe_args="uvmt_cv32e40x_tb -depth all -all -memories" -sv_all_logs - -# If the tracer exists, dump the string of the disassembled instruction -if { [find -scope uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i -instance tracer_i] != ""} { - ida_probe -wave -wave_probe_args="uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.tracer_i.insn_disas -depth 1" - ida_probe -wave -wave_probe_args="uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.tracer_i.insn_regs_write -depth 1" -} - -# If the iss_wrap exists dump the string of the ISS disassembled instruction -if { [find -scope uvmt_cv32e40x_tb -instance iss_wrap] != ""} { - ida_probe -wave -wave_probe_args="uvmt_cv32e40x_tb.iss_wrap.cpu.state.decode -depth 1" -} - -# Only execute if we are not in interactive mode -# When in interactive (gui) mode the env variable INDAGO_ENABLE_INTERACTIVE_DEBUG will exist -if { ![info exists ::env(INDAGO_ENABLE_INTERACTIVE_DEBUG)] } { - run - exit -} - diff --git a/cv32e40x/sim/tools/xrun/probe.tcl b/cv32e40x/sim/tools/xrun/probe.tcl deleted file mode 100644 index 62489f19cb..0000000000 --- a/cv32e40x/sim/tools/xrun/probe.tcl +++ /dev/null @@ -1,5 +0,0 @@ -database -open waves -default -incsize 2G -probe -create uvmt_cv32e40x_tb -depth all -database waves - -run -exit diff --git a/cv32e40x/sim/tools/xrun/probe_mem.tcl b/cv32e40x/sim/tools/xrun/probe_mem.tcl deleted file mode 100644 index a154fee0c6..0000000000 --- a/cv32e40x/sim/tools/xrun/probe_mem.tcl +++ /dev/null @@ -1,5 +0,0 @@ -database -open waves -default -incsize 2G -probe -create uvmt_cv32e40x_tb -depth all -all -memories -database waves - -run -exit diff --git a/cv32e40x/sim/tools/xrun/restore.tcl b/cv32e40x/sim/tools/xrun/restore.tcl deleted file mode 100644 index 12c60c1927..0000000000 --- a/cv32e40x/sim/tools/xrun/restore.tcl +++ /dev/null @@ -1,66 +0,0 @@ - -# XM-Sim Command File -# TOOL: xmsim(64) 19.09-s007 -# -# -# You can restore this configuration with: -# -# xrun -l xrun-hello-world.log -64bit -R -input ../xrun/restore.tcl +UVM_VERBOSITY=UVM_LOW +=+USE_ISS -sv_lib /wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../vendor_lib/imperas/riscv_CV32E40X_OVPsim/bin/Linux64/riscv_CV32E40X.dpi.so +elf_file=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.elf +nm_file=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.nm +UVM_TESTNAME=uvmt_cv32_firmware_test_c +firmware=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.hex -input /wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/xrun/restore.tcl -# - -set tcl_prompt1 {puts -nonewline "xcelium> "} -set tcl_prompt2 {puts -nonewline "> "} -set vlog_format %h -set vhdl_format %v -set real_precision 6 -set display_unit auto -set time_unit module -set heap_garbage_size -200 -set heap_garbage_time 0 -set assert_report_level note -set assert_stop_level error -set autoscope yes -set assert_1164_warnings yes -set pack_assert_off {} -set severity_pack_assert_off {note warning} -set assert_output_stop_level failed -set tcl_debug_level 0 -set relax_path_name 1 -set vhdl_vcdmap XX01ZX01X -set intovf_severity_level ERROR -set probe_screen_format 0 -set rangecnst_severity_level ERROR -set textio_severity_level ERROR -set vital_timing_checks_on 1 -set vlog_code_show_force 0 -set assert_count_attempts 1 -set tcl_all64 false -set tcl_runerror_exit false -set assert_report_incompletes 0 -set show_force 1 -set force_reset_by_reinvoke 0 -set tcl_relaxed_literal 0 -set probe_exclude_patterns {} -set probe_packed_limit 4k -set probe_unpacked_limit 16k -set assert_internal_msg no -set svseed 1 -set assert_reporting_mode 0 -alias . run -alias quit exit -stop -create -name Randomize -randomize -database -open -shm -into waves.shm waves -default -probe -create -database waves uvmt_cv32_tb.step_compare.ev_compare uvmt_cv32_tb.step_compare.ev_ovp uvmt_cv32_tb.step_compare.ev_rtl uvmt_cv32_tb.step_compare.miscompare uvmt_cv32_tb.step_compare.ret_ovp uvmt_cv32_tb.step_compare.ret_rtl uvmt_cv32_tb.step_compare.step_ovp uvmt_cv32_tb.step_compare.step_rtl uvmt_cv32_tb.step_compare.Clk uvmt_cv32_tb.step_compare_if.insn_pc uvmt_cv32_tb.step_compare_if.ovp_b1_Step uvmt_cv32_tb.step_compare_if.ovp_b1_Stepping uvmt_cv32_tb.step_compare_if.ovp_cpu_PCr uvmt_cv32_tb.step_compare_if.ovp_cpu_busWait uvmt_cv32_tb.step_compare_if.ovp_cpu_retire uvmt_cv32_tb.step_compare_if.riscv_retire uvmt_cv32_tb.clknrst_if.clk uvmt_cv32_tb.clknrst_if.clk_active uvmt_cv32_tb.clknrst_if.clk_period uvmt_cv32_tb.clknrst_if.reset_n uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.clk uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_pc uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.retire uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_disas uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_regs_write uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.clk uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem uvmt_cv32_tb.iss_wrap.cpu.Retire uvmt_cv32_tb.iss_wrap.b1.Clk uvmt_cv32_tb.iss_wrap.b1.Step uvmt_cv32_tb.iss_wrap.b1.Stepping uvmt_cv32_tb.iss_wrap.cpu.PCr uvmt_cv32_tb.iss_wrap.cpu.GPR uvmt_cv32_tb.step_compare_if.ovp_cpu_GPR uvmt_cv32_tb.step_compare_if.riscy_GPR -probe -create -database waves uvmt_cv32_tb.dut_wrap.riscv_core_i.clk_i uvmt_cv32_tb.dut_wrap.riscv_core_i.clk -probe -create -database waves uvmt_cv32_tb.dut_wrap.ram_i.clk_i uvmt_cv32_tb.dut_wrap.ram_i.data_addr_i uvmt_cv32_tb.dut_wrap.ram_i.data_be_i uvmt_cv32_tb.dut_wrap.ram_i.data_gnt_o uvmt_cv32_tb.dut_wrap.ram_i.data_rdata_o uvmt_cv32_tb.dut_wrap.ram_i.data_req_i uvmt_cv32_tb.dut_wrap.ram_i.data_rvalid_o uvmt_cv32_tb.dut_wrap.ram_i.data_wdata_i uvmt_cv32_tb.dut_wrap.ram_i.data_we_i uvmt_cv32_tb.dut_wrap.ram_i.exit_valid_o uvmt_cv32_tb.dut_wrap.ram_i.exit_value_o uvmt_cv32_tb.dut_wrap.ram_i.instr_addr_i uvmt_cv32_tb.dut_wrap.ram_i.instr_gnt_o uvmt_cv32_tb.dut_wrap.ram_i.instr_rdata_o uvmt_cv32_tb.dut_wrap.ram_i.instr_req_i uvmt_cv32_tb.dut_wrap.ram_i.instr_rvalid_o uvmt_cv32_tb.dut_wrap.ram_i.irq_ack_i uvmt_cv32_tb.dut_wrap.ram_i.irq_id_i uvmt_cv32_tb.dut_wrap.ram_i.irq_id_o uvmt_cv32_tb.dut_wrap.ram_i.irq_o uvmt_cv32_tb.dut_wrap.ram_i.pc_core_id_i uvmt_cv32_tb.dut_wrap.ram_i.rst_ni uvmt_cv32_tb.dut_wrap.ram_i.tests_failed_o uvmt_cv32_tb.dut_wrap.ram_i.tests_passed_o -probe -create -database waves uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.cycles -probe -create -database waves uvmt_cv32_tb.iss_wrap.cpu.CSR -probe -create -database waves uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mcause_q uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mepc_q uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mstatus_q uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mtvec_q -probe -create -database waves uvmt_cv32_tb.iss_wrap.b1.DData -probe -create -database waves uvmt_cv32_tb.dut_wrap.ram_i.core_data_rdata uvmt_cv32_tb.dut_wrap.ram_i.ram_data_rdata uvmt_cv32_tb.dut_wrap.ram_i.rnd_stall_data_rdata -probe -create -database waves uvmt_cv32_tb.dut_wrap.ram_i.data_random_stalls.data_process.mem_acc -probe -create -database waves uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.csr_illegal uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.illegal_insn_o uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.illegal_c_insn_i -probe -create -database waves uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.instr_rdata_i -probe -create -database waves uvmt_cv32_tb.iss_wrap.b1.DAddr uvmt_cv32_tb.iss_wrap.b1.DSize uvmt_cv32_tb.iss_wrap.b1.Dbe uvmt_cv32_tb.iss_wrap.b1.Drd uvmt_cv32_tb.iss_wrap.b1.Dwr uvmt_cv32_tb.iss_wrap.b1.IAddr uvmt_cv32_tb.iss_wrap.b1.IData uvmt_cv32_tb.iss_wrap.b1.ISize uvmt_cv32_tb.iss_wrap.b1.Ibe uvmt_cv32_tb.iss_wrap.b1.Ird - -simvision -input ../xrun/restore.tcl.svcf diff --git a/cv32e40x/sim/tools/xrun/restore.tcl.svcf b/cv32e40x/sim/tools/xrun/restore.tcl.svcf deleted file mode 100644 index fe89456e4d..0000000000 --- a/cv32e40x/sim/tools/xrun/restore.tcl.svcf +++ /dev/null @@ -1,851 +0,0 @@ -# SimVision Command Script (Fri May 15 14:26:58 MDT 2020) -# -# Version 19.09.s007 -# -# You can restore this configuration with: -# -# xrun -l xrun-hello-world.log -64bit -R -input ../xrun/restore.tcl +UVM_VERBOSITY=UVM_LOW +=+USE_ISS -sv_lib /wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../vendor_lib/imperas/riscv_CV32E40X_OVPsim/bin/Linux64/riscv_CV32E40X.dpi.so +elf_file=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.elf +nm_file=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.nm +UVM_TESTNAME=uvmt_cv32_firmware_test_c +firmware=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.hex -input /wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/xrun/restore.tcl -# - - -# -# Preferences -# -preferences set waveform-dont-show-assert-debug-info 1 -preferences set toolbar-Standard-WatchWindow { - usual - shown 0 -} -preferences set waveform-print-variables selected -preferences set script-input-warning 0 -preferences set txe-locate-add-fibers 1 -preferences set signal-type-colors {assertion #FF0000 output #FFA500 group #0099FF inout #00FFFF input #FFFF00 fiber #00EEEE errorsignal #FF0000 unknown #FFFFFF overlay #0099FF internal #00FF00 reference #FFFFFF} -preferences set seq-time-width 20 -preferences set txe-view-hold 0 -preferences set txe-navigate-search-locate 0 -preferences set plugin-enable-svdatabrowser-new 1 -preferences set cursorctl-dont-show-sync-warning 1 -preferences set toolbar-Windows-WatchWindow { - usual - shown 0 -} -preferences set verilog-colors {Su #ff0099 0 {} 1 {} HiZ #ff9900 We #00ffff Pu #9900ff Sm #00ff99 X #ff0000 StrX #ff0000 other #ffff00 Z #ff9900 Me #0000ff La #ff00ff St {}} -preferences set waveform-signal-add-radix hex -preferences set toolbar-sendToIndago-WaveWindow { - usual - position -pos 1 -} -preferences set txe-navigate-waveform-locate 1 -preferences set txe-view-hidden 0 -preferences set waveform-height 16 -preferences set toolbar-Standard-Console { - usual - position -pos 1 -} -preferences set txe-search-show-linenumbers 1 -preferences set toolbar-Search-Console { - usual - position -pos 2 -} -preferences set toolbar-txe_waveform_toggle-WaveWindow { - usual - position -pos 3 -} -preferences set memviewer-addressradix hex -preferences set plugin-enable-groupscope 0 -preferences set standard-methodology-filtering 1 -preferences set key-bindings {PageUp PageUp Edit>Undo Ctrl+z View>Zoom>Next {Alt+Right arrow} View>Zoom>In Alt+i PageDown PageDown ScrollDown {Down arrow} Edit>Copy Ctrl+c View>Zoom>FullY_widget y Edit>Create>Group Ctrl+g Simulation>NextInScope F7 Edit>Select>All Ctrl+a Format>Radix>Decimal Ctrl+Shift+D Edit>Ungroup Ctrl+Shift+G TopOfPage Home Edit>Create>Condition Ctrl+e {command -console SimVision {%w sidebar access designbrowser selectall}} Alt+a View>Zoom>FullX_widget = ScrollLeft {Left arrow} Edit>SelectAllText Alt+a Edit>TextSearchConsole Alt+s Windows>SendTo>Waveform Ctrl+w Simulation>Return Shift+F5 View>CallstackDown {Ctrl+Down arrow} Select>All Ctrl+a Edit>Delete Del Format>Radix>Octal Ctrl+Shift+O Edit>Cut Ctrl+x Simulation>Run F2 Edit>Create>Marker Ctrl+m View>Center Alt+c View>CallstackInWindow Ctrl+k Edit>SelectAll Ctrl+a File>OpenDatabase Ctrl+o Edit>Redo Ctrl+y Format>Radix>Binary Ctrl+Shift+B View>ExpandSequenceTime>AtCursor Alt+x ScrollUp {Up arrow} File>CloseWindow Ctrl+Shift+w ScrollRight {Right arrow} View>Zoom>FullX Alt+= Edit>Create>Bus Ctrl+b Explore>NextEdge Ctrl+\] View>Zoom>Cursor-Baseline Alt+z View>Zoom>OutX Alt+o Edit>GoToLine Ctrl+g View>Zoom>Fit Alt+= View>Zoom>OutX_widget o View>CallstackUp {Ctrl+Up arrow} View>Bookmarks>Add Ctrl+b Format>Radix>Hexadecimal Ctrl+Shift+H Edit>Search Ctrl+f Simulation>Next F6 View>ShowValues Ctrl+s View>Zoom>InX Alt+i Edit>Create>MarkerAtCursor Ctrl+Shift+M View>Zoom>Out Alt+o Edit>TextSearch Ctrl+f Format>Signed Ctrl+Shift+S Edit>Paste Ctrl+v View>Zoom>Previous {Alt+Left arrow} View>CollapseSequenceTime>AtCursor Alt+s Format>Radix>ASCII Ctrl+Shift+A View>Zoom>InX_widget i Explore>PreviousEdge {Ctrl+[} Simulation>Step F5 BottomOfPage End} -preferences set sb-display-values 1 -preferences set plugin-enable-interleaveandcompare 0 -preferences set plugin-enable-waveformfrequencyplot 0 -preferences set toolbar-SimControl-WatchWindow { - usual - shown 0 -} -preferences set toolbar-Windows-WaveWindow { - usual - position -pos 4 -} -preferences set txe-navigate-waveform-next-child 1 -preferences set memviewer-radix hex -preferences set print-designer {make GUI='-gui -input restore.tcl' TARGET=INCISIVE APP=hello} -preferences set vhdl-colors {X #ff0000 0 {} L #00ffff H #00ffff U #9900ff 1 {} - {} Z #ff9900 W #ff0000} -preferences set txe-locate-scroll-x 1 -preferences set txe-locate-scroll-y 1 -preferences set waveform-assertion-debug 1 -preferences set txe-locate-pop-waveform 1 -preferences set whats-new-dont-show-at-startup 1 -preferences set toolbar-TimeSearch-WatchWindow { - usual - shown 0 -} -preferences set prompt-exit 0 -preferences set key-bindings {Edit>Undo Ctrl+z PageUp PageUp View>Zoom>In Alt+i View>Zoom>Next {Alt+Right arrow} PageDown PageDown Edit>Copy Ctrl+c ScrollDown {Down arrow} Edit>Select>All Ctrl+a Simulation>NextInScope F7 Edit>Create>Group Ctrl+g View>Zoom>FullY_widget y Format>Radix>Decimal Ctrl+Shift+D Edit>Ungroup Ctrl+Shift+G TopOfPage Home Edit>Create>Condition Ctrl+e {command -console SimVision {%w sidebar access designbrowser selectall}} Alt+a View>Zoom>FullX_widget = ScrollLeft {Left arrow} Edit>SelectAllText Alt+a Edit>TextSearchConsole Alt+s Windows>SendTo>Waveform Ctrl+w Simulation>Return Shift+F5 View>CallstackDown {Ctrl+Down arrow} Select>All Ctrl+a Edit>Delete Del Format>Radix>Octal Ctrl+Shift+O Edit>Cut Ctrl+x Simulation>Run F2 Edit>Create>Marker Ctrl+m View>Center Alt+c View>CallstackInWindow Ctrl+k Edit>SelectAll Ctrl+a File>OpenDatabase Ctrl+o Edit>Redo Ctrl+y Format>Radix>Binary Ctrl+Shift+B View>ExpandSequenceTime>AtCursor Alt+x ScrollUp {Up arrow} File>CloseWindow Ctrl+Shift+w ScrollRight {Right arrow} View>Zoom>FullX Alt+= Edit>Create>Bus Ctrl+b Explore>NextEdge Ctrl+\] View>Zoom>Cursor-Baseline Alt+z View>Zoom>OutX Alt+o Edit>GoToLine Ctrl+g View>Zoom>Fit Alt+= View>Zoom>OutX_widget o View>CallstackUp {Ctrl+Up arrow} View>Bookmarks>Add Ctrl+b View>ShowValues Ctrl+s Simulation>Next F6 Edit>Search Ctrl+f Format>Radix>Hexadecimal Ctrl+Shift+H Edit>Create>MarkerAtCursor Ctrl+Shift+M View>Zoom>InX Alt+i View>Zoom>Out Alt+o Edit>TextSearch Ctrl+f View>Zoom>Previous {Alt+Left arrow} Edit>Paste Ctrl+v Format>Signed Ctrl+Shift+S View>CollapseSequenceTime>AtCursor Alt+s View>Zoom>InX_widget i Format>Radix>ASCII Ctrl+Shift+A BottomOfPage End Simulation>Step F5 Explore>PreviousEdge {Ctrl+[}} -preferences set toolbar-sendToIndago-WaveWindow { - usual - position -pos 4 -} - -# -# Simulator -# -database require simulator -hints { - simulator "xrun -l xrun-hello-world.log -64bit -R -gui -input ../xrun/restore.tcl +UVM_VERBOSITY=UVM_LOW +=+USE_ISS -sv_lib /wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../vendor_lib/imperas/riscv_CV32E40X_OVPsim/bin/Linux64/riscv_CV32E40X.dpi.so +elf_file=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.elf +nm_file=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.nm +UVM_TESTNAME=uvmt_cv32_firmware_test_c +firmware=/wrk/gtumbush/mcu/OpenHW/iss_integration_fork/cv32/sim/uvmt_cv32/../../../cv32/tests/core/custom/illegal.hex -input restore.tcl" -} - -# -# Conditions -# -set expression simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.clk -if {[catch {condition new -name tracer_clk -expr $expression}] != ""} { - condition set -using tracer_clk -expr $expression -} -# -# Groups -# -catch {group new -name ISS -overlay 0} -catch {group new -name RTL -overlay 0} -catch {group new -name step_compare_if -overlay 0} -catch {group new -name clknrst_if -overlay 0} -catch {group new -name {RISCV RAM} -overlay 0} -catch {group new -name instr_bus -overlay 0} -catch {group new -name registers -overlay 0} -catch {group new -name {ISS RAM} -overlay 0} -catch {group new -name {data bus} -overlay 0} -catch {group new -name {inst _bus} -overlay 0} -group using ISS -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - simulator::uvmt_cv32_tb.iss_wrap.cpu.Retire \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Clk \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Step \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Stepping \ - simulator::uvmt_cv32_tb.iss_wrap.cpu.PCr \ - {simulator::uvmt_cv32_tb.iss_wrap.cpu.GPR[0:31]} \ - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mcause"]} \ - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mepc"]} \ - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["misa"]} \ - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mstatus"]} \ - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mtvec"]} -group using RTL -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - tracer_clk \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_pc[31:0]} \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.retire \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_disas \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_regs_write \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.clk \ - registers \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.csr_illegal \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.instr_rdata_i[31:0]} \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.illegal_insn_o \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.illegal_c_insn_i -group using step_compare_if -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {simulator::uvmt_cv32_tb.step_compare_if.insn_pc[31:0]} \ - simulator::uvmt_cv32_tb.step_compare_if.ovp_b1_Step \ - simulator::uvmt_cv32_tb.step_compare_if.ovp_b1_Stepping \ - {simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_GPR[0:31]} \ - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_PCr \ - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_busWait \ - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_retire \ - simulator::uvmt_cv32_tb.step_compare_if.reg_t \ - simulator::uvmt_cv32_tb.step_compare_if.riscv_retire \ - {simulator::uvmt_cv32_tb.step_compare_if.riscy_GPR[31:0]} -group using clknrst_if -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - simulator::uvmt_cv32_tb.clknrst_if.clk \ - simulator::uvmt_cv32_tb.clknrst_if.clk_active \ - simulator::uvmt_cv32_tb.clknrst_if.reset_n \ - simulator::uvmt_cv32_tb.clknrst_if.clk_period -group using {RISCV RAM} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.clk_i \ - instr_bus \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.exit_valid_o \ - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.exit_value_o[31:0]} \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_ack_i \ - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_id_i[4:0]} \ - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_id_o[4:0]} \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_o \ - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.pc_core_id_i[31:0]} \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.rst_ni \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.tests_failed_o \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.tests_passed_o -group using instr_bus -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_addr_i[19:0]} \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_req_i \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_gnt_o \ - simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_rvalid_o -group using registers -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[18]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[17]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[16]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[15]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[14]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[13]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[3]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[2]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[31:0]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mcause_q[6:0]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mepc_q[31:0]} \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.MISA_VALUE[31:0]} \ - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mstatus_q \ - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mtvec_q[23:0]} -group using {ISS RAM} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - {data bus} \ - {inst _bus} -group using {data bus} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - simulator::uvmt_cv32_tb.iss_wrap.b1.DAddr \ - simulator::uvmt_cv32_tb.iss_wrap.b1.DSize \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Dbe \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Drd \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Dwr \ - simulator::uvmt_cv32_tb.iss_wrap.b1.DData -group using {inst _bus} -group set -overlay 0 -group set -comment {} -group clear 0 end - -group insert \ - simulator::uvmt_cv32_tb.iss_wrap.b1.IAddr \ - simulator::uvmt_cv32_tb.iss_wrap.b1.IData \ - simulator::uvmt_cv32_tb.iss_wrap.b1.ISize \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Ibe \ - simulator::uvmt_cv32_tb.iss_wrap.b1.Ird - -# -# Mnemonic Maps -# -mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low} -{%c=TRUE -edgepriority 1 -shape high}} -mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus} -{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT} -{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT} -{%x=* -label %x -linecolor gray -shape bus}} - -# -# Time Ranges -# -timerange new -name startup -start 0 -end 277722.442ps -timerange new -name {GPR miscompare} -start 111779.448ps -end 152715.121ps -timerange new -name {illegal instr} -start 24337.912632ns -end 24474.11169ns - -# -# Design Browser windows -# -if {[catch {window new WatchList -name "Design Browser 1" -geometry 856x639+893+216}] != ""} { - window geometry "Design Browser 1" 856x639+893+216 -} -window target "Design Browser 1" on -browser using {Design Browser 1} -browser set -scope simulator::uvmt_cv32_tb.iss_wrap.ram -browser set \ - -signalsort name -browser yview see simulator::uvmt_cv32_tb.iss_wrap.ram -browser timecontrol set -lock 0 - -# -# Waveform windows -# -if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1181x782+116+21}] != ""} { - window geometry "Waveform 1" 1181x782+116+21 -} -window target "Waveform 1" on -waveform using {Waveform 1} -waveform sidebar visibility partial -waveform set \ - -primarycursor TimeA \ - -signalnames name \ - -signalwidth 258 \ - -units ns \ - -valuewidth 1 -waveform baseline set -time 2,884,000,000fs - -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.ev_compare - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.ev_ovp - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.ev_rtl - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.miscompare - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.iss_wrap.cpu.PCr - } ] -waveform format $id -radix %x -set id [waveform add -signals { - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_pc[31:0]} - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_disas - } ] -waveform format $id -radix %a -set id [waveform add -signals { - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[10]} - } ] -waveform format $id -radix %x -set id [waveform add -signals { - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[3]} - } ] -waveform format $id -radix %x - -set groupId0 [waveform add -groups RTL] - -set groupId1 [waveform find -name registers] -set gpGlist1 [waveform hierarchy contents $groupId1] -set gpID1 [lindex $gpGlist1 0] -foreach {name attrs} { - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[18]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[17]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[16]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[15]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[14]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[13]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[3]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[2]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.mem[31:0]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mcause_q[6:0]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mepc_q[31:0]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.MISA_VALUE[31:0]} {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mstatus_q {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.cs_registers_i.mtvec_q[23:0]} {-radix %x} -} childcmds { - {} - {} - {} - {} - {} - {} - {} - {} - { - set id $gpID1 - waveform hierarchy expand $id - set id2 [lindex [waveform hierarchy content $id] 0] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 1] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 2] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 3] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 4] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 5] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 6] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 7] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 8] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 9] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 10] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 11] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 12] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 13] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 14] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 15] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 16] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 17] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 18] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 19] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 20] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 21] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 22] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 23] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 24] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 25] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 26] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 27] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 28] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 29] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 30] - waveform format $id2 -radix %x - set id2 [lindex [waveform hierarchy content $id] 31] - waveform format $id2 -radix %x - waveform hierarchy collapse $id - } - {} - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID1] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID1 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist1 [lrange $gpGlist1 1 end] - set gpID1 [lindex $gpGlist1 0] -} -waveform hierarchy collapse $groupId1 - -set gpGlist0 [waveform hierarchy contents $groupId0] -set gpID0 [lindex $gpGlist0 0] -foreach {name attrs} { - tracer_clk {} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_pc[31:0]} {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.retire {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_disas {-radix %a} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.insn_regs_write {-trace analogSampleAndHold} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.register_file_i.clk {} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.csr_illegal {} - {simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.instr_rdata_i[31:0]} {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.illegal_insn_o {} - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.id_stage_i.decoder_i.illegal_c_insn_i {} -} childcmds { - {} - {} - {} - {} - { - set id $gpID0 - waveform hierarchy expand $id - set id2 [lindex [waveform hierarchy content $id] 0] - waveform format $id2 -radix %x - waveform hierarchy collapse $id - } - {} - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID0] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID0 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist0 [lrange $gpGlist0 1 end] - set gpID0 [lindex $gpGlist0 0] -} -waveform hierarchy collapse $groupId0 - - -set groupId0 [waveform add -groups ISS] -set gpGlist0 [waveform hierarchy contents $groupId0] -set gpID0 [lindex $gpGlist0 0] -foreach {name attrs} { - simulator::uvmt_cv32_tb.iss_wrap.cpu.Retire {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.Clk {} - simulator::uvmt_cv32_tb.iss_wrap.b1.Step {} - simulator::uvmt_cv32_tb.iss_wrap.b1.Stepping {} - simulator::uvmt_cv32_tb.iss_wrap.cpu.PCr {-radix %x} - {simulator::uvmt_cv32_tb.iss_wrap.cpu.GPR[0:31]} {-radix %x} - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mcause"]} {-radix %x} - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mepc"]} {-radix %x} - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["misa"]} {-radix %x} - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mstatus"]} {-radix %x} - {simulator::uvmt_cv32_tb.iss_wrap.cpu.CSR["mtvec"]} {-radix %x} -} childcmds { - {} - {} - {} - {} - {} - {} - {} - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID0] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID0 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist0 [lrange $gpGlist0 1 end] - set gpID0 [lindex $gpGlist0 0] -} -waveform hierarchy collapse $groupId0 - - -set groupId0 [waveform add -groups {{ISS RAM}}] - -set groupId1 [waveform find -name {data bus}] -set gpGlist1 [waveform hierarchy contents $groupId1] -set gpID1 [lindex $gpGlist1 0] -foreach {name attrs} { - simulator::uvmt_cv32_tb.iss_wrap.b1.DAddr {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.DSize {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.Dbe {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.Drd {} - simulator::uvmt_cv32_tb.iss_wrap.b1.Dwr {} - simulator::uvmt_cv32_tb.iss_wrap.b1.DData {-radix %x} -} childcmds { - {} - {} - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID1] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID1 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist1 [lrange $gpGlist1 1 end] - set gpID1 [lindex $gpGlist1 0] -} -waveform hierarchy collapse $groupId1 - - -set groupId1 [waveform find -name {inst _bus}] -set gpGlist1 [waveform hierarchy contents $groupId1] -set gpID1 [lindex $gpGlist1 0] -foreach {name attrs} { - simulator::uvmt_cv32_tb.iss_wrap.b1.IAddr {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.IData {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.ISize {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.Ibe {-radix %x} - simulator::uvmt_cv32_tb.iss_wrap.b1.Ird {} -} childcmds { - {} - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID1] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID1 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist1 [lrange $gpGlist1 1 end] - set gpID1 [lindex $gpGlist1 0] -} -waveform hierarchy collapse $groupId1 - -waveform hierarchy collapse $groupId0 - - -set groupId0 [waveform add -groups {{RISCV RAM}}] - -set groupId1 [waveform find -name instr_bus] -set gpGlist1 [waveform hierarchy contents $groupId1] -set gpID1 [lindex $gpGlist1 0] -foreach {name attrs} { - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_addr_i[19:0]} {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_req_i {} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_gnt_o {} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.instr_rvalid_o {} -} childcmds { - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID1] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID1 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist1 [lrange $gpGlist1 1 end] - set gpID1 [lindex $gpGlist1 0] -} -waveform hierarchy collapse $groupId1 - -set gpGlist0 [waveform hierarchy contents $groupId0] -set gpID0 [lindex $gpGlist0 0] -foreach {name attrs} { - simulator::uvmt_cv32_tb.dut_wrap.ram_i.clk_i {} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.exit_valid_o {} - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.exit_value_o[31:0]} {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_ack_i {} - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_id_i[4:0]} {-radix %x} - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_id_o[4:0]} {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.irq_o {} - {simulator::uvmt_cv32_tb.dut_wrap.ram_i.pc_core_id_i[31:0]} {-radix %x} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.rst_ni {} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.tests_failed_o {} - simulator::uvmt_cv32_tb.dut_wrap.ram_i.tests_passed_o {} -} childcmds { - {} - {} - {} - {} - {} - {} - {} - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID0] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID0 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist0 [lrange $gpGlist0 1 end] - set gpID0 [lindex $gpGlist0 0] -} -waveform hierarchy collapse $groupId0 - - -set groupId0 [waveform add -groups clknrst_if] -set gpGlist0 [waveform hierarchy contents $groupId0] -set gpID0 [lindex $gpGlist0 0] -foreach {name attrs} { - simulator::uvmt_cv32_tb.clknrst_if.clk {} - simulator::uvmt_cv32_tb.clknrst_if.clk_active {} - simulator::uvmt_cv32_tb.clknrst_if.reset_n {} - simulator::uvmt_cv32_tb.clknrst_if.clk_period {-trace analogSampleAndHold} -} childcmds { - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID0] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID0 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist0 [lrange $gpGlist0 1 end] - set gpID0 [lindex $gpGlist0 0] -} -waveform hierarchy collapse $groupId0 - -set id [waveform add -signals { - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.riscv_tracer_i.cycles - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.ret_ovp - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.ret_rtl - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.step_ovp - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.step_rtl - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare.Clk - } ] -set id [waveform add -signals { - {simulator::uvmt_cv32_tb.step_compare_if.insn_pc[31:0]} - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare_if.ovp_b1_Step - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare_if.ovp_b1_Stepping - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_PCr - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_busWait - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_retire - } ] -waveform format $id -radix %x -set id [waveform add -signals { - simulator::uvmt_cv32_tb.step_compare_if.riscv_retire - } ] -waveform format $id -radix %x - -set groupId0 [waveform add -groups clknrst_if] -set gpGlist0 [waveform hierarchy contents $groupId0] -set gpID0 [lindex $gpGlist0 0] -foreach {name attrs} { - simulator::uvmt_cv32_tb.clknrst_if.clk {} - simulator::uvmt_cv32_tb.clknrst_if.clk_active {} - simulator::uvmt_cv32_tb.clknrst_if.reset_n {} - simulator::uvmt_cv32_tb.clknrst_if.clk_period {-trace analogSampleAndHold} -} childcmds { - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID0] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID0 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist0 [lrange $gpGlist0 1 end] - set gpID0 [lindex $gpGlist0 0] -} -waveform hierarchy collapse $groupId0 - - -set groupId0 [waveform add -groups step_compare_if] -set gpGlist0 [waveform hierarchy contents $groupId0] -set gpID0 [lindex $gpGlist0 0] -foreach {name attrs} { - {simulator::uvmt_cv32_tb.step_compare_if.insn_pc[31:0]} {-radix %x} - simulator::uvmt_cv32_tb.step_compare_if.ovp_b1_Step {} - simulator::uvmt_cv32_tb.step_compare_if.ovp_b1_Stepping {} - {simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_GPR[0:31]} {-radix %x} - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_PCr {-radix %x} - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_busWait {-radix %x} - simulator::uvmt_cv32_tb.step_compare_if.ovp_cpu_retire {-radix %x} - simulator::uvmt_cv32_tb.step_compare_if.reg_t {-radix %x} - simulator::uvmt_cv32_tb.step_compare_if.riscv_retire {-radix %x} - {simulator::uvmt_cv32_tb.step_compare_if.riscy_GPR[31:0]} {-radix %x} -} childcmds { - {} - {} - {} - {} - {} - {} - {} - {} - {} - {} -} { - set expected [ join [waveform signals -format fullpath $gpID0] ] - if {[string equal $name $expected] || $name == "cdivider"} { - if {$attrs != ""} { - eval waveform format $gpID0 $attrs - } - if { $childcmds != ""} { - eval $childcmds - } - } - set gpGlist0 [lrange $gpGlist0 1 end] - set gpID0 [lindex $gpGlist0 0] -} -waveform hierarchy collapse $groupId0 - -set id [waveform add -signals { - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.clk_i - } ] -set id [waveform add -signals { - simulator::uvmt_cv32_tb.dut_wrap.riscv_core_i.clk - } ] - -waveform xview limits 1308.568422ns 1367.430905ns - -# -# Waveform Window Links -# - -# -# Console windows -# -console set -windowname Console -window geometry Console 1059x365+-5+678 - -# -# Layout selection -# diff --git a/cv32e40x/sim/tools/xrun/strichmo_indago.wsf b/cv32e40x/sim/tools/xrun/strichmo_indago.wsf deleted file mode 100644 index 076efdcf90..0000000000 --- a/cv32e40x/sim/tools/xrun/strichmo_indago.wsf +++ /dev/null @@ -1,107 +0,0 @@ -# Indago Command Script (Wed, 12 May 2021 09:29:06 -0500) -# -# Version 21.02.001-a - -# -# Signal List -# -waveform group add {OBI I} -waveform add -in_group {OBI I} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.instr_req_o} -waveform add -in_group {OBI I} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.instr_gnt_i} -waveform add -in_group {OBI I} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.instr_rvalid_i} -waveform add -in_group {OBI I} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.instr_addr_o} -waveform add -in_group {OBI I} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.instr_rdata_i} -waveform add -in_group {OBI I} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.instr_err_i} -waveform group add {OBI D} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_req_o} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_gnt_i} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_rvalid_i} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_we_o} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_be_o} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_addr_o} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_wdata_o} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_rdata_i} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_err_i} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_atop_o} -waveform add -in_group {OBI D} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.data_exokay_i} -waveform group add {Imperas ISS D RAM} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.Clk} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.DAddr} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.DData} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.DM} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.DSize} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.Dbe} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.Drd} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.b1.Dwr} -waveform add -in_group {Imperas ISS D RAM} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.pc} -waveform group add {IRQ} -waveform add -in_group {IRQ} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.irq_i} -waveform add -in_group {IRQ} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.irq_ack_o} -waveform add -in_group {IRQ} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.irq_id_o} -waveform group add {RVFI 0} -waveform add -in_group {RVFI 0} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_i.clk_i} -waveform group add -in_group {RVFI 0} {INSTR} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_valid} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_halt} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_insn} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_intr} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_ixl} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_mode} -waveform add -in_group {RVFI 0>INSTR} -radix d {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_order} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_trap} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_pc_wdata} -waveform add -in_group {RVFI 0>INSTR} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_pc_rdata} -waveform group add -in_group {RVFI 0} {REG} -waveform add -in_group {RVFI 0>REG} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_rs1_addr} -waveform add -in_group {RVFI 0>REG} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_rs1_rdata} -waveform add -in_group {RVFI 0>REG} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_rs2_addr} -waveform add -in_group {RVFI 0>REG} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_rs2_rdata} -waveform add -in_group {RVFI 0>REG} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_rd1_addr} -waveform add -in_group {RVFI 0>REG} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_rd1_wdata} -waveform group add -in_group {RVFI 0} {MEM} -waveform add -in_group {RVFI 0>MEM} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_mem_addr} -waveform add -in_group {RVFI 0>MEM} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_mem_rdata} -waveform add -in_group {RVFI 0>MEM} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_mem_rmask} -waveform add -in_group {RVFI 0>MEM} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_mem_wdata} -waveform add -in_group {RVFI 0>MEM} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_mem_wmask} -waveform group add {RVVI Control} -waveform add -in_group {RVVI Control} {uvmt_cv32e40x_tb.iss_wrap.cpu.control.cmd} -waveform add -in_group {RVVI Control} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.control.ssmode} -waveform add -in_group {RVVI Control} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.control.state_cont} -waveform add -in_group {RVVI Control} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.control.state_idle} -waveform add -in_group {RVVI Control} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.control.state_stepi} -waveform add -in_group {RVVI Control} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.control.state_stop} -waveform group add {RVVI State} -waveform add -in_group {RVVI State} -radix a {uvmt_cv32e40x_tb.iss_wrap.cpu.state.decode} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.notify} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.halt} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.insn} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.isize} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.ixl} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.mode} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.pc} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.pcnext} -waveform add -in_group {RVVI State} -radix h {uvmt_cv32e40x_tb.iss_wrap.cpu.state.x} -waveform group add {Core} -waveform group add -in_group {Core} {IRQ} -waveform add -in_group {Core>IRQ} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.irq_i} -waveform add -in_group {Core>IRQ} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.irq_id_o} -waveform add -in_group {Core>IRQ} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.irq_ack_o} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.register_file_wrapper_i.register_file_i.mem} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.cs_registers_i.pc_ex_i} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.cs_registers_i.mstatus_q} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.cs_registers_i.mcause_q} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.cs_registers_i.mscratch_q} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.cs_registers_i.mip} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.cs_registers_i.mie_q} -waveform add -in_group {Core} -radix h {uvmt_cv32e40x_tb.dut_wrap.cv32e40x_wrapper_i.core_i.cs_registers_i.mepc_q} - -# -# Visible Time Range -# -waveform xview limits -win Waveform 345,256.343982ns 345,426.3ns -# -# Insertion Point -# -waveform insertion -win Waveform {6,1} -waveform scroll -win Waveform -vertical 0.0 diff --git a/cv32e40x/sim/uvmt/Makefile b/cv32e40x/sim/uvmt/Makefile deleted file mode 100644 index 2197298cdd..0000000000 --- a/cv32e40x/sim/uvmt/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -############################################################################### -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -############################################################################### -# -# Makefile for the CV32E40X "uvmt_cv32" testbench. Substantially modified -# from the original Makefile for the RI5CY testbench. -# -############################################################################### -# -# Copyright 2019 Claire Wolf -# Copyright 2019 Robert Balas -# -# Permission to use, copy, modify, and/or distribute this software for any -# purpose with or without fee is hereby granted, provided that the above -# copyright notice and this permission notice appear in all copies. -# -# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH -# REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY -# AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, -# INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM -# LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -# PERFORMANCE OF THIS SOFTWARE. -# -# Original Author: Robert Balas (balasr@iis.ee.ethz.ch) -# -############################################################################### - -# "Constants" -MAKE = make -MAKE_PATH := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST)))) -export CORE_V_VERIF = $(abspath $(MAKE_PATH)/../../..) -export CV_CORE ?= cv32e40x - -include ../ExternalRepos.mk -include $(CORE_V_VERIF)/mk/uvmt/uvmt.mk diff --git a/cv32e40x/sim/uvmt/README.md b/cv32e40x/sim/uvmt/README.md deleted file mode 100644 index 7918811f5e..0000000000 --- a/cv32e40x/sim/uvmt/README.md +++ /dev/null @@ -1,7 +0,0 @@ -Simulation Makefile Directory for CV32E40X UVM Verification Environment -================================== -This is the directory in which you should run all tests of the UVM environment.
-All results (compile logs, waveforms, run logs, simulation databases, etc.) will be placed in this directory under $(SIMULATOR)\_results
-For directory independent execution, please see the makeuvmt utility in the [$CORE_V_VERIF/bin](../../../bin) directory
- -For information on invoking and controlling the UVM verification environment, see the [README in the $CORE_V_VERIF/mk directory](../../../mk)
diff --git a/cv32e40x/tb/README.md b/cv32e40x/tb/README.md deleted file mode 100644 index ad493b17aa..0000000000 --- a/cv32e40x/tb/README.md +++ /dev/null @@ -1,28 +0,0 @@ -## CV32/TB: testbenches for the CV32E40X CORE-V family of RISC-V cores. -Derived from the -[tb](https://github.com/pulp-platform/riscv/tree/master/tb) -directory of the PULP-Platform RI5CY project. There are two distinct -testbenches: - -### core -Modified to remove a few RTL files (placed these in the rtl directory). This -testbench supports Verilator and we will do what we can to maintain Verilator -support here. Note that `tb_riscv` is now a sub-directory of `core`. - -### uvmt -The testbench and testharness for the CV32E40X UVM verification -environments. This tb/th maintains support for all features of the `core` -testbench. This testbench must be run with a SystemVerilog 1800-compliant simulator, -i.e. it cannot be run with Verilator. - -## Retired Testbenches -A set of directories inherited from the RI5CY project have fallen into disuse -and were deleted. Since nothing is ever gone in GitHub, if you _must_ have -this content, it is available in any hash of this repo older than -11ffa1577abfff2f7dce8afed6047b0c86ad335c. The deleted directories are: - -* dm -* scripts -* serDiv -* tb_MPU -* verilator-model diff --git a/cv32e40x/tb/core/.clang-format b/cv32e40x/tb/core/.clang-format deleted file mode 100644 index ab4772e00f..0000000000 --- a/cv32e40x/tb/core/.clang-format +++ /dev/null @@ -1,35 +0,0 @@ ---- -BasedOnStyle: LLVM -IndentWidth: 4 -UseTab: Never -BreakBeforeBraces: Linux -AlwaysBreakBeforeMultilineStrings: true -AllowShortIfStatementsOnASingleLine: false -AllowShortLoopsOnASingleLine: false -AllowShortFunctionsOnASingleLine: false -IndentCaseLabels: false -AlignEscapedNewlinesLeft: false -AlignTrailingComments: true -AlignOperands: true -AllowAllParametersOfDeclarationOnNextLine: false -AlignAfterOpenBracket: true -SpaceAfterCStyleCast: false -MaxEmptyLinesToKeep: 2 -BreakBeforeBinaryOperators: NonAssignment -BreakStringLiterals: false -SortIncludes: false -ContinuationIndentWidth: 4 -ColumnLimit: 80 -IndentPPDirectives: AfterHash -BinPackArguments: true -BinPackParameters: true -ForEachMacros: - - 'TAILQ_FOREACH' - - 'TAILQ_FOREACH_REVERSE' -BreakBeforeBinaryOperators: None -MaxEmptyLinesToKeep: 1 -AlwaysBreakAfterDefinitionReturnType: None -AlwaysBreakAfterReturnType: None -AlwaysBreakBeforeMultilineStrings: false -AlignConsecutiveAssignments: true -... diff --git a/cv32e40x/tb/core/.gitignore b/cv32e40x/tb/core/.gitignore deleted file mode 100644 index e9e88a5859..0000000000 --- a/cv32e40x/tb/core/.gitignore +++ /dev/null @@ -1,16 +0,0 @@ -csmith/platform.info -csmith/test.c -csmith/test.elf -csmith/test_ref -csmith/output_ref.txt -csmith/output_sim.txt -platform.info -memory_dump.bin -riscv-fesvr -riscv-isa-sim -modelsim.ini -DVEfiles -csrc -inter.vpd -ucli.key -vc_hdrs.h diff --git a/cv32e40x/tb/core/cv32e40x_tb_wrapper.sv b/cv32e40x/tb/core/cv32e40x_tb_wrapper.sv deleted file mode 100644 index d882efe723..0000000000 --- a/cv32e40x/tb/core/cv32e40x_tb_wrapper.sv +++ /dev/null @@ -1,202 +0,0 @@ -// Copyright 2018 Robert Balas -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -// Wrapper for a CV32E40X testbench, containing CV32E40X, Memory and stdout peripheral -// Contributor: Robert Balas -// Module renamed from riscv_wrapper to cv32e40x_tb_wrapper because (1) the -// name of the core changed, and (2) the design has a cv32e40x_wrapper module. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-0.51 - -module cv32e40x_tb_wrapper - #(parameter // Parameters used by TB - INSTR_RDATA_WIDTH = 32, - RAM_ADDR_WIDTH = 20, - BOOT_ADDR = 'h80, - DM_HALTADDRESS = 32'h1A11_0800, - HART_ID = 32'h0000_0000, - IMP_ID = 32'h0000_0000, - // Parameters used by DUT - NUM_MHPMCOUNTERS = 1 - ) - (input logic clk_i, - input logic rst_ni, - - input logic fetch_enable_i, - output logic tests_passed_o, - output logic tests_failed_o, - output logic [31:0] exit_value_o, - output logic exit_valid_o); - - // signals connecting core to memory - logic instr_req; - logic instr_gnt; - logic instr_rvalid; - logic [31:0] instr_addr; - logic [INSTR_RDATA_WIDTH-1:0] instr_rdata; - - logic data_req; - logic data_gnt; - logic data_rvalid; - logic [31:0] data_addr; - logic data_we; - logic [3:0] data_be; - logic [31:0] data_rdata; - logic [31:0] data_wdata; - - // signals to debug unit - logic debug_req; - - // irq signals (not used) - logic [0:31] irq; - logic [0:4] irq_id_in; - logic irq_ack; - logic [0:4] irq_id_out; - logic irq_sec; - - - // interrupts (only timer for now) - assign irq_sec = '0; - - // eXtension Interface - if_xif #( - .X_NUM_RS ( 2 ), - .X_MEM_WIDTH ( 32 ), - .X_RFR_WIDTH ( 32 ), - .X_RFW_WIDTH ( 32 ), - .X_MISA ( '0 ) - ) ext_if(); - - - // instantiate the core - cv32e40x_core #( - .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS) - ) - cv32e40x_core_i - ( - // Clock and Reset - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .scan_cg_en_i ( '0 ), - - // Control interface: more or less static - .boot_addr_i ( BOOT_ADDR ), - .mtvec_addr_i ( '0 ), // TODO - .dm_halt_addr_i ( DM_HALTADDRESS ), - .mhartid_i ( HART_ID ), - .mimpid_i ( IMP_ID ), - .dm_exception_addr_i ( '0 ), // TODO - .nmi_addr_i ( '0 ), // TODO - - // Instruction memory interface - .instr_req_o ( instr_req ), - .instr_gnt_i ( instr_gnt ), - .instr_rvalid_i ( instr_rvalid ), - .instr_addr_o ( instr_addr ), - .instr_memtype_o ( ), // TODO: should the core tb check this? - .instr_prot_o ( ), // TODO: should the core tb check this? - .instr_dbg_o ( ), // TODO: should the core tb check this? - .instr_rdata_i ( instr_rdata ), - .instr_err_i ( 1'b0 ), - - // Data memory interface - .data_req_o ( data_req ), - .data_gnt_i ( data_gnt ), - .data_rvalid_i ( data_rvalid ), - .data_we_o ( data_we ), - .data_be_o ( data_be ), - .data_addr_o ( data_addr ), - .data_memtype_o ( ), // TODO: should the core tb check this? - .data_prot_o ( ), // TODO: should the core tb check this? - .data_dbg_o ( ), // TODO - .data_err_i ( 1'b0 ), - .data_atop_o ( ), - .data_exokay_i ( 1'b1 ), - - // Cycle Count - .mcycle_o ( ), // TODO - - // eXtension interface - .xif_compressed_if ( ext_if ), - .xif_issue_if ( ext_if ), - .xif_commit_if ( ext_if ), - .xif_mem_if ( ext_if ), - .xif_mem_result_if ( ext_if ), - .xif_result_if ( ext_if ), - - // Interrupts - .irq_i ( {32{1'b0}} ), - - .clic_irq_i ( 1'b0 ), // TODO - .clic_irq_id_i ( 12'h0 ), // TODO - .clic_irq_il_i ( 8'h0 ), // TODO - .clic_irq_priv_i ( 2'h0 ), // TODO - .clic_irq_hv_i ( 1'b0 ), // TODO - .clic_irq_id_o ( ), // TODO - .clic_irq_mode_o ( ), - .clic_irq_exit_o ( ), - - - - // Fencei flush handshake - .fencei_flush_req_o ( ), - .fencei_flush_ack_i ( 1'b0 ), - - .debug_req_i ( debug_req ), - .debug_havereset_o ( ), - .debug_running_o ( ), - .debug_halted_o ( ), - - // CPU Control Signals - .fetch_enable_i ( fetch_enable_i ), - .core_sleep_o ( core_sleep_o ) - ); - - // this handles read to RAM and memory mapped pseudo peripherals - mm_ram - #(.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH), - .INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH)) - ram_i - (.clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .dm_halt_addr_i ( DM_HALTADDRESS ), - - .instr_req_i ( instr_req ), - .instr_addr_i ( { {10{1'b0}}, - instr_addr[RAM_ADDR_WIDTH-1:0] - } ), - .instr_rdata_o ( instr_rdata ), - .instr_rvalid_o ( instr_rvalid ), - .instr_gnt_o ( instr_gnt ), - - .data_req_i ( data_req ), - .data_addr_i ( data_addr ), - .data_we_i ( data_we ), - .data_be_i ( data_be ), - .data_wdata_i ( data_wdata ), - .data_rdata_o ( data_rdata ), - .data_rvalid_o ( data_rvalid ), - .data_gnt_o ( data_gnt ), - - .irq_id_i ( irq_id_out ), - .irq_ack_i ( irq_ack ), - .irq_o ( irq ), - - .debug_req_o ( debug_req ), - - .pc_core_id_i ( cv32e40x_core_i.if_id_pipe.pc ), - - .tests_passed_o ( tests_passed_o ), - .tests_failed_o ( tests_failed_o ), - .exit_valid_o ( exit_valid_o ), - .exit_value_o ( exit_value_o )); - -endmodule // cv32e40x_tb_wrapper diff --git a/cv32e40x/tb/core/dp_ram.sv b/cv32e40x/tb/core/dp_ram.sv deleted file mode 100644 index 08e8610447..0000000000 --- a/cv32e40x/tb/core/dp_ram.sv +++ /dev/null @@ -1,82 +0,0 @@ -// Copyright 2015 ETH Zurich and University of Bologna. -// Copyright 2017 Embecosm Limited -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module dp_ram - #(parameter ADDR_WIDTH = 8, - parameter INSTR_RDATA_WIDTH = 128) - (input logic clk_i, - - input logic en_a_i, - input logic [ADDR_WIDTH-1:0] addr_a_i, - input logic [31:0] wdata_a_i, - output logic [INSTR_RDATA_WIDTH-1:0] rdata_a_o, - input logic we_a_i, - input logic [3:0] be_a_i, - - input logic en_b_i, - input logic [ADDR_WIDTH-1:0] addr_b_i, - input logic [31:0] wdata_b_i, - output logic [31:0] rdata_b_o, - input logic we_b_i, - input logic [3:0] be_b_i); - - localparam bytes = 2**ADDR_WIDTH; - - logic [7:0] mem[bytes]; - logic [ADDR_WIDTH-1:0] addr_a_int; - logic [ADDR_WIDTH-1:0] addr_b_int; - - always_comb addr_a_int = {addr_a_i[ADDR_WIDTH-1:2], 2'b0}; - always_comb addr_b_int = {addr_b_i[ADDR_WIDTH-1:2], 2'b0}; - - always @(posedge clk_i) begin - for (int i = 0; i < INSTR_RDATA_WIDTH/8; i++) begin - rdata_a_o[(i*8)+: 8] <= mem[addr_a_int + i]; - end - - /* addr_b_i is the actual memory address referenced */ - if (en_b_i) begin - /* handle writes */ - if (we_b_i) begin - if (be_b_i[0]) mem[addr_b_int ] <= wdata_b_i[ 0+:8]; - if (be_b_i[1]) mem[addr_b_int + 1] <= wdata_b_i[ 8+:8]; - if (be_b_i[2]) mem[addr_b_int + 2] <= wdata_b_i[16+:8]; - if (be_b_i[3]) mem[addr_b_int + 3] <= wdata_b_i[24+:8]; - end - /* handle reads */ - else begin - if ($test$plusargs("verbose")) - $display("read addr=0x%08x: data=0x%08x", addr_b_int, - {mem[addr_b_int + 3], mem[addr_b_int + 2], - mem[addr_b_int + 1], mem[addr_b_int + 0]}); - - rdata_b_o[ 7: 0] <= mem[addr_b_int ]; - rdata_b_o[15: 8] <= mem[addr_b_int + 1]; - rdata_b_o[23:16] <= mem[addr_b_int + 2]; - rdata_b_o[31:24] <= mem[addr_b_int + 3]; - end - end - end - - export "DPI-C" function read_byte; - export "DPI-C" task write_byte; - - function int read_byte(input logic [ADDR_WIDTH-1:0] byte_addr); - read_byte = mem[byte_addr]; - endfunction - - task write_byte(input logic [ADDR_WIDTH-1:0] byte_addr, logic [7:0] val, output logic [7:0] other); - mem[byte_addr] = val; - other = mem[byte_addr]; - - endtask - -endmodule // dp_ram diff --git a/cv32e40x/tb/core/mm_ram.sv b/cv32e40x/tb/core/mm_ram.sv deleted file mode 100644 index d2457d47d1..0000000000 --- a/cv32e40x/tb/core/mm_ram.sv +++ /dev/null @@ -1,867 +0,0 @@ -// Copyright 2017 Embecosm Limited -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -// RAM and MM wrapper for RI5CY -// Contributor: Jeremy Bennett -// Robert Balas -// -// This maps the dp_ram module to the instruction and data ports of the RI5CY -// processor core and some pseudo peripherals - -module mm_ram -`ifndef VERILATOR - import uvm_pkg::*; - `include "uvm_macros.svh" -`endif - #( - parameter RAM_ADDR_WIDTH = 16, - INSTR_RDATA_WIDTH = 128, // width of read_data on instruction bus - DATA_RDATA_WIDTH = 32, // width of read_data on data bus - DBG_ADDR_WIDTH = 14, // POT ammount of memory allocated for debugger - // physically located at end of memory - IRQ_WIDTH = 32 // IRQ vector width - ) - ( - input logic clk_i, - input logic rst_ni, - input logic [31:0] dm_halt_addr_i, - - input logic instr_req_i, - input logic [31:0] instr_addr_i, - output logic [INSTR_RDATA_WIDTH-1:0] instr_rdata_o, - output logic instr_rvalid_o, - output logic instr_gnt_o, - - input logic data_req_i, - input logic [31:0] data_addr_i, - input logic data_we_i, - input logic [3:0] data_be_i, - input logic [31:0] data_wdata_i, - output logic [31:0] data_rdata_o, - output logic data_rvalid_o, - output logic data_gnt_o, - - input logic [4:0] irq_id_i, - input logic irq_ack_i, - output logic [IRQ_WIDTH-1:0] irq_o, - - input logic [31:0] pc_core_id_i, - - output logic debug_req_o, - - output logic tests_passed_o, - output logic tests_failed_o, - output logic exit_valid_o, - output logic [31:0] exit_value_o); - - localparam int RND_STALL_REGS = 16; - localparam int RND_STALL_INSTR_EN = 0; - localparam int RND_STALL_INSTR_MODE = 2; - localparam int RND_STALL_INSTR_MAX = 4; - localparam int RND_STALL_INSTR_GNT = 6; - localparam int RND_STALL_INSTR_VALID = 8; - localparam int RND_STALL_DATA_EN = 1; - localparam int RND_STALL_DATA_MODE = 3; - localparam int RND_STALL_DATA_MAX = 5; - localparam int RND_STALL_DATA_GNT = 7; - localparam int RND_STALL_DATA_VALID = 9; - - localparam int RND_IRQ_ID = 31; - - localparam int MMADDR_PRINT = 32'h1000_0000; - localparam int MMADDR_TESTSTATUS = 32'h2000_0000; - localparam int MMADDR_EXIT = 32'h2000_0004; - localparam int MMADDR_SIGBEGIN = 32'h2000_0008; - localparam int MMADDR_SIGEND = 32'h2000_000C; - localparam int MMADDR_SIGDUMP = 32'h2000_0010; - localparam int MMADDR_TIMERREG = 32'h1500_0000; - localparam int MMADDR_TIMERVAL = 32'h1500_0004; - localparam int MMADDR_DBG = 32'h1500_0008; - localparam int MMADDR_RNDSTALL = 16'h1600; - localparam int MMADDR_RNDNUM = 32'h1500_1000; - localparam int MMADDR_TICKS = 32'h1500_1004; - localparam int MMADDR_TICKS_PRINT = 32'h1500_1008; - - // UVM info tags - localparam string MM_RAM_TAG = "MM_RAM"; - localparam string RNDSTALL_TAG = "RNDSTALL"; - - // mux for read and writes - enum logic [2:0]{RAM, MM, RND_STALL, ERR, RND_NUM, TICKS} select_rdata_d, select_rdata_q; - - enum logic {T_RAM, T_PER} transaction; - - - integer i; - - logic [31:0] data_addr_aligned; - - // signals for handshake - logic data_rvalid_q; - logic instr_rvalid_q; - logic [INSTR_RDATA_WIDTH-1:0] core_instr_rdata; - logic [31:0] core_data_rdata; - - // signals to ram - logic ram_data_req; - logic [RAM_ADDR_WIDTH-1:0] ram_data_addr; - logic [31:0] ram_data_wdata; - logic [31:0] ram_data_rdata; - logic ram_data_we; - logic [3:0] ram_data_be; - logic ram_data_gnt; - logic ram_data_valid; - - logic data_req_dec; - logic [31:0] data_wdata_dec; - logic [RAM_ADDR_WIDTH-1:0] data_addr_dec; - logic data_we_dec; - logic [3:0] data_be_dec; - - logic [INSTR_RDATA_WIDTH-1:0] ram_instr_rdata; - logic ram_instr_req; - logic [RAM_ADDR_WIDTH-1:0] ram_instr_addr; - logic ram_instr_gnt; - logic ram_instr_valid; - logic [RAM_ADDR_WIDTH-1:0] instr_addr_remap; - - // signals to print peripheral - logic [31:0] print_wdata; - logic print_valid; - - // signature data - logic [31:0] sig_end_d, sig_end_q; - logic [31:0] sig_begin_d, sig_begin_q; - - // signals to timer - logic [IRQ_WIDTH-1:0] timer_irq_mask_q; - logic [31:0] timer_cnt_q; - logic [IRQ_WIDTH-1:0] irq_q; - logic timer_reg_valid; - logic timer_val_valid; - logic [31:0] timer_wdata; - - // cycle counting - logic [31:0] cycle_count_q; - logic cycle_count_overflow_q; - logic cycle_count_clear; - logic cycle_count_print; - - // debugger control signals - logic [31:0] debugger_wdata; - logic debugger_valid; - - // signals to rnd_stall - logic [31:0] rnd_stall_regs [0:RND_STALL_REGS-1]; - - logic rnd_stall_req; - logic [31:0] rnd_stall_addr; - logic [31:0] rnd_stall_wdata; - logic rnd_stall_we; - logic [31:0] rnd_stall_rdata; - - //signal delayed by random stall - logic rnd_stall_instr_req; - logic rnd_stall_instr_gnt; - - logic rnd_stall_data_req; - logic rnd_stall_data_gnt; - - // random number generation - logic rnd_num_req; - logic [31:0] rnd_num; - - //random or monitor interrupt request - logic rnd_irq; - - // used by dump_signature methods - string sig_file; - string sig_string; - bit use_sig_file; - integer sig_fd; - integer errno; - string error_str; - - // uhh, align? - always_comb data_addr_aligned = {data_addr_i[31:2], 2'b0}; - - always @(negedge rst_ni) begin : configure_stalls - for (i = 0; i < RND_STALL_REGS; i=i+1) begin - rnd_stall_regs[i] = 0; - end -`ifndef VERILATOR - if (!$test$plusargs("rand_stall_obi_disable")) begin - if ($test$plusargs("max_data_zero_instr_stall")) begin - `uvm_info(RNDSTALL_TAG, "Max data stall, zero instruction stall configuration", UVM_LOW) - // This "knob" creates maximum stalls on data loads/stores, and - // no stalls on instruction fetches. Used for fence.i testing. - rnd_stall_regs[RND_STALL_DATA_EN] = 1; - rnd_stall_regs[RND_STALL_DATA_MODE] = 2; - rnd_stall_regs[RND_STALL_DATA_GNT] = 2; - rnd_stall_regs[RND_STALL_DATA_VALID] = 2; - rnd_stall_regs[RND_STALL_DATA_MAX] = 8; - end - else if ($test$plusargs("rvalid_singles_stall")) begin - `uvm_info(RNDSTALL_TAG, "Single-cycle data and instr stall configuration", UVM_LOW) - // This "knob" creates single-cycle stalls on data and instr loads/stores. - // Used for testing performance impact of instruction fetch policies. - rnd_stall_regs[RND_STALL_DATA_EN] = 1; - rnd_stall_regs[RND_STALL_DATA_MODE] = 1; - rnd_stall_regs[RND_STALL_DATA_GNT] = 0; - rnd_stall_regs[RND_STALL_DATA_VALID] = 1; - rnd_stall_regs[RND_STALL_DATA_MAX] = 1; - rnd_stall_regs[RND_STALL_INSTR_EN] = 1; - rnd_stall_regs[RND_STALL_INSTR_MODE] = 1; - rnd_stall_regs[RND_STALL_INSTR_GNT] = 0; - rnd_stall_regs[RND_STALL_INSTR_VALID] = 1; - rnd_stall_regs[RND_STALL_INSTR_MAX] = 1; - end - else begin - randcase - 2: begin - // No delays - end - 1: begin - // Create RAM stall delays - rnd_stall_regs[RND_STALL_INSTR_EN] = 1; - rnd_stall_regs[RND_STALL_INSTR_MODE] = $urandom_range(2,1); - rnd_stall_regs[RND_STALL_INSTR_GNT] = $urandom_range(3,0); - rnd_stall_regs[RND_STALL_INSTR_VALID] = $urandom_range(3,0); - rnd_stall_regs[RND_STALL_INSTR_MAX] = $urandom_range(3,0); - end - endcase - - randcase - 2: begin - // No delays - end - 1: begin - // Create RAM stall delays - rnd_stall_regs[RND_STALL_DATA_EN] = 1; - rnd_stall_regs[RND_STALL_DATA_MODE] = $urandom_range(2,1); - rnd_stall_regs[RND_STALL_DATA_GNT] = $urandom_range(2,0); - rnd_stall_regs[RND_STALL_DATA_VALID] = $urandom_range(2,0); - rnd_stall_regs[RND_STALL_DATA_MAX] = $urandom_range(3,0); - end - endcase - end - end - - `uvm_info(RNDSTALL_TAG, $sformatf("INSTR OBI stall enable: %0d", rnd_stall_regs[RND_STALL_INSTR_EN]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("INSTR OBI stall mode: %0d", rnd_stall_regs[RND_STALL_INSTR_MODE]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("INSTR OBI stall gnt: %0d", rnd_stall_regs[RND_STALL_INSTR_GNT]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("INSTR OBI stall valid: %0d", rnd_stall_regs[RND_STALL_INSTR_VALID]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("INSTR OBI stall max: %0d", rnd_stall_regs[RND_STALL_INSTR_MAX]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("DATA OBI stall enable: %0d", rnd_stall_regs[RND_STALL_DATA_EN]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("DATA OBI stall mode: %0d", rnd_stall_regs[RND_STALL_DATA_MODE]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("DATA OBI stall gnt: %0d", rnd_stall_regs[RND_STALL_DATA_GNT]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("DATA OBI stall valid: %0d", rnd_stall_regs[RND_STALL_DATA_VALID]), UVM_LOW) - `uvm_info(RNDSTALL_TAG, $sformatf("DATA OBI stall max: %0d", rnd_stall_regs[RND_STALL_DATA_MAX]), UVM_LOW) -`endif - end : configure_stalls - -`ifndef VERILATOR - function bit is_stall_sim(); - return rnd_stall_regs[RND_STALL_DATA_EN] || rnd_stall_regs[RND_STALL_INSTR_EN]; - endfunction : is_stall_sim -`endif - - // handle the mapping of read and writes to either memory or pseudo - // peripherals (currently just a redirection of writes to stdout) - always_comb begin - tests_passed_o = '0; - tests_failed_o = '0; - exit_value_o = 0; - exit_valid_o = '0; - data_req_dec = '0; - data_addr_dec = '0; - data_wdata_dec = '0; - data_we_dec = '0; - data_be_dec = '0; - print_wdata = '0; - print_valid = '0; - timer_wdata = '0; - timer_reg_valid = '0; - timer_val_valid = '0; - debugger_wdata = '0; - debugger_valid = '0; - sig_end_d = sig_end_q; - sig_begin_d = sig_begin_q; - rnd_stall_req = '0; - rnd_stall_addr = '0; - rnd_stall_wdata = '0; - rnd_stall_we = '0; - rnd_num_req = '0; - cycle_count_clear = '0; - cycle_count_print = '0; - select_rdata_d = RAM; - transaction = T_PER; - - if (data_req_i & data_gnt_o) begin - if (data_we_i) begin // handle writes - if (data_addr_i < 2 ** RAM_ADDR_WIDTH || - ( (data_addr_i >= dm_halt_addr_i) && - (data_addr_i < (dm_halt_addr_i + (2 ** DBG_ADDR_WIDTH)) )) - ) - begin - data_req_dec = data_req_i; - if ( (data_addr_i >= dm_halt_addr_i) && - (data_addr_i < (dm_halt_addr_i + (2 ** DBG_ADDR_WIDTH)) ) - ) - // remap debug code to end of memory - data_addr_dec = (data_addr_i[RAM_ADDR_WIDTH-1:0] - dm_halt_addr_i[RAM_ADDR_WIDTH-1:0]) + - 2**RAM_ADDR_WIDTH - 2**DBG_ADDR_WIDTH; - else - data_addr_dec = data_addr_i[RAM_ADDR_WIDTH-1:0]; - data_wdata_dec = data_wdata_i; - data_we_dec = data_we_i; - data_be_dec = data_be_i; - transaction = T_RAM; - end else if (data_addr_i == MMADDR_PRINT) begin - print_wdata = data_wdata_i; - print_valid = '1; - - end else if (data_addr_i == MMADDR_TESTSTATUS) begin - if (data_wdata_i == 123456789) - tests_passed_o = '1; - else if (data_wdata_i == 1) - tests_failed_o = '1; - - end else if (data_addr_i == MMADDR_EXIT) begin - exit_valid_o = '1; - exit_value_o = data_wdata_i; - - end else if (data_addr_i == MMADDR_SIGBEGIN) begin - // sets signature begin - sig_begin_d = data_wdata_i; - - end else if (data_addr_i == MMADDR_SIGEND) begin - // sets signature end - sig_end_d = data_wdata_i; - - end else if (data_addr_i == MMADDR_SIGDUMP) begin - // dump signature and halt -`ifndef VERILATOR - if ($value$plusargs("signature=%s", sig_file)) begin - sig_fd = $fopen(sig_file, "w"); - if (sig_fd == 0) begin - errno = $ferror(sig_fd, error_str); - `uvm_error(MM_RAM_TAG, $sformatf("Cannot open signature file %s for writing (error_str: %s).", sig_file, error_str)) - use_sig_file = 1'b0; - end else begin - use_sig_file = 1'b1; - end - end - - sig_string = ""; - for (logic [31:0] addr = sig_begin_q; addr < sig_end_q; addr +=4) begin - sig_string = {sig_string, $sformatf("%x%x%x%x\n", dp_ram_i.mem[addr+3], dp_ram_i.mem[addr+2], - dp_ram_i.mem[addr+1], dp_ram_i.mem[addr+0])}; - if (use_sig_file) begin - $fdisplay(sig_fd, "%x%x%x%x", dp_ram_i.mem[addr+3], dp_ram_i.mem[addr+2], - dp_ram_i.mem[addr+1], dp_ram_i.mem[addr+0]); - end - end - `uvm_info(MM_RAM_TAG, $sformatf("Dumping signature:\n%s", sig_string), UVM_LOW) -`else - if ($value$plusargs("signature=%s", sig_file)) begin - sig_fd = $fopen(sig_file, "w"); - if (sig_fd == 0) begin - $error("can't open file"); - use_sig_file = 1'b0; - end else begin - use_sig_file = 1'b1; - end - end - - $display("%m @ %0t: Dumping signature", $time); - for (logic [31:0] addr = sig_begin_q; addr < sig_end_q; addr +=4) begin - $display("%x%x%x%x", dp_ram_i.mem[addr+3], dp_ram_i.mem[addr+2], - dp_ram_i.mem[addr+1], dp_ram_i.mem[addr+0]); - if (use_sig_file) begin - $fdisplay(sig_fd, "%x%x%x%x", dp_ram_i.mem[addr+3], dp_ram_i.mem[addr+2], - dp_ram_i.mem[addr+1], dp_ram_i.mem[addr+0]); - end - end -`endif // ifndef VERILATOR - exit_valid_o = '1; // signal halt to testbench - exit_value_o = '0; - - end else if (data_addr_i == MMADDR_TIMERREG) begin - timer_wdata = data_wdata_i; - timer_reg_valid = '1; - - end else if (data_addr_i == MMADDR_TIMERVAL) begin - timer_wdata = data_wdata_i; - timer_val_valid = '1; - - end else if (data_addr_i == MMADDR_DBG) begin - debugger_wdata = data_wdata_i; - debugger_valid = '1; - - end else if (data_addr_i[31:16] == MMADDR_RNDSTALL) begin - rnd_stall_req = data_req_i; - rnd_stall_wdata = data_wdata_i; - rnd_stall_addr = data_addr_i; - rnd_stall_we = data_we_i; - end else if (data_addr_i == MMADDR_TICKS) begin - cycle_count_clear = 1; - end else if (data_addr_i == MMADDR_TICKS_PRINT) begin - cycle_count_print = 1; - end else begin - // out of bounds write - end - - end else begin // handle reads - if (data_addr_i < 2 ** RAM_ADDR_WIDTH || - ( (data_addr_i >= dm_halt_addr_i) && - (data_addr_i < (dm_halt_addr_i + (2 ** DBG_ADDR_WIDTH)) )) - ) - begin - select_rdata_d = RAM; - - data_req_dec = data_req_i; - if ( (data_addr_i >= dm_halt_addr_i) && - (data_addr_i < (dm_halt_addr_i + (2 ** DBG_ADDR_WIDTH)) ) - ) - // remap debug code to end of memory - data_addr_dec = (data_addr_i[RAM_ADDR_WIDTH-1:0] - dm_halt_addr_i[RAM_ADDR_WIDTH-1:0]) + - 2**RAM_ADDR_WIDTH - 2**DBG_ADDR_WIDTH; - else - data_addr_dec = data_addr_i[RAM_ADDR_WIDTH-1:0]; - data_wdata_dec = data_wdata_i; - data_we_dec = data_we_i; - data_be_dec = data_be_i; - transaction = T_RAM; - end else if (data_addr_i[31:16] == MMADDR_RNDSTALL) begin - select_rdata_d = RND_STALL; - - rnd_stall_req = data_req_i; - rnd_stall_wdata = data_wdata_i; - rnd_stall_addr = data_addr_i; - rnd_stall_we = data_we_i; - end else if (data_addr_i[31:0] == MMADDR_RNDNUM) begin - rnd_num_req = 1'b1; - select_rdata_d = RND_NUM; - end else if (data_addr_i == MMADDR_TICKS) begin - select_rdata_d = TICKS; - end else - select_rdata_d = ERR; - - end - end - end - -`ifndef VERILATOR - // signal out of bound writes - out_of_bounds_write: assert property - (@(posedge clk_i) disable iff (~rst_ni) - (data_req_i && data_we_i |-> data_addr_i < 2 ** RAM_ADDR_WIDTH - || ( (data_addr_i >= dm_halt_addr_i) && - (data_addr_i < (dm_halt_addr_i + (2 ** DBG_ADDR_WIDTH)) ) - ) - || data_addr_i == MMADDR_PRINT - || data_addr_i == MMADDR_TIMERREG - || data_addr_i == MMADDR_TIMERVAL - || data_addr_i == MMADDR_DBG - || data_addr_i == MMADDR_TESTSTATUS - || data_addr_i == MMADDR_EXIT - || data_addr_i == MMADDR_SIGBEGIN - || data_addr_i == MMADDR_SIGEND - || data_addr_i == MMADDR_SIGDUMP - || data_addr_i == MMADDR_TICKS - || data_addr_i == MMADDR_TICKS_PRINT - || data_addr_i[31:16] == MMADDR_RNDSTALL)) - else `uvm_fatal(MM_RAM_TAG, $sformatf("out of bounds write to %08x with %08x", data_addr_i, data_wdata_i)) -`endif - - logic[31:0] data_rdata_mux; - - // make sure we select the proper read data - always_comb begin: read_mux - data_rdata_mux = '0; - - if(select_rdata_q == RAM) begin - data_rdata_mux = core_data_rdata; - end else if(select_rdata_q == RND_STALL) begin - data_rdata_mux = rnd_stall_rdata; -`ifndef VERILATOR - `uvm_fatal(MM_RAM_TAG, $sformatf("out of bounds read from %08x\nRandom stall generator is not supported with Verilator", data_addr_i)); -`endif - end else if (select_rdata_q == RND_NUM) begin - data_rdata_mux = rnd_num; - end else if (select_rdata_q == TICKS) begin - data_rdata_mux = cycle_count_q; -`ifndef VERILATOR - if (cycle_count_overflow_q) begin - `uvm_fatal(MM_RAM_TAG, "cycle counter read after overflow"); - end - end else if (select_rdata_q == ERR) begin - `uvm_fatal(MM_RAM_TAG, $sformatf("out of bounds read from %08x", data_addr_i)); -`endif - end - end - - // print to stdout pseudo peripheral - always_ff @(posedge clk_i, negedge rst_ni) begin: print_peripheral - if(print_valid) begin - if ($test$plusargs("verbose")) begin - if (32 <= print_wdata && print_wdata < 128) - $display("OUT: '%c'", print_wdata[7:0]); - else - $display("OUT: %3d", print_wdata); - - end else begin - $write("%c", print_wdata[7:0]); -`ifndef VERILATOR - $fflush(); -`endif - end - end - end - - assign irq_o = irq_q | rnd_irq << RND_IRQ_ID; - - // Set irq vector to timer_irq_mask_q when timer counts down - // irq bit cleared when acknowledged - always_ff @(posedge clk_i, negedge rst_ni) begin: tb_irq_timer - if(~rst_ni) begin - timer_irq_mask_q <= '0; - timer_cnt_q <= '0; - irq_q <= '0; - end else begin - // set timer irq mask - if(timer_reg_valid) - timer_irq_mask_q <= timer_wdata; - - // write timer value - if(timer_val_valid) - timer_cnt_q <= timer_wdata; - else if(timer_cnt_q > 0) - timer_cnt_q <= timer_cnt_q - 1; - - // set/clear irq - if(timer_cnt_q == 1) - irq_q <= timer_irq_mask_q ; - else if(irq_ack_i) - irq_q[irq_id_i] <= 1'b0; - - end // else: !if(~rst_ni) - end // block: tb_irq_timer - - // Count cycles - always_ff @(posedge clk_i, negedge rst_ni) begin: tb_cycle_counter - if (~rst_ni) begin - cycle_count_q <= '0; - cycle_count_overflow_q <= 0; - end else begin - - if (cycle_count_print) begin -`ifndef VERILATOR - `uvm_info(MM_RAM_TAG, $sformatf("Cycle count is %0d", cycle_count_q), UVM_LOW); -`else - $display("MM_RAM: Cycle count is %0d", cycle_count_q); -`endif - end - - if (cycle_count_clear) begin - cycle_count_q <= '0; - end else begin - cycle_count_q <= cycle_count_q + 1; - end - - if (cycle_count_q + 1 == 0) begin - cycle_count_overflow_q <= 1; - end - end - end - - // Update random stall control - always @(posedge clk_i, negedge rst_ni) begin: tb_stall - if(~rst_ni) begin - rnd_stall_rdata <= '0; - end else begin - if(rnd_stall_req) begin - if(rnd_stall_we) - rnd_stall_regs[rnd_stall_addr[5:2]] <= rnd_stall_wdata; - else - rnd_stall_rdata <= rnd_stall_regs[rnd_stall_addr[5:2]]; - end - end - end // block: tb_stall - - // ------------------------------------------------------------- - // Generate a random number using the SystemVerilog random number function - always_ff @(posedge clk_i, negedge rst_ni) begin : rnd_num_gen - if (!rst_ni) - rnd_num <= 32'h0; - else if (rnd_num_req) -`ifndef VERILATOR - rnd_num <= $urandom(); -`else - rnd_num <= 32'h0; -`endif - end - - // ------------------------------------------------------------- - // Control debug_req. Writing to this alias will change or create - // a debug_req pulse. The debug_req can be a pulse or level change, - // can have a delay when to assert, and also have pulse duration - // determined by the values in the wdata field: - // - // wdata[31] = debug_req signal value - // wdata[30] = debug request mode, 0= level, 1= pulse - // wdata[29] = debug pulse duration random - // wdata[28:16] = debug pulse duration or pulse random max range - // wdata[15] = random start - // wdata[14:0] = start delay or start random max range - - logic [14:0] debugger_start_cnt_q; - logic debug_req_value_q; - logic [12:0] debug_req_duration_q; - always_ff @(posedge clk_i, negedge rst_ni) begin: tb_debugger - if(~rst_ni) begin - debugger_start_cnt_q <= '0; - debug_req_value_q <= '0; - debug_req_duration_q <= '0; - debug_req_o <= '0; - end else begin - - if(debugger_valid && (debugger_start_cnt_q==0) && (debug_req_duration_q==0)) begin - if(debugger_wdata[15]) //If random start - // then set max random delay range to wdata[14:0] - // note, if wdata[14:0] == 0, then assign max random range to 128 -`ifndef VERILATOR - debugger_start_cnt_q <= $urandom_range(1,~|debugger_wdata[14:0] ? 128 : debugger_wdata[14:0]); -`else - debugger_start_cnt_q <= 1; -`endif - else - // else, the delay is determined by wdata[14:0] - // note, if wdata[14:0] == 0, then assign value to 1 - debugger_start_cnt_q <= ~|debugger_wdata[14:0] ? 1 : debugger_wdata[14:0]; - - debug_req_value_q <= debugger_wdata[31]; // value to be applied to debug_req - - if(!debugger_wdata[30]) // If mode is level then set duration to 0 - debug_req_duration_q <= 'b0; - else // Else mode is pulse - if(debugger_wdata[29]) // If random pulse width - // then set max random pulse width to wdata[28:16] - // note, if wdata[28:16] ==0, then assign max to 128 -`ifndef VERILATOR - debug_req_duration_q <= $urandom_range(1,~|debugger_wdata[28:16] ? 128 : debugger_wdata[28:16]); -`else - debugger_start_cnt_q <= 1; -`endif - else - // else, the pulse is determined by wdata[28:16] - // note, if wdata[28:16]==0, then set pulse width to 1 - debug_req_duration_q <= ~|debugger_wdata[28:16] ? 1 : debugger_wdata[28:16]; - - end else begin - // Count down the delay to start - if(debugger_start_cnt_q > 0)begin - debugger_start_cnt_q <= debugger_start_cnt_q - 1; - // At count == 1, then assert the debug_req - if(debugger_start_cnt_q == 1) - debug_req_o <= debug_req_value_q; - end - // Count down debug_req pulse duration - else if(debug_req_duration_q > 0)begin - debug_req_duration_q <= debug_req_duration_q - 1; - // At count == 1, then de-assert debug_req - if(debug_req_duration_q == 1) - debug_req_o <= !debug_req_value_q; - end - end - end - end - - // ------------------------------------------------------------- - // show writes if requested - always_ff @(posedge clk_i, negedge rst_ni) begin: verbose_writes - if ($test$plusargs("verbose") && data_req_i && data_we_i) - $display("write addr=0x%08x: data=0x%08x", - data_addr_i, data_wdata_i); - end - - // instantiate the ram - dp_ram - #(.ADDR_WIDTH (RAM_ADDR_WIDTH), - .INSTR_RDATA_WIDTH(INSTR_RDATA_WIDTH)) - dp_ram_i - ( - .clk_i ( clk_i ), - - .en_a_i ( ram_instr_req ), - .addr_a_i ( ram_instr_addr ), - .wdata_a_i ( '0 ), // Not writing so ignored - .rdata_a_o ( ram_instr_rdata ), - .we_a_i ( '0 ), - .be_a_i ( 4'b1111 ), // Always want 32-bits - - .en_b_i ( ram_data_req ), - .addr_b_i ( ram_data_addr ), - .wdata_b_i ( ram_data_wdata ), - .rdata_b_o ( ram_data_rdata ), - .we_b_i ( ram_data_we ), - .be_b_i ( ram_data_be )); - - riscv_rvalid_stall instr_rvalid_stall_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .req_i ( instr_req_i ), - .gnt_i ( instr_gnt_o ), - .we_i ( 1'b0 ), - .rdata_i ( ram_instr_rdata ), - .rdata_o ( instr_rdata_o ), - .rvalid_o ( instr_rvalid_o ), - .en_stall_i ( rnd_stall_regs[RND_STALL_INSTR_EN][0]), - .stall_mode_i ( rnd_stall_regs[RND_STALL_INSTR_MODE] ), - .max_stall_i ( rnd_stall_regs[RND_STALL_INSTR_MAX] ), - .valid_stall_i( rnd_stall_regs[RND_STALL_INSTR_VALID])); - - riscv_rvalid_stall data_rvalid_stall_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .req_i ( data_req_i ), - .gnt_i ( data_gnt_o ), - .we_i ( data_we_i ), - .rdata_i ( data_rdata_mux ), - .rdata_o ( data_rdata_o ), - .rvalid_o ( data_rvalid_o ), - .en_stall_i ( rnd_stall_regs[RND_STALL_DATA_EN][0]), - .stall_mode_i ( rnd_stall_regs[RND_STALL_DATA_MODE] ), - .max_stall_i ( rnd_stall_regs[RND_STALL_DATA_MAX] ), - .valid_stall_i( rnd_stall_regs[RND_STALL_DATA_VALID])); - - // signature range - always @(posedge clk_i, negedge rst_ni) begin - if (~rst_ni) begin - sig_end_q <= '0; - sig_begin_q <= '0; - end else begin - sig_end_q <= sig_end_d; - sig_begin_q <= sig_begin_d; - end - end - - always_ff @(posedge clk_i, negedge rst_ni) begin - if (~rst_ni) begin - select_rdata_q <= RAM; - end else begin - select_rdata_q <= select_rdata_d; - end - end - - assign instr_gnt_o = ram_instr_gnt; - assign data_gnt_o = ram_data_gnt; - - // remap debug code to end of memory - assign instr_addr_remap = ( (instr_addr_i >= dm_halt_addr_i) && - (instr_addr_i < (dm_halt_addr_i + (2 ** DBG_ADDR_WIDTH)) ) ) ? - (instr_addr_i - dm_halt_addr_i) + 2**RAM_ADDR_WIDTH - 2**DBG_ADDR_WIDTH : - instr_addr_i ; - - always_comb - begin - ram_instr_req = instr_req_i; - ram_instr_addr = instr_addr_remap; - ram_instr_gnt = instr_req_i ? 1'b1 : $urandom; - core_instr_rdata = ram_instr_rdata; - - ram_data_req = data_req_dec; - ram_data_addr = data_addr_dec; - ram_data_gnt = data_req_i ? 1'b1 : $urandom; - core_data_rdata = ram_data_rdata; - ram_data_wdata = data_wdata_dec; - ram_data_we = data_we_dec; - ram_data_be = data_be_dec; - - if(rnd_stall_regs[RND_STALL_INSTR_EN]) begin - ram_instr_req = rnd_stall_instr_req; - ram_instr_gnt = rnd_stall_instr_gnt; - end - if(rnd_stall_regs[RND_STALL_DATA_EN]) begin - ram_data_req = rnd_stall_data_req; - ram_data_gnt = rnd_stall_data_gnt; - end - end - - riscv_gnt_stall - #( - .DATA_WIDTH (INSTR_RDATA_WIDTH), - .RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ) - ) - instr_gnt_stall_i - ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .grant_mem_i ( rnd_stall_instr_req ), - .grant_core_o ( rnd_stall_instr_gnt ), - - .req_core_i ( instr_req_i ), - .req_mem_o ( rnd_stall_instr_req ), - - .en_stall_i ( rnd_stall_regs[RND_STALL_INSTR_EN][0]), - .stall_mode_i ( rnd_stall_regs[RND_STALL_INSTR_MODE] ), - .max_stall_i ( rnd_stall_regs[RND_STALL_INSTR_MAX] ), - .gnt_stall_i ( rnd_stall_regs[RND_STALL_INSTR_GNT] ) - ); - - riscv_gnt_stall - #( - .DATA_WIDTH (DATA_RDATA_WIDTH), - .RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ) - ) - data_gnt_stall_i - ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .grant_mem_i ( rnd_stall_data_req ), - .grant_core_o ( rnd_stall_data_gnt ), - - .req_core_i ( data_req_i ), - .req_mem_o ( rnd_stall_data_req ), - - .en_stall_i ( rnd_stall_regs[RND_STALL_DATA_EN][0]), - .stall_mode_i ( rnd_stall_regs[RND_STALL_DATA_MODE] ), - .max_stall_i ( rnd_stall_regs[RND_STALL_DATA_MAX] ), - .gnt_stall_i ( rnd_stall_regs[RND_STALL_DATA_GNT] ) - ); - -`ifndef VERILATOR - riscv_random_interrupt_generator - random_interrupt_generator_i - ( - .rst_ni ( rst_ni ), - .clk_i ( clk_i ), - .irq_i ( 1'b0 ), - .irq_id_i ( '0 ), - .irq_ack_i ( irq_ack_i == 1'b1 && irq_id_i == RND_IRQ_ID ), - .irq_ack_o ( ), - .irq_o ( rnd_irq ), - .irq_id_o ( /*disconnected, always generate RND_IRQ_ID*/ ), - .irq_mode_i ( rnd_stall_regs[10] ), - .irq_min_cycles_i ( rnd_stall_regs[11] ), - .irq_max_cycles_i ( rnd_stall_regs[12] ), - .irq_min_id_i ( RND_IRQ_ID ), - .irq_max_id_i ( RND_IRQ_ID ), - .irq_act_id_o ( ), - .irq_id_we_o ( ), - .irq_pc_id_i ( pc_core_id_i ), - .irq_pc_trig_i ( rnd_stall_regs[13] ) - ); -`endif - -endmodule // ram diff --git a/cv32e40x/tb/core/tb_riscv/README.md b/cv32e40x/tb/core/tb_riscv/README.md deleted file mode 100644 index f1f0f3bbc2..0000000000 --- a/cv32e40x/tb/core/tb_riscv/README.md +++ /dev/null @@ -1,56 +0,0 @@ -# TB_RISCV: VERIFICATION ENVIRONMENT FOR THE PULP CORES - -Files and directories foundn here are adopted from the testbench for the PULP -cores. They are now known as the `core` testbench of the CV32E40X testbench. -Note that some information in this file may be out of date. - -## Description - -The top file of this repository is called `tb_riscv_core.sv`. The input and output signals of this unit are the same as RI5CY. -It includes the following components: - - The core instance - - The instance of the perturbation module, that is described in the file `riscv_perturbation.sv`. - This programmable unit is able to introduce stalls on the memory interfaces and to generate interrupts requests. This is accomplished with the units `riscv_random_stall.sv` and `riscv_random_interrupt_generator.sv`, for stalls and interrupts respectively. - - The instance of the simulation checker is used to check the functional correctness of the core, you should set to 1 the parameter SIMCHECKER in the parameters list of the `tb_riscv_core.sv`. - -## How to set up the perturbation module - -The perturbation module is programmable. It contains a set of memory-mapped registers used to program the module according to the user needs. These registers are mapped in the debug unit address space, and the same buses of the debug unit are used to read and write those registers. - -#### How to set up the stalls generators - -Since both the instruction and data stalls generators are instances of the same unit, they are configured with the same steps. - -1) The default mode does not introduce any stalls on the interface. The input of the units are directly forwarded to the output ports. - -2) The mode STANDARD will introduce a fixed number of stalls on the specified signals of the desired interface. - -3) The mode RANDOM will randomly injects stalls on the desired interface. - -#### How to set up the interrupt generator - -As for the stalls generators, the interrupt generator can be easily programmed with load and store instructions. Again, three working modes are supported: - -1) The default mode does not generate any interrupt request. The input of the module, coming from the event unit and the core, are simply forwarded to the output ports. This allows the external peripherals to eventually raise interrupt requests. - -2) The mode RANDOM will randomize on the generation of interrupt requests. In particular, the module randomizes on both the number of stalls that separate two consecutive interrupt requests, as well as on the interrupt causes. - -3) The mode PC_TRIG is about raising an interrupt request when the value of the program counter, taken from the ID stage of the core, is equal to the value stored in a proper perturbation register. For this interrupt cause, the identifier 18 is reserved. - -Following an example to directly use the Assembler to set up the interrupt generator working with the PC-triggered mode: - -``` -la %[pc_trig], pc_label; -sw %[pc_trig], 0(%[perturbation_reg_addr]); -sw %[irq_mode], 0(%[perturbation_mode_addr]); -.... -pc_label: nop; -.... -``` - -In the previous example, `pc_label` represents the instruction address at which the interrupt request will be raised (i.e. when the `nop` instruction is in the ID stage of the core). -The address is stored in the perturbation register and The PC_TRIG mode is set via the last store instruction. - -## TODO: - -The simulation checker should be used yet. It is under development. diff --git a/cv32e40x/tb/core/tb_riscv/include/perturbation_defines.sv b/cv32e40x/tb/core/tb_riscv/include/perturbation_defines.sv deleted file mode 100644 index 3bd380de25..0000000000 --- a/cv32e40x/tb/core/tb_riscv/include/perturbation_defines.sv +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// // -// Author: Francesco Minervini - minervif@student.ethz.ch // -// // -// Additional contributions by: // -// Design Name: Interrupt generator // -// Project Name: RI5CY, Zeroriscy // -// Language: SystemVerilog // -// // -// Description: Defines for the perturbation module // -////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -package perturbation_defines; - - parameter STANDARD = 32'h1; - parameter RANDOM = 32'h2; - parameter PC_TRIG = 32'h3; - -endpackage \ No newline at end of file diff --git a/cv32e40x/tb/core/tb_riscv/riscv_gnt_stall.sv b/cv32e40x/tb/core/tb_riscv/riscv_gnt_stall.sv deleted file mode 100644 index 9148158b87..0000000000 --- a/cv32e40x/tb/core/tb_riscv/riscv_gnt_stall.sv +++ /dev/null @@ -1,143 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// -// -// riscv_gnt_stall.sv -// -// OBI Grant stalling module for CV32E40X -// -// Author: Steve Richmond -// email: steve.richmond@silabs.com -// -////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -module riscv_gnt_stall -`ifndef VERILATOR - import perturbation_defines::*; -`endif - #( - parameter MAX_STALL_N = 1, - RAM_ADDR_WIDTH = 32, - DATA_WIDTH = 32 - ) - -( - input logic clk_i, - input logic rst_ni, - - input logic req_core_i, - output logic req_mem_o, - - // grant to memory - output logic grant_core_o, - input logic grant_mem_i, - - input logic en_stall_i, - input logic [31:0] stall_mode_i, - input logic [31:0] max_stall_i, - input logic [31:0] gnt_stall_i -); - -// ----------------------------------------------------------------------------------------------- -// Local variables -// ----------------------------------------------------------------------------------------------- - -logic req_core_i_q; -logic grant_core_o_q; - -integer grant_delay_cnt; - -integer delay_value; - -// ----------------------------------------------------------------------------------------------- -// Tasks and functions -// ----------------------------------------------------------------------------------------------- -task set_delay_value(); -`ifndef VERILATOR - if (!en_stall_i) - delay_value = 0; - else if (stall_mode_i == perturbation_defines::STANDARD) - delay_value = gnt_stall_i; - else if (stall_mode_i == perturbation_defines::RANDOM) - delay_value = $urandom_range(max_stall_i, 0); - else - delay_value = 0; -`else - delay_value = 0; -`endif -endtask : set_delay_value - -// ----------------------------------------------------------------------------------------------- -// Begin module code -// ----------------------------------------------------------------------------------------------- - -assign req_mem_o = req_core_i; - -always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - req_core_i_q <= 1'b0; - grant_core_o_q <= 1'b0; - end - else begin - req_core_i_q <= req_core_i; - grant_core_o_q <= grant_core_o; - end -end - -always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - grant_core_o <= 1'b0; - grant_delay_cnt <= 0; - end - else begin -`ifdef VERILATOR - //#1; -`else - #(100ps); -`endif - - // When request is removed, randomize gnt - if (!req_core_i) begin - grant_core_o <= $urandom; - end - - // New request coming in - else if (grant_core_o_q || !req_core_i_q) begin - // Initialize stall here - set_delay_value(); - if (delay_value == 0) begin - grant_delay_cnt <= 0; - grant_core_o <= 1'b1; - end - else begin - grant_delay_cnt <= delay_value; - grant_core_o <= 1'b0; - end - end - else if (grant_delay_cnt == 1) begin - grant_delay_cnt <= 0; - grant_core_o <= 1'b1; - end - else begin - grant_delay_cnt <= grant_delay_cnt - 1; - end - end -end - -endmodule : riscv_gnt_stall diff --git a/cv32e40x/tb/core/tb_riscv/riscv_perturbation.sv b/cv32e40x/tb/core/tb_riscv/riscv_perturbation.sv deleted file mode 100644 index 1f915fab4d..0000000000 --- a/cv32e40x/tb/core/tb_riscv/riscv_perturbation.sv +++ /dev/null @@ -1,322 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -////////////////////////////////////////////////////////////////////////////////////////////// -// // -// Author: Francesco Minervini - minervif@student.ethz.ch // -// // -// Additional contributions by: // -// Design Name: Perturbation Unit // -// Project Name: RI5CY, Zeroriscy // -// Language: SystemVerilog // -// // -// Description: This module instantiates both data and instructions stalls // -// generators as well as the random interrupt generator // -// // -////////////////////////////////////////////////////////////////////////////////////////////// - -import riscv_defines::*; -`include "riscv_config.sv" - -module riscv_perturbation -#( - parameter PERT_REGS = 15, - parameter INSTR_RDATA_WIDTH = 32 -) - -( - input logic rst_ni, - input logic clk_i, - - //Instruction interface - input logic pert_instr_req_i, - output logic pert_instr_req_o, - input logic pert_instr_grant_i, - output logic pert_instr_grant_o, - input logic pert_instr_rvalid_i, - output logic pert_instr_rvalid_o, - input logic [31:0] pert_instr_addr_i, - output logic [31:0] pert_instr_addr_o, - input logic [INSTR_RDATA_WIDTH-1:0] pert_instr_rdata_i, - output logic [INSTR_RDATA_WIDTH-1:0] pert_instr_rdata_o, - - //Data interface - input logic pert_data_req_i, - output logic pert_data_req_o, - input logic pert_data_grant_i, - output logic pert_data_grant_o, - input logic pert_data_rvalid_i, - output logic pert_data_rvalid_o, - input logic pert_data_we_i, - output logic pert_data_we_o, - input logic [3:0] pert_data_be_i, - output logic [3:0] pert_data_be_o, - input logic [31:0] pert_data_addr_i, - output logic [31:0] pert_data_addr_o, - input logic [31:0] pert_data_wdata_i, - output logic [31:0] pert_data_wdata_o, - input logic [INSTR_RDATA_WIDTH-1:0] pert_data_rdata_i, - output logic [INSTR_RDATA_WIDTH-1:0] pert_data_rdata_o, - - //Debug-perturbation interface - input logic pert_debug_req_i, - output logic pert_debug_req_o, - input logic pert_debug_gnt_i, - output logic pert_debug_gnt_o, - input logic pert_debug_rvalid_i, - output logic pert_debug_rvalid_o, - input logic pert_debug_we_i, - output logic pert_debug_we_o, - input logic [14:0] pert_debug_addr_i, - output logic [14:0] pert_debug_addr_o, - input logic [31:0] pert_debug_wdata_i, - output logic [31:0] pert_debug_wdata_o, - input logic [31:0] pert_debug_rdata_i, - output logic [31:0] pert_debug_rdata_o, - - //Interrupt interface - input logic pert_irq_i, - output logic pert_irq_o, - input logic [4:0] pert_irq_id_i, - output logic [4:0] pert_irq_id_o, - input logic pert_irq_ack_i, - output logic pert_irq_ack_o, - input logic [4:0] pert_irq_core_resp_id_i, - output logic [4:0] pert_irq_core_resp_id_o, - input logic [31:0] pert_pc_id_i - ); - - logic [31:0] pert_regs [0:PERT_REGS-1]; - logic [3:0] pert_addr_int; - logic [31:0] irq_act_id_int; - logic irq_id_resp_we_i; - //Signals for instruction stalls generator - logic [31:0] pert_instr_mode, pert_instr_max_stall, pert_instr_grant_stall, pert_instr_valid_stall; - //Signals for data stalls generator - logic [31:0] pert_data_mode, pert_data_max_stall, pert_data_grant_stall, pert_data_valid_stall; - //Signals for interrupt generator - logic [31:0] pert_irq_mode, pert_irq_min_cycles, pert_irq_max_cycles, pert_irq_min_id, pert_irq_max_id, pert_irq_pc_trig; - - logic is_perturbation; - - riscv_random_stall instr_random_stalls - ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .grant_per_i ( pert_instr_grant_i ), - .grant_per_o ( pert_instr_grant_o ), - - .rvalid_per_i ( pert_instr_rvalid_i ), - .rvalid_per_o ( pert_instr_rvalid_o ), - - .rdata_per_i ( pert_instr_rdata_i ), - .rdata_per_o ( pert_instr_rdata_o ), - - .req_per_i ( pert_instr_req_i ), - .req_mem_o ( pert_instr_req_o ), - - .addr_per_i ( pert_instr_addr_i ), - .addr_mem_o ( pert_instr_addr_o ), - - .wdata_per_i ( ), - .wdata_mem_o ( ), - - .we_per_i ( ), - .we_mem_o ( ), - - .be_per_i ( ), - .be_mem_o ( ), - - .dbg_req_i ( pert_debug_req_i ), - .dbg_we_i ( pert_debug_we_i ), - - .dbg_mode_i ( pert_instr_mode ), - .dbg_max_stall_i ( pert_instr_max_stall ), - - .dbg_gnt_stall_i ( pert_instr_grant_stall ), - .dbg_valid_stall_i ( pert_instr_valid_stall ) - ); - - riscv_random_stall data_random_stalls - ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .grant_per_i ( pert_data_grant_i ), - .grant_per_o ( pert_data_grant_o ), - - .rvalid_per_i ( pert_data_rvalid_i ), - .rvalid_per_o ( pert_data_rvalid_o ), - - .rdata_per_i ( pert_data_rdata_i ), - .rdata_per_o ( pert_data_rdata_o ), - - .req_per_i ( pert_data_req_i ), - .req_mem_o ( pert_data_req_o ), - - .addr_per_i ( pert_data_addr_i ), - .addr_mem_o ( pert_data_addr_o ), - - .wdata_per_i ( pert_data_wdata_i ), - .wdata_mem_o ( pert_data_wdata_o ), - - .we_per_i ( pert_data_we_i ), - .we_mem_o ( pert_data_we_o ), - - .be_per_i ( pert_data_be_i ), - .be_mem_o ( pert_data_be_o ), - - .dbg_req_i ( pert_debug_req_i ), - .dbg_we_i ( pert_debug_we_i ), - - .dbg_mode_i ( pert_data_mode ), - .dbg_max_stall_i ( pert_data_max_stall ), - - .dbg_gnt_stall_i ( pert_data_grant_stall ), - .dbg_valid_stall_i ( pert_data_valid_stall ) - ); - - - riscv_random_interrupt_generator riscv_random_interrupt_generator_i - ( - .rst_ni ( rst_ni ), - .clk_i ( clk_i ), - .irq_i ( pert_irq_i ), - .irq_id_i ( pert_irq_id_i ), - .irq_ack_i ( pert_irq_ack_i ), - .irq_ack_o ( pert_irq_ack_o ), - .irq_o ( pert_irq_o ), - .irq_id_o ( pert_irq_id_o ), - .irq_mode_i ( pert_irq_mode ), - .irq_min_cycles_i ( pert_irq_min_cycles ), - .irq_max_cycles_i ( pert_irq_max_cycles ), - .irq_min_id_i ( pert_irq_min_id ), - .irq_max_id_i ( pert_irq_max_id ), - .irq_act_id_o ( irq_act_id_int ), - .irq_id_we_o ( irq_id_resp_we_i ), - .irq_pc_id_i ( pert_pc_id_i ), - .irq_pc_trig_i ( pert_irq_pc_trig ) - ); - -assign pert_addr_int = pert_debug_addr_i[5:2]; - -assign is_perturbation = pert_debug_addr_i[13:8] == 6'b000110; - -always_ff @(posedge clk_i or negedge rst_ni) begin - if(~rst_ni) begin - for(int i=0; i= 0; - n<= max_val; - }; - stalls = wait_cycles.n; - - end else begin - stalls = 0; - end - - - while(stalls != 0) begin - @(negedge clk_i); - stalls--; - end - - @(negedge clk_i); - if(req_per_q == 1'b1) begin - grant_core_o = 1'b1; - mem_acc.addr = addr_core_i; - mem_acc.be = be_core_i; - mem_acc.we = we_core_i; - mem_acc.wdata = wdata_core_i; - core_reqs.put(mem_acc); - core_resps_granted.put(1'b1); - end - - end - end - - initial - begin : data_process - stall_mem_t mem_acc; - automatic rand_data_cycles wait_cycles = new (); - logic granted; - int temp, stalls, max_val; - - while(1) begin - @(posedge clk_i); - #1; - rvalid_core_o = 1'b0; - rdata_core_o = 'x; - - core_resps_granted.get(granted); - - core_resps.get(mem_acc); - - if(stall_mode_i == STANDARD) begin //FIXED NUMBER OF STALLS MODE - stalls = valid_stall_i; - end else if(stall_mode_i == RANDOM) begin - max_val = max_stall_i; - temp = wait_cycles.randomize() with { - n>= 0; - n<= max_val; - }; - stalls = wait_cycles.n; - - end else begin - - stalls = 0; - end - - - while(stalls != 0) begin - @(negedge clk_i); - stalls--; - end - - rdata_core_o = mem_acc.rdata; - rvalid_core_o = 1'b1; - end - end - - initial - begin : wait_for_grant - stall_mem_t mem_acc; - we_mem_o = 1'b0; - req_mem_o = 1'b0; - addr_mem_o = '0; - be_mem_o = 4'b0; - wdata_mem_o = 'x; - - while(1) begin - @(posedge clk_i); - #1; - req_mem_o = 1'b0; - addr_mem_o = '0; - wdata_mem_o = 'x; - core_reqs.get(mem_acc); - req_mem_o = 1'b1; - addr_mem_o = mem_acc.addr; - we_mem_o = mem_acc.we; - be_mem_o = mem_acc.be; - wdata_mem_o = mem_acc.wdata; - - wait(grant_per_q); - memory_transfers.put(mem_acc); - - end - end - - initial - begin : wait_for_valid - stall_mem_t mem_acc; - while(1) begin - memory_transfers.get(mem_acc); - - wait(rvalid_per_q == 1'b1); - @(negedge clk_i); - mem_acc.rdata = rdata_mem_i; - - core_resps.put(mem_acc); - - end - end - `endif - endmodule diff --git a/cv32e40x/tb/core/tb_riscv/riscv_rvalid_stall.sv b/cv32e40x/tb/core/tb_riscv/riscv_rvalid_stall.sv deleted file mode 100644 index 039fe701e7..0000000000 --- a/cv32e40x/tb/core/tb_riscv/riscv_rvalid_stall.sv +++ /dev/null @@ -1,184 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// -// -// riscv_rvalid_stall.sv -// -// Simple FIFO to store data responses for the OBI -// This file should be completely compatible with Verilator and all commerical SystemVerilog simulators -// -// Author: Steve Richmond -// email: steve.richmond@silabs.com -// -////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -module riscv_rvalid_stall( - // Clock, reset - input clk_i, - input rst_ni, - - // Request/gnt interface, to push entries into the FIFO - input req_i, - input gnt_i, - input we_i, - - // Read data valid, signals that read data from RAM is valid on this cycle - input [31:0] rdata_i, - - // Response bus, connect directly to OBI response port - output logic [31:0] rdata_o, - output logic rvalid_o, - - // Stall knobs - input logic en_stall_i, - input logic [31:0] stall_mode_i, - input logic [31:0] max_stall_i, - input logic [31:0] valid_stall_i -); - -// ----------------------------------------------------------------------------------------------- -// Local parameters -// ----------------------------------------------------------------------------------------------- -localparam FIFO_DATA_WL = 32; -localparam FIFO_DELAY_WL = 4; // Up to 15 cycles of delay -localparam FIFO_WE_WL = 1; - -localparam FIFO_DATA_LSB = 0; -localparam FIFO_DELAY_LSB = FIFO_DATA_LSB + FIFO_DATA_WL; -localparam FIFO_WE_LSB = FIFO_DELAY_LSB + FIFO_DELAY_WL; - -localparam FIFO_WL = FIFO_DATA_WL + FIFO_DELAY_WL + FIFO_WE_WL; - -localparam FIFO_DEPTH = 8; -localparam FIFO_PTR_WL = $clog2(FIFO_DEPTH) + 1; - -// ----------------------------------------------------------------------------------------------- -// Local variables -// ----------------------------------------------------------------------------------------------- -wire fifo_empty; -wire fifo_full; -wire fifo_push; - -logic [FIFO_PTR_WL-1:0] wptr; -logic [FIFO_PTR_WL-1:0] rptr; -logic [FIFO_PTR_WL-2:0] wptr_rdata; - -reg [FIFO_WL-1:0] fifo[FIFO_DEPTH]; -reg rvalid_i_q; - -wire [FIFO_DELAY_WL-1:0] current_delay; - -integer i; - -// ----------------------------------------------------------------------------------------------- -// Tasks and functions -// ----------------------------------------------------------------------------------------------- -`ifndef VERILATOR -function logic [FIFO_DELAY_WL-1:0] get_random_delay(); - if (!en_stall_i) - get_random_delay = 0; - else if (stall_mode_i == perturbation_defines::STANDARD) - get_random_delay = valid_stall_i; - else if (stall_mode_i == perturbation_defines::RANDOM) - get_random_delay = $urandom_range(max_stall_i, 0); - else - get_random_delay = 0; -endfunction : get_random_delay -`endif - -// ----------------------------------------------------------------------------------------------- -// Begin module code -// ----------------------------------------------------------------------------------------------- - -assign fifo_push = req_i && gnt_i; - -always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - wptr <= '0; - rptr <= '0; - end - else begin - wptr <= (req_i && gnt_i) ? wptr + 1 : wptr; - rptr <= (rvalid_o) ? rptr + 1 : rptr; - end -end - -assign fifo_empty = (wptr == rptr) ? 1 : 0; -assign fifo_full = (wptr == {~rptr[FIFO_PTR_WL-1], rptr[FIFO_PTR_WL-2:0]}) ? 1 : 0; - -always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - for (i = 0; i < FIFO_DEPTH; i++) begin - fifo[i] = {FIFO_WL{1'b0}}; - end - end - else begin - if (fifo_push) begin - fifo[wptr[FIFO_PTR_WL-2:0]] = { - we_i, -`ifdef VERILATOR - 4'h0, -`else - get_random_delay(), -`endif - 32'h0}; - - wptr_rdata <= wptr[FIFO_PTR_WL-2:0]; - - rvalid_i_q <= (!we_i) ? 1 : 0; - end - else begin - rvalid_i_q <= 1'b0; - end - - if (rvalid_i_q) begin - fifo[wptr_rdata][31:0] <= fifo[wptr_rdata][FIFO_WE_LSB] ? 32'h0 : rdata_i; - end - end -end - -// Read interface -assign current_delay = fifo[rptr[FIFO_PTR_WL-2:0]][FIFO_DELAY_LSB +: FIFO_DELAY_WL]; - -always @(*) begin - rdata_o = '0; - rvalid_o = '0; - if (!fifo_empty && current_delay == 0) begin - rvalid_o = 1'b1; - if (rptr[FIFO_PTR_WL-2:0] == wptr_rdata && rvalid_i_q) - if (fifo[rptr[FIFO_PTR_WL-2:0]][FIFO_WE_LSB]) - rdata_o = 32'h0; - else - rdata_o = rdata_i; - else - rdata_o = fifo[rptr[FIFO_PTR_WL-2:0]][FIFO_DATA_LSB +: FIFO_DATA_WL]; - end -end - -// Manage current delay counter -always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - end - else begin - if (!fifo_empty && current_delay > 0) begin - fifo[rptr[FIFO_PTR_WL-2:0]][FIFO_DELAY_LSB +: FIFO_DELAY_WL] <= current_delay - 1; - end - end -end - -endmodule : riscv_rvalid_stall diff --git a/cv32e40x/tb/core/tb_riscv/riscv_simchecker.sv b/cv32e40x/tb/core/tb_riscv/riscv_simchecker.sv deleted file mode 100644 index 5442475fbd..0000000000 --- a/cv32e40x/tb/core/tb_riscv/riscv_simchecker.sv +++ /dev/null @@ -1,645 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -////////////////////////////////////////////////////////////////////////////////////////////// -// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch // -// // -// Additional contributions by: // -// Francesco Minervini - minervif@student.ethz.ch // -// // -// Design Name: RISC-V Simchecker // -// Project Name: RI5CY // -// Language: SystemVerilog // -// // -// Description: Compares the executed instructions with a golden model // -// // -////////////////////////////////////////////////////////////////////////////////////////////// -`ifndef VERILATOR -`include "riscv_config.sv" - -import riscv_defines::*; - -// do not import anything if the simchecker is not used -// this gets rid of warnings during simulation -import "DPI-C" function chandle riscv_checker_init(input int boot_addr, input int core_id, input int cluster_id, input string name); -import "DPI-C" function int riscv_checker_step(input chandle cpu, input longint simtime, input int cycle, input logic [31:0] pc, input logic [31:0] instr); -import "DPI-C" function void riscv_checker_irq(input chandle cpu, input int irq, input int irq_no); -import "DPI-C" function void riscv_checker_mem_access(input chandle cpu, input int we, input logic [31:0] addr, input logic [31:0] data); -import "DPI-C" function void riscv_checker_reg_access(input chandle cpu, input logic [31:0] addr, input logic [31:0] data); - -module riscv_simchecker -( - // Clock and Reset - input logic clk, - input logic rst_n, - - input logic fetch_enable, - input logic [31:0] boot_addr, - input logic [3:0] core_id, - input logic [5:0] cluster_id, - - input logic [15:0] instr_compressed, - input logic if_valid, - input logic pc_set, - - input logic [31:0] pc, - input logic [31:0] instr, - input logic is_compressed, - input logic id_valid, - input logic is_decoding, - input logic is_illegal, - input logic is_interrupt, - input logic [4:0] irq_no, - input logic pipe_flush, - input logic irq_i, - input logic is_mret, - - input logic int_enable, - - //Signals added for FPU ops - input logic lsu_ready_wb, - input logic apu_ready_wb, - input logic wb_contention, - - input logic apu_en_id, - input logic apu_req, - input logic apu_gnt, - input logic apu_valid, - input logic apu_singlecycle, - input logic apu_multicycle, - input logic [1:0] apu_latency, - input logic apu_active, - input logic apu_en_ex, -//////////////////////////////////////////// - input logic ex_valid, - input logic [ 5:0] ex_reg_addr, - - input logic ex_reg_we, - input logic [31:0] ex_reg_wdata, - - input logic ex_data_req, - input logic ex_data_gnt, - input logic ex_data_we, - input logic [31:0] ex_data_addr, - input logic [31:0] ex_data_wdata, - - input logic lsu_misaligned, - input logic wb_bypass, - - input logic wb_valid, - input logic [ 5:0] wb_reg_addr, - - input logic wb_reg_we, - input logic [31:0] wb_reg_wdata, - - input logic wb_data_rvalid, - input logic [31:0] wb_data_rdata - - -); - - // DPI stuff - chandle dpi_simdata; - - // SV-only stuff - typedef struct { - logic [ 5:0] addr; - logic [31:0] value; - } reg_t; - - typedef struct { - logic [31:0] addr; - logic we; - logic [ 3:0] be; - logic [31:0] wdata; - logic [31:0] rdata; - } mem_acc_t; - - class instr_trace_t; - time simtime; - int cycles; - logic [31:0] pc; - logic [31:0] instr; - logic irq; - logic [ 4:0] irq_no; - logic wb_bypass; - logic fpu_first; - int next_wait; - reg_t regs_write[$]; - mem_acc_t mem_access[$]; - - function new (); - irq = 1'b0; - wb_bypass = 1'b1; - fpu_first = 1'b0; - next_wait = 0; - regs_write = {}; - mem_access = {}; - endfunction - endclass - - - mailbox rdata_stack = new (4); - integer rdata_writes = 0; - - integer cycles; - integer mismatch=0; - logic pipe_wait; - logic fpu_in_ex; - int fp_completed; - int fp_ended; - int instr_is_valid; - - logic [15:0] instr_compressed_id; - logic is_irq_if, is_irq_id; - logic [ 4:0] irq_no_id, irq_no_if; - logic apu_req_accepted; - logic apu_res_on_alu_port; - logic apu_res_on_lsu_port; - logic enable = 0; - logic [ 1:0] apu_lat; - - instr_trace_t instr_queue[$]; - - localparam SIMCHECKER_VERBOSE = 0; - - mailbox instr_ex = new (4); - mailbox instr_wb = new (4); - mailbox fpu_active = new (4); - mailbox fpu_ex = new (4); - mailbox fpu_wb = new (4); - mailbox fpu_done = new (4); - mailbox fpu_end = new (4); - mailbox instr_wait = new (4); - - mailbox fpu_wait = new (4); - - // simchecker initialization - initial - begin - - enable = 1'b1; - pipe_wait = 1'b0; - fpu_in_ex = 1'b0; - fp_completed = 0; - fp_ended = 0; - instr_is_valid = 0; - instr_queue = {}; - wait(rst_n == 1'b1); - wait(fetch_enable == 1'b1); - - dpi_simdata = riscv_checker_init(boot_addr, core_id, cluster_id, "riscyv2"); - - end - - // virtual ID/EX pipeline - initial - begin - - instr_trace_t trace; - mem_acc_t mem_acc; - reg_t reg_write; - - while(1) begin - instr_ex.get(trace); - - - // wait until we are going to the next stage - do begin - @(negedge clk); - - reg_write.addr = ex_reg_addr; - reg_write.value = ex_reg_wdata; - - if(trace.fpu_first == 1'b1) begin //If the fp operation has been completed, the instruction doesn't have to wait anymore - if(apu_valid) - trace.fpu_first = 1'b0; - end - - - if (ex_reg_we) begin - trace.regs_write.push_back(reg_write); - end - // look for data accesses and log them - if (ex_data_req && ex_data_gnt) begin - mem_acc.addr = ex_data_addr; - mem_acc.we = ex_data_we; - - - if (mem_acc.we) - mem_acc.wdata = ex_data_wdata; - else - mem_acc.wdata = 'x; - - trace.mem_access.push_back(mem_acc); - end - end while (((!ex_valid || lsu_misaligned) && (!wb_bypass)) || (wb_contention)); //wb_contention is normally low, so it will not stop the process. As soon as there is a contention, this - //condition is true and restart storing values without unlocking the following check process. - trace.wb_bypass = wb_bypass; - - instr_wb.put(trace); - end - - end - - // virtual EX/WB pipeline - initial - begin - - instr_trace_t trace, fpu_trace; - reg_t reg_write; - logic [31:0] tmp_discard; - logic [31:0] rdata_tmp; - - while(1) begin - instr_wb.get(trace); - - if (!trace.wb_bypass) begin - - // wait until we are going to the next stage - do begin - @(negedge clk); - #1; - - - // pop rdata from stack when there were pending writes - while(rdata_stack.num() > 0 && rdata_writes > 0) begin - rdata_writes--; - rdata_stack.get(tmp_discard); - end - - if(lsu_ready_wb && !apu_ready_wb) begin - reg_write.addr = wb_reg_addr; - reg_write.value = wb_reg_wdata; - if(wb_reg_we) begin - trace.regs_write.push_back(reg_write); - end - end - - end while ((!wb_valid) && (!lsu_ready_wb)); - - - reg_write.addr = wb_reg_addr; - reg_write.value = wb_reg_wdata; - - - - if (wb_reg_we && !apu_valid) begin - trace.regs_write.push_back(reg_write); - end - - // take care of rdata - foreach(trace.mem_access[i]) begin - if (trace.mem_access[i].we) begin - // for writes we don't need to wait for the rdata, so if it has - // not appeared yet, we count it and remove it later from out - // stack - if (rdata_stack.num() > 0) - rdata_stack.get(tmp_discard); - else - rdata_writes++; - - end else begin - if (rdata_stack.num() == 0) - $warning("rdata stack is empty, but we are waiting for a read"); - - if (rdata_writes > 0) - $warning("rdata_writes is > 0, but we are waiting for a read"); - - // indirect addressing workaround for ncsim - rdata_tmp = trace.mem_access[i].rdata; - rdata_stack.get(rdata_tmp); - end - end - end - - - if(trace.fpu_first == 1'b1) begin //Check whether one instruction has to wait for the fp operation to be completed, then accumulate all the incoming instructions - pipe_wait = 1'b1; - #1; - end - - if(pipe_wait) begin - instr_wait.put(trace); - - end else begin - - foreach(trace.mem_access[i]) begin - if (trace.mem_access[i].we) begin - //TEMPORARY SOLUTION WITH BYPASS FOR UNINITIALIZED REGISTERS - if(trace.mem_access[i].wdata === 'X) - $display("Uninitialized register was met, skip this check"); - else begin - riscv_checker_mem_access(dpi_simdata, trace.mem_access[i].we, trace.mem_access[i].addr, trace.mem_access[i].wdata); - end - end else begin - riscv_checker_mem_access(dpi_simdata, trace.mem_access[i].we, trace.mem_access[i].addr, trace.mem_access[i].rdata); - end - end - - foreach(trace.regs_write[i]) begin - riscv_checker_reg_access(dpi_simdata, trace.regs_write[i].addr, trace.regs_write[i].value); - end - - riscv_checker_irq(dpi_simdata, trace.irq, trace.irq_no); - - if (riscv_checker_step(dpi_simdata, trace.simtime, trace.cycles, trace.pc, trace.instr)) begin - $display("SIMCHECKER: CORE pipeline: Cycle %d at %g ps 0x%x: Cluster %d, Core %d: Mismatch between simulator and RTL detected", trace.cycles, trace.simtime, trace.pc, cluster_id, core_id); - mismatch ++; - if(mismatch > 10) - $stop(); - end - end - end - end - - - - - - assign apu_req_accepted = apu_req & apu_gnt; - assign apu_res_on_alu_port = apu_singlecycle | apu_multicycle; - assign apu_res_on_lsu_port = (!apu_singlecycle & !apu_multicycle); - - initial - begin - - instr_trace_t trace; - while(1) begin - fpu_active.get(trace); - - if(apu_en_ex) begin //This is 1 if we already have a fp instruction in execution - if(~apu_active) begin //APU is active if there is an unreturned request. If it's low but apu_en_ex is high, we have to wait for the - apu_lat = apu_latency; //previous instruction to be done. This depends on the latency of that instruction - while(apu_lat > 1) begin - @(negedge clk); - apu_lat --; - end - - end else begin - do begin - @(negedge clk); - end while(apu_active); //APU is active when there is an unreturned request. FPU is still not available for a new operation. - end - end - - fpu_ex.put(trace); - end - - end - - - initial //FPU pipeline: "ID/EX stage" - begin - - - instr_trace_t trace; - reg_t reg_write;///////////////////////////////////////////////// - while(1) begin - fpu_ex.get(trace); - - if(!apu_req_accepted) begin - do begin - @(negedge clk); - end while(!apu_req_accepted); - end - - if((id_valid && is_decoding) || (pipe_flush && is_decoding) || (is_decoding && is_illegal) || (id_valid && is_mret)) begin - if(apu_en_id) - trace.next_wait = 0; - else begin - - fpu_in_ex = 1'b1; - trace.next_wait = 1; - end - end else trace.next_wait = 0; - - fpu_wb.put(trace); - end - - end - - initial //FPU pipeline: "EX/WB stage" - begin - - - instr_trace_t trace; - reg_t reg_write; - - while(1) begin - fpu_wb.get(trace); - - while(!apu_valid) begin - @(negedge clk); - end - - if(apu_res_on_lsu_port) begin - reg_write.addr = wb_reg_addr; - reg_write.value = wb_reg_wdata; - if(wb_reg_we) begin - - trace.regs_write.push_back(reg_write); - end - end else begin - if(apu_res_on_alu_port) begin - reg_write.addr = ex_reg_addr; - reg_write.value = ex_reg_wdata; - if(ex_reg_we) - trace.regs_write.push_back(reg_write); - end - end - - fpu_done.put(trace); - end - - end - - initial //FPU pipeline: "WB/CHECK STAGE". Call the ISS to check the results - begin - - - instr_trace_t trace; - while(1) begin - fpu_done.get(trace); - - - foreach(trace.regs_write[i]) begin - - riscv_checker_reg_access(dpi_simdata, trace.regs_write[i].addr, trace.regs_write[i].value); - end - if(riscv_checker_step(dpi_simdata, trace.simtime, trace.cycles, trace.pc, trace.instr)) begin - $display("SIMCHECKER: FPU pipeline: Cycle %d at %g ps 0x%x: Cluster %d, Core %d: Mismatch between simulator and RTL detected", trace.cycles, trace.simtime, trace.pc, cluster_id, core_id); - mismatch ++; - if(mismatch > 10) - $stop(); - end - #1; - - - if(trace.next_wait == 1) begin - fpu_end.put(1); - end - fpu_in_ex = 1'b0; - end - - end - - - initial - begin - - instr_trace_t trace; - - while(1) begin - @(negedge clk); - instr_is_valid = instr_wait.try_get(trace); - if(instr_is_valid == 1) begin - - instr_queue.push_back(trace); - end - - fp_completed = fpu_end.try_get(fp_ended); - if(fp_completed == 1) begin - foreach(instr_queue[i]) begin - for (int j = 0; j < instr_queue[i].mem_access.size(); j++) begin - /* code */ - if(instr_queue[i].mem_access[j].we) begin - if(instr_queue[i].mem_access[j].wdata === 'X) - $display("Uninitialized register was met, skip this check"); - else begin - riscv_checker_mem_access(dpi_simdata, instr_queue[i].mem_access[j].we, instr_queue[i].mem_access[j].addr, instr_queue[i].mem_access[j].wdata); - end - end else begin - riscv_checker_mem_access(dpi_simdata, instr_queue[i].mem_access[j].we, instr_queue[i].mem_access[j].addr, instr_queue[i].mem_access[j].rdata); - end - end - - for (int j = 0; j < instr_queue[i].regs_write.size(); j++) begin - /* code */ - riscv_checker_reg_access(dpi_simdata, instr_queue[i].regs_write[j].addr, instr_queue[i].regs_write[j].value); - end - - riscv_checker_irq(dpi_simdata, instr_queue[i].irq, instr_queue[i].irq_no); - - if(riscv_checker_step(dpi_simdata, instr_queue[i].simtime, instr_queue[i].cycles, instr_queue[i].pc, instr_queue[i].instr)) begin - $display("SIMCHECKER: In INSTR QUEUE: CORE pipeline: Cycle %d at %g ps 0x%x: Cluster %d, Core %d: Mismatch between simulator and RTL detected", cycles, instr_queue[i].simtime, instr_queue[i].pc, cluster_id, core_id); - mismatch ++; - if(mismatch > 10) - $stop(); - end - end - - instr_queue = {}; //Empty the queue, so that is available to accumulate new instructions - pipe_wait = 1'b0; //Pipe doesn't have to wait anymore - fp_completed = 0; - end - end - end - - - // cycle counter - always_ff @(posedge clk, negedge rst_n) - begin - if (rst_n == 1'b0) - cycles = 0; - else - cycles = cycles + 1; - end - - // create rdata stack - initial - begin - - while(1) begin - @(negedge clk); - - if (wb_data_rvalid) begin - rdata_stack.put(wb_data_rdata); - end - end - - end - - always_ff @(enable, posedge clk) - begin - if (pc_set) begin - is_irq_if <= is_interrupt; - irq_no_if <= irq_no; - end else if (if_valid) begin - is_irq_if <= 1'b0; - end - end - - always_ff @(enable, posedge clk) - begin - if (if_valid) begin - instr_compressed_id <= instr_compressed; - is_irq_id <= is_irq_if; - irq_no_id <= irq_no_if; - end else begin - is_irq_id <= is_irq_if; - irq_no_id <= irq_no_if; - end - end - - - - // log execution - initial - begin - - instr_trace_t trace; - - while(1) begin - @(negedge clk); - - // - special case for WFI because we don't wait for unstalling there - // - special case for illegal instructions, since they will not go through - // the pipe - - if ((id_valid && is_decoding) || (pipe_flush && is_decoding) || (is_decoding && is_illegal) || (id_valid && is_mret)) - begin - trace = new (); - - trace.simtime = $time; - trace.cycles = cycles; - trace.pc = pc; - - if (is_compressed) - trace.instr = {instr_compressed_id, instr_compressed_id}; - else - trace.instr = instr; - - - if(is_irq_id) begin - trace.irq = 1'b1; - trace.irq_no = irq_no_id; - end else begin - if(!int_enable) begin - trace.irq = irq_i; - trace.irq_no = irq_no; - end - end - if(apu_en_id) begin - fpu_active.put(trace); - end - else begin - #1; - if(apu_req_accepted && apu_en_ex && ~apu_valid && fpu_in_ex) begin - trace.fpu_first = 1'b1; //This means the instruction will go out of the pipeline - end - instr_ex.put(trace); - end - end - end - end - -endmodule -`endif diff --git a/cv32e40x/tb/core/tb_riscv/tb_riscv_core.sv b/cv32e40x/tb/core/tb_riscv/tb_riscv_core.sv deleted file mode 100644 index 620800a771..0000000000 --- a/cv32e40x/tb/core/tb_riscv/tb_riscv_core.sv +++ /dev/null @@ -1,386 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -///////////////////////////////////////////////////////////////////////////////////////////////// -// // -// Author: Francesco Minervini - minervif@student.ethz.ch // -// // -// Additional contributions by: // -// // -// Design Name: Top level module including riscv core and perturbation // -// module // -// Project Name: TB RISC-V // -// Language: SystemVerilog // -// // -// Description: This module is instantiated in the core_region.sv code // -// when the parameter TB_RISCV is set to 1. // -// This module instantiates one between zero_riscy or riscy // -// core depending on the value of USE_ZERO_RISCY, then // -// it also instantiates and connects the core to the // -// perturbation module. // -// // -///////////////////////////////////////////////////////////////////////////////////////////////// - -module tb_riscv_core -#( - parameter N_EXT_PERF_COUNTERS = 0, - parameter INSTR_RDATA_WIDTH = 32, - parameter PULP_SECURE = 0, - parameter N_PMP_ENTRIES = 16, - parameter PULP_CLUSTER = 1, - parameter FPU = 0, - parameter SHARED_FP = 0, - parameter SHARED_DSP_MULT = 0, - parameter SHARED_INT_DIV = 0, - parameter SHARED_FP_DIVSQRT = 0, - parameter WAPUTYPE = 0, - parameter APU_NARGS_CPU = 3, - parameter APU_WOP_CPU = 6, - parameter APU_NDSFLAGS_CPU = 15, - parameter APU_NUSFLAGS_CPU = 5, - parameter SIMCHECKER = 0 -) -( - // Clock and Reset - input logic clk_i, - input logic rst_ni, - - input logic clock_en_i, // enable clock, otherwise it is gated - input logic test_en_i, // enable all clock gates for testing - - input logic fregfile_disable_i, // disable the fp regfile, using int regfile instead - - // Core ID, Cluster ID and boot address are considered more or less static - input logic [31:0] boot_addr_i, - input logic [ 3:0] core_id_i, - input logic [ 5:0] cluster_id_i, - - // Instruction memory interface - output logic instr_req_o, - input logic instr_gnt_i, - input logic instr_rvalid_i, - output logic [31:0] instr_addr_o, - input logic [INSTR_RDATA_WIDTH-1:0] instr_rdata_i, - - // Data memory interface - output logic data_req_o, - input logic data_gnt_i, - input logic data_rvalid_i, - output logic data_we_o, - output logic [3:0] data_be_o, - output logic [31:0] data_addr_o, - output logic [31:0] data_wdata_o, - input logic [31:0] data_rdata_i, - // apu-interconnect - // handshake signals - output logic apu_master_req_o, - output logic apu_master_ready_o, - input logic apu_master_gnt_i, - // request channel - output logic [31:0] apu_master_operands_o [APU_NARGS_CPU-1:0], - output logic [APU_WOP_CPU-1:0] apu_master_op_o, - output logic [WAPUTYPE-1:0] apu_master_type_o, - output logic [APU_NDSFLAGS_CPU-1:0] apu_master_flags_o, - // response channel - input logic apu_master_valid_i, - input logic [31:0] apu_master_result_i, - input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i, - - // Interrupt inputs - input logic irq_i, // level sensitive IR lines - input logic [4:0] irq_id_i, - output logic irq_ack_o, - output logic [4:0] irq_id_o, - input logic irq_sec_i, - - output logic sec_lvl_o, - - // Debug Interface - input logic debug_req_i, - output logic debug_gnt_o, - output logic debug_rvalid_o, - input logic [14:0] debug_addr_i, - input logic debug_we_i, - input logic [31:0] debug_wdata_i, - output logic [31:0] debug_rdata_o, - output logic debug_halted_o, - input logic debug_halt_i, - input logic debug_resume_i, - - // CPU Control Signals - input logic fetch_enable_i, - output logic core_busy_o, - - input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_counters_i -); - -localparam PERT_REGS = 15; - -////////////////////////////////////////////////////////////// -//Internal signals to connect core and perturbation module -///////////////////////////////////////////////////////////// - -// Additional instruction signals - -logic instr_req_int; -logic instr_grant_int; -logic instr_rvalid_int; -logic [31:0] instr_addr_int; -logic [INSTR_RDATA_WIDTH-1:0] instr_rdata_int; - -// Additional data signals -logic data_req_int; -logic data_grant_int; -logic data_rvalid_int; -logic data_we_int; -logic [3:0] data_be_int; -logic [31:0] data_addr_int; -logic [31:0] data_wdata_int; -logic [31:0] data_rdata_int; - -// Additional signals for pertubation/debug registers -logic debug_req_int; -logic debug_grant_int; -logic debug_rvalid_int; -logic debug_we_int; -logic [14:0] debug_addr_int; -logic [31:0] debug_wdata_int; -logic [31:0] debug_rdata_int; - -// Additional interrupt signals -logic irq_int; -logic irq_ack_int; -logic [4:0] irq_id_int; -logic [4:0] irq_core_resp_id_int; - - - - riscv_core - #( - .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS ), - .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), - .PULP_SECURE ( PULP_SECURE ), - .N_PMP_ENTRIES ( N_PMP_ENTRIES ), - .FPU ( FPU ), - .SHARED_FP ( SHARED_FP ), - .SHARED_DSP_MULT ( SHARED_DSP_MULT ), - .SHARED_INT_DIV ( SHARED_INT_DIV ), - .SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ), - .WAPUTYPE ( WAPUTYPE ), - .APU_NARGS_CPU ( APU_NARGS_CPU ), - .APU_WOP_CPU ( APU_WOP_CPU ), - .APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ), - .APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU ) - ) - RISCV_CORE - ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .clock_en_i ( clock_en_i ), - .test_en_i ( test_en_i ), - - .fregfile_disable_i ( fregfile_disable_i ), - - .boot_addr_i ( boot_addr_i ), - .core_id_i ( core_id_i ), - .cluster_id_i ( cluster_id_i ), - - .instr_req_o ( instr_req_int ), - .instr_gnt_i ( instr_grant_int ), - .instr_rvalid_i ( instr_rvalid_int ), - .instr_addr_o ( instr_addr_int ), - .instr_rdata_i ( instr_rdata_int ), - - .data_req_o ( data_req_int ), - .data_gnt_i ( data_grant_int ), - .data_rvalid_i ( data_rvalid_int ), - .data_we_o ( data_we_int ), - .data_be_o ( data_be_int ), - .data_addr_o ( data_addr_int ), - .data_wdata_o ( data_wdata_int ), - .data_rdata_i ( data_rdata_int ), - - .apu_master_req_o ( apu_master_req_o ), - .apu_master_ready_o ( apu_master_ready_o ), - .apu_master_gnt_i ( apu_master_gnt_i ), - .apu_master_operands_o ( apu_master_operands_o ), - .apu_master_op_o ( apu_master_op_o ), - .apu_master_type_o ( apu_master_type_o ), - .apu_master_flags_o ( apu_master_flags_o ), - - .apu_master_valid_i ( apu_master_valid_i ), - .apu_master_result_i ( apu_master_result_i ), - .apu_master_flags_i ( apu_master_flags_i ), - - .irq_i ( irq_int ), - .irq_id_i ( irq_id_int ), - .irq_ack_o ( irq_ack_int ), - .irq_id_o ( irq_core_resp_id_int ), - .irq_sec_i ( irq_sec_i ), - - .sec_lvl_o ( sec_lvl_o ), - - .debug_req_i ( debug_req_int ), - .debug_gnt_o ( debug_grant_int ), - .debug_rvalid_o ( debug_rvalid_int ), - .debug_addr_i ( debug_addr_int ), - .debug_we_i ( debug_we_int ), - .debug_wdata_i ( debug_wdata_int ), - .debug_rdata_o ( debug_rdata_int ), - .debug_halted_o ( debug_halted_o ), - .debug_halt_i ( debug_halt_i ), - .debug_resume_i ( debug_resume_i ), - - .fetch_enable_i ( fetch_enable_i ), - .core_busy_o ( core_busy_o ), - - .ext_perf_counters_i ( ext_perf_counters_i ) - ); - - // Perturbation module instance - riscv_perturbation - #( - .PERT_REGS ( PERT_REGS ), - .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ) - ) - riscv_perturbation_i - ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .pert_instr_req_i ( instr_req_int ), - .pert_instr_req_o ( instr_req_o ), - .pert_instr_grant_i ( instr_gnt_i ), - .pert_instr_grant_o ( instr_grant_int ), - .pert_instr_rvalid_i ( instr_rvalid_i ), - .pert_instr_rvalid_o ( instr_rvalid_int ), - .pert_instr_addr_i ( instr_addr_int ), - .pert_instr_addr_o ( instr_addr_o ), - .pert_instr_rdata_i ( instr_rdata_i ), - .pert_instr_rdata_o ( instr_rdata_int ), - - .pert_data_req_i ( data_req_int ), - .pert_data_req_o ( data_req_o ), - .pert_data_grant_i ( data_gnt_i ), - .pert_data_grant_o ( data_grant_int ), - .pert_data_rvalid_i ( data_rvalid_i ), - .pert_data_rvalid_o ( data_rvalid_int ), - .pert_data_we_i ( data_we_int ), - .pert_data_we_o ( data_we_o ), - .pert_data_be_i ( data_be_int ), - .pert_data_be_o ( data_be_o ), - .pert_data_addr_i ( data_addr_int ), - .pert_data_addr_o ( data_addr_o ), - .pert_data_wdata_i ( data_wdata_int ), - .pert_data_wdata_o ( data_wdata_o ), - .pert_data_rdata_i ( data_rdata_i ), - .pert_data_rdata_o ( data_rdata_int ), - - .pert_debug_req_i ( debug_req_i ), - .pert_debug_req_o ( debug_req_int ), - .pert_debug_gnt_i ( debug_grant_int ), - .pert_debug_gnt_o ( debug_gnt_o ), - .pert_debug_rvalid_i ( debug_rvalid_int ), - .pert_debug_rvalid_o ( debug_rvalid_o ), - .pert_debug_we_i ( debug_we_i ), - .pert_debug_we_o ( debug_we_int ), - .pert_debug_addr_i ( debug_addr_i ), - .pert_debug_addr_o ( debug_addr_int ), - .pert_debug_wdata_i ( debug_wdata_i ), - .pert_debug_wdata_o ( debug_wdata_int ), - .pert_debug_rdata_i ( debug_rdata_int ), - .pert_debug_rdata_o ( debug_rdata_o ), - - .pert_irq_i ( irq_i ), - .pert_irq_o ( irq_int ), - .pert_irq_id_i ( irq_id_i ), - .pert_irq_id_o ( irq_id_int ), - .pert_irq_ack_i ( irq_ack_int ), - .pert_irq_ack_o ( irq_ack_o ), - .pert_irq_core_resp_id_i ( irq_core_resp_id_int ), - .pert_irq_core_resp_id_o ( irq_id_o ), - .pert_pc_id_i ( RISCV_CORE.pc_id ) - ); - - - `ifndef VERILATOR - generate - if(SIMCHECKER) begin: ri5cy_simchecker - riscv_simchecker riscv_simchecker_i - ( - .clk ( RISCV_CORE.clk_i ), - .rst_n ( RISCV_CORE.rst_ni ), - - .fetch_enable ( RISCV_CORE.fetch_enable_i ), - .boot_addr ( RISCV_CORE.boot_addr_i ), - .core_id ( RISCV_CORE.core_id_i ), - .cluster_id ( RISCV_CORE.cluster_id_i ), - - .instr_compressed ( RISCV_CORE.if_stage_i.fetch_rdata[15:0] ), - .if_valid ( RISCV_CORE.if_stage_i.if_valid ), - .pc_set ( RISCV_CORE.pc_set ), - - - .pc ( RISCV_CORE.id_stage_i.pc_id_i ), - .instr ( RISCV_CORE.id_stage_i.instr ), - .is_compressed ( RISCV_CORE.is_compressed_id ), - .id_valid ( RISCV_CORE.id_stage_i.id_valid_o ), - .is_decoding ( RISCV_CORE.id_stage_i.is_decoding_o ), - .is_illegal ( RISCV_CORE.id_stage_i.illegal_insn_dec ), - .is_interrupt ( RISCV_CORE.is_interrupt ), - .irq_no ( RISCV_CORE.irq_id_i ), - .pipe_flush ( RISCV_CORE.id_stage_i.controller_i.pipe_flush_i ), - .irq_i ( RISCV_CORE.irq_i ), - .is_mret ( RISCV_CORE.id_stage_i.controller_i.mret_insn_i ), - - .int_enable ( RISCV_CORE.id_stage_i.m_irq_enable_i ), - - .lsu_ready_wb ( RISCV_CORE.lsu_ready_wb ), - .apu_ready_wb ( RISCV_CORE.apu_ready_wb ), - .wb_contention ( RISCV_CORE.ex_stage_i.wb_contention ), - - .apu_en_id ( RISCV_CORE.id_stage_i.apu_en ), - .apu_req ( RISCV_CORE.ex_stage_i.apu_req ), - .apu_gnt ( RISCV_CORE.ex_stage_i.apu_gnt ), - .apu_valid ( RISCV_CORE.ex_stage_i.apu_valid ), - .apu_singlecycle ( RISCV_CORE.ex_stage_i.apu_singlecycle ), - .apu_multicycle ( RISCV_CORE.ex_stage_i.apu_multicycle ), - .apu_latency ( RISCV_CORE.ex_stage_i.apu_lat_i ), - .apu_active ( RISCV_CORE.ex_stage_i.apu_active ), - .apu_en_ex ( RISCV_CORE.ex_stage_i.apu_en_i ), - - .ex_valid ( RISCV_CORE.ex_valid ), - .ex_reg_addr ( RISCV_CORE.id_stage_i.register_file_i.waddr_b_i ), - - .ex_reg_we ( RISCV_CORE.id_stage_i.register_file_i.we_b_i ), - .ex_reg_wdata ( RISCV_CORE.id_stage_i.register_file_i.wdata_b_i ), - - .ex_data_req ( RISCV_CORE.data_req_o ), - .ex_data_gnt ( RISCV_CORE.data_gnt_i ), - .ex_data_we ( RISCV_CORE.data_we_o ), - .ex_data_addr ( RISCV_CORE.data_addr_o ), - .ex_data_wdata ( RISCV_CORE.data_wdata_o ), - - .lsu_misaligned ( RISCV_CORE.data_misaligned ), - .wb_bypass ( RISCV_CORE.ex_stage_i.branch_in_ex_i ), - - .wb_valid ( RISCV_CORE.wb_valid ), - .wb_reg_addr ( RISCV_CORE.id_stage_i.register_file_i.waddr_a_i ), - .wb_reg_we ( RISCV_CORE.id_stage_i.register_file_i.we_a_i ), - .wb_reg_wdata ( RISCV_CORE.id_stage_i.register_file_i.wdata_a_i ), - .wb_data_rvalid ( RISCV_CORE.data_rvalid_i ), - .wb_data_rdata ( RISCV_CORE.data_rdata_i ) - ); - end - endgenerate - `endif - -endmodule // tb_riscv_core diff --git a/cv32e40x/tb/core/tb_top.sv b/cv32e40x/tb/core/tb_top.sv deleted file mode 100644 index d5cd1dd567..0000000000 --- a/cv32e40x/tb/core/tb_top.sv +++ /dev/null @@ -1,165 +0,0 @@ -// Copyright 2017 Embecosm Limited -// Copyright 2018 Robert Balas -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -// Top level wrapper for a RI5CY testbench -// Contributor: Robert Balas -// Jeremy Bennett - -`define TB_CORE - -module tb_top - #(parameter INSTR_RDATA_WIDTH = 32, - parameter RAM_ADDR_WIDTH = 22, - parameter BOOT_ADDR = 'h80); - - // comment to record execution trace - //`define TRACE_EXECUTION - - const time CLK_PHASE_HI = 5ns; - const time CLK_PHASE_LO = 5ns; - const time CLK_PERIOD = CLK_PHASE_HI + CLK_PHASE_LO; - const time STIM_APPLICATION_DEL = CLK_PERIOD * 0.1; - const time RESP_ACQUISITION_DEL = CLK_PERIOD * 0.9; - const time RESET_DEL = STIM_APPLICATION_DEL; - const int RESET_WAIT_CYCLES = 4; - - - // clock and reset for tb - logic core_clk; - logic iss_clk; - logic core_rst_n; - - // cycle counter - int unsigned cycle_cnt_q; - - // testbench result - logic tests_passed; - logic tests_failed; - logic exit_valid; - logic [31:0] exit_value; - - // signals for ri5cy - logic fetch_enable; - - // make the core start fetching instruction immediately - assign fetch_enable = '1; - - // allow vcd dump - initial begin - if ($test$plusargs("vcd")) begin - $dumpfile("riscy_tb.vcd"); - $dumpvars(0, tb_top); - end - end - - // we either load the provided firmware or execute a small test program that - // doesn't do more than an infinite loop with some I/O - initial begin: load_prog - automatic string firmware; - automatic int prog_size = 6; - - if($value$plusargs("firmware=%s", firmware)) begin - if($test$plusargs("verbose")) - $display("[TESTBENCH] @ t=%0t: loading firmware %0s", - $time, firmware); - $readmemh(firmware, cv32e40x_tb_wrapper_i.ram_i.dp_ram_i.mem); - end else begin - $display("No firmware specified"); - $finish; - end - end - - initial begin: clock_gen - forever begin - #CLK_PHASE_HI core_clk = 1'b0; - #CLK_PHASE_LO core_clk = 1'b1; - end - end: clock_gen - - - // timing format, reset generation and parameter check - initial begin - $timeformat(-9, 0, "ns", 9); - core_rst_n = 1'b0; - - // wait a few cycles - repeat (RESET_WAIT_CYCLES) begin - @(posedge core_clk); //TODO: was posedge, see below - end - - // start running - #RESET_DEL core_rst_n = 1'b1; - - repeat (3) @(negedge core_clk); - core_rst_n = 1'b1; - - if($test$plusargs("verbose")) begin - $display("reset deasserted", $time); - end - - if ( !( (INSTR_RDATA_WIDTH == 128) || (INSTR_RDATA_WIDTH == 32) ) ) begin - $fatal(2, "invalid INSTR_RDATA_WIDTH, choose 32 or 128"); - end - end - - // abort after n cycles, if we want to - always_ff @(posedge core_clk, negedge core_rst_n) begin - automatic int maxcycles; - if($value$plusargs("maxcycles=%d", maxcycles)) begin - if (~core_rst_n) begin - cycle_cnt_q <= 0; - end else begin - cycle_cnt_q <= cycle_cnt_q + 1; - if (cycle_cnt_q >= maxcycles) begin - $fatal(2, "Simulation aborted due to maximum cycle limit"); - end - end - end - end - - // check if we succeded - always_ff @(posedge core_clk, negedge core_rst_n) begin - if (tests_passed) begin - $display("ALL TESTS PASSED"); - $finish; - end - if (tests_failed) begin - $display("TEST(S) FAILED!"); - $finish; - end - if (exit_valid) begin - if (exit_value == 0) - $display("%m @ %0t: EXIT SUCCESS", $time); - else - $display("%m @ %0t: EXIT FAILURE: %d", exit_value, $time); - $finish; - end - end - - // wrapper for CV32E40X, the memory system and stdout peripheral - cv32e40x_tb_wrapper - #( - .INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH), - .RAM_ADDR_WIDTH (RAM_ADDR_WIDTH), - .BOOT_ADDR (BOOT_ADDR) - ) - cv32e40x_tb_wrapper_i - ( - .clk_i ( core_clk ), - .rst_ni ( core_rst_n ), - .fetch_enable_i ( fetch_enable ), - .tests_passed_o ( tests_passed ), - .tests_failed_o ( tests_failed ), - .exit_valid_o ( exit_valid ), - .exit_value_o ( exit_value ) - ); - -endmodule // tb_top diff --git a/cv32e40x/tb/core/tb_top_verilator.cpp b/cv32e40x/tb/core/tb_top_verilator.cpp deleted file mode 100644 index c0cb0e491c..0000000000 --- a/cv32e40x/tb/core/tb_top_verilator.cpp +++ /dev/null @@ -1,111 +0,0 @@ -#include "svdpi.h" -#include "Vtb_top_verilator__Dpi.h" -#include "Vtb_top_verilator.h" -#include "verilated_vcd_c.h" -#include "verilated.h" - -#include -#include -#include -#include -#include -#include -#include - -void dump_memory(); -double sc_time_stamp(); - -static vluint64_t t = 0; -Vtb_top_verilator *top; - -int main(int argc, char **argv, char **env) -{ - -#ifdef MCY - int mutidx = 0; - for (int i = 1; i < argc; i++) - { - if (!strcmp(argv[i], "--mutidx") && i+1 < argc) - { - i++; - std::string s(argv[i]); - mutidx = std::stoi(s); - } - } -#endif - - Verilated::commandArgs(argc, argv); - Verilated::traceEverOn(true); - top = new Vtb_top_verilator(); - - svSetScope(svGetScopeFromName( - "TOP.tb_top_verilator.cv32e40x_tb_wrapper_i.ram_i.dp_ram_i")); - Verilated::scopesDump(); - -#ifdef VCD_TRACE - VerilatedVcdC *tfp = new VerilatedVcdC; - top->trace(tfp, 99); - tfp->open("verilator_tb.vcd"); -#endif - top->fetch_enable_i = 1; - top->clk_i = 0; - top->rst_ni = 0; - - top->eval(); - dump_memory(); - -#ifdef MCY - svSetScope(svGetScopeFromName( - "TOP.tb_top_verilator.cv32e40x_tb_wrapper_i.riscv_core_i.ex_stage_i.alu_i.int_div.div_i")); - svLogicVecVal idx = {0}; - idx.aval = mutidx; - set_mutidx(&idx); - std::cout << "[tb_top_verilator] mutsel = " << idx.aval << "\n"; -#endif - - while (!Verilated::gotFinish()) { - if (t > 40) - top->rst_ni = 1; - top->clk_i = !top->clk_i; - top->eval(); -#ifdef VCD_TRACE - tfp->dump(t); -#endif - t += 5; - } -#ifdef VCD_TRACE - tfp->close(); -#endif - delete top; - exit(0); -} - -double sc_time_stamp() -{ - return t; -} - -void dump_memory() -{ - errno = 0; - std::ofstream mem_file; - svLogicVecVal addr = {0}; - - mem_file.exceptions(std::ofstream::failbit | std::ofstream::badbit); - try { - mem_file.open("memory_dump.bin"); - for (size_t i = 0; i < 1048576; i++) { - addr.aval = i; - uint32_t val = read_byte(&addr); - //uint32_t val = read_byte(&addr.aval); // mike@openhwgroup.org: if the above line fails to compile on your system, try this line - mem_file << std::setfill('0') << std::setw(2) << std::hex << val - << std::endl; - } - mem_file.close(); - - std::cout << "[tb_top_verilator] finished dumping memory" << std::endl; - - } catch (std::ofstream::failure e) { - std::cerr << "[tb_top_verilator] exception opening/reading/closing file memory_dump.bin\n"; - } -} diff --git a/cv32e40x/tb/core/tb_top_verilator.sv b/cv32e40x/tb/core/tb_top_verilator.sv deleted file mode 100644 index e63b71745c..0000000000 --- a/cv32e40x/tb/core/tb_top_verilator.sv +++ /dev/null @@ -1,104 +0,0 @@ -// Copyright 2018 Robert Balas -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -// Top level wrapper for a verilator RI5CY testbench -// Contributor: Robert Balas - -module tb_top_verilator - #(parameter INSTR_RDATA_WIDTH = 128, - parameter RAM_ADDR_WIDTH = 22, - parameter BOOT_ADDR = 'h80) - (input logic clk_i, - input logic rst_ni, - input logic fetch_enable_i, - output logic tests_passed_o, - output logic tests_failed_o); - - // cycle counter - int unsigned cycle_cnt_q; - - // testbench result - logic exit_valid; - logic [31:0] exit_value; - - - // Load the test-program (must be pre-compiled beforehand). - initial begin: load_prog - automatic logic [1023:0] firmware; - automatic int prog_size = 6; - - if($value$plusargs("firmware=%s", firmware)) begin - if($test$plusargs("verbose")) - $display("[TESTBENCH] %t: loading firmware %0s ...", - $time, firmware); - $readmemh(firmware, cv32e40x_tb_wrapper_i.ram_i.dp_ram_i.mem); - - end else begin - $display("No firmware specified"); - $finish; - end - end - - // abort after n cycles, if we want to - always_ff @(posedge clk_i, negedge rst_ni) begin - automatic int maxcycles; - if($value$plusargs("maxcycles=%d", maxcycles)) begin - if (~rst_ni) begin - cycle_cnt_q <= 0; - end else begin - cycle_cnt_q <= cycle_cnt_q + 1; - if (cycle_cnt_q >= maxcycles) begin - // we $finish instead of $fatal because riscv-compliance - // interprets the return error code as total failure, which - // we don't want - $finish("Simulation aborted due to maximum cycle limit"); - end - end - end - end - - // check if we succeded - always_ff @(posedge clk_i, negedge rst_ni) begin - if (tests_passed_o) begin - $display("%m @ %0t: ALL TESTS PASSED", $time); - $finish; - end - if (tests_failed_o) begin - $display("%m @ %0t: TEST(S) FAILED!", $time); - $finish; - end - if (exit_valid) begin - if (exit_value == 0) - $display("%m @ %0t: EXIT SUCCESS", $time); - else - $display("%m @ %0t: EXIT FAILURE: %d", exit_value, $time); - $finish; - end - end - - // wrapper for cv32e40x, the memory system and stdout peripheral - cv32e40x_tb_wrapper - #(.INSTR_RDATA_WIDTH (INSTR_RDATA_WIDTH), - .RAM_ADDR_WIDTH (RAM_ADDR_WIDTH), - .BOOT_ADDR (BOOT_ADDR), - .DM_HALTADDRESS (32'h1A11_0800), - .HART_ID (32'h0000_0000), - .NUM_MHPMCOUNTERS (1) - ) - cv32e40x_tb_wrapper_i - (.clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .fetch_enable_i ( fetch_enable_i ), - .tests_passed_o ( tests_passed_o ), - .tests_failed_o ( tests_failed_o ), - .exit_valid_o ( exit_valid ), - .exit_value_o ( exit_value )); - -endmodule // tb_top_verilator diff --git a/cv32e40x/tb/ldgen/ldgen_tb.sv b/cv32e40x/tb/ldgen/ldgen_tb.sv deleted file mode 100644 index 775e9b3c2a..0000000000 --- a/cv32e40x/tb/ldgen/ldgen_tb.sv +++ /dev/null @@ -1,32 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -`include "cv32e40x_pkg.sv" - -import cv32e40x_pkg::pma_region_t; - -`include "uvmt_cv32e40x_constants.sv" -`include "pma_adapted_mem_region_gen.sv" -`include "cv32e40x_ldgen.sv" - -module ldgen_tb; - - initial begin : ldgen_start - cv32e40x_ldgen_c linker_generator; - linker_generator = new(); - linker_generator.gen_pma_linker_scripts(); - end - -endmodule : ldgen_tb diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x.flist b/cv32e40x/tb/uvmt/uvmt_cv32e40x.flist deleted file mode 100644 index b67588ee31..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x.flist +++ /dev/null @@ -1,69 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -// Libraries --f ${DV_UVML_HRTBT_PATH}/uvml_hrtbt_pkg.flist --f ${DV_UVML_TRN_PATH}/uvml_trn_pkg.flist --f ${DV_UVML_LOGS_PATH}/uvml_logs_pkg.flist --f ${DV_UVML_SB_PATH}/uvml_sb_pkg.flist --f ${DV_UVML_MEM_PATH}/uvml_mem_pkg.flist --f $(DV_SVLIB_PATH)/svlib_pkg.flist - -// Agents --f ${DV_UVMA_CORE_CNTRL_PATH}/uvma_core_cntrl_pkg.flist --f ${DV_UVMA_OBI_MEMORY_PATH}/src/uvma_obi_memory_pkg.flist --f ${DV_UVMA_RVFI_PATH}/uvma_rvfi_pkg.flist --f ${DV_UVMA_RVVI_PATH}/uvma_rvvi_pkg.flist --f ${DV_UVMA_ISACOV_PATH}/uvma_isacov_pkg.flist --f ${DV_UVMA_PMA_PATH}/src/uvma_pma_pkg.flist --f ${DV_UVMA_CLKNRST_PATH}/uvma_clknrst_pkg.flist --f ${DV_UVMA_INTERRUPT_PATH}/uvma_interrupt_pkg.flist --f ${DV_UVMA_DEBUG_PATH}/uvma_debug_pkg.flist --f ${DV_UVMA_RVVI_OVPSIM_PATH}/uvma_rvvi_ovpsim_pkg.flist --f ${DV_UVMA_FENCEI_PATH}/uvma_fencei_pkg.flist - -// Environments --f ${DV_UVME_PATH}/uvme_cv32e40x_pkg.flist - -// CV32E40X test bench Directories -+incdir+${DV_UVMT_PATH} -+incdir+${DV_UVMT_PATH}/../../tests/uvmt -+incdir+${DV_UVMT_PATH}/../../tests/uvmt/base-tests -+incdir+${DV_UVMT_PATH}/../../tests/uvmt/compliance-tests -+incdir+${DV_UVMT_PATH}/../../tests/uvmt/vseq - -// CV32E40X tests (includes constants/macros/types meant for test bench) -+incdir+${TBSRC_HOME} -${DV_UVMT_PATH}/uvmt_cv32e40x_pkg.sv - -// CV32E40X test bench files -${DV_UVMT_PATH}/uvmt_cv32e40x_dut_wrap.sv -${DV_UVMT_PATH}/uvmt_cv32e40x_tb.sv -${TBSRC_HOME}/core/tb_riscv/include/perturbation_defines.sv -${TBSRC_HOME}/uvmt/uvmt_cv32e40x_tb.sv -${TBSRC_HOME}/uvmt/uvmt_cv32e40x_dut_wrap.sv -${TBSRC_HOME}/core/mm_ram.sv -${TBSRC_HOME}/core/dp_ram.sv -${TBSRC_HOME}/core/tb_riscv/riscv_gnt_stall.sv -${TBSRC_HOME}/core/tb_riscv/riscv_rvalid_stall.sv -${TBSRC_HOME}/core/tb_riscv/riscv_random_interrupt_generator.sv - -${DV_UVMT_PATH}/uvmt_cv32e40x_interrupt_assert.sv -${DV_UVMT_PATH}/uvmt_cv32e40x_debug_assert.sv -${DV_UVMT_PATH}/uvmt_cv32e40x_fencei_assert.sv -${DV_UVMT_PATH}/uvmt_cv32e40x_integration_assert.sv diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_constants.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_constants.sv deleted file mode 100644 index e8afdbfcdf..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_constants.sv +++ /dev/null @@ -1,178 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -`ifndef __UVMT_CV32E40X_CONSTANTS_SV__ -`define __UVMT_CV32E40X_CONSTANTS_SV__ - - `ifdef ZBA_ZBB_ZBS - parameter cv32e40x_pkg::b_ext_e B_EXT = cv32e40x_pkg::ZBA_ZBB_ZBS; - `elsif ZBA_ZBB_ZBC_ZBS - parameter cv32e40x_pkg::b_ext_e B_EXT = cv32e40x_pkg::ZBA_ZBB_ZBC_ZBS; - `else - parameter cv32e40x_pkg::b_ext_e B_EXT = cv32e40x_pkg::B_NONE; - `endif - - `ifdef PMA_CUSTOM_CFG - const string pma_cfg_name = "pma_custom_cfg"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 3; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - // Overlap "shadow" of main code (.text), for testing overlap priority - cv32e40x_pkg::pma_region_t'{ - word_addr_low : '0, - word_addr_high : ('h 1a11_0800 + 'd 16) >> 2, // should be identical to the prioritized region below - main : 0, // Would stop all execution, but should be overruled - bufferable : 0, - cacheable : 0, - atomic : 0}, - // Main code (.text) is executable up til into dbg region - cv32e40x_pkg::pma_region_t'{ - word_addr_low : '0, - word_addr_high : ('h 1a11_0800 + 'd 16) >> 2, // "dbg" address plus arbitrary offset to have a known usable area - main : 1, - bufferable : 1, - cacheable : 1, - atomic : 1}, - // Second portion of dbg up til end is exec - cv32e40x_pkg::pma_region_t'{ - word_addr_low : 'h 1A11_1000 >> 2, // after ".debugger" - word_addr_high : 'h FFFF_FFFF, - main : 1, - bufferable : 0, - cacheable : 0, - atomic : 1} - }; - `elsif PMA_DEBUG_CFG - const string pma_cfg_name = "pma_debug_cfg"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 2; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - // Everything is initially executable - cv32e40x_pkg::pma_region_t'{ - word_addr_low : '0, - word_addr_high : 'h FFFF_FFFF, - main : 1, - bufferable : 0, - cacheable : 0, - atomic : 1}, - // A small region below "dbg" is forbidden to facilitate pma exception testing - cv32e40x_pkg::pma_region_t'{ - word_addr_low : ('h 1a11_0800 - 'd 16) >> 2, - word_addr_high : 'h 1a11_0800 >> 2, - main : 0, - bufferable : 0, - cacheable : 0, - atomic : 0} - }; - `elsif PMA_TEST_CFG_1 - const string pma_cfg_name = "pma_test_cfg_1"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 1; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[0:CORE_PARAM_PMA_NUM_REGIONS-1] = '{ - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h7FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1} - }; - - `elsif PMA_TEST_CFG_2 - const string pma_cfg_name = "pma_test_cfg_2"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 7; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'hE010_0000>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'hE000_0000>>2, word_addr_high : 32'hE00F_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'hA000_0000>>2, word_addr_high : 32'hDFFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h6000_0000>>2, word_addr_high : 32'h9FFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h4000_0000>>2, word_addr_high : 32'h5FFF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h2000_0000>>2, word_addr_high : 32'h3FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h1FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1} - }; - `elsif PMA_TEST_CFG_3 - const string pma_cfg_name = "pma_test_cfg_3"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'h0000_A000>>2, word_addr_high : 32'hFFFE_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h0200_0000>>2, word_addr_high : 32'hEFFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h0500_0000>>2, word_addr_high : 32'h8459_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h1000_00F1>>2, word_addr_high : 32'h82FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h13AC_AA55>>2, word_addr_high : 32'h7FFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h2000_0000>>2, word_addr_high : 32'h63FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h2340_000A>>2, word_addr_high : 32'h600F_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h2A00_0000>>2, word_addr_high : 32'h56FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h2C5A_3200>>2, word_addr_high : 32'h52FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h3000_1353>>2, word_addr_high : 32'h5140_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h3100_FCAB>>2, word_addr_high : 32'h5000_BCCA>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h3420_C854>>2, word_addr_high : 32'h5000_ABFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h3600_A000>>2, word_addr_high : 32'h4F99_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h3ACE_0000>>2, word_addr_high : 32'h4ABC_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h4400_0000>>2, word_addr_high : 32'h4BFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h4800_0000>>2, word_addr_high : 32'h49FF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1} - }; - `elsif PMA_TEST_CFG_4 - const string pma_cfg_name = "pma_test_cfg_4"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'hE700_EF00>>2, word_addr_high : 32'hE9FF_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'hC000_0000>>2, word_addr_high : 32'hDFFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'hBC00_0000>>2, word_addr_high : 32'hBCFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'hA000_0000>>2, word_addr_high : 32'hAFFF_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h6300_0000>>2, word_addr_high : 32'h6700_FFFF>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h5400_0000>>2, word_addr_high : 32'h5FFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h5100_0000>>2, word_addr_high : 32'h52FF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h4D00_5555>>2, word_addr_high : 32'h4FFF_ABCD>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h4AAA_F000>>2, word_addr_high : 32'h4C00_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h3440_0000>>2, word_addr_high : 32'h3800_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h3100_A000>>2, word_addr_high : 32'h32FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h2020_0010>>2, word_addr_high : 32'h2FFF_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1}, - '{word_addr_low : 32'h1800_1234>>2, word_addr_high : 32'h18FF_AB21>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h1000_0000>>2, word_addr_high : 32'h1001_0000>>2, main : 1'b0, bufferable : 1'b1, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0030_0000>>2, word_addr_high : 32'h04FF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h0001_0000>>2, word_addr_high : 32'h001F_FFFF>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b1} - }; - `elsif PMA_TEST_CFG_5 - const string pma_cfg_name = "pma_test_cfg_5"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 16; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b1, bufferable : 1'b1, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h1249_2492>>2, word_addr_high : 32'h1249_2492>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'hDB6D_B6DB>>2, word_addr_high : 32'hDB6D_B6DB>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h9249_2492>>2, word_addr_high : 32'h9249_2492>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'hFFFF_FFFF>>2, word_addr_high : 32'hFFFF_FFFF>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'hE38E_E38E>>2, word_addr_high : 32'hE38E_E38E>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'hCCCC_CCCC>>2, word_addr_high : 32'hCCCC_CCCC>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'hAAAA_AAAA>>2, word_addr_high : 32'hAAAA_AAAA>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h5555_5555>>2, word_addr_high : 32'h5555_5555>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0}, - '{word_addr_low : 32'h0000_0000>>2, word_addr_high : 32'h0000_0000>>2, main : 1'b0, bufferable : 1'b0, cacheable : 1'b0, atomic : 1'b0} - }; - `elsif PMA_TEST_CFG_X1 // Used for memory layout generator debug - const string pma_cfg_name = "pma_test_cfg_x1"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 5; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[CORE_PARAM_PMA_NUM_REGIONS-1:0] = '{ - '{word_addr_low : 32'h00000000>>2, word_addr_high : 32'h20000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h30000000>>2, word_addr_high : 32'h40000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h50000000>>2, word_addr_high : 32'h60000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h70000000>>2, word_addr_high : 32'h80000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1}, - '{word_addr_low : 32'h00000000>>2, word_addr_high : 32'hF0000000>>2, main : 1'b1, bufferable : 1'b0, cacheable : 1'b1, atomic : 1'b1} - }; - `else - const string pma_cfg_name = "pma_noregion"; - parameter int unsigned CORE_PARAM_PMA_NUM_REGIONS = 0; - parameter cv32e40x_pkg::pma_region_t CORE_PARAM_PMA_CFG[-1:0] = '{default:cv32e40x_pkg::PMA_R_DEFAULT}; - `endif - - -`endif // __UVMT_CV32E40X_CONSTANTS_SV__ diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_debug_assert.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_debug_assert.sv deleted file mode 100644 index e8356f124b..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_debug_assert.sv +++ /dev/null @@ -1,741 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -module uvmt_cv32e40x_debug_assert - import uvm_pkg::*; - import cv32e40x_pkg::*; - ( - uvmt_cv32e40x_debug_cov_assert_if cov_assert_if - ); - - // --------------------------------------------------------------------------- - // Local parameters - // --------------------------------------------------------------------------- - localparam WFI_INSTR_MASK = 32'h ffff_ffff; - localparam WFI_INSTR_OPCODE = 32'h 1050_0073; - localparam EBREAK_INSTR_OPCODE = 32'h 0010_0073; - localparam CEBREAK_INSTR_OPCODE = 32'h 0000_9002; - localparam DRET_INSTR_OPCODE = 32'h 7B20_0073; - - // --------------------------------------------------------------------------- - // Local variables - // --------------------------------------------------------------------------- - string info_tag = "CV32E40X_DEBUG_ASSERT"; - logic [31:0] pc_at_dbg_req; // Capture PC when debug_req_i or ebreak is active - logic [31:0] pc_at_ebreak; // Capture PC when ebreak - logic [31:0] halt_addr_at_entry; - logic halt_addr_at_entry_flag; - logic [31:0] exception_addr_at_entry; - logic exception_addr_at_entry_flag; - logic [31:0] tdata2_at_entry; - // Locally track which debug cause should be used - logic [2:0] debug_cause_pri; - logic [31:0] boot_addr_at_entry; - logic [31:0] mtvec_addr; - logic is_trigger_match; - - // Locally track pc in ID stage to detect first instruction of debug code - logic first_debug_ins_flag; - logic first_debug_ins; - logic started_decoding_in_debug; - - // --------------------------------------------------------------------------- - // Clocking blocks - // --------------------------------------------------------------------------- - - // Single clock, single reset design, use default clocking - default clocking @(posedge cov_assert_if.clk_i); endclocking - default disable iff !(cov_assert_if.rst_ni); - - assign cov_assert_if.is_ebreak = - cov_assert_if.wb_valid - && (cov_assert_if.wb_stage_instr_rdata_i == EBREAK_INSTR_OPCODE) - && !cov_assert_if.wb_err - && (cov_assert_if.wb_mpu_status == MPU_OK); - - assign cov_assert_if.is_cebreak = - cov_assert_if.wb_valid - && (cov_assert_if.wb_stage_instr_rdata_i == CEBREAK_INSTR_OPCODE) - && !cov_assert_if.wb_err - && (cov_assert_if.wb_mpu_status == MPU_OK); - - assign cov_assert_if.is_mulhsu = - cov_assert_if.wb_stage_instr_valid_i - && (cov_assert_if.wb_stage_instr_rdata_i[31:25] == 7'h1) - && (cov_assert_if.wb_stage_instr_rdata_i[14:12] == 3'b010) - && (cov_assert_if.wb_stage_instr_rdata_i[6:0] == 7'h33); - - assign is_trigger_match = cov_assert_if.trigger_match_in_wb && cov_assert_if.wb_valid; - - assign mtvec_addr = {cov_assert_if.mtvec[31:2], 2'b00}; - - // --------------------------------------- - // Assertions - // --------------------------------------- - - // Helper sequence: Go to next WB retirement - - sequence s_conse_next_retire; // Should only be used in consequent (not antecedent) - ($fell(cov_assert_if.wb_stage_instr_valid_i) [->1] // Finish current WB preoccupation - ##0 cov_assert_if.wb_valid [->1]) // Go to next WB done - or - ($fell(cov_assert_if.ex_valid) [->1] // Finish current EX preoccupation - ##0 cov_assert_if.wb_valid [->2]) // Go to next two WB done - or - (cov_assert_if.wb_valid [->1] // Go directly to next WB done - ##0 (cov_assert_if.dcsr_q[8:6] inside {3, 4})) // Need good reason to forgo $fell(instr_valid) - ; - endsequence - - - // Check that we enter debug mode when expected. CSR checks are done in other assertions - property p_enter_debug; - $changed(debug_cause_pri) && (debug_cause_pri != 0) && !cov_assert_if.debug_mode_q - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q; - endproperty - - a_enter_debug: assert property(p_enter_debug) - else `uvm_error(info_tag, $sformatf("Debug mode not entered after exepected cause %d", debug_cause_pri)); - - - // Check that dpc gets the correct value when debug mode is entered. - - a_debug_mode_pc: assert property( - $rose(first_debug_ins) - |-> - cov_assert_if.wb_stage_pc == halt_addr_at_entry - ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong pc. pc==%08x", cov_assert_if.wb_stage_pc)); - - a_debug_mode_pc_dpc: assert property( - $rose(first_debug_ins) - |-> - cov_assert_if.depc_q == pc_at_dbg_req - ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong dpc. dpc==%08x", cov_assert_if.depc_q)); - - a_debug_mode_pc_dmode: assert property( - $rose(first_debug_ins) - |-> - cov_assert_if.debug_mode_q - ) else `uvm_error(info_tag, "First debug mode instruction predicted wrongly"); - - - // Check that dcsr.cause is as expected - - property p_dcsr_cause; - $rose(first_debug_ins) - |-> - (cov_assert_if.dcsr_q[8:6] == debug_cause_pri); - endproperty - - a_dcsr_cause: assert property(p_dcsr_cause) - else `uvm_error(info_tag, "dcsr.cause was not as expected"); - - - // Check that debug with cause haltreq is correct - property p_debug_mode_ext_req; - $rose(cov_assert_if.debug_mode_q) && (cov_assert_if.dcsr_q[8:6] == cv32e40x_pkg::DBG_CAUSE_HALTREQ) - |-> debug_cause_pri == cv32e40x_pkg::DBG_CAUSE_HALTREQ; - endproperty - - a_debug_mode_ext_req: assert property(p_debug_mode_ext_req) - else `uvm_error(info_tag, $sformatf("Debug cause not correct for haltreq, cause = %d",cov_assert_if.dcsr_q[8:6])); - - // Check that debug with cause ebreak is correct - property p_cebreak_debug_mode; - $rose(cov_assert_if.debug_mode_q) && (cov_assert_if.dcsr_q[8:6] == cv32e40x_pkg::DBG_CAUSE_EBREAK) - |-> debug_cause_pri == cv32e40x_pkg::DBG_CAUSE_EBREAK; - endproperty - - a_cebreak_debug_mode: assert property(p_cebreak_debug_mode) - else `uvm_error(info_tag,$sformatf("Debug mode with wrong cause after ebreak, case = %d",cov_assert_if.dcsr_q[8:6])); - - - // ebreak / c.ebreak without dcsr.ebreakm results in exception at mtvec - // (Exclude single stepping as the sequence gets very complicated) - - property p_general_ebreak_exception(ebreak); - $rose(ebreak) - && !cov_assert_if.debug_mode_q - && !cov_assert_if.dcsr_q[2] - && !cov_assert_if.dcsr_q[15] - ##0 ( - (!cov_assert_if.pending_debug && !cov_assert_if.irq_ack_o && !cov_assert_if.pending_nmi) - throughout (##1 cov_assert_if.wb_valid [->1]) - ) - |-> - !cov_assert_if.debug_mode_q - && (cov_assert_if.mcause_q[30:0] === cv32e40x_pkg::EXC_CAUSE_BREAKPOINT) - && (cov_assert_if.mepc_q == pc_at_ebreak) - && (cov_assert_if.wb_stage_pc == mtvec_addr); - // TODO:ropeders need assertions for what happens if cebreak and req/irq? - endproperty - - a_cebreak_exception: assert property( - p_general_ebreak_exception(cov_assert_if.is_cebreak) - ) else `uvm_error(info_tag, $sformatf("Exception not entered correctly after c.ebreak with dcsr.ebreak=0")); - - a_ebreak_exception: assert property( - p_general_ebreak_exception(cov_assert_if.is_ebreak) - ) else `uvm_error(info_tag, $sformatf("Exception not entered correctly after ebreak with dcsr.ebreak=0")); - - - // c.ebreak during debug mode results in relaunch of debug mode - - property p_cebreak_during_debug_mode; - $rose(cov_assert_if.is_cebreak) && cov_assert_if.debug_mode_q - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.wb_stage_pc == halt_addr_at_entry); - // TODO should check no change in dpc and dcsr - endproperty - - a_cebreak_during_debug_mode: assert property(p_cebreak_during_debug_mode) - else `uvm_error(info_tag,$sformatf("Debug mode not restarted after c.ebreak")); - - - // ebreak during debug mode results in relaunch - - property p_ebreak_during_debug_mode; - $rose(cov_assert_if.is_ebreak) && cov_assert_if.debug_mode_q - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.wb_stage_pc == halt_addr_at_entry); - // TODO should check no change in dpc and dcsr - endproperty - - a_ebreak_during_debug_mode: assert property(p_ebreak_during_debug_mode) - else `uvm_error(info_tag,$sformatf("Debug mode not restarted after ebreak")); - - - // Trigger match results in debug mode - - property p_trigger_match; - is_trigger_match ##0 cov_assert_if.tdata1[2] ##0 !cov_assert_if.debug_mode_q - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6] === cv32e40x_pkg::DBG_CAUSE_TRIGGER) - && (cov_assert_if.depc_q == tdata2_at_entry) && (cov_assert_if.wb_stage_pc == halt_addr_at_entry); - endproperty - - a_trigger_match: assert property(p_trigger_match) - else `uvm_error(info_tag, - $sformatf("Debug mode not correctly entered after trigger match depc=%08x, tdata2=%08x", - cov_assert_if.depc_q, tdata2_at_entry)); - - // Address match without trigger enabled should NOT result in debug mode - - property p_trigger_match_disabled; - $rose(cov_assert_if.addr_match) && !cov_assert_if.debug_mode_q |-> ##[1:6] !cov_assert_if.debug_mode_q; - endproperty - - a_trigger_match_disabled: assert property(p_trigger_match_disabled) - else `uvm_error(info_tag, "Trigger match with tdata[2]==0 resulted in debug mode"); - - - // Exception in debug mode results in pc->dm_exception_addr_i - - property p_debug_mode_exception; - $rose(cov_assert_if.illegal_insn_i) && cov_assert_if.debug_mode_q - |=> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.wb_stage_pc == exception_addr_at_entry); - endproperty - - a_debug_mode_exception : assert property(p_debug_mode_exception) - else `uvm_error(info_tag, - $sformatf("Exception in debug mode not handled incorrectly. dm=%d, pc=%08x", - cov_assert_if.debug_mode_q, cov_assert_if.wb_stage_pc)); - - - // ECALL in debug mode results in pc->dm_exception_addr_i - property p_debug_mode_ecall; - $rose(cov_assert_if.sys_ecall_insn_i && cov_assert_if.sys_en_i) && cov_assert_if.debug_mode_q - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.wb_stage_pc == exception_addr_at_entry); - endproperty - - a_debug_mode_ecall : assert property(p_debug_mode_ecall) - else `uvm_error(info_tag, - $sformatf("ECALL in debug mode not handled incorrectly. dm=%d, pc=%08x", - cov_assert_if.debug_mode_q, cov_assert_if.wb_stage_pc)); - - // IRQ in debug mode are masked - property p_irq_in_debug; - cov_assert_if.debug_mode_q |-> !cov_assert_if.irq_ack_o; - endproperty - - a_irq_in_debug : assert property(p_irq_in_debug) - else - `uvm_error(info_tag, $sformatf("IRQ not ignored while in debug mode")); - - - // WFI in debug mode does not sleep - - property p_wfi_in_debug; - cov_assert_if.debug_mode_q && $rose(cov_assert_if.is_wfi) |-> ##6 !cov_assert_if.core_sleep_o; - // TODO:ropeders should/could the consequent be more specific? - endproperty - - a_wfi_in_debug : assert property(p_wfi_in_debug) - else `uvm_error(info_tag, $sformatf("WFI in debug mode cause core_sleep_o=1")); - - - // Debug request while sleeping makes core wake up and enter debug mode with cause=haltreq - - property p_sleep_debug_req; - cov_assert_if.in_wfi && cov_assert_if.debug_req_i - |=> - !cov_assert_if.core_sleep_o - ##0 s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6] == cv32e40x_pkg::DBG_CAUSE_HALTREQ); - endproperty - - a_sleep_debug_req : assert property(p_sleep_debug_req) - else `uvm_error(info_tag, - $sformatf("Did not exit sleep(== %d) after debug_req_i. Debug_mode = %d cause = %d", - cov_assert_if.core_sleep_o, cov_assert_if.debug_mode_q, cov_assert_if.dcsr_q[8:6])); - - - // Accessing debug regs in m-mode is illegal - - property p_debug_regs_mmode; - int tmp; - cov_assert_if.ex_stage_csr_en && cov_assert_if.ex_valid && !cov_assert_if.debug_mode_q - && cov_assert_if.ex_stage_instr_rdata_i[31:20] inside {'h7B0, 'h7B1, 'h7B2, 'h7B3} - ##0 (1, tmp = cov_assert_if.ex_stage_pc) - |=> - (cov_assert_if.wb_stage_pc == tmp) [->1] - ##0 cov_assert_if.illegal_insn_i; - endproperty - - a_debug_regs_mmode : assert property(p_debug_regs_mmode) - else - `uvm_error(info_tag, "Accessing debug regs in M-mode did not result in illegal instruction"); - - - // Exception while single step -> PC is set to exception handler before debug - property p_single_step_exception; - !cov_assert_if.debug_mode_q && cov_assert_if.dcsr_q[2] - && cov_assert_if.illegal_insn_i && cov_assert_if.wb_valid && !is_trigger_match - |-> ##[1:20] cov_assert_if.debug_mode_q && (cov_assert_if.depc_q == mtvec_addr); - endproperty - - a_single_step_exception : assert property(p_single_step_exception) - else `uvm_error(info_tag, "PC not set to exception handler after single step with exception"); - - - // Trigger during single step - property p_single_step_trigger; - !cov_assert_if.debug_mode_q && cov_assert_if.dcsr_q[2] - && cov_assert_if.addr_match && cov_assert_if.wb_valid && cov_assert_if.tdata1[2] - |-> ##[1:20] cov_assert_if.debug_mode_q && (cov_assert_if.dcsr_q[8:6] == cv32e40x_pkg::DBG_CAUSE_TRIGGER) - && (cov_assert_if.depc_q == pc_at_dbg_req); - endproperty - - a_single_step_trigger : assert property (p_single_step_trigger) - else `uvm_error(info_tag, - $sformatf("Single step and trigger error: depc = %08x, cause = %d",cov_assert_if.depc_q, cov_assert_if.dcsr_q[8:6])); - - - // Single step WFI must not result in sleeping - - property p_single_step_wfi; - !cov_assert_if.debug_mode_q && cov_assert_if.dcsr_q[2] && cov_assert_if.is_wfi - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && !cov_assert_if.core_sleep_o; - endproperty - - a_single_step_wfi : assert property(p_single_step_wfi) - else `uvm_error(info_tag, "Debug mode not entered after single step WFI or core went sleeping"); - - - // Executing with single step with no irq results in debug mode - - property p_single_step; - !cov_assert_if.debug_mode_q && cov_assert_if.dcsr_q[2] && !cov_assert_if.dcsr_q[11] - && cov_assert_if.wb_stage_instr_valid_i - |=> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q; - endproperty - - a_single_step: assert property(p_single_step) - else `uvm_error(info_tag, "Debug mode not entered for single step"); - - - // dret in M-mode will cause illegal instruction - // If pending debug req, illegal insn will not assert until resume - property p_mmode_dret; - !cov_assert_if.debug_mode_q && cov_assert_if.is_dret && !cov_assert_if.pending_debug - |-> cov_assert_if.illegal_insn_i; - endproperty - - a_mmode_dret : assert property(p_mmode_dret) - else `uvm_error(info_tag, "Executing dret in M-mode did not result in illegal instruction"); - - - // dret in D-mode will restore pc (if no re-entry or interrupt intervenes) - - property p_dmode_dret_pc; - int dpc; (1, dpc =cov_assert_if.rvfi_csr_dpc_rdata) - ##0(cov_assert_if.rvfi_valid && cov_assert_if.rvfi_dbg_mode && cov_assert_if.rvfi_insn == DRET_INSTR_OPCODE) - - ##1 cov_assert_if.rvfi_valid[->1] - ##0 (!cov_assert_if.rvfi_intr && !cov_assert_if.rvfi_dbg_mode) - |-> - - cov_assert_if.rvfi_pc_rdata == dpc; - endproperty - - a_dmode_dret_pc : assert property(p_dmode_dret_pc) - else `uvm_error(info_tag, "Dret did not cause correct return from debug mode"); - - // dret in D-mode will place dpc in mepc if re-entry is interrupted - - /* - //TODO:mateilga reinstate this when the "kill" signal sensitivity in RVFI has been added - property p_dmode_dret_pc_int; - int dpc; (1, dpc =cov_assert_if.rvfi_csr_dpc_rdata) - ##0(cov_assert_if.rvfi_valid && cov_assert_if.rvfi_dbg_mode && cov_assert_if.rvfi_insn == DRET_INSTR_OPCODE) - - ##1 cov_assert_if.rvfi_valid[->1] - ##0 (cov_assert_if.rvfi_intr && !cov_assert_if.rvfi_dbg_mode) - |-> - - (cov_assert_if.rvfi_csr_mepc_wdata & cov_assert_if.rvfi_csr_mepc_wmask) == dpc; - - endproperty - - a_dmode_dret_pc_int : assert property(p_dmode_dret_pc_int) - else `uvm_error(info_tag, "Dret did not save dpc to mepc when return from debug mode was interrupted"); - - */ - - // dret in D-mode will exit D-mode - - property p_dmode_dret_exit; - cov_assert_if.debug_mode_q && cov_assert_if.is_dret - |=> !cov_assert_if.debug_mode_q; - // TODO:ropeders also assert, stays in mmode until wb_valid if no debug_request - endproperty - - a_dmode_dret_exit : assert property(p_dmode_dret_exit) - else `uvm_error(info_tag, "Dret did not exit debug mode"); - - // TODO:ropeders what is missing from these dret assertions? - - - // Check that trigger regs cannot be written from M-mode - // TSEL, and TDATA3 are tied to zero, hence no register to check - property p_mmode_tdata1_write; - !cov_assert_if.debug_mode_q && cov_assert_if.csr_access && cov_assert_if.csr_op == 'h1 // TODO:ropeders also "set" op? - && cov_assert_if.wb_stage_instr_rdata_i[31:20] == 'h7A1 - |-> - ##0 $stable(cov_assert_if.tdata1) [*4]; - endproperty - - a_mmode_tdata1_write : assert property(p_mmode_tdata1_write) - else `uvm_error(info_tag, "Writing tdata1 from M-mode not allowed to change register value!"); - - property p_mmode_tdata2_write; - !cov_assert_if.debug_mode_q && cov_assert_if.csr_access && cov_assert_if.csr_op == 'h1 - && cov_assert_if.wb_stage_instr_rdata_i[31:20] == 'h7A2 - |-> - ##0 $stable(cov_assert_if.tdata2) [*4]; - endproperty - - a_mmode_tdata2_write : assert property(p_mmode_tdata2_write) - else `uvm_error(info_tag, "Writing tdata2 from M-mode not allowed to change register value!"); - - - // Check that mcycle works as expected when not sleeping - // Counter can be written an arbitrary value, check that - // it changed only when not being written to - - property p_mcycle_count; - !cov_assert_if.mcountinhibit_q[0] && !cov_assert_if.core_sleep_o - && !(cov_assert_if.csr_we_int && (cov_assert_if.csr_addr ==12'hB00 || cov_assert_if.csr_addr == 12'hB80)) - |=> $changed(cov_assert_if.mcycle); - endproperty - - a_mcycle_count : assert property(p_mcycle_count) - else `uvm_error(info_tag, "Mcycle not counting when mcountinhibit[0] is cleared!"); - - - // Check that minstret works as expected when not sleeping - // Check only when not written to - - property p_minstret_count; - !cov_assert_if.mcountinhibit_q[2] && cov_assert_if.inst_ret && !cov_assert_if.core_sleep_o - && !(cov_assert_if.csr_we_int && (cov_assert_if.csr_addr == 12'hB02 || cov_assert_if.csr_addr == 12'hB82)) - |=> (cov_assert_if.minstret == ($past(cov_assert_if.minstret)+1)); - endproperty - - a_minstret_count : assert property(p_minstret_count) - else - `uvm_error(info_tag, "Minstret not counting when mcountinhibit[2] is cleared!"); - - // Check debug_req_i and irq on same cycle. - // Should result in debug mode with regular pc in dpc, not pc from interrupt handler. - // PC is checked in another assertion - property p_debug_req_and_irq; - ((cov_assert_if.debug_req_i || cov_assert_if.debug_req_q) && !cov_assert_if.debug_mode_q) - && (cov_assert_if.pending_enabled_irq != 0) - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q; - // TODO:ropeders should dpc be checked here? - endproperty - - a_debug_req_and_irq : assert property(p_debug_req_and_irq) - else `uvm_error(info_tag, "Debug mode not entered after debug_req_i and irq on same cycle"); - - - // debug_req at reset should result in debug mode and no instructions executed - - property p_debug_at_reset; - (cov_assert_if.ctrl_fsm_cs == cv32e40x_pkg::RESET) && cov_assert_if.debug_req_i - |-> - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.depc_q == boot_addr_at_entry); - endproperty - - a_debug_at_reset : assert property(p_debug_at_reset) - else `uvm_error(info_tag, "Debug mode not entered correctly at reset!"); - - - // Debug vs reset - - a_debug_state_onehot : assert property ( - $onehot({cov_assert_if.debug_havereset, cov_assert_if.debug_running, cov_assert_if.debug_halted}) - ) else `uvm_error(info_tag, "Should have exactly 1 of havereset/running/halted"); - - cov_havereset_to_running : cover property ( - (cov_assert_if.debug_havereset == 1) - && (cov_assert_if.debug_running == 0) - && (cov_assert_if.debug_halted == 0) - #=# - (cov_assert_if.debug_havereset == 0) - && (cov_assert_if.debug_running == 1) - && (cov_assert_if.debug_halted == 0) - ); - - cov_havereset_to_halted : cover property ( - (cov_assert_if.debug_havereset == 1) - && (cov_assert_if.debug_running == 0) - && (cov_assert_if.debug_halted == 0) - #=# - (cov_assert_if.debug_havereset == 0) - && (cov_assert_if.debug_running == 0) - && (cov_assert_if.debug_halted == 1) - ); - - - // Check that we cover the case where a debug_req_i - // comes while flushing due to an illegal insn, causing - // dpc to be set to the exception handler entry addr - - // TODO We have excluded the case where an nmi is taken in the second stage of the antecedent. - // Make sure this is covered in a debug vs nmi assertion when it is written - sequence s_illegal_insn_debug_req_ante; // Antecedent - cov_assert_if.wb_illegal && cov_assert_if.wb_valid && !cov_assert_if.debug_mode_q - ##1 cov_assert_if.debug_req_i && !cov_assert_if.debug_mode_q && !cov_assert_if.pending_nmi; - endsequence - - sequence s_illegal_insn_debug_req_conse; // Consequent - s_conse_next_retire - ##0 cov_assert_if.debug_mode_q && (cov_assert_if.depc_q == mtvec_addr); - endsequence - - // Need to confirm that the assertion can be reached for non-trivial cases - cov_illegal_insn_debug_req_nonzero : cover property( - s_illegal_insn_debug_req_ante |-> s_illegal_insn_debug_req_conse ##0 (cov_assert_if.depc_q != 0)); - - a_illegal_insn_debug_req : assert property(s_illegal_insn_debug_req_ante |-> s_illegal_insn_debug_req_conse) - else `uvm_error(info_tag, "Debug mode not entered correctly while handling illegal instruction!"); - - - // ------------------------------------------- - // Capture internal states for use in checking - // ------------------------------------------- - - always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin - if(!cov_assert_if.rst_ni) begin - pc_at_dbg_req <= 32'h0; - pc_at_ebreak <= 32'h0; - end else begin - // Capture debug pc - if (cov_assert_if.ctrl_fsm_cs == cv32e40x_pkg::BOOT_SET) begin - pc_at_dbg_req <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; - end - if (cov_assert_if.rvfi_valid) begin - pc_at_dbg_req <= cov_assert_if.rvfi_pc_wdata; - if ((debug_cause_pri == 2) && !started_decoding_in_debug) begin // trigger - pc_at_dbg_req <= cov_assert_if.rvfi_pc_rdata; - end - if ((debug_cause_pri == 1) && !started_decoding_in_debug) begin // ebreak - pc_at_dbg_req <= cov_assert_if.rvfi_pc_rdata; - end - end - if (cov_assert_if.addr_match && !cov_assert_if.tdata1[18] && cov_assert_if.wb_valid) begin // trigger - pc_at_dbg_req <= cov_assert_if.wb_stage_pc; - end - if (cov_assert_if.irq_ack_o) begin // interrupt - if (cov_assert_if.mtvec[1:0] == 0) begin - pc_at_dbg_req <= mtvec_addr; - end else if (cov_assert_if.mtvec[1:0] == 1) begin - pc_at_dbg_req <= mtvec_addr + (cov_assert_if.irq_id_o << 2); - end - end - if(cov_assert_if.pending_nmi && cov_assert_if.nmi_allowed && (cov_assert_if.ctrl_fsm_cs == cv32e40x_pkg::FUNCTIONAL)) - begin - //TODO:ropeders shouldn't "nmi_allowed" be trustable without "ctrl_fsm_cs"? - //TODO:ropeders shouldn't "dcsr.nmip" be usable as a "dpc" pedictor? - //TODO:ropeders shouldn't there be an assert for "dpc" not only on first instr in dmode? - pc_at_dbg_req <= cov_assert_if.nmi_addr_i; - end - if(cov_assert_if.debug_mode_q && started_decoding_in_debug) begin - pc_at_dbg_req <= pc_at_dbg_req; - end - - // Capture pc at ebreak - if(cov_assert_if.is_ebreak || cov_assert_if.is_cebreak ) begin - pc_at_ebreak <= cov_assert_if.wb_stage_pc; - end - end - end - - - // Keep track of wfi state - - always @(posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin - if (!cov_assert_if.rst_ni) begin - cov_assert_if.in_wfi <= 1'b0; - end else begin - // Enter wfi if we have a valid instruction, and conditions allow it (e.g. no single-step etc) - if (cov_assert_if.is_wfi && cov_assert_if.wb_valid - && !cov_assert_if.pending_debug && !cov_assert_if.debug_mode_q && !cov_assert_if.dcsr_q[2]) - cov_assert_if.in_wfi <= 1'b1; - if (cov_assert_if.pending_enabled_irq || cov_assert_if.debug_req_i) - cov_assert_if.in_wfi <= 1'b0; - end - end - - - // Capture dm_halt_addr_i value - - always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin - //TODO:ropeders this should be entirely unnecessary because user manual says it should be stable. Could remove? - if(!cov_assert_if.rst_ni) begin - halt_addr_at_entry_flag <= 1'b0; - end else begin - if(!halt_addr_at_entry_flag) begin - if(cov_assert_if.ctrl_fsm_cs == cv32e40x_pkg::DEBUG_TAKEN) begin - halt_addr_at_entry <= {cov_assert_if.dm_halt_addr_i[31:2], 2'b00}; - tdata2_at_entry <= cov_assert_if.tdata2; - halt_addr_at_entry_flag <= 1'b1; - end - end - - // Clear flag while not in dmode or we see ebreak in debug - if ((!cov_assert_if.debug_mode_q && halt_addr_at_entry_flag) - || (cov_assert_if.debug_mode_q && (cov_assert_if.is_ebreak || cov_assert_if.is_cebreak))) - begin - halt_addr_at_entry_flag <= 1'b0; - end - - // Capture boot addr - if(cov_assert_if.ctrl_fsm_cs == cv32e40x_pkg::BOOT_SET) - boot_addr_at_entry <= {cov_assert_if.boot_addr_i[31:2], 2'b00}; - end - end - always@ (posedge cov_assert_if.clk_i) begin - if ((cov_assert_if.illegal_insn_i || (cov_assert_if.sys_ecall_insn_i && cov_assert_if.sys_en_i)) - && cov_assert_if.pc_set && cov_assert_if.debug_mode_q && cov_assert_if.wb_valid) - begin - exception_addr_at_entry = {cov_assert_if.dm_exception_addr_i[31:2], 2'b00}; - end - end - - assign cov_assert_if.addr_match = (cov_assert_if.wb_stage_pc == cov_assert_if.tdata2); - assign cov_assert_if.dpc_will_hit = (cov_assert_if.depc_n == cov_assert_if.tdata2); - assign cov_assert_if.pending_enabled_irq = |(cov_assert_if.irq_i & cov_assert_if.mie_q); - assign cov_assert_if.is_wfi = - cov_assert_if.wb_valid - && ((cov_assert_if.wb_stage_instr_rdata_i & WFI_INSTR_MASK) == WFI_INSTR_OPCODE) - && !cov_assert_if.wb_err - && (cov_assert_if.wb_mpu_status == MPU_OK); - assign cov_assert_if.is_dret = - cov_assert_if.wb_valid - && (cov_assert_if.wb_stage_instr_rdata_i == DRET_INSTR_OPCODE) - && !cov_assert_if.wb_err - && (cov_assert_if.wb_mpu_status == MPU_OK); - - - // Track which debug cause should be expected - - always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin - if( !cov_assert_if.rst_ni) begin - debug_cause_pri <= 3'b000; - end else if(!cov_assert_if.debug_mode_q) begin - if (is_trigger_match) begin - debug_cause_pri <= 3'b010; // Trigger match - end else if(cov_assert_if.dcsr_q[15] && (cov_assert_if.is_ebreak || cov_assert_if.is_cebreak)) begin - debug_cause_pri <= 3'b001; // Ebreak - end else if((cov_assert_if.debug_req_i || cov_assert_if.debug_req_q) - && (cov_assert_if.ctrl_fsm_cs == cv32e40x_pkg::FUNCTIONAL)) begin - debug_cause_pri <= 3'b011; // Haltreq - end else if((cov_assert_if.dcsr_q[2]) && (debug_cause_pri inside {3'b100, 0})) begin // "step" - debug_cause_pri <= 3'b100; // Single step - end else if(cov_assert_if.ctrl_fsm_cs == cv32e40x_pkg::FUNCTIONAL) begin - debug_cause_pri <= 3'b000; // (not a cause) - end - // TODO:ropeders should have cause 5 when RTL is ready - end - end - - - // Detect first instruction of debug code - - assign first_debug_ins = - cov_assert_if.debug_mode_q && cov_assert_if.wb_valid - && !first_debug_ins_flag && started_decoding_in_debug; - - always@ (posedge cov_assert_if.clk_i or negedge cov_assert_if.rst_ni) begin - if( !cov_assert_if.rst_ni) begin - first_debug_ins_flag <= 0; - started_decoding_in_debug <= 0; - end else begin - if(cov_assert_if.debug_mode_q) begin - if(cov_assert_if.wb_valid) begin - first_debug_ins_flag <= 1; - end - if(cov_assert_if.id_valid) begin - started_decoding_in_debug <= 1; - end - end else begin - first_debug_ins_flag <= 0; - started_decoding_in_debug <= 0; - end - end - end - -endmodule : uvmt_cv32e40x_debug_assert diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv deleted file mode 100644 index e390a57b54..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv +++ /dev/null @@ -1,230 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -/////////////////////////////////////////////////////////////////////////////// -// -// Modified version of the wrapper for a RI5CY testbench, containing RI5CY, -// plus Memory and stdout virtual peripherals. -// Contributor: Robert Balas -// Copyright 2018 Robert Balas -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// - - -`ifndef __UVMT_CV32E40X_DUT_WRAP_SV__ -`define __UVMT_CV32E40X_DUT_WRAP_SV__ - - -/** - * Module wrapper for CV32E40X RTL DUT. - */ -module uvmt_cv32e40x_dut_wrap - import cv32e40x_pkg::*; - - #(// DUT (riscv_core) parameters. - parameter NUM_MHPMCOUNTERS = 1, - parameter cv32e40x_pkg::b_ext_e B_EXT = cv32e40x_pkg::B_NONE, - parameter int PMA_NUM_REGIONS = 0, - parameter pma_region_t PMA_CFG[PMA_NUM_REGIONS-1 : 0] = '{default:PMA_R_DEFAULT}, - // Remaining parameters are used by TB components only - INSTR_ADDR_WIDTH = 32, - INSTR_RDATA_WIDTH = 32, - RAM_ADDR_WIDTH = 20 - ) - ( - uvma_clknrst_if clknrst_if, - uvma_interrupt_if interrupt_if, - uvmt_cv32e40x_vp_status_if vp_status_if, - uvme_cv32e40x_core_cntrl_if core_cntrl_if, - uvmt_cv32e40x_core_status_if core_status_if, - uvma_obi_memory_if obi_instr_if_i, - uvma_obi_memory_if obi_data_if_i, - uvma_fencei_if fencei_if_i - ); - - import uvm_pkg::*; // needed for the UVM messaging service (`uvm_info(), etc.) - - // signals connecting core to memory - logic instr_req; - logic instr_gnt; - logic instr_rvalid; - logic [INSTR_ADDR_WIDTH-1 :0] instr_addr; - logic [INSTR_RDATA_WIDTH-1:0] instr_rdata; - - logic data_req; - logic data_gnt; - logic data_rvalid; - logic [31:0] data_addr; - logic data_we; - logic [3:0] data_be; - logic [31:0] data_rdata; - logic [31:0] data_wdata; - - logic [31:0] irq; - - logic debug_havereset; - logic debug_running; - logic debug_halted; - - // eXtension interface - // todo: Connect to TB when implemented. - // Included to allow core-v-verif to compile with RTL including - // interface definition. - if_xif xif(); - - assign debug_if.clk = clknrst_if.clk; - assign debug_if.reset_n = clknrst_if.reset_n; - - // -------------------------------------------- - // OBI Instruction agent v1.2 signal tie-offs - assign obi_instr_if_i.we = 'b0; - assign obi_instr_if_i.be = 'hf; // Always assumes 32-bit full bus reads on instruction OBI - assign obi_instr_if_i.auser = 'b0; - assign obi_instr_if_i.wuser = 'b0; - assign obi_instr_if_i.aid = 'b0; - assign obi_instr_if_i.atop = 'b0; - assign obi_instr_if_i.wdata = 'b0; - assign obi_instr_if_i.reqpar = ~obi_instr_if_i.req; - assign obi_instr_if_i.achk = 'b0; - assign obi_instr_if_i.rchk = 'b0; - assign obi_instr_if_i.rready = 1'b1; - assign obi_instr_if_i.rreadypar = 1'b0; - - // -------------------------------------------- - // OBI Data agent v12.2 signal tie-offs - assign obi_data_if_i.auser = 'b0; - assign obi_data_if_i.wuser = 'b0; - assign obi_data_if_i.aid = 'b0; - assign obi_data_if_i.reqpar = ~obi_data_if_i.req; - assign obi_data_if_i.achk = 'b0; - assign obi_data_if_i.rchk = 'b0; - assign obi_data_if_i.rready = 1'b1; - assign obi_data_if_i.rreadypar = 1'b0; - - // -------------------------------------------- - // Connect to uvma_interrupt_if - assign interrupt_if.clk = clknrst_if.clk; - assign interrupt_if.reset_n = clknrst_if.reset_n; - assign interrupt_if.irq_id = cv32e40x_wrapper_i.core_i.irq_id; - assign interrupt_if.irq_ack = cv32e40x_wrapper_i.core_i.irq_ack; - - // -------------------------------------------- - // Connect to core_cntrl_if - assign core_cntrl_if.num_mhpmcounters = NUM_MHPMCOUNTERS; - assign core_cntrl_if.b_ext = B_EXT; - initial begin - core_cntrl_if.pma_cfg = new[PMA_NUM_REGIONS]; - foreach (core_cntrl_if.pma_cfg[i]) begin - core_cntrl_if.pma_cfg[i].word_addr_low = PMA_CFG[i].word_addr_low; - core_cntrl_if.pma_cfg[i].word_addr_high = PMA_CFG[i].word_addr_high; - core_cntrl_if.pma_cfg[i].main = PMA_CFG[i].main; - core_cntrl_if.pma_cfg[i].bufferable = PMA_CFG[i].bufferable; - core_cntrl_if.pma_cfg[i].cacheable = PMA_CFG[i].cacheable; - core_cntrl_if.pma_cfg[i].atomic = PMA_CFG[i].atomic; - end - end - - // -------------------------------------------- - // instantiate the core - cv32e40x_wrapper #( - .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS), - .B_EXT (B_EXT), - .PMA_NUM_REGIONS (PMA_NUM_REGIONS), - .PMA_CFG (PMA_CFG) - ) - cv32e40x_wrapper_i - ( - .clk_i ( clknrst_if.clk ), - .rst_ni ( clknrst_if.reset_n ), - - .scan_cg_en_i ( core_cntrl_if.scan_cg_en ), - - .boot_addr_i ( core_cntrl_if.boot_addr ), - .mtvec_addr_i ( core_cntrl_if.mtvec_addr ), - .dm_halt_addr_i ( core_cntrl_if.dm_halt_addr ), - .nmi_addr_i ( core_cntrl_if.nmi_addr ), - .mhartid_i ( core_cntrl_if.mhartid ), - .mimpid_i ( core_cntrl_if.mimpid ), - .dm_exception_addr_i ( core_cntrl_if.dm_exception_addr), - - .instr_req_o ( obi_instr_if_i.req ), - .instr_gnt_i ( obi_instr_if_i.gnt ), - .instr_addr_o ( obi_instr_if_i.addr ), - .instr_prot_o ( obi_instr_if_i.prot ), - .instr_dbg_o ( /* obi_instr_if_i.dbg */ ), // todo: Support OBI 1.3 - .instr_memtype_o ( obi_instr_if_i.memtype ), - .instr_rdata_i ( obi_instr_if_i.rdata ), - .instr_rvalid_i ( obi_instr_if_i.rvalid ), - .instr_err_i ( obi_instr_if_i.err ), - - .data_req_o ( obi_data_if_i.req ), - .data_gnt_i ( obi_data_if_i.gnt ), - .data_rvalid_i ( obi_data_if_i.rvalid ), - .data_we_o ( obi_data_if_i.we ), - .data_be_o ( obi_data_if_i.be ), - .data_addr_o ( obi_data_if_i.addr ), - .data_wdata_o ( obi_data_if_i.wdata ), - .data_prot_o ( obi_data_if_i.prot ), - .data_dbg_o ( /* obi_data_if_i.dbg */ ), // todo: Support OBI 1.3 - .data_memtype_o ( obi_data_if_i.memtype ), - .data_rdata_i ( obi_data_if_i.rdata ), - .data_atop_o ( obi_data_if_i.atop ), - .data_err_i ( obi_data_if_i.err ), - .data_exokay_i ( obi_data_if_i.exokay ), - - .mcycle_o ( /*todo: connect */ ), - - .xif_compressed_if ( xif.cpu_compressed ), - .xif_issue_if ( xif.cpu_issue ), - .xif_commit_if ( xif.cpu_commit ), - .xif_mem_if ( xif.cpu_mem ), - .xif_mem_result_if ( xif.cpu_mem_result ), - .xif_result_if ( xif.cpu_result ), - - .irq_i ( interrupt_if.irq ), - - .clic_irq_i ( '0 /*todo: connect */ ), - .clic_irq_id_i ( '0 /*todo: connect */ ), - .clic_irq_il_i ( '0 /*todo: connect */ ), - .clic_irq_priv_i ( '0 /*todo: connect */ ), - .clic_irq_hv_i ( '0 /*todo: connect */ ), - .clic_irq_id_o ( /*todo: connect */ ), - .clic_irq_mode_o ( /*todo: connect */ ), - .clic_irq_exit_o ( /*todo: connect */ ), - - .fencei_flush_req_o ( fencei_if_i.flush_req ), - .fencei_flush_ack_i ( fencei_if_i.flush_ack ), - - .debug_req_i ( debug_if.debug_req ), - .debug_havereset_o ( debug_havereset ), - .debug_running_o ( debug_running ), - .debug_halted_o ( debug_halted ), - - .fetch_enable_i ( core_cntrl_if.fetch_en ), - .core_sleep_o ( core_status_if.core_busy ) - ); - -endmodule : uvmt_cv32e40x_dut_wrap - -`endif // __UVMT_CV32E40X_DUT_WRAP_SV__ diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_fencei_assert.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_fencei_assert.sv deleted file mode 100644 index 8081b35c50..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_fencei_assert.sv +++ /dev/null @@ -1,272 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - - -module uvmt_cv32e40x_fencei_assert - import cv32e40x_pkg::*; - import uvm_pkg::*; -#( - parameter int PMA_NUM_REGIONS = 0, - parameter pma_region_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:'Z} -)( - input clk_i, - input rst_ni, - - input fencei_flush_req_o, - input fencei_flush_ack_i, - - input wb_valid, - input wb_instr_valid, - input wb_sys_en, - input wb_sys_fencei_insn, - input [31:0] wb_pc, - input [31:0] wb_rdata, - input wb_buffer_state, - - input instr_req_o, - input [31:0] instr_addr_o, - input instr_gnt_i, - - input data_req_o, - input data_gnt_i, - input data_rvalid_i, - - input rvfi_valid, - input rvfi_intr, - input rvfi_dbg_mode -); - - localparam int CYCLE_COUNT = 6; - default clocking @(posedge clk_i); endclocking - default disable iff !rst_ni; - string info_tag = "CV32E40X_FENCEI_ASSERT"; - - logic is_fencei_in_wb; - assign is_fencei_in_wb = wb_sys_fencei_insn && wb_sys_en && wb_instr_valid; - - int obi_outstanding; - always @(posedge clk_i, negedge rst_ni) begin - if (~rst_ni) begin - obi_outstanding <= 0; - end else if (data_req_o && data_gnt_i && !data_rvalid_i) begin - obi_outstanding <= obi_outstanding + 1; - end else if (data_rvalid_i && !(data_req_o && data_gnt_i)) begin - obi_outstanding <= obi_outstanding - 1; - end - end - - function logic bufferable_in_config; - bufferable_in_config = 0; - foreach (PMA_CFG[i]) begin - if (PMA_CFG[i].bufferable) begin - bufferable_in_config = 1; - end - end - endfunction - - a_req_stay_high: assert property ( - fencei_flush_req_o && !fencei_flush_ack_i - |=> - fencei_flush_req_o - ) else `uvm_error(info_tag, "req must not drop before ack"); - - a_req_drop_lo: assert property ( - fencei_flush_req_o && fencei_flush_ack_i - |=> - !fencei_flush_req_o - ) else `uvm_error(info_tag, "req must drop after ack"); - - a_req_rise_before_retire: assert property ( - $rose(is_fencei_in_wb) - |-> - !wb_valid throughout ( - ($rose(fencei_flush_req_o) [->1]) - or - ($fell(is_fencei_in_wb) [->1]) - ) - ) else `uvm_error(info_tag, "fencei shall not retire without seeing a rising flush req"); - - a_req_must_retire: assert property ( - fencei_flush_req_o - |-> - is_fencei_in_wb until_with wb_valid - ) else `uvm_error(info_tag, "if there is no retire then there can't be a req"); - - property p_fetch_after_retire; - int pc_next; - (is_fencei_in_wb && wb_valid, pc_next={wb_pc[31:2],2'b00}+4) - |-> - ( - // Normal execution - (instr_req_o && instr_gnt_i) [->1:2] // next req-gnt (or second next, if ongoing req) - ##0 (instr_addr_o == pc_next) - ) or ( - // Exception execution - rvfi_valid [->2:3] // retire: fencei, (optionally "rvfi_trap"), interrupt/debug handler - ##0 (rvfi_intr || rvfi_dbg_mode) - ); - endproperty - a_fetch_after_retire: assert property ( - p_fetch_after_retire - ) else `uvm_error(info_tag, "after fencei, the next-pc fetching cannot be forgone"); - - a_stall_until_ack: assert property ( - fencei_flush_req_o && !fencei_flush_ack_i - |=> - !$changed(wb_pc) - ) else `uvm_error(info_tag, "WB stage must remain unchanged until the flush req is acked"); - - property p_branch_after_retire; - int pc_next; - (fencei_flush_req_o, pc_next=wb_pc+4) - ##1 !fencei_flush_req_o - |=> - ( - wb_valid [->1:2] - ##0 (wb_pc == pc_next) - ) or ( - rvfi_valid [->2] - ##0 (rvfi_intr || rvfi_dbg_mode) - ); - endproperty - a_branch_after_retire: assert property ( - p_branch_after_retire - ) else `uvm_error(info_tag, "the pc following fencei did not enter WB"); - - a_supress_datareq: assert property ( - fencei_flush_req_o - |-> - !data_req_o - ) else `uvm_error(info_tag, "obi data req shall not happen while fencei is flushing"); - - property p_fencei_quick_retire; - $rose(is_fencei_in_wb) - ##1 (fencei_flush_req_o && fencei_flush_ack_i); - endproperty - a_cycle_count_minimum: assert property ( - p_fencei_quick_retire - implies - (##1 !$rose(wb_instr_valid) [*CYCLE_COUNT-1]) - ) else `uvm_error(info_tag, "fencei shan't finish before the expected number of cycles"); - c_cycle_count_minimum: cover property ( - p_fencei_quick_retire - and - (s_nexttime [CYCLE_COUNT] $rose(wb_instr_valid)) - ); - - property p_req_wait_bus; - fencei_flush_req_o - |-> - !data_rvalid_i throughout ( - $fell(wb_valid) [->1] - ##1 (data_req_o && data_gnt_i) [->1] - ); - endproperty - a_req_wait_bus: assert property (p_req_wait_bus) - else `uvm_error(info_tag, "flush req shall not come if rvalid is awaited"); - if (bufferable_in_config()) begin : gen_c_req_wait_bus - c_req_wait_bus: cover property ( - $rose(is_fencei_in_wb) - ##1 ( - is_fencei_in_wb throughout ( - ($rose(data_rvalid_i) [->1]) - ##0 ($rose(fencei_flush_req_o) [->1]) - ) - ) - ); - end - - property p_req_wait_outstanding; - fencei_flush_req_o |-> (obi_outstanding == 0); - endproperty - a_req_wait_outstanding: assert property (p_req_wait_outstanding) - else `uvm_error(info_tag, "flush req shall not come if obi has outstanding transactions"); - if (bufferable_in_config()) begin : gen_c_req_wait_outstanding_1 - c_req_wait_outstanding_1: cover property ( - is_fencei_in_wb throughout ((obi_outstanding >= 1) ##0 (fencei_flush_req_o [->1])) - ); - end - - - property p_req_wait_buffer; - is_fencei_in_wb && (wb_buffer_state == WBUF_FULL) |-> - !fencei_flush_req_o throughout( - (data_rvalid_i && (wb_buffer_state == WBUF_EMPTY)) [->1] - ); - endproperty - - a_req_wait_buffer: assert property(p_req_wait_buffer) - else `uvm_error(info_tag, "fencei_flush_req_o should be held low until write buffer is empty"); - - - // TODO:ropeders assert fencei flush req explicitly vs X interface queue (not just vs rvalid) - - - for (genvar i = 1; i <= 5; i++) begin: gen_ack_delayed - // "5" is an appropriate arbitrary upper limit - c_ack_delayed: cover property ( - $rose(fencei_flush_req_o) - ##0 (!fencei_flush_ack_i) [*i] - ##1 fencei_flush_ack_i - ); - end - - covergroup cg_reqack(string name) @(posedge clk_i); - option.per_instance = 1; - option.name = name; - - cp_req: coverpoint fencei_flush_req_o { - bins hi = {1}; - bins lo = {0}; - bins rose = (0 => 1); - bins fell = (1 => 0); - } - cp_ack: coverpoint fencei_flush_ack_i { - bins hi = {1}; - bins lo = {0}; - bins rose = (0 => 1); - bins fell = (1 => 0); - } - cross_req_ack: cross cp_req, cp_ack { - illegal_bins il = binsof(cp_req.fell) && binsof(cp_ack.rose); - } - endgroup - cg_reqack reqack_cg = new("reqack"); - - c_no_retire: cover property ( - $rose(is_fencei_in_wb) - ##0 (!wb_valid throughout ($fell(is_fencei_in_wb) [->1])) - ); - - covergroup cg_reserved(string name) @(posedge clk_i); - option.per_instance = 1; - option.name = name; - - // Just a handfull of different values for reserved to-be-ignored fields - cp_imm: coverpoint wb_rdata[31:20] iff (is_fencei_in_wb && wb_valid) { - bins b[4] = {[0:$]}; - } - cp_rs1: coverpoint wb_rdata[19:15] iff (is_fencei_in_wb && wb_valid) { - bins b[4] = {[0:$]}; - } - cp_rd: coverpoint wb_rdata[11:7] iff (is_fencei_in_wb && wb_valid) { - bins b[4] = {[0:$]}; - } - endgroup - cg_reserved reserved_cg = new("reserved"); - -endmodule : uvmt_cv32e40x_fencei_assert diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_integration_assert.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_integration_assert.sv deleted file mode 100644 index 1560907c5b..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_integration_assert.sv +++ /dev/null @@ -1,93 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - - -// This module contains assertions relating to the "Core Integration" chapter -// of the user manual - -module uvmt_cv32e40x_integration_assert - import uvm_pkg::*; -( - input clk_i, - input rst_ni, - - input fetch_enable_i, - - input [31:0] boot_addr_i, - input [31:0] dm_exception_addr_i, - input [31:0] dm_halt_addr_i, - input [31:0] mtvec_addr_i, - input [31:0] nmi_addr_i -); - - default clocking @(posedge clk_i); endclocking - default disable iff !rst_ni; - string info_tag = "CV32E40X_INTEGRATION_ASSERT"; - - logic fetch_enable_i_sticky; - always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - fetch_enable_i_sticky <= 0; - end else if (fetch_enable_i) begin - fetch_enable_i_sticky <= 1; - end - end - - - // Check that addresses are stable after "fetch_enable_i" - - property p_stable_addr(addr); - fetch_enable_i_sticky |-> $stable(addr); - endproperty - - a_stable_bootaddr : assert property (p_stable_addr(boot_addr_i)) - else `uvm_error(info_tag, "boot_addr_i changed after fetch_enable_i"); - - a_stable_dmexceptionaddr : assert property (p_stable_addr(dm_exception_addr_i)) - else `uvm_error(info_tag, "dm_exception_addr_i changed after fetch_enable_i"); - - a_stable_dmhaltaddr : assert property (p_stable_addr(dm_halt_addr_i)) - else `uvm_error(info_tag, "dm_halt_addr_i changed after fetch_enable_i"); - - a_stable_mtvecaddr : assert property (p_stable_addr(mtvec_addr_i)) - else `uvm_error(info_tag, "mtvec_addr_i changed after fetch_enable_i"); - - a_stable_nmiaddr : assert property (p_stable_addr(nmi_addr_i)) - else `uvm_error(info_tag, "nmi_addr_i changed after fetch_enable_i"); - - - // Check that addresses are word-aligned - - property p_aligned_addr(addr); - addr[1:0] == 2'b00; - endproperty - - a_aligned_bootaddr : assert property (p_aligned_addr(boot_addr_i)) - else `uvm_error(info_tag, "boot_addr_i not word-aligned"); - - a_aligned_dmexceptionaddr : assert property (p_aligned_addr(dm_exception_addr_i)) - else `uvm_error(info_tag, "dm_exception_addr_i not word-aligned"); - - a_aligned_dmhaltaddr : assert property (p_aligned_addr(dm_halt_addr_i)) - else `uvm_error(info_tag, "dm_halt_addr_i not word-aligned"); - - //a_aligned_mtvecaddr is not required by the user manual as per now - - a_aligned_nmiaddr : assert property (p_aligned_addr(nmi_addr_i)) - else `uvm_error(info_tag, "nmi_addr_i not word-aligned"); - -endmodule : uvmt_cv32e40x_integration_assert diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_interrupt_assert.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_interrupt_assert.sv deleted file mode 100644 index ff0edfb2a1..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_interrupt_assert.sv +++ /dev/null @@ -1,438 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - -module uvmt_cv32e40x_interrupt_assert - import uvm_pkg::*; - import cv32e40x_pkg::*; - ( - - input clk, // Gated clock - input clk_i, // Free-running core clock - input rst_ni, - - // Core inputs - input fetch_enable_i, // external core fetch enable - - // External interrupt interface - input [31:0] irq_i, - input irq_ack_o, - input [4:0] irq_id_o, - - // External debug req (for WFI modeling) - input debug_req_i, - input debug_mode_q, - - // CSR Interface - input [5:0] mcause_n, // mcause_n[5]: interrupt, mcause_n[4]: vector - input [31:0] mip, // machine interrupt pending - input [31:0] mie_q, // machine interrupt enable - input mstatus_mie, // machine mode interrupt enable - input [1:0] mtvec_mode_q, // machine mode interrupt vector mode - - // Instruction fetch stage - input if_stage_instr_req_o, - input if_stage_instr_rvalid_i, // Instruction word is valid - input [31:0] if_stage_instr_rdata_i, // Instruction word data - input [ 1:0] alignbuf_outstanding, // Alignment buffer's number of outstanding transactions - - // Instruction EX stage - input ex_stage_instr_valid, // EX pipeline stage has valid input - - // Instruction WB stage (determines executed instructions) - input wb_stage_instr_valid_i, // instruction word is valid - input [31:0] wb_stage_instr_rdata_i, // Instruction word data - input wb_stage_instr_err_i, // OBI "err" - input mpu_status_e wb_stage_instr_mpu_status, // MPU read/write errors - - // Load-store unit status - input lsu_busy, - - // Determine whether to cancel instruction if branch taken - input branch_taken_ex, - - // WFI Interface - input core_sleep_o - ); - - // --------------------------------------------------------------------------- - // Local parameters - // --------------------------------------------------------------------------- - localparam NUM_IRQ = 32; - localparam VALID_IRQ_MASK = 32'hffff_0888; // Valid external interrupt signals - - localparam WFI_INSTR_DATA = 32'h10500073; - - localparam WFI_TO_CORE_SLEEP_LATENCY = 2; - localparam WFI_WAKEUP_LATENCY = 40; - - // --------------------------------------------------------------------------- - // Local variables - // --------------------------------------------------------------------------- - string info_tag = "CV32E40X_IRQ_ASSERT"; - - wire [31:0] pending_enabled_irq; - wire [31:0] pending_enabled_irq_q; - - reg in_wfi; // Local model of WFI state of core - - reg[31:0] irq_q; - - reg[31:0] next_irq; - reg next_irq_valid; - - reg[31:0] next_irq_q; - reg next_irq_valid_q; - reg[31:0] saved_mie_q; - - reg[31:0] expected_irq; - logic expected_irq_ack; - - reg[31:0] last_instr_rdata; - - // --------------------------------------------------------------------------- - // Clocking blocks - // --------------------------------------------------------------------------- - - // Single clock, single reset design, use default clocking - default clocking @(posedge clk_i); endclocking - default disable iff !(rst_ni); - - // --------------------------------------------------------------------------- - // Begin module code - // --------------------------------------------------------------------------- - assign pending_enabled_irq = irq_i & mie_q; - assign pending_enabled_irq_q = irq_q & mie_q; - - // --------------------------------------------------------------------------- - // Interrupt interface checks - // --------------------------------------------------------------------------- - - // irq_ack_o is always a pulse - property p_irq_ack_o_pulse; - irq_ack_o |=> !irq_ack_o; - endproperty - a_irq_ack_o_pulse: assert property(p_irq_ack_o_pulse) - else - `uvm_error(info_tag, - "Interrupt ack was asserted for more than one cycle"); - - // irq_id_o is never a reserved irq - property p_irq_id_o_not_reserved; - irq_ack_o |-> VALID_IRQ_MASK[irq_id_o]; - endproperty - a_irq_id_o_not_reserved: assert property(p_irq_id_o_not_reserved) - else - `uvm_error(info_tag, - $sformatf("int_id_o output is 0x%0x which is reserved", irq_id_o)); - - // irq_id_o is never a disabled irq - property p_irq_id_o_mie_enabled; - irq_ack_o |-> mie_q[irq_id_o]; - endproperty - a_irq_id_o_mie_enabled: assert property(p_irq_id_o_mie_enabled) - else - `uvm_error(info_tag, - $sformatf("irq_id_o output is 0x%0x which is disabled in MIE: 0x%08x", irq_id_o, mie_q)); - - // irq_ack_o cannot be asserted if mstatus_mie is deasserted - property p_irq_id_o_mstatus_mie_enabled; - irq_ack_o |-> mstatus_mie; - endproperty - a_irq_id_o_mstatus_mie_enabled: assert property(p_irq_id_o_mstatus_mie_enabled) - else - `uvm_error(info_tag, - $sformatf("int_id_o output is 0x%0x but MSTATUS.MIE is disabled", irq_id_o)); - - // --------------------------------------------------------------------------- - // Interrupt CSR checks - // --------------------------------------------------------------------------- - - // Coverage for individual interupt assertions - sequence s_irq_taken(irq); - irq_i[irq] ##0 mie_q[irq] ##0 mstatus_mie ##0 irq_ack_o ##0 irq_id_o == irq; - endsequence : s_irq_taken - - // Interrupt fired, global interrupts enabled, but not taken due to global MSTATUS.MIE setting - property p_irq_masked(irq); - irq_i[irq] ##0 !mie_q[irq] ##0 mstatus_mie; - endproperty : p_irq_masked - - // Interrupt fired and locally enabled in MIE, but masked due to MSTATUS_MIE - property p_irq_masked_mstatus(irq); - irq_i[irq] ##0 mie_q[irq] ##0 !mstatus_mie; - endproperty : p_irq_masked_mstatus - - // Interrupt taken - property p_irq_taken(irq); - s_irq_taken(irq); - endproperty : p_irq_taken - - // Interrupt enabled via MIE locally masked - property p_irq_masked_then_enabled(irq); - irq_i[irq] ##0 !mie_q[irq] ##0 mstatus_mie ##1 irq_i[irq] ##0 mie_q[irq] ##0 mstatus_mie; - endproperty : p_irq_masked_then_enabled - - // Interrupt enabled via MSTATUS_MIE locally masked - property p_irq_masked_mstatus_then_enabled(irq); - irq_i[irq] ##0 mie_q[irq] ##0 !mstatus_mie ##1 irq_i[irq] ##0 mie_q[irq] ##0 mstatus_mie; - endproperty : p_irq_masked_mstatus_then_enabled - - // Interrupt request deasserted when enabled but not acked - property p_irq_deasserted_while_enabled_not_acked(irq); - irq_i[irq] ##0 mie_q[irq] ##0 mstatus_mie ##0 !irq_ack_o ##1 - !irq_i[irq] ##0 !irq_ack_o; - endproperty : p_irq_deasserted_while_enabled_not_acked - - // Interrupt taken in each supported mtvec mode - property p_irq_in_mtvec(irq, mtvec); - s_irq_taken(irq) ##0 mtvec_mode_q == mtvec; - endproperty - generate for(genvar gv_i = 0; gv_i < NUM_IRQ; gv_i++) begin : gen_irq_cov - if (VALID_IRQ_MASK[gv_i]) begin : gen_valid - c_irq_masked: cover property(p_irq_masked(gv_i)); - c_irq_masked_mstatus: cover property(p_irq_masked_mstatus(gv_i)); - c_irq_taken: cover property(p_irq_taken(gv_i)); - c_irq_masked_then_enabled: cover property(p_irq_masked_then_enabled(gv_i)); - c_irq_masked_mstatus_then_enabled: cover property(p_irq_masked_mstatus_then_enabled(gv_i)); - c_irq_deasserted_while_enabled_not_acked: cover property(p_irq_deasserted_while_enabled_not_acked(gv_i)); - c_irq_in_mtvec_fixed: cover property(p_irq_in_mtvec(gv_i, 0)); - c_irq_in_mtvec_vector: cover property(p_irq_in_mtvec(gv_i, 1)); - end - end - endgenerate - - // Detect arbitration of interrupt assertion - always @* begin - next_irq_valid = 1'b0; - next_irq = '0; - casex ({pending_enabled_irq_q[31:16], pending_enabled_irq_q[11], pending_enabled_irq_q[3], pending_enabled_irq_q[7]}) - 19'b1???_????_????_????_???: begin next_irq = 'd31; next_irq_valid = '1; end - 19'b01??_????_????_????_???: begin next_irq = 'd30; next_irq_valid = '1; end - 19'b001?_????_????_????_???: begin next_irq = 'd29; next_irq_valid = '1; end - 19'b0001_????_????_????_???: begin next_irq = 'd28; next_irq_valid = '1; end - 19'b0000_1???_????_????_???: begin next_irq = 'd27; next_irq_valid = '1; end - 19'b0000_01??_????_????_???: begin next_irq = 'd26; next_irq_valid = '1; end - 19'b0000_001?_????_????_???: begin next_irq = 'd25; next_irq_valid = '1; end - 19'b0000_0001_????_????_???: begin next_irq = 'd24; next_irq_valid = '1; end - 19'b0000_0000_1???_????_???: begin next_irq = 'd23; next_irq_valid = '1; end - 19'b0000_0000_01??_????_???: begin next_irq = 'd22; next_irq_valid = '1; end - 19'b0000_0000_001?_????_???: begin next_irq = 'd21; next_irq_valid = '1; end - 19'b0000_0000_0001_????_???: begin next_irq = 'd20; next_irq_valid = '1; end - 19'b0000_0000_0000_1???_???: begin next_irq = 'd19; next_irq_valid = '1; end - 19'b0000_0000_0000_01??_???: begin next_irq = 'd18; next_irq_valid = '1; end - 19'b0000_0000_0000_001?_???: begin next_irq = 'd17; next_irq_valid = '1; end - 19'b0000_0000_0000_0001_???: begin next_irq = 'd16; next_irq_valid = '1; end - 19'b0000_0000_0000_0000_1??: begin next_irq = 'd11; next_irq_valid = '1; end - 19'b0000_0000_0000_0000_01?: begin next_irq = 'd3; next_irq_valid = '1; end - 19'b0000_0000_0000_0000_001: begin next_irq = 'd7; next_irq_valid = '1; end - endcase - end - - always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - irq_q <= 0; - next_irq_q <= 0; - next_irq_valid_q <= 0; - saved_mie_q <= 0; - end - else begin - irq_q <= irq_i; - next_irq_q <= next_irq; - next_irq_valid_q <= next_irq_valid; - saved_mie_q <= mie_q; - end - end - - always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) - expected_irq <= 0; - else - expected_irq <= next_irq_q; - end - - assign expected_irq_ack = next_irq_valid & mstatus_mie; - - // Check expected interrupt wins - property p_irq_arb; - irq_ack_o |-> irq_id_o == next_irq; - endproperty - a_irq_arb: assert property(p_irq_arb) - else - `uvm_error(info_tag, - $sformatf("Expected winning interrupt: %0d, actual interrupt: %0d", next_irq, irq_id_o)) - - // Check that an interrupt is expected - property p_irq_expected; - irq_ack_o |-> expected_irq_ack; - endproperty - a_irq_expected: assert property(p_irq_expected) - else - `uvm_error(info_tag, - $sformatf("Did not expect interrupt ack: %0d", irq_id_o)) - - // --------------------------------------------------------------------------- - // The infamous "first" flag (kludge for $past() handling of t=0 values) - // Would like to use a leading ##1 in the property instead but this currently - // does not work with dsim - // --------------------------------------------------------------------------- - reg first; - always @(posedge clk or negedge rst_ni) - if (!rst_ni) - first <= 1'b1; - else - first <= 1'b0; - - // mip reflects flopped interrupt inputs (irq_i) regardless of other configuration - // Note that this runs on the gated clock - property p_mip_irq_i; - @(posedge clk) - !first |-> mip == ($past(irq_i) & VALID_IRQ_MASK); - endproperty - a_mip_irq_i: assert property(p_mip_irq_i) - else - `uvm_error(info_tag, - $sformatf("MIP of 0x%08x does not follow flopped irq_i input: 0x%08x", mip, $past(irq_i))); - - // mip should not be reserved - property p_mip_not_reserved; - (mip & ~VALID_IRQ_MASK) == 0; - endproperty - a_mip_not_reserved: assert property(p_mip_not_reserved) - else - `uvm_error(info_tag, - $sformatf("MIP of reserved interrupt is asserted: mip = 0x%08x", mip)); - - // --------------------------------------------------------------------------- - // Instruction coverage when taking an interrupt - // --------------------------------------------------------------------------- - always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - last_instr_rdata <= '0; - end - else if (wb_stage_instr_valid_i) begin - last_instr_rdata <= wb_stage_instr_rdata_i; - end - end - - // --------------------------------------------------------------------------- - // WFI Checks - // --------------------------------------------------------------------------- - assign is_wfi = wb_stage_instr_valid_i && - (wb_stage_instr_rdata_i == WFI_INSTR_DATA) && - !branch_taken_ex && - !wb_stage_instr_err_i && - (wb_stage_instr_mpu_status == MPU_OK); - always @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - in_wfi <= 1'b0; - end - else begin - if (is_wfi) - in_wfi <= 1'b1; - else if (|pending_enabled_irq || debug_req_i) - in_wfi <= 1'b0; - end - end - - assign pipeline_ready_for_wfi = (alignbuf_outstanding == 0) && !lsu_busy; - - // WFI assertion will assert core_sleep_o (in WFI_TO_CORE_SLEEP_LATENCY cycles after wb, given ideal conditions) - property p_wfi_assert_core_sleep_o; - !in_wfi - ##1 (in_wfi && !pending_enabled_irq && !debug_mode_q && !debug_req_i)[*(WFI_TO_CORE_SLEEP_LATENCY-1)] - ##1 ( - (in_wfi && !pending_enabled_irq && !debug_mode_q && !debug_req_i) - throughout $past(pipeline_ready_for_wfi)[->1] - ) - |-> - core_sleep_o; - endproperty - a_wfi_assert_core_sleep_o: assert property(p_wfi_assert_core_sleep_o) - else - `uvm_error(info_tag, - $sformatf("Assertion of core_sleep_o did not occur within %0d clocks", WFI_TO_CORE_SLEEP_LATENCY)) - c_wfi_assert_core_sleep_o: cover property(p_wfi_assert_core_sleep_o); - - // WFI assertion will assert core_sleep_o (after required conditions are met) - property p_wfi_assert_core_sleep_o_cond; - !in_wfi - ##1 ( - (in_wfi && !pending_enabled_irq && !debug_mode_q && !debug_req_i) - throughout (##1 ($past(pipeline_ready_for_wfi)[->1]) ) - ) - |-> - core_sleep_o; - endproperty - a_wfi_assert_core_sleep_o_cond: assert property(p_wfi_assert_core_sleep_o_cond) - else - `uvm_error(info_tag, - "Assertion of core_sleep_o did not occur upon its prerequisite conditions") - c_wfi_assert_core_sleep_o_cond: cover property(p_wfi_assert_core_sleep_o_cond); - - // core_sleep_o deassertion in wfi should be followed by WFI deassertion - property p_core_sleep_deassert; - $fell(core_sleep_o) ##0 in_wfi |-> ##1 !in_wfi; - endproperty - a_core_sleep_deassert: assert property(p_core_sleep_deassert) - else - `uvm_error(info_tag, - "Deassertion of core_sleep_o in WFI not followed by WFI wakeup"); - - // When WFI deasserts the core should be awake - property p_wfi_deassert_core_sleep_o; - core_sleep_o ##1 pending_enabled_irq |-> !core_sleep_o; - endproperty - a_wfi_deassert_core_sleep_o: assert property(p_wfi_deassert_core_sleep_o) - else - `uvm_error(info_tag, - "Deassertion of WFI occurred and core is still asleep"); - - // Outside of WFI, the core should not sleep - a_wfi_deny_core_sleep_o: assert property ( - !in_wfi |-> !core_sleep_o - ) else - `uvm_error(info_tag, "Only WFI should trigger core sleep"); - - // WFI wakeup to next instruction fetch/execution - property p_wfi_wake_to_instr_fetch; - disable iff (!rst_ni || !fetch_enable_i || debug_mode_q) - core_sleep_o && in_wfi - ##1 !in_wfi[->1] - |-> - ##[0:WFI_WAKEUP_LATENCY] - ($rose(if_stage_instr_req_o) // IF starts fetching again - || $rose(ex_stage_instr_valid)); // Or continue with prefetched data - endproperty - a_wfi_wake_to_instr_fetch: assert property(p_wfi_wake_to_instr_fetch) - else - `uvm_error(info_tag, - $sformatf("Core did not start fetching %0d cycles after WFI completed", WFI_WAKEUP_LATENCY)); - - // Cover property, detect sleep deassertion due to asserted and non-asserted interrupts - property p_wfi_wake_mstatus_mie(irq, mie); - $fell(in_wfi) ##0 irq_i[irq] ##0 mie_q[irq] ##0 mstatus_mie == mie; - endproperty - - generate for(genvar gv_i = 0; gv_i < 32; gv_i++) begin : gen_wfi_cov - if (VALID_IRQ_MASK[gv_i]) begin - c_wfi_wake_mstatus_mie_0: cover property(p_wfi_wake_mstatus_mie(gv_i, 0)); - c_wfi_wake_mstatus_mie_1: cover property(p_wfi_wake_mstatus_mie(gv_i, 1)); - end - end - endgenerate - -endmodule : uvmt_cv32e40x_interrupt_assert diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_iss_wrap.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_iss_wrap.sv deleted file mode 100644 index f602056017..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_iss_wrap.sv +++ /dev/null @@ -1,71 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// - -`ifndef __UVMT_CV32E40X_ISS_WRAP_SV__ -`define __UVMT_CV32E40X_ISS_WRAP_SV__ - -/** - * Module wrapper for Imperas OVP. - * Instanitates "CPU", the OVP wrapper, and "RAM" a spare memory model. - */ -module uvmt_cv32e40x_iss_wrap - import uvm_pkg::*; - #( - parameter int ROM_START_ADDR = 'h00000000, - parameter int ROM_BYTE_SIZE = 'h0, - parameter int RAM_BYTE_SIZE = 'h1B000000, - parameter int ID = 0 - ) - - ( - input realtime clk_period, - uvma_clknrst_if clknrst_if - ); - - RVVI_bus bus(); - RVVI_io io(); - - MONITOR mon(bus, io); - RAM #( - .ROM_START_ADDR(ROM_START_ADDR), - .ROM_BYTE_SIZE(ROM_BYTE_SIZE), - .RAM_BYTE_SIZE(RAM_BYTE_SIZE)) ram(bus); - - CPU #(.ID(ID), .VARIANT("CV32E40X")) cpu(bus, io); - - bit use_iss = 0; - - assign bus.Clk = clknrst_if.clk; - - initial begin - if ($test$plusargs("USE_ISS")) - use_iss = 1; - end - - initial begin - clknrst_if.clk = 1'b0; - #1; // time for clknrst_if_dut to set the clk_period - wait (clk_period != 0.0); - `uvm_info("OVPWRAP", "Starting OVP clock", UVM_LOW) - clknrst_if.set_period(clk_period); - clknrst_if.start_clk(); - end - -endmodule : uvmt_cv32e40x_iss_wrap - -`endif // __UVMT_CV32E40X_ISS_WRAP_SV__ - diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_macros.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_macros.sv deleted file mode 100644 index 35c6345b7f..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_macros.sv +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - -`ifndef __UVMT_CV32E40X_MACROS_SV__ -`define __UVMT_CV32E40X_MACROS_SV__ - - -// Create bind for RVFI CSR interface -`define RVFI_CSR_BIND(csr_name) \ - bind cv32e40x_wrapper \ - uvma_rvfi_csr_if#(uvme_cv32e40x_pkg::XLEN) rvfi_csr_``csr_name``_if_0_i(.clk(clk_i), \ - .reset_n(rst_ni), \ - .rvfi_csr_rmask(rvfi_i.rvfi_csr_``csr_name``_rmask), \ - .rvfi_csr_wmask(rvfi_i.rvfi_csr_``csr_name``_wmask), \ - .rvfi_csr_rdata(rvfi_i.rvfi_csr_``csr_name``_rdata), \ - .rvfi_csr_wdata(rvfi_i.rvfi_csr_``csr_name``_wdata) \ - ); - -`define RVFI_CSR_IDX_BIND(csr_name,csr_suffix,idx) \ - bind cv32e40x_wrapper \ - uvma_rvfi_csr_if#(uvme_cv32e40x_pkg::XLEN) rvfi_csr_``csr_name````idx````csr_suffix``_if_0_i( \ - .clk(clk_i), \ - .reset_n(rst_ni), \ - .rvfi_csr_rmask(rvfi_i.rvfi_csr_``csr_name````csr_suffix``_rmask[``idx``]), \ - .rvfi_csr_wmask(rvfi_i.rvfi_csr_``csr_name````csr_suffix``_wmask[``idx``]), \ - .rvfi_csr_rdata(rvfi_i.rvfi_csr_``csr_name````csr_suffix``_rdata[``idx``]), \ - .rvfi_csr_wdata(rvfi_i.rvfi_csr_``csr_name````csr_suffix``_wdata[``idx``]) \ - ); - -// Create uvm_config_db::set call for a CSR interface -`define RVFI_CSR_UVM_CONFIG_DB_SET(csr_name) \ - uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \ - .inst_name("*.env.rvfi_agent"), \ - .field_name({"csr_", `"csr_name`", "_vif0"}), \ - .value(dut_wrap.cv32e40x_wrapper_i.rvfi_csr_``csr_name``_if_0_i)); - -`endif // __UVMT_CV32E40X_MACROS_SV__ diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_pkg.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_pkg.sv deleted file mode 100644 index e9d4ca2842..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_pkg.sv +++ /dev/null @@ -1,66 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - -`ifndef __UVMT_CV32E40X_PKG_SV__ -`define __UVMT_CV32E40X_PKG_SV__ - - -// Pre-processor macros -`include "uvm_macros.svh" -`include "uvml_hrtbt_macros.sv" -`include "uvml_logs_macros.sv" -`include "uvmt_cv32e40x_macros.sv" - - - -/** - * Encapsulates all the types and test cases for the verification of an - * CV32E40X RTL design. - */ -package uvmt_cv32e40x_pkg; - - import uvm_pkg::*; - import uvme_cv32e40x_pkg::*; - import uvml_hrtbt_pkg::*; - import uvml_logs_pkg::*; - import uvma_rvvi_ovpsim_pkg::*; - - - // Constants / Parameters / Structs / Enums - `include "uvmt_cv32e40x_constants.sv" - `include "uvmt_cv32e40x_tdefs.sv" - - // Virtual sequence library - // TODO Add virtual sequences - // Ex: `include "uvmt_cv32e40x_sanity_vseq.sv" - `include "uvmt_cv32e40x_vseq_lib.sv" - - // Base test case - `include "uvmt_cv32e40x_test_cfg.sv" - `include "uvmt_cv32e40x_base_test.sv" // all testcases should extend from this testcase - //`include "uvmt_cv32e40x_smoke_test.sv" // smoke test has multile XMRs that are illegal according to the LRM - - // Compilance tests - `include "uvmt_cv32e40x_firmware_test.sv" - -endpackage : uvmt_cv32e40x_pkg - -// All Interfaces used by the CV32E40X TB are here -`include "uvmt_cv32e40x_tb_ifs.sv" - -`endif // __UVMT_CV32E40X_PKG_SV__ diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_rvvi_handcar.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_rvvi_handcar.sv deleted file mode 100644 index 44f392412e..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_rvvi_handcar.sv +++ /dev/null @@ -1,12 +0,0 @@ - -import "DPI-C" initialize_simulator = function void handcar_initialize_simulator(input string options); -import "DPI-C" step_simulator = function int handcar_step_simulator(input int target_id, input int num_steps, input int stx_failed); - -module uvmt_cv32e40x_rvvi_handcar(); - - RVVI_control control_if(); - RVVI_state state_if(); - - initial handcar_initialize_simulator("-p1 -hartids=0"); - -endmodule : uvmt_cv32e40x_rvvi_handcar diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_tb.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_tb.sv deleted file mode 100644 index e3e1a2279e..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_tb.sv +++ /dev/null @@ -1,811 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// - - -`ifndef __UVMT_CV32E40X_TB_SV__ -`define __UVMT_CV32E40X_TB_SV__ - - -/** - * Module encapsulating the CV32E40X DUT wrapper, and associated SV interfaces. - * Also provide UVM environment entry and exit points. - */ -`default_nettype none -module uvmt_cv32e40x_tb; - - import uvm_pkg::*; - import cv32e40x_pkg::*; - import uvmt_cv32e40x_pkg::*; - import uvme_cv32e40x_pkg::*; - - // CORE parameters -`ifdef SET_NUM_MHPMCOUNTERS - parameter int CORE_PARAM_NUM_MHPMCOUNTERS = `SET_NUM_MHPMCOUNTERS; -`else - parameter int CORE_PARAM_NUM_MHPMCOUNTERS = 1; -`endif - // ENV (testbench) parameters - parameter int ENV_PARAM_INSTR_ADDR_WIDTH = 32; - parameter int ENV_PARAM_INSTR_DATA_WIDTH = 32; - parameter int ENV_PARAM_RAM_ADDR_WIDTH = 22; - - // Capture regs for test status from Virtual Peripheral in dut_wrap.mem_i - bit tp; - bit tf; - bit evalid; - bit [31:0] evalue; - - // Agent interfaces - uvma_isacov_if isacov_if(); - uvma_clknrst_if clknrst_if(); // clock and resets from the clknrst agent - uvma_clknrst_if clknrst_if_iss(); - uvma_debug_if debug_if(); - uvma_interrupt_if interrupt_if(); - uvma_obi_memory_if obi_instr_if_i( - .clk(clknrst_if.clk), - .reset_n(clknrst_if.reset_n) - ); - uvma_obi_memory_if obi_data_if_i( - .clk(clknrst_if.clk), - .reset_n(clknrst_if.reset_n) - ); - uvma_fencei_if fencei_if_i( - .clk(clknrst_if.clk), - .reset_n(clknrst_if.reset_n) - ); - - // DUT Wrapper Interfaces - uvmt_cv32e40x_vp_status_if vp_status_if(.tests_passed(), - .tests_failed(), - .exit_valid(), - .exit_value()); // Status information generated by the Virtual Peripherals in the DUT WRAPPER memory. - uvme_cv32e40x_core_cntrl_if core_cntrl_if(); - uvmt_cv32e40x_core_status_if core_status_if(.core_busy(), - .sec_lvl()); // Core status outputs - - /** - * DUT WRAPPER instance: - * This is an update of the riscv_wrapper.sv from PULP-Platform RI5CY project with - * a few mods to bring unused ports from the CORE to this level using SV interfaces. - */ - uvmt_cv32e40x_dut_wrap #( - .NUM_MHPMCOUNTERS (CORE_PARAM_NUM_MHPMCOUNTERS), - .B_EXT (uvmt_cv32e40x_pkg::B_EXT), - .PMA_NUM_REGIONS (uvmt_cv32e40x_pkg::CORE_PARAM_PMA_NUM_REGIONS), - .PMA_CFG (uvmt_cv32e40x_pkg::CORE_PARAM_PMA_CFG), - .INSTR_ADDR_WIDTH (ENV_PARAM_INSTR_ADDR_WIDTH), - .INSTR_RDATA_WIDTH (ENV_PARAM_INSTR_DATA_WIDTH), - .RAM_ADDR_WIDTH (ENV_PARAM_RAM_ADDR_WIDTH) - ) - dut_wrap ( - .clknrst_if(clknrst_if), - .interrupt_if(interrupt_if), - .vp_status_if(vp_status_if), - .core_cntrl_if(core_cntrl_if), - .core_status_if(core_status_if), - .obi_instr_if_i(obi_instr_if_i), - .obi_data_if_i(obi_data_if_i), - .fencei_if_i(fencei_if_i), - .*); - - bind cv32e40x_wrapper - uvma_rvfi_instr_if#(uvme_cv32e40x_pkg::ILEN, - uvme_cv32e40x_pkg::XLEN) rvfi_instr_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - - .rvfi_valid(rvfi_i.rvfi_valid[0]), - .rvfi_order(rvfi_i.rvfi_order[uvma_rvfi_pkg::ORDER_WL*0+:uvma_rvfi_pkg::ORDER_WL]), - .rvfi_insn(rvfi_i.rvfi_insn[uvme_cv32e40x_pkg::ILEN*0+:uvme_cv32e40x_pkg::ILEN]), - .rvfi_trap(rvfi_i.rvfi_trap[11:0]), - .rvfi_halt(rvfi_i.rvfi_halt[0]), - .rvfi_intr(rvfi_i.rvfi_intr[0]), - .rvfi_dbg(rvfi_i.rvfi_dbg), - .rvfi_dbg_mode(rvfi_i.rvfi_dbg_mode), - .rvfi_nmip(rvfi_i.rvfi_nmip), - .rvfi_mode(rvfi_i.rvfi_mode[uvma_rvfi_pkg::MODE_WL*0+:uvma_rvfi_pkg::MODE_WL]), - .rvfi_ixl(rvfi_i.rvfi_ixl[uvma_rvfi_pkg::IXL_WL*0+:uvma_rvfi_pkg::IXL_WL]), - .rvfi_pc_rdata(rvfi_i.rvfi_pc_rdata[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_pc_wdata(rvfi_i.rvfi_pc_wdata[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_rs1_addr(rvfi_i.rvfi_rs1_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rs1_rdata(rvfi_i.rvfi_rs1_rdata[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_rs2_addr(rvfi_i.rvfi_rs2_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rs2_rdata(rvfi_i.rvfi_rs2_rdata[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_rs3_addr('0), - .rvfi_rs3_rdata('0), - .rvfi_rd1_addr(rvfi_i.rvfi_rd_addr[uvma_rvfi_pkg::GPR_ADDR_WL*0+:uvma_rvfi_pkg::GPR_ADDR_WL]), - .rvfi_rd1_wdata(rvfi_i.rvfi_rd_wdata[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_rd2_addr('0), - .rvfi_rd2_wdata('0), - .rvfi_mem_addr(rvfi_i.rvfi_mem_addr[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_mem_rdata(rvfi_i.rvfi_mem_rdata[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_mem_rmask(rvfi_i.rvfi_mem_rmask[uvme_cv32e40x_pkg::XLEN/8*0+:uvme_cv32e40x_pkg::XLEN/8]), - .rvfi_mem_wdata(rvfi_i.rvfi_mem_wdata[uvme_cv32e40x_pkg::XLEN*0+:uvme_cv32e40x_pkg::XLEN]), - .rvfi_mem_wmask(rvfi_i.rvfi_mem_wmask[uvme_cv32e40x_pkg::XLEN/8*0+:uvme_cv32e40x_pkg::XLEN/8]) - ); - - // RVFI CSR binds - `RVFI_CSR_BIND(marchid) - `RVFI_CSR_BIND(mcountinhibit) - `RVFI_CSR_BIND(mstatus) - `RVFI_CSR_BIND(mstatush) - `RVFI_CSR_BIND(mvendorid) - `RVFI_CSR_BIND(misa) - `RVFI_CSR_BIND(mtvec) - `RVFI_CSR_BIND(mtval) - `RVFI_CSR_BIND(mscratch) - `RVFI_CSR_BIND(mepc) - `RVFI_CSR_BIND(mcause) - `RVFI_CSR_BIND(mip) - `RVFI_CSR_BIND(mie) - `RVFI_CSR_BIND(mhartid) - `RVFI_CSR_BIND(mcontext) - `RVFI_CSR_BIND(scontext) - `RVFI_CSR_BIND(mimpid) - `RVFI_CSR_BIND(minstret) - `RVFI_CSR_BIND(minstreth) - `RVFI_CSR_BIND(mcycle) - `RVFI_CSR_BIND(mcycleh) - - `RVFI_CSR_BIND(dcsr) - `RVFI_CSR_BIND(dpc) - `RVFI_CSR_BIND(tselect) - `RVFI_CSR_BIND(tinfo) - `RVFI_CSR_BIND(tcontrol) - - `RVFI_CSR_IDX_BIND(mhpmcounter,,3) - `RVFI_CSR_IDX_BIND(mhpmcounter,,4) - `RVFI_CSR_IDX_BIND(mhpmcounter,,5) - `RVFI_CSR_IDX_BIND(mhpmcounter,,6) - `RVFI_CSR_IDX_BIND(mhpmcounter,,7) - `RVFI_CSR_IDX_BIND(mhpmcounter,,8) - `RVFI_CSR_IDX_BIND(mhpmcounter,,9) - `RVFI_CSR_IDX_BIND(mhpmcounter,,10) - `RVFI_CSR_IDX_BIND(mhpmcounter,,11) - `RVFI_CSR_IDX_BIND(mhpmcounter,,12) - `RVFI_CSR_IDX_BIND(mhpmcounter,,13) - `RVFI_CSR_IDX_BIND(mhpmcounter,,14) - `RVFI_CSR_IDX_BIND(mhpmcounter,,15) - `RVFI_CSR_IDX_BIND(mhpmcounter,,16) - `RVFI_CSR_IDX_BIND(mhpmcounter,,17) - `RVFI_CSR_IDX_BIND(mhpmcounter,,18) - `RVFI_CSR_IDX_BIND(mhpmcounter,,19) - `RVFI_CSR_IDX_BIND(mhpmcounter,,20) - `RVFI_CSR_IDX_BIND(mhpmcounter,,21) - `RVFI_CSR_IDX_BIND(mhpmcounter,,22) - `RVFI_CSR_IDX_BIND(mhpmcounter,,23) - `RVFI_CSR_IDX_BIND(mhpmcounter,,24) - `RVFI_CSR_IDX_BIND(mhpmcounter,,25) - `RVFI_CSR_IDX_BIND(mhpmcounter,,26) - `RVFI_CSR_IDX_BIND(mhpmcounter,,27) - `RVFI_CSR_IDX_BIND(mhpmcounter,,28) - `RVFI_CSR_IDX_BIND(mhpmcounter,,29) - `RVFI_CSR_IDX_BIND(mhpmcounter,,30) - `RVFI_CSR_IDX_BIND(mhpmcounter,,31) - - `RVFI_CSR_IDX_BIND(mhpmevent,,3) - `RVFI_CSR_IDX_BIND(mhpmevent,,4) - `RVFI_CSR_IDX_BIND(mhpmevent,,5) - `RVFI_CSR_IDX_BIND(mhpmevent,,6) - `RVFI_CSR_IDX_BIND(mhpmevent,,7) - `RVFI_CSR_IDX_BIND(mhpmevent,,8) - `RVFI_CSR_IDX_BIND(mhpmevent,,9) - `RVFI_CSR_IDX_BIND(mhpmevent,,10) - `RVFI_CSR_IDX_BIND(mhpmevent,,11) - `RVFI_CSR_IDX_BIND(mhpmevent,,12) - `RVFI_CSR_IDX_BIND(mhpmevent,,13) - `RVFI_CSR_IDX_BIND(mhpmevent,,14) - `RVFI_CSR_IDX_BIND(mhpmevent,,15) - `RVFI_CSR_IDX_BIND(mhpmevent,,16) - `RVFI_CSR_IDX_BIND(mhpmevent,,17) - `RVFI_CSR_IDX_BIND(mhpmevent,,18) - `RVFI_CSR_IDX_BIND(mhpmevent,,19) - `RVFI_CSR_IDX_BIND(mhpmevent,,20) - `RVFI_CSR_IDX_BIND(mhpmevent,,21) - `RVFI_CSR_IDX_BIND(mhpmevent,,22) - `RVFI_CSR_IDX_BIND(mhpmevent,,23) - `RVFI_CSR_IDX_BIND(mhpmevent,,24) - `RVFI_CSR_IDX_BIND(mhpmevent,,25) - `RVFI_CSR_IDX_BIND(mhpmevent,,26) - `RVFI_CSR_IDX_BIND(mhpmevent,,27) - `RVFI_CSR_IDX_BIND(mhpmevent,,28) - `RVFI_CSR_IDX_BIND(mhpmevent,,29) - `RVFI_CSR_IDX_BIND(mhpmevent,,30) - `RVFI_CSR_IDX_BIND(mhpmevent,,31) - - `RVFI_CSR_IDX_BIND(mhpmcounter,h,3) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,4) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,5) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,6) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,7) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,8) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,9) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,10) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,11) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,12) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,13) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,14) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,15) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,16) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,17) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,18) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,19) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,20) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,21) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,22) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,23) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,24) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,25) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,26) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,27) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,28) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,29) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,30) - `RVFI_CSR_IDX_BIND(mhpmcounter,h,31) - - `RVFI_CSR_BIND(mconfigptr) - - - // dscratch0 - bind cv32e40x_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40x_pkg::XLEN) rvfi_csr_dscratch0_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_dscratch_rmask[0]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_dscratch_wmask[0]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_dscratch_rdata[0]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_dscratch_wdata[0]) - ); - - // dscratch1 - bind cv32e40x_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40x_pkg::XLEN) rvfi_csr_dscratch1_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_dscratch_rmask[1]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_dscratch_wmask[1]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_dscratch_rdata[1]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_dscratch_wdata[1]) - ); - - // tdata1 - bind cv32e40x_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40x_pkg::XLEN) rvfi_csr_tdata1_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[1]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[1]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[1]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[1]) - ); - - // tdata2 - bind cv32e40x_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40x_pkg::XLEN) rvfi_csr_tdata2_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[2]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[2]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[2]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[2]) - ); - - // tdata3 - bind cv32e40x_wrapper - uvma_rvfi_csr_if#(uvme_cv32e40x_pkg::XLEN) rvfi_csr_tdata3_if_0_i(.clk(clk_i), - .reset_n(rst_ni), - .rvfi_csr_rmask(rvfi_i.rvfi_csr_tdata_rmask[3]), - .rvfi_csr_wmask(rvfi_i.rvfi_csr_tdata_wmask[3]), - .rvfi_csr_rdata(rvfi_i.rvfi_csr_tdata_rdata[3]), - .rvfi_csr_wdata(rvfi_i.rvfi_csr_tdata_wdata[3]) - ); - - bind uvmt_cv32e40x_dut_wrap - uvma_obi_memory_assert_if_wrp#( - .ADDR_WIDTH(32), - .DATA_WIDTH(32), - .AUSER_WIDTH(0), - .WUSER_WIDTH(0), - .RUSER_WIDTH(0), - .ID_WIDTH(0), - .ACHK_WIDTH(0), - .RCHK_WIDTH(0), - .IS_1P2(1) - ) obi_instr_memory_assert_i(.obi(obi_instr_if_i)); - - bind uvmt_cv32e40x_dut_wrap - uvma_obi_memory_assert_if_wrp#( - .ADDR_WIDTH(32), - .DATA_WIDTH(32), - .AUSER_WIDTH(0), - .WUSER_WIDTH(0), - .RUSER_WIDTH(0), - .ID_WIDTH(0), - .ACHK_WIDTH(0), - .RCHK_WIDTH(0), - .IS_1P2(1) - ) obi_data_memory_assert_i(.obi(obi_data_if_i)); - - // Bind in verification modules to the design - bind cv32e40x_core - uvmt_cv32e40x_interrupt_assert interrupt_assert_i( - .mcause_n ({cs_registers_i.mcause_n.irq, cs_registers_i.mcause_n.exception_code[4:0]}), - .mip (cs_registers_i.mip), - .mie_q (cs_registers_i.mie_q), - .mstatus_mie (cs_registers_i.mstatus_q.mie), - .mtvec_mode_q (cs_registers_i.mtvec_q.mode), - - .if_stage_instr_req_o (if_stage_i.m_c_obi_instr_if.s_req.req), - .if_stage_instr_rvalid_i (if_stage_i.m_c_obi_instr_if.s_rvalid.rvalid), - .if_stage_instr_rdata_i (if_stage_i.m_c_obi_instr_if.resp_payload.rdata), - .alignbuf_outstanding (if_stage_i.prefetch_unit_i.alignment_buffer_i.outstanding_cnt_q), - - .ex_stage_instr_valid (ex_stage_i.id_ex_pipe_i.instr_valid), - - .wb_stage_instr_valid_i (wb_stage_i.instr_valid), - .wb_stage_instr_rdata_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.rdata), - .wb_stage_instr_err_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.err), - .wb_stage_instr_mpu_status (wb_stage_i.ex_wb_pipe_i.instr.mpu_status), - - .branch_taken_ex (controller_i.controller_fsm_i.branch_taken_ex), - .debug_mode_q (controller_i.controller_fsm_i.debug_mode_q), - - .irq_ack_o (core_i.irq_ack), - .irq_id_o (core_i.irq_id), - - .* - ); - - // Fence.i assertions - - bind cv32e40x_wrapper - uvmt_cv32e40x_fencei_assert #( - .PMA_NUM_REGIONS (uvmt_cv32e40x_pkg::CORE_PARAM_PMA_NUM_REGIONS), - .PMA_CFG (uvmt_cv32e40x_pkg::CORE_PARAM_PMA_CFG) - ) fencei_assert_i ( - .wb_valid (core_i.wb_stage_i.wb_valid), - .wb_instr_valid (core_i.ex_wb_pipe.instr_valid), - .wb_sys_en (core_i.ex_wb_pipe.sys_en), - .wb_sys_fencei_insn (core_i.ex_wb_pipe.sys_fencei_insn), - .wb_pc (core_i.ex_wb_pipe.pc), - .wb_rdata (core_i.ex_wb_pipe.instr.bus_resp.rdata), - .wb_buffer_state (core_i.load_store_unit_i.write_buffer_i.state), - - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_intr (rvfi_i.rvfi_intr), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - - .* - ); - - - // Core integration assertions - - bind cv32e40x_wrapper - uvmt_cv32e40x_integration_assert integration_assert_i (.*); - - - // Debug assertion and coverage interface - - // Instantiate debug assertions - - bind cv32e40x_wrapper - uvmt_cv32e40x_debug_cov_assert_if debug_cov_assert_if ( - .id_valid (core_i.id_stage_i.id_valid_o), - .sys_fence_insn_i (core_i.id_stage_i.decoder_i.sys_fencei_insn_o), - - .ex_stage_csr_en (core_i.id_ex_pipe.csr_en), - .ex_valid (core_i.ex_stage_i.instr_valid), - .ex_stage_instr_rdata_i (core_i.id_ex_pipe.instr.bus_resp.rdata), - .ex_stage_pc (core_i.id_ex_pipe.pc), - - .wb_stage_instr_rdata_i (core_i.ex_wb_pipe.instr.bus_resp.rdata), - .wb_stage_instr_valid_i (core_i.ex_wb_pipe.instr_valid), - .wb_stage_pc (core_i.wb_stage_i.ex_wb_pipe_i.pc), - .wb_err (core_i.ex_wb_pipe.instr.bus_resp.err), - .wb_illegal (core_i.ex_wb_pipe.illegal_insn), - .wb_valid (core_i.wb_stage_i.wb_valid_o), - .wb_mpu_status (core_i.ex_wb_pipe.instr.mpu_status), - .illegal_insn_i (core_i.ex_wb_pipe.illegal_insn), - .sys_en_i (core_i.ex_wb_pipe.sys_en), - .sys_ecall_insn_i (core_i.ex_wb_pipe.sys_ecall_insn), - - .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), - .debug_req_i (core_i.controller_i.controller_fsm_i.debug_req_i), - .debug_havereset (core_i.debug_havereset_o), - .debug_running (core_i.debug_running_o), - .debug_halted (core_i.debug_halted_o), - - .debug_req_q (core_i.controller_i.controller_fsm_i.debug_req_q), - .pending_debug (core_i.controller_i.controller_fsm_i.pending_debug), - .pending_nmi (core_i.controller_i.controller_fsm_i.pending_nmi), - .nmi_allowed (core_i.controller_i.controller_fsm_i.nmi_allowed), - .debug_mode_q (core_i.controller_i.controller_fsm_i.debug_mode_q), - .trigger_match_in_wb (core_i.controller_i.controller_fsm_i.trigger_match_in_wb), - .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), - - .mie_q (core_i.cs_registers_i.mie_q), - .dcsr_q (core_i.cs_registers_i.dcsr_q), - .depc_q (core_i.cs_registers_i.dpc_q), - .depc_n (core_i.cs_registers_i.dpc_n), - .mcause_q (core_i.cs_registers_i.mcause_q), - .mtvec (core_i.cs_registers_i.mtvec_q), - .mepc_q (core_i.cs_registers_i.mepc_q), - .tdata1 (core_i.cs_registers_i.tmatch_control_q), - .tdata2 (core_i.cs_registers_i.tmatch_value_q), - .mcountinhibit_q (core_i.cs_registers_i.mcountinhibit_q), - .mcycle (core_i.cs_registers_i.mhpmcounter_q[0]), - .minstret (core_i.cs_registers_i.mhpmcounter_q[2]), - .csr_we_int (core_i.cs_registers_i.csr_we_int), - - // TODO: review this change from CV32E40X_HASH f6196bf to a26b194. It should be logically equivalent. - //assign debug_cov_assert_if.inst_ret = core_i.cs_registers_i.inst_ret; - // First attempt: this causes unexpected failures of a_minstret_count - //assign debug_cov_assert_if.inst_ret = (core_i.id_valid & - // core_i.is_decoding); - // Second attempt: (based on OK input). This passes, but maybe only because p_minstret_count - // is the only property sensitive to inst_ret. Will - // this work in the general case? - .inst_ret (core_i.ctrl_fsm.mhpmevent.minstret), - .csr_access (core_i.ex_wb_pipe.csr_en), - .csr_op (core_i.ex_wb_pipe.csr_op), - .csr_addr (core_i.ex_wb_pipe.csr_addr), - .irq_ack_o (core_i.irq_ack), - .irq_id_o (core_i.irq_id), - .dm_halt_addr_i (core_i.dm_halt_addr_i), - .dm_exception_addr_i (core_i.dm_exception_addr_i), - .nmi_addr_i (core_i.nmi_addr_i), - .core_sleep_o (core_i.core_sleep_o), - .irq_i (core_i.irq_i), - .pc_set (core_i.ctrl_fsm.pc_set), - .boot_addr_i (core_i.boot_addr_i), - - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_insn (rvfi_i.rvfi_insn), - .rvfi_intr (rvfi_i.rvfi_intr), - .rvfi_dbg (rvfi_i.rvfi_dbg), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - .rvfi_pc_wdata (rvfi_i.rvfi_pc_wdata), - .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), - .rvfi_csr_dpc_rdata (rvfi_i.rvfi_csr_dpc_rdata), - .rvfi_csr_mepc_wdata (rvfi_i.rvfi_csr_mepc_wdata), - .rvfi_csr_mepc_wmask (rvfi_i.rvfi_csr_mepc_wmask), - - .is_wfi (), - .in_wfi (), - .dpc_will_hit (), - .addr_match (), - .is_ebreak (), - .is_cebreak (), - .is_dret (), - .is_mulhsu (), - .pending_enabled_irq (), - - .* - ); - - bind cv32e40x_wrapper uvmt_cv32e40x_debug_assert u_debug_assert(.cov_assert_if(debug_cov_assert_if)); - - //uvmt_cv32e40x_rvvi_handcar u_rvvi_handcar(); - /** - * ISS WRAPPER instance: - */ - uvmt_cv32e40x_iss_wrap #( - .ID (0), - .ROM_START_ADDR('h0), - .ROM_BYTE_SIZE('h0), - .RAM_BYTE_SIZE('h1_0000_0000) - ) - iss_wrap ( .clk_period(clknrst_if.clk_period), - .clknrst_if(clknrst_if_iss) - ); - - assign clknrst_if_iss.reset_n = clknrst_if.reset_n; - - /** - * Test bench entry point. - */ - initial begin : test_bench_entry_point - - // Specify time format for simulation (units_number, precision_number, suffix_string, minimum_field_width) - $timeformat(-9, 3, " ns", 8); - - // Add interfaces handles to uvm_config_db - uvm_config_db#(virtual uvma_isacov_if )::set(.cntxt(null), .inst_name("*.env.isacov_agent"), .field_name("vif"), .value(isacov_if)); - uvm_config_db#(virtual uvma_debug_if )::set(.cntxt(null), .inst_name("*.env.debug_agent"), .field_name("vif"), .value(debug_if)); - uvm_config_db#(virtual uvma_clknrst_if )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"), .value(clknrst_if)); - uvm_config_db#(virtual uvma_interrupt_if )::set(.cntxt(null), .inst_name("*.env.interrupt_agent"), .field_name("vif"), .value(interrupt_if)); - uvm_config_db#(virtual uvma_obi_memory_if )::set(.cntxt(null), .inst_name("*.env.obi_memory_instr_agent"), .field_name("vif"), .value(obi_instr_if_i) ); - uvm_config_db#(virtual uvma_obi_memory_if )::set(.cntxt(null), .inst_name("*.env.obi_memory_data_agent"), .field_name("vif"), .value(obi_data_if_i) ); - uvm_config_db#(virtual uvma_fencei_if )::set(.cntxt(null), .inst_name("*.env.fencei"), .field_name("vif"), .value(fencei_if_i)); - uvm_config_db#(virtual uvma_rvfi_instr_if )::set(.cntxt(null), .inst_name("*.env.rvfi_agent"), .field_name("instr_vif0"),.value(dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i)); - uvm_config_db#(virtual uvma_fencei_if )::set(.cntxt(null), .inst_name("*.env.fencei_agent"), .field_name("fencei_vif"), .value(fencei_if_i) ); - uvm_config_db#(virtual uvmt_cv32e40x_vp_status_if )::set(.cntxt(null), .inst_name("*"), .field_name("vp_status_vif"), .value(vp_status_if) ); - uvm_config_db#(virtual uvma_interrupt_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("intr_vif"), .value(interrupt_if) ); - uvm_config_db#(virtual uvma_debug_if )::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_vif"), .value(debug_if) ); -// uvm_config_db#(virtual uvmt_cv32e40x_debug_cov_assert_if)::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"), .value(debug_cov_assert_if)); - `RVFI_CSR_UVM_CONFIG_DB_SET(marchid) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcountinhibit) - `RVFI_CSR_UVM_CONFIG_DB_SET(mstatus) - `RVFI_CSR_UVM_CONFIG_DB_SET(mstatush) - `RVFI_CSR_UVM_CONFIG_DB_SET(misa) - `RVFI_CSR_UVM_CONFIG_DB_SET(mtvec) - `RVFI_CSR_UVM_CONFIG_DB_SET(mtval) - `RVFI_CSR_UVM_CONFIG_DB_SET(mvendorid) - `RVFI_CSR_UVM_CONFIG_DB_SET(mscratch) - `RVFI_CSR_UVM_CONFIG_DB_SET(mepc) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcause) - `RVFI_CSR_UVM_CONFIG_DB_SET(mip) - `RVFI_CSR_UVM_CONFIG_DB_SET(mie) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhartid) - `RVFI_CSR_UVM_CONFIG_DB_SET(mimpid) - `RVFI_CSR_UVM_CONFIG_DB_SET(minstret) - `RVFI_CSR_UVM_CONFIG_DB_SET(minstreth) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcontext) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcycle) - `RVFI_CSR_UVM_CONFIG_DB_SET(mcycleh) - - `RVFI_CSR_UVM_CONFIG_DB_SET(dcsr) - `RVFI_CSR_UVM_CONFIG_DB_SET(dpc) - `RVFI_CSR_UVM_CONFIG_DB_SET(dscratch0) - `RVFI_CSR_UVM_CONFIG_DB_SET(dscratch1) - `RVFI_CSR_UVM_CONFIG_DB_SET(scontext) - `RVFI_CSR_UVM_CONFIG_DB_SET(tselect) - `RVFI_CSR_UVM_CONFIG_DB_SET(tdata1) - `RVFI_CSR_UVM_CONFIG_DB_SET(tdata2) - `RVFI_CSR_UVM_CONFIG_DB_SET(tdata3) - `RVFI_CSR_UVM_CONFIG_DB_SET(tinfo) - `RVFI_CSR_UVM_CONFIG_DB_SET(tcontrol) - - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent3) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent4) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent5) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent6) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent7) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent8) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent9) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent10) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent11) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent12) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent13) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent14) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent15) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent16) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent17) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent18) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent19) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent20) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent21) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent22) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent23) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent24) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent25) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent26) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent27) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent28) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent29) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent30) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmevent31) - - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter3) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter4) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter5) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter6) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter7) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter8) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter9) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter10) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter11) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter12) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter13) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter14) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter15) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter16) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter17) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter18) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter19) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter20) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter21) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter22) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter23) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter24) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter25) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter26) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter27) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter28) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter29) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter30) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter31) - - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter3h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter4h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter5h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter6h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter7h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter8h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter9h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter10h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter11h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter12h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter13h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter14h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter15h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter16h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter17h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter18h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter19h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter20h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter21h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter22h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter23h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter24h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter25h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter26h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter27h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter28h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter29h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter30h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mhpmcounter31h) - `RVFI_CSR_UVM_CONFIG_DB_SET(mconfigptr) - - uvm_config_db#(virtual RVVI_state#(.ILEN(uvme_cv32e40x_pkg::ILEN), - .XLEN(uvme_cv32e40x_pkg::XLEN) - ))::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("state_vif"), .value(iss_wrap.cpu.state)); - uvm_config_db#(virtual RVVI_control )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("control_vif"), .value(iss_wrap.cpu.control)); - uvm_config_db#(virtual RVVI_bus )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("ovpsim_bus_vif"), .value(iss_wrap.bus)); - uvm_config_db#(virtual RVVI_io )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("ovpsim_io_vif"), .value(iss_wrap.io)); - uvm_config_db#(virtual RVVI_memory )::set(.cntxt(null), .inst_name("*.env.rvvi_agent"), .field_name("ovpsim_mem_vif"), .value(iss_wrap.ram.memory)); - uvm_config_db#(virtual uvmt_cv32e40x_vp_status_if )::set(.cntxt(null), .inst_name("*"), .field_name("vp_status_vif"), .value(vp_status_if) ); - uvm_config_db#(virtual uvme_cv32e40x_core_cntrl_if )::set(.cntxt(null), .inst_name("*"), .field_name("core_cntrl_vif"), .value(core_cntrl_if) ); - uvm_config_db#(virtual uvmt_cv32e40x_core_status_if )::set(.cntxt(null), .inst_name("*"), .field_name("core_status_vif"), .value(core_status_if) ); - uvm_config_db#(virtual uvmt_cv32e40x_debug_cov_assert_if)::set(.cntxt(null), .inst_name("*.env"), .field_name("debug_cov_vif"),.value(dut_wrap.cv32e40x_wrapper_i.debug_cov_assert_if)); - - // Make the DUT Wrapper Virtual Peripheral's status outputs available to the base_test - uvm_config_db#(bit )::set(.cntxt(null), .inst_name("*"), .field_name("tp"), .value(1'b0) ); - uvm_config_db#(bit )::set(.cntxt(null), .inst_name("*"), .field_name("tf"), .value(1'b0) ); - uvm_config_db#(bit )::set(.cntxt(null), .inst_name("*"), .field_name("evalid"), .value(1'b0) ); - uvm_config_db#(bit[31:0])::set(.cntxt(null), .inst_name("*"), .field_name("evalue"), .value(32'h00000000)); - - // DUT and ENV parameters - uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("CORE_PARAM_NUM_MHPMCOUNTERS"), .value(CORE_PARAM_NUM_MHPMCOUNTERS)); - uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_ADDR_WIDTH"), .value(ENV_PARAM_INSTR_ADDR_WIDTH) ); - uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_DATA_WIDTH"), .value(ENV_PARAM_INSTR_DATA_WIDTH) ); - uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_RAM_ADDR_WIDTH"), .value(ENV_PARAM_RAM_ADDR_WIDTH) ); - - // Run test - uvm_top.enable_print_topology = 0; // ENV coders enable this as a debug aid - uvm_top.finish_on_completion = 1; - uvm_top.run_test(); - end : test_bench_entry_point - - assign core_cntrl_if.clk = clknrst_if.clk; - - // Informational print message on loading of OVPSIM ISS to benchmark some elf image loading times - // OVPSIM runs its initialization at the #1ns timestamp, and should dominate the initial startup time - longint start_ovpsim_init_time; - longint end_ovpsim_init_time; - initial begin - if (!$test$plusargs("DISABLE_OVPSIM")) begin - #0.9ns; - `uvm_info("OVPSIM", $sformatf("Start benchmarking OVPSIM initialization"), UVM_LOW) - start_ovpsim_init_time = svlib_pkg::sys_dayTime(); - #1.1ns; - end_ovpsim_init_time = svlib_pkg::sys_dayTime(); - `uvm_info("OVPSIM", $sformatf("Initialization time: %0d seconds", end_ovpsim_init_time - start_ovpsim_init_time), UVM_LOW) - end - end - - //TODO verify these are correct with regards to isacov function - always @(dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_valid) -> isacov_if.retire; - assign isacov_if.instr = dut_wrap.cv32e40x_wrapper_i.rvfi_instr_if_0_i.rvfi_insn; - //assign isacov_if.is_compressed = dut_wrap.cv32e40x_wrapper_i.tracer_i.insn_compressed; - - // Capture the test status and exit pulse flags - // TODO: put this logic in the vp_status_if (makes it easier to pass to ENV) - always @(posedge clknrst_if.clk) begin - if (!clknrst_if.reset_n) begin - tp <= 1'b0; - tf <= 1'b0; - evalid <= 1'b0; - evalue <= 32'h00000000; - end - else begin - if (vp_status_if.tests_passed) begin - tp <= 1'b1; - uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("tp"), .value(1'b1)); - end - if (vp_status_if.tests_failed) begin - tf <= 1'b1; - uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("tf"), .value(1'b1)); - end - if (vp_status_if.exit_valid) begin - evalid <= 1'b1; - uvm_config_db#(bit)::set(.cntxt(null), .inst_name("*"), .field_name("evalid"), .value(1'b1)); - end - if (vp_status_if.exit_valid) begin - evalue <= vp_status_if.exit_value; - uvm_config_db#(bit[31:0])::set(.cntxt(null), .inst_name("*"), .field_name("evalue"), .value(vp_status_if.exit_value)); - end - end - end - - - /** - * End-of-test summary printout. - */ - final begin: end_of_test - string summary_string; - uvm_report_server rs; - int err_count; - int warning_count; - int fatal_count; - static bit sim_finished = 0; - - static string red = "\033[31m\033[1m"; - static string green = "\033[32m\033[1m"; - static string reset = "\033[0m"; - - rs = uvm_top.get_report_server(); - err_count = rs.get_severity_count(UVM_ERROR); - warning_count = rs.get_severity_count(UVM_WARNING); - fatal_count = rs.get_severity_count(UVM_FATAL); - - void'(uvm_config_db#(bit)::get(null, "", "sim_finished", sim_finished)); - - $display("\n%m: *** Test Summary ***\n"); - - if (sim_finished && (err_count == 0) && (fatal_count == 0)) begin - $display(" PPPPPPP AAAAAA SSSSSS SSSSSS EEEEEEEE DDDDDDD "); - $display(" PP PP AA AA SS SS SS SS EE DD DD "); - $display(" PP PP AA AA SS SS EE DD DD "); - $display(" PPPPPPP AAAAAAAA SSSSSS SSSSSS EEEEE DD DD "); - $display(" PP AA AA SS SS EE DD DD "); - $display(" PP AA AA SS SS SS SS EE DD DD "); - $display(" PP AA AA SSSSSS SSSSSS EEEEEEEE DDDDDDD "); - $display(" ----------------------------------------------------------"); - if (warning_count == 0) begin - $display(" SIMULATION PASSED "); - end - else begin - $display(" SIMULATION PASSED with WARNINGS "); - end - $display(" ----------------------------------------------------------"); - end - else begin - $display(" FFFFFFFF AAAAAA IIIIII LL EEEEEEEE DDDDDDD "); - $display(" FF AA AA II LL EE DD DD "); - $display(" FF AA AA II LL EE DD DD "); - $display(" FFFFF AAAAAAAA II LL EEEEE DD DD "); - $display(" FF AA AA II LL EE DD DD "); - $display(" FF AA AA II LL EE DD DD "); - $display(" FF AA AA IIIIII LLLLLLLL EEEEEEEE DDDDDDD "); - - if (sim_finished == 0) begin - $display(" --------------------------------------------------------"); - $display(" SIMULATION FAILED - ABORTED "); - $display(" --------------------------------------------------------"); - end - else begin - $display(" --------------------------------------------------------"); - $display(" SIMULATION FAILED "); - $display(" --------------------------------------------------------"); - end - end - end - -endmodule : uvmt_cv32e40x_tb -`default_nettype wire - -`endif // __UVMT_CV32E40X_TB_SV__ diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_tb_ifs.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_tb_ifs.sv deleted file mode 100644 index a9c422c8e3..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_tb_ifs.sv +++ /dev/null @@ -1,267 +0,0 @@ - -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - - -// This file specifies all interfaces used by the CV32E40X test bench (uvmt_cv32e40x_tb). -// Most interfaces support tasks to allow control by the ENV or test cases. - -`ifndef __UVMT_CV32E40X_TB_IFS_SV__ -`define __UVMT_CV32E40X_TB_IFS_SV__ - - -/** - * clocks and reset - */ -interface uvmt_cv32e40x_clk_gen_if (output logic core_clock, output logic core_reset_n); - - import uvm_pkg::*; - - bit start_clk = 0; - // TODO: get the uvme_cv32e40x_* values from random ENV CFG members. - realtime core_clock_period = 1500ps; // uvme_cv32e40x_clk_period * 1ps; - realtime reset_deassert_duration = 7400ps; // uvme_cv32e40x_reset_deassert_duarion * 1ps; - realtime reset_assert_duration = 7400ps; // uvme_cv32e40x_reset_assert_duarion * 1ps; - - /** - * Generates clock and reset signals. - * If reset_n comes up de-asserted (1'b1), wait a bit, then assert, then de-assert - * Otherwise, leave reset asserted, wait a bit, then de-assert. - */ - initial begin - core_clock = 0; // uvme_cv32e40x_clk_initial_value; - core_reset_n = 0; // uvme_cv32e40x_reset_initial_value; - wait (start_clk); - fork - forever begin - #(core_clock_period/2) core_clock = ~core_clock; - end - begin - if (core_reset_n == 1'b1) #(reset_deassert_duration); - core_reset_n = 1'b0; - #(reset_assert_duration); - core_reset_n = 1'b1; - end - join_none - end - - /** - * Sets clock period in ps. - */ - function void set_clk_period ( real clk_period ); - core_clock_period = clk_period * 1ps; - endfunction : set_clk_period - - /** Triggers the generation of clk. */ - function void start(); - start_clk = 1; - `uvm_info("CLK_GEN_IF", "uvmt_cv32e40x_clk_gen_if.start() called", UVM_NONE) - endfunction : start - -endinterface : uvmt_cv32e40x_clk_gen_if - -/** - * Status information generated by the Virtual Peripherals in the DUT WRAPPER memory. - */ -interface uvmt_cv32e40x_vp_status_if ( - output bit tests_passed, - output bit tests_failed, - output bit exit_valid, - output bit [31:0] exit_value - ); - - import uvm_pkg::*; - - // TODO: X/Z checks - initial begin - end - -endinterface : uvmt_cv32e40x_vp_status_if - - - -/** - * Core status signals. - */ -interface uvmt_cv32e40x_core_status_if ( - input wire core_busy, - input logic sec_lvl - ); - - import uvm_pkg::*; - -endinterface : uvmt_cv32e40x_core_status_if - -// Interface to debug assertions and covergroups -interface uvmt_cv32e40x_debug_cov_assert_if - import cv32e40x_pkg::*; - ( - input clk_i, - input rst_ni, - - // External interrupt interface - input [31:0] irq_i, - input irq_ack_o, - input [4:0] irq_id_o, - input [31:0] mie_q, - - input ex_stage_csr_en, - input ex_valid, - input [31:0] ex_stage_instr_rdata_i, - input [31:0] ex_stage_pc, - - input wb_stage_instr_valid_i, - input [31:0] wb_stage_instr_rdata_i, - input [31:0] wb_stage_pc, // Program counter in writeback - input wb_illegal, - input wb_valid, - input wb_err, - input mpu_status_e wb_mpu_status, - - input id_valid, - input wire ctrl_state_e ctrl_fsm_cs, // Controller FSM states with debug_req - input illegal_insn_i, - input sys_en_i, - input sys_ecall_insn_i, - - // Core signals - input [31:0] boot_addr_i, - input [31:0] nmi_addr_i, - input fetch_enable_i, - - input rvfi_valid, - input [31:0] rvfi_insn, - input rvfi_intr, - input [2:0] rvfi_dbg, - input rvfi_dbg_mode, - input [31:0] rvfi_pc_wdata, - input [31:0] rvfi_pc_rdata, - input [31:0] rvfi_csr_dpc_rdata, - input [31:0] rvfi_csr_mepc_wdata, - input [31:0] rvfi_csr_mepc_wmask, - - // Debug signals - input debug_req_i, // From controller - input debug_req_q, // From controller - input debug_havereset, - input debug_running, - input debug_halted, - - input pending_debug, // From controller - input pending_nmi, // From controller - input nmi_allowed, // From controller - input debug_mode_q, // From controller - input [31:0] dcsr_q, // From controller - input [31:0] depc_q, // From cs regs //TODO:ropeders rename "dpc_q" - input [31:0] depc_n, - input [31:0] dm_halt_addr_i, - input [31:0] dm_exception_addr_i, - - input [31:0] mcause_q, - input [31:0] mtvec, - input [31:0] mepc_q, - input [31:0] tdata1, - input [31:0] tdata2, - input trigger_match_in_wb, - - // Counter related input from cs_registers - input [31:0] mcountinhibit_q, - input [63:0] mcycle, - input [63:0] minstret, - input inst_ret, - - // WFI Interface - input core_sleep_o, - - input sys_fence_insn_i, - - input csr_access, - input [1:0] csr_op, - input [11:0] csr_addr, - input csr_we_int, - - output logic is_wfi, - output logic in_wfi, - output logic dpc_will_hit, - output logic addr_match, - output logic is_ebreak, - output logic is_cebreak, - output logic is_dret, - output logic is_mulhsu, - output logic [31:0] pending_enabled_irq, - input pc_set, - input branch_in_ex -); - - clocking mon_cb @(posedge clk_i); - input #1step - - irq_i, - irq_ack_o, - irq_id_o, - mie_q, - - wb_stage_instr_valid_i, - wb_stage_instr_rdata_i, - wb_valid, - - ctrl_fsm_cs, - illegal_insn_i, - sys_en_i, - sys_ecall_insn_i, - boot_addr_i, - rvfi_pc_wdata, - rvfi_pc_rdata, - debug_req_i, - debug_mode_q, - dcsr_q, - depc_q, - depc_n, - dm_halt_addr_i, - dm_exception_addr_i, - mcause_q, - mtvec, - mepc_q, - tdata1, - tdata2, - trigger_match_in_wb, - sys_fence_insn_i, - mcountinhibit_q, - mcycle, - minstret, - inst_ret, - - core_sleep_o, - csr_access, - csr_op, - csr_addr, - is_wfi, - in_wfi, - dpc_will_hit, - addr_match, - is_ebreak, - is_cebreak, - is_dret, - is_mulhsu, - pending_enabled_irq, - pc_set, - branch_in_ex; - endclocking : mon_cb - -endinterface : uvmt_cv32e40x_debug_cov_assert_if - -`endif // __UVMT_CV32E40X_TB_IFS_SV__ diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_tdefs.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_tdefs.sv deleted file mode 100644 index 008517cf10..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_tdefs.sv +++ /dev/null @@ -1,35 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - -`ifndef __UVMT_CV32E40X_TDEFS_SV__ -`define __UVMT_CV32E40X_TDEFS_SV__ - - -/** - * Test Program Type. See the Verification Strategy for a discussion of this. - */ -typedef enum { - PREEXISTING_SELFCHECKING, - PREEXISTING_NOTSELFCHECKING, - GENERATED_SELFCHECKING, - GENERATED_NOTSELFCHECKING, - NO_TEST_PROGRAM - } test_program_type; - - -`endif // __UVMT_CV32E40X_TDEFS_SV__ diff --git a/cv32e40x/tb/uvmt/uvmt_cv32e40x_uvm_macros_inc.sv b/cv32e40x/tb/uvmt/uvmt_cv32e40x_uvm_macros_inc.sv deleted file mode 100644 index 0104cbc991..0000000000 --- a/cv32e40x/tb/uvmt/uvmt_cv32e40x_uvm_macros_inc.sv +++ /dev/null @@ -1,30 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - -`ifndef __UVMT_CV32E40X_UVM_MACROS_INC_SV__ -`define __UVMT_CV32E40X_UVM_MACROS_INC_SV__ - -// Simple inclusion of the uvm_macros.svh file into compilation scope. -// This should only be used in Xcelium where automatic load of UVM does not -// include the macros definition file. -// use of this include file "first" in the simulator compilation filelist -// ensures all macros are properly defined for usage - -`include "uvm_macros.svh" - -`endif diff --git a/cv32e40x/tests/.clang-format b/cv32e40x/tests/.clang-format deleted file mode 100644 index ab4772e00f..0000000000 --- a/cv32e40x/tests/.clang-format +++ /dev/null @@ -1,35 +0,0 @@ ---- -BasedOnStyle: LLVM -IndentWidth: 4 -UseTab: Never -BreakBeforeBraces: Linux -AlwaysBreakBeforeMultilineStrings: true -AllowShortIfStatementsOnASingleLine: false -AllowShortLoopsOnASingleLine: false -AllowShortFunctionsOnASingleLine: false -IndentCaseLabels: false -AlignEscapedNewlinesLeft: false -AlignTrailingComments: true -AlignOperands: true -AllowAllParametersOfDeclarationOnNextLine: false -AlignAfterOpenBracket: true -SpaceAfterCStyleCast: false -MaxEmptyLinesToKeep: 2 -BreakBeforeBinaryOperators: NonAssignment -BreakStringLiterals: false -SortIncludes: false -ContinuationIndentWidth: 4 -ColumnLimit: 80 -IndentPPDirectives: AfterHash -BinPackArguments: true -BinPackParameters: true -ForEachMacros: - - 'TAILQ_FOREACH' - - 'TAILQ_FOREACH_REVERSE' -BreakBeforeBinaryOperators: None -MaxEmptyLinesToKeep: 1 -AlwaysBreakAfterDefinitionReturnType: None -AlwaysBreakAfterReturnType: None -AlwaysBreakBeforeMultilineStrings: false -AlignConsecutiveAssignments: true -... diff --git a/cv32e40x/tests/.gitignore b/cv32e40x/tests/.gitignore deleted file mode 100644 index c95622eafc..0000000000 --- a/cv32e40x/tests/.gitignore +++ /dev/null @@ -1,17 +0,0 @@ -csmith/platform.info -csmith/test.c -csmith/test.elf -csmith/test_ref -csmith/output_ref.txt -csmith/output_sim.txt -platform.info -memory_dump.bin -riscv-fesvr -riscv-isa-sim -modelsim.ini -DVEfiles -csrc -inter.vpd -ucli.key -vc_hdrs.h -emb_*/ diff --git a/cv32e40x/tests/asm/user_define.h b/cv32e40x/tests/asm/user_define.h deleted file mode 100644 index 1e2a93fd0e..0000000000 --- a/cv32e40x/tests/asm/user_define.h +++ /dev/null @@ -1,30 +0,0 @@ -# Google UVM Generated Test -# Extracted from riscv_compliance_tests/riscv_test.h -.set print_port, 0x00800000 -.set test_ret_val, 0x008000c0 -.section .data -.global test_results -test_results: - .word 123456789 - -#TODO: figure out how to move this to the end of the program -#.section .text -#quick_fast_exit: -# /* print "DONE\n" */ -# lui a0,print_port>>12 -# addi a1,zero,'D' -# addi a2,zero,'O' -# addi a3,zero,'N' -# addi a4,zero,'E' -# addi a5,zero,'\n' -# sw a1,0(a0) -# sw a2,0(a0) -# sw a3,0(a0) -# sw a4,0(a0) -# sw a5,0(a0) -# -# li a0, CV_VP_STATUS_FLAGS_OFFSET -# lw a1, test_results /* report result */ -# sw a1,0(a0) -# -# wfi /* we are done */ diff --git a/cv32e40x/tests/cfg/b_ext_abs.yaml b/cv32e40x/tests/cfg/b_ext_abs.yaml deleted file mode 100644 index 511b31db60..0000000000 --- a/cv32e40x/tests/cfg/b_ext_abs.yaml +++ /dev/null @@ -1,14 +0,0 @@ -name: b_ext_abs -description: Enables the B extensions ZBA_ZBB_ZBS in the cv32e40x -compile_flags: - +define+ZBA_ZBB_ZBS -ovpsim: > -# --showoverrides -# --trace --tracechange --traceshowicount --monitornets -cflags: > -riscv_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbs1p00 - diff --git a/cv32e40x/tests/cfg/b_ext_all.yaml b/cv32e40x/tests/cfg/b_ext_all.yaml deleted file mode 100644 index dec74a8a1f..0000000000 --- a/cv32e40x/tests/cfg/b_ext_all.yaml +++ /dev/null @@ -1,14 +0,0 @@ -name: b_ext_all -description: Enables the B extensions ZBA_ZBB_ZBC_ZBS in the cv32e40x -compile_flags: - +define+ZBA_ZBB_ZBC_ZBS -ovpsim: > -# --showoverrides -# --trace --tracechange --traceshowicount --monitornets -cflags: > -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 - diff --git a/cv32e40x/tests/cfg/default.yaml b/cv32e40x/tests/cfg/default.yaml deleted file mode 100644 index 4cdc76a695..0000000000 --- a/cv32e40x/tests/cfg/default.yaml +++ /dev/null @@ -1,19 +0,0 @@ -name: default -description: Default configuration for CV32E40X simulations -compile_flags: - +define+ZBA_ZBB_ZBC_ZBS -ovpsim: > - # --showoverrides - # --trace --tracechange --traceshowicount --monitornets -cflags: > -plusargs: > - +enable_zba_extension=1 - +enable_zbb_extension=1 - +enable_zbc_extension=1 - +enable_zbs_extension=1 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -# Note: the following are depreciated -#riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -#llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/cfg/no_bitmanip.yaml b/cv32e40x/tests/cfg/no_bitmanip.yaml deleted file mode 100644 index c66ca48030..0000000000 --- a/cv32e40x/tests/cfg/no_bitmanip.yaml +++ /dev/null @@ -1,2 +0,0 @@ -name: no_bitmanip -description: Default configuration for CV32E40X simulations diff --git a/cv32e40x/tests/cfg/num_mhpmcounter_29.yaml b/cv32e40x/tests/cfg/num_mhpmcounter_29.yaml deleted file mode 100644 index 97ce7a48b6..0000000000 --- a/cv32e40x/tests/cfg/num_mhpmcounter_29.yaml +++ /dev/null @@ -1,14 +0,0 @@ -name: num_mhpmcounters_29 -description: Configuration for CV32E40X simulations with NUM_MHPMCOUNTER set to 29 -compile_flags: - +define+ZBA_ZBB_ZBC_ZBS - +define+SET_NUM_MHPMCOUNTERS=29 -plusargs: > - +enable_zba_extension=1 - +enable_zbb_extension=1 - +enable_zbc_extension=1 - +enable_zbs_extension=1 - +DISABLE_CSR_CHECK=mcountinhibit - # FIXME: Remove the DISABLE_CSR_CHECK when correct reset value is implemented in the ISS -cv_sw_march: > - rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/cfg/pma.yaml b/cv32e40x/tests/cfg/pma.yaml deleted file mode 100644 index eb1ac12e5b..0000000000 --- a/cv32e40x/tests/cfg/pma.yaml +++ /dev/null @@ -1,5 +0,0 @@ -name: pma -description: PMA configuration for regions and attributes -compile_flags: - +define+PMA_CUSTOM_CFG - diff --git a/cv32e40x/tests/cfg/pma_debug.yaml b/cv32e40x/tests/cfg/pma_debug.yaml deleted file mode 100644 index 8fdc13a034..0000000000 --- a/cv32e40x/tests/cfg/pma_debug.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: pma -description: PMA configuration for pma_debug test -compile_flags: - +define+PMA_DEBUG_CFG diff --git a/cv32e40x/tests/cfg/pma_test_cfg_1.yaml b/cv32e40x/tests/cfg/pma_test_cfg_1.yaml deleted file mode 100644 index 3abcb00f93..0000000000 --- a/cv32e40x/tests/cfg/pma_test_cfg_1.yaml +++ /dev/null @@ -1,17 +0,0 @@ -name: pma_test_cfg_1 -description: PMA configuration for the PMA_TEST_CFG_1 test case -compile_flags: - +define+PMA_TEST_CFG_1 - +define+ZBA_ZBB_ZBC_ZBS -plusargs: - +enable_pma=1 - +fix_sp=1 - +enable_zba_extension=1 - +enable_zbb_extension=1 - +enable_zbc_extension=1 - +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/cfg/pma_test_cfg_2.yaml b/cv32e40x/tests/cfg/pma_test_cfg_2.yaml deleted file mode 100644 index cf8ec97e28..0000000000 --- a/cv32e40x/tests/cfg/pma_test_cfg_2.yaml +++ /dev/null @@ -1,17 +0,0 @@ -name: pma_test_cfg_2 -description: PMA configuration for the PMA_TEST_CFG_2 test case -compile_flags: - +define+PMA_TEST_CFG_2 - +define+ZBA_ZBB_ZBC_ZBS -plusargs: - +enable_pma=1 - +fix_sp=1 - +enable_zba_extension=1 - +enable_zbb_extension=1 - +enable_zbc_extension=1 - +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/cfg/pma_test_cfg_3.yaml b/cv32e40x/tests/cfg/pma_test_cfg_3.yaml deleted file mode 100644 index 3ea237805e..0000000000 --- a/cv32e40x/tests/cfg/pma_test_cfg_3.yaml +++ /dev/null @@ -1,21 +0,0 @@ -name: pma_test_cfg_3 -description: PMA configuration for the PMA_TEST_CFG_3 test case -compile_flags: - +define+PMA_TEST_CFG_3 - +define+ZBA_ZBB_ZBC_ZBS -plusargs: - +enable_pma=1 - +boot_addr=0x48000080 - +mtvec_addr=0x48000000 - +nmi_addr=0x48100000 - +enable_large_mem_support=0 - +fix_sp=1 - +enable_zba_extension=1 - +enable_zbb_extension=1 - +enable_zbc_extension=1 - +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/cfg/pma_test_cfg_4.yaml b/cv32e40x/tests/cfg/pma_test_cfg_4.yaml deleted file mode 100644 index bb93a82537..0000000000 --- a/cv32e40x/tests/cfg/pma_test_cfg_4.yaml +++ /dev/null @@ -1,22 +0,0 @@ -name: pma_test_cfg_4 -description: PMA configuration for the PMA_TEST_CFG_4 test case -compile_flags: - +define+PMA_TEST_CFG_4 - +define+ZBA_ZBB_ZBC_ZBS -plusargs: - +enable_pma=1 - +boot_addr=0x10080 - +mtvec_addr=0x10000 - +nmi_addr=0xbc000100 - +dm_halt_addr=0x32010000 - +dm_exception_addr=0x32010800 - +fix_sp=1 - +enable_zba_extension=1 - +enable_zbb_extension=1 - +enable_zbc_extension=1 - +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/cfg/pma_test_cfg_5.yaml b/cv32e40x/tests/cfg/pma_test_cfg_5.yaml deleted file mode 100644 index 0fb3d39adb..0000000000 --- a/cv32e40x/tests/cfg/pma_test_cfg_5.yaml +++ /dev/null @@ -1,20 +0,0 @@ -name: pma_test_cfg_5 -description: PMA configuration for the PMA_TEST_CFG_5 test case -compile_flags: - +define+PMA_TEST_CFG_5 - +define+ZBA_ZBB_ZBC_ZBS -plusargs: - +enable_pma=1 - +boot_addr=0x80 - +fix_sp=1 - +dm_halt_addr=0x301000 - +dm_exception_addr=0x301800 - +enable_zba_extension=1 - +enable_zbb_extension=1 - +enable_zbc_extension=1 - +enable_zbs_extension=1 -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -cv_sw_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/embench/README.md b/cv32e40x/tests/embench/README.md deleted file mode 100644 index 24c71716a8..0000000000 --- a/cv32e40x/tests/embench/README.md +++ /dev/null @@ -1,122 +0,0 @@ -# EMBench for Core-V-Verif - -[EMBench](https://github.com/embench/embench-iot) has been integrated into Core-V-Verif to allow easy benchmarking of the RISC-V cores supported by -Core-V-Verif. This document explains the usage and implementation of the EMBench scripts and their integration -into the makefile environment of Core-V-Verif.

- - -## Quick start guide - -For a core that already has the supporting configuration files, running the EMBench Benchmarks can be achieved -in the following manner:
-from path: ->/core-v-verif/\[core\]/sim/uvmt - -run the following shell command: ->% make embench SIMULATOR=\[available simulator\] - -This will run the EMBench default benchmark \(speed\) on the core in the path, with the simulator given in the options. -**Note** that runtime here can be several hours. If you are uncertain if the simulations are running as they -should, the tests can be run outside of the benchmarking script, see [this](#simulate-an-embench-test-outside-of-the-script) section for details. - -If you want to set a target score for you benchmark, you can set the option EMB_TARGET, like this: ->% make embench SIMULATOR=\[sim\] EMB_TARGET=\[float\] - -The EMBench script will determine if the target has been met, for either a speed or size benchmark, and report -the result. - -To run a size benchmark, set the EMB_TYPE option to *size*: ->% make embench EMB_TYPE=size - -**Note** that SIMULATOR is not set when running size, as no simulation is necessary. Also note that when building the tests for the size benchmark, they are built without support files and libraries to match EMBench baseline, so any simulation with these files will fail.

- - -## Relevant files and directories - -- **core-v-verif/bin/run_embench.py**
-Main script that builds, runs and evaluates EMBench Benchmarks on the selected core. - -- **/core-v-verif/\[core\]/tests/embench/config/**
-Core specific configuration required by EMBench - -- **/core-v-verif/\[core\]/tests/embench/pylib/run_corev32.py**
-Core specific python module required by EMBench - -- **/core-v-verif/\[core\]/tests/programs/embench/**
-Test directory that is populated by the EMBench script with files necessary to run the EMBench tests -with the *make test ..* method. - -- **/core-v-verif/\[core\]/vendor_lib/embench/**
-Directory where the EMBench repo is cloned when the script runs

- -## Script options from make environment -The following table lists the available options, their default values and their function. -**Note** that only options unique to the EMBench scripts are included here, other dependencies, like the -SIMULATOR option, are omitted. - -| Option | Default | Description | -|----------------|------------|----------------------------------------------------------------------------------------------------------------------------------------| -| EMB_TYPE | speed | What benchmark to run. Valid options: speed, size
NOTE: type affects build configuration! | -| EMB_BUILD_ONLY | NO | Set this option to "YES" to only build the benchmarks | -| EMB_TARGET | 0(not set) | Set a target(float) for your EMBench score
Benchmark run will fail if target is not met
If no target is set, no checking is done | -| EMB_CPU_MHZ | 1 | Set the core frequency in MHz \* | -| EMB_PARALLEL | NO | Launches simulation jobs in parallel. The user must set CV_SIM_PREFIX based on any configured jobs manager (e.g. LSF, SLURM, .etc.) | -| EMB_DEBUG | NO | Set this option to "YES" to increase verbosity of the script | -| EMB_TIMEOUT | 3600 | Timeout for jobs to complete (in seconds) | - -
-* This value is used for calculation in EMBench only. Measurement is done by cycle count, so this does not -have to match simulation, but can be used to predict results for a system running the core at a -specific frequency.

- -## Simulate an EMBench test outside of the scripted environment -As the EMBench integration utilizes the *make test* calls already present in Core-V-Verif, the tests can be -simulated separately from the benchmark environment. To accomplish this, complete the following steps: - -1. Run the EMBench script with the "EMB_BUILD_ONLY=YES" option. Type must be *speed*, but can be left out as this is the default. - >% make embench EMB_BUILD_ONLY=YES -2. Run *make test* in the following manner: - >% make test TEST=emb_\[testname\] SIMULATOR=\[sim\] USE_ISS=NO - -This will simulate as any other test. Note that step 1 can be omitted if there has been a previously run -speed benchmark, and the repository has not been cleaned. At the time of writing, ISS must be disabled -as the accesses to the cycle counter in the mm_ram causes step and compare mismatches. Simulating with ISS -will also cause a significant increase in runtime.

- -## Extend EMBench integration to a new core -As new core designs are added to Core-V-Verif, we will want to run the Benchmarks on these. This section -describes the necessary steps to accomplish this. *Note* that this description only includes EMBench -unique files, dependencies in the core specific makefiles also exist. - -Copy the embench configuration directory from cv32e40p to the new core: ->/core-v-verif/\[core\]/tests/embench - -Copy the embench makefile defines(EMBENCH_*) from cv32e40p to the new core: ->/core-v-verif/\[core\]/sim/Common.mk - -Copy over the embench directory under *programs*. This should be empty except for a readme file. ->/core-v-verif/\[core\]/tests/programs/embench - - -Make the following changes to the .gitignore files listed:
-| File | Add line | -|----------------------------------------------|----------| -| /core-v-verif/\[core\]/tests/.gitignore | emb_*/ | -| /core-v-verif/\[core\]/vendor_lib/.gitignore | embench/ | - - - -
If there are no differences in configuration necessary compared to the cv32e40p, you are now done, and can -run the EMBench scripts in the manner described above. However, if there are notable differences, -a quick description on what to check follows. For full details, please check the EMBench [documentation](https://github.com/embench/embench-iot/blob/master/doc/README.md).
- -For compiler flags, linker flags or library dependencies, check the follwing files: ->/core-v-verif/\[core\]/tests/embench/config/corev32/chips/size/chip.cfg
->/core-v-verif/\[core\]/tests/embench/config/corev32/chips/speed/chip.cfg - -For changes to how the test files communicates with the testbench: ->/core-v-verif/\[core\]/tests/embench/config/corev32/chips/\[type\]/chipsupport.c
->/core-v-verif/\[core\]/tests/embench/config/corev32/chips/\[type\]/chipsupport.h - -If the new core has specific requirements to it's *make test* call, check this file: ->/core-v-verif/\[core\]/tests/embench/pylib/run_corev32.py \ No newline at end of file diff --git a/cv32e40x/tests/embench/config/corev32/arch.cfg b/cv32e40x/tests/embench/config/corev32/arch.cfg deleted file mode 100644 index 0583bdfe6e..0000000000 --- a/cv32e40x/tests/embench/config/corev32/arch.cfg +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################### -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -############################################################################### - -# This is a python setting of parameters for the architecture. The following -# parameters may be set (other keys are silently ignored). Defaults are shown -# in brackets -# - cc ('cc') -# - ld (same value as for cc) -# - cflags ([]) -# - ldflags ([]) -# - cc_define_pattern ('-D{0}') -# - cc_incdir_pattern ('-I{0}') -# - cc_input_pattern ('{0}') -# - cc_output_pattern ('-o {0}') -# - ld_input_pattern ('{0}') -# - ld_output_pattern ('-o {0}') -# - user_libs ([]) -# - dummy_libs ([]) -# - cpu_mhz (1) -# - warmup_heat (1) - -# The "flags" and "libs" parameters (cflags, ldflags, user_libs, dummy_libs) -# should be lists of arguments to be passed to the compile or link line as -# appropriate. Patterns are Python format patterns used to create arguments. -# Thus for GCC or Clang/LLVM defined constants can be passed using the prefix -# '-D', and the pattern '-D{0}' would be appropriate (which happens to be the -# default). - -# "user_libs" may be absolute file names or arguments to the linker. In the -# latter case corresponding arguments in ldflags may be needed. For example -# with GCC or Clang/LLVM is "-l" flags are used in "user_libs", the "-L" flags -# may be needed in "ldflags". - -# Dummy libs have their source in the "support" subdirectory. Thus if 'crt0' -# is specified, there should be a source file 'dummy-crt0.c' in the support -# directory. - -# There is no need to set an unused parameter, and this file may be empty to -# set no flags. - -# Parameter values which are duplicated in architecture, board, chip or -# command line are used in the following order of priority -# - default value -# - architecture specific value -# - chip specific value -# - board specific value -# - command line value - -# For flags, this priority is applied to individual flags, not the complete -# list of flags. diff --git a/cv32e40x/tests/embench/config/corev32/boards/corev32/board.cfg b/cv32e40x/tests/embench/config/corev32/boards/corev32/board.cfg deleted file mode 100644 index 5d7d45435f..0000000000 --- a/cv32e40x/tests/embench/config/corev32/boards/corev32/board.cfg +++ /dev/null @@ -1,69 +0,0 @@ -############################################################################### -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -############################################################################### - -# This is a python setting of parameters for the board. The following -# parameters may be set (other keys are silently ignored). Defaults are shown -# in brackets -# - cc ('cc') -# - ld (same value as for cc) -# - cflags ([]) -# - ldflags ([]) -# - cc_define_pattern ('-D{0}') -# - cc_incdir_pattern ('-I{0}') -# - cc_input_pattern ('{0}') -# - cc_output_pattern ('-o {0}') -# - ld_input_pattern ('{0}') -# - ld_output_pattern ('-o {0}') -# - user_libs ([]) -# - dummy_libs ([]) -# - cpu_mhz (1) -# - warmup_heat (1) - -# The "flags" and "libs" parameters (cflags, ldflags, user_libs, dummy_libs) -# should be lists of arguments to be passed to the compile or link line as -# appropriate. Patterns are Python format patterns used to create arguments. -# Thus for GCC or Clang/LLVM defined constants can be passed using the prefix -# '-D', and the pattern '-D{0}' would be appropriate (which happens to be the -# default). - -# "user_libs" may be absolute file names or arguments to the linker. In the -# latter case corresponding arguments in ldflags may be needed. For example -# with GCC or Clang/LLVM is "-l" flags are used in "user_libs", the "-L" flags -# may be needed in "ldflags". - -# Dummy libs have their source in the "support" subdirectory. Thus if 'crt0' -# is specified, there should be a source file 'dummy-crt0.c' in the support -# directory. - -# There is no need to set an unused parameter, and this file may be empty to -# set no flags. - -# Parameter values which are duplicated in architecture, board, chip or -# command line are used in the following order of priority -# - default value -# - architecture specific value -# - chip specific value -# - board specific value -# - command line value - -# For flags, this priority is applied to individual flags, not the complete -# list of flags. - -cpu_mhz = 1 diff --git a/cv32e40x/tests/embench/config/corev32/boards/corev32/boardsupport.c b/cv32e40x/tests/embench/config/corev32/boards/corev32/boardsupport.c deleted file mode 100644 index ac024cbdb8..0000000000 --- a/cv32e40x/tests/embench/config/corev32/boards/corev32/boardsupport.c +++ /dev/null @@ -1,21 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -*/ - -#include "boardsupport.h" - diff --git a/cv32e40x/tests/embench/config/corev32/boards/corev32/boardsupport.h b/cv32e40x/tests/embench/config/corev32/boards/corev32/boardsupport.h deleted file mode 100644 index f791f556ba..0000000000 --- a/cv32e40x/tests/embench/config/corev32/boards/corev32/boardsupport.h +++ /dev/null @@ -1,21 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -*/ - - - diff --git a/cv32e40x/tests/embench/config/corev32/chips/size/chip.cfg b/cv32e40x/tests/embench/config/corev32/chips/size/chip.cfg deleted file mode 100644 index 12f894d3b5..0000000000 --- a/cv32e40x/tests/embench/config/corev32/chips/size/chip.cfg +++ /dev/null @@ -1,86 +0,0 @@ -############################################################################### -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -############################################################################### - -# This is a python setting of parameters for the chip. The following -# parameters may be set (other keys are silently ignored). Defaults are shown -# in brackets -# - cc ('cc') -# - ld (same value as for cc) -# - cflags ([]) -# - ldflags ([]) -# - cc_define_pattern ('-D{0}') -# - cc_incdir_pattern ('-I{0}') -# - cc_input_pattern ('{0}') -# - cc_output_pattern ('-o {0}') -# - ld_input_pattern ('{0}') -# - ld_output_pattern ('-o {0}') -# - user_libs ([]) -# - dummy_libs ([]) -# - cpu_mhz (1) -# - warmup_heat (1) - -# The "flags" and "libs" parameters (cflags, ldflags, user_libs, dummy_libs) -# should be lists of arguments to be passed to the compile or link line as -# appropriate. Patterns are Python format patterns used to create arguments. -# Thus for GCC or Clang/LLVM defined constants can be passed using the prefix -# '-D', and the pattern '-D{0}' would be appropriate (which happens to be the -# default). - -# "user_libs" may be absolute file names or arguments to the linker. In the -# latter case corresponding arguments in ldflags may be needed. For example -# with GCC or Clang/LLVM is "-l" flags are used in "user_libs", the "-L" flags -# may be needed in "ldflags". - -# Dummy libs have their source in the "support" subdirectory. Thus if 'crt0' -# is specified, there should be a source file 'dummy-crt0.c' in the support -# directory. - -# There is no need to set an unused parameter, and this file may be empty to -# set no flags. - -# Parameter values which are duplicated in architecture, board, chip or -# command line are used in the following order of priority -# - default value -# - architecture specific value -# - chip specific value -# - board specific value -# - command line value - -# For flags, this priority is applied to individual flags, not the complete -# list of flags. - -# This is the generic framework for compilers, where the only common set up -# is: - -# '-c' is used to specify generation of object files when compiling a - -# each global data and function is put in its own section - -# - we garbage collect unused sections on linking - -cflags = [ - '-c', '-Os', '-ffunction-sections', '-mabi=ilp32', '-march=rv32imc' -] - -ldflags = [ - '-Wl,-gc-sections', '-Wl,-A,elf32lriscv', '-nostartfiles', '-nostdlib', '-mabi=ilp32', '-march=rv32imc' -] - -dummy_libs = ['crt0', 'libm', 'libc', 'libgcc'] diff --git a/cv32e40x/tests/embench/config/corev32/chips/size/chipsupport.c b/cv32e40x/tests/embench/config/corev32/chips/size/chipsupport.c deleted file mode 100644 index 55e6d6eb4b..0000000000 --- a/cv32e40x/tests/embench/config/corev32/chips/size/chipsupport.c +++ /dev/null @@ -1,44 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -*/ - -#include -#include -#include "corev_uvmt.h" -#include "chipsupport.h" - -void -initialise_board () -{ - printf("Initialize board corev32 \n"); - __asm__ volatile ("li a0, 0" : : : "memory"); -} - -void __attribute__ ((noinline)) __attribute__ ((externally_visible)) -start_trigger () -{ - - - __asm__ volatile ("li a0, 0" : : : "memory"); -} - -void __attribute__ ((noinline)) __attribute__ ((externally_visible)) -stop_trigger () -{ - -} diff --git a/cv32e40x/tests/embench/config/corev32/chips/size/chipsupport.h b/cv32e40x/tests/embench/config/corev32/chips/size/chipsupport.h deleted file mode 100644 index cdaa90e88c..0000000000 --- a/cv32e40x/tests/embench/config/corev32/chips/size/chipsupport.h +++ /dev/null @@ -1,27 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -*/ - -#ifndef CHIPSUPPORT_H -#define CHIPSUPPORT_H - -#define CPU_MHZ 1 - -#define TICKS_ADDR (*((volatile uint32_t*) (CV_VP_CYCLE_COUNTER_BASE + 0))) - -#endif diff --git a/cv32e40x/tests/embench/config/corev32/chips/speed/chip.cfg b/cv32e40x/tests/embench/config/corev32/chips/speed/chip.cfg deleted file mode 100644 index d8762b60b9..0000000000 --- a/cv32e40x/tests/embench/config/corev32/chips/speed/chip.cfg +++ /dev/null @@ -1,87 +0,0 @@ -############################################################################### -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -############################################################################### - -# This is a python setting of parameters for the chip. The following -# parameters may be set (other keys are silently ignored). Defaults are shown -# in brackets -# - cc ('cc') -# - ld (same value as for cc) -# - cflags ([]) -# - ldflags ([]) -# - cc_define_pattern ('-D{0}') -# - cc_incdir_pattern ('-I{0}') -# - cc_input_pattern ('{0}') -# - cc_output_pattern ('-o {0}') -# - ld_input_pattern ('{0}') -# - ld_output_pattern ('-o {0}') -# - user_libs ([]) -# - dummy_libs ([]) -# - cpu_mhz (1) -# - warmup_heat (1) - -# The "flags" and "libs" parameters (cflags, ldflags, user_libs, dummy_libs) -# should be lists of arguments to be passed to the compile or link line as -# appropriate. Patterns are Python format patterns used to create arguments. -# Thus for GCC or Clang/LLVM defined constants can be passed using the prefix -# '-D', and the pattern '-D{0}' would be appropriate (which happens to be the -# default). - -# "user_libs" may be absolute file names or arguments to the linker. In the -# latter case corresponding arguments in ldflags may be needed. For example -# with GCC or Clang/LLVM is "-l" flags are used in "user_libs", the "-L" flags -# may be needed in "ldflags". - -# Dummy libs have their source in the "support" subdirectory. Thus if 'crt0' -# is specified, there should be a source file 'dummy-crt0.c' in the support -# directory. - -# There is no need to set an unused parameter, and this file may be empty to -# set no flags. - -# Parameter values which are duplicated in architecture, board, chip or -# command line are used in the following order of priority -# - default value -# - architecture specific value -# - chip specific value -# - board specific value -# - command line value - -# For flags, this priority is applied to individual flags, not the complete -# list of flags. - -# This is the generic framework for compilers, where the only common set up -# is: - -# '-c' is used to specify generation of object files when compiling a - -# each global data and function is put in its own section - -# - we garbage collect unused sections on linking - -cflags = [ - '-c', '-O2', '-ffunction-sections', '-mabi=ilp32', '-march=rv32im' -] - -ldflags = [ - '-Wl,-gc-sections', '-Wl,-A,elf32lriscv', '-nostartfiles', '-mabi=ilp32', '-march=rv32im' -] -user_libs = ['-lm'] - -#dummy_libs = ['libm'] diff --git a/cv32e40x/tests/embench/config/corev32/chips/speed/chipsupport.c b/cv32e40x/tests/embench/config/corev32/chips/speed/chipsupport.c deleted file mode 100644 index 6f3557472e..0000000000 --- a/cv32e40x/tests/embench/config/corev32/chips/speed/chipsupport.c +++ /dev/null @@ -1,51 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -*/ - -#include -#include -#include "corev_uvmt.h" -#include "chipsupport.h" - -void -initialise_board () -{ - printf("Initialize board corev32 \n"); - __asm__ volatile ("li a0, 0" : : : "memory"); -} - -void __attribute__ ((noinline)) __attribute__ ((externally_visible)) -start_trigger () -{ - printf("start of test \n"); - //reset cycle counter - TICKS_ADDR = 0; - - __asm__ volatile ("li a0, 0" : : : "memory"); -} - -void __attribute__ ((noinline)) __attribute__ ((externally_visible)) -stop_trigger () -{ - uint32_t cycle_cnt = TICKS_ADDR; - printf("end of test \n"); - printf("Result is given in CPU cycles \n"); - printf("RES: %d \n", cycle_cnt); - - _exit(0); -} diff --git a/cv32e40x/tests/embench/config/corev32/chips/speed/chipsupport.h b/cv32e40x/tests/embench/config/corev32/chips/speed/chipsupport.h deleted file mode 100644 index cdaa90e88c..0000000000 --- a/cv32e40x/tests/embench/config/corev32/chips/speed/chipsupport.h +++ /dev/null @@ -1,27 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -*/ - -#ifndef CHIPSUPPORT_H -#define CHIPSUPPORT_H - -#define CPU_MHZ 1 - -#define TICKS_ADDR (*((volatile uint32_t*) (CV_VP_CYCLE_COUNTER_BASE + 0))) - -#endif diff --git a/cv32e40x/tests/embench/pylib/run_corev32.py b/cv32e40x/tests/embench/pylib/run_corev32.py deleted file mode 100644 index 98d300346c..0000000000 --- a/cv32e40x/tests/embench/pylib/run_corev32.py +++ /dev/null @@ -1,120 +0,0 @@ -#!/usr/bin/env python3 - -################################################################################ -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 -# -################################################################################ -# -# run_corev32 : python module provided to EMBench to allow the run script to -# run simulations in core-v-verif -# -# Author: Marton Teilgård -# email: mateilga@silabs.com -# -# -# Restriction: -# -# -# TODO: -################################################################################ - -""" -Embench module to run benchmark programs. - -This version is part of core-v-verif integration to EMBench. -""" - -__all__ = [ - 'get_target_args', - 'build_benchmark_cmd', - 'decode_results', -] - -import argparse -import re - -from embench_core import log - - -def get_target_args(remnant): - """Parse left over arguments""" - parser = argparse.ArgumentParser(description='Get target specific args') - - parser.add_argument( - '--cpu-mhz', - type=int, - default=1, - help='Processor clock speed in MHz' - ) - - parser.add_argument( - '--make-path', - type=str, - required=True, - help='The path to run make test from' - ) - - parser.add_argument( - '--simulator', - type=str, - required=True, - help='Simulator to run the benchmarks' - ) - - return parser.parse_args(remnant) - - -def build_benchmark_cmd(bench, args): - """Construct the command to run the benchmark. "args" is a - namespace with target specific arguments""" - - #CPU period - global cpu_per - cpu_per = float(1/(args.cpu_mhz*1_000_000)) - - #Utilize "make test" environment in core-v-verif - return ['make', '-C', args.make_path, 'test', - f"TEST=emb_{bench}", f"COMP=0", - f"SIMULATOR={args.simulator}", 'USE_ISS=NO'] - -def decode_results(stdout_str, stderr_str): - """Extract the results from the output string of the run. Return the - elapsed time in milliseconds or zero if the run failed.""" - - - global cpu_per - - #check that simulation returned successfully - if not re.search('SIMULATION PASSED', stdout_str, re.S): - log.debug('Warning: Simulation reporting error') - return 0.0 - - # Match "RES: " - rcstr = re.search('RES: (\d+)', stdout_str, re.S) - if not rcstr: - log.debug('Warning: Failed to find result') - return 0.0 - - time = float(rcstr.group(1))*cpu_per - time_ms = time * 1000 - - return time_ms - - # We must have failed to find a time - log.debug('Warning: Failed to find timing') - return 0.0 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_arithmetic_base_test/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_arithmetic_base_test/corev-dv.yaml deleted file mode 100644 index 2223c1e173..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_arithmetic_base_test/corev-dv.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_arithmetic_base_test -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated arithmetic test -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=0 - +directed_instr_0=riscv_int_numeric_corner_stream,4 - +no_fence=1 - +no_data_page=1 - +no_branch_jump=1 - +boot_mode=m - +no_csr_instr=1 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_arithmetic_base_test/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_arithmetic_base_test/test.yaml deleted file mode 100644 index 8f080c0472..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_arithmetic_base_test/test.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Test definition YAML for generated corev arithmetic base test - -name: corev_rand_arithmetic_base_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Math test generated by corev-dv - diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err/corev-dv.yaml deleted file mode 100644 index d6b53a5a0d..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err/corev-dv.yaml +++ /dev/null @@ -1,28 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_data_obi_err -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random instruction test with OBI data bus errors -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=6 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 - +directed_instr_5=riscv_mem_region_stress_test,4 - +directed_instr_6=riscv_jal_instr,4 - +directed_instr_7=corev_xori_not_instr,1 - +hint_instr_ratio=2 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +no_wfi=1 - +enable_ebreak_in_debug_rom=0 - +set_dcsr_ebreak=0 - +enable_debug_single_step=1 - +gen_debug_section=1 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err/test.yaml deleted file mode 100644 index f6a656c84f..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err/test.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Test definition YAML for generated corev arithmetic base test - -name: corev_rand_data_obi_err -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv with random data bus errors -plusargs: > - +random_fetch_toggle - +obi_memory_data_random_err_enabled - +obi_memory_data_one_shot_err_enabled - +gen_irq_noise diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err_debug/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err_debug/corev-dv.yaml deleted file mode 100644 index a907ed74df..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err_debug/corev-dv.yaml +++ /dev/null @@ -1,26 +0,0 @@ -name: corev_rand_data_obi_err_debug -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated test with OBI data bus errors in debug mode -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=6 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 - +directed_instr_5=riscv_mem_region_stress_test,4 - +directed_instr_6=riscv_jal_instr,4 - +directed_instr_7=corev_xori_not_instr,1 - +hint_instr_ratio=2 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +no_wfi=0 - +enable_ebreak_in_debug_rom=0 - +set_dcsr_ebreak=0 - +enable_debug_single_step=0 - +gen_debug_section=1 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml deleted file mode 100644 index f4541fd191..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_data_obi_err_debug/test.yaml +++ /dev/null @@ -1,10 +0,0 @@ -name: corev_rand_data_obi_err_debug -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv with random data bus errors in debug mode -plusargs: > - +random_fetch_toggle - +obi_memory_data_random_err_enabled - +obi_memory_data_one_shot_err_enabled - +gen_irq_noise - +gen_random_debug diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_debug/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_debug/corev-dv.yaml deleted file mode 100644 index e9bc438d5e..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_debug/corev-dv.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Test definition YAML for corev-dv test generator - -# corev-dv generator test -name: corev_rand_interrupt -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random debug tests -plusargs: > - +instr_cnt=30000 - +num_of_sub_program=0 - +directed_instr_0=riscv_int_numeric_corner_stream,4 - +no_fence=1 - +no_data_page=1 - +no_branch_jump=0 - +boot_mode=m - +no_csr_instr=1 - +no_wfi=0 - +no_ebreak=0 - +no_dret=1 - +set_dcsr_ebreak=1 - +enable_misaligned_instr=1 - +enable_ebreak_in_debug_rom=0 - +set_dcsr_ebreak=0 - +enable_debug_single_step=0 - +gen_debug_section=1 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_debug/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_debug/test.yaml deleted file mode 100644 index 2c848cd4ac..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_debug/test.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Test definition YAML for random debug test - -# corev-dv generator test -name: corev_rand_debug -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random debug generator test -plusargs: > - +gen_random_debug diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_ebreak/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_debug_ebreak/corev-dv.yaml deleted file mode 100644 index 7a844ff1e6..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_ebreak/corev-dv.yaml +++ /dev/null @@ -1,24 +0,0 @@ -name: corev_rand_debug_ebreak -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random debug test with ebreak from the debug ROM -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=0 - +directed_instr_0=riscv_int_numeric_corner_stream,4 - +no_fence=1 - +no_data_page=1 - +no_branch_jump=0 - +boot_mode=m - +no_csr_instr=0 - +no_wfi=0 - +no_ebreak=0 - +no_dret=1 - +enable_misaligned_instr=1 - +enable_ebreak_in_debug_rom=1 - +set_dcsr_ebreak=1 - +enable_debug_single_step=0 - +gen_debug_section=1 - +num_debug_sub_program=0 - +illegal_instr_ratio=2 - +enable_illegal_csr_instruction=1 \ No newline at end of file diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_ebreak/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_debug_ebreak/test.yaml deleted file mode 100644 index efa0f580da..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_ebreak/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -name: corev_rand_debug_ebreak -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random debug generator test with ebreak in debug ROM supported -plusargs: > - +gen_random_debug diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_single_step/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_debug_single_step/corev-dv.yaml deleted file mode 100644 index b8a2939e04..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_single_step/corev-dv.yaml +++ /dev/null @@ -1,21 +0,0 @@ -name: corev_rand_debug_single_step -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random debug test with single-stepping from the debug ROM -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=0 - +directed_instr_0=riscv_int_numeric_corner_stream,4 - +no_fence=1 - +no_data_page=1 - +no_branch_jump=0 - +boot_mode=m - +no_csr_instr=1 - +no_wfi=0 - +no_ebreak=1 - +no_dret=1 - +enable_misaligned_instr=1 - +enable_ebreak_in_debug_rom=0 - +set_dcsr_ebreak=0 - +enable_debug_single_step=1 - +gen_debug_section=1 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_single_step/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_debug_single_step/test.yaml deleted file mode 100644 index 8c2c1b6762..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_debug_single_step/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -name: corev_rand_debug_single_step -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random debug generator test with single-stepping supported in the debug ROM -plusargs: > - +gen_random_debug diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_fencei/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_fencei/corev-dv.yaml deleted file mode 100644 index f8c76e8e58..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_fencei/corev-dv.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_fencei -uvm_test: $(CV_CORE_LC)_instr_base_test -description: RISCV-DV generated random fencei test -plusargs: > - +instr_cnt=10000 - +directed_instr_0=corev_store_fencei_load_instr_stream,10 - +directed_instr_1=corev_store_fencei_exec_instr_stream,10 - +directed_instr_2=corev_vp_fencei_exec_instr_stream,10 - +rand_stall_obi_disable diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_fencei/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_fencei/test.yaml deleted file mode 100644 index 0296bbd835..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_fencei/test.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# Test definition YAML for generated corev fencei test - -name: corev_rand_fencei -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: RISCV-DV generated random fencei test diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_illegal_instr_test/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_illegal_instr_test/corev-dv.yaml deleted file mode 100644 index 4b65e2d94a..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_illegal_instr_test/corev-dv.yaml +++ /dev/null @@ -1,17 +0,0 @@ -name: corev_rand_illegal_instr_test -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random instruction test with illegal instructions -plusargs: > - +instr_cnt=30000 - +num_of_sub_program=5 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 - +directed_instr_5=riscv_mem_region_stress_test,4 - +directed_instr_6=riscv_jal_instr,4 - +illegal_instr_ratio=10 - +hint_instr_ratio=5 - diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_illegal_instr_test/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_illegal_instr_test/test.yaml deleted file mode 100644 index d391bd59ca..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_illegal_instr_test/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: corev_rand_illegal_instr_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv with illegal instructions diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_long_stall/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_long_stall/corev-dv.yaml deleted file mode 100644 index 9d2039d7f3..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_long_stall/corev-dv.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_instr_long_stall -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random instruction test with long OBI stalls -plusargs: > - +instr_cnt=50000 - +num_of_sub_program=10 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 - +directed_instr_5=riscv_mem_region_stress_test,4 - +directed_instr_6=riscv_jal_instr,4 - +hint_instr_ratio=2 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_long_stall/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_long_stall/test.yaml deleted file mode 100644 index b7a8a1c392..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_long_stall/test.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Test definition YAML for generated corev arithmetic base test - -name: corev_rand_instr_long_stall -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv -plusargs: > - +random_fetch_toggle - +max_data_zero_instr_stall diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err/corev-dv.yaml deleted file mode 100644 index 7275f0a61f..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err/corev-dv.yaml +++ /dev/null @@ -1,28 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_instr_obi_err -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random instruction test with OBI instruction bus errors -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=6 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 - +directed_instr_5=riscv_mem_region_stress_test,4 - +directed_instr_6=riscv_jal_instr,4 - +directed_instr_7=corev_xori_not_instr,1 - +hint_instr_ratio=2 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +no_wfi=0 - +enable_ebreak_in_debug_rom=0 - +set_dcsr_ebreak=0 - +enable_debug_single_step=1 - +gen_debug_section=1 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err/test.yaml deleted file mode 100644 index 0c9d538f9c..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err/test.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Test definition YAML for generated corev arithmetic base test - -name: corev_rand_instr_obi_err -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv with random instruction bus errors -plusargs: > - +random_fetch_toggle - +obi_memory_instr_random_err_enabled - +obi_memory_instr_one_shot_err_enabled - +gen_irq_noise diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/corev-dv.yaml deleted file mode 100644 index c686844945..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/corev-dv.yaml +++ /dev/null @@ -1,27 +0,0 @@ -name: corev_rand_instr_obi_err_debug -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated test with OBI instruction bus errors in debug mode -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=6 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 - +directed_instr_5=riscv_mem_region_stress_test,4 - +directed_instr_6=riscv_jal_instr,4 - +directed_instr_7=corev_xori_not_instr,1 - +hint_instr_ratio=2 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +no_wfi=0 - +enable_ebreak_in_debug_rom=0 - +set_dcsr_ebreak=0 - +enable_debug_single_step=1 - +gen_debug_section=1 - +exit_on_debug_exception=1 \ No newline at end of file diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/test.yaml deleted file mode 100644 index 272dcbcddd..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_obi_err_debug/test.yaml +++ /dev/null @@ -1,10 +0,0 @@ -name: corev_rand_instr_obi_err_debug -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv with random instruction bus errors in debug mode -plusargs: > - +random_fetch_toggle - +obi_memory_instr_random_err_enabled - +obi_memory_instr_one_shot_err_enabled - +gen_irq_noise - +gen_random_debug diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_test/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_test/corev-dv.yaml deleted file mode 100644 index 10893460cf..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_test/corev-dv.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_instr_test -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random instruction test -plusargs: > - +instr_cnt=50000 - +num_of_sub_program=10 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 - +directed_instr_5=riscv_mem_region_stress_test,4 - +directed_instr_6=riscv_jal_instr,4 - +directed_instr_7=corev_xori_not_instr,1 - +hint_instr_ratio=2 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_test/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_instr_test/test.yaml deleted file mode 100644 index f68eeb1ce4..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_instr_test/test.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Test definition YAML for generated corev arithmetic base test - -name: corev_rand_instr_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv -plusargs: > - +random_fetch_toggle diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt/corev-dv.yaml deleted file mode 100644 index 917e9c7ad0..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt/corev-dv.yaml +++ /dev/null @@ -1,19 +0,0 @@ -name: corev_rand_interrupt -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random interrupt test -plusargs: > - +instr_cnt=10000 - +num_of_sub_program=20 - +directed_instr_0=riscv_load_store_rand_instr_stream,2 - +directed_instr_1=riscv_mem_region_stress_test,5 - +directed_instr_2=riscv_loop_instr,4 - +directed_instr_3=riscv_hazard_instr_stream,1 - +directed_instr_4=riscv_jal_instr,3 - +directed_instr_5=corev_interrupt_csr_instr_stream,3 - +no_fence=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt/test.yaml deleted file mode 100644 index bac22a4de1..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt/test.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Test definition YAML for random interrupt test - -# corev-dv generator test -name: corev_rand_interrupt -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random interrupt generator test -plusargs: > - +gen_irq_noise \ No newline at end of file diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_debug/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_debug/corev-dv.yaml deleted file mode 100644 index b298ba2e6f..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_debug/corev-dv.yaml +++ /dev/null @@ -1,23 +0,0 @@ -name: corev_rand_interrupt_debug -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random interrupt tests with exceptions -plusargs: > - +instr_cnt=4000 - +num_of_sub_program=15 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=corev_interrupt_csr_wfi_instr_stream,5 - +no_fence=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=1 - +no_ebreak=0 - +gen_debug_section=1 - +set_dcsr_ebreak=1 - +illegal_instr_ratio=0 - +no_wfi=0 \ No newline at end of file diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_debug/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_debug/test.yaml deleted file mode 100644 index efcd4c293a..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_debug/test.yaml +++ /dev/null @@ -1,12 +0,0 @@ -# Test definition YAML for random interrupt test - -# corev-dv generator test -name: corev_rand_interrupt_debug -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random interrupt generator test with debug ebreaks -plusargs: > - +gen_irq_noise - +reset_debug - +gen_random_debug - diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_exception/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_exception/corev-dv.yaml deleted file mode 100644 index 8b14f38549..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_exception/corev-dv.yaml +++ /dev/null @@ -1,26 +0,0 @@ -name: corev_rand_interrupt_exception -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random interrupt tests with exceptions -plusargs: > - +instr_cnt=5000 - +num_of_sub_program=5 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=corev_interrupt_csr_wfi_instr_stream,5 - +directed_instr_5=corev_ecall_instr_stream,3 - +directed_instr_6=corev_jal_wfi_instr,1 - +no_fence=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 - +no_ebreak=0 - +no_dret=0 - +gen_debug_section=1 - +set_dcsr_ebreak=1 - +illegal_instr_ratio=1 - +no_wfi=0 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_exception/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_exception/test.yaml deleted file mode 100644 index 03142a613c..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_exception/test.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Test definition YAML for random interrupt test - -# corev-dv generator test -name: corev_rand_interrupt_exception -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random interrupt generator test with exceptions -plusargs: > - +gen_irq_noise diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_nested/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_nested/corev-dv.yaml deleted file mode 100644 index 9fb13d12b9..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_nested/corev-dv.yaml +++ /dev/null @@ -1,20 +0,0 @@ -name: corev_rand_interrupt_nested -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random interrupt tests with nested -plusargs: > - +instr_cnt=20000 - +num_of_sub_program=5 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_loop_instr,4 - +directed_instr_2=riscv_hazard_instr_stream,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,4 - +directed_instr_4=corev_interrupt_csr_wfi_instr_stream,5 - +no_fence=0 - +enable_interrupt=1 - +enable_nested_interrupt=1 - +enable_fast_interrupt_handler=1 - +no_wfi=1 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_nested/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_nested/test.yaml deleted file mode 100644 index e6f65ba0e4..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_nested/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -name: corev_rand_interrupt_nested -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random interrupt generator test with nested interrupts -plusargs: > - +gen_irq_noise diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi/corev-dv.yaml deleted file mode 100644 index 628f198123..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi/corev-dv.yaml +++ /dev/null @@ -1,22 +0,0 @@ -name: corev_rand_interrupt_wfi -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random interrupt tests with WFI -plusargs: > - +instr_cnt=2000 - +num_of_sub_program=15 - +directed_instr_0=riscv_load_store_rand_instr_stream,4 - +directed_instr_1=riscv_mem_region_stress_test,5 - +directed_instr_2=riscv_loop_instr,4 - +directed_instr_3=riscv_load_store_hazard_instr_stream,1 - +directed_instr_4=corev_jal_wfi_instr,1 - +directed_instr_5=corev_interrupt_csr_wfi_instr_stream,5 - +directed_instr_6=corev_jalr_wfi_instr,1 - +no_fence=0 - +disable_compressed_instr=0 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +no_wfi=0 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi/test.yaml deleted file mode 100644 index a5044e958c..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -name: corev_rand_interrupt_wfi -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random interrupt generator test with WFI -plusargs: > - +gen_irq_noise diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/corev-dv.yaml deleted file mode 100644 index 5b1301d212..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/corev-dv.yaml +++ /dev/null @@ -1,18 +0,0 @@ -name: corev_rand_interrupt_wfi_mem_stress -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random interrupt tests with WFI with memory stress test to cover load/store combinations -plusargs: > - +instr_cnt=30000 - +num_of_sub_program=2 - +directed_instr_0=corev_compressed_load_store_wfi_stress_instr_stream,20 - +directed_instr_1=corev_interrupt_csr_wfi_instr_stream,2 - +directed_instr_2=corev_jalr_wfi_instr,1 - +no_fence=0 - +disable_compressed_instr=0 - +randomize_csr=1 - +boot_mode=m - +no_csr_instr=0 - +enable_interrupt=1 - +enable_fast_interrupt_handler=1 - +no_wfi=0 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/test.yaml deleted file mode 100644 index e7480171c7..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_interrupt_wfi_mem_stress/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -name: corev_rand_interrupt_wfi_mem_stress -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random interrupt generator test with WFI -plusargs: > - +gen_irq_noise diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_jump_stress_test/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_jump_stress_test/corev-dv.yaml deleted file mode 100644 index be4675955c..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_jump_stress_test/corev-dv.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_jump_stress_test -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated jump stress test -plusargs: > - +instr_cnt=5000 - +num_of_sub_program=5 - +directed_instr_1=riscv_jal_instr,20 - diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_jump_stress_test/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_jump_stress_test/test.yaml deleted file mode 100644 index 5c1f28ca2e..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_jump_stress_test/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Test definition YAML for generated corev arithmetic base test - -name: corev_rand_jump_stress_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Jump stress test generated by corev-dv diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_pma_test/corev-dv.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_pma_test/corev-dv.yaml deleted file mode 100644 index fb295c36e0..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_pma_test/corev-dv.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# Test definition YAML for corev-dv test generator - -name: corev_rand_pma_test -uvm_test: $(CV_CORE_LC)_instr_base_test -description: > - RISCV-DV generated random PMA test -plusargs: > - +instr_cnt=1000 - +num_of_sub_program=7 - +directed_instr_0=corev_load_store_pma_misaligned_instr_stream,20 - +directed_instr_1=corev_jalr_pma_instr,20 - +directed_instr_2=corev_load_store_pma_mixed_instr_stream,20 - +directed_instr_3=corev_jalr_pma_cacheable_instr,20 - +directed_instr_4=corev_load_pma_instr_stream,20 - +directed_instr_5=corev_jalr_pma_bufferable_instr,20 - +directed_instr_6=corev_store_pma_instr_stream,20 - +directed_instr_7=corev_jalr_pma_undefined_region_instr,20 - #+directed_instr_10=corev_pma_atomic_random_instr_stream,3 - #+directed_instr_11=corev_pma_atomic_aligned_instr_stream,3 - #+directed_instr_12=corev_pma_atomic_misaligned_instr_stream,3 - #+directed_instr_13=corev_pma_atomic_allowed_instr_stream,3 - #+directed_instr_14=corev_pma_atomic_disallowed_instr_stream,3 - #+directed_instr_15=corev_pma_atomic_amo_instr_stream,3 diff --git a/cv32e40x/tests/programs/corev-dv/corev_rand_pma_test/test.yaml b/cv32e40x/tests/programs/corev-dv/corev_rand_pma_test/test.yaml deleted file mode 100644 index db98912b05..0000000000 --- a/cv32e40x/tests/programs/corev-dv/corev_rand_pma_test/test.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Test definition YAML for generated corev arithmetic base test - -name: corev_rand_pma_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Random instruction test generated by corev-dv -plusargs: > - +random_fetch_toggle diff --git a/cv32e40x/tests/programs/custom/b_ext_test/b_ext_test.c b/cv32e40x/tests/programs/custom/b_ext_test/b_ext_test.c deleted file mode 100644 index b80451d370..0000000000 --- a/cv32e40x/tests/programs/custom/b_ext_test/b_ext_test.c +++ /dev/null @@ -1,490 +0,0 @@ - -#include -#include - -unsigned int test; - -int test_shnadd(void); -int test_clz(void); -int test_ctz(void); -int test_cpop(void); -int test_rol(void); -int test_ror(void); -int test_rori(void); -int test_max(void); -int test_min(void); -int test_maxu(void); -int test_minu(void); -int test_or_c(void); -int test_andn(void); -int test_orn(void); -int test_xnor(void); -int test_rev8(void); -int test_bset(void); -int test_bseti(void); -int test_bclr(void); -int test_bclri(void); -int test_bext(void); -int test_bexti(void); -int test_binv(void); -int test_binvi(void); - -int main(int argc, char *argv[]) -{ - int failures=0; - // Zba - failures += test_shnadd(); - // Zbb - failures += test_clz(); - failures += test_ctz(); - failures += test_cpop(); - failures += test_rol(); - failures += test_ror(); - failures += test_rori(); - failures += test_max(); - failures += test_min(); - failures += test_maxu(); - failures += test_minu(); - failures += test_or_c(); - failures += test_andn(); - failures += test_orn(); - failures += test_xnor(); - failures += test_rev8(); - // Zbs - failures += test_bset(); - failures += test_bseti(); - failures += test_bclr(); - failures += test_bclri(); - failures += test_bext(); - failures += test_bexti(); - failures += test_binv(); - failures += test_binvi(); - - if(failures == 0){ - return EXIT_SUCCESS; - } - else { - return EXIT_FAILURE; - } -} - -int test_clz(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 8");// Store 8 in t3 - __asm__ volatile("clz t5, t3"); // Count Leading Zeros and store result in t5 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 28) { - printf("ERROR, CLZ result not as expected\n"); - failures++; - } - - return failures; -} - -int test_ctz(void){ - int failures = 0; - - __asm__ volatile("addi t4, zero, 32"); // Store 32 in t4 - __asm__ volatile("ctz t5, t4"); // Count Trailing Zeros, store result in t5 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 5 ) { - printf("ERROR, CTZ result not as expected\n"); - failures++; - } - - return failures; -} - -int test_cpop(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 5"); // Store 5 in t3 - __asm__ volatile("cpop t5, t3"); // Count POPulation, store result in t5 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 2 ) { - printf("ERROR, CPOP result not as expected\n"); - failures++; - } - - return failures; -} - -int test_max(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, -7"); // Store -7 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("max t5, t3, t4"); // Find max - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 1 ) { - printf("ERROR, MAX result not as expected\n"); - failures++; - } - - return failures; -} - -int test_min(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, -7"); // Store -7 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("min t5, t3, t4"); // Find min - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != -7 ) { - printf("ERROR, MIN result not as expected\n"); - failures++; - } - - return failures; -} - -int test_maxu(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, -7"); // Store -7 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("maxu t5, t3, t4"); // Find unsigned max - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != -7 ) { - printf("ERROR, MAXU result not as expected\n"); - failures++; - } - - return failures; -} - -int test_minu(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, -7"); // Store -7 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("minu t5, t3, t4"); // Find unsigned min - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 1 ) { - printf("ERROR, MINU result not as expected\n"); - failures++; - } - - return failures; -} - -int test_or_c(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 1"); // Store 1 in t3 - __asm__ volatile("orc.b t5, t3"); // Calculate bytewize or - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 0xFF ) { - printf("ERROR, ORC.B result not as expected: %x\n", test); - failures++; - } - - return failures; -} - -int test_andn(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 10"); // Store 10 in t3 - __asm__ volatile("addi t4, zero, -4"); // Store -4 in t4 - __asm__ volatile("andn t5, t3, t4"); // OR Negated - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 0x2 ) { - printf("ERROR, ANDN result not as expected: %x\n", test); - failures++; - } - - return failures; -} - -int test_orn(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 10"); // Store 10 in t3 - __asm__ volatile("addi t4, zero, -4"); // Store -4 in t4 - __asm__ volatile("orn t5, t3, t4"); // OR Negated - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 0xB ) { - printf("ERROR, ORN result not as expected: %x\n", test); - failures++; - } - - return failures; -} - -int test_xnor(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 10"); // Store 10 in t3 - __asm__ volatile("addi t4, zero, -4"); // Store -4 in t4 - __asm__ volatile("xnor t5, t3, t4"); // XOR Negated - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 0x9 ) { - printf("ERROR, XORN result not as expected: %x\n", test); - failures++; - } - - return failures; -} - -int test_rev8(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 15"); // Store 15 in t3 - __asm__ volatile("rev8 t5, t3"); // Reverse bytes - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 0x0F000000 ) { - printf("ERROR, REV8 result not as expected: %x\n", test); - failures++; - } - - return failures; -} - -int test_rol(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 7"); // Store 7 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("rol t5, t3, t4"); // ROtate Left - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 14 ) { - printf("ERROR, ROL result not as expected\n"); - failures++; - } - - return failures; -} - - -int test_ror(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 10"); // Store 10 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("ror t5, t3, t4"); // ROtate Right - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 5 ) { - printf("ERROR, ROR result not as expected\n"); - failures++; - } - - return failures; -} - - -int test_rori(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 10"); // Store 5 in t3 - __asm__ volatile("rori t5, t3, 1"); // ROtate Right Immediate - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 5 ) { - printf("ERROR, RORI result not as expected %x\n", test); - failures++; - } - - return failures; -} - -int test_bset(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 5"); // Store 5 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - - __asm__ volatile("bset t5, t3, t4"); // Set bit 1 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 7 ) { - printf("ERROR, BSET result not as expected %x\n", test); - failures++; - } - - return failures; -} - -int test_bseti(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 5"); // Store 5 in t3 - __asm__ volatile("bseti t5, t3, 3"); // Set bit 3 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 13 ) { - printf("ERROR, BSETI result not as expected %x\n", test); - failures++; - } - - return failures; -} - -int test_bclr(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 7"); // Store 7 in t3 - __asm__ volatile("addi t4, zero, 1"); // Store 1 in t4 - __asm__ volatile("bclr t5, t3, t4"); // Clear bit 1 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 5 ) { - printf("ERROR, BCLR result not as expected %x\n", test); - failures++; - } - return failures; -} - -int test_bclri(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 15"); // Store 15 in t3 - __asm__ volatile("bclri t5, t3, 3"); // Clear bit 3 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 7 ) { - printf("ERROR, BCLRI result not as expected %x\n", test); - failures++; - } - return failures; -} -int test_bext(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 8"); // Store 8 in t3 - __asm__ volatile("addi t4, zero, 3"); // Store 3 in t4 - __asm__ volatile("bext t5, t3, t4"); // Extract bit 3 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 1 ) { - printf("ERROR, BEXT result not as expected %x\n", test); - failures++; - } - return failures; -} - -int test_bexti(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 7"); // Store 7 in t3 - __asm__ volatile("bexti t5, t3, 3"); // Extract bit 3 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 0 ) { - printf("ERROR, BEXTI result not as expected %x\n", test); - failures++; - } - return failures; -} - -int test_binv(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 10"); // Store 10 in t3 - __asm__ volatile("addi t4, zero, 2"); // Store 2 in t4 - __asm__ volatile("binv t5, t3, t4"); // Invert bit 2 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 14 ) { - printf("ERROR, BINV result not as expected %x\n", test); - failures++; - } - return failures; -} - -int test_binvi(void){ - int failures = 0; - - __asm__ volatile("addi t3, zero, 5"); // Store 5 in t3 - __asm__ volatile("binvi t5, t3, 3"); // Invert bit 3 - __asm__ volatile("sw t5, test, t0"); // Store t5 to test - - if (test != 13 ) { - printf("ERROR, BINVI result not as expected %x\n", test); - failures++; - } - return failures; -} - - - -int test_shnadd(void){ - - int failures = 0; - - - printf("Testing SHnADD\n"); - - // Store 5 and 7 in t3, t4 - __asm__ volatile("addi t3, zero, 5"); - __asm__ volatile("addi t4, zero, 7"); - - // t5 = (t4 << 1) + t3 - __asm__ volatile("sh1add t5, t4, t3"); - - // Store t5 to test - __asm__ volatile("sw t5, test, t0"); - - if(test != (7<<1) + 5){ - printf("ERROR, SH1ADD result not as expected\n"); - failures++; - } - else { - printf("INFO, SH1ADD result as expected\n"); - } - - printf("test: 0x%x\n", test); - - // Store 5 and 7 in t3, t4 - __asm__ volatile("addi t3, zero, 5"); - __asm__ volatile("addi t4, zero, 7"); - // t5 = (t4 << 2) + t3 - __asm__ volatile("sh2add t5, t4, t3"); - // Store t5 to test - __asm__ volatile("sw t5, test, t0"); - - if(test != (7<<2) + 5){ - printf("ERROR, SH2ADD result not as expected\n"); - failures++; - } - else { - printf("INFO, SH2ADD result as expected\n"); - } - printf("test: 0x%x\n", test); - - // Store 5 and 7 in t3, t4 - __asm__ volatile("addi t3, zero, 5"); - __asm__ volatile("addi t4, zero, 7"); - // t5 = (t4 << 3) + t3 - __asm__ volatile("sh3add t5, t4, t3"); - // Store t5 to test - __asm__ volatile("sw t5, test, t0"); - - if(test != (7<<3) + 5){ - printf("ERROR, SH3ADD result not as expected\n"); - failures++; - } - else { - printf("INFO, SH3ADD result as expected\n"); - } - printf("test: 0x%x\n", test); - - - return failures; -} diff --git a/cv32e40x/tests/programs/custom/b_ext_test/test.yaml b/cv32e40x/tests/programs/custom/b_ext_test/test.yaml deleted file mode 100644 index dcd8934a23..0000000000 --- a/cv32e40x/tests/programs/custom/b_ext_test/test.yaml +++ /dev/null @@ -1,11 +0,0 @@ -name: b_ext_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Simple sanity check for B extension instructions - -# Toolchain configurations -riscv_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -gnu_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -corev_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 -pulp_not_supported: 1 -llvm_march: rv32imc_zba1p00_zbb1p00_zbc1p00_zbs1p00 diff --git a/cv32e40x/tests/programs/custom/branch_zero/branch_zero.c b/cv32e40x/tests/programs/custom/branch_zero/branch_zero.c deleted file mode 100644 index 9c6bf86cdd..0000000000 --- a/cv32e40x/tests/programs/custom/branch_zero/branch_zero.c +++ /dev/null @@ -1,172 +0,0 @@ -#include -#include -#include -#include -#include "corev_uvmt.h" - -#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE + 0)) -#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE + 4)) - -void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { - *TIMER_REG_ADDR = mask; - *TIMER_VAL_ADDR = 1 + cycle_delay; -} - -void enable_interrupts() { - asm("csrw mie,%0" : : "r"(0x1 << 16 | 0x1 << 17)); - asm("csrs mstatus,%0" : : "r"(0x1 << 3)); -} - -void m_fast0_irq_handler(void) { - asm("addi x18,x18,1"); - asm("mret"); -} - -void m_fast1_irq_handler(void) { - asm("addi x15,x15,1"); - asm("mret"); -} - -int main() { - printf("In branch zero test\n"); - - // Enable interrupt 16 - enable_interrupts(); - unsigned int a = 0x12345678; - unsigned int b = 0x12345678; - - // -------------------------------------- - // beq - // -------------------------------------- - printf("Test BEQ to zero offset\n"); - mm_ram_assert_irq(0x1 << 16, 100); - __asm__ - ( - "li x18, %0\n" - "li x19, %1\n" - "1:\n" - "beq x18,x19,1b\n" - : - : "i"(a), "i"(b) - : "x18", "x19" - ); - - - // -------------------------------------- - // bne - // -------------------------------------- - printf("Test BNE to zero offset\n"); - mm_ram_assert_irq(0x1 << 16, 100); - __asm__ - ( - "li x18, %0\n" - "li x19, %1\n" - "1:\n" - "bne x18,x19,1b\n" - : - : "i"(a), "i"(b+1) - : "x18", "x19" - ); - - // -------------------------------------- - // blt - // -------------------------------------- - printf("Test BLT to zero offset\n"); - mm_ram_assert_irq(0x1 << 16, 100); - __asm__ - ( - "li x18, %0\n" - "li x19, %1\n" - "1:\n" - "blt x18,x19,1b\n" - : - : "i"(a), "i"(b) - : "x18", "x19" - ); - - // -------------------------------------- - // bge - // -------------------------------------- - printf("Test BGE to zero offset\n"); - a = 0x7fffffff; - b = 0xffffffff; - mm_ram_assert_irq(0x1 << 16, 100); - __asm__ - ( - "li x18, %0\n" - "li x19, %1\n" - "1:\n" - "bge x18,x19,1b\n" - : - : "i"(a), "i"(b) - : "x18", "x19" - ); - - // -------------------------------------- - // bltu - // -------------------------------------- - printf("Test BLTU to zero offset\n"); - a = 0x12345678; - b = 0x12345679; - mm_ram_assert_irq(0x1 << 16, 100); - __asm__ - ( - "li x18, %0\n" - "li x19, %1\n" - "1:\n" - "bltu x18,x19,1b\n" - : - : "i"(a), "i"(b) - : "x18", "x19" - ); - - // -------------------------------------- - // bge - // -------------------------------------- - printf("Test BGEU to zero offset\n"); - a = 0xffffffff; - b = 0xffffffff; - mm_ram_assert_irq(0x1 << 16, 100); - __asm__ - ( - "li x18, %0\n" - "li x19, %1\n" - "1:\n" - "bgeu x18,x19,1b\n" - : - : "i"(a), "i"(b) - : "x18", "x19" - ); - - // -------------------------------------- - // c.beqz - // -------------------------------------- - printf("Test C.BEQZ to zero offset\n"); - a = 0; - mm_ram_assert_irq(0x1 << 17, 100); - __asm__ - ( - "li x15, %0\n" - "1:\n" - "c.beqz x15,1b\n" - : - : "i"(a) - : "x15" - ); - - // -------------------------------------- - // c.bnez - // -------------------------------------- - printf("Test C.BNEZ to zero offset\n"); - a = 0xffffffff; - mm_ram_assert_irq(0x1 << 17, 100); - __asm__ - ( - "li x15, %0\n" - "1:\n" - "c.bnez x15,1b\n" - : - : "i"(a) - : "x15" - ); -} \ No newline at end of file diff --git a/cv32e40x/tests/programs/custom/branch_zero/test.yaml b/cv32e40x/tests/programs/custom/branch_zero/test.yaml deleted file mode 100644 index 94ae467b08..0000000000 --- a/cv32e40x/tests/programs/custom/branch_zero/test.yaml +++ /dev/null @@ -1,5 +0,0 @@ -name: branch_zero -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Directed test that targets branches with zero offsets - diff --git a/cv32e40x/tests/programs/custom/coremark/LICENSE.md b/cv32e40x/tests/programs/custom/coremark/LICENSE.md deleted file mode 100644 index a146fd8b0c..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/LICENSE.md +++ /dev/null @@ -1,100 +0,0 @@ -# COREMARK® ACCEPTABLE USE AGREEMENT - -This ACCEPTABLE USE AGREEMENT (this “Agreement”) is offered by Embedded Microprocessor Benchmark Consortium, a California nonprofit corporation (“Licensor”), to users of its CoreMark® software (“Licensee”) exclusively on the following terms. - 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However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. - -END OF TERMS AND CONDITIONS diff --git a/cv32e40x/tests/programs/custom/coremark/core_list_join.c b/cv32e40x/tests/programs/custom/coremark/core_list_join.c deleted file mode 100644 index d9c256d4bf..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/core_list_join.c +++ /dev/null @@ -1,595 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include "coremark.h" -/* -Topic: Description - Benchmark using a linked list. - - Linked list is a common data structure used in many applications. - - For our purposes, this will excercise the memory units of the processor. - In particular, usage of the list pointers to find and alter data. - - We are not using Malloc since some platforms do not support this -library. - - Instead, the memory block being passed in is used to create a list, - and the benchmark takes care not to add more items then can be - accomodated by the memory block. The porting layer will make sure - that we have a valid memory block. - - All operations are done in place, without using any extra memory. - - The list itself contains list pointers and pointers to data items. - Data items contain the following: - - idx - An index that captures the initial order of the list. - data - Variable data initialized based on the input parameters. The 16b -are divided as follows: o Upper 8b are backup of original data. o Bit 7 -indicates if the lower 7 bits are to be used as is or calculated. o Bits 0-2 -indicate type of operation to perform to get a 7b value. o Bits 3-6 provide -input for the operation. - -*/ - -/* local functions */ - -list_head *core_list_find(list_head *list, list_data *info); -list_head *core_list_reverse(list_head *list); -list_head *core_list_remove(list_head *item); -list_head *core_list_undo_remove(list_head *item_removed, - list_head *item_modified); -list_head *core_list_insert_new(list_head * insert_point, - list_data * info, - list_head **memblock, - list_data **datablock, - list_head * memblock_end, - list_data * datablock_end); -typedef ee_s32 (*list_cmp)(list_data *a, list_data *b, core_results *res); -list_head *core_list_mergesort(list_head * list, - list_cmp cmp, - core_results *res); - -ee_s16 -calc_func(ee_s16 *pdata, core_results *res) -{ - ee_s16 data = *pdata; - ee_s16 retval; - ee_u8 optype - = (data >> 7) - & 1; /* bit 7 indicates if the function result has been cached */ - if (optype) /* if cached, use cache */ - return (data & 0x007f); - else - { /* otherwise calculate and cache the result */ - ee_s16 flag = data & 0x7; /* bits 0-2 is type of function to perform */ - ee_s16 dtype - = ((data >> 3) - & 0xf); /* bits 3-6 is specific data for the operation */ - dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */ - switch (flag) - { - case 0: - if (dtype < 0x22) /* set min period for bit corruption */ - dtype = 0x22; - retval = core_bench_state(res->size, - res->memblock[3], - res->seed1, - res->seed2, - dtype, - res->crc); - if (res->crcstate == 0) - res->crcstate = retval; - break; - case 1: - retval = core_bench_matrix(&(res->mat), dtype, res->crc); - if (res->crcmatrix == 0) - res->crcmatrix = retval; - break; - default: - retval = data; - break; - } - res->crc = crcu16(retval, res->crc); - retval &= 0x007f; - *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */ - return retval; - } -} -/* Function: cmp_complex - Compare the data item in a list cell. - - Can be used by mergesort. -*/ -ee_s32 -cmp_complex(list_data *a, list_data *b, core_results *res) -{ - ee_s16 val1 = calc_func(&(a->data16), res); - ee_s16 val2 = calc_func(&(b->data16), res); - return val1 - val2; -} - -/* Function: cmp_idx - Compare the idx item in a list cell, and regen the data. - - Can be used by mergesort. -*/ -ee_s32 -cmp_idx(list_data *a, list_data *b, core_results *res) -{ - if (res == NULL) - { - a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16 >> 8)); - b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16 >> 8)); - } - return a->idx - b->idx; -} - -void -copy_info(list_data *to, list_data *from) -{ - to->data16 = from->data16; - to->idx = from->idx; -} - -/* Benchmark for linked list: - - Try to find multiple data items. - - List sort - - Operate on data from list (crc) - - Single remove/reinsert - * At the end of this function, the list is back to original state -*/ -ee_u16 -core_bench_list(core_results *res, ee_s16 finder_idx) -{ - ee_u16 retval = 0; - ee_u16 found = 0, missed = 0; - list_head *list = res->list; - ee_s16 find_num = res->seed3; - list_head *this_find; - list_head *finder, *remover; - list_data info; - ee_s16 i; - - info.idx = finder_idx; - /* find values in the list, and change the list each time - * (reverse and cache if value found) */ - for (i = 0; i < find_num; i++) - { - info.data16 = (i & 0xff); - this_find = core_list_find(list, &info); - list = core_list_reverse(list); - if (this_find == NULL) - { - missed++; - retval += (list->next->info->data16 >> 8) & 1; - } - else - { - found++; - if (this_find->info->data16 & 0x1) /* use found value */ - retval += (this_find->info->data16 >> 9) & 1; - /* and cache next item at the head of the list (if any) */ - if (this_find->next != NULL) - { - finder = this_find->next; - this_find->next = finder->next; - finder->next = list->next; - list->next = finder; - } - } - if (info.idx >= 0) - info.idx++; -#if CORE_DEBUG - ee_printf("List find %d: [%d,%d,%d]\n", i, retval, missed, found); -#endif - } - retval += found * 4 - missed; - /* sort the list by data content and remove one item*/ - if (finder_idx > 0) - list = core_list_mergesort(list, cmp_complex, res); - remover = core_list_remove(list->next); - /* CRC data content of list from location of index N forward, and then undo - * remove */ - finder = core_list_find(list, &info); - if (!finder) - finder = list->next; - while (finder) - { - retval = crc16(list->info->data16, retval); - finder = finder->next; - } -#if CORE_DEBUG - ee_printf("List sort 1: %04x\n", retval); -#endif - remover = core_list_undo_remove(remover, list->next); - /* sort the list by index, in effect returning the list to original state */ - list = core_list_mergesort(list, cmp_idx, NULL); - /* CRC data content of list */ - finder = list->next; - while (finder) - { - retval = crc16(list->info->data16, retval); - finder = finder->next; - } -#if CORE_DEBUG - ee_printf("List sort 2: %04x\n", retval); -#endif - return retval; -} -/* Function: core_list_init - Initialize list with data. - - Parameters: - blksize - Size of memory to be initialized. - memblock - Pointer to memory block. - seed - Actual values chosen depend on the seed parameter. - The seed parameter MUST be supplied from a source that cannot be - determined at compile time - - Returns: - Pointer to the head of the list. - -*/ -list_head * -core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) -{ - /* calculated pointers for the list */ - ee_u32 per_item = 16 + sizeof(struct list_data_s); - ee_u32 size = (blksize / per_item) - - 2; /* to accomodate systems with 64b pointers, and make sure - same code is executed, set max list elements */ - list_head *memblock_end = memblock + size; - list_data *datablock = (list_data *)(memblock_end); - list_data *datablock_end = datablock + size; - /* some useful variables */ - ee_u32 i; - list_head *finder, *list = memblock; - list_data info; - - /* create a fake items for the list head and tail */ - list->next = NULL; - list->info = datablock; - list->info->idx = 0x0000; - list->info->data16 = (ee_s16)0x8080; - memblock++; - datablock++; - info.idx = 0x7fff; - info.data16 = (ee_s16)0xffff; - core_list_insert_new( - list, &info, &memblock, &datablock, memblock_end, datablock_end); - - /* then insert size items */ - for (i = 0; i < size; i++) - { - ee_u16 datpat = ((ee_u16)(seed ^ i) & 0xf); - ee_u16 dat - = (datpat << 3) | (i & 0x7); /* alternate between algorithms */ - info.data16 = (dat << 8) | dat; /* fill the data with actual data and - upper bits with rebuild value */ - core_list_insert_new( - list, &info, &memblock, &datablock, memblock_end, datablock_end); - } - /* and now index the list so we know initial seed order of the list */ - finder = list->next; - i = 1; - while (finder->next != NULL) - { - if (i < size / 5) /* first 20% of the list in order */ - finder->info->idx = i++; - else - { - ee_u16 pat = (ee_u16)(i++ ^ seed); /* get a pseudo random number */ - finder->info->idx = 0x3fff - & (((i & 0x07) << 8) - | pat); /* make sure the mixed items end up - after the ones in sequence */ - } - finder = finder->next; - } - list = core_list_mergesort(list, cmp_idx, NULL); -#if CORE_DEBUG - ee_printf("Initialized list:\n"); - finder = list; - while (finder) - { - ee_printf( - "[%04x,%04x]", finder->info->idx, (ee_u16)finder->info->data16); - finder = finder->next; - } - ee_printf("\n"); -#endif - return list; -} - -/* Function: core_list_insert - Insert an item to the list - - Parameters: - insert_point - where to insert the item. - info - data for the cell. - memblock - pointer for the list header - datablock - pointer for the list data - memblock_end - end of region for list headers - datablock_end - end of region for list data - - Returns: - Pointer to new item. -*/ -list_head * -core_list_insert_new(list_head * insert_point, - list_data * info, - list_head **memblock, - list_data **datablock, - list_head * memblock_end, - list_data * datablock_end) -{ - list_head *newitem; - - if ((*memblock + 1) >= memblock_end) - return NULL; - if ((*datablock + 1) >= datablock_end) - return NULL; - - newitem = *memblock; - (*memblock)++; - newitem->next = insert_point->next; - insert_point->next = newitem; - - newitem->info = *datablock; - (*datablock)++; - copy_info(newitem->info, info); - - return newitem; -} - -/* Function: core_list_remove - Remove an item from the list. - - Operation: - For a singly linked list, remove by copying the data from the next item - over to the current cell, and unlinking the next item. - - Note: - since there is always a fake item at the end of the list, no need to - check for NULL. - - Returns: - Removed item. -*/ -list_head * -core_list_remove(list_head *item) -{ - list_data *tmp; - list_head *ret = item->next; - /* swap data pointers */ - tmp = item->info; - item->info = ret->info; - ret->info = tmp; - /* and eliminate item */ - item->next = item->next->next; - ret->next = NULL; - return ret; -} - -/* Function: core_list_undo_remove - Undo a remove operation. - - Operation: - Since we want each iteration of the benchmark to be exactly the same, - we need to be able to undo a remove. - Link the removed item back into the list, and switch the info items. - - Parameters: - item_removed - Return value from the - item_modified - List item that was modified during - - Returns: - The item that was linked back to the list. - -*/ -list_head * -core_list_undo_remove(list_head *item_removed, list_head *item_modified) -{ - list_data *tmp; - /* swap data pointers */ - tmp = item_removed->info; - item_removed->info = item_modified->info; - item_modified->info = tmp; - /* and insert item */ - item_removed->next = item_modified->next; - item_modified->next = item_removed; - return item_removed; -} - -/* Function: core_list_find - Find an item in the list - - Operation: - Find an item by idx (if not 0) or specific data value - - Parameters: - list - list head - info - idx or data to find - - Returns: - Found item, or NULL if not found. -*/ -list_head * -core_list_find(list_head *list, list_data *info) -{ - if (info->idx >= 0) - { - while (list && (list->info->idx != info->idx)) - list = list->next; - return list; - } - else - { - while (list && ((list->info->data16 & 0xff) != info->data16)) - list = list->next; - return list; - } -} -/* Function: core_list_reverse - Reverse a list - - Operation: - Rearrange the pointers so the list is reversed. - - Parameters: - list - list head - info - idx or data to find - - Returns: - Found item, or NULL if not found. -*/ - -list_head * -core_list_reverse(list_head *list) -{ - list_head *next = NULL, *tmp; - while (list) - { - tmp = list->next; - list->next = next; - next = list; - list = tmp; - } - return next; -} -/* Function: core_list_mergesort - Sort the list in place without recursion. - - Description: - Use mergesort, as for linked list this is a realistic solution. - Also, since this is aimed at embedded, care was taken to use iterative - rather then recursive algorithm. The sort can either return the list to - original order (by idx) , or use the data item to invoke other other - algorithms and change the order of the list. - - Parameters: - list - list to be sorted. - cmp - cmp function to use - - Returns: - New head of the list. - - Note: - We have a special header for the list that will always be first, - but the algorithm could theoretically modify where the list starts. - - */ -list_head * -core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) -{ - list_head *p, *q, *e, *tail; - ee_s32 insize, nmerges, psize, qsize, i; - - insize = 1; - - while (1) - { - p = list; - list = NULL; - tail = NULL; - - nmerges = 0; /* count number of merges we do in this pass */ - - while (p) - { - nmerges++; /* there exists a merge to be done */ - /* step `insize' places along from p */ - q = p; - psize = 0; - for (i = 0; i < insize; i++) - { - psize++; - q = q->next; - if (!q) - break; - } - - /* if q hasn't fallen off end, we have two lists to merge */ - qsize = insize; - - /* now we have two lists; merge them */ - while (psize > 0 || (qsize > 0 && q)) - { - - /* decide whether next element of merge comes from p or q */ - if (psize == 0) - { - /* p is empty; e must come from q. */ - e = q; - q = q->next; - qsize--; - } - else if (qsize == 0 || !q) - { - /* q is empty; e must come from p. */ - e = p; - p = p->next; - psize--; - } - else if (cmp(p->info, q->info, res) <= 0) - { - /* First element of p is lower (or same); e must come from - * p. */ - e = p; - p = p->next; - psize--; - } - else - { - /* First element of q is lower; e must come from q. */ - e = q; - q = q->next; - qsize--; - } - - /* add the next element to the merged list */ - if (tail) - { - tail->next = e; - } - else - { - list = e; - } - tail = e; - } - - /* now p has stepped `insize' places along, and q has too */ - p = q; - } - - tail->next = NULL; - - /* If we have done only one merge, we're finished. */ - if (nmerges <= 1) /* allow for nmerges==0, the empty list case */ - return list; - - /* Otherwise repeat, merging lists twice the size */ - insize *= 2; - } -#if COMPILER_REQUIRES_SORT_RETURN - return list; -#endif -} diff --git a/cv32e40x/tests/programs/custom/coremark/core_main.c b/cv32e40x/tests/programs/custom/coremark/core_main.c deleted file mode 100644 index 4f6ee177d9..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/core_main.c +++ /dev/null @@ -1,443 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - - -/* File: core_main.c - This file contains the framework to acquire a block of memory, seed - initial parameters, tun t he benchmark and report the results. -*/ -#include "coremark.h" - -/* Function: iterate - Run the benchmark for a specified number of iterations. - - Operation: - For each type of benchmarked algorithm: - a - Initialize the data block for the algorithm. - b - Execute the algorithm N times. - - Returns: - NULL. -*/ -static ee_u16 list_known_crc[] = { (ee_u16)0xd4b0, - (ee_u16)0x3340, - (ee_u16)0x6a79, - (ee_u16)0xe714, - (ee_u16)0xe3c1 }; -static ee_u16 matrix_known_crc[] = { (ee_u16)0xbe52, - (ee_u16)0x1199, - (ee_u16)0x5608, - (ee_u16)0x1fd7, - (ee_u16)0x0747 }; -static ee_u16 state_known_crc[] = { (ee_u16)0x5e47, - (ee_u16)0x39bf, - (ee_u16)0xe5a4, - (ee_u16)0x8e3a, - (ee_u16)0x8d84 }; -void * -iterate(void *pres) -{ - ee_u32 i; - ee_u16 crc; - core_results *res = (core_results *)pres; - ee_u32 iterations = res->iterations; - res->crc = 0; - res->crclist = 0; - res->crcmatrix = 0; - res->crcstate = 0; - - for (i = 0; i < iterations; i++) - { - crc = core_bench_list(res, 1); - res->crc = crcu16(crc, res->crc); - crc = core_bench_list(res, -1); - res->crc = crcu16(crc, res->crc); - if (i == 0) - res->crclist = res->crc; - } - return NULL; -} - -#if (SEED_METHOD == SEED_ARG) -ee_s32 get_seed_args(int i, int argc, char *argv[]); -#define get_seed(x) (ee_s16) get_seed_args(x, argc, argv) -#define get_seed_32(x) get_seed_args(x, argc, argv) -#else /* via function or volatile */ -ee_s32 get_seed_32(int i); -#define get_seed(x) (ee_s16) get_seed_32(x) -#endif - -#if (MEM_METHOD == MEM_STATIC) -ee_u8 static_memblk[TOTAL_DATA_SIZE]; -#endif -char *mem_name[3] = { "Static", "Heap", "Stack" }; -/* Function: main - Main entry routine for the benchmark. - This function is responsible for the following steps: - - 1 - Initialize input seeds from a source that cannot be determined at - compile time. 2 - Initialize memory block for use. 3 - Run and time the - benchmark. 4 - Report results, testing the validity of the output if the - seeds are known. - - Arguments: - 1 - first seed : Any value - 2 - second seed : Must be identical to first for iterations to be - identical 3 - third seed : Any value, should be at least an order of - magnitude less then the input size, but bigger then 32. 4 - Iterations : - Special, if set to 0, iterations will be automatically determined such that - the benchmark will run between 10 to 100 secs - -*/ - -#if MAIN_HAS_NOARGC -MAIN_RETURN_TYPE -main(void) -{ - int argc = 0; - char *argv[1]; -#else -MAIN_RETURN_TYPE -main(int argc, char *argv[]) -{ -#endif - ee_u16 i, j = 0, num_algorithms = 0; - ee_s16 known_id = -1, total_errors = 0; - ee_u16 seedcrc = 0; - CORE_TICKS total_time; - core_results results[MULTITHREAD]; -#if (MEM_METHOD == MEM_STACK) - ee_u8 stack_memblock[TOTAL_DATA_SIZE * MULTITHREAD]; -#endif - /* first call any initializations needed */ - portable_init(&(results[0].port), &argc, argv); - /* First some checks to make sure benchmark will run ok */ - if (sizeof(struct list_head_s) > 128) - { - ee_printf("list_head structure too big for comparable data!\n"); - return MAIN_RETURN_VAL; - } - results[0].seed1 = get_seed(1); - results[0].seed2 = get_seed(2); - results[0].seed3 = get_seed(3); - results[0].iterations = get_seed_32(4); -#if CORE_DEBUG - results[0].iterations = 1; -#endif - results[0].execs = get_seed_32(5); - if (results[0].execs == 0) - { /* if not supplied, execute all algorithms */ - results[0].execs = ALL_ALGORITHMS_MASK; - } - /* put in some default values based on one seed only for easy testing */ - if ((results[0].seed1 == 0) && (results[0].seed2 == 0) - && (results[0].seed3 == 0)) - { /* perfromance run */ - results[0].seed1 = 0; - results[0].seed2 = 0; - results[0].seed3 = 0x66; - } - if ((results[0].seed1 == 1) && (results[0].seed2 == 0) - && (results[0].seed3 == 0)) - { /* validation run */ - results[0].seed1 = 0x3415; - results[0].seed2 = 0x3415; - results[0].seed3 = 0x66; - } -#if (MEM_METHOD == MEM_STATIC) - results[0].memblock[0] = (void *)static_memblk; - results[0].size = TOTAL_DATA_SIZE; - results[0].err = 0; -#if (MULTITHREAD > 1) -#error "Cannot use a static data area with multiple contexts!" -#endif -#elif (MEM_METHOD == MEM_MALLOC) - for (i = 0; i < MULTITHREAD; i++) - { - ee_s32 malloc_override = get_seed(7); - if (malloc_override != 0) - results[i].size = malloc_override; - else - results[i].size = TOTAL_DATA_SIZE; - results[i].memblock[0] = portable_malloc(results[i].size); - results[i].seed1 = results[0].seed1; - results[i].seed2 = results[0].seed2; - results[i].seed3 = results[0].seed3; - results[i].err = 0; - results[i].execs = results[0].execs; - } -#elif (MEM_METHOD == MEM_STACK) -for (i = 0; i < MULTITHREAD; i++) -{ - results[i].memblock[0] = stack_memblock + i * TOTAL_DATA_SIZE; - results[i].size = TOTAL_DATA_SIZE; - results[i].seed1 = results[0].seed1; - results[i].seed2 = results[0].seed2; - results[i].seed3 = results[0].seed3; - results[i].err = 0; - results[i].execs = results[0].execs; -} -#else -#error "Please define a way to initialize a memory block." -#endif - /* Data init */ - /* Find out how space much we have based on number of algorithms */ - for (i = 0; i < NUM_ALGORITHMS; i++) - { - if ((1 << (ee_u32)i) & results[0].execs) - num_algorithms++; - } - for (i = 0; i < MULTITHREAD; i++) - results[i].size = results[i].size / num_algorithms; - /* Assign pointers */ - for (i = 0; i < NUM_ALGORITHMS; i++) - { - ee_u32 ctx; - if ((1 << (ee_u32)i) & results[0].execs) - { - for (ctx = 0; ctx < MULTITHREAD; ctx++) - results[ctx].memblock[i + 1] - = (char *)(results[ctx].memblock[0]) + results[0].size * j; - j++; - } - } - /* call inits */ - for (i = 0; i < MULTITHREAD; i++) - { - if (results[i].execs & ID_LIST) - { - results[i].list = core_list_init( - results[0].size, results[i].memblock[1], results[i].seed1); - } - if (results[i].execs & ID_MATRIX) - { - core_init_matrix(results[0].size, - results[i].memblock[2], - (ee_s32)results[i].seed1 - | (((ee_s32)results[i].seed2) << 16), - &(results[i].mat)); - } - if (results[i].execs & ID_STATE) - { - core_init_state( - results[0].size, results[i].seed1, results[i].memblock[3]); - } - } - - /* automatically determine number of iterations if not set */ - if (results[0].iterations == 0) - { - secs_ret secs_passed = 0; - ee_u32 divisor; - results[0].iterations = 1; - while (secs_passed < (secs_ret)1) - { - results[0].iterations *= 10; - start_time(); - iterate(&results[0]); - stop_time(); - secs_passed = time_in_secs(get_time()); - } - /* now we know it executes for at least 1 sec, set actual run time at - * about 10 secs */ - divisor = (ee_u32)secs_passed; - if (divisor == 0) /* some machines cast float to int as 0 since this - conversion is not defined by ANSI, but we know at - least one second passed */ - divisor = 1; - results[0].iterations *= 1 + 10 / divisor; - } - /* perform actual benchmark */ - start_time(); -#if (MULTITHREAD > 1) - if (default_num_contexts > MULTITHREAD) - { - default_num_contexts = MULTITHREAD; - } - for (i = 0; i < default_num_contexts; i++) - { - results[i].iterations = results[0].iterations; - results[i].execs = results[0].execs; - core_start_parallel(&results[i]); - } - for (i = 0; i < default_num_contexts; i++) - { - core_stop_parallel(&results[i]); - } -#else - iterate(&results[0]); -#endif - stop_time(); - total_time = get_time(); - /* get a function of the input to report */ - seedcrc = crc16(results[0].seed1, seedcrc); - seedcrc = crc16(results[0].seed2, seedcrc); - seedcrc = crc16(results[0].seed3, seedcrc); - seedcrc = crc16(results[0].size, seedcrc); - - switch (seedcrc) - { /* test known output for common seeds */ - case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */ - known_id = 0; - ee_printf("6k performance run parameters for coremark.\n"); - break; - case 0x7b05: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per - algorithm */ - known_id = 1; - ee_printf("6k validation run parameters for coremark.\n"); - break; - case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm - */ - known_id = 2; - ee_printf("Profile generation run parameters for coremark.\n"); - break; - case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */ - known_id = 3; - ee_printf("2K performance run parameters for coremark.\n"); - break; - case 0x18f2: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per - algorithm */ - known_id = 4; - ee_printf("2K validation run parameters for coremark.\n"); - break; - default: - total_errors = -1; - break; - } - if (known_id >= 0) - { - for (i = 0; i < default_num_contexts; i++) - { - results[i].err = 0; - if ((results[i].execs & ID_LIST) - && (results[i].crclist != list_known_crc[known_id])) - { - ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n", - i, - results[i].crclist, - list_known_crc[known_id]); - results[i].err++; - } - if ((results[i].execs & ID_MATRIX) - && (results[i].crcmatrix != matrix_known_crc[known_id])) - { - ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n", - i, - results[i].crcmatrix, - matrix_known_crc[known_id]); - results[i].err++; - } - if ((results[i].execs & ID_STATE) - && (results[i].crcstate != state_known_crc[known_id])) - { - ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n", - i, - results[i].crcstate, - state_known_crc[known_id]); - results[i].err++; - } - total_errors += results[i].err; - } - } - total_errors += check_data_types(); - /* and report results */ - ee_printf("CoreMark Size : %lu\n", (long unsigned)results[0].size); - ee_printf("Total ticks : %lu\n", (long unsigned)total_time); -#if HAS_FLOAT - ee_printf("Total time (secs): %f\n", time_in_secs(total_time)); - if (time_in_secs(total_time) > 0) - ee_printf("Iterations/Sec : %f\n", - default_num_contexts * results[0].iterations - / time_in_secs(total_time)); -#else - ee_printf("Total time (secs): %d\n", time_in_secs(total_time)); - if (time_in_secs(total_time) > 0) - ee_printf("Iterations/Sec : %d\n", - default_num_contexts * results[0].iterations - / time_in_secs(total_time)); -#endif - if (time_in_secs(total_time) < 10) - { - ee_printf( - "ERROR! Must execute for at least 10 secs for a valid result!\n"); - total_errors++; - } - - ee_printf("Iterations : %lu\n", - (long unsigned)default_num_contexts * results[0].iterations); - ee_printf("Compiler version : %s\n", COMPILER_VERSION); - ee_printf("Compiler flags : %s\n", COMPILER_FLAGS); -#if (MULTITHREAD > 1) - ee_printf("Parallel %s : %d\n", PARALLEL_METHOD, default_num_contexts); -#endif - ee_printf("Memory location : %s\n", MEM_LOCATION); - /* output for verification */ - ee_printf("seedcrc : 0x%04x\n", seedcrc); - if (results[0].execs & ID_LIST) - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crclist : 0x%04x\n", i, results[i].crclist); - if (results[0].execs & ID_MATRIX) - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crcmatrix : 0x%04x\n", i, results[i].crcmatrix); - if (results[0].execs & ID_STATE) - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crcstate : 0x%04x\n", i, results[i].crcstate); - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crcfinal : 0x%04x\n", i, results[i].crc); - if (total_errors == 0) - { - ee_printf( - "Correct operation validated. See README.md for run and reporting " - "rules.\n"); -#if HAS_FLOAT - if (known_id == 3) - { - ee_printf("CoreMark 1.0 : %f / %s %s", - default_num_contexts * results[0].iterations - / time_in_secs(total_time), - COMPILER_VERSION, - COMPILER_FLAGS); -#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC) - ee_printf(" / %s", MEM_LOCATION); -#else - ee_printf(" / %s", mem_name[MEM_METHOD]); -#endif - -#if (MULTITHREAD > 1) - ee_printf(" / %d:%s", default_num_contexts, PARALLEL_METHOD); -#endif - ee_printf("\n"); - } -#endif - } - if (total_errors > 0) - ee_printf("Errors detected\n"); - if (total_errors < 0) - ee_printf( - "Cannot validate operation for these seed values, please compare " - "with results on a known platform.\n"); - -#if (MEM_METHOD == MEM_MALLOC) - for (i = 0; i < MULTITHREAD; i++) - portable_free(results[i].memblock[0]); -#endif - /* And last call any target specific code for finalizing */ - portable_fini(&(results[0].port)); - - return MAIN_RETURN_VAL; -} diff --git a/cv32e40x/tests/programs/custom/coremark/core_matrix.c b/cv32e40x/tests/programs/custom/coremark/core_matrix.c deleted file mode 100644 index 505f456f76..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/core_matrix.c +++ /dev/null @@ -1,360 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - - -#include "coremark.h" -/* -Topic: Description - Matrix manipulation benchmark - - This very simple algorithm forms the basis of many more complex -algorithms. - - The tight inner loop is the focus of many optimizations (compiler as -well as hardware based) and is thus relevant for embedded processing. - - The total available data space will be divided to 3 parts: - NxN Matrix A - initialized with small values (upper 3/4 of the bits all -zero). NxN Matrix B - initialized with medium values (upper half of the bits all -zero). NxN Matrix C - used for the result. - - The actual values for A and B must be derived based on input that is not -available at compile time. -*/ -ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val); -ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval); -void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val); -void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); -void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); -void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); -void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val); - -#define matrix_test_next(x) (x + 1) -#define matrix_clip(x, y) ((y) ? (x)&0x0ff : (x)&0x0ffff) -#define matrix_big(x) (0xf000 | (x)) -#define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff << (to)))) - -#if CORE_DEBUG -void -printmat(MATDAT *A, ee_u32 N, char *name) -{ - ee_u32 i, j; - ee_printf("Matrix %s [%dx%d]:\n", name, N, N); - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - if (j != 0) - ee_printf(","); - ee_printf("%d", A[i * N + j]); - } - ee_printf("\n"); - } -} -void -printmatC(MATRES *C, ee_u32 N, char *name) -{ - ee_u32 i, j; - ee_printf("Matrix %s [%dx%d]:\n", name, N, N); - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - if (j != 0) - ee_printf(","); - ee_printf("%d", C[i * N + j]); - } - ee_printf("\n"); - } -} -#endif -/* Function: core_bench_matrix - Benchmark function - - Iterate N times, - changing the matrix values slightly by a constant amount each time. -*/ -ee_u16 -core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) -{ - ee_u32 N = p->N; - MATRES *C = p->C; - MATDAT *A = p->A; - MATDAT *B = p->B; - MATDAT val = (MATDAT)seed; - - crc = crc16(matrix_test(N, C, A, B, val), crc); - - return crc; -} - -/* Function: matrix_test - Perform matrix manipulation. - - Parameters: - N - Dimensions of the matrix. - C - memory for result matrix. - A - input matrix - B - operator matrix (not changed during operations) - - Returns: - A CRC value that captures all results calculated in the function. - In particular, crc of the value calculated on the result matrix - after each step by . - - Operation: - - 1 - Add a constant value to all elements of a matrix. - 2 - Multiply a matrix by a constant. - 3 - Multiply a matrix by a vector. - 4 - Multiply a matrix by a matrix. - 5 - Add a constant value to all elements of a matrix. - - After the last step, matrix A is back to original contents. -*/ -ee_s16 -matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) -{ - ee_u16 crc = 0; - MATDAT clipval = matrix_big(val); - - matrix_add_const(N, A, val); /* make sure data changes */ -#if CORE_DEBUG - printmat(A, N, "matrix_add_const"); -#endif - matrix_mul_const(N, C, A, val); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_const"); -#endif - matrix_mul_vect(N, C, A, B); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_vect"); -#endif - matrix_mul_matrix(N, C, A, B); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_matrix"); -#endif - matrix_mul_matrix_bitextract(N, C, A, B); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_matrix_bitextract"); -#endif - - matrix_add_const(N, A, -val); /* return matrix to initial value */ - return crc; -} - -/* Function : matrix_init - Initialize the memory block for matrix benchmarking. - - Parameters: - blksize - Size of memory to be initialized. - memblk - Pointer to memory block. - seed - Actual values chosen depend on the seed parameter. - p - pointers to containing initialized matrixes. - - Returns: - Matrix dimensions. - - Note: - The seed parameter MUST be supplied from a source that cannot be - determined at compile time -*/ -ee_u32 -core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) -{ - ee_u32 N = 0; - MATDAT *A; - MATDAT *B; - ee_s32 order = 1; - MATDAT val; - ee_u32 i = 0, j = 0; - if (seed == 0) - seed = 1; - while (j < blksize) - { - i++; - j = i * i * 2 * 4; - } - N = i - 1; - A = (MATDAT *)align_mem(memblk); - B = A + N * N; - - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - seed = ((order * seed) % 65536); - val = (seed + order); - val = matrix_clip(val, 0); - B[i * N + j] = val; - val = (val + order); - val = matrix_clip(val, 1); - A[i * N + j] = val; - order++; - } - } - - p->A = A; - p->B = B; - p->C = (MATRES *)align_mem(B + N * N); - p->N = N; -#if CORE_DEBUG - printmat(A, N, "A"); - printmat(B, N, "B"); -#endif - return N; -} - -/* Function: matrix_sum - Calculate a function that depends on the values of elements in the - matrix. - - For each element, accumulate into a temporary variable. - - As long as this value is under the parameter clipval, - add 1 to the result if the element is bigger then the previous. - - Otherwise, reset the accumulator and add 10 to the result. -*/ -ee_s16 -matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) -{ - MATRES tmp = 0, prev = 0, cur = 0; - ee_s16 ret = 0; - ee_u32 i, j; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - cur = C[i * N + j]; - tmp += cur; - if (tmp > clipval) - { - ret += 10; - tmp = 0; - } - else - { - ret += (cur > prev) ? 1 : 0; - } - prev = cur; - } - } - return ret; -} - -/* Function: matrix_mul_const - Multiply a matrix by a constant. - This could be used as a scaler for instance. -*/ -void -matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) -{ - ee_u32 i, j; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - C[i * N + j] = (MATRES)A[i * N + j] * (MATRES)val; - } - } -} - -/* Function: matrix_add_const - Add a constant value to all elements of a matrix. -*/ -void -matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) -{ - ee_u32 i, j; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - A[i * N + j] += val; - } - } -} - -/* Function: matrix_mul_vect - Multiply a matrix by a vector. - This is common in many simple filters (e.g. fir where a vector of - coefficients is applied to the matrix.) -*/ -void -matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) -{ - ee_u32 i, j; - for (i = 0; i < N; i++) - { - C[i] = 0; - for (j = 0; j < N; j++) - { - C[i] += (MATRES)A[i * N + j] * (MATRES)B[j]; - } - } -} - -/* Function: matrix_mul_matrix - Multiply a matrix by a matrix. - Basic code is used in many algorithms, mostly with minor changes such as - scaling. -*/ -void -matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) -{ - ee_u32 i, j, k; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - C[i * N + j] = 0; - for (k = 0; k < N; k++) - { - C[i * N + j] += (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; - } - } - } -} - -/* Function: matrix_mul_matrix_bitextract - Multiply a matrix by a matrix, and extract some bits from the result. - Basic code is used in many algorithms, mostly with minor changes such as - scaling. -*/ -void -matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) -{ - ee_u32 i, j, k; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - C[i * N + j] = 0; - for (k = 0; k < N; k++) - { - MATRES tmp = (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; - C[i * N + j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5, 7); - } - } - } -} diff --git a/cv32e40x/tests/programs/custom/coremark/core_portme.c b/cv32e40x/tests/programs/custom/coremark/core_portme.c deleted file mode 100644 index cb60554de4..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/core_portme.c +++ /dev/null @@ -1,105 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 - -#include "coremark.h" -#include "corev_uvmt.h" - -#define TICKS_ADDR (CV_VP_CYCLE_COUNTER_BASE) - -ee_u32 default_num_contexts = 1; - -static CORETIMETYPE start_time_val, stop_time_val; - -#if VALIDATION_RUN -volatile ee_s32 seed1_volatile = 0x3415; -volatile ee_s32 seed2_volatile = 0x3415; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PERFORMANCE_RUN -volatile ee_s32 seed1_volatile = 0x0; -volatile ee_s32 seed2_volatile = 0x0; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PROFILE_RUN -volatile ee_s32 seed1_volatile = 0x8; -volatile ee_s32 seed2_volatile = 0x8; -volatile ee_s32 seed3_volatile = 0x8; -#endif -volatile ee_s32 seed4_volatile = ITERATIONS; -volatile ee_s32 seed5_volatile = 0; - -void -portable_init(core_portable *p, int *argc, char *argv[]) -{ - // Don't need to do anything here atm. - (void)p; - (void)argc; - (void)argv; -} - -void -portable_fini(core_portable *p) -{ - // Don't need to do anything here atm. - (void)p; -} - -void -start_time(void) -{ - ee_ptr_int *ticks_io = (ee_ptr_int *)TICKS_ADDR; - - start_time_val = *ticks_io; -} - -void -stop_time(void) -{ - ee_ptr_int *ticks_io = (ee_ptr_int *)TICKS_ADDR; - - stop_time_val = *ticks_io; -} - -CORE_TICKS -get_time(void) -{ - return (stop_time_val - start_time_val); -} - -secs_ret -time_in_secs(CORE_TICKS ticks) -{ - return ticks; // NB! Not implemented. Score is derivable from cycle count. -} diff --git a/cv32e40x/tests/programs/custom/coremark/core_portme.h b/cv32e40x/tests/programs/custom/coremark/core_portme.h deleted file mode 100644 index 5a15066a50..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/core_portme.h +++ /dev/null @@ -1,93 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -// Copyright 2020 OpenHW Group -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 - -#include -#include - -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef ee_u32 ee_ptr_int; -typedef size_t ee_size_t; - -typedef ee_u32 CORE_TICKS; - -typedef struct CORE_PORTABLE_S -{ - ee_u8 portable_id; -} core_portable; - -#ifndef MULTITHREAD -#define MULTITHREAD 1 // 1 means single-core -#define USE_PTHREAD 0 -#define USE_FORK 0 -#define USE_SOCKET 0 -#endif - -#ifndef COMPILER_VERSION -#ifdef __GNUC__ -#define COMPILER_VERSION "GCC"__VERSION__ -#else -#define COMPILER_VERSION "Undefined non-gcc compiler used" -#endif -#endif - -#ifndef COMPILER_FLAGS -#define COMPILER_FLAGS FLAGS_STR -#endif - -#ifndef MEM_LOCATION -#define MEM_LOCATION "" -#endif - -#ifndef SEED_METHOD -#define SEED_METHOD SEED_VOLATILE -#endif - -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3)) - -#define CORETIMETYPE ee_u32 - -extern ee_u32 default_num_contexts; - -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); diff --git a/cv32e40x/tests/programs/custom/coremark/core_state.c b/cv32e40x/tests/programs/custom/coremark/core_state.c deleted file mode 100644 index 6eb0d60e83..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/core_state.c +++ /dev/null @@ -1,331 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - - -#include "coremark.h" -/* local functions */ -enum CORE_STATE core_state_transition(ee_u8 **instr, ee_u32 *transition_count); - -/* -Topic: Description - Simple state machines like this one are used in many embedded products. - - For more complex state machines, sometimes a state transition table -implementation is used instead, trading speed of direct coding for ease of -maintenance. - - Since the main goal of using a state machine in CoreMark is to excercise -the switch/if behaviour, we are using a small moore machine. - - In particular, this machine tests type of string input, - trying to determine whether the input is a number or something else. - (see core_state.png). -*/ - -/* Function: core_bench_state - Benchmark function - - Go over the input twice, once direct, and once after introducing some - corruption. -*/ -ee_u16 -core_bench_state(ee_u32 blksize, - ee_u8 *memblock, - ee_s16 seed1, - ee_s16 seed2, - ee_s16 step, - ee_u16 crc) -{ - ee_u32 final_counts[NUM_CORE_STATES]; - ee_u32 track_counts[NUM_CORE_STATES]; - ee_u8 *p = memblock; - ee_u32 i; - -#if CORE_DEBUG - ee_printf("State Bench: %d,%d,%d,%04x\n", seed1, seed2, step, crc); -#endif - for (i = 0; i < NUM_CORE_STATES; i++) - { - final_counts[i] = track_counts[i] = 0; - } - /* run the state machine over the input */ - while (*p != 0) - { - enum CORE_STATE fstate = core_state_transition(&p, track_counts); - final_counts[fstate]++; -#if CORE_DEBUG - ee_printf("%d,", fstate); - } - ee_printf("\n"); -#else - } -#endif - p = memblock; - while (p < (memblock + blksize)) - { /* insert some corruption */ - if (*p != ',') - *p ^= (ee_u8)seed1; - p += step; - } - p = memblock; - /* run the state machine over the input again */ - while (*p != 0) - { - enum CORE_STATE fstate = core_state_transition(&p, track_counts); - final_counts[fstate]++; -#if CORE_DEBUG - ee_printf("%d,", fstate); - } - ee_printf("\n"); -#else - } -#endif - p = memblock; - while (p < (memblock + blksize)) - { /* undo corruption is seed1 and seed2 are equal */ - if (*p != ',') - *p ^= (ee_u8)seed2; - p += step; - } - /* end timing */ - for (i = 0; i < NUM_CORE_STATES; i++) - { - crc = crcu32(final_counts[i], crc); - crc = crcu32(track_counts[i], crc); - } - return crc; -} - -/* Default initialization patterns */ -static ee_u8 *intpat[4] - = { (ee_u8 *)"5012", (ee_u8 *)"1234", (ee_u8 *)"-874", (ee_u8 *)"+122" }; -static ee_u8 *floatpat[4] = { (ee_u8 *)"35.54400", - (ee_u8 *)".1234500", - (ee_u8 *)"-110.700", - (ee_u8 *)"+0.64400" }; -static ee_u8 *scipat[4] = { (ee_u8 *)"5.500e+3", - (ee_u8 *)"-.123e-2", - (ee_u8 *)"-87e+832", - (ee_u8 *)"+0.6e-12" }; -static ee_u8 *errpat[4] = { (ee_u8 *)"T0.3e-1F", - (ee_u8 *)"-T.T++Tq", - (ee_u8 *)"1T3.4e4z", - (ee_u8 *)"34.0e-T^" }; - -/* Function: core_init_state - Initialize the input data for the state machine. - - Populate the input with several predetermined strings, interspersed. - Actual patterns chosen depend on the seed parameter. - - Note: - The seed parameter MUST be supplied from a source that cannot be - determined at compile time -*/ -void -core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p) -{ - ee_u32 total = 0, next = 0, i; - ee_u8 *buf = 0; -#if CORE_DEBUG - ee_u8 *start = p; - ee_printf("State: %d,%d\n", size, seed); -#endif - size--; - next = 0; - while ((total + next + 1) < size) - { - if (next > 0) - { - for (i = 0; i < next; i++) - *(p + total + i) = buf[i]; - *(p + total + i) = ','; - total += next + 1; - } - seed++; - switch (seed & 0x7) - { - case 0: /* int */ - case 1: /* int */ - case 2: /* int */ - buf = intpat[(seed >> 3) & 0x3]; - next = 4; - break; - case 3: /* float */ - case 4: /* float */ - buf = floatpat[(seed >> 3) & 0x3]; - next = 8; - break; - case 5: /* scientific */ - case 6: /* scientific */ - buf = scipat[(seed >> 3) & 0x3]; - next = 8; - break; - case 7: /* invalid */ - buf = errpat[(seed >> 3) & 0x3]; - next = 8; - break; - default: /* Never happen, just to make some compilers happy */ - break; - } - } - size++; - while (total < size) - { /* fill the rest with 0 */ - *(p + total) = 0; - total++; - } -#if CORE_DEBUG - ee_printf("State Input: %s\n", start); -#endif -} - -static ee_u8 -ee_isdigit(ee_u8 c) -{ - ee_u8 retval; - retval = ((c >= '0') & (c <= '9')) ? 1 : 0; - return retval; -} - -/* Function: core_state_transition - Actual state machine. - - The state machine will continue scanning until either: - 1 - an invalid input is detcted. - 2 - a valid number has been detected. - - The input pointer is updated to point to the end of the token, and the - end state is returned (either specific format determined or invalid). -*/ - -enum CORE_STATE -core_state_transition(ee_u8 **instr, ee_u32 *transition_count) -{ - ee_u8 * str = *instr; - ee_u8 NEXT_SYMBOL; - enum CORE_STATE state = CORE_START; - for (; *str && state != CORE_INVALID; str++) - { - NEXT_SYMBOL = *str; - if (NEXT_SYMBOL == ',') /* end of this input */ - { - str++; - break; - } - switch (state) - { - case CORE_START: - if (ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INT; - } - else if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') - { - state = CORE_S1; - } - else if (NEXT_SYMBOL == '.') - { - state = CORE_FLOAT; - } - else - { - state = CORE_INVALID; - transition_count[CORE_INVALID]++; - } - transition_count[CORE_START]++; - break; - case CORE_S1: - if (ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INT; - transition_count[CORE_S1]++; - } - else if (NEXT_SYMBOL == '.') - { - state = CORE_FLOAT; - transition_count[CORE_S1]++; - } - else - { - state = CORE_INVALID; - transition_count[CORE_S1]++; - } - break; - case CORE_INT: - if (NEXT_SYMBOL == '.') - { - state = CORE_FLOAT; - transition_count[CORE_INT]++; - } - else if (!ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INVALID; - transition_count[CORE_INT]++; - } - break; - case CORE_FLOAT: - if (NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e') - { - state = CORE_S2; - transition_count[CORE_FLOAT]++; - } - else if (!ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INVALID; - transition_count[CORE_FLOAT]++; - } - break; - case CORE_S2: - if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') - { - state = CORE_EXPONENT; - transition_count[CORE_S2]++; - } - else - { - state = CORE_INVALID; - transition_count[CORE_S2]++; - } - break; - case CORE_EXPONENT: - if (ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_SCIENTIFIC; - transition_count[CORE_EXPONENT]++; - } - else - { - state = CORE_INVALID; - transition_count[CORE_EXPONENT]++; - } - break; - case CORE_SCIENTIFIC: - if (!ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INVALID; - transition_count[CORE_INVALID]++; - } - break; - default: - break; - } - } - *instr = str; - return state; -} diff --git a/cv32e40x/tests/programs/custom/coremark/core_util.c b/cv32e40x/tests/programs/custom/coremark/core_util.c deleted file mode 100644 index 88637e8276..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/core_util.c +++ /dev/null @@ -1,250 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - - -#include "coremark.h" -/* Function: get_seed - Get a values that cannot be determined at compile time. - - Since different embedded systems and compilers are used, 3 different - methods are provided: 1 - Using a volatile variable. This method is only - valid if the compiler is forced to generate code that reads the value of a - volatile variable from memory at run time. Please note, if using this method, - you would need to modify core_portme.c to generate training profile. 2 - - Command line arguments. This is the preferred method if command line - arguments are supported. 3 - System function. If none of the first 2 methods - is available on the platform, a system function which is not a stub can be - used. - - e.g. read the value on GPIO pins connected to switches, or invoke - special simulator functions. -*/ -#if (SEED_METHOD == SEED_VOLATILE) -extern volatile ee_s32 seed1_volatile; -extern volatile ee_s32 seed2_volatile; -extern volatile ee_s32 seed3_volatile; -extern volatile ee_s32 seed4_volatile; -extern volatile ee_s32 seed5_volatile; -ee_s32 -get_seed_32(int i) -{ - ee_s32 retval; - switch (i) - { - case 1: - retval = seed1_volatile; - break; - case 2: - retval = seed2_volatile; - break; - case 3: - retval = seed3_volatile; - break; - case 4: - retval = seed4_volatile; - break; - case 5: - retval = seed5_volatile; - break; - default: - retval = 0; - break; - } - return retval; -} -#elif (SEED_METHOD == SEED_ARG) -ee_s32 -parseval(char *valstring) -{ - ee_s32 retval = 0; - ee_s32 neg = 1; - int hexmode = 0; - if (*valstring == '-') - { - neg = -1; - valstring++; - } - if ((valstring[0] == '0') && (valstring[1] == 'x')) - { - hexmode = 1; - valstring += 2; - } - /* first look for digits */ - if (hexmode) - { - while (((*valstring >= '0') && (*valstring <= '9')) - || ((*valstring >= 'a') && (*valstring <= 'f'))) - { - ee_s32 digit = *valstring - '0'; - if (digit > 9) - digit = 10 + *valstring - 'a'; - retval *= 16; - retval += digit; - valstring++; - } - } - else - { - while ((*valstring >= '0') && (*valstring <= '9')) - { - ee_s32 digit = *valstring - '0'; - retval *= 10; - retval += digit; - valstring++; - } - } - /* now add qualifiers */ - if (*valstring == 'K') - retval *= 1024; - if (*valstring == 'M') - retval *= 1024 * 1024; - - retval *= neg; - return retval; -} - -ee_s32 -get_seed_args(int i, int argc, char *argv[]) -{ - if (argc > i) - return parseval(argv[i]); - return 0; -} - -#elif (SEED_METHOD == SEED_FUNC) -/* If using OS based function, you must define and implement the functions below - * in core_portme.h and core_portme.c ! */ -ee_s32 -get_seed_32(int i) -{ - ee_s32 retval; - switch (i) - { - case 1: - retval = portme_sys1(); - break; - case 2: - retval = portme_sys2(); - break; - case 3: - retval = portme_sys3(); - break; - case 4: - retval = portme_sys4(); - break; - case 5: - retval = portme_sys5(); - break; - default: - retval = 0; - break; - } - return retval; -} -#endif - -/* Function: crc* - Service functions to calculate 16b CRC code. - -*/ -ee_u16 -crcu8(ee_u8 data, ee_u16 crc) -{ - ee_u8 i = 0, x16 = 0, carry = 0; - - for (i = 0; i < 8; i++) - { - x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1)); - data >>= 1; - - if (x16 == 1) - { - crc ^= 0x4002; - carry = 1; - } - else - carry = 0; - crc >>= 1; - if (carry) - crc |= 0x8000; - else - crc &= 0x7fff; - } - return crc; -} -ee_u16 -crcu16(ee_u16 newval, ee_u16 crc) -{ - crc = crcu8((ee_u8)(newval), crc); - crc = crcu8((ee_u8)((newval) >> 8), crc); - return crc; -} -ee_u16 -crcu32(ee_u32 newval, ee_u16 crc) -{ - crc = crc16((ee_s16)newval, crc); - crc = crc16((ee_s16)(newval >> 16), crc); - return crc; -} -ee_u16 -crc16(ee_s16 newval, ee_u16 crc) -{ - return crcu16((ee_u16)newval, crc); -} - -ee_u8 -check_data_types() -{ - ee_u8 retval = 0; - if (sizeof(ee_u8) != 1) - { - ee_printf("ERROR: ee_u8 is not an 8b datatype!\n"); - retval++; - } - if (sizeof(ee_u16) != 2) - { - ee_printf("ERROR: ee_u16 is not a 16b datatype!\n"); - retval++; - } - if (sizeof(ee_s16) != 2) - { - ee_printf("ERROR: ee_s16 is not a 16b datatype!\n"); - retval++; - } - if (sizeof(ee_s32) != 4) - { - ee_printf("ERROR: ee_s32 is not a 32b datatype!\n"); - retval++; - } - if (sizeof(ee_u32) != 4) - { - ee_printf("ERROR: ee_u32 is not a 32b datatype!\n"); - retval++; - } - if (sizeof(ee_ptr_int) != sizeof(int *)) - { - ee_printf( - "ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n"); - retval++; - } - if (retval > 0) - { - ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n"); - } - return retval; -} diff --git a/cv32e40x/tests/programs/custom/coremark/coremark.h b/cv32e40x/tests/programs/custom/coremark/coremark.h deleted file mode 100644 index ab9a4e90d0..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/coremark.h +++ /dev/null @@ -1,184 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - - -/* Topic: Description - This file contains declarations of the various benchmark functions. -*/ - -/* Configuration: TOTAL_DATA_SIZE - Define total size for data algorithms will operate on -*/ -#ifndef TOTAL_DATA_SIZE -#define TOTAL_DATA_SIZE 2 * 1000 -#endif - -#define SEED_ARG 0 -#define SEED_FUNC 1 -#define SEED_VOLATILE 2 - -#define MEM_STATIC 0 -#define MEM_MALLOC 1 -#define MEM_STACK 2 - -#include "core_portme.h" - -#if HAS_STDIO -#include -#endif -#if HAS_PRINTF -#define ee_printf printf -#endif - -/* Actual benchmark execution in iterate */ -void *iterate(void *pres); - -/* Typedef: secs_ret - For machines that have floating point support, get number of seconds as - a double. Otherwise an unsigned int. -*/ -#if HAS_FLOAT -typedef double secs_ret; -#else -typedef ee_u32 secs_ret; -#endif - -#if MAIN_HAS_NORETURN -#define MAIN_RETURN_VAL -#define MAIN_RETURN_TYPE void -#else -#define MAIN_RETURN_VAL 0 -#define MAIN_RETURN_TYPE int -#endif - -void start_time(void); -void stop_time(void); -CORE_TICKS get_time(void); -secs_ret time_in_secs(CORE_TICKS ticks); - -/* Misc useful functions */ -ee_u16 crcu8(ee_u8 data, ee_u16 crc); -ee_u16 crc16(ee_s16 newval, ee_u16 crc); -ee_u16 crcu16(ee_u16 newval, ee_u16 crc); -ee_u16 crcu32(ee_u32 newval, ee_u16 crc); -ee_u8 check_data_types(void); -void * portable_malloc(ee_size_t size); -void portable_free(void *p); -ee_s32 parseval(char *valstring); - -/* Algorithm IDS */ -#define ID_LIST (1 << 0) -#define ID_MATRIX (1 << 1) -#define ID_STATE (1 << 2) -#define ALL_ALGORITHMS_MASK (ID_LIST | ID_MATRIX | ID_STATE) -#define NUM_ALGORITHMS 3 - -/* list data structures */ -typedef struct list_data_s -{ - ee_s16 data16; - ee_s16 idx; -} list_data; - -typedef struct list_head_s -{ - struct list_head_s *next; - struct list_data_s *info; -} list_head; - -/*matrix benchmark related stuff */ -#define MATDAT_INT 1 -#if MATDAT_INT -typedef ee_s16 MATDAT; -typedef ee_s32 MATRES; -#else -typedef ee_f16 MATDAT; -typedef ee_f32 MATRES; -#endif - -typedef struct MAT_PARAMS_S -{ - int N; - MATDAT *A; - MATDAT *B; - MATRES *C; -} mat_params; - -/* state machine related stuff */ -/* List of all the possible states for the FSM */ -typedef enum CORE_STATE -{ - CORE_START = 0, - CORE_INVALID, - CORE_S1, - CORE_S2, - CORE_INT, - CORE_FLOAT, - CORE_EXPONENT, - CORE_SCIENTIFIC, - NUM_CORE_STATES -} core_state_e; - -/* Helper structure to hold results */ -typedef struct RESULTS_S -{ - /* inputs */ - ee_s16 seed1; /* Initializing seed */ - ee_s16 seed2; /* Initializing seed */ - ee_s16 seed3; /* Initializing seed */ - void * memblock[4]; /* Pointer to safe memory location */ - ee_u32 size; /* Size of the data */ - ee_u32 iterations; /* Number of iterations to execute */ - ee_u32 execs; /* Bitmask of operations to execute */ - struct list_head_s *list; - mat_params mat; - /* outputs */ - ee_u16 crc; - ee_u16 crclist; - ee_u16 crcmatrix; - ee_u16 crcstate; - ee_s16 err; - /* ultithread specific */ - core_portable port; -} core_results; - -/* Multicore execution handling */ -#if (MULTITHREAD > 1) -ee_u8 core_start_parallel(core_results *res); -ee_u8 core_stop_parallel(core_results *res); -#endif - -/* list benchmark functions */ -list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed); -ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx); - -/* state benchmark functions */ -void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p); -ee_u16 core_bench_state(ee_u32 blksize, - ee_u8 *memblock, - ee_s16 seed1, - ee_s16 seed2, - ee_s16 step, - ee_u16 crc); - -/* matrix benchmark functions */ -ee_u32 core_init_matrix(ee_u32 blksize, - void * memblk, - ee_s32 seed, - mat_params *p); -ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc); diff --git a/cv32e40x/tests/programs/custom/coremark/test.yaml b/cv32e40x/tests/programs/custom/coremark/test.yaml deleted file mode 100644 index 61350068e7..0000000000 --- a/cv32e40x/tests/programs/custom/coremark/test.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright 2020, 2023 OpenHW Group -# Copyright 2020 Silicon Labs, Inc. -# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.1 -name: coremark -uvm_test: uvmt_cv32e40x_firmware_test_c -default_cflags: > - -O3 - -mabi=ilp32 - -march=rv32im - -falign-functions=16 - -funroll-all-loops - -falign-jumps=4 - -finline-functions - -Wall - -static - -pedantic - -DPERFORMANCE_RUN=1 - -DITERATIONS=10 - -DFLAGS_STR=\""-mabi=ilp32 -O3 -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -pedanic -nostartfiles -static"\" -description: > - Runs the CoreMark benchmark diff --git a/cv32e40x/tests/programs/custom/csr_instr_asm/csr_instr_asm.S b/cv32e40x/tests/programs/custom/csr_instr_asm/csr_instr_asm.S deleted file mode 100644 index e97f153e3a..0000000000 --- a/cv32e40x/tests/programs/custom/csr_instr_asm/csr_instr_asm.S +++ /dev/null @@ -1,6320 +0,0 @@ -################################################################################ -# -# Copyright 2020 OpenHW Group -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 -# -################################################################################ -# Script-generated, brute force and ignorance approach to running all legal CSR -# instructions for the MSCRATCH CSR. Implements all 6 real (not pseudo) CSR -# access instructions. THIS TEST IS NOT SELF CHECKING: you must run against a -# reference model to check results. -################################################################################ -#include "corev_uvmt.h" - -.include "user_define.h" -.section .text.start -.globl _start -.section .text -#.include "user_init.s" -.type _start, @function - -_start: - j _start_main - -.globl _start_main -.section .text -_start_main: - - #define EXP_MISA 0x40001104 - -# CSR 0x340 is a 32-bit R/W scratch-pad - # Immediates - csrrci x0, 0x340, 0x0 - csrrsi x0, 0x340, 0x0 - csrrwi x0, 0x340, 0x0 - csrrci x0, 0x340, 0x1 - csrrsi x0, 0x340, 0x1 - csrrwi x0, 0x340, 0x1 - csrrci x0, 0x340, 0x2 - csrrsi x0, 0x340, 0x2 - csrrwi x0, 0x340, 0x2 - csrrci x0, 0x340, 0x3 - csrrsi x0, 0x340, 0x3 - csrrwi x0, 0x340, 0x3 - csrrci x0, 0x340, 0x4 - csrrsi x0, 0x340, 0x4 - csrrwi x0, 0x340, 0x4 - csrrci x0, 0x340, 0x5 - csrrsi x0, 0x340, 0x5 - csrrwi x0, 0x340, 0x5 - csrrci x0, 0x340, 0x6 - csrrsi x0, 0x340, 0x6 - csrrwi x0, 0x340, 0x6 - csrrci x0, 0x340, 0x7 - csrrsi x0, 0x340, 0x7 - csrrwi x0, 0x340, 0x7 - csrrci x0, 0x340, 0x8 - csrrsi x0, 0x340, 0x8 - csrrwi x0, 0x340, 0x8 - csrrci x0, 0x340, 0x9 - csrrsi x0, 0x340, 0x9 - csrrwi x0, 0x340, 0x9 - csrrci x0, 0x340, 0xa - csrrsi x0, 0x340, 0xa - csrrwi x0, 0x340, 0xa - csrrci x0, 0x340, 0xb - csrrsi x0, 0x340, 0xb - csrrwi x0, 0x340, 0xb - csrrci x0, 0x340, 0xc - csrrsi x0, 0x340, 0xc - csrrwi x0, 0x340, 0xc - csrrci x0, 0x340, 0xd - csrrsi x0, 0x340, 0xd - csrrwi x0, 0x340, 0xd - csrrci x0, 0x340, 0xe - csrrsi x0, 0x340, 0xe - csrrwi x0, 0x340, 0xe - csrrci x0, 0x340, 0xf - csrrsi x0, 0x340, 0xf - csrrwi x0, 0x340, 0xf - csrrci x0, 0x340, 0x10 - csrrsi x0, 0x340, 0x10 - csrrwi x0, 0x340, 0x10 - csrrci x0, 0x340, 0x11 - csrrsi x0, 0x340, 0x11 - csrrwi x0, 0x340, 0x12 - csrrci x0, 0x340, 0x12 - csrrsi x0, 0x340, 0x12 - csrrwi x0, 0x340, 0x12 - csrrci x0, 0x340, 0x13 - csrrsi x0, 0x340, 0x13 - csrrwi x0, 0x340, 0x13 - csrrci x0, 0x340, 0x14 - csrrsi x0, 0x340, 0x14 - csrrwi x0, 0x340, 0x14 - csrrci x0, 0x340, 0x15 - csrrsi x0, 0x340, 0x15 - csrrwi x0, 0x340, 0x15 - csrrci x0, 0x340, 0x16 - csrrsi x0, 0x340, 0x16 - csrrwi x0, 0x340, 0x16 - csrrci x0, 0x340, 0x17 - csrrsi x0, 0x340, 0x17 - csrrwi x0, 0x340, 0x17 - csrrci x0, 0x340, 0x18 - csrrsi x0, 0x340, 0x18 - csrrwi x0, 0x340, 0x18 - csrrci x0, 0x340, 0x19 - csrrsi x0, 0x340, 0x19 - csrrwi x0, 0x340, 0x19 - csrrci x0, 0x340, 0x1a - csrrsi x0, 0x340, 0x1a - csrrwi x0, 0x340, 0x1a - csrrci x0, 0x340, 0x1b - csrrsi x0, 0x340, 0x1b - csrrwi x0, 0x340, 0x1b - csrrci x0, 0x340, 0x1c - csrrsi x0, 0x340, 0x1c - csrrwi x0, 0x340, 0x1c - csrrci x0, 0x340, 0x1d - csrrsi x0, 0x340, 0x1d - csrrwi x0, 0x340, 0x1d - csrrci x0, 0x340, 0x1e - csrrsi x0, 0x340, 0x1e - csrrwi x0, 0x340, 0x1e - csrrci x0, 0x340, 0x1f - csrrsi x0, 0x340, 0x1f - csrrwi x0, 0x340, 0x1f - - csrrci x1, 0x340, 0x0 - csrrsi x1, 0x340, 0x0 - csrrwi x1, 0x340, 0x0 - csrrci x1, 0x340, 0x1 - csrrsi x1, 0x340, 0x1 - csrrwi x1, 0x340, 0x1 - csrrci x1, 0x340, 0x2 - csrrsi x1, 0x340, 0x2 - csrrwi x1, 0x340, 0x2 - csrrci x1, 0x340, 0x3 - csrrsi x1, 0x340, 0x3 - csrrwi x1, 0x340, 0x3 - csrrci x1, 0x340, 0x4 - csrrsi x1, 0x340, 0x4 - csrrwi x1, 0x340, 0x4 - csrrci x1, 0x340, 0x5 - csrrsi x1, 0x340, 0x5 - csrrwi x1, 0x340, 0x5 - csrrci x1, 0x340, 0x6 - csrrsi x1, 0x340, 0x6 - csrrwi x1, 0x340, 0x6 - csrrci x1, 0x340, 0x7 - csrrsi x1, 0x340, 0x7 - csrrwi x1, 0x340, 0x7 - csrrci x1, 0x340, 0x8 - csrrsi x1, 0x340, 0x8 - csrrwi x1, 0x340, 0x8 - csrrci x1, 0x340, 0x9 - csrrsi x1, 0x340, 0x9 - csrrwi x1, 0x340, 0x9 - csrrci x1, 0x340, 0xa - csrrsi x1, 0x340, 0xa - csrrwi x1, 0x340, 0xa - csrrci x1, 0x340, 0xb - csrrsi x1, 0x340, 0xb - csrrwi x1, 0x340, 0xb - csrrci x1, 0x340, 0xc - csrrsi x1, 0x340, 0xc - csrrwi x1, 0x340, 0xc - csrrci x1, 0x340, 0xd - csrrsi x1, 0x340, 0xd - csrrwi x1, 0x340, 0xd - csrrci x1, 0x340, 0xe - csrrsi x1, 0x340, 0xe - csrrwi x1, 0x340, 0xe - csrrci x1, 0x340, 0xf - csrrsi x1, 0x340, 0xf - csrrwi x1, 0x340, 0xf - csrrci x1, 0x340, 0x10 - csrrsi x1, 0x340, 0x10 - csrrwi x1, 0x340, 0x10 - csrrci x1, 0x340, 0x11 - csrrsi x1, 0x340, 0x11 - csrrwi x1, 0x340, 0x11 - csrrci x1, 0x340, 0x12 - csrrsi x1, 0x340, 0x12 - csrrwi x1, 0x340, 0x12 - csrrci x1, 0x340, 0x13 - csrrsi x1, 0x340, 0x13 - csrrwi x1, 0x340, 0x13 - csrrci x1, 0x340, 0x14 - csrrsi x1, 0x340, 0x14 - csrrwi x1, 0x340, 0x14 - csrrci x1, 0x340, 0x15 - csrrsi x1, 0x340, 0x15 - csrrwi x1, 0x340, 0x15 - csrrci x1, 0x340, 0x16 - csrrsi x1, 0x340, 0x16 - csrrwi x1, 0x340, 0x16 - csrrci x1, 0x340, 0x17 - csrrsi x1, 0x340, 0x17 - csrrwi x1, 0x340, 0x17 - csrrci x1, 0x340, 0x18 - csrrsi x1, 0x340, 0x18 - csrrwi x1, 0x340, 0x18 - csrrci x1, 0x340, 0x19 - csrrsi x1, 0x340, 0x19 - csrrwi x1, 0x340, 0x19 - csrrci x1, 0x340, 0x1a - csrrsi x1, 0x340, 0x1a - csrrwi x1, 0x340, 0x1a - csrrci x1, 0x340, 0x1b - csrrsi x1, 0x340, 0x1b - csrrwi x1, 0x340, 0x1b - csrrci x1, 0x340, 0x1c - csrrsi x1, 0x340, 0x1c - csrrwi x1, 0x340, 0x1c - csrrci x1, 0x340, 0x1d - csrrsi x1, 0x340, 0x1d - csrrwi x1, 0x340, 0x1d - csrrci x1, 0x340, 0x1e - csrrsi x1, 0x340, 0x1e - csrrwi x1, 0x340, 0x1e - csrrci x1, 0x340, 0x1f - csrrsi x1, 0x340, 0x1f - csrrwi x1, 0x340, 0x1f - - csrrci x2, 0x340, 0x0 - csrrsi x2, 0x340, 0x0 - csrrwi x2, 0x340, 0x0 - csrrci x2, 0x340, 0x1 - csrrsi x2, 0x340, 0x1 - csrrwi x2, 0x340, 0x1 - csrrci x2, 0x340, 0x2 - csrrsi x2, 0x340, 0x2 - csrrwi x2, 0x340, 0x2 - csrrci x2, 0x340, 0x3 - csrrsi x2, 0x340, 0x3 - csrrwi x2, 0x340, 0x3 - csrrci x2, 0x340, 0x4 - csrrsi x2, 0x340, 0x4 - csrrwi x2, 0x340, 0x4 - csrrci x2, 0x340, 0x5 - csrrsi x2, 0x340, 0x5 - csrrwi x2, 0x340, 0x5 - csrrci x2, 0x340, 0x6 - csrrsi x2, 0x340, 0x6 - csrrwi x2, 0x340, 0x6 - csrrci x2, 0x340, 0x7 - csrrsi x2, 0x340, 0x7 - csrrwi x2, 0x340, 0x7 - csrrci x2, 0x340, 0x8 - csrrsi x2, 0x340, 0x8 - csrrwi x2, 0x340, 0x8 - csrrci x2, 0x340, 0x9 - csrrsi x2, 0x340, 0x9 - csrrwi x2, 0x340, 0x9 - csrrci x2, 0x340, 0xa - csrrsi x2, 0x340, 0xa - csrrwi x2, 0x340, 0xa - csrrci x2, 0x340, 0xb - csrrsi x2, 0x340, 0xb - csrrwi x2, 0x340, 0xb - csrrci x2, 0x340, 0xc - csrrsi x2, 0x340, 0xc - csrrwi x2, 0x340, 0xc - csrrci x2, 0x340, 0xd - csrrsi x2, 0x340, 0xd - csrrwi x2, 0x340, 0xd - csrrci x2, 0x340, 0xe - csrrsi x2, 0x340, 0xe - csrrwi x2, 0x340, 0xe - csrrci x2, 0x340, 0xf - csrrsi x2, 0x340, 0xf - csrrwi x2, 0x340, 0xf - csrrci x2, 0x340, 0x10 - csrrsi x2, 0x340, 0x10 - csrrwi x2, 0x340, 0x10 - csrrci x2, 0x340, 0x11 - csrrsi x2, 0x340, 0x11 - csrrwi x2, 0x340, 0x11 - csrrci x2, 0x340, 0x12 - csrrsi x2, 0x340, 0x12 - csrrwi x2, 0x340, 0x12 - csrrci x2, 0x340, 0x13 - csrrsi x2, 0x340, 0x13 - csrrwi x2, 0x340, 0x13 - csrrci x2, 0x340, 0x14 - csrrsi x2, 0x340, 0x14 - csrrwi x2, 0x340, 0x14 - csrrci x2, 0x340, 0x15 - csrrsi x2, 0x340, 0x15 - csrrwi x2, 0x340, 0x15 - csrrci x2, 0x340, 0x16 - csrrsi x2, 0x340, 0x16 - csrrwi x2, 0x340, 0x16 - csrrci x2, 0x340, 0x17 - csrrsi x2, 0x340, 0x17 - csrrwi x2, 0x340, 0x17 - csrrci x2, 0x340, 0x18 - csrrsi x2, 0x340, 0x18 - csrrwi x2, 0x340, 0x18 - csrrci x2, 0x340, 0x19 - csrrsi x2, 0x340, 0x19 - csrrwi x2, 0x340, 0x19 - csrrci x2, 0x340, 0x1a - csrrsi x2, 0x340, 0x1a - csrrwi x2, 0x340, 0x1a - csrrci x2, 0x340, 0x1b - csrrsi x2, 0x340, 0x1b - csrrwi x2, 0x340, 0x1b - csrrci x2, 0x340, 0x1c - csrrsi x2, 0x340, 0x1c - csrrwi x2, 0x340, 0x1c - csrrci x2, 0x340, 0x1d - csrrsi x2, 0x340, 0x1d - csrrwi x2, 0x340, 0x1d - csrrci x2, 0x340, 0x1e - csrrsi x2, 0x340, 0x1e - csrrwi x2, 0x340, 0x1e - csrrci x2, 0x340, 0x1f - csrrsi x2, 0x340, 0x1f - csrrwi x2, 0x340, 0x1f - - csrrci x3, 0x340, 0x0 - csrrsi x3, 0x340, 0x0 - csrrwi x3, 0x340, 0x0 - csrrci x3, 0x340, 0x1 - csrrsi x3, 0x340, 0x1 - csrrwi x3, 0x340, 0x1 - csrrci x3, 0x340, 0x2 - csrrsi x3, 0x340, 0x2 - csrrwi x3, 0x340, 0x2 - csrrci x3, 0x340, 0x3 - csrrsi x3, 0x340, 0x3 - csrrwi x3, 0x340, 0x3 - csrrci x3, 0x340, 0x4 - csrrsi x3, 0x340, 0x4 - csrrwi x3, 0x340, 0x4 - csrrci x3, 0x340, 0x5 - csrrsi x3, 0x340, 0x5 - csrrwi x3, 0x340, 0x5 - csrrci x3, 0x340, 0x6 - csrrsi x3, 0x340, 0x6 - csrrwi x3, 0x340, 0x6 - csrrci x3, 0x340, 0x7 - csrrsi x3, 0x340, 0x7 - csrrwi x3, 0x340, 0x7 - csrrci x3, 0x340, 0x8 - csrrsi x3, 0x340, 0x8 - csrrwi x3, 0x340, 0x8 - csrrci x3, 0x340, 0x9 - csrrsi x3, 0x340, 0x9 - csrrwi x3, 0x340, 0x9 - csrrci x3, 0x340, 0xa - csrrsi x3, 0x340, 0xa - csrrwi x3, 0x340, 0xa - csrrci x3, 0x340, 0xb - csrrsi x3, 0x340, 0xb - csrrwi x3, 0x340, 0xb - csrrci x3, 0x340, 0xc - csrrsi x3, 0x340, 0xc - csrrwi x3, 0x340, 0xc - csrrci x3, 0x340, 0xd - csrrsi x3, 0x340, 0xd - csrrwi x3, 0x340, 0xd - csrrci x3, 0x340, 0xe - csrrsi x3, 0x340, 0xe - csrrwi x3, 0x340, 0xe - csrrci x3, 0x340, 0xf - csrrsi x3, 0x340, 0xf - csrrwi x3, 0x340, 0xf - csrrci x3, 0x340, 0x10 - csrrsi x3, 0x340, 0x10 - csrrwi x3, 0x340, 0x10 - csrrci x3, 0x340, 0x11 - csrrsi x3, 0x340, 0x11 - csrrwi x3, 0x340, 0x11 - csrrci x3, 0x340, 0x12 - csrrsi x3, 0x340, 0x12 - csrrwi x3, 0x340, 0x12 - csrrci x3, 0x340, 0x13 - csrrsi x3, 0x340, 0x13 - csrrwi x3, 0x340, 0x13 - csrrci x3, 0x340, 0x14 - csrrsi x3, 0x340, 0x14 - csrrwi x3, 0x340, 0x14 - csrrci x3, 0x340, 0x15 - csrrsi x3, 0x340, 0x15 - csrrwi x3, 0x340, 0x15 - csrrci x3, 0x340, 0x16 - csrrsi x3, 0x340, 0x16 - csrrwi x3, 0x340, 0x16 - csrrci x3, 0x340, 0x17 - csrrsi x3, 0x340, 0x17 - csrrwi x3, 0x340, 0x17 - csrrci x3, 0x340, 0x18 - csrrsi x3, 0x340, 0x18 - csrrwi x3, 0x340, 0x18 - csrrci x3, 0x340, 0x19 - csrrsi x3, 0x340, 0x19 - csrrwi x3, 0x340, 0x19 - csrrci x3, 0x340, 0x1a - csrrsi x3, 0x340, 0x1a - csrrwi x3, 0x340, 0x1a - csrrci x3, 0x340, 0x1b - csrrsi x3, 0x340, 0x1b - csrrwi x3, 0x340, 0x1b - csrrci x3, 0x340, 0x1c - csrrsi x3, 0x340, 0x1c - csrrwi x3, 0x340, 0x1c - csrrci x3, 0x340, 0x1d - csrrsi x3, 0x340, 0x1d - csrrwi x3, 0x340, 0x1d - csrrci x3, 0x340, 0x1e - csrrsi x3, 0x340, 0x1e - csrrwi x3, 0x340, 0x1e - csrrci x3, 0x340, 0x1f - csrrsi x3, 0x340, 0x1f - csrrwi x3, 0x340, 0x1f - - csrrci x4, 0x340, 0x0 - csrrsi x4, 0x340, 0x0 - csrrwi x4, 0x340, 0x0 - csrrci x4, 0x340, 0x1 - csrrsi x4, 0x340, 0x1 - csrrwi x4, 0x340, 0x1 - csrrci x4, 0x340, 0x2 - csrrsi x4, 0x340, 0x2 - csrrwi x4, 0x340, 0x2 - csrrci x4, 0x340, 0x3 - csrrsi x4, 0x340, 0x3 - csrrwi x4, 0x340, 0x3 - csrrci x4, 0x340, 0x4 - csrrsi x4, 0x340, 0x4 - csrrwi x4, 0x340, 0x4 - csrrci x4, 0x340, 0x5 - csrrsi x4, 0x340, 0x5 - csrrwi x4, 0x340, 0x5 - csrrci x4, 0x340, 0x6 - csrrsi x4, 0x340, 0x6 - csrrwi x4, 0x340, 0x6 - csrrci x4, 0x340, 0x7 - csrrsi x4, 0x340, 0x7 - csrrwi x4, 0x340, 0x7 - csrrci x4, 0x340, 0x8 - csrrsi x4, 0x340, 0x8 - csrrwi x4, 0x340, 0x8 - csrrci x4, 0x340, 0x9 - csrrsi x4, 0x340, 0x9 - csrrwi x4, 0x340, 0x9 - csrrci x4, 0x340, 0xa - csrrsi x4, 0x340, 0xa - csrrwi x4, 0x340, 0xa - csrrci x4, 0x340, 0xb - csrrsi x4, 0x340, 0xb - csrrwi x4, 0x340, 0xb - csrrci x4, 0x340, 0xc - csrrsi x4, 0x340, 0xc - csrrwi x4, 0x340, 0xc - csrrci x4, 0x340, 0xd - csrrsi x4, 0x340, 0xd - csrrwi x4, 0x340, 0xd - csrrci x4, 0x340, 0xe - csrrsi x4, 0x340, 0xe - csrrwi x4, 0x340, 0xe - csrrci x4, 0x340, 0xf - csrrsi x4, 0x340, 0xf - csrrwi x4, 0x340, 0xf - csrrci x4, 0x340, 0x10 - csrrsi x4, 0x340, 0x10 - csrrwi x4, 0x340, 0x10 - csrrci x4, 0x340, 0x11 - csrrsi x4, 0x340, 0x11 - csrrwi x4, 0x340, 0x11 - csrrci x4, 0x340, 0x12 - csrrsi x4, 0x340, 0x12 - csrrwi x4, 0x340, 0x12 - csrrci x4, 0x340, 0x13 - csrrsi x4, 0x340, 0x13 - csrrwi x4, 0x340, 0x13 - csrrci x4, 0x340, 0x14 - csrrsi x4, 0x340, 0x14 - csrrwi x4, 0x340, 0x14 - csrrci x4, 0x340, 0x15 - csrrsi x4, 0x340, 0x15 - csrrwi x4, 0x340, 0x15 - csrrci x4, 0x340, 0x16 - csrrsi x4, 0x340, 0x16 - csrrwi x4, 0x340, 0x16 - csrrci x4, 0x340, 0x17 - csrrsi x4, 0x340, 0x17 - csrrwi x4, 0x340, 0x17 - csrrci x4, 0x340, 0x18 - csrrsi x4, 0x340, 0x18 - csrrwi x4, 0x340, 0x18 - csrrci x4, 0x340, 0x19 - csrrsi x4, 0x340, 0x19 - csrrwi x4, 0x340, 0x19 - csrrci x4, 0x340, 0x1a - csrrsi x4, 0x340, 0x1a - csrrwi x4, 0x340, 0x1a - csrrci x4, 0x340, 0x1b - csrrsi x4, 0x340, 0x1b - csrrwi x4, 0x340, 0x1b - csrrci x4, 0x340, 0x1c - csrrsi x4, 0x340, 0x1c - csrrwi x4, 0x340, 0x1c - csrrci x4, 0x340, 0x1d - csrrsi x4, 0x340, 0x1d - csrrwi x4, 0x340, 0x1d - csrrci x4, 0x340, 0x1e - csrrsi x4, 0x340, 0x1e - csrrwi x4, 0x340, 0x1e - csrrci x4, 0x340, 0x1f - csrrsi x4, 0x340, 0x1f - csrrwi x4, 0x340, 0x1f - - csrrci x5, 0x340, 0x0 - csrrsi x5, 0x340, 0x0 - csrrwi x5, 0x340, 0x0 - csrrci x5, 0x340, 0x1 - csrrsi x5, 0x340, 0x1 - csrrwi x5, 0x340, 0x1 - csrrci x5, 0x340, 0x2 - csrrsi x5, 0x340, 0x2 - csrrwi x5, 0x340, 0x2 - csrrci x5, 0x340, 0x3 - csrrsi x5, 0x340, 0x3 - csrrwi x5, 0x340, 0x3 - csrrci x5, 0x340, 0x4 - csrrsi x5, 0x340, 0x4 - csrrwi x5, 0x340, 0x4 - csrrci x5, 0x340, 0x5 - csrrsi x5, 0x340, 0x5 - csrrwi x5, 0x340, 0x5 - csrrci x5, 0x340, 0x6 - csrrsi x5, 0x340, 0x6 - csrrwi x5, 0x340, 0x6 - csrrci x5, 0x340, 0x7 - csrrsi x5, 0x340, 0x7 - csrrwi x5, 0x340, 0x7 - csrrci x5, 0x340, 0x8 - csrrsi x5, 0x340, 0x8 - csrrwi x5, 0x340, 0x8 - csrrci x5, 0x340, 0x9 - csrrsi x5, 0x340, 0x9 - csrrwi x5, 0x340, 0x9 - csrrci x5, 0x340, 0xa - csrrsi x5, 0x340, 0xa - csrrwi x5, 0x340, 0xa - csrrci x5, 0x340, 0xb - csrrsi x5, 0x340, 0xb - csrrwi x5, 0x340, 0xb - csrrci x5, 0x340, 0xc - csrrsi x5, 0x340, 0xc - csrrwi x5, 0x340, 0xc - csrrci x5, 0x340, 0xd - csrrsi x5, 0x340, 0xd - csrrwi x5, 0x340, 0xd - csrrci x5, 0x340, 0xe - csrrsi x5, 0x340, 0xe - csrrwi x5, 0x340, 0xe - csrrci x5, 0x340, 0xf - csrrsi x5, 0x340, 0xf - csrrwi x5, 0x340, 0xf - csrrci x5, 0x340, 0x10 - csrrsi x5, 0x340, 0x10 - csrrwi x5, 0x340, 0x10 - csrrci x5, 0x340, 0x11 - csrrsi x5, 0x340, 0x11 - csrrwi x5, 0x340, 0x11 - csrrci x5, 0x340, 0x12 - csrrsi x5, 0x340, 0x12 - csrrwi x5, 0x340, 0x12 - csrrci x5, 0x340, 0x13 - csrrsi x5, 0x340, 0x13 - csrrwi x5, 0x340, 0x13 - csrrci x5, 0x340, 0x14 - csrrsi x5, 0x340, 0x14 - csrrwi x5, 0x340, 0x14 - csrrci x5, 0x340, 0x15 - csrrsi x5, 0x340, 0x15 - csrrwi x5, 0x340, 0x15 - csrrci x5, 0x340, 0x16 - csrrsi x5, 0x340, 0x16 - csrrwi x5, 0x340, 0x16 - csrrci x5, 0x340, 0x17 - csrrsi x5, 0x340, 0x17 - csrrwi x5, 0x340, 0x17 - csrrci x5, 0x340, 0x18 - csrrsi x5, 0x340, 0x18 - csrrwi x5, 0x340, 0x18 - csrrci x5, 0x340, 0x19 - csrrsi x5, 0x340, 0x19 - csrrwi x5, 0x340, 0x19 - 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csrrwi x30, 0x340, 0x16 - csrrci x30, 0x340, 0x17 - csrrsi x30, 0x340, 0x17 - csrrwi x30, 0x340, 0x17 - csrrci x30, 0x340, 0x18 - csrrsi x30, 0x340, 0x18 - csrrwi x30, 0x340, 0x18 - csrrci x30, 0x340, 0x19 - csrrsi x30, 0x340, 0x19 - csrrwi x30, 0x340, 0x19 - csrrci x30, 0x340, 0x1a - csrrsi x30, 0x340, 0x1a - csrrwi x30, 0x340, 0x1a - csrrci x30, 0x340, 0x1b - csrrsi x30, 0x340, 0x1b - csrrwi x30, 0x340, 0x1b - csrrci x30, 0x340, 0x1c - csrrsi x30, 0x340, 0x1c - csrrwi x30, 0x340, 0x1c - csrrci x30, 0x340, 0x1d - csrrsi x30, 0x340, 0x1d - csrrwi x30, 0x340, 0x1d - csrrci x30, 0x340, 0x1e - csrrsi x30, 0x340, 0x1e - csrrwi x30, 0x340, 0x1e - csrrci x30, 0x340, 0x1f - csrrsi x30, 0x340, 0x1f - csrrwi x30, 0x340, 0x1f - - csrrci x31, 0x340, 0x0 - csrrsi x31, 0x340, 0x0 - csrrwi x31, 0x340, 0x0 - csrrci x31, 0x340, 0x1 - csrrsi x31, 0x340, 0x1 - csrrwi x31, 0x340, 0x1 - csrrci x31, 0x340, 0x2 - csrrsi x31, 0x340, 0x2 - csrrwi x31, 0x340, 0x2 - csrrci x31, 0x340, 0x3 - csrrsi x31, 0x340, 0x3 - csrrwi x31, 0x340, 0x3 - csrrci x31, 0x340, 0x4 - csrrsi x31, 0x340, 0x4 - csrrwi x31, 0x340, 0x4 - csrrci x31, 0x340, 0x5 - csrrsi x31, 0x340, 0x5 - csrrwi x31, 0x340, 0x5 - csrrci x31, 0x340, 0x6 - csrrsi x31, 0x340, 0x6 - csrrwi x31, 0x340, 0x6 - csrrci x31, 0x340, 0x7 - csrrsi x31, 0x340, 0x7 - csrrwi x31, 0x340, 0x7 - csrrci x31, 0x340, 0x8 - csrrsi x31, 0x340, 0x8 - csrrwi x31, 0x340, 0x8 - csrrci x31, 0x340, 0x9 - csrrsi x31, 0x340, 0x9 - csrrwi x31, 0x340, 0x9 - csrrci x31, 0x340, 0xa - csrrsi x31, 0x340, 0xa - csrrwi x31, 0x340, 0xa - csrrci x31, 0x340, 0xb - csrrsi x31, 0x340, 0xb - csrrwi x31, 0x340, 0xb - csrrci x31, 0x340, 0xc - csrrsi x31, 0x340, 0xc - csrrwi x31, 0x340, 0xc - csrrci x31, 0x340, 0xd - csrrsi x31, 0x340, 0xd - csrrwi x31, 0x340, 0xd - csrrci x31, 0x340, 0xe - csrrsi x31, 0x340, 0xe - csrrwi x31, 0x340, 0xe - csrrci x31, 0x340, 0xf - csrrsi x31, 0x340, 0xf - csrrwi x31, 0x340, 0xf - csrrci x31, 0x340, 0x10 - csrrsi x31, 0x340, 0x10 - csrrwi x31, 0x340, 0x10 - csrrci x31, 0x340, 0x11 - csrrsi x31, 0x340, 0x11 - csrrwi x31, 0x340, 0x11 - csrrci x31, 0x340, 0x12 - csrrsi x31, 0x340, 0x12 - csrrwi x31, 0x340, 0x12 - csrrci x31, 0x340, 0x13 - csrrsi x31, 0x340, 0x13 - csrrwi x31, 0x340, 0x13 - csrrci x31, 0x340, 0x14 - csrrsi x31, 0x340, 0x14 - csrrwi x31, 0x340, 0x14 - csrrci x31, 0x340, 0x15 - csrrsi x31, 0x340, 0x15 - csrrwi x31, 0x340, 0x15 - csrrci x31, 0x340, 0x16 - csrrsi x31, 0x340, 0x16 - csrrwi x31, 0x340, 0x16 - csrrci x31, 0x340, 0x17 - csrrsi x31, 0x340, 0x17 - csrrwi x31, 0x340, 0x17 - csrrci x31, 0x340, 0x18 - csrrsi x31, 0x340, 0x18 - csrrwi x31, 0x340, 0x18 - csrrci x31, 0x340, 0x19 - csrrsi x31, 0x340, 0x19 - csrrwi x31, 0x340, 0x19 - csrrci x31, 0x340, 0x1a - csrrsi x31, 0x340, 0x1a - csrrwi x31, 0x340, 0x1a - csrrci x31, 0x340, 0x1b - csrrsi x31, 0x340, 0x1b - csrrwi x31, 0x340, 0x1b - csrrci x31, 0x340, 0x1c - csrrsi x31, 0x340, 0x1c - csrrwi x31, 0x340, 0x1c - csrrci x31, 0x340, 0x1d - csrrsi x31, 0x340, 0x1d - csrrwi x31, 0x340, 0x1d - csrrci x31, 0x340, 0x1e - csrrsi x31, 0x340, 0x1e - csrrwi x31, 0x340, 0x1e - csrrci x31, 0x340, 0x1f - csrrsi x31, 0x340, 0x1f - csrrwi x31, 0x340, 0x1f - - - - # Non-immediates - csrrc x0, 0x340, x0 - csrrs x0, 0x340, x0 - csrrw x0, 0x340, x0 - csrrc x0, 0x340, x1 - csrrs x0, 0x340, x1 - csrrw x0, 0x340, x1 - csrrc x0, 0x340, x2 - csrrs x0, 0x340, x2 - csrrw x0, 0x340, x2 - csrrc x0, 0x340, x3 - csrrs x0, 0x340, x3 - csrrw x0, 0x340, x3 - csrrc x0, 0x340, x4 - csrrs x0, 0x340, x4 - csrrw x0, 0x340, x4 - csrrc x0, 0x340, x5 - csrrs x0, 0x340, x5 - csrrw x0, 0x340, x5 - csrrc x0, 0x340, x6 - csrrs x0, 0x340, x6 - csrrw x0, 0x340, x6 - csrrc x0, 0x340, x7 - csrrs x0, 0x340, x7 - csrrw x0, 0x340, x7 - csrrc x0, 0x340, x8 - csrrs x0, 0x340, x8 - csrrw x0, 0x340, x8 - csrrc x0, 0x340, x9 - csrrs x0, 0x340, x9 - csrrw x0, 0x340, x9 - csrrc x0, 0x340, x10 - csrrs x0, 0x340, x10 - csrrw x0, 0x340, x10 - csrrc x0, 0x340, x11 - csrrs x0, 0x340, x11 - csrrw x0, 0x340, x11 - csrrc x0, 0x340, x12 - csrrs x0, 0x340, x12 - csrrw x0, 0x340, x12 - csrrc x0, 0x340, x13 - csrrs x0, 0x340, x13 - csrrw x0, 0x340, x13 - csrrc x0, 0x340, x14 - csrrs x0, 0x340, x14 - csrrw x0, 0x340, x14 - csrrc x0, 0x340, x15 - csrrs x0, 0x340, x15 - csrrw x0, 0x340, x15 - csrrc x0, 0x340, x16 - csrrs x0, 0x340, x16 - csrrw x0, 0x340, x16 - csrrc x0, 0x340, x17 - csrrs x0, 0x340, x17 - csrrw x0, 0x340, x17 - csrrc x0, 0x340, x18 - csrrs x0, 0x340, x18 - csrrw x0, 0x340, x18 - csrrc x0, 0x340, x19 - csrrs x0, 0x340, x19 - csrrw x0, 0x340, x19 - csrrc x0, 0x340, x20 - csrrs x0, 0x340, x20 - csrrw x0, 0x340, x20 - csrrc x0, 0x340, x21 - csrrs x0, 0x340, x21 - csrrw x0, 0x340, x21 - csrrc x0, 0x340, x22 - csrrs x0, 0x340, x22 - csrrw x0, 0x340, x22 - csrrc x0, 0x340, x23 - csrrs x0, 0x340, x23 - csrrw x0, 0x340, x23 - csrrc x0, 0x340, x24 - csrrs x0, 0x340, x24 - csrrw x0, 0x340, x24 - csrrc x0, 0x340, x25 - csrrs x0, 0x340, x25 - csrrw x0, 0x340, x25 - csrrc x0, 0x340, x26 - csrrs x0, 0x340, x26 - csrrw x0, 0x340, x26 - csrrc x0, 0x340, x27 - csrrs x0, 0x340, x27 - csrrw x0, 0x340, x27 - csrrc x0, 0x340, x28 - csrrs x0, 0x340, x28 - csrrw x0, 0x340, x28 - csrrc x0, 0x340, x29 - csrrs x0, 0x340, x29 - csrrw x0, 0x340, x29 - csrrc x0, 0x340, x30 - csrrs x0, 0x340, x30 - csrrw x0, 0x340, x30 - csrrc x0, 0x340, x31 - csrrs x0, 0x340, x31 - csrrw x0, 0x340, x31 - - csrrc x1, 0x340, x0 - csrrs x1, 0x340, x0 - csrrw x1, 0x340, x0 - csrrc x1, 0x340, x1 - csrrs x1, 0x340, x1 - csrrw x1, 0x340, x1 - csrrc x1, 0x340, x2 - csrrs x1, 0x340, x2 - csrrw x1, 0x340, x2 - csrrc x1, 0x340, x3 - csrrs x1, 0x340, x3 - csrrw x1, 0x340, x3 - csrrc x1, 0x340, x4 - csrrs x1, 0x340, x4 - csrrw x1, 0x340, x4 - csrrc x1, 0x340, x5 - csrrs x1, 0x340, x5 - csrrw x1, 0x340, x5 - csrrc x1, 0x340, x6 - csrrs x1, 0x340, x6 - csrrw x1, 0x340, x6 - csrrc x1, 0x340, x7 - csrrs x1, 0x340, x7 - csrrw x1, 0x340, x7 - csrrc x1, 0x340, x8 - csrrs x1, 0x340, x8 - csrrw x1, 0x340, x8 - csrrc x1, 0x340, x9 - csrrs x1, 0x340, x9 - csrrw x1, 0x340, x9 - csrrc x1, 0x340, x10 - csrrs x1, 0x340, x10 - csrrw x1, 0x340, x10 - csrrc x1, 0x340, x11 - csrrs x1, 0x340, x11 - csrrw x1, 0x340, x11 - csrrc x1, 0x340, x12 - csrrs x1, 0x340, x12 - csrrw x1, 0x340, x12 - csrrc x1, 0x340, x13 - csrrs x1, 0x340, x13 - csrrw x1, 0x340, x13 - csrrc x1, 0x340, x14 - csrrs x1, 0x340, x14 - csrrw x1, 0x340, x14 - csrrc x1, 0x340, x15 - csrrs x1, 0x340, x15 - csrrw x1, 0x340, x15 - csrrc x1, 0x340, x16 - csrrs x1, 0x340, x16 - csrrw x1, 0x340, x16 - csrrc x1, 0x340, x17 - csrrs x1, 0x340, x17 - csrrw x1, 0x340, x17 - csrrc x1, 0x340, x18 - csrrs x1, 0x340, x18 - csrrw x1, 0x340, x18 - csrrc x1, 0x340, x19 - csrrs x1, 0x340, x19 - csrrw x1, 0x340, x19 - csrrc x1, 0x340, x20 - csrrs x1, 0x340, x20 - csrrw x1, 0x340, x20 - csrrc x1, 0x340, x21 - csrrs x1, 0x340, x21 - csrrw x1, 0x340, x21 - csrrc x1, 0x340, x22 - csrrs x1, 0x340, x22 - csrrw x1, 0x340, x22 - csrrc x1, 0x340, x23 - csrrs x1, 0x340, x23 - csrrw x1, 0x340, x23 - csrrc x1, 0x340, x24 - csrrs x1, 0x340, x24 - csrrw x1, 0x340, x24 - csrrc x1, 0x340, x25 - csrrs x1, 0x340, x25 - csrrw x1, 0x340, x25 - csrrc x1, 0x340, x26 - csrrs x1, 0x340, x26 - csrrw x1, 0x340, x26 - csrrc x1, 0x340, x27 - csrrs x1, 0x340, x27 - csrrw x1, 0x340, x27 - csrrc x1, 0x340, x28 - csrrs x1, 0x340, x28 - csrrw x1, 0x340, x28 - csrrc x1, 0x340, x29 - csrrs x1, 0x340, x29 - csrrw x1, 0x340, x29 - csrrc x1, 0x340, x30 - csrrs x1, 0x340, x30 - csrrw x1, 0x340, x30 - csrrc x1, 0x340, x31 - csrrs x1, 0x340, x31 - csrrw x1, 0x340, x31 - - csrrc x2, 0x340, x0 - csrrs x2, 0x340, x0 - csrrw x2, 0x340, x0 - csrrc x2, 0x340, x1 - csrrs x2, 0x340, x1 - csrrw x2, 0x340, x1 - csrrc x2, 0x340, x2 - csrrs x2, 0x340, x2 - csrrw x2, 0x340, x2 - csrrc x2, 0x340, x3 - csrrs x2, 0x340, x3 - csrrw x2, 0x340, x3 - csrrc x2, 0x340, x4 - csrrs x2, 0x340, x4 - csrrw x2, 0x340, x4 - csrrc x2, 0x340, x5 - csrrs x2, 0x340, x5 - csrrw x2, 0x340, x5 - csrrc x2, 0x340, x6 - csrrs x2, 0x340, x6 - csrrw x2, 0x340, x6 - csrrc x2, 0x340, x7 - csrrs x2, 0x340, x7 - csrrw x2, 0x340, x7 - csrrc x2, 0x340, x8 - csrrs x2, 0x340, x8 - csrrw x2, 0x340, x8 - csrrc x2, 0x340, x9 - csrrs x2, 0x340, x9 - csrrw x2, 0x340, x9 - csrrc x2, 0x340, x10 - csrrs x2, 0x340, x10 - csrrw x2, 0x340, x10 - csrrc x2, 0x340, x11 - csrrs x2, 0x340, x11 - csrrw x2, 0x340, x11 - csrrc x2, 0x340, x12 - csrrs x2, 0x340, x12 - csrrw x2, 0x340, x12 - csrrc x2, 0x340, x13 - csrrs x2, 0x340, x13 - csrrw x2, 0x340, x13 - csrrc x2, 0x340, x14 - csrrs x2, 0x340, x14 - csrrw x2, 0x340, x14 - csrrc x2, 0x340, x15 - csrrs x2, 0x340, x15 - csrrw x2, 0x340, x15 - csrrc x2, 0x340, x16 - csrrs x2, 0x340, x16 - csrrw x2, 0x340, x16 - csrrc x2, 0x340, x17 - csrrs x2, 0x340, x17 - csrrw x2, 0x340, x17 - csrrc x2, 0x340, x18 - csrrs x2, 0x340, x18 - csrrw x2, 0x340, x18 - csrrc x2, 0x340, x19 - csrrs x2, 0x340, x19 - csrrw x2, 0x340, x19 - csrrc x2, 0x340, x20 - csrrs x2, 0x340, x20 - csrrw x2, 0x340, x20 - csrrc x2, 0x340, x21 - csrrs x2, 0x340, x21 - csrrw x2, 0x340, x21 - csrrc x2, 0x340, x22 - csrrs x2, 0x340, x22 - csrrw x2, 0x340, x22 - csrrc x2, 0x340, x23 - csrrs x2, 0x340, x23 - csrrw x2, 0x340, x23 - csrrc x2, 0x340, x24 - csrrs x2, 0x340, x24 - csrrw x2, 0x340, x24 - csrrc x2, 0x340, x25 - csrrs x2, 0x340, x25 - csrrw x2, 0x340, x25 - csrrc x2, 0x340, x26 - csrrs x2, 0x340, x26 - csrrw x2, 0x340, x26 - csrrc x2, 0x340, x27 - csrrs x2, 0x340, x27 - csrrw x2, 0x340, x27 - csrrc x2, 0x340, x28 - csrrs x2, 0x340, x28 - csrrw x2, 0x340, x28 - csrrc x2, 0x340, x29 - csrrs x2, 0x340, x29 - csrrw x2, 0x340, x29 - csrrc x2, 0x340, x30 - csrrs x2, 0x340, x30 - csrrw x2, 0x340, x30 - csrrc x2, 0x340, x31 - csrrs x2, 0x340, x31 - csrrw x2, 0x340, x31 - - csrrc x3, 0x340, x0 - csrrs x3, 0x340, x0 - csrrw x3, 0x340, x0 - csrrc x3, 0x340, x1 - csrrs x3, 0x340, x1 - csrrw x3, 0x340, x1 - csrrc x3, 0x340, x2 - csrrs x3, 0x340, x2 - csrrw x3, 0x340, x2 - csrrc x3, 0x340, x3 - csrrs x3, 0x340, x3 - csrrw x3, 0x340, x3 - csrrc x3, 0x340, x4 - csrrs x3, 0x340, x4 - csrrw x3, 0x340, x4 - csrrc x3, 0x340, x5 - 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csrrc x30, 0x340, x2 - csrrs x30, 0x340, x2 - csrrw x30, 0x340, x2 - csrrc x30, 0x340, x3 - csrrs x30, 0x340, x3 - csrrw x30, 0x340, x3 - csrrc x30, 0x340, x4 - csrrs x30, 0x340, x4 - csrrw x30, 0x340, x4 - csrrc x30, 0x340, x5 - csrrs x30, 0x340, x5 - csrrw x30, 0x340, x5 - csrrc x30, 0x340, x6 - csrrs x30, 0x340, x6 - csrrw x30, 0x340, x6 - csrrc x30, 0x340, x7 - csrrs x30, 0x340, x7 - csrrw x30, 0x340, x7 - csrrc x30, 0x340, x8 - csrrs x30, 0x340, x8 - csrrw x30, 0x340, x8 - csrrc x30, 0x340, x9 - csrrs x30, 0x340, x9 - csrrw x30, 0x340, x9 - csrrc x30, 0x340, x10 - csrrs x30, 0x340, x10 - csrrw x30, 0x340, x10 - csrrc x30, 0x340, x11 - csrrs x30, 0x340, x11 - csrrw x30, 0x340, x11 - csrrc x30, 0x340, x12 - csrrs x30, 0x340, x12 - csrrw x30, 0x340, x12 - csrrc x30, 0x340, x13 - csrrs x30, 0x340, x13 - csrrw x30, 0x340, x13 - csrrc x30, 0x340, x14 - csrrs x30, 0x340, x14 - csrrw x30, 0x340, x14 - csrrc x30, 0x340, x15 - csrrs x30, 0x340, x15 - csrrw x30, 0x340, x15 - csrrc x30, 0x340, x16 - csrrs x30, 0x340, x16 - csrrw x30, 0x340, x16 - csrrc x30, 0x340, x17 - csrrs x30, 0x340, x17 - csrrw x30, 0x340, x17 - csrrc x30, 0x340, x18 - csrrs x30, 0x340, x18 - csrrw x30, 0x340, x18 - csrrc x30, 0x340, x19 - csrrs x30, 0x340, x19 - csrrw x30, 0x340, x19 - csrrc x30, 0x340, x20 - csrrs x30, 0x340, x20 - csrrw x30, 0x340, x20 - csrrc x30, 0x340, x21 - csrrs x30, 0x340, x21 - csrrw x30, 0x340, x21 - csrrc x30, 0x340, x22 - csrrs x30, 0x340, x22 - csrrw x30, 0x340, x22 - csrrc x30, 0x340, x23 - csrrs x30, 0x340, x23 - csrrw x30, 0x340, x23 - csrrc x30, 0x340, x24 - csrrs x30, 0x340, x24 - csrrw x30, 0x340, x24 - csrrc x30, 0x340, x25 - csrrs x30, 0x340, x25 - csrrw x30, 0x340, x25 - csrrc x30, 0x340, x26 - csrrs x30, 0x340, x26 - csrrw x30, 0x340, x26 - csrrc x30, 0x340, x27 - csrrs x30, 0x340, x27 - csrrw x30, 0x340, x27 - csrrc x30, 0x340, x28 - csrrs x30, 0x340, x28 - csrrw x30, 0x340, x28 - csrrc x30, 0x340, x29 - csrrs x30, 0x340, x29 - csrrw x30, 0x340, x29 - csrrc x30, 0x340, x30 - csrrs x30, 0x340, x30 - csrrw x30, 0x340, x30 - csrrc x30, 0x340, x31 - csrrs x30, 0x340, x31 - csrrw x30, 0x340, x31 - - csrrc x31, 0x340, x0 - csrrs x31, 0x340, x0 - csrrw x31, 0x340, x0 - csrrc x31, 0x340, x1 - csrrs x31, 0x340, x1 - csrrw x31, 0x340, x1 - csrrc x31, 0x340, x2 - csrrs x31, 0x340, x2 - csrrw x31, 0x340, x2 - csrrc x31, 0x340, x3 - csrrs x31, 0x340, x3 - csrrw x31, 0x340, x3 - csrrc x31, 0x340, x4 - csrrs x31, 0x340, x4 - csrrw x31, 0x340, x4 - csrrc x31, 0x340, x5 - csrrs x31, 0x340, x5 - csrrw x31, 0x340, x5 - csrrc x31, 0x340, x6 - csrrs x31, 0x340, x6 - csrrw x31, 0x340, x6 - csrrc x31, 0x340, x7 - csrrs x31, 0x340, x7 - csrrw x31, 0x340, x7 - csrrc x31, 0x340, x8 - csrrs x31, 0x340, x8 - csrrw x31, 0x340, x8 - csrrc x31, 0x340, x9 - csrrs x31, 0x340, x9 - csrrw x31, 0x340, x9 - csrrc x31, 0x340, x10 - csrrs x31, 0x340, x10 - csrrw x31, 0x340, x10 - csrrc x31, 0x340, x11 - csrrs x31, 0x340, x11 - csrrw x31, 0x340, x11 - csrrc x31, 0x340, x12 - csrrs x31, 0x340, x12 - csrrw x31, 0x340, x12 - csrrc x31, 0x340, x13 - csrrs x31, 0x340, x13 - csrrw x31, 0x340, x13 - csrrc x31, 0x340, x14 - csrrs x31, 0x340, x14 - csrrw x31, 0x340, x14 - csrrc x31, 0x340, x15 - csrrs x31, 0x340, x15 - csrrw x31, 0x340, x15 - csrrc x31, 0x340, x16 - csrrs x31, 0x340, x16 - csrrw x31, 0x340, x16 - csrrc x31, 0x340, x17 - csrrs x31, 0x340, x17 - csrrw x31, 0x340, x17 - csrrc x31, 0x340, x18 - csrrs x31, 0x340, x18 - csrrw x31, 0x340, x18 - csrrc x31, 0x340, x19 - csrrs x31, 0x340, x19 - csrrw x31, 0x340, x19 - csrrc x31, 0x340, x20 - csrrs x31, 0x340, x20 - csrrw x31, 0x340, x20 - csrrc x31, 0x340, x21 - csrrs x31, 0x340, x21 - csrrw x31, 0x340, x21 - csrrc x31, 0x340, x22 - csrrs x31, 0x340, x22 - csrrw x31, 0x340, x22 - csrrc x31, 0x340, x23 - csrrs x31, 0x340, x23 - csrrw x31, 0x340, x23 - csrrc x31, 0x340, x24 - csrrs x31, 0x340, x24 - csrrw x31, 0x340, x24 - csrrc x31, 0x340, x25 - csrrs x31, 0x340, x25 - csrrw x31, 0x340, x25 - csrrc x31, 0x340, x26 - csrrs x31, 0x340, x26 - csrrw x31, 0x340, x26 - csrrc x31, 0x340, x27 - csrrs x31, 0x340, x27 - csrrw x31, 0x340, x27 - csrrc x31, 0x340, x28 - csrrs x31, 0x340, x28 - csrrw x31, 0x340, x28 - csrrc x31, 0x340, x29 - csrrs x31, 0x340, x29 - csrrw x31, 0x340, x29 - csrrc x31, 0x340, x30 - csrrs x31, 0x340, x30 - csrrw x31, 0x340, x30 - csrrc x31, 0x340, x31 - csrrs x31, 0x340, x31 - csrrw x31, 0x340, x31 - -test_done: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'D' - sw a1,0(a0) - addi a1,zero,'O' - sw a1,0(a0) - addi a1,zero,'N' - sw a1,0(a0) - addi a1,zero,'E' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - -csr_pass: - li x18, 123456789 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi - -csr_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - - li x18, 1 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi -# -# end -# diff --git a/cv32e40x/tests/programs/custom/csr_instr_asm/test.yaml b/cv32e40x/tests/programs/custom/csr_instr_asm/test.yaml deleted file mode 100644 index d576cdc194..0000000000 --- a/cv32e40x/tests/programs/custom/csr_instr_asm/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: csr_instr_asm -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR access instruction test diff --git a/cv32e40x/tests/programs/custom/csr_instructions/csr_instructions.c b/cv32e40x/tests/programs/custom/csr_instructions/csr_instructions.c deleted file mode 100644 index 9e9a7b99c0..0000000000 --- a/cv32e40x/tests/programs/custom/csr_instructions/csr_instructions.c +++ /dev/null @@ -1,117 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** CSR instruction test: Execute each Zicsr instruction at least once. -** This test exists purely to debug functional coverage. -** -******************************************************************************* -*/ - -#include -#include - -int main(int argc, char *argv[]) -{ - unsigned int readd; // Read data - unsigned int writed; // Write data - unsigned int mask; // Make value - - int err_cnt, sum; - - readd = 0; - writed = 0; - mask = 0; - err_cnt = 0; - sum = 0; - - printf("\n\nCSR Instruction Test\n"); - - // Control and Status Register Read - // pseudoinstruction: expands to csrrs rd, csr, x0 - __asm__ volatile("csrr %0, 0x340" : "=r"(readd)); // CSR 0x340 is a 32-bit R/W scratch-pad - - // Control and Status Register Clear - // pseudoinstruction: expands to csrrc x0, csr, rs1 - __asm__ volatile("csrc 0x340, %0" : "=r"(writed)); - - // Control and Status Register Clear Immediate - // pseudoinstruction: expands to csrrci x0, csr, zimm - __asm__ volatile("csrci 0x340, 0xF"); - - // Control and Status Register Read and Clear - __asm__ volatile("csrrc %0, 0x340, %1" : "=r"(readd) : "r"(mask)); - - // Control and Status Register Read and Clear Immediate - __asm__ volatile("csrrci %0, 0x340, 0xF" : "=r"(readd)); - - // Control and Status Register Read and Set - __asm__ volatile("csrrs %0, 0x340, %1" : "=r"(readd) : "r"(mask)); - - // Control and Status Register Read and Set Immediate - __asm__ volatile("csrrsi %0, 0x340, 0xF" : "=r"(readd)); - - // Control and Status Register Read and Write - __asm__ volatile("csrrw %0, 0x340, %1" : "=r"(readd) : "r"(mask)); - - // Control and Status Register Read and Write Immediate - __asm__ volatile("csrrwi %0, 0x340, 0xF" : "=r"(readd)); - - // Control and Status Register Set - // pseudoinstruction: expands to csrrs x0, csr, rs1 - __asm__ volatile("csrs 0x340, %0" : "=r"(mask)); - - // Control and Status Register Set Immediate - // pseudoinstruction: expands to csrrsi x0, csr, zimm - __asm__ volatile("csrsi 0x340, 0xF"); - - // Control and Status Register Write - // pseudoinstruction: expands to csrrw x0, csr, rs1 - __asm__ volatile("csrw 0x340, %0" : "=r"(mask)); - - // Control and Status Register Write Immediate - // pseudoinstruction: expands to csrrwi x0, csr, rs1 - __asm__ volatile("csrwi 0x340, 0xF"); - - printf("\n\nMSTATUS (0x300) CSR Write-Read Test\n"); - // Control and Status Register Read - // pseudoinstruction: expands to csrrs rd, csr, x0 - __asm__ volatile("csrr %0, 0x300" : "=r"(readd)); - printf("MSTATUS Read Value is %0x\n", readd); - // Control and Status Register Write - // pseudoinstruction: expands to csrrw x0, csr, rs1 - mask = 0xFFFFFFFF; - __asm__ volatile("li a5, 0x0"); - __asm__ volatile("li a5,0xFFFFFFFF"); - __asm__ volatile("csrw 0x300, a5"); - // Control and Status Register Read - // pseudoinstruction: expands to csrrs rd, csr, x0 - __asm__ volatile("csrr %0, 0x300" : "=r"(readd)); - printf("MSTATUS Read Value is %0x\n", readd); - - - - printf("DONE!\n\n"); - - if (!err_cnt) { - return EXIT_SUCCESS; - } else { - printf("\n%0d failures\n", sum); - return EXIT_FAILURE; - } - -} diff --git a/cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/cv32e40x_csr_access_test.S b/cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/cv32e40x_csr_access_test.S deleted file mode 100644 index 4623cccdeb..0000000000 --- a/cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/cv32e40x_csr_access_test.S +++ /dev/null @@ -1,1767 +0,0 @@ -# CSR access test -# Generated by gen_csr_test.py (part of riscv-dv) -# Manual edits to fit with BSP and enhance debug -.macro init -.endm -#include "corev_uvmt.h" -.include "user_define.h" -.section .text.start -.globl _start -.option norvc -.section .text -#.include "user_init.s" -.type _start, @function - -_start: - j _start_main - -.globl _start_main -.section .text -_start_main: - - #define EXP_MISA 0x40001104 - -############################################################################### -# -# Generated code starts... -# -############################################################################### -_start0: - # mcycle - li x15, 0xa5a5a5a5 - csrrw x7, 2816, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 2816, x15 - li x15, 0xa5a5a5a5 - bne x15, x7, csr_fail - li x15, 0xa527d2fd - csrrw x7, 2816, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 2816, x15 - li x15, 0xa527d2fd - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 2816, x15 - li x15, 0xa5a7f7fd - bne x15, x7, csr_fail - li x15, 0x8d490a7c - csrrs x7, 2816, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 2816, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 2816, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xf1619953 - csrrc x7, 2816, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2816, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2816, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 2816, 0b10001 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 2816, 0b00101 - li x15, 0x00000011 - bne x15, x7, csr_fail - csrrsi x7, 2816, 0b11010 - li x15, 0x00000015 - bne x15, x7, csr_fail - csrrsi x7, 2816, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2816, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2816, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 2816, 0b00001 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mcycleh - li x15, 0xa5a5a5a5 - csrrw x7, 2944, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 2944, x15 - li x15, 0xa5a5a5a5 - bne x15, x7, csr_fail - li x15, 0x881290d3 - csrrw x7, 2944, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 2944, x15 - li x15, 0x881290d3 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 2944, x15 - li x15, 0xadb7b5f7 - bne x15, x7, csr_fail - li x15, 0x90840da8 - csrrs x7, 2944, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 2944, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 2944, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa8c12f4c - csrrc x7, 2944, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2944, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2944, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 2944, 0b11110 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 2944, 0b00101 - li x15, 0x0000001e - bne x15, x7, csr_fail - csrrsi x7, 2944, 0b11010 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrsi x7, 2944, 0b00010 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2944, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2944, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 2944, 0b01001 - li x15, 0x00000000 - bne x15, x7, csr_fail - # minstret - li x15, 0xa5a5a5a5 - csrrw x7, 2818, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 2818, x15 - li x15, 0xa5a5a5a5 - bne x15, x7, csr_fail - li x15, 0x1b912585 - csrrw x7, 2818, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 2818, x15 - li x15, 0x1b912585 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 2818, x15 - li x15, 0xbfb5a5a5 - bne x15, x7, csr_fail - li x15, 0x4016d3d3 - csrrs x7, 2818, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 2818, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 2818, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xd103824a - csrrc x7, 2818, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2818, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2818, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 2818, 0b01101 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 2818, 0b00101 - li x15, 0x0000000d - bne x15, x7, csr_fail - csrrsi x7, 2818, 0b11010 - li x15, 0x0000000d - bne x15, x7, csr_fail - csrrsi x7, 2818, 0b00011 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2818, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2818, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 2818, 0b01011 - li x15, 0x00000000 - bne x15, x7, csr_fail - # minstreth - li x15, 0xa5a5a5a5 - csrrw x7, 2946, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 2946, x15 - li x15, 0xa5a5a5a5 - bne x15, x7, csr_fail - li x15, 0x2d778987 - csrrw x7, 2946, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 2946, x15 - li x15, 0x2d778987 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 2946, x15 - li x15, 0xadf7ada7 - bne x15, x7, csr_fail - li x15, 0xea732bc2 - csrrs x7, 2946, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 2946, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 2946, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0x66e6e62c - csrrc x7, 2946, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2946, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2946, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 2946, 0b11001 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 2946, 0b00101 - li x15, 0x00000019 - bne x15, x7, csr_fail - csrrsi x7, 2946, 0b11010 - li x15, 0x0000001d - bne x15, x7, csr_fail - csrrsi x7, 2946, 0b00001 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2946, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2946, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 2946, 0b11011 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mhpmcounter3 - li x15, 0xa5a5a5a5 - csrrw x7, 2819, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 2819, x15 - li x15, 0xa5a5a5a5 - bne x15, x7, csr_fail - li x15, 0xafd13031 - csrrw x7, 2819, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 2819, x15 - li x15, 0xafd13031 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 2819, x15 - li x15, 0xaff5b5b5 - bne x15, x7, csr_fail - li x15, 0x48aaa619 - csrrs x7, 2819, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 2819, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 2819, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xd665c88b - csrrc x7, 2819, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2819, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2819, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 2819, 0b11100 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 2819, 0b00101 - li x15, 0x0000001c - bne x15, x7, csr_fail - csrrsi x7, 2819, 0b11010 - li x15, 0x0000001d - bne x15, x7, csr_fail - csrrsi x7, 2819, 0b11001 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2819, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2819, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 2819, 0b11000 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mhpmcounter3h - li x15, 0xa5a5a5a5 - csrrw x7, 2947, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 2947, x15 - li x15, 0xa5a5a5a5 - bne x15, x7, csr_fail - li x15, 0x972dca32 - csrrw x7, 2947, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 2947, x15 - li x15, 0x972dca32 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 2947, x15 - li x15, 0xb7adefb7 - bne x15, x7, csr_fail - li x15, 0x10f316b1 - csrrs x7, 2947, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 2947, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 2947, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xdab0ba1c - csrrc x7, 2947, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2947, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 2947, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 2947, 0b01100 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 2947, 0b00101 - li x15, 0x0000000c - bne x15, x7, csr_fail - csrrsi x7, 2947, 0b11010 - li x15, 0x0000000d - bne x15, x7, csr_fail - csrrsi x7, 2947, 0b00111 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2947, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 2947, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 2947, 0b01110 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mstatus - li x15, 0xa5a5a5a5 - csrrw x7, 768, x15 - li x15, 0x00001800 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 768, x15 - li x15, 0x00001880 - bne x15, x7, csr_fail - li x15, 0xb70f07da - csrrw x7, 768, x15 - li x15, 0x00001808 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 768, x15 - li x15, 0x00001888 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 768, x15 - li x15, 0x00001888 - bne x15, x7, csr_fail - li x15, 0x1364e406 - csrrs x7, 768, x15 - li x15, 0x00001888 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 768, x15 - li x15, 0x00001888 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 768, x15 - li x15, 0x00001808 - bne x15, x7, csr_fail - li x15, 0x82551c5a - csrrc x7, 768, x15 - li x15, 0x00001800 - bne x15, x7, csr_fail - csrrwi x7, 768, 0b00101 - li x15, 0x00001800 - bne x15, x7, csr_fail - csrrwi x7, 768, 0b11010 - li x15, 0x00001800 - bne x15, x7, csr_fail - csrrwi x7, 768, 0b10101 - li x15, 0x00001808 - bne x15, x7, csr_fail - csrrsi x7, 768, 0b00101 - li x15, 0x00001800 - bne x15, x7, csr_fail - csrrsi x7, 768, 0b11010 - li x15, 0x00001800 - bne x15, x7, csr_fail - csrrsi x7, 768, 0b11100 - li x15, 0x00001808 - bne x15, x7, csr_fail - csrrci x7, 768, 0b00101 - li x15, 0x00001808 - bne x15, x7, csr_fail - csrrci x7, 768, 0b11010 - li x15, 0x00001808 - bne x15, x7, csr_fail - csrrci x7, 768, 0b01101 - li x15, 0x00001800 - bne x15, x7, csr_fail - # misa - li x15, 0xa5a5a5a5 - csrrw x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0xe0f3b6a0 - csrrw x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0x255c4c31 - csrrs x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - li x15, 0xa82fcbc3 - csrrc x7, 769, x15 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrwi x7, 769, 0b00101 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrwi x7, 769, 0b11010 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrwi x7, 769, 0b00011 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrsi x7, 769, 0b00101 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrsi x7, 769, 0b11010 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrsi x7, 769, 0b01011 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrci x7, 769, 0b00101 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrci x7, 769, 0b11010 - li x15, 0x40001104 - bne x15, x7, csr_fail - csrrci x7, 769, 0b01001 - li x15, 0x40001104 - bne x15, x7, csr_fail - # mie - li x15, 0xa5a5a5a5 - csrrw x7, 772, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 772, x15 - li x15, 0xa5a50080 - bne x15, x7, csr_fail - li x15, 0x23ff47bd - csrrw x7, 772, x15 - li x15, 0x5a5a0808 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 772, x15 - li x15, 0x23ff0088 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 772, x15 - li x15, 0xa7ff0088 - bne x15, x7, csr_fail - li x15, 0xb70cb628 - csrrs x7, 772, x15 - li x15, 0xffff0888 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 772, x15 - li x15, 0xffff0888 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 772, x15 - li x15, 0x5a5a0808 - bne x15, x7, csr_fail - li x15, 0x037366d2 - csrrc x7, 772, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 772, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 772, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 772, 0b01100 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrsi x7, 772, 0b00101 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrsi x7, 772, 0b11010 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrsi x7, 772, 0b01010 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrci x7, 772, 0b00101 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrci x7, 772, 0b11010 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrci x7, 772, 0b10010 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mtvec - li x15, 0xa5a5a5a5 - csrrw x7, 773, x15 - li x15, 0x00000001 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 773, x15 - li x15, 0xa5a5a501 - bne x15, x7, csr_fail - li x15, 0xde1843c8 - csrrw x7, 773, x15 - li x15, 0x5a5a5a00 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 773, x15 - li x15, 0xde184300 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 773, x15 - li x15, 0xffbde701 - bne x15, x7, csr_fail - li x15, 0x7d36af52 - csrrs x7, 773, x15 - li x15, 0xffffff01 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 773, x15 - li x15, 0xffffff01 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 773, x15 - li x15, 0x5a5a5a00 - bne x15, x7, csr_fail - li x15, 0xf709ea8a - csrrc x7, 773, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 773, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 773, 0b11010 - li x15, 0x00000001 - bne x15, x7, csr_fail - csrrwi x7, 773, 0b11100 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 773, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 773, 0b11010 - li x15, 0x00000001 - bne x15, x7, csr_fail - csrrsi x7, 773, 0b11110 - li x15, 0x00000001 - bne x15, x7, csr_fail - csrrci x7, 773, 0b00101 - li x15, 0x00000001 - bne x15, x7, csr_fail - csrrci x7, 773, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 773, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mstatush - li x15, 0xa5a5a5a5 - csrrw x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x4adbdc3e - csrrw x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x659c9d55 - csrrs x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa6776c49 - csrrc x7, 784, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 784, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 784, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 784, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 784, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 784, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 784, 0b00111 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 784, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 784, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 784, 0b11100 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mcountinhibit - li x15, 0xa5a5a5a5 - csrrw x7, 800, x15 - li x15, 0x0000000d - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 800, x15 - li x15, 0x00000005 - bne x15, x7, csr_fail - li x15, 0xf17ec5b5 - csrrw x7, 800, x15 - li x15, 0x00000008 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 800, x15 - li x15, 0x00000005 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 800, x15 - li x15, 0x00000005 - bne x15, x7, csr_fail - li x15, 0x7752c30b - csrrs x7, 800, x15 - li x15, 0x0000000d - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 800, x15 - li x15, 0x0000000d - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 800, x15 - li x15, 0x00000008 - bne x15, x7, csr_fail - li x15, 0xcb53622a - csrrc x7, 800, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 800, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 800, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 800, 0b11111 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrsi x7, 800, 0b00101 - li x15, 0x0000000d - bne x15, x7, csr_fail - csrrsi x7, 800, 0b11010 - li x15, 0x0000000d - bne x15, x7, csr_fail - csrrsi x7, 800, 0b11000 - li x15, 0x0000000d - bne x15, x7, csr_fail - csrrci x7, 800, 0b00101 - li x15, 0x0000000d - bne x15, x7, csr_fail - csrrci x7, 800, 0b11010 - li x15, 0x00000008 - bne x15, x7, csr_fail - csrrci x7, 800, 0b10100 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mhpmevent3 - li x15, 0xa5a5a5a5 - csrrw x7, 803, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 803, x15 - li x15, 0x0000a5a5 - bne x15, x7, csr_fail - li x15, 0x51071d43 - csrrw x7, 803, x15 - li x15, 0x00005a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 803, x15 - li x15, 0x00001d43 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 803, x15 - li x15, 0x0000bde7 - bne x15, x7, csr_fail - li x15, 0x9bdd8c41 - csrrs x7, 803, x15 - li x15, 0x0000ffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 803, x15 - li x15, 0x0000ffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 803, x15 - li x15, 0x00005a5a - bne x15, x7, csr_fail - li x15, 0x05d19134 - csrrc x7, 803, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 803, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 803, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 803, 0b10110 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 803, 0b00101 - li x15, 0x00000016 - bne x15, x7, csr_fail - csrrsi x7, 803, 0b11010 - li x15, 0x00000017 - bne x15, x7, csr_fail - csrrsi x7, 803, 0b11111 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 803, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 803, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 803, 0b11101 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mscratch - li x15, 0xa5a5a5a5 - csrrw x7, 832, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 832, x15 - li x15, 0xa5a5a5a5 - bne x15, x7, csr_fail - li x15, 0x5b31710a - csrrw x7, 832, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 832, x15 - li x15, 0x5b31710a - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 832, x15 - li x15, 0xffb5f5af - bne x15, x7, csr_fail - li x15, 0x7935b59f - csrrs x7, 832, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 832, x15 - li x15, 0xffffffff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 832, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xf3e47802 - csrrc x7, 832, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 832, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 832, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 832, 0b10101 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 832, 0b00101 - li x15, 0x00000015 - bne x15, x7, csr_fail - csrrsi x7, 832, 0b11010 - li x15, 0x00000015 - bne x15, x7, csr_fail - csrrsi x7, 832, 0b00000 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 832, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 832, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 832, 0b01000 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mepc - li x15, 0xa5a5a5a5 - csrrw x7, 833, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 833, x15 - li x15, 0xa5a5a5a4 - bne x15, x7, csr_fail - li x15, 0x350117aa - csrrw x7, 833, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 833, x15 - li x15, 0x350117aa - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 833, x15 - li x15, 0xb5a5b7ae - bne x15, x7, csr_fail - li x15, 0x5081123d - csrrs x7, 833, x15 - li x15, 0xfffffffe - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 833, x15 - li x15, 0xfffffffe - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 833, x15 - li x15, 0x5a5a5a5a - bne x15, x7, csr_fail - li x15, 0xf9424657 - csrrc x7, 833, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 833, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 833, 0b11010 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrwi x7, 833, 0b11111 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 833, 0b00101 - li x15, 0x0000001e - bne x15, x7, csr_fail - csrrsi x7, 833, 0b11010 - li x15, 0x0000001e - bne x15, x7, csr_fail - csrrsi x7, 833, 0b01010 - li x15, 0x0000001e - bne x15, x7, csr_fail - csrrci x7, 833, 0b00101 - li x15, 0x0000001e - bne x15, x7, csr_fail - csrrci x7, 833, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 833, 0b10011 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mcause - li x15, 0xa5a5a5a5 - csrrw x7, 834, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 834, x15 - li x15, 0x800000a5 - bne x15, x7, csr_fail - li x15, 0x744e83e3 - csrrw x7, 834, x15 - li x15, 0x0000005a - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 834, x15 - li x15, 0x000000e3 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 834, x15 - li x15, 0x800000e7 - bne x15, x7, csr_fail - li x15, 0x8b28cc8a - csrrs x7, 834, x15 - li x15, 0x800000ff - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 834, x15 - li x15, 0x800000ff - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 834, x15 - li x15, 0x0000005a - bne x15, x7, csr_fail - li x15, 0xae82d4c9 - csrrc x7, 834, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 834, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 834, 0b11010 - li x15, 0x00000005 - bne x15, x7, csr_fail - csrrwi x7, 834, 0b10000 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrsi x7, 834, 0b00101 - li x15, 0x00000010 - bne x15, x7, csr_fail - csrrsi x7, 834, 0b11010 - li x15, 0x00000015 - bne x15, x7, csr_fail - csrrsi x7, 834, 0b01011 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 834, 0b00101 - li x15, 0x0000001f - bne x15, x7, csr_fail - csrrci x7, 834, 0b11010 - li x15, 0x0000001a - bne x15, x7, csr_fail - csrrci x7, 834, 0b01000 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mtval - li x15, 0xa5a5a5a5 - csrrw x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa31c7189 - csrrw x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x74950622 - csrrs x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x355c59d1 - csrrc x7, 835, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 835, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 835, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 835, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 835, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 835, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 835, 0b10111 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 835, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 835, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 835, 0b11110 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mip - li x15, 0xa5a5a5a5 - csrrw x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xfb3251cd - csrrw x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x9e4344c7 - csrrs x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x4c565f09 - csrrc x7, 836, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 836, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 836, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 836, 0b01011 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 836, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 836, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 836, 0b01110 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 836, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 836, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 836, 0b11101 - li x15, 0x00000000 - bne x15, x7, csr_fail - # tselect - li x15, 0xa5a5a5a5 - csrrw x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xd09a26a5 - csrrw x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x7c9b6a12 - csrrs x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x7296ad41 - csrrc x7, 1952, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1952, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1952, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1952, 0b01001 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1952, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1952, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1952, 0b10110 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1952, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1952, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1952, 0b11100 - li x15, 0x00000000 - bne x15, x7, csr_fail - # tdata1 - li x15, 0xa5a5a5a5 - csrrw x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0xaa99b722 - csrrw x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0x03957142 - csrrs x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - li x15, 0x1509aee1 - csrrc x7, 1953, x15 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrwi x7, 1953, 0b00101 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrwi x7, 1953, 0b11010 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrwi x7, 1953, 0b10100 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrsi x7, 1953, 0b00101 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrsi x7, 1953, 0b11010 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrsi x7, 1953, 0b00010 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrci x7, 1953, 0b00101 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrci x7, 1953, 0b11010 - li x15, 0x28001040 - bne x15, x7, csr_fail - csrrci x7, 1953, 0b11110 - li x15, 0x28001040 - bne x15, x7, csr_fail - # tdata2 - li x15, 0xa5a5a5a5 - csrrw x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x79d9b9fc - csrrw x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xc030ed13 - csrrs x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xb92aacac - csrrc x7, 1954, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1954, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1954, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1954, 0b00100 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1954, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1954, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1954, 0b01010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1954, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1954, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1954, 0b11111 - li x15, 0x00000000 - bne x15, x7, csr_fail - # tdata3 - li x15, 0xa5a5a5a5 - csrrw x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xf7decd0c - csrrw x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x48d86b19 - csrrs x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xdae19b10 - csrrc x7, 1955, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1955, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1955, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1955, 0b01011 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1955, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1955, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1955, 0b01100 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1955, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1955, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1955, 0b00000 - li x15, 0x00000000 - bne x15, x7, csr_fail - # tinfo - li x15, 0xa5a5a5a5 - csrrw x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0x93d9e0f7 - csrrw x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0x8de85005 - csrrs x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - li x15, 0x5f4fd829 - csrrc x7, 1956, x15 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrwi x7, 1956, 0b00101 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrwi x7, 1956, 0b11010 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrwi x7, 1956, 0b10111 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrsi x7, 1956, 0b00101 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrsi x7, 1956, 0b11010 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrsi x7, 1956, 0b11110 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrci x7, 1956, 0b00101 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrci x7, 1956, 0b11010 - li x15, 0x00000004 - bne x15, x7, csr_fail - csrrci x7, 1956, 0b10010 - li x15, 0x00000004 - bne x15, x7, csr_fail - # mcontext - li x15, 0xa5a5a5a5 - csrrw x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xb7aad2d0 - csrrw x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5ac9f7e8 - csrrs x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xf0f305cf - csrrc x7, 1960, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1960, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1960, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1960, 0b01100 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1960, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1960, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1960, 0b00000 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1960, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1960, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1960, 0b00110 - li x15, 0x00000000 - bne x15, x7, csr_fail - # mscontext - li x15, 0xa5a5a5a5 - csrrw x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x68cfe737 - csrrw x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xea92f9cd - csrrs x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x3f4b24e2 - csrrc x7, 1962, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1962, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1962, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1962, 0b11110 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1962, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1962, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1962, 0b01011 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1962, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1962, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1962, 0b00000 - li x15, 0x00000000 - bne x15, x7, csr_fail - # tcontrol - li x15, 0xa5a5a5a5 - csrrw x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrw x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xaaa02d21 - csrrw x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrs x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrs x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x6230f001 - csrrs x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0xa5a5a5a5 - csrrc x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x5a5a5a5a - csrrc x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - li x15, 0x8a71644f - csrrc x7, 1957, x15 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1957, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1957, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrwi x7, 1957, 0b01011 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1957, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1957, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrsi x7, 1957, 0b00111 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1957, 0b00101 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1957, 0b11010 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrrci x7, 1957, 0b00110 - li x15, 0x00000000 - bne x15, x7, csr_fail - csrr x7, 1957 - li x15, 0x00000000 - bne x15, x7, csr_fail -################################################################################ -# -# Generated code ends... -# -################################################################################ -test_done: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'D' - sw a1,0(a0) - addi a1,zero,'O' - sw a1,0(a0) - addi a1,zero,'N' - sw a1,0(a0) - addi a1,zero,'E' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - -csr_pass: - li x18, 123456789 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi - -csr_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - - li x18, 1 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi - -# -# End -# diff --git a/cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/test.yaml b/cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/test.yaml deleted file mode 100644 index d4e9561a54..0000000000 --- a/cv32e40x/tests/programs/custom/cv32e40x_csr_access_test/test.yaml +++ /dev/null @@ -1,5 +0,0 @@ -name: cv32e40x_csr_access_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR access test for the cv32e40x -llvm_cflags: -fno-integrated-as diff --git a/cv32e40x/tests/programs/custom/cv32e40x_readonly_csr_access_test/cv32e40x_readonly_csr_access_test.S b/cv32e40x/tests/programs/custom/cv32e40x_readonly_csr_access_test/cv32e40x_readonly_csr_access_test.S deleted file mode 100644 index 8d9361dc2d..0000000000 --- a/cv32e40x/tests/programs/custom/cv32e40x_readonly_csr_access_test/cv32e40x_readonly_csr_access_test.S +++ /dev/null @@ -1,314 +0,0 @@ -# -# Copyright (C) EM Microelectronic US Inc. -# Copyright (C) 2020 OpenHW Group -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. -# -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 -# -############################################################################### -# READ ONLY CSRs: access read-only CSRs and check for side-effects. -############################################################################### - -.globl _start -.globl main -.globl exit -.global debug -.section .text -.global u_sw_irq_handler - -#include "corev_uvmt.h" - -#define TEST_PASS 123456789 -#define TEST_FAIL 1 -#define VIRT_PERIPH_STATUS_FLAG_ADDR CV_VP_STATUS_FLAGS_BASE -#define EXPECTED_ILLEGAL_INSTRUCTIONS 86 - -main: - li t0, (0x1 << 3) - csrs mstatus, t0 - li x5, 0x0 - li x6, 0x6 - li x7, 0x7 - li x8, 0x8 - li x9, 0x9 - li x10, 0xa - li x11, 0xb - li x12, 0xc - li x13, 0xd - li x14, 0xe - li x15, 0xf - li x16, 0x10 - li x17, 0x11 - li x18, 0x12 - li x19, 0x13 - li x20, 0x14 - li x21, 0x15 - li x22, 0x16 - li x23, 0x17 - li x24, 0x18 - li x25, 0x19 - li x28, 0x1c - li x29, 0x1d - li x30, 0x1e - li x31, 0x0 - addi sp,sp,-84 - sw x6,80(sp) - sw x7,76(sp) - sw x8,72(sp) - sw x9,68(sp) - sw x10,64(sp) - sw x11,60(sp) - sw x12,56(sp) - sw x13,52(sp) - sw x14,48(sp) - sw x15,44(sp) - sw x16,40(sp) - sw x17,36(sp) - sw x18,32(sp) - sw x19,28(sp) - sw x20,24(sp) - sw x21,20(sp) - sw x22,16(sp) - sw x23,12(sp) - sw x24,8(sp) - sw x25,4(sp) -############################################################################### - - csrrci x5, 0x340, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmevent3 - csrrci x5, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0x323, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 0x323, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0x323, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0x323, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - - # mvendorid - csrrc x5, 0xF11, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 0xF11, x5 # illegal instruction: attempt to write RO CSR - csrrci x5, 0xF11, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 0xF11, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 0xF11, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 0xF11, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 0xF11, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 0xF11, x0 # not illegal - li x30, 0x00000602 - bne x5, x30, fail - - # marchid - csrrc x5, 0xF12, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 0xF12, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 0xF12, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 0xF12, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 0xF12, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 0xF12, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 0xF12, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 0xF12, x0 # not illegal - li x30, 0x00000014 - bne x5, x30, fail - - # mipmid - csrrc x5, 0xF13, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 0xF13, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 0xF13, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 0xF13, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 0xF13, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 0xF13, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 0xF13, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 0xF13, x0 # not illegal - li x30, 0x00000000 - bne x5, x30, fail - - # mhartid - csrrc x5, 0xF14, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 0xF14, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 0xF14, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 0xF14, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 0xF14, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 0xF14, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 0xF14, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 0xF14, x0 # not illegal - li x30, 0x00000000 - bne x5, x30, fail - - # mconfigptr 3861 - csrrc x5, 0xF15, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 0xF15, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 0xF15, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 0xF15, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 0xF15, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 0xF15, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 0xF15, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 0xF15, x0 # not illegal - li x30, 0x00000000 - bne x5, x30, fail - - ## - ## Access the User Custom CSRs. These are all illegal instructions when - ## PULP_XPULP = 0 (which is the default for CV32E40X). - ## - - # lpstart0 - csrrc x5, 0x800, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0x800, x5 - csrrci x0, 0x800, 0x0a - csrrs x0, 0x800, x5 - csrrsi x0, 0x800, 0x0a - csrrw x0, 0x800, x0 - csrrwi x0, 0x800, 0x0a - - # lpend0 - csrrc x5, 0x801, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0x801, x5 - csrrci x0, 0x801, 0x0a - csrrs x0, 0x801, x5 - csrrsi x0, 0x801, 0x0a - csrrw x0, 0x801, x0 - csrrwi x0, 0x801, 0x0a - - # lpcount0 - csrrc x5, 0x802, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0x802, x5 - csrrci x0, 0x802, 0x0a - csrrs x0, 0x802, x5 - csrrsi x0, 0x802, 0x0a - csrrw x0, 0x802, x0 - csrrwi x0, 0x802, 0x0a - - # lpstart1 - csrrc x5, 0x804, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0x804, x5 - csrrci x0, 0x804, 0x0a - csrrs x0, 0x804, x5 - csrrsi x0, 0x804, 0x0a - csrrw x0, 0x804, x0 - csrrwi x0, 0x804, 0x0a - - # lpend1 - csrrc x5, 0x805, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0x805, x5 - csrrci x0, 0x805, 0x0a - csrrs x0, 0x805, x5 - csrrsi x0, 0x805, 0x0a - csrrw x0, 0x805, x0 - csrrwi x0, 0x805, 0x0a - - # lpcount1 - csrrc x5, 0x806, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0x806, x5 - csrrci x0, 0x806, 0x0a - csrrs x0, 0x806, x5 - csrrsi x0, 0x806, 0x0a - csrrw x0, 0x806, x0 - csrrwi x0, 0x806, 0x0a - - # uhartid - csrrc x5, 0xCC0, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0xCC0, x5 - csrrci x0, 0xCC0, 0x0a - csrrs x0, 0xCC0, x5 - csrrsi x0, 0xCC0, 0x0a - csrrw x0, 0xCC0, x0 - csrrwi x0, 0xCC0, 0x0a - - # privlv - csrrc x5, 0xCC1, x0 # illegal instructions: attempt access "non-existant" CSR - csrrc x0, 0xCC1, x5 - csrrci x0, 0xCC1, 0x0a - csrrs x0, 0xCC1, x5 - csrrsi x0, 0xCC1, 0x0a - csrrw x0, 0xCC1, x0 - csrrwi x0, 0xCC1, 0x0a - -############################################################################### - lw x5,80(sp) - bne x5, x6, fail - lw x5,76(sp) - bne x5, x7, fail - lw x5,72(sp) - bne x5, x8, fail - lw x5,68(sp) - bne x5, x9, fail - lw x5,64(sp) - bne x5, x10, fail - lw x5,60(sp) - bne x5, x11, fail - lw x5,56(sp) - bne x5, x12, fail - lw x5,52(sp) - bne x5, x13, fail - lw x5,48(sp) - bne x5, x14, fail - lw x5,44(sp) - bne x5, x15, fail - lw x5,40(sp) - bne x5, x16, fail - lw x5,36(sp) - bne x5, x17, fail - lw x5,32(sp) - bne x5, x18, fail - lw x5,28(sp) - bne x5, x19, fail - lw x5,24(sp) - bne x5, x20, fail - lw x5,20(sp) - bne x5, x21, fail - lw x5,16(sp) - bne x5, x22, fail - lw x5,12(sp) - bne x5, x23, fail - lw x5,8(sp) - bne x5, x24, fail - lw x5,4(sp) - bne x5, x25, fail - addi sp,sp,84 - li x18, TEST_PASS - li x16, EXPECTED_ILLEGAL_INSTRUCTIONS - beq x31, x16, test_end -fail: - li x18, TEST_FAIL -test_end: - li x17, VIRT_PERIPH_STATUS_FLAG_ADDR - sw x18,0(x17) - j _exit - -# The "sw_irq_handler" is entered on each illegal instruction. Clears -# mepc and increments the illegal instruction count in x31. -u_sw_irq_handler: - li x30, 0xf - csrrc x29, mcause, x0 - and x30, x29, x30 - li x28, 2 - bne x30, x28, _exit - csrrc x27, mepc, x0 - c.addi x27, 4 - csrrw x0, mepc, x27 - c.addi x31, 1 - mret - -_exit: - j _exit - -debug: - j _exit diff --git a/cv32e40x/tests/programs/custom/cv32e40x_readonly_csr_access_test/test.yaml b/cv32e40x/tests/programs/custom/cv32e40x_readonly_csr_access_test/test.yaml deleted file mode 100644 index 2a79544434..0000000000 --- a/cv32e40x/tests/programs/custom/cv32e40x_readonly_csr_access_test/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: cv32e40x_readonly_csr_access_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR access test for RO CSRs of cv32e40x diff --git a/cv32e40x/tests/programs/custom/data_bus_error/data_bus_error.c b/cv32e40x/tests/programs/custom/data_bus_error/data_bus_error.c deleted file mode 100644 index 45b8a203e2..0000000000 --- a/cv32e40x/tests/programs/custom/data_bus_error/data_bus_error.c +++ /dev/null @@ -1,162 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Basic turnon test for data bus faults (errors on OBI-D load/store) -** -******************************************************************************* -*/ - -#include -#include -#include -#include "corev_uvmt.h" - -#define TEST_LOOPS 6 - -// Globals -volatile uint32_t load_bus_fault_count = 0; -volatile uint32_t load_bus_fault_exp = 0; -volatile uint32_t store_bus_fault_count = 0; -volatile uint32_t store_bus_fault_exp = 0; -volatile uint32_t error_word = 0x789a1234; - -void handle_data_load_bus_fault() { - __asm__ __volatile__( - "la a0, load_bus_fault_count \n" - "lw a1, 0(a0) \n" - "addi a1,a1,1 \n" - "sw a1, 0(a0) \n" - "j nmi_end_handler_ret" : : : - ); -} - -void handle_data_store_bus_fault() { - __asm__ __volatile__( - "la a0, store_bus_fault_count \n" - "lw a1, 0(a0) \n" - "addi a1,a1,1 \n" - "sw a1, 0(a0) \n" - "j nmi_end_handler_ret" : : : - ); -} - -int test_data_load_error() { - volatile uint32_t data_word; - - printf("Testing data load bus fault injection\n"); - - load_bus_fault_exp = 1; - store_bus_fault_exp = 0; - - if (load_bus_fault_count != 0) { - printf("test_data_load_error: Received load bus faults before injecting"); - return EXIT_FAILURE; - } - - if (store_bus_fault_count != 0) { - printf("test_data_store_error: Received load bus faults before injecting"); - return EXIT_FAILURE; - } - - // Write the Virtual Peripheral - *CV_VP_OBI_SLV_RESP_D_ERR_ADDR_MIN = (uint32_t) &error_word; - *CV_VP_OBI_SLV_RESP_D_ERR_ADDR_MAX = (uint32_t) &error_word; - *CV_VP_OBI_SLV_RESP_D_ERR_VALID = 1; - asm volatile("fence"); - - // Do the load - data_word = error_word; - - // Verify we received a fault - if (load_bus_fault_count != load_bus_fault_exp) { - printf("loads: received %lu bus faults, expected %lu\n", load_bus_fault_count, load_bus_fault_exp); - return EXIT_FAILURE; - } - - if (store_bus_fault_count != store_bus_fault_exp) { - printf("loads: received %lu bus faults, expected %lu\n", store_bus_fault_count, store_bus_fault_exp); - return EXIT_FAILURE; - } - - *CV_VP_OBI_SLV_RESP_D_ERR_VALID = 0; - load_bus_fault_count = 0; - store_bus_fault_count = 0; - - return EXIT_SUCCESS; -} - -int test_data_store_error() { - volatile uint32_t data_word; - - printf("Testing data store bus fault injection\n"); - - load_bus_fault_exp = 0; - store_bus_fault_exp = 1; - - if (load_bus_fault_count != 0) { - printf("test_data_load_error: Received load bus faults before injecting"); - return EXIT_FAILURE; - } - - if (store_bus_fault_count != 0) { - printf("test_data_store_error: Received load bus faults before injecting"); - return EXIT_FAILURE; - } - - // Write the Virtual Peripheral - *CV_VP_OBI_SLV_RESP_D_ERR_ADDR_MIN = (uint32_t) &error_word; - *CV_VP_OBI_SLV_RESP_D_ERR_ADDR_MAX = (uint32_t) &error_word; - *CV_VP_OBI_SLV_RESP_D_ERR_VALID = 1; - asm volatile("fence"); - - // Do the store - data_word = 0x12345678; - error_word = data_word; - - // Verify we received a fault - if (load_bus_fault_count != load_bus_fault_exp) { - printf("loads: received %lu bus faults, expected %lu\n", load_bus_fault_count, load_bus_fault_exp); - return EXIT_FAILURE; - } - if (store_bus_fault_count != store_bus_fault_exp) { - printf("loads: received %lu bus faults, expected %lu\n", store_bus_fault_count, store_bus_fault_exp); - return EXIT_FAILURE; - } - - *CV_VP_OBI_SLV_RESP_D_ERR_VALID = 0; - load_bus_fault_count = 0; - store_bus_fault_count = 0; - - return EXIT_SUCCESS; -} - -int main(int argc, char *argv[]) { - - printf("Start data_bus_error test\n"); - - for (int i = 0; i < TEST_LOOPS; i++) { - if (test_data_load_error() != EXIT_SUCCESS) { - return EXIT_FAILURE; - } - if (test_data_store_error() != EXIT_SUCCESS) { - return EXIT_FAILURE; - } - } - - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/data_bus_error/test.yaml b/cv32e40x/tests/programs/custom/data_bus_error/test.yaml deleted file mode 100644 index 6fecc2049d..0000000000 --- a/cv32e40x/tests/programs/custom/data_bus_error/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: data_bus_error -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Directed bus error test diff --git a/cv32e40x/tests/programs/custom/debug_test/debug_test.c b/cv32e40x/tests/programs/custom/debug_test/debug_test.c deleted file mode 100644 index be2ff11e2e..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test/debug_test.c +++ /dev/null @@ -1,557 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Basic debugger test. Needs more work and bugs fixed -** It will launch a debug request and have debugger code execute (debugger.S) -******************************************************************************* -*/ - -#include -#include -#include "corev_uvmt.h" - -volatile int glb_hart_status = 0; // Written by main code only, read by debug code -volatile int glb_debug_status = 0; // Written by debug code only, read by main code -volatile int glb_ebreak_status = 0; // Written by ebreak code only, read by main code -volatile int glb_illegal_insn_status = 0; // Written by illegal instruction code only, read by main code -volatile int glb_debug_exception_status = 0; // Written by debug code during exception only -volatile int glb_exception_ebreak_status = 0; // Written by main code, read by exception handler - -volatile int glb_previous_dpc = 0; // holds last dpc, used for checking correctness of stepping -volatile int glb_step_info = 0; // info to dbg code about actions to take on stepping -volatile int glb_step_count = 0; // Written by debug code for each time single step is entered -// Expectation flags. Raise an error if handler or routine is enterred when not expected, -volatile int glb_expect_illegal_insn = 0; -volatile int glb_expect_ebreak_handler = 0; -volatile int glb_expect_debug_entry = 0; -volatile int glb_expect_debug_exception = 0; -volatile int glb_expect_irq_entry = 0; -volatile int glb_irq_timeout = 0; -// Counter values -// Checked at start and end of debug code -// Only lower 32 bits checked, as simulation cannot overflow on 32 bits -volatile int glb_mcycle_start = 0; -volatile int glb_mcycle_end = 0; -volatile int glb_minstret_start = 0; -volatile int glb_minstret_end = 0; -#define TEST_FAILED *(volatile int *)CV_VP_STATUS_FLAGS_BASE = 1 -#define TEST_PASSED *(volatile int *)CV_VP_STATUS_FLAGS_BASE = 123456789 - -extern int __stack_start; -typedef union { - struct { - unsigned int start_delay : 15; // 14: 0 - unsigned int rand_start_delay : 1; // 15 - unsigned int pulse_width : 13; // 28:16 - unsigned int rand_pulse_width : 1; // 29 - unsigned int pulse_mode : 1; // 30 0 = level, 1 = pulse - unsigned int value : 1; // 31 - } fields; - unsigned int bits; -} debug_req_control_t; - -#define DEBUG_REQ_CONTROL_REG *((volatile uint32_t *) (CV_VP_DEBUG_CONTROL_BASE)) -#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE+0)) -#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE+4)) - -typedef union { - struct { - unsigned int uie : 1; // 0 // Implemented if USER mode enabled - unsigned int sie : 1; // 1 - unsigned int wpri : 1; // 2 - unsigned int mie : 1; // 3 // Implemented - unsigned int upie : 1; // 4 // Implemented if USER mode enabled - unsigned int spie : 1; // 5 - unsigned int wpri0 : 1; // 6 - unsigned int mpie : 1; // 7 // Implemented - unsigned int spp : 1; // 8 - unsigned int wpri1 : 2; // 10: 9 - unsigned int mpp : 2; // 12:11 // Implemented - unsigned int fs : 2; // 14:13 - unsigned int xs : 2; // 16:15 - unsigned int mprv : 1; // 17 - unsigned int sum : 1; // 18 - unsigned int mxr : 1; // 19 - unsigned int tvm : 1; // 20 - unsigned int tw : 1; // 21 - unsigned int tsr : 1; // 22 - unsigned int wpri3 : 8; // 30:23 - unsigned int sd : 1; // 31 - } fields; - unsigned int bits; -} mstatus_t; - -extern void _single_step(int d); -// Tag is simply to help debug and determine where the failure came from -void check_debug_status(int tag, int value) -{ - if(glb_debug_status != value){ - printf("ERROR: check_debug_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_debug_status, value); - TEST_FAILED; - } -} -void check_debug_exception_status(int tag, int value) -{ - if(glb_debug_exception_status != value){ - printf("ERROR: check_debug_exception_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_debug_exception_status, value); - TEST_FAILED; - } -} -void check_hart_status(int tag, int value) -{ - if(glb_hart_status != value){ - printf("ERROR: check_hart_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_hart_status, value); - TEST_FAILED; - } -} -void check_ebreak_status(int tag, int value) -{ - if(glb_ebreak_status != value){ - printf("ERROR: check_ebreak_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_ebreak_status, value); - TEST_FAILED; - } -} -void check_illegal_insn_status(int tag, int value) -{ - if(glb_illegal_insn_status != value){ - printf("ERROR: check_illegal_insn_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_illegal_insn_status, value); - TEST_FAILED; - } -} -void delay(int count) { - for (volatile int d = 0; d < count; d++); -} - -void mstatus_mie_enable() { - int mie_bit = 0x1 << 3; - asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mstatus_mie_disable() { - int mie_bit = 0x1 << 3; - asm volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mie_enable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_disable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_enable(uint32_t irq) { - // Enable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); -} - -void mie_disable(uint32_t irq) { - // Disable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); -} - -void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { - *TIMER_REG_ADDR = mask; - *TIMER_VAL_ADDR = 1 + cycle_delay; -} - -void counters_enable() { - // Enable counters mcycle (bit0) and minstret (bit2) - uint32_t mask = 1<<2 | 1<<0; - asm volatile("csrrc x0, 0x320, %0" : : "r" (mask)); -} -#define MACHINE 3 -int main(int argc, char *argv[]) -{ - unsigned int temp,temp1,temp2; - debug_req_control_t debug_req_control; - mstatus_t mstatus, mstatus_cmp; - counters_enable(); - printf("\nBasic test checking debug functionality.\n"); - - printf("------------------------\n"); - printf(" Test1: check initialization values\n"); - //check_debug_status(0,0); - - temp1 = 0xFFFFFFFF; - /* get relevant CSRs and compare init values*/ - __asm__ volatile("csrr %0, mstatus" : "=r"(temp1)); - __asm__ volatile("csrw mstatus, %0 " : "=r"(temp1)); - __asm__ volatile("csrr %0, mstatus" : "=r"(mstatus.bits)); - __asm__ volatile("csrr %0, mie" : "=r"(temp)); - __asm__ volatile("csrw mie, %0 " : "=r"(temp1)); - __asm__ volatile("csrr %0, mie" : "=r"(temp2)); - printf("\tmstats_rval = 0x%0x 0x%0x 0x%0x 0x%0x\n",temp2,mstatus.bits,temp,temp1); - - check_debug_status(0,0); - printf("------------------------\n"); - printf(" Test2.1: check access to Debug and Trigger registers\n"); - // debug specifcation 13.2: 4.8 Core Debug Registers are not accessable unless in debug mode - - // ---------------------- - // Check Debug Write Access - temp = 0xFFFFFFFF; - temp1 = glb_illegal_insn_status+1; - glb_expect_illegal_insn = 1; - __asm__ volatile("csrw dcsr, %0" : "=r"(temp)); // Debug DCSR - check_illegal_insn_status(11,temp1++); - glb_expect_illegal_insn = 1; - __asm__ volatile("csrw dpc, %0" : "=r"(temp)); // Debug DPC - check_illegal_insn_status(12,temp1++); - glb_expect_illegal_insn = 1; - __asm__ volatile("csrw dscratch, %0" : "=r"(temp)); // Debug DSCRATCH0 - check_illegal_insn_status(13,temp1++); - glb_expect_illegal_insn = 1; - __asm__ volatile("csrw 0x7b3, %0" : "=r"(temp)); // Debug DSCRATCH1 - check_illegal_insn_status(14,temp1++); - - // Check Read Access - temp1 = glb_illegal_insn_status+1; - // Allow illegal instruction handler to run - glb_expect_illegal_insn = 1; - __asm__ volatile("csrr %0, dcsr" : "=r"(temp)); // Debug DCSR - check_illegal_insn_status(1,temp1++); - glb_expect_illegal_insn = 1; - __asm__ volatile("csrr %0, dpc" : "=r"(temp)); // Debug DPC - check_illegal_insn_status(2,temp1++); - glb_expect_illegal_insn = 1; - __asm__ volatile("csrr %0, dscratch": "=r"(temp)); // Debug DSCRATCH0 - check_illegal_insn_status(3,temp1++); - glb_expect_illegal_insn = 1; - __asm__ volatile("csrr %0, 0x7b3" : "=r"(temp)); // Debug DSCRATCH1 - check_illegal_insn_status(4,temp1++); - - printf("------------------------\n"); - printf(" Test2.2: check access to Trigger registers\n"); - // Writes are ignored - temp = 0xFFFFFFFF; - __asm__ volatile("csrw 0x7a0, %0" : "=r"(temp)); // Trigger TSELECT - __asm__ volatile("csrw 0x7a1, %0" : "=r"(temp)); // Trigger TDATA1 - __asm__ volatile("csrw 0x7a2, %0" : "=r"(temp)); // Trigger TDATA2 - __asm__ volatile("csrw 0x7a3, %0" : "=r"(temp)); // Trigger TDATA3 - __asm__ volatile("csrw 0x7a4, %0" : "=r"(temp)); // Trigger TINFO - __asm__ volatile("csrw 0x7a8, %0" : "=r"(temp)); // Trigger MCONTEXT - __asm__ volatile("csrw 0x7aa, %0" : "=r"(temp)); // Trigger SCONTEXT - - // Read default value - __asm__ volatile("csrr %0, 0x7a0" : "=r"(temp)); // Trigger TSELECT - if(temp != 0x0){printf("ERROR: TSELET Read\n");TEST_FAILED;} - - __asm__ volatile("csrr %0, 0x7a1" : "=r"(temp)); // Trigger TDATA1 - // 31:28 type = 2 - // 27 dmode = 1 - // 15:12 action = 1 - // 6 m(achine) = 1 - if(temp != (2<<28 | 1<<27 | 1<<12 | 1<<6)){printf("ERROR: TDATA1 Read\n");TEST_FAILED;} - - __asm__ volatile("csrr %0, 0x7a2" : "=r"(temp)); // Trigger TDATA2 - if(temp != 0x0){printf("ERROR: TDATA2 Read\n");TEST_FAILED;} - - __asm__ volatile("csrr %0, 0x7a3" : "=r"(temp)); // Trigger TDATA3 - if(temp != 0x0){printf("ERROR: TDATA3 Read\n");TEST_FAILED;} - - __asm__ volatile("csrr %0, 0x7a4" : "=r"(temp)); // Trigger TINFO - // tmatch = 1<<2 - if(temp != 1<<2){printf("ERROR: TINFO Read %d \n",temp);TEST_FAILED;} - - __asm__ volatile("csrr %0, 0x7a8" : "=r"(temp)); // Trigger MCONTEXT - if(temp != 0x0){printf("ERROR: MCONTEXT Read\n");TEST_FAILED;} - - __asm__ volatile("csrr %0, 0x7aa" : "=r"(temp)); // Trigger SCONTEXT - if(temp != 0x0){printf("ERROR: SCONTEXT Read\n");TEST_FAILED;} - - - - // Do not expect or allow any more illegal instructions - - - mstatus_cmp = (mstatus_t) { - .fields.mpp = MACHINE // - }; - if(mstatus_cmp.bits != mstatus.bits) {printf("ERROR: init mstatus mismatch exp=%x val=%x\n", - mstatus_cmp.bits, mstatus.bits); TEST_FAILED;} - - printf("------------------------\n"); - printf(" Test3.1: check hart ebreak executes ebreak handler but does not execute debugger code\n"); - glb_expect_ebreak_handler = 1; - asm volatile("c.ebreak"); - check_ebreak_status(32,1); - - printf("------------------------\n"); - printf(" Test3.2: check hart c.ebreak executes ebreak handler but does not execute debugger code\n"); - glb_expect_ebreak_handler = 1; - asm volatile(".4byte 0x00100073"); - check_ebreak_status(32,2); - - printf("------------------------\n"); - printf(" Test4: request hardware debugger\n"); - - debug_req_control = (debug_req_control_t) { - .fields.value = 1, - .fields.pulse_mode = 1, //PULSE Mode - .fields.rand_pulse_width = 0, - .fields.pulse_width = 5,// FIXME: BUG: one clock pulse cause core to lock up - .fields.rand_start_delay = 0, - .fields.start_delay = 200 - }; - glb_expect_debug_entry = 1; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - - glb_hart_status = 4; // Basic test - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - check_debug_status(41,glb_hart_status); - - printf("------------------------\n"); - printf(" Test5: have debugger execute ebreak 3 more times\n"); - - glb_hart_status = 5; - glb_expect_debug_entry = 1; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - while(glb_debug_status != (5+3)){ - printf("Wait for Debugger\n"); - } - check_debug_status(51,(5+3)); - - printf("------------------------\n"); - printf(" Test6: Test CSR access and default values in debug mode\n"); - glb_hart_status = 6; - glb_expect_debug_entry = 1; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - check_debug_status(61,glb_hart_status); - - - printf("------------------------\n"); - printf(" Test10: check hart ebreak executes debugger code\n"); - glb_hart_status = 10; - glb_expect_debug_entry = 1; - asm volatile(".4byte 0x00100073"); - check_debug_status(33,glb_hart_status); - - printf("------------------------\n"); - printf(" Test11: check illegal csr exception during debug launches debugger exception and no csr modified\n"); - glb_hart_status = 11; - glb_expect_debug_entry = 1; - glb_expect_debug_exception = 1; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - check_debug_status(111,glb_hart_status); - check_debug_exception_status(111,glb_hart_status); - //FIXME TBD BUG : need to update test to check actual csrs not modified. - - printf("------------------------\n"); - printf(" Test12: check ecall exception during debug launches debugger exception and no csr modified\n"); - glb_hart_status = 12; - glb_expect_debug_entry = 1; - glb_expect_debug_exception = 1; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - check_debug_status(112,glb_hart_status); - check_debug_exception_status(112,glb_hart_status); - //FIXME TBD BUG : need to update test to check actual csrs not modified. - - printf("------------------------\n"); - printf(" Test13: check mret during debug launches debugger exception and no csr modified\n"); - glb_hart_status = 13; - glb_expect_debug_entry = 1; - glb_expect_debug_exception = 1; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - check_debug_status(113,glb_hart_status); - check_debug_exception_status(113,glb_hart_status); - - printf("------------------------\n"); - printf(" Test14: Check exception ebreak enters debug mode\n"); - glb_hart_status = 14; - glb_expect_illegal_insn = 1; - glb_exception_ebreak_status = 1; - glb_expect_debug_entry = 1; - - // DCSR read will cause illegal instruction. - // Exception routine reads glb_exception_ebreak_status=1 and executes c.ebreak - __asm__ volatile("csrr %0, dcsr" : "=r"(temp)); // Debug DCSR - - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - - check_illegal_insn_status(114,temp1++); - check_debug_status(114, glb_hart_status); - printf("----------------------\n"); - printf("Test 16: dret in m-mode causes exception\n"); - - glb_expect_illegal_insn = 1; - __asm__ volatile("dret"); - check_illegal_insn_status(16, temp1++); - - printf("------------------------\n"); - printf("Test 17: WFI before debug_req_i and WFI in debug mode\n"); - printf("If test hangs, WFI is NOT converted to NOP\n"); - - glb_expect_debug_entry = 1; - glb_hart_status = 17; - // start_delay is set to 200, should get the wfi executing before dbg request is asserted - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - - // Execute WFI, when debug is asserted, it will act as NOP and enter debug mode - // If not, test will hang - __asm__ volatile("wfi"); - check_debug_status(117, glb_hart_status); - - printf("----------------------\n"); - printf("Checking interrupt, as this is needed by later tests\n"); - - // Assert and check irq, as this is needed by some tests. - mstatus_mie_enable(); - mie_enable(30); - glb_expect_irq_entry = 1; - mm_ram_assert_irq(0x40000000, 1); - while(glb_expect_irq_entry == 1); - mm_ram_assert_irq(0,0); - printf("Irq check done\n"); - - // Check that stoupcount bit (10) in dcsr has no affect - printf("-------------------------\n"); - printf("Test 21: Setting stopcount bit=1\n"); - glb_expect_debug_entry = 1; - glb_hart_status = 21; - - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - check_debug_status(121, glb_hart_status); - - - printf("------------------------\n"); - printf("Test 18: Single stepping\n"); - glb_hart_status = 18; - - // Run single step code (in single_step.S) - _single_step(0); - - // Single step code should generate 2 illegal insn - temp1++; - check_illegal_insn_status(118, temp1++); - check_debug_status(118, glb_hart_status); - - printf("Stepped %d times\n", glb_step_count); - - - printf("------------------------\n"); - printf("Test 19: irq in debug\n"); - glb_hart_status = 19; - glb_expect_debug_entry = 1; - - // Does not expect irq to be taken while in debug mode - // but it will be taken when we exit from debug. - // Timeout added in debug code to check for taken irq or not - glb_expect_irq_entry = 1; - DEBUG_REQ_CONTROL_REG=debug_req_control.bits; - - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - - check_debug_status(119, glb_hart_status); - if(glb_irq_timeout != 0) { - printf("glb_irq_timeout != 0, interrupt taken in debug.\n"); - TEST_FAILED; - } - - // Test debug req vs irq timing - printf("-----------------------\n"); - printf("Test 20: Asserting debug_req and irq at the same cycle\n"); - glb_expect_debug_entry = 1; - glb_expect_irq_entry = 1; - glb_hart_status = 20; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - // 170 halts on first instuction in interrupt handler - // 175 gives same timing for interrupt and debug_req_i - mm_ram_assert_irq(0x40000000, 175+20); - - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - check_debug_status(120, glb_hart_status); - - - // Execute fence instruction in debug - printf("-----------------------------\n"); - printf("Test 22: Execute fence in debug mode\n"); - glb_expect_debug_entry = 1; - glb_hart_status = 22; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - - while(glb_debug_status != glb_hart_status) { - printf("Wait for debugger\n"); - } - - check_debug_status(121, glb_hart_status); - - printf("------------------------\n"); - printf("Test 23: trigger match in debug mode with match disabled\n"); - glb_hart_status = 23; - glb_expect_debug_entry = 1; - - // Request debug - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - - check_debug_status(123, glb_hart_status); - printf("------------------------\n"); - printf("Test 24: trigger register access in D-mode\n"); - glb_hart_status = 24; - glb_expect_debug_entry = 1; - - // Request debug - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - - while(glb_debug_status != glb_hart_status){ - printf("Wait for Debugger\n"); - } - - check_debug_status(124, glb_hart_status); - - //-------------------------------- - //return EXIT_FAILURE; - printf("------------------------\n"); - printf("Finished \n"); - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/debug_test/debugger.S b/cv32e40x/tests/programs/custom/debug_test/debugger.S deleted file mode 100644 index 9681fcb0e9..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test/debugger.S +++ /dev/null @@ -1,647 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger code -******************************************************************************* -*/ - -#include "corev_uvmt.h" - -.section .debugger, "ax" -.global _debugger_start -.global glb_debug_status -.global glb_hart_status -.global glb_expect_debug_entry -.global glb_step_info -.global glb_previous_dpc -.global glb_step_count -.global glb_irq_timeout -.global glb_mcycle_start -.global glb_mcycle_end -.global glb_minstret_start -.global glb_minstret_end -.global _step_trig_point -.global __debugger_stack_start -.global _debugger_fail -.global _debugger_end -.set timer_reg_addr, CV_VP_INTR_TIMER_BASE+0 -.set timer_val_addr, CV_VP_INTR_TIMER_BASE+4 -.set test_ret_val, CV_VP_STATUS_FLAGS_BASE -.set test_fail, 0x1 - -_debugger_start: - // Debugger Stack - csrw dscratch, a0 // dscratch0 - la a0, __debugger_stack_start - //sw t0, 0(a0) - csrw 0x7b3, t0 // dscratch1 - sw t1, 4(a0) - sw t2, 8(a0) - sw a1, 12(a0) - sw a2, 16(a0) - // Check if expecting debug entry - la a1, glb_expect_debug_entry - lw t1, 0(a1) - beq x0,t1,_debugger_fail - - // Read lower 32 bits of mcycle and minstret - // and store in globals for check at exit - csrr t1, mcycle - csrr t2, minstret - la a1, glb_mcycle_start - sw t1, 0(a1) - la a1, glb_minstret_start - sw t2, 0(a1) - - // Determine Test to execute in debugger code based on glb_hart_status - la a2, glb_hart_status - lw t2, 0(a2) - - // ebreak test will loop in debugger code over several iterations - // and will increment the global status each time - li t0,5 - beq t2,t0,_debugger_ebreak // Test 5 - - // For all other tests, - // Set debug status = hart status - la a1, glb_debug_status - sw t2, 0(a1) - - li t0, 4 - beq t2,t0,_debugger_simple // Test 4 - - li t0,6 - beq t2,t0,_debugger_csr // Test 6 - - li t0,10 - beq t2,t0,_debugger_ebreak_entry // Test 10 - - li t0,11 - beq t2,t0,_debugger_csr_exception // Test 11 - - li t0,12 - beq t2,t0,_debugger_ecall_exception // Test 12 - - li t0,13 - beq t2,t0,_debugger_mret_call // Test 13 - - li t0,14 - beq t2,t0, _debugger_ebreak_entry // Test 14 - - - li t0,17 - beq t2,t0, _debugger_wfi_test // Test 17 - - li t0,18 - beq t2, t0, _debugger_single_step - - li t0, 19 - beq t2, t0, _debugger_irq - - li t0, 20 - beq t2, t0, _debugger_req_and_irq - - li t0, 21 - beq t2, t0, _debugger_stopcount - - li t0, 22 - beq t2, t0, _debugger_fence - - li t0, 23 - beq t2, t0, _debugger_trigger_disabled_in_debug - - li t0, 24 - beq t2, t0, _debugger_trigger_regs_access - -_debugger_trigger_regs_access: - # R/W trigger regs otherwise not accessed - # to close coverage holes - li t0, 0xff - csrw 0x7a4, t0 # tinfo - csrr t0, 0x7a4 - li t1, 4 - bne t0, t1, _debugger_fail - - li t0, 0xff - csrw 0x7a3, t0 # tdata3 - csrr t0, 0x7a3 - bne t0, x0, _debugger_fail - - li t0, 0xff - csrw 0x7a0, t0 # tsel - csrr t0, 0x7a0 - bne t0, x0, _debugger_fail - - j _debugger_end - - -_debugger_fence: - fence - nop - nop - fence.i - nop - nop - j _debugger_end - -_debugger_req_and_irq: - // Debug was requested at the same cycle as irq - // Check dpc to see that pc is not at irq handler - // IRQ used was 30, so addr would be 30*4=120, 0x78 - csrr t0, dpc - li t1, 0x78 - beq t0, t1, _debugger_fail - j _debugger_end - -_debugger_stopcount: - li t0, 1<<10 - csrrs x0, dcsr, t0 - j _debugger_end -_debugger_irq: - // Assert irq - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 2 - sw t0, 0(a1) - - li t1, 1000 -// Wait for 1000 cycles, then timeout -_irq_wait_loop: - la a1, glb_expect_irq_entry - lw t0, 0(a1); - beq t1, x0, _irq_loop_end - addi t1, t1, -1 - bne t0, x0, _irq_wait_loop -_irq_loop_end: - la a1, glb_irq_timeout - sw t1, 0(a1) - j _debugger_end - -_debugger_single_step: - // Copy step_info - la a1, glb_step_info - lw t0, 0(a1) - - // Check action to take - li t1, 0 - beq t0, t1, _debugger_single_step_basic - li t1, 1 - beq t0, t1, _debugger_single_step_enable - li t1, 2 - beq t0, t1, _debugger_single_step_disable - li t1, 3 - //beq t0, t1, _debugger_single_step_illegal_insn - beq t0, t1, _debugger_single_step_basic - li t1, 4 - beq t0, t1, _debugger_single_step_trig_setup - li t1, 5 - beq t0, t1, _debugger_single_step_stepie_enable - li t1, 6 - beq t0, t1, _debugger_single_step_stepie_disable - li t1, 7 - beq t0, t1, _debugger_single_step_cebreak - li t1, 8 - beq t0, t1, _debugger_single_step_ebreak - li t1, 9 - beq t0, t1, _debugger_single_step_ebreak_exception - li t1, 10 - beq t0, t1, _debugger_single_step_cebreak_exception - j _debugger_fail - -_debugger_single_step_stepie_disable: - // enable stepi - li t0, 4<<28 | 1<<15 | 1<<2 | 0<<11 - csrw dcsr, t0 - - j _debugger_single_step_end -_debugger_single_step_stepie_enable: - // enable stepi - li t0, 4<<28 | 1<<15 | 1<<2 | 1<<11 - csrw dcsr, t0 - - j _debugger_single_step_end -_debugger_single_step_enable: - // Check dcsr - csrr t0, dcsr - li t1, 4<<28 | 1<<15 | 1<<6 | 3<<0 - bne t0, t1, _debugger_fail - - // Enable step bit in dcsr - li t0, 4<<28 | 1<<15 | 1<<2 - csrw dcsr, t0 - - // ebreak used to enter single step test, incr dpc - csrr t0, dpc - addi t0, t0, 2 - csrw dpc, t0 - j _debugger_single_step_end - -_debugger_single_step_disable: - // Turn off single stepping - li t0, 1<<15 - csrw dcsr, t0 - // Clear glb_expect_debug entry - // as this will not be done in - // _debugger_end for single step - la a1, glb_expect_debug_entry - sw x0, 0(a1) - j _debugger_end - -_debugger_single_step_trig_setup: - // Set trigger to match on _step_trig_point - la t0, _step_trig_point - csrw tdata2,t0 - li t1, 1<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - j _debugger_single_step_basic - -_debugger_single_step_end: - // Store dpc to variable for checking in next step - la a1, glb_previous_dpc - csrr t0, dpc - sw t0, 0(a1) - - // Increase step count - la a1, glb_step_count - lw t0, 0(a1) - addi t0, t0, 1 - sw t0, 0(a1) - - // Clear step info if not 3 (exception) or 5 (irq while stepping) - // 6, 7 or 8, 9, 10 - // In exception test we expect jumps - // to mtvec and other places, so keep - // step info to waive dpc checks - la a1, glb_step_info - lw t0, 0(a1) - li t1, 3 - beq t0, t1, _debugger_end - li t1, 5 - beq t0, t1, _debugger_end - li t1, 6 - beq t0, t1, _debugger_end - li t1, 7 - beq t0, t1, _debugger_end - li t1, 8 - beq t0, t1, _debugger_end - li t1, 9 - beq t0, t1, _debugger_end - li t1, 10 - beq t0, t1, _debugger_end - li t1, 0 - sw t1, 0(a1) - - // return to m-mode - j _debugger_end - -_debugger_single_step_illegal_insn: - // Check dcsr - // ebreakm step stepen - li t1, 4<<28 | 1<<15 | 4<<6 | 1<<2 | 3<<0 - csrr t2, dcsr - bne t1, t2, _debugger_fail - // read dpc and mtvec - //csrr t0, dpc - //csrr t1, mtvec - //andi t1, t1, 0xffffff00 - //bne t0, t1, _debugger_fail - j _debugger_single_step_end - -_debugger_step_trig_entry: - // Advance dpc to skip first match instruction - csrr t0, dpc - la a1, _step_trig_exit - csrw dpc, a1 - j _debugger_single_step_end - -_debugger_single_step_cebreak: - # If cause == 1, we need to advance dpc by 2 - li t1, 4<<28 | 1<<15 | 1<<6 | 1<<2 | 3<<0 - csrr t2, dcsr - beq t1, t2, _inc_dpc_cebreak - - j _debugger_single_step_end -_inc_dpc_cebreak: - csrr t1, dpc - addi t1, t1, 2 - csrw dpc, t1 - j _debugger_single_step_end - -_debugger_single_step_ebreak: - # If cause == 1, we need to advance dpc by 4 - li t1, 4<<28 | 1<<15 | 1<<6 | 1<<2 | 3<<0 - csrr t2, dcsr - beq t1, t2, _inc_dpc_ebreak - - j _debugger_single_step_end -_inc_dpc_ebreak: - csrr t1, dpc - addi t1, t1, 4 - csrw dpc, t1 - - # Turn off dcsr.ebreakm for next two tests - li t1, 4<<28 | 0<<15 | 1<<6 | 1<<2 | 3<<0 - csrw dcsr, t1 - j _debugger_single_step_end - -_debugger_single_step_ebreak_exception: - j _debugger_single_step_end - -_debugger_single_step_cebreak_exception: - # depc != 0 => we have passed the first - # instruction of the handler, and we can - # set dcsr.ebreakm again - csrr t0, dpc - bne t0, x0, _end - - li t1, 4<<28 | 1<<15 | 1<<6 | 1<<2 | 3<<0 - csrw dcsr, t1 - -_end: - j _debugger_single_step_end - -_debugger_single_step_basic: - // Check dcsr, jump to match-in-step if flagged in dcsr - li t1, 4<<28 | 1<<15 | 2<<6 | 1<<2 | 3<<0 - csrr t2, dcsr - beq t1, t2, _debugger_step_trig_entry - - - // Ensure tval (0x343) always == 0 - csrr t1, 0x343 - bne x0, t1, _debugger_fail -// ebreakm step stepen - li t1, 4<<28 | 1<<15 | 4<<6 | 1<<2 | 3<<0 - bne t1, t2, _debugger_fail - // Check that dpc increased by 2 or 4 - csrr t0, dpc - la a1, glb_previous_dpc - lw t1, 0(a1) - sub t0, t0, t1 - li t1, 2 - beq t0, t1, _debugger_single_step_end - li t1, 4 - beq t0, t1, _debugger_single_step_end - - // Waive dpc errors if we expect illegal instruction - la a1, glb_step_info - lw t0, 0(a1) - li t1, 3 -// bne t0, t1, _debugger_fail - j _debugger_single_step_end - -_debugger_csr_exception: - csrr t2,0xea8 // illegal insn - -_debugger_ecall_exception: - ecall // exception - -_debugger_mret_call: - mret // will invoke debugger exception routine - -_debugger_ebreak_entry: - la a1, glb_debug_status - li t1, 4<<28 | 1<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - csrr a1,dpc - addi a1,a1,4 # uncompressed ebreak used to enter debug here - csrw dpc,a1 - //sw t1, 0(a1) - j _debugger_end - -_debugger_simple: - // Check cause 0x3, debugger - csrr t2,dcsr - li t1, 4<<28 | 3<<6 | 3<<0 - bne t1, t2, _debugger_fail - - //csrr t2,0xea8 // illegal insn - li t1, 1 - //sw t1, 0(a1) - j _debugger_end - -_debugger_csr: - // Check CSR access - // When done, set the ebreakm bit to allow next test to enter debug with ebreak - - // TBD BUG FIXME : make sure appropriate list of CSR (from sspecifications) - //csrr t2,mvendorid - //csrr t2,marchid - //csrr t2,mimpid - csrr t2,mhartid - - // machine trap setup - csrr t2,mstatus - csrr t2,misa - csrr t2,mie - csrr t2,mtvec - //FIXME csrr t2,mtval - - // machine trap handling - csrr t2,mscratch - csrr t2,mepc - csrr t2,mcause - csrr t2,mip - - // ----------------------- - // Debug CSRs - - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 3 debugger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 3<<6 | 3<<0 - csrr t2,dcsr - bne t1,t2,_debugger_fail - csrr t2,dpc - beq x0,t2,_debugger_fail - //Already test this csrr t2,dscratch //dscratch0 - //Already test this csrr t2,0x7b3 //dscratch1 - - // Set ebreakm in dcsr - li t1, 4<<28 | 3<<6 | 3<<0| 1<<15 - csrw dcsr, t1 - - // ---------------------- - // Trigger CSRs - - // Expect TMATCH=TDATA1 - // 31:28 type = 2 - // 27 dmode = 1 - // 15:12 action = 1 - // 6 m(achine) = 1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - csrr t2,tselect - bne x0,t2,_debugger_fail - csrr t2,tdata2 - bne x0,t2,_debugger_fail - csrr t2,tdata3 - bne x0,t2,_debugger_fail - csrr t2,0x7a8 //mcontext - bne x0,t2,_debugger_fail - csrr t2,0x7aa //scontext - bne x0,t2,_debugger_fail - - j _debugger_end - -_debugger_ebreak: - li t0, 4<<28 | 3<<6 | 3<<0 - csrr t1, dcsr - bne t0, t1, _debugger_fail - // Increment glb_debug_status - la a1, glb_debug_status - lw t1, 0(a1) - addi t1,t1,1 - sw t1, 0(a1) - // Repeat executing debug code until debug status = hart_status + 3 - addi t0, t2, 3 - beq t1, t0, _debugger_end - // Execute non-compressed ebreak for iteration 2 - addi t0, t2, 2 - beq t1, t0, _uncompressed_ebreak - // Debugger Un-Stack and call debugger code from start using ebreak - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - ebreak -_uncompressed_ebreak: - // Debugger Un-Stack and call debugger code from start using ebreak - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - .4byte 0x00100073 # ebreak - -_debugger_trigger_in_debug: - // setup address to trigger on - la a1, _debugger_trig_point - csrw tdata2,a1 - li t1, 1<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - // Clear glb_expect_debug_entry - // If we trig, we'll reenter debug and - // test will fail due to 0 flag - la a1, glb_expect_debug_entry - li t1, 0 - sw t1, 0(a1) -_debugger_trig_point: - // Should _not_trig here - nop - // Clear trigger - li t1, 0<<2 - csrw tdata1, t1 - j _debugger_end - -_debugger_trigger_disabled_in_debug: - // setup address to trigger on - la a1, _debugger_trig_point_dis - // Set trig enable to 0 - csrw tdata2,a1 - li t1, 0<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 0 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - // Clear glb_expect_debug_entry - // If we trig, we'll reenter debug and - // test will fail due to 0 flag - la a1, glb_expect_debug_entry - li t1, 0 - sw t1, 0(a1) -_debugger_trig_point_dis: - // Should _not_trig here - nop - // Clear trigger - li t1, 0<<2 - csrw tdata1, t1 - j _debugger_end -_debugger_wfi_test: - la a1, glb_debug_status - csrr t2,dcsr - // ebreakm is set by previous test - li t1, 4<<28 | 3<<6 | 3<<0 | 1<<15 - bne t1, t2, _debugger_fail - - // If the following wfi is not converted - // to a nop, test will hang - wfi - j _debugger_end - -_debugger_end: - // Check counter values. They should have increased while in debug - // regardless of stopcount bit in csr - csrr t1, mcycle - la a1, glb_mcycle_start - lw t2, 0(a1) - sub t1, t1, t2 - beq t1, x0, _debugger_fail - - csrr t1, minstret - la a1, glb_minstret_start - lw t2, 0(a1) - sub t1, t1, t2 - beq t1, x0, _debugger_fail - - // If single stepping, do not clear - la a1, glb_hart_status - lw t0, 0(a1) - li t1, 18 - beq t0, t1, _debugger_end_continue - - // Clear debug entry expectation flag - la a1, glb_expect_debug_entry - sw x0, 0(a1) -_debugger_end_continue: - // Debugger Un-Stack - //lw t0, 0(a0) - la a0, __debugger_stack_start - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - dret -_debugger_fail: //Test Failed - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - nop - nop - nop - nop - diff --git a/cv32e40x/tests/programs/custom/debug_test/debugger_exception.S b/cv32e40x/tests/programs/custom/debug_test/debugger_exception.S deleted file mode 100644 index d3d1e9dd4c..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test/debugger_exception.S +++ /dev/null @@ -1,77 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger Exception code -******************************************************************************* -*/ - -#include "corev_uvmt.h" - -.section .debugger_exception, "ax" -.global _debugger_exception_start -.global glb_debug_status -.global glb_hart_status -.global glb_debug_exception_status -.global glb_expect_debug_exception -//.global _debugger_fail -//.global _debugger_end -.set test_fail, 0x1 - -_debugger_exception_start: - // First check to see if exception was expected - la a1, glb_expect_debug_exception - lw t1, 0(a1) - //beq x0,t1,_debugger_fail - beq x0,t1,_debugger_exception_fail - - // Set exception status to hart status - la a1, glb_hart_status - lw t1, 0(a1) - la a2, glb_debug_exception_status - sw t1, 0(a2) - - //j _debugger_end - j _debugger_exception_end - -// Should be exact same function as implmented in debugger.S - // I can't seem to point to that symble from this file -_debugger_exception_end: - // Clear debug entry expectation flag - la a1, glb_expect_debug_entry - sw x0, 0(a1) - la a1, glb_expect_debug_exception - sw x0, 0(a1) - // Debugger Un-Stack - //lw t0, 0(a0) - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - dret -// Should be exact same function as implmented in debugger.S -_debugger_exception_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - nop - nop - nop - nop - diff --git a/cv32e40x/tests/programs/custom/debug_test/handlers.S b/cv32e40x/tests/programs/custom/debug_test/handlers.S deleted file mode 100644 index 0bdee311f8..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test/handlers.S +++ /dev/null @@ -1,349 +0,0 @@ -/* -* Copyright 2019 ETH Zürich and University of Bologna -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include "corev_uvmt.h" - -/* Exception codes */ -#define EXCEPTION_ILLEGAL_INSN 2 -#define EXCEPTION_BREAKPOINT 3 -#define EXCEPTION_ECALL_M 11 - -.section .text.handlers -.global __no_irq_handler -.global u_sw_irq_handler -.global m_software_irq_handler -.global m_timer_irq_handler -.global m_external_irq_handler -.global m_fast0_irq_handler -.global m_fast1_irq_handler -.global m_fast2_irq_handler -.global m_fast3_irq_handler -.global m_fast4_irq_handler -.global m_fast5_irq_handler -.global m_fast6_irq_handler -.global m_fast7_irq_handler -.global m_fast8_irq_handler -.global m_fast9_irq_handler -.global m_fast10_irq_handler -.global m_fast11_irq_handler -.global m_fast12_irq_handler -.global m_fast13_irq_handler -.global m_fast14_irq_handler -.global m_fast15_irq_handler - -.weak m_software_irq_handler -.weak m_timer_irq_handler -.weak m_external_irq_handler -.weak m_fast0_irq_handler -.weak m_fast1_irq_handler -.weak m_fast2_irq_handler -.weak m_fast3_irq_handler -.weak m_fast4_irq_handler -.weak m_fast5_irq_handler -.weak m_fast6_irq_handler -.weak m_fast7_irq_handler -.weak m_fast8_irq_handler -.weak m_fast9_irq_handler -.weak m_fast10_irq_handler -.weak m_fast11_irq_handler -.weak m_fast12_irq_handler -.weak m_fast13_irq_handler -.weak m_fast14_irq_handler -.weak m_fast15_irq_handler - -.global glb_illegal_insn_status -.global glb_ebreak_status -.global glb_expect_illegal_insn -.global glb_expect_ebreak_handler -.global glb_exception_ebreak_status -.global glb_expect_irq_entry -.set test_ret_val, CV_VP_STATUS_FLAGS_BASE -.set test_fail, 0x1 - -/* exception handling */ -__no_irq_handler: - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - - la a0, no_exception_handler_msg - jal ra, puts - - // Check if we expected to enter irq - la a1, glb_expect_irq_entry - lw t0, 0(a1) - beq t0, x0, _irq_fail - - // Clear entry flag - li t0, 0 - sw t0, 0(a1) - //j __no_irq_handler - - // Return - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret - -_irq_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - ret - -u_sw_irq_handler: - /* While we are still using puts in handlers, save all caller saved - regs. Eventually, some of these saves could be deferred. */ - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr t0, mcause - li t1, EXCEPTION_ILLEGAL_INSN - beq t0, t1, handle_illegal_insn - li t1, EXCEPTION_ECALL_M - beq t0, t1, handle_ecall - li t1, EXCEPTION_BREAKPOINT - beq t0, t1, handle_ebreak - j handle_unknown - -handle_ecall: - la a0, ecall_msg - jal ra, handle_syscall - j end_handler_incr_mepc - -m_software_irq_handler: - j __no_irq_handler - -m_timer_irq_handler: - j __no_irq_handler - -m_external_irq_handler: - j __no_irq_handler - -m_fast0_irq_handler: - j __no_irq_handler - -m_fast1_irq_handler: - j __no_irq_handler - -m_fast2_irq_handler: - j __no_irq_handler - -m_fast3_irq_handler: - j __no_irq_handler - -m_fast4_irq_handler: - j __no_irq_handler - -m_fast5_irq_handler: - j __no_irq_handler - -m_fast6_irq_handler: - j __no_irq_handler - -m_fast7_irq_handler: - j __no_irq_handler - -m_fast8_irq_handler: - j __no_irq_handler - -m_fast9_irq_handler: - j __no_irq_handler - -m_fast10_irq_handler: - j __no_irq_handler - -m_fast11_irq_handler: - j __no_irq_handler - -m_fast12_irq_handler: - j __no_irq_handler - -m_fast13_irq_handler: - j __no_irq_handler - -m_fast14_irq_handler: - j __no_irq_handler - -m_fast15_irq_handler: - j __no_irq_handler - - -handle_ebreak: - /* TODO support debug handling requirements. */ - la a0, ebreak_msg - jal ra, puts - // Check if expecting ebreak handler - la a0, glb_expect_ebreak_handler - lw t0, 0(a0) - bne t0, x0, cont_handle_ebreak - // Not expecting ebreak, assert test failed - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) - j end_handler_incr_mepc -cont_handle_ebreak: - //increment hart status - sw x0, 0(a0) - la a0, glb_ebreak_status - lw t0, 0(a0) - addi t0,t0,1 - sw t0, 0(a0) - j end_handler_incr_mepc - - - -handle_illegal_insn: - la a0, illegal_insn_msg - jal ra, puts - // Check if expecting illegal instruction - la a0, glb_expect_illegal_insn - lw t0, 0(a0) - bne t0, x0, cont_illegal_insn - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) //Test Failed - j end_handler_incr_mepc -cont_illegal_insn: - //increment hart status - sw x0, 0(a0) - la a0, glb_illegal_insn_status - lw t0, 0(a0) - addi t0,t0,1 - sw t0, 0(a0) - - // Check if we are expected to execute ebreak - la a0, glb_exception_ebreak_status - lw t0, 0(a0) - // End handler if no ebreak is to be executed - beq t0, x0, end_handler_incr_mepc - - // Clear ebreak flag - sw x0, 0(a0) - // Execute ebreak - .4byte 0x00100073 - // Exit handler - j end_handler_incr_mepc - - j end_handler_incr_mepc - - - - - - - -handle_unknown: - la a0, unknown_msg - jal ra, puts - /* We don't know what interrupt/exception is being handled, so don't - increment mepc. */ - j end_handler_ret - - - - - - -end_handler_incr_mepc: - csrr t0, mepc - lb t1, 0(t0) - li a0, 0x3 - and t1, t1, a0 - /* Increment mepc by 2 or 4 depending on whether the instruction at mepc - is compressed or not. */ - bne t1, a0, end_handler_incr_mepc2 - addi t0, t0, 2 -end_handler_incr_mepc2: - addi t0, t0, 2 - csrw mepc, t0 -end_handler_ret: - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret -/* this interrupt can be generated for verification purposes, random or when the - PC is equal to a given value*/ -verification_irq_handler: - mret - -.section .rodata -illegal_insn_msg: - .string "illegal instruction exception handler entered\n" -ecall_msg: - .string "ecall exception handler entered\n" -ebreak_msg: - .string "ebreak exception handler entered\n" -unknown_msg: - .string "unknown exception handler entered\n" -no_exception_handler_msg: - .string "no exception handler installed\n" diff --git a/cv32e40x/tests/programs/custom/debug_test/single_step.S b/cv32e40x/tests/programs/custom/debug_test/single_step.S deleted file mode 100644 index 4337b197fe..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test/single_step.S +++ /dev/null @@ -1,233 +0,0 @@ -#Copyright 202[x] Silicon Labs, Inc. - -#This file, and derivatives thereof are licensed under the -#Solderpad License, Version 2.0 (the "License"); -#Use of this file means you agree to the terms and conditions -#of the license and are in full compliance with the License. -#You may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.0/ -# -#Unless required by applicable law or agreed to in writing, software -#and hardware implementations thereof -#distributed under the License is distributed on an "AS IS" BASIS, -#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. -#See the License for the specific language governing permissions and -#limitations under the License. - -#include "corev_uvmt.h" - -.section .single_step_code_sect, "ax" -.set timer_reg_addr, CV_VP_INTR_TIMER_BASE+0 -.set timer_val_addr, CV_VP_INTR_TIMER_BASE+4 -.set test_ret_val, CV_VP_STATUS_FLAGS_BASE -.set test_fail, 0x1 - -.global glb_step_info -.global glb_expect_debug_entry -.global glb_expect_illegal_insn -.global glb_expect_irq_entry -.global _step_trig_point -.global _step_trig_exit -.global _single_step - - -_single_step: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - // Expect debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - // Set step cause to 1 - enable single stepping - la a1, glb_step_info - li t0, 1 - sw t0, 0(a1) - - // Set t0 to 0 - li t0, 0 - - // Enter debug mode to execute cause=1 - c.ebreak - - // To check if debug code increments DPC correctly, - // Load up t0 in first instruction after ebreak - li t0, 1 - beq t0, x0, _single_step_fail - - // We are single stepping, WFI should complete as NOP - // Test will hang here if WFI is not converted properly - wfi - - // illegal instruction - la a1, glb_expect_illegal_insn - li t0, 1 - sw t0, 0(a1) - - la a1, glb_step_info - li t0, 3 - sw t0, 0(a1) - - csrr t0, dcsr // illegal - - la a1, glb_expect_illegal_insn - li t0, 1 - sw t0, 0(a1) - dret // illegal - - // Trigger match setup - la a1, glb_step_info - li t0, 4 - sw t0, 0(a1) - nop - nop - li t0, 0 - -_step_trig_point: - li t0, 1 // trig here - -_step_trig_exit: - addi t0, t0,2 // debug code moves dpc to here - li t1, 2 - // If trigger was correct, debug code skips - // loading of t0 to 1, and t0 should be of value 2 - bne t0, t1, _single_step_fail - - - //----------------- - // Stepping with interrupt, stepie=1 - la a1, glb_step_info - li t0, 5 - sw t0, 0(a1) - - // Expect irq flag - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - // Assert irq - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 2 - sw t0, 0(a1) - -_irq_wait_loop: - la a1, glb_expect_irq_entry - lw t0, 0(a1); - bne t0, x0, _irq_wait_loop - - - //----------------- - // Stepping with interrupt, stepie=0 - la a1, glb_step_info - li t0, 6 - sw t0, 0(a1) - - // Assert irq - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 2 - sw t0, 0(a1) - - // Wait out some instructions to give IRQ a chance - // Report an ERROR if IRQ taken as we did not set glb_expect_irq_entry flag - nop - nop - nop - nop - - // De-Assert irq - li a1, timer_reg_addr - li t0, 0x00000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 1 - sw t0, 0(a1) - - nop - nop - - # set step reason to 7 (step with c.ebreak) - la a1, glb_step_info - li t0, 7 - sw t0, 0(a1) - - # Ebreak to cover ebreak vs step cause priority - c.ebreak - - # set step reason to 8 (step with ebreak) - la a1, glb_step_info - li t0, 8 - sw t0, 0(a1) - - # Ebreak to cover ebreak vs step cause priority - .4byte 0x00100073 - - # Set step reason to 9, ebreak without dcsr.ebreakm - la a1, glb_step_info - li t0, 9 - sw t0, 0(a1) - - # Expect to enter ebreak handler - la a0, glb_expect_ebreak_handler - li t0, 1 - sw t0, 0(a0) - - .4byte 0x00100073 - - # Expect to enter ebreak handler - la a0, glb_expect_ebreak_handler - li t0, 1 - sw t0, 0(a0) - # Set step reason to 10, cebreak without dcsr.ebreakm - la a1, glb_step_info - li t0, 10 - sw t0, 0(a1) - - c.ebreak - - # set step reason to 0, normal step - la a1, glb_step_info - li t0, 0 - sw t0, 0(a1) - - ecall - // Cause 2, disable single stepping - la a1, glb_step_info - li t0, 2 - sw t0, 0(a1) - nop - nop - j _single_step_done - -_single_step_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - // Turn off single step - la a1, glb_step_info - li t0, 2 - sw t0, 0(a1) - - j _single_step_done - -_single_step_done: - lw t0, 0(sp) - lw t1, 4(sp) - lw a0, 8(sp) - lw a1, 12(sp) - lw a2, 16(sp) - lw ra, 20(sp) - addi sp,sp,30 - ret diff --git a/cv32e40x/tests/programs/custom/debug_test/test.yaml b/cv32e40x/tests/programs/custom/debug_test/test.yaml deleted file mode 100644 index 3f975a0737..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test/test.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Test definition YAML for test - -# Debug directed test -name: debug_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -program: debug_test -description: > - Debug directed test -# FIXME:The minstret compare issues with this test should be filed as bug and fixed -disable_csr_check: - - minstret diff --git a/cv32e40x/tests/programs/custom/debug_test/trigger_code.S b/cv32e40x/tests/programs/custom/debug_test/trigger_code.S deleted file mode 100644 index f66a54ca2c..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test/trigger_code.S +++ /dev/null @@ -1,160 +0,0 @@ -#Copyright 202[x] Silicon Labs, Inc. -# -#This file, and derivatives thereof are licensed under the -#Solderpad License, Version 2.0 (the "License"); -#Use of this file means you agree to the terms and conditions -#of the license and are in full compliance with the License. -#You may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.0/ -# -#Unless required by applicable law or agreed to in writing, software -#and hardware implementations thereof -#distributed under the License is distributed on an "AS IS" BASIS, -#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. -#See the License for the specific language governing permissions and -#limitations under the License. - -#include "corev_uvmt.h" - -.section .trigger_code_sect, "ax" -.set test_ret_val, CV_VP_STATUS_FLAGS_BASE -.set test_fail, 0x1 - -.global _trigger_exit -.global _trigger_test -.global _trigger_code -.global _trigger_test_ebreak -.global _trigger_code_ebreak -.global _trigger_code_illegal_insn -.global _trigger_code_branch_insn -.global _trigger_code_multicycle_insn -.global _trigger_code_cebreak -.type _trigger_code, @function -.type _trigger_code_ebreak, @function -.type _trigger_code_cebreak, @function -.type _trigger_code_illegal_insn, @function -.type _trigger_code_branch_insn, @function -.type _trigger_code_multicycle_insn, @function - - -_trigger_code_ebreak: - .4byte 0x00100073 - ret - -_trigger_code_cebreak: - c.ebreak - ret -_trigger_code_illegal_insn: - dret - ret -_trigger_code_branch_insn: - beq t0, t1, __trigger_fail - ret -_trigger_code_multicycle_insn: - mulhsu t0, t0, t1 - ret -_trigger_test_ebreak: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - # a0 holds argument - # 0 - ebreak - # 1 - c.c.ebreak - # 2 - illegal instruction - # 3 - branch instruction - # 4 - multicycle instruction (mulhsu) - - mv t1, a0 - li t0, 0 - beq t0, t1, _jmp_ebreak - - li t0, 1 - beq t0, t1, _jmp_cebreak - - li t0, 2 - beq t0, t1, _jmp_illegal_insn - - li t0, 3 - beq t0, t1, _jmp_branch_insn - - li t0, 4 - beq t0, t1, _jmp_multicycle_insn - -_jmp_ebreak: - jal ra, _trigger_code_ebreak - j __trigger_done -_jmp_cebreak: - jal ra, _trigger_code_cebreak - j __trigger_done -_jmp_illegal_insn: - jal ra, _trigger_code_illegal_insn - j __trigger_done -_jmp_branch_insn: - jal ra, _trigger_code_branch_insn - j __trigger_done -_jmp_multicycle_insn: - jal ra, _trigger_code_multicycle_insn - j __trigger_done - -# j __trigger_done - - - // We will trigger on the _trigger_code addess - // We should not expect the first instruction to execute - // The debugger code will move the PC to the trigger_exit_code - // Which essentially avoid executing all of the code in the trigger_code -_trigger_code: - add a2,a0,a1 - ret -_trigger_exit: - ret -_trigger_test: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - // a0 holds input to function (expect trigger) - mv t1, a0 - - // Load up some random data to add - li a0, 7893 - li a1, 1452 - li a2, 191 // a2 value will be overwrriten by _trigger_code - mv t2, a2 // keep a copy of the value to compare against - - // Call function that will have a trigger match - // If no trigger match, then a2=a0+a1 - // Else if trigger matched, then a2 is not modified - jal ra, _trigger_code - - // if (expect trigger) check against original value (in t2) - bne t1 ,x0, __trigger_check - // else - // trigger match not expected, function executes as normal - // set execpted value to t2 = a0 + a1 - add t2, a0, a1 -__trigger_check: - beq t2,a2,__trigger_done -__trigger_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) -__trigger_done: - lw t0, 0(sp) - lw t1, 4(sp) - lw a0, 8(sp) - lw a1, 12(sp) - lw a2, 16(sp) - lw ra, 20(sp) - addi sp,sp,30 - ret diff --git a/cv32e40x/tests/programs/custom/debug_test_boot_set/debug_test_reset.c b/cv32e40x/tests/programs/custom/debug_test_boot_set/debug_test_reset.c deleted file mode 100644 index edf6e2a93a..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_boot_set/debug_test_reset.c +++ /dev/null @@ -1,43 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Basic debugger test. Needs more work and bugs fixed -** It will launch a debug request and have debugger code execute (debugger.S) -******************************************************************************* -*/ - -#include -#include - -extern volatile uint32_t test_debugger_entry; - -#define MACHINE 3 -int main(int argc, char *argv[]) -{ - unsigned int check_reg; - check_reg = test_debugger_entry; - - printf("Debug reg = %08x\n", check_reg); - // Debug code will write 0xff to this register - // If debug mode has not been entered, we will fail - if ((check_reg & 0xff) == 0xa5) { - return EXIT_SUCCESS; - } - else { - return EXIT_FAILURE; - } -} diff --git a/cv32e40x/tests/programs/custom/debug_test_boot_set/debugger.S b/cv32e40x/tests/programs/custom/debug_test_boot_set/debugger.S deleted file mode 100644 index 89fcd1bd3a..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_boot_set/debugger.S +++ /dev/null @@ -1,55 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger code -******************************************************************************* -*/ - -#include "corev_uvmt.h" - -.section .debugger, "ax" -.global _debugger_start -.set test_fail, 0x1 -.set test_debugger_ok, 0xa5 - -_debugger_start: - // No code should have been run before this - // check dpc == boot_addr == 0x80 - csrr t1, dpc - li t2, 0x80 # Boot addr - bne t1, t2, _debugger_error - - // Write known value to memory@0x1000 - // We don't have any globals or pointers - // at this time, so we must rely on - // memory (hopefully) not being used - la a0, test_debugger_entry - li t0, test_debugger_ok - sw t0, 0(a0) - dret - -_debugger_error: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - dret - -.section .data -.global test_debugger_entry -test_debugger_entry: - .word 0 diff --git a/cv32e40x/tests/programs/custom/debug_test_boot_set/test.yaml b/cv32e40x/tests/programs/custom/debug_test_boot_set/test.yaml deleted file mode 100644 index bf67489026..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_boot_set/test.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Test definition YAML for test - -# Debug directed test for debug request at reset -name: debug_test_boot_set -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -program: debug_test_reset -description: > - Debug directed test, debug at reset -plusargs: > - +debug_boot_set - +fetch_initial_delay diff --git a/cv32e40x/tests/programs/custom/debug_test_reset/debug_test_reset.c b/cv32e40x/tests/programs/custom/debug_test_reset/debug_test_reset.c deleted file mode 100644 index edf6e2a93a..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_reset/debug_test_reset.c +++ /dev/null @@ -1,43 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Basic debugger test. Needs more work and bugs fixed -** It will launch a debug request and have debugger code execute (debugger.S) -******************************************************************************* -*/ - -#include -#include - -extern volatile uint32_t test_debugger_entry; - -#define MACHINE 3 -int main(int argc, char *argv[]) -{ - unsigned int check_reg; - check_reg = test_debugger_entry; - - printf("Debug reg = %08x\n", check_reg); - // Debug code will write 0xff to this register - // If debug mode has not been entered, we will fail - if ((check_reg & 0xff) == 0xa5) { - return EXIT_SUCCESS; - } - else { - return EXIT_FAILURE; - } -} diff --git a/cv32e40x/tests/programs/custom/debug_test_reset/debugger.S b/cv32e40x/tests/programs/custom/debug_test_reset/debugger.S deleted file mode 100644 index f5a24e9859..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_reset/debugger.S +++ /dev/null @@ -1,489 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger code -******************************************************************************* -*/ -#include "corev_uvmt.h" - - -.section .debugger, "ax" -.global _debugger_start - -.set test_fail, 0x1 -.set test_debugger_ok, 0xa5 - -_debugger_start: - // No code should have been run before this - // check dpc == boot_addr == 0x80 - csrr t1, dpc - li t2, 0x80 # Boot addr - bne t1, t2, _debugger_error - - // Write known value to memory - // We don't have any globals or pointers - // at this time, so we must rely on - // memory (hopefully) not being used - la a0, test_debugger_entry - li t0, test_debugger_ok - sw t0, 0(a0) - -_debugger_trigger_regs_access: - # R/W trigger regs otherwise not accessed - # to close coverage holes - li t0, 0xff - csrw 0x7a4, t0 # tinfo - csrr t0, 0x7a4 - li t1, 4 - bne t0, t1, _debugger_error - - li t0, 0xff - csrw 0x7a3, t0 # tdata3 - csrr t0, 0x7a3 - bne t0, x0, _debugger_error - - li t0, 0xff - csrw 0x7a0, t0 # tsel - csrr t0, 0x7a0 - bne t0, x0, _debugger_error - - # CSR access with all instructions to cover - # functional coverage - # TDATA1, CSRRSI - csrr t1, 0x7A1 - csrrsi t0, 0x7A1, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 - bne t0, t1, _debugger_error - - # TDATA1, CSRRCI - csrr t1, 0x7A1 - csrrci t0, 0x7A1, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 0<<2 - bne t0, t1, _debugger_error - - # TDATA1, CSRRS - csrr t1, 0x7A1 - li t0, 0x4 - csrrs t0, 0x7A1, t0 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 - bne t0, t1, _debugger_error - - # TDATA1, CSRRC - csrr t1, 0x7A1 - li t0, 0x4 - csrrc t0, 0x7A1, t0 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 0<<2 - bne t0, t1, _debugger_error - - # TDATA1, CSRRWI - csrr t1, 0x7A1 - csrrwi t0, 0x7A1, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 - bne t0, t1, _debugger_error - - # TDATA1, CSRRW - csrr t1, 0x7A1 - li t0, 0xffffffff - csrrw t0, 0x7A1, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 - bne t0, t1, _debugger_error - - # TDATA2, CSRRSI - csrw 0x7A2, x0 # clear before test - csrr t1, 0x7A2 - csrrsi t0, 0x7A2, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A2 - li t1, 1<<2 - bne t0, t1, _debugger_error - - # TDATA2, CSRRCI - csrr t1, 0x7A2 - csrrci t0, 0x7A2, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A2 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA2, CSRRS - csrr t1, 0x7A2 - li t0, 0xa5a5a5a5 - csrrs t0, 0x7A2, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A2 - li t1, 0xa5a5a5a5 - bne t0, t1, _debugger_error - - # TDATA2, CSRRC - csrr t1, 0x7A2 - li t0, 0xFFFFFFFF - csrrc t0, 0x7A2, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A2 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA2, CSRRWI - csrr t1, 0x7A2 - csrrwi t0, 0x7A2, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A2 - li t1, 1<<2 - bne t0, t1, _debugger_error - - # TDATA3, CSRRSI - csrw 0x7A3, x0 # clear before test - csrr t1, 0x7A3 - csrrsi t0, 0x7A3, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRCI - csrr t1, 0x7A3 - csrrci t0, 0x7A3, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRS - csrr t1, 0x7A3 - li t0, 0xa5a5a5a5 - csrrs t0, 0x7A3, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRC - csrr t1, 0x7A3 - li t0, 0xFFFFFFFF - csrrc t0, 0x7A3, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TDATA3, CSRRWI - csrr t1, 0x7A3 - csrrwi t0, 0x7A3, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A3 - li t1, 0x0 - bne t0, t1, _debugger_error - - # TINFO, CSRRSI - csrw 0x7A4, x0 # clear before test - csrr t1, 0x7A4 - csrrsi t0, 0x7A4, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A4 - li t1, 4 - bne t0, t1, _debugger_error - - # TINFO, CSRRCI - csrr t1, 0x7A4 - csrrci t0, 0x7A4, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A4 - li t1, 4 - bne t0, t1, _debugger_error - - # TINFO, CSRRS - csrr t1, 0x7A4 - li t0, 0xa5a5a5a5 - csrrs t0, 0x7A4, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A4 - li t1, 4 - bne t0, t1, _debugger_error - - # TINFO, CSRRC - csrr t1, 0x7A4 - li t0, 0xFFFFFFFF - csrrc t0, 0x7A4, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A4 - li t1, 4 - bne t0, t1, _debugger_error - - # TINFO, CSRRWI - csrr t1, 0x7A4 - csrrwi t0, 0x7A4, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A4 - li t1, 4 - bne t0, t1, _debugger_error - - # TSELECT, CSRRSI - csrw 0x7A0, x0 # clear before test - csrr t1, 0x7A0 - csrrsi t0, 0x7A0, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A0 - li t1, 0 - bne t0, t1, _debugger_error - - # TSELECT, CSRRCI - csrr t1, 0x7A0 - csrrci t0, 0x7A0, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A0 - li t1, 0 - bne t0, t1, _debugger_error - - # TSELECT, CSRRS - csrr t1, 0x7A0 - li t0, 0xa5a5a5a5 - csrrs t0, 0x7A0, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A0 - li t1, 0 - bne t0, t1, _debugger_error - - # TSELECT, CSRRC - csrr t1, 0x7A0 - li t0, 0xFFFFFFFF - csrrc t0, 0x7A0, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7A0 - li t1, 0 - bne t0, t1, _debugger_error - - # TSELECT, CSRRWI - csrr t1, 0x7A0 - csrrwi t0, 0x7A0, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7A0 - li t1, 0 - bne t0, t1, _debugger_error - - # Store dscratch0 - csrr t2, 0x7B2 - # DSCRATCH0, CSRRSI - csrw 0x7B2, x0 # clear before test - csrr t1, 0x7B2 - csrrsi t0, 0x7B2, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B2 - li t1, 4 - bne t0, t1, _debugger_error - - # DSCRATCH0, CSRRCI - csrr t1, 0x7B2 - csrrci t0, 0x7B2, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B2 - li t1, 0 - bne t0, t1, _debugger_error - - # DSCRATCH0, CSRRS - csrr t1, 0x7B2 - li t0, 0xa5a5a5a5 - csrrs t0, 0x7B2, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7B2 - li t1, 0xa5a5a5a5 - bne t0, t1, _debugger_error - - # DSCRATCH0, CSRRC - csrr t1, 0x7B2 - li t0, 0xFFFFFFFF - csrrc t0, 0x7B2, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7B2 - li t1, 0 - bne t0, t1, _debugger_error - - # DSCRATCH0, CSRRWI - csrr t1, 0x7B2 - csrrwi t0, 0x7B2, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B2 - li t1, 0x4 - bne t0, t1, _debugger_error - # Restore dscratch0 - csrw 0x7B2, t2 - - # Store dscratch1 - csrr t2, 0x7B3 - # DSCRATCH1, CSRRSI - csrw 0x7B3, x0 # clear before test - csrr t1, 0x7B3 - csrrsi t0, 0x7B3, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B3 - li t1, 4 - bne t0, t1, _debugger_error - - # DSCRATCH1, CSRRCI - csrr t1, 0x7B3 - csrrci t0, 0x7B3, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B3 - li t1, 0 - bne t0, t1, _debugger_error - - # DSCRATCH1, CSRRS - csrr t1, 0x7B3 - li t0, 0xa5a5a5a5 - csrrs t0, 0x7B3, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7B3 - li t1, 0xa5a5a5a5 - bne t0, t1, _debugger_error - - # DSCRATCH1, CSRRC - csrr t1, 0x7B3 - li t0, 0xFFFFFFFF - csrrc t0, 0x7B3, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7B3 - li t1, 0 - bne t0, t1, _debugger_error - - # DSCRATCH1, CSRRWI - csrr t1, 0x7B3 - csrrwi t0, 0x7B3, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B3 - li t1, 0x4 - bne t0, t1, _debugger_error - # Restore dscratch1 - csrw 0x7B3, t2 - - # Store dpc - csrr t2, 0x7B1 - # DPC, CSRRSI - csrw 0x7B1, x0 # clear before test - csrr t1, 0x7B1 - csrrsi t0, 0x7B1, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B1 - li t1, 4 - bne t0, t1, _debugger_error - - # DPC, CSRRCI - csrr t1, 0x7B1 - csrrci t0, 0x7B1, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B1 - li t1, 0 - bne t0, t1, _debugger_error - - # DPC, CSRRS - csrr t1, 0x7B1 - li t0, 0xfffffff0 - csrrs t0, 0x7B1, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7B1 - li t1, 0xfffffff0 - bne t0, t1, _debugger_error - - # DPC, CSRRC - csrr t1, 0x7B1 - li t0, 0xFFFFFFFF - csrrc t0, 0x7B1, t0 - bne t0, t1, _debugger_error - csrr t0, 0x7B1 - li t1, 0 - bne t0, t1, _debugger_error - - # DPC, CSRRWI - csrr t1, 0x7B1 - csrrwi t0, 0x7B1, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, 0x7B1 - li t1, 0x4 - bne t0, t1, _debugger_error - - # Restore dpc - csrw 0x7B1, t2 - - # Store dcsr - csrr t2, dcsr - # DCSR, CSRRSI - csrw dcsr, x0 # clear before test - csrr t1, dcsr - csrrsi t0, dcsr, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, dcsr - addi t1, t2, 0x4 - bne t0, t1, _debugger_error - - # DCSR, CSRRCI - csrr t1, dcsr - csrrci t0, dcsr, 0x4 # Clear bit 2 - bne t0, t1, _debugger_error - csrr t0, dcsr - bne t0, t2, _debugger_error - - # DCSR, CSRRS - csrr t1, dcsr - li t0, 0 - addi t0, t2, 4 - csrrs t0, dcsr, t0 - bne t0, t1, _debugger_error - csrr t0, dcsr - addi t1, t2, 0x4 - bne t0, t1, _debugger_error - - # DCSR, CSRRC - csrr t1, dcsr - li t0, 0x4 - csrrc t0, dcsr, t0 - bne t0, t1, _debugger_error - csrr t0, dcsr - bne t0, t2, _debugger_error - - # DCSR, CSRRWI - csrr t1, dcsr - csrrwi t0, dcsr, 0x4 # Set bit 2 - bne t0, t1, _debugger_error - csrr t0, dcsr - addi t1, t2, 0x4 - bne t0, t1, _debugger_error - - # Restore dpc - csrw dcsr, t2 - dret - -_debugger_error: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - dret - -.section .data -.global test_debugger_entry -test_debugger_entry: - .word 0 diff --git a/cv32e40x/tests/programs/custom/debug_test_reset/test.yaml b/cv32e40x/tests/programs/custom/debug_test_reset/test.yaml deleted file mode 100644 index aefc002e6e..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_reset/test.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# Test definition YAML for test - -# Debug directed test for debug request at reset -name: debug_test_reset -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Debug directed test, debug at reset -plusargs: > - +reset_debug - diff --git a/cv32e40x/tests/programs/custom/debug_test_trigger/debug_test.c b/cv32e40x/tests/programs/custom/debug_test_trigger/debug_test.c deleted file mode 100644 index db5a005051..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_trigger/debug_test.c +++ /dev/null @@ -1,207 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Basic debugger test. Needs more work and bugs fixed -** It will launch a debug request and have debugger code execute (debugger.S) -******************************************************************************* -*/ - -#include -#include -#include "corev_uvmt.h" - -volatile int glb_hart_status = 0; // Written by main code only, read by debug code -volatile int glb_debug_status = 0; // Written by debug code only, read by main code -volatile int glb_ebreak_status = 0; // Written by ebreak code only, read by main code -volatile int glb_illegal_insn_status = 0; // Written by illegal instruction code only, read by main code -volatile int glb_debug_exception_status = 0; // Written by debug code during exception only -volatile int glb_exception_ebreak_status = 0; // Written by main code, read by exception handler - -// Expectation flags. Raise an error if handler or routine is enterred when not expected, -volatile int glb_expect_illegal_insn = 0; -volatile int glb_expect_ebreak_handler = 0; -volatile int glb_expect_debug_entry = 0; -volatile int glb_expect_debug_exception = 0; -volatile int glb_expect_irq_entry = 0; -// Counter values -// Checked at start and end of debug code -// Only lower 32 bits checked, as simulation cannot overflow on 32 bits -volatile int glb_mcycle_start = 0; -volatile int glb_mcycle_end = 0; -volatile int glb_minstret_start = 0; -volatile int glb_minstret_end = 0; -#define TEST_FAILED *(volatile int *)CV_VP_STATUS_FLAGS_BASE = 1 -#define TEST_PASSED *(volatile int *)CV_VP_STATUS_FLAGS_BASE = 123456789 - -extern int __stack_start; -extern int _trigger_code; -extern int _trigger_code_ebreak; -extern int _trigger_code_cebreak; -extern int _trigger_code_illegal_insn; -extern int _trigger_code_branch_insn; -extern int _trigger_code_multicycle_insn; -typedef union { - struct { - unsigned int start_delay : 15; // 14: 0 - unsigned int rand_start_delay : 1; // 15 - unsigned int pulse_width : 13; // 28:16 - unsigned int rand_pulse_width : 1; // 29 - unsigned int pulse_mode : 1; // 30 0 = level, 1 = pulse - unsigned int value : 1; // 31 - } fields; - unsigned int bits; -} debug_req_control_t; - -#define DEBUG_REQ_CONTROL_REG *(volatile int *) CV_VP_DEBUG_CONTROL_BASE -#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE+0)) -#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE+4)) - -typedef union { - struct { - unsigned int uie : 1; // 0 // Implemented if USER mode enabled - unsigned int sie : 1; // 1 - unsigned int wpri : 1; // 2 - unsigned int mie : 1; // 3 // Implemented - unsigned int upie : 1; // 4 // Implemented if USER mode enabled - unsigned int spie : 1; // 5 - unsigned int wpri0 : 1; // 6 - unsigned int mpie : 1; // 7 // Implemented - unsigned int spp : 1; // 8 - unsigned int wpri1 : 2; // 10: 9 - unsigned int mpp : 2; // 12:11 // Implemented - unsigned int fs : 2; // 14:13 - unsigned int xs : 2; // 16:15 - unsigned int mprv : 1; // 17 - unsigned int sum : 1; // 18 - unsigned int mxr : 1; // 19 - unsigned int tvm : 1; // 20 - unsigned int tw : 1; // 21 - unsigned int tsr : 1; // 22 - unsigned int wpri3 : 8; // 30:23 - unsigned int sd : 1; // 31 - } fields; - unsigned int bits; -} mstatus_t; - -extern void _trigger_test(int d); -extern void _trigger_test_ebreak(int d); -extern void _trigger_test_combo(); -extern void _single_step(int d); -// Tag is simply to help debug and determine where the failure came from -void check_debug_status(int tag, int value) -{ - if(glb_debug_status != value){ - printf("ERROR: check_debug_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_debug_status, value); - TEST_FAILED; - } -} -void check_debug_exception_status(int tag, int value) -{ - if(glb_debug_exception_status != value){ - printf("ERROR: check_debug_exception_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_debug_exception_status, value); - TEST_FAILED; - } -} -void check_hart_status(int tag, int value) -{ - if(glb_hart_status != value){ - printf("ERROR: check_hart_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_hart_status, value); - TEST_FAILED; - } -} -void check_ebreak_status(int tag, int value) -{ - if(glb_ebreak_status != value){ - printf("ERROR: check_ebreak_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_ebreak_status, value); - TEST_FAILED; - } -} -void check_illegal_insn_status(int tag, int value) -{ - if(glb_illegal_insn_status != value){ - printf("ERROR: check_illegal_insn_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", - tag, value, tag, glb_illegal_insn_status, value); - TEST_FAILED; - } -} -void delay(int count) { - for (volatile int d = 0; d < count; d++); -} - -void mstatus_mie_enable() { - int mie_bit = 0x1 << 3; - asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mstatus_mie_disable() { - int mie_bit = 0x1 << 3; - asm volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mie_enable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_disable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_enable(uint32_t irq) { - // Enable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); -} - -void mie_disable(uint32_t irq) { - // Disable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); -} - -void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { - *TIMER_REG_ADDR = mask; - *TIMER_VAL_ADDR = 1 + cycle_delay; -} - -void counters_enable() { - // Enable counters mcycle (bit0) and minstret (bit2) - uint32_t mask = 1<<2 | 1<<0; - asm volatile("csrrc x0, 0x320, %0" : : "r" (mask)); -} -#define MACHINE 3 -int main(int argc, char *argv[]) -{ - debug_req_control_t debug_req_control; - counters_enable(); - - // Enable interrupt - mstatus_mie_enable(); - mie_enable(30); - - // Assembly code from here to get better control of timing - _trigger_test_combo(); - - printf("------------------------\n"); - printf("Finished \n"); - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/debug_test_trigger/debugger.S b/cv32e40x/tests/programs/custom/debug_test_trigger/debugger.S deleted file mode 100644 index fd1a85b09c..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_trigger/debugger.S +++ /dev/null @@ -1,380 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger code -******************************************************************************* -*/ - -#include "corev_uvmt.h" - -.section .debugger, "ax" -.global _debugger_start -.global glb_debug_status -.global glb_hart_status -.global glb_expect_debug_entry -.global glb_mcycle_start -.global glb_mcycle_end -.global glb_minstret_start -.global glb_minstret_end -.global _trigger_code -.global _trigger_code_ebreak -.global _trigger_code_cebreak -.global _trigger_code_illegal_insn -.global _trigger_code_branch_insn -.global _trigger_code_multicycle_insn -.global __debugger_stack_start -.global _debugger_fail -.global _debugger_end -.set test_fail, 0x1 - -_debugger_start: - // Debugger Stack - csrw dscratch, a0 // dscratch0 - la a0, __debugger_stack_start - //sw t0, 0(a0) - csrw 0x7b3, t0 // dscratch1 - sw t1, 4(a0) - sw t2, 8(a0) - sw a1, 12(a0) - sw a2, 16(a0) - // Check if expecting debug entry - la a1, glb_expect_debug_entry - lw t1, 0(a1) - beq x0,t1,_debugger_fail - - // Read lower 32 bits of mcycle and minstret - // and store in globals for check at exit - csrr t1, mcycle - csrr t2, minstret - la a1, glb_mcycle_start - sw t1, 0(a1) - la a1, glb_minstret_start - sw t2, 0(a1) - - // Determine Test to execute in debugger code based on glb_hart_status - la a2, glb_hart_status - lw t2, 0(a2) - - - // For all other tests, - // Set debug status = hart status - la a1, glb_debug_status - sw t2, 0(a1) - - - li t0,7 - beq t2,t0,_debugger_trigger_setup // Test 7 - - li t0,10 - beq t2,t0, _debugger_trigger_match_no_dpc // Test 10 - - li t0,8 - beq t2,t0,_debugger_trigger_match // Test 8 - - li t0, 81 - beq t2,t0, _debugger_trigger_match_ebreak - - li t0, 82 - beq t2, t0, _debugger_trigger_match_cebreak - - li t0, 83 - beq t2, t0, _debugger_trigger_match_illegal_insn - - li t0, 84 - beq t2, t0, _debugger_trigger_match_branch_insn - - li t0, 85 - beq t2, t0, _debugger_trigger_match_multicycle_insn - - li t0,9 - beq t2,t0, _debugger_trigger_disable // Test 9 - - li t0,13 - beq t2,t0, _debugger_mret_call // Test 13 - - li t0,15 - beq t2,t0, _debugger_trigger_in_debug // Test 15 - - -_debugger_mret_call: - mret // will invoke debugger exception routine - -_debugger_trigger_setup: - // setup address to trigger on - la a1,_trigger_code - csrw tdata2,a1 - li t1, 1<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrw dcsr, t1 - j _debugger_end - -_debugger_trigger_match_no_dpc: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - // Clear the tdata1 execute field (tdata1[2]) to avoid re-entering the trigger when dret executes - csrci tdata1, 0x4 - - j _debugger_end - -_debugger_trigger_match: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code - csrr a2,dpc - bne a1,a2,_debugger_fail - la a1,_trigger_exit - csrw dpc,a1 - - // Setup match addr for next match: ebreak - la a1, _trigger_code_ebreak - csrw tdata2, a1 - j _debugger_end -_debugger_trigger_match_ebreak: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_ebreak - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past ebreak insn - addi a2, a2, 4 - csrw dpc, a2 - - # Setup match addr for next match: c.ebreak - la a1, _trigger_code_cebreak - csrw tdata2, a1 - - j _debugger_end -_debugger_trigger_match_cebreak: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 2 Trigger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_cebreak - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past c.ebreak insn - addi a2, a2, 2 - csrw dpc, a2 - - # Setup match addr for next match: illegal_insn - la a1, _trigger_code_illegal_insn - csrw tdata2, a1 - - // Disable trigger - //csrw tdata1, x0 - j _debugger_end - -_debugger_trigger_match_illegal_insn: - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_illegal_insn - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past illegal insn (dret, 4 bytes) - addi a2, a2, 4 - csrw dpc, a2 - - # Setup match addr for next match: branch_insn - la a1, _trigger_code_branch_insn - csrw tdata2, a1 - - j _debugger_end - -_debugger_trigger_match_branch_insn: - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_branch_insn - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past illegal branch (beq, 4 bytes) - addi a2, a2, 4 - csrw dpc, a2 - - # Setup match addr for next match: multicycle_insn - la a1, _trigger_code_multicycle_insn - csrw tdata2, a1 - - j _debugger_end - -_debugger_trigger_match_multicycle_insn: - li t1, 4<<28 | 2<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - la a1,_trigger_code_multicycle_insn - csrr a2,dpc - bne a1,a2,_debugger_fail - - # Advance pc past multicycle insn (mulhsu, 4 bytes) - addi a2, a2, 4 - csrw dpc, a2 - - # disable trigger - csrw tdata1, x0 - - j _debugger_end - -_debugger_trigger_disable: - // Expect DCSR - // 31:28 XDEBUGER Version = 4 - // 8:6 Cause = 3 debugger - // 1:0 Privelege = 3 Machine - // TBD FIXME BUG documentation update needed - li t1, 4<<28 | 3<<6 | 3<<0 | 1<<15 - csrr t2,dcsr - bne t1,t2,_debugger_fail - - csrw tdata1,x0 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - j _debugger_end - - -_debugger_trigger_in_debug: - // setup address to trigger on - la a1, _debugger_trig_point - csrw tdata2,a1 - li t1, 1<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - // Clear glb_expect_debug_entry - // If we trig, we'll reenter debug and - // test will fail due to 0 flag - la a1, glb_expect_debug_entry - li t1, 0 - sw t1, 0(a1) -_debugger_trig_point: - // Should _not_trig here - nop - // Clear trigger - li t1, 0<<2 - csrw tdata1, t1 - j _debugger_end - -_debugger_trigger_disabled_in_debug: - // setup address to trigger on - la a1, _debugger_trig_point_dis - // Set trig enable to 0 - csrw tdata2,a1 - li t1, 0<<2 - csrw tdata1,t1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 0 <<2 - csrr t2,tdata1 - bne t1,t2,_debugger_fail - - // Clear glb_expect_debug_entry - // If we trig, we'll reenter debug and - // test will fail due to 0 flag - la a1, glb_expect_debug_entry - li t1, 0 - sw t1, 0(a1) -_debugger_trig_point_dis: - // Should _not_trig here - nop - // Clear trigger - li t1, 0<<2 - csrw tdata1, t1 - j _debugger_end - -_debugger_end: - // Check counter values. They should have increased while in debug - // regardless of stopcount bit in csr - csrr t1, mcycle - la a1, glb_mcycle_start - lw t2, 0(a1) - sub t1, t1, t2 - beq t1, x0, _debugger_fail - - csrr t1, minstret - la a1, glb_minstret_start - lw t2, 0(a1) - sub t1, t1, t2 - beq t1, x0, _debugger_fail - - // If single stepping, do not clear - la a1, glb_hart_status - lw t0, 0(a1) - li t1, 18 - beq t0, t1, _debugger_end_continue - - // Clear debug entry expectation flag - la a1, glb_expect_debug_entry - sw x0, 0(a1) -_debugger_end_continue: - // Debugger Un-Stack - //lw t0, 0(a0) - la a0, __debugger_stack_start - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - dret -_debugger_fail: //Test Failed - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - nop - nop - nop - nop - diff --git a/cv32e40x/tests/programs/custom/debug_test_trigger/debugger_exception.S b/cv32e40x/tests/programs/custom/debug_test_trigger/debugger_exception.S deleted file mode 100644 index d3d1e9dd4c..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_trigger/debugger_exception.S +++ /dev/null @@ -1,77 +0,0 @@ - -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** Debugger Exception code -******************************************************************************* -*/ - -#include "corev_uvmt.h" - -.section .debugger_exception, "ax" -.global _debugger_exception_start -.global glb_debug_status -.global glb_hart_status -.global glb_debug_exception_status -.global glb_expect_debug_exception -//.global _debugger_fail -//.global _debugger_end -.set test_fail, 0x1 - -_debugger_exception_start: - // First check to see if exception was expected - la a1, glb_expect_debug_exception - lw t1, 0(a1) - //beq x0,t1,_debugger_fail - beq x0,t1,_debugger_exception_fail - - // Set exception status to hart status - la a1, glb_hart_status - lw t1, 0(a1) - la a2, glb_debug_exception_status - sw t1, 0(a2) - - //j _debugger_end - j _debugger_exception_end - -// Should be exact same function as implmented in debugger.S - // I can't seem to point to that symble from this file -_debugger_exception_end: - // Clear debug entry expectation flag - la a1, glb_expect_debug_entry - sw x0, 0(a1) - la a1, glb_expect_debug_exception - sw x0, 0(a1) - // Debugger Un-Stack - //lw t0, 0(a0) - csrr t0, 0x7b3 - lw t1, 4(a0) - lw t2, 8(a0) - lw a1, 12(a0) - lw a2, 16(a0) - csrr a0, dscratch - dret -// Should be exact same function as implmented in debugger.S -_debugger_exception_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - nop - nop - nop - nop - diff --git a/cv32e40x/tests/programs/custom/debug_test_trigger/handlers.S b/cv32e40x/tests/programs/custom/debug_test_trigger/handlers.S deleted file mode 100644 index bebe00743a..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_trigger/handlers.S +++ /dev/null @@ -1,348 +0,0 @@ -/* -* Copyright 2019 ETH Zürich and University of Bologna -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include "corev_uvmt.h" - -/* Exception codes */ -#define EXCEPTION_ILLEGAL_INSN 2 -#define EXCEPTION_BREAKPOINT 3 -#define EXCEPTION_ECALL_M 11 - -.section .text.handlers -.global __no_irq_handler -.global u_sw_irq_handler -.global m_software_irq_handler -.global m_timer_irq_handler -.global m_external_irq_handler -.global m_fast0_irq_handler -.global m_fast1_irq_handler -.global m_fast2_irq_handler -.global m_fast3_irq_handler -.global m_fast4_irq_handler -.global m_fast5_irq_handler -.global m_fast6_irq_handler -.global m_fast7_irq_handler -.global m_fast8_irq_handler -.global m_fast9_irq_handler -.global m_fast10_irq_handler -.global m_fast11_irq_handler -.global m_fast12_irq_handler -.global m_fast13_irq_handler -.global m_fast14_irq_handler -.global m_fast15_irq_handler - -.weak m_software_irq_handler -.weak m_timer_irq_handler -.weak m_external_irq_handler -.weak m_fast0_irq_handler -.weak m_fast1_irq_handler -.weak m_fast2_irq_handler -.weak m_fast3_irq_handler -.weak m_fast4_irq_handler -.weak m_fast5_irq_handler -.weak m_fast6_irq_handler -.weak m_fast7_irq_handler -.weak m_fast8_irq_handler -.weak m_fast9_irq_handler -.weak m_fast10_irq_handler -.weak m_fast11_irq_handler -.weak m_fast12_irq_handler -.weak m_fast13_irq_handler -.weak m_fast14_irq_handler -.weak m_fast15_irq_handler - -.global glb_illegal_insn_status -.global glb_ebreak_status -.global glb_expect_illegal_insn -.global glb_expect_ebreak_handler -.global glb_exception_ebreak_status -.global glb_expect_irq_entry -.set test_fail, 0x1 - -/* exception handling */ -__no_irq_handler: - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - - la a0, no_exception_handler_msg - jal ra, puts - - // Check if we expected to enter irq - la a1, glb_expect_irq_entry - lw t0, 0(a1) - beq t0, x0, _irq_fail - - // Clear entry flag - li t0, 0 - sw t0, 0(a1) - //j __no_irq_handler - - // Return - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret - -_irq_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, test_fail - sw t0, 0(a0) - ret - -u_sw_irq_handler: - /* While we are still using puts in handlers, save all caller saved - regs. Eventually, some of these saves could be deferred. */ - addi sp,sp,-64 - sw ra, 0(sp) - sw a0, 4(sp) - sw a1, 8(sp) - sw a2, 12(sp) - sw a3, 16(sp) - sw a4, 20(sp) - sw a5, 24(sp) - sw a6, 28(sp) - sw a7, 32(sp) - sw t0, 36(sp) - sw t1, 40(sp) - sw t2, 44(sp) - sw t3, 48(sp) - sw t4, 52(sp) - sw t5, 56(sp) - sw t6, 60(sp) - csrr t0, mcause - li t1, EXCEPTION_ILLEGAL_INSN - beq t0, t1, handle_illegal_insn - li t1, EXCEPTION_ECALL_M - beq t0, t1, handle_ecall - li t1, EXCEPTION_BREAKPOINT - beq t0, t1, handle_ebreak - j handle_unknown - -handle_ecall: - la a0, ecall_msg - jal ra, handle_syscall - j end_handler_incr_mepc - -m_software_irq_handler: - j __no_irq_handler - -m_timer_irq_handler: - j __no_irq_handler - -m_external_irq_handler: - j __no_irq_handler - -m_fast0_irq_handler: - j __no_irq_handler - -m_fast1_irq_handler: - j __no_irq_handler - -m_fast2_irq_handler: - j __no_irq_handler - -m_fast3_irq_handler: - j __no_irq_handler - -m_fast4_irq_handler: - j __no_irq_handler - -m_fast5_irq_handler: - j __no_irq_handler - -m_fast6_irq_handler: - j __no_irq_handler - -m_fast7_irq_handler: - j __no_irq_handler - -m_fast8_irq_handler: - j __no_irq_handler - -m_fast9_irq_handler: - j __no_irq_handler - -m_fast10_irq_handler: - j __no_irq_handler - -m_fast11_irq_handler: - j __no_irq_handler - -m_fast12_irq_handler: - j __no_irq_handler - -m_fast13_irq_handler: - j __no_irq_handler - -m_fast14_irq_handler: - j __no_irq_handler - -m_fast15_irq_handler: - j __no_irq_handler - - -handle_ebreak: - /* TODO support debug handling requirements. */ - la a0, ebreak_msg - jal ra, puts - // Check if expecting ebreak handler - la a0, glb_expect_ebreak_handler - lw t0, 0(a0) - bne t0, x0, cont_handle_ebreak - // Not expecting ebreak, assert test failed - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) - j end_handler_incr_mepc -cont_handle_ebreak: - //increment hart status - sw x0, 0(a0) - la a0, glb_ebreak_status - lw t0, 0(a0) - addi t0,t0,1 - sw t0, 0(a0) - j end_handler_incr_mepc - - - -handle_illegal_insn: - la a0, illegal_insn_msg - jal ra, puts - // Check if expecting illegal instruction - la a0, glb_expect_illegal_insn - lw t0, 0(a0) - bne t0, x0, cont_illegal_insn - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) //Test Failed - j end_handler_incr_mepc -cont_illegal_insn: - //increment hart status - sw x0, 0(a0) - la a0, glb_illegal_insn_status - lw t0, 0(a0) - addi t0,t0,1 - sw t0, 0(a0) - - // Check if we are expected to execute ebreak - la a0, glb_exception_ebreak_status - lw t0, 0(a0) - // End handler if no ebreak is to be executed - beq t0, x0, end_handler_incr_mepc - - // Clear ebreak flag - sw x0, 0(a0) - // Execute ebreak - .4byte 0x00100073 - // Exit handler - j end_handler_incr_mepc - - j end_handler_incr_mepc - - - - - - - -handle_unknown: - la a0, unknown_msg - jal ra, puts - /* We don't know what interrupt/exception is being handled, so don't - increment mepc. */ - j end_handler_ret - - - - - - -end_handler_incr_mepc: - csrr t0, mepc - lb t1, 0(t0) - li a0, 0x3 - and t1, t1, a0 - /* Increment mepc by 2 or 4 depending on whether the instruction at mepc - is compressed or not. */ - bne t1, a0, end_handler_incr_mepc2 - addi t0, t0, 2 -end_handler_incr_mepc2: - addi t0, t0, 2 - csrw mepc, t0 -end_handler_ret: - lw ra, 0(sp) - lw a0, 4(sp) - lw a1, 8(sp) - lw a2, 12(sp) - lw a3, 16(sp) - lw a4, 20(sp) - lw a5, 24(sp) - lw a6, 28(sp) - lw a7, 32(sp) - lw t0, 36(sp) - lw t1, 40(sp) - lw t2, 44(sp) - lw t3, 48(sp) - lw t4, 52(sp) - lw t5, 56(sp) - lw t6, 60(sp) - addi sp,sp,64 - mret -/* this interrupt can be generated for verification purposes, random or when the - PC is equal to a given value*/ -verification_irq_handler: - mret - -.section .rodata -illegal_insn_msg: - .string "illegal instruction exception handler entered\n" -ecall_msg: - .string "ecall exception handler entered\n" -ebreak_msg: - .string "ebreak exception handler entered\n" -unknown_msg: - .string "unknown exception handler entered\n" -no_exception_handler_msg: - .string "no exception handler installed\n" diff --git a/cv32e40x/tests/programs/custom/debug_test_trigger/test.yaml b/cv32e40x/tests/programs/custom/debug_test_trigger/test.yaml deleted file mode 100644 index 332d7f4107..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_trigger/test.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# Test definition YAML for test - -# Debug trigger directed test -name: debug_test_trigger -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Debug trigger directed test -# Directed test timing is exact, requires no OBI stalls -plusargs: > - +rand_stall_obi_disable diff --git a/cv32e40x/tests/programs/custom/debug_test_trigger/trigger_code.S b/cv32e40x/tests/programs/custom/debug_test_trigger/trigger_code.S deleted file mode 100644 index c35ffd29c8..0000000000 --- a/cv32e40x/tests/programs/custom/debug_test_trigger/trigger_code.S +++ /dev/null @@ -1,567 +0,0 @@ -#Copyright 202[x] Silicon Labs, Inc. -# -#This file, and derivatives thereof are licensed under the -#Solderpad License, Version 2.0 (the "License"); -#Use of this file means you agree to the terms and conditions -#of the license and are in full compliance with the License. -#You may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.0/ -# -#Unless required by applicable law or agreed to in writing, software -#and hardware implementations thereof -#distributed under the License is distributed on an "AS IS" BASIS, -#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. -#See the License for the specific language governing permissions and -#limitations under the License. - -#include "corev_uvmt.h" - -.section .trigger_code_sect, "ax" -.set test_ret_val, CV_VP_STATUS_FLAGS_BASE -.set test_fail, 0x1 -.set timer_reg_addr, CV_VP_INTR_TIMER_BASE -.set timer_val_addr, CV_VP_INTR_TIMER_BASE+4 -.set debug_req_reg, CV_VP_DEBUG_CONTROL_BASE -.global _trigger_exit -.global _trigger_test -.global _trigger_code -.global _trigger_test_ebreak -.global _trigger_code_ebreak -.global _trigger_code_illegal_insn -.global _trigger_code_branch_insn -.global _trigger_code_multicycle_insn -.global _trigger_code_cebreak -.global _trigger_test_combo -.global glb_hart_status -.global glb_expect_debug_entry -.global glb_expect_irq_entry -.global glb_expect_illegal_insn -.global glb_debug_status -.type _trigger_code, @function -.type _trigger_code_ebreak, @function -.type _trigger_code_cebreak, @function -.type _trigger_code_illegal_insn, @function -.type _trigger_code_branch_insn, @function -.type _trigger_code_multicycle_insn, @function -#.type _trigger_test_combo, @function - -_trigger_code_ebreak: - .4byte 0x00100073 - ret - -_trigger_code_cebreak: - c.ebreak - ret - -_trigger_code_illegal_insn: - dret - ret - -_trigger_code_branch_insn: - beq t0, t1, __trigger_fail - ret - -_trigger_code_multicycle_insn: - mulhsu t0, t0, t1 - ret - -_trigger_test_ebreak: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - # a0 holds argument - # 0 - ebreak - # 1 - c.c.ebreak - # 2 - illegal instruction - # 3 - branch instruction - # 4 - multicycle instruction (mulhsu) - - mv t1, a0 - li t0, 0 - beq t0, t1, _jmp_ebreak - - li t0, 1 - beq t0, t1, _jmp_cebreak - - li t0, 2 - beq t0, t1, _jmp_illegal_insn - - li t0, 3 - beq t0, t1, _jmp_branch_insn - - li t0, 4 - beq t0, t1, _jmp_multicycle_insn - -_jmp_ebreak: - jal ra, _trigger_code_ebreak - j __trigger_done -_jmp_cebreak: - jal ra, _trigger_code_cebreak - j __trigger_done -_jmp_illegal_insn: - jal ra, _trigger_code_illegal_insn - j __trigger_done -_jmp_branch_insn: - jal ra, _trigger_code_branch_insn - j __trigger_done -_jmp_multicycle_insn: - jal ra, _trigger_code_multicycle_insn - j __trigger_done - -# Enter debug mode to set tdata1 and tdata2 for triggering on execution of instruction at _trigger_code -_trigger_setup: - addi sp,sp,-8 - sw ra, 4(sp) - - # Don't expect trigger match - li a0, 0 - jal ra, _trigger_test - - # Setup trigger - la a1, glb_hart_status - li t0, 7 - sw t0, 0(a1) - - # expect debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # Assert debug_req - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0xc8) - sw t0, 0(a1) -_wait1: - la a1, glb_hart_status - lw t0, 0(a1) - la a1, glb_debug_status - lw t1, 0(a1) - bne t0, t1, _wait1 - - // Check csrs - csrr t0, 0x7A1 - li t1, 2<<28 | 1<<27 | 1<<12 | 1<<6 | 1<<2 - bne t0, t1, __trigger_fail - - csrr t0, 0x7A2 - la t1, _trigger_code - bne t0, t1, __trigger_fail - - lw ra, 4(sp) - addi sp,sp,8 - - ret - -# Assembly code for generating -# cycle accurate debug_req -# and irq -_trigger_test_combo: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - jal ra, _trigger_setup - - # ---------------------------------------------------- - # Test 10: Expect trigger and return to the same instruction - # Debugger will clear tdata[2] to avoid re-triggering upon return - # ---------------------------------------------------- - la a1, glb_hart_status - li t0, 10 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # execute trigger code - li a0, 0 - jal ra, _trigger_test - - # Re-set the triger to re-enable - jal ra, _trigger_setup - - # ---------------------------------------------------- - # Test 8: Expect trigger with dpc changed in debugger handler to avoid - # ---------------------------------------------------- - la a1, glb_hart_status - li t0, 8 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # execute trigger code - li a0, 1 - jal ra, _trigger_test - -_wait2: - la a1, glb_hart_status - lw t0, 0(a1) - la a1, glb_debug_status - lw t1, 0(a1) - bne t0, t1, _wait2 - - # Setup trigger again - la a1, glb_hart_status - li t0, 7 - sw t0, 0(a1) - - # expect debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # Assert debug_req - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x8) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0xc8) - sw t0, 0(a1) -_wait3: - la a1, glb_hart_status - lw t0, 0(a1) - la a1, glb_debug_status - lw t1, 0(a1) - bne t0, t1, _wait3 - - # ---------------------------------------------------- - # debug_req and trigger on same cycle - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 8 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x5) - sw t0, 0(a1) - - # Call trigger function - li a0, 1 - jal ra, _trigger_code - - # ---------------------------------------------------- - # debug_req and irq when trigger on ebreak - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 81 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # ---------------------------------------------------- - # Enable debug_req in VP - # ---------------------------------------------------- - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1c) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 18 - sw t0, 0(a1) - - # Call trigger function - li a0, 0 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on c.ebreak - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 82 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1c) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 19 - sw t0, 0(a1) - - # Call trigger function - li a0, 1 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on illegal insn - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 83 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x20) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 23 - sw t0, 0(a1) - - # Call trigger function - li a0, 2 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on branch insn - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 84 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x20) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 23 - sw t0, 0(a1) - - # Call trigger function - li a0, 3 - jal ra, _trigger_test_ebreak - - # ---------------------------------------------------- - # debug_req and irq when trigger on multicycle insn - # ---------------------------------------------------- - # Set hart status - la a1, glb_hart_status - li t0, 85 - sw t0, 0(a1) - - # set expected debug - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - # set expected irq - la a1, glb_expect_irq_entry - li t0, 1 - sw t0, 0(a1) - - # Enable debug_req in VP - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x24) - sw t0, 0(a1) - - # Enable interrupt - li a1, timer_reg_addr - li t0, 0x40000000 - sw t0, 0(a1) - li a1, timer_val_addr - li t0, 27 - sw t0, 0(a1) - - # Call trigger function - li a0, 4 - jal ra, _trigger_test_ebreak - - # Trigger disabled - la a1, glb_hart_status - li t0, 9 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1) - sw t0, 0(a1) - nop - nop - nop - - li a0, 0 - jal ra, _trigger_test - - la a1, glb_debug_status - lw t0, 0(a1) - li t1, 9 - bne t0, t1, __trigger_fail - - # ---------------------------------------------------- - # trigger match in debug mode - # ---------------------------------------------------- - la a1, glb_hart_status - li t0, 15 - sw t0, 0(a1) - - la a1, glb_expect_debug_entry - li t0, 1 - sw t0, 0(a1) - - li a1, debug_req_reg - li t0, CV_VP_DEBUG_CONTROL_DBG_REQ(0x1) | \ - CV_VP_DEBUG_CONTROL_REQ_MODE(0x1) | \ - CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x5) | \ - CV_VP_DEBUG_CONTROL_START_DELAY(0x1) - sw t0, 0(a1) - nop - nop - - la a1, glb_debug_status - lw t0, 0(a1) - li t1, 15 - bne t0, t1, __trigger_fail - - j __trigger_done - - - // We will trigger on the _trigger_code addess - // We should not expect the first instruction to execute - // The debugger code will move the PC to the trigger_exit_code - // We will trigger on the _trigger_code addess -_trigger_code: - add a2,a0,a1 - ret -_trigger_exit: - ret -_trigger_test: - addi sp,sp,-30 - sw t0, 0(sp) - sw t1, 4(sp) - sw a0, 8(sp) - sw a1, 12(sp) - sw a2, 16(sp) - sw ra, 20(sp) - - // a0 holds input to function (expect trigger) - mv t1, a0 - - // Load up some random data to add - li a0, 7893 - li a1, 1452 - li a2, 191 // a2 value will be overwrriten by _trigger_code - mv t2, a2 // keep a copy of the value to compare against - - // Call function that will have a trigger match - // If no trigger match, then a2=a0+a1 - // Else if trigger matched, then a2 is not modified - jal ra, _trigger_code - - // if (expect trigger) check against original value (in t2) - bne t1 ,x0, __trigger_check - // else - // trigger match not expected, function executes as normal - // set execpted value to t2 = a0 + a1 - add t2, a0, a1 -__trigger_check: - beq t2,a2,__trigger_done -__trigger_fail: - li a0, CV_VP_STATUS_FLAGS_BASE - li t0, 1 - sw t0, 0(a0) -__trigger_done: - lw t0, 0(sp) - lw t1, 4(sp) - lw a0, 8(sp) - lw a1, 12(sp) - lw a2, 16(sp) - lw ra, 20(sp) - addi sp,sp,30 - ret diff --git a/cv32e40x/tests/programs/custom/dhrystone/dhrystone.c b/cv32e40x/tests/programs/custom/dhrystone/dhrystone.c deleted file mode 100644 index a74cfaa0aa..0000000000 --- a/cv32e40x/tests/programs/custom/dhrystone/dhrystone.c +++ /dev/null @@ -1,1140 +0,0 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_1.c (part 2 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - **************************************************************************** - */ -#include "stdio.h" -#include -#include "corev_uvmt.h" - -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry.h (part 1 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * Siemens AG, AUT E 51 - * Postfach 3220 - * 8520 Erlangen - * Germany (West) - * Phone: [+49]-9131-7-20330 - * (8-17 Central European Time) - * Usenet: ..!mcsun!unido!estevax!weicker - * - * Original Version (in Ada) published in - * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), - * pp. 1013 - 1030, together with the statistics - * on which the distribution of statements etc. is based. - * - * In this C version, the following C library functions are used: - * - strcpy, strcmp (inside the measurement loop) - * - printf, scanf (outside the measurement loop) - * In addition, Berkeley UNIX system calls "times ()" or "time ()" - * are used for execution time measurement. For measurements - * on other systems, these calls have to be changed. - * - * Updated January, 1997 Rick Cramer, Galileo(R) to work with - * the i960jx and Galileo-5 Reference Design. - * - * - * Collection of Results: - * Reinhold Weicker (address see above) and - * - * Rick Richardson - * PC Research. Inc. - * 94 Apple Orchard Drive - * Tinton Falls, NJ 07724 - * Phone: (201) 389-8963 (9-17 EST) - * Usenet: ...!uunet!pcrat!rick - * - * Please send results to Rick Richardson and/or Reinhold Weicker. - * Complete information should be given on hardware and software used. - * Hardware information includes: Machine type, CPU, type and size - * of caches; for microprocessors: clock frequency, memory speed - * (number of wait states). - * Software information includes: Compiler (and runtime library) - * manufacturer and version, compilation switches, OS version. - * The Operating System version may give an indication about the - * compiler; Dhrystone itself performs no OS calls in the measurement loop. - * - * The complete output generated by the program should be mailed - * such that at least some checks for correctness can be made. - * - *************************************************************************** - * - * History: This version C/2.1 has been made for two reasons: - * - * 1) There is an obvious need for a common C version of - * Dhrystone, since C is at present the most popular system - * programming language for the class of processors - * (microcomputers, minicomputers) where Dhrystone is used most. - * There should be, as far as possible, only one C version of - * Dhrystone such that results can be compared without - * restrictions. In the past, the C versions distributed - * by Rick Richardson (Version 1.1) and by Reinhold Weicker - * had small (though not significant) differences. - * - * 2) As far as it is possible without changes to the Dhrystone - * statistics, optimizing compilers should be prevented from - * removing significant statements. - * - * This C version has been developed in cooperation with - * Rick Richardson (Tinton Falls, NJ), it incorporates many - * ideas from the "Version 1.1" distributed previously by - * him over the UNIX network Usenet. - * I also thank Chaim Benedelac (National Semiconductor), - * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), - * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) - * for their help with comments on earlier versions of the - * benchmark. - * - * Changes: In the initialization part, this version follows mostly - * Rick Richardson's version distributed via Usenet, not the - * version distributed earlier via floppy disk by Reinhold Weicker. - * As a concession to older compilers, names have been made - * unique within the first 8 characters. - * Inside the measurement loop, this version follows the - * version previously distributed by Reinhold Weicker. - * - * At several places in the benchmark, code has been added, - * but within the measurement loop only in branches that - * are not executed. The intention is that optimizing compilers - * should be prevented from moving code out of the measurement - * loop, or from removing code altogether. Since the statements - * that are executed within the measurement loop have NOT been - * changed, the numbers defining the "Dhrystone distribution" - * (distribution of statements, operand types and locality) - * still hold. Except for sophisticated optimizing compilers, - * execution times for this version should be the same as - * for previous versions. - * - * Since it has proven difficult to subtract the time for the - * measurement loop overhead in a correct way, the loop check - * has been made a part of the benchmark. This does have - * an impact - though a very minor one - on the distribution - * statistics which have been updated for this version. - * - * All changes within the measurement loop are described - * and discussed in the companion paper "Rationale for - * Dhrystone version 2". - * - * Because of the self-imposed limitation that the order and - * distribution of the executed statements should not be - * changed, there are still cases where optimizing compilers - * may not generate code for some statements. To a certain - * degree, this is unavoidable for small synthetic benchmarks. - * Users of the benchmark are advised to check code listings - * whether code is generated for all statements of Dhrystone. - * - * Version 2.1 is identical to version 2.0 distributed via - * the UNIX network Usenet in March 1988 except that it corrects - * some minor deficiencies that were found by users of version 2.0. - * The only change within the measurement loop is that a - * non-executed "else" part was added to the "if" statement in - * Func_3, and a non-executed "else" part removed from Proc_3. - * - *************************************************************************** - * - * Defines: The following "Defines" are possible: - * -DREG=register (default: Not defined) - * As an approximation to what an average C programmer - * might do, the "register" storage class is applied - * (if enabled by -DREG=register) - * - for local variables, if they are used (dynamically) - * five or more times - * - for parameters if they are used (dynamically) - * six or more times - * Note that an optimal "register" strategy is - * compiler-dependent, and that "register" declarations - * do not necessarily lead to faster execution. - * -DNOSTRUCTASSIGN (default: Not defined) - * Define if the C compiler does not support - * assignment of structures. - * -DNOENUMS (default: Not defined) - * Define if the C compiler does not support - * enumeration types. - * -DICACHEON (default: Not defined) - * Adjust performace by conditionally compiling - * these i960jx CACHE paramaters. - * -DICACHEOFF - * -DDCACHEON (default: Not defined) - * -DDCACHEOFF - * - * NOTE: Galileo-5 Board Frequency is set to 33Mhz in the - * file jx-timer.c. If the operating frequency is - * changed by replacing the crystal, then this #define - * must also be changed. - * - *************************************************************************** - * - * Compilation model and measurement (IMPORTANT): - * - * This C version of Dhrystone consists of four files: - * - dhry.h (this file, containing global definitions and comments) - * - dhry_1.c (containing the code corresponding to Ada package Pack_1) - * - dhry_2.c (containing the code corresponding to Ada package Pack_2) - * - jx-timer.c (containing the code to access the i960jx timer) - * - * The following "ground rules" apply for measurements: - * - No procedure merging - * - Otherwise, compiler optimizations are allowed but should be indicated - * - Default results are those without register declarations - * See the companion paper "Rationale for Dhrystone Version 2" for a more - * detailed discussion of these ground rules. - * - * For 16-Bit processors (e.g. 80186, 80286), times for all compilation - * models ("small", "medium", "large" etc.) should be given if possible, - * together with a definition of these models for the compiler system used. - * - * Example Intel 960jx compile syntax for Galileo-5. - * - * ic960 -AJA -Tgal5 -O2 -DREG=register dhry_1.c dhry_2.c jx-timer.c - * - ************************************************************************** - * - * Dhrystone (C version) statistics: - * - * [Comment from the first distribution, updated for version 2. - * Note that because of language differences, the numbers are slightly - * different from the Ada version.] - * - * The following program contains statements of a high level programming - * language (here: C) in a distribution considered representative: - * - * assignments 52 (51.0 %) - * control statements 33 (32.4 %) - * procedure, function calls 17 (16.7 %) - * - * 103 statements are dynamically executed. The program is balanced with - * respect to the three aspects: - * - * - statement type - * - operand type - * - operand locality - * operand global, local, parameter, or constant. - * - * The combination of these three aspects is balanced only approximately. - * - * 1. Statement Type: - * ----------------- number - * - * V1 = V2 9 - * (incl. V1 = F(..) - * V = Constant 12 - * Assignment, 7 - * with array element - * Assignment, 6 - * with record component - * -- - * 34 34 - * - * X = Y +|-|"&&"|"|" Z 5 - * X = Y +|-|"==" Constant 6 - * X = X +|- 1 3 - * X = Y *|/ Z 2 - * X = Expression, 1 - * two operators - * X = Expression, 1 - * three operators - * -- - * 18 18 - * - * if .... 14 - * with "else" 7 - * without "else" 7 - * executed 3 - * not executed 4 - * for ... 7 | counted every time - * while ... 4 | the loop condition - * do ... while 1 | is evaluated - * switch ... 1 - * break 1 - * declaration with 1 - * initialization - * -- - * 34 34 - * - * P (...) procedure call 11 - * user procedure 10 - * library procedure 1 - * X = F (...) - * function call 6 - * user function 5 - * library function 1 - * -- - * 17 17 - * --- - * 103 - * - * The average number of parameters in procedure or function calls - * is 1.82 (not counting the function values as implicit parameters). - * - * - * 2. Operators - * ------------ - * number approximate - * percentage - * - * Arithmetic 32 50.8 - * - * + 21 33.3 - * - 7 11.1 - * * 3 4.8 - * / (int div) 1 1.6 - * - * Comparison 27 42.8 - * - * == 9 14.3 - * /= 4 6.3 - * > 1 1.6 - * < 3 4.8 - * >= 1 1.6 - * <= 9 14.3 - * - * Logic 4 6.3 - * - * && (AND-THEN) 1 1.6 - * | (OR) 1 1.6 - * ! (NOT) 2 3.2 - * - * -- ----- - * 63 100.1 - * - * - * 3. Operand Type (counted once per operand reference): - * --------------- - * number approximate - * percentage - * - * Integer 175 72.3 % - * Character 45 18.6 % - * Pointer 12 5.0 % - * String30 6 2.5 % - * Array 2 0.8 % - * Record 2 0.8 % - * --- ------- - * 242 100.0 % - * - * When there is an access path leading to the final operand (e.g. a record - * component), only the final data type on the access path is counted. - * - * - * 4. Operand Locality: - * ------------------- - * number approximate - * percentage - * - * local variable 114 47.1 % - * global variable 22 9.1 % - * parameter 45 18.6 % - * value 23 9.5 % - * reference 22 9.1 % - * function result 6 2.5 % - * constant 55 22.7 % - * --- ------- - * 242 100.0 % - * - * - * The program does not compute anything meaningful, but it is syntactically - * and semantically correct. All variables have a value assigned to them - * before they are used as a source operand. - * - * There has been no explicit effort to account for the effects of a - * cache, or to balance the use of long or short displacements for code or - * data. - * - *************************************************************************** - */ - -/* Compiler and system dependent definitions: */ - -// mm_ram cycle counter address -#define TICKS_ADDR (*((volatile uint32_t*) (CV_VP_CYCLE_COUNTER_BASE + 0))) -#define TICKS_PRINT_ADDR (*((volatile uint32_t*)(CV_VP_CYCLE_COUNTER_BASE + 4))) - -#define Mic_secs_Per_Second 1000000.0 - /* Berkeley UNIX C returns process times in seconds/HZ */ - -#ifdef NOSTRUCTASSIGN -#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) -#else -#define structassign(d, s) d = s -#endif - -#ifdef NOENUM -#define Ident_1 0 -#define Ident_2 1 -#define Ident_3 2 -#define Ident_4 3 -#define Ident_5 4 - typedef int Enumeration; -#else - typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} - Enumeration; -#endif - /* for boolean and enumeration types in Ada, Pascal */ - -/* General definitions: */ - -/* #include - */ - /* for strcpy, strcmp */ - -#define Null 0 - /* Value of a Null pointer */ -#define true 1 -#define false 0 - -typedef int One_Thirty; -typedef int One_Fifty; -typedef char Capital_Letter; -typedef int Boolean; -typedef char Str_30 [31]; -typedef int Arr_1_Dim [50]; -typedef int Arr_2_Dim [50] [50]; - -typedef struct record - { - struct record *Ptr_Comp; - Enumeration Discr; - union { - struct { - Enumeration Enum_Comp; - int Int_Comp; - char Str_Comp [31]; - } var_1; - struct { - Enumeration E_Comp_2; - char Str_2_Comp [31]; - } var_2; - struct { - char Ch_1_Comp; - char Ch_2_Comp; - } var_3; - } variant; - } Rec_Type, *Rec_Pointer; - - - -#define NUM_RUNS (100) -#ifdef CONSTANT -#define NUM_RUNS (CONSTANT) -#else -#define NUM_RUNS (100) -#endif -#define DLX_FREQ 200 /* in MHz */ -#define PROC_6 0 - -void Ireport ( int c ) { - // report(c); -} - -#ifndef strcpy -char *strcpy (char *dst0, const char *src0) -{ - char *s = dst0; - - while ((*dst0++ = *src0++)); - - return s; -} -#endif - -#ifndef strcmp -int strcmp (const char *s1, const char *s2) -{ - while (*s1 && *s2 && *s1 == *s2) { - s1++; - s2++; - } - return (*(unsigned char *) s1) - (*(unsigned char *) s2); -} -#endif - -#define DETECTNULL(X) (((X) - 0x01010101) & ~(X) & 0x80808080) -#define UNALIGNED(X, Y) \ - (((long)X & (sizeof (long) - 1)) | ((long)Y & (sizeof (long) - 1))) - - -/* Global Variables: */ - -Rec_Pointer Ptr_Glob, - Next_Ptr_Glob; -int Int_Glob; -Boolean Bool_Glob; -char Ch_1_Glob, - Ch_2_Glob; -int Arr_1_Glob [50]; -int Arr_2_Glob [50] [50]; - - - /* forward declaration necessary since Enumeration may not simply be int */ - -#ifndef REG - Boolean Reg = false; -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#else - Boolean Reg = true; -#endif - -/* variables for time measurement: */ - -#if DLX || OR1K -#define Too_Small_Time DLX_FREQ -#else -#define Too_Small_Time 1 -#endif - -#define TIMER0 0 -#define TIMER1 1 - - - - - -unsigned int Begin_Time, - End_Time, - User_Time, - Microseconds, - Dhrystones_Per_Second; - -/* end of variables for time measurement */ - - -void Proc_1(REG Rec_Pointer Ptr_Val_Par); -void Proc_2(One_Fifty *Int_Par_Ref); -void Proc_3(Rec_Pointer *Ptr_Ref_Par); -void Proc_4(); -void Proc_5(); -void Proc_6( - Enumeration Enum_Val_Par, - Enumeration *Enum_Ref_Par); -void Proc_7( - One_Fifty Int_1_Par_Val, - One_Fifty Int_2_Par_Val, - One_Fifty *Int_Par_Ref); -void Proc_8( - Arr_1_Dim Arr_1_Par_Ref, - Arr_2_Dim Arr_2_Par_Ref, - int Int_1_Par_Val, - int Int_2_Par_Val); -Enumeration Func_1(Capital_Letter Ch_1_Par_Val, - Capital_Letter Ch_2_Par_Val); -Boolean Func_2(Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref); -Boolean Func_3(Enumeration Enum_Par_Val); - -int main (int argc, char *argv[]) -/*****/ - - /* main program, corresponds to procedures */ - /* Main and Proc_0 in the Ada version */ -{ - One_Fifty Int_1_Loc; - REG One_Fifty Int_2_Loc=0; - One_Fifty Int_3_Loc; - REG char Ch_Index; - Enumeration Enum_Loc; - Str_30 Str_1_Loc; - Str_30 Str_2_Loc; - REG int Run_Index; - REG int Number_Of_Runs; - Rec_Type x, y; - - /* Initializations */ - - Next_Ptr_Glob = (Rec_Pointer) &x; - Ptr_Glob = (Rec_Pointer) &y; - - Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; - Ptr_Glob->Discr = Ident_1; - Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; - Ptr_Glob->variant.var_1.Int_Comp = 40; - strcpy (Ptr_Glob->variant.var_1.Str_Comp, - "DHRYSTONE PROGRAM, SOME STRING"); - strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); - - Arr_2_Glob [8][7] = 10; - /* Was missing in published program. Without this statement, */ - /* Arr_2_Glob [8][7] would have an undefined value. */ - /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ - /* overflow may occur for this array element. */ - -/* Initalize Data and Instruction Cache */ - - - printf (" %c", '\n'); - printf ("Dhrystone Benchmark, Version 2.1 (Language: C)%c", '\n'); - printf (" %c", '\n'); - if (Reg) - { - printf ("Program compiled with 'register' attribute%c", '\n'); - printf (" %c", '\n'); - } - else - { - printf ("Program compiled without 'register' attribute%c", '\n'); - printf (" %c", '\n'); - } - - Number_Of_Runs = (argc >= 2) ? atoi(argv[1]) : NUM_RUNS; - - printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); - - // reset cycle counter - TICKS_ADDR = 0; - - for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) - { - - Ireport(1); - Ireport(Run_Index); - Proc_5(); - Ireport(2); - Proc_4(); - Ireport(3); - /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ - Int_1_Loc = 2; - Int_2_Loc = 3; - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); - Enum_Loc = Ident_2; - Ireport(0x31); - Ireport((unsigned long)Str_1_Loc); - Ireport((unsigned long)Str_2_Loc); - - Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); - /* Bool_Glob == 1 */ - Ireport(4); - while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ - { - Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; - /* Int_3_Loc == 7 */ - Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); - /* Int_3_Loc == 7 */ - Int_1_Loc += 1; - } /* while */ - Ireport(5); - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ -#if DBG - printf("a) Int_1_Loc: %x\n", Int_1_Loc); - printf("a) Int_2_Loc: %x\n", Int_2_Loc); - printf("a) Int_3_Loc: %x\n\n", Int_3_Loc); -#endif - Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); - /* Int_Glob == 5 */ -#if DBG - printf("b) Int_1_Loc: %x\n", Int_1_Loc); - printf("b) Int_2_Loc: %x\n", Int_2_Loc); - printf("b) Int_3_Loc: %x\n\n", Int_3_Loc); -#endif - Ireport(6); - - Proc_1 (Ptr_Glob); -#if DBG - printf("c) Int_1_Loc: %x\n", Int_1_Loc); - printf("c) Int_2_Loc: %x\n", Int_2_Loc); - printf("c) Int_3_Loc: %x\n\n", Int_3_Loc); -#endif - Ireport(7); - - for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) - /* loop body executed twice */ - { - if (Enum_Loc == Func_1 (Ch_Index, 'C')) - /* then, not executed */ - { - Proc_6 (Ident_1, &Enum_Loc); - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); - Int_2_Loc = Run_Index; - Int_Glob = Run_Index; -#if DBG - printf("d) Int_1_Loc: %x\n", Int_1_Loc); - printf("d) Int_2_Loc: %x\n", Int_2_Loc); - printf("d) Int_3_Loc: %x\n\n", Int_3_Loc); -#endif - } - } - Ireport(8); - - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ -#if DBG - printf("e) Int_1_Loc: %x\n", Int_1_Loc); - printf("e) Int_2_Loc: %x\n", Int_2_Loc); - printf("e) Int_3_Loc: %x\n", Int_3_Loc); - printf("e) Ch_1_Glob: %c\n\n", Ch_1_Glob); -#endif - Int_2_Loc = Int_2_Loc * Int_1_Loc; - Int_1_Loc = Int_2_Loc / Int_3_Loc; - Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; - /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ - Proc_2 (&Int_1_Loc); - Ireport(9); - - /* Int_1_Loc == 5 */ -#if DBG - printf("f) Int_1_Loc: %x\n", Int_1_Loc); - printf("f) Int_2_Loc: %x\n", Int_2_Loc); - printf("f) Int_3_Loc: %x\n\n", Int_3_Loc); -#endif - - } /* loop "for Run_Index" */ - - //print cycle counter - TICKS_PRINT_ADDR = 0; - - printf ("Execution ends%c", '\n'); - printf (" %c", '\n'); - printf ("Final values of the variables used in the benchmark:%c", '\n'); - printf (" %c", '\n'); - printf ("Int_Glob: %d\n", Int_Glob); - printf (" should be: %d\n", 5); - printf ("Bool_Glob: %d\n", Bool_Glob); - printf (" should be: %d\n", 1); - printf ("Ch_1_Glob: %c\n", Ch_1_Glob); - printf (" should be: %c\n", 'A'); - printf ("Ch_2_Glob: %c\n", Ch_2_Glob); - printf (" should be: %c\n", 'B'); - printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); - printf (" should be: %d\n", 7); - printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); - printf (" should be: Number_Of_Runs + 10%c", '\n'); - printf ("Ptr_Glob->%c", '\n'); -// printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent)%c", '\n'); - printf (" Discr: %d\n", Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 2); - printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 17); - printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING%c", '\n'); - printf ("Next_Ptr_Glob->%c", '\n'); -// printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent), same as above%c", '\n'); - printf (" Discr: %d\n", Next_Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 1); - printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 18); - printf (" Str_Comp: %s\n", - Next_Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING%c", '\n'); - printf ("Int_1_Loc: %d\n", Int_1_Loc); - printf (" should be: %d\n", 5); - printf ("Int_2_Loc: %d\n", Int_2_Loc); - printf (" should be: %d\n", 13); - printf ("Int_3_Loc: %d\n", Int_3_Loc); - printf (" should be: %d\n", 7); - printf ("Enum_Loc: %d\n", Enum_Loc); - printf (" should be: %d\n", 1); - printf ("Str_1_Loc: %s\n", Str_1_Loc); - printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING%c", '\n'); - printf ("Str_2_Loc: %s\n", Str_2_Loc); - printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING%c", '\n'); - - - - - - User_Time = End_Time - Begin_Time; - /* microseconds */ - - printf("Begin Time = %d\n",Begin_Time); - printf("End Time = %d\n",End_Time); - - - if (User_Time < Too_Small_Time) - { - printf ("Measured time too small to obtain meaningful results%c", '\n'); - printf ("Please increase number of runs%c", '\n'); - printf (" %c", '\n'); - } - else - { -#if DLX || OR1K - User_Time /= DLX_FREQ; -#if DLX - printf("DLX%c", ' '); -#else -#if OR1K - printf("OR1K%c", ' '); -#else - printf("Unknown CPU%c", '\n'); -#endif -#endif - printf("at %u MHz ", DLX_FREQ); - if (PROC_6) - printf("(+PROC_6) "); - printf(" %c", '\n'); -#endif - Microseconds = User_Time / Number_Of_Runs; - Dhrystones_Per_Second = Number_Of_Runs * 1000 / User_Time; - printf ("Microseconds for one run through Dhrystone:%c", ' '); - printf ("%d us / %d runs\n", User_Time,Number_Of_Runs); - printf ("Dhrystones per Second: %c", ' '); - printf ("%d \n", Dhrystones_Per_Second); - } - //report (0xdeaddead); -#ifdef MICROBLAZE - void exit(int); - exit(0); -#endif - return 0; -} - - -void Proc_1(Ptr_Val_Par) -/******************/ - - REG Rec_Pointer Ptr_Val_Par; - /* executed once */ -{ - REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; - /* == Ptr_Glob_Next */ - /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ - /* corresponds to "rename" in Ada, "with" in Pascal */ - - Ireport(0x20010); - - structassign(*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); - Ptr_Val_Par->variant.var_1.Int_Comp = 5; - Next_Record->variant.var_1.Int_Comp - = Ptr_Val_Par->variant.var_1.Int_Comp; - Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; - Proc_3(&Next_Record->Ptr_Comp); - Ireport(0x20011); - /* - * Ptr_Val_Par->Ptr_Comp->Ptr_Comp == Ptr_Glob->Ptr_Comp - */ - if (Next_Record->Discr == Ident_1) - /* then, executed */ - { - Next_Record->variant.var_1.Int_Comp = 6; - Proc_6(Ptr_Val_Par->variant.var_1.Enum_Comp, - &Next_Record->variant.var_1.Enum_Comp); - Ireport(0x20012); - Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; - Proc_7(Next_Record->variant.var_1.Int_Comp, 10, - &Next_Record->variant.var_1.Int_Comp); - } else /* not executed */ - structassign(*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); - Ireport(0x20013); - -} /* Proc_1 */ - - -void - Proc_2(Int_Par_Ref) -/******************/ - /* executed once */ - /* *Int_Par_Ref == 1, becomes 4 */ - - One_Fifty *Int_Par_Ref; -{ - One_Fifty Int_Loc; - Enumeration Enum_Loc = 0; - - Ireport(0x20020); - - Int_Loc = *Int_Par_Ref + 10; - do /* executed once */ - if (Ch_1_Glob == 'A') - /* then, executed */ - { - Int_Loc -= 1; - *Int_Par_Ref = Int_Loc - Int_Glob; - Enum_Loc = Ident_1; - } /* if */ - while (Enum_Loc != Ident_1);/* true */ -} /* Proc_2 */ - - -void - Proc_3(Ptr_Ref_Par) -/******************/ - /* executed once */ - /* Ptr_Ref_Par becomes Ptr_Glob */ - - Rec_Pointer *Ptr_Ref_Par; - -{ - Ireport(0x20030); - - if (Ptr_Glob != Null) - /* then, executed */ - *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; - Proc_7(10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); -} /* Proc_3 */ - - -void - Proc_4() -{ /* without parameters */ - /*******/ - /* executed once */ - Boolean Bool_Loc; - - Ireport(0x20040); - - Bool_Loc = Ch_1_Glob == 'A'; - Bool_Glob = Bool_Loc | Bool_Glob; - Ch_2_Glob = 'B'; -} /* Proc_4 */ - - -void - Proc_5() -{ /* without parameters */ - /*******/ - /* executed once */ - Ireport(0x20050); - - Ch_1_Glob = 'A'; - Bool_Glob = false; -} /* Proc_5 */ - -/* @(#)dhry_2.c 1.2 92/05/28 14:44:54, AMD */ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_2.c (part 3 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - **************************************************************************** - */ - -#ifndef REG -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#ifdef _AM29K -#undef REG -#define REG register /* Define REG; saves room on 127-char MS-DOS cmd line */ -#endif -#endif - - -void - Proc_6(Enum_Val_Par, Enum_Ref_Par) -/*********************************/ - /* executed once */ - /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ - - Enumeration Enum_Val_Par; - Enumeration *Enum_Ref_Par; -{ -#if PROC_6 - Ireport(0x20060); - - *Enum_Ref_Par = Enum_Val_Par; - if (!Func_3(Enum_Val_Par)) - /* then, not executed */ - *Enum_Ref_Par = Ident_4; - switch (Enum_Val_Par) { - case Ident_1: - *Enum_Ref_Par = Ident_1; - break; - case Ident_2: - if (Int_Glob > 100) - /* then */ - *Enum_Ref_Par = Ident_1; - else - *Enum_Ref_Par = Ident_4; - break; - case Ident_3: /* executed */ - *Enum_Ref_Par = Ident_2; - break; - case Ident_4: - break; - case Ident_5: - *Enum_Ref_Par = Ident_3; - break; - } /* switch */ -#endif - return; -} /* Proc_6 */ - - -void - Proc_7(Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) -/**********************************************/ - /* executed three times */ - /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ - /* Int_Par_Ref becomes 7 */ - /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ - /* Int_Par_Ref becomes 17 */ - /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ - /* Int_Par_Ref becomes 18 */ - One_Fifty Int_1_Par_Val; - One_Fifty Int_2_Par_Val; - One_Fifty *Int_Par_Ref; -{ - One_Fifty Int_Loc; - - Ireport(0x20070); - - Int_Loc = Int_1_Par_Val + 2; - *Int_Par_Ref = Int_2_Par_Val + Int_Loc; -} /* Proc_7 */ - - -void - Proc_8(Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) -/*********************************************************************/ - /* executed once */ - /* Int_Par_Val_1 == 3 */ - /* Int_Par_Val_2 == 7 */ - Arr_1_Dim Arr_1_Par_Ref; - Arr_2_Dim Arr_2_Par_Ref; - int Int_1_Par_Val; - int Int_2_Par_Val; -{ - REG One_Fifty Int_Index; - REG One_Fifty Int_Loc; - -#if DBG - printf("X) Int_1_Par_Val: %x\n", Int_1_Par_Val); - printf("X) Int_2_Par_Val: %x\n", Int_2_Par_Val); -#endif - - Ireport(0x20080); - - Int_Loc = Int_1_Par_Val + 5; - Arr_1_Par_Ref[Int_Loc] = Int_2_Par_Val; - Arr_1_Par_Ref[Int_Loc + 1] = Arr_1_Par_Ref[Int_Loc]; - Arr_1_Par_Ref[Int_Loc + 30] = Int_Loc; - for (Int_Index = Int_Loc; Int_Index <= Int_Loc + 1; ++Int_Index) - Arr_2_Par_Ref[Int_Loc][Int_Index] = Int_Loc; - Arr_2_Par_Ref[Int_Loc][Int_Loc - 1] += 1; - Arr_2_Par_Ref[Int_Loc + 20][Int_Loc] = Arr_1_Par_Ref[Int_Loc]; - Int_Glob = 5; - -#if DBG - printf("Y) Int_1_Par_Val: %x\n", Int_1_Par_Val); - printf("Y) Int_2_Par_Val: %x\n", Int_2_Par_Val); -#endif - -} /* Proc_8 */ - - -Enumeration - Func_1(Ch_1_Par_Val, Ch_2_Par_Val) -/*************************************************/ - /* executed three times */ - /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ - /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ - /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ - - Capital_Letter Ch_1_Par_Val; - Capital_Letter Ch_2_Par_Val; -{ - Capital_Letter Ch_1_Loc; - Capital_Letter Ch_2_Loc; - - Ireport(0x30010); - - Ch_1_Loc = Ch_1_Par_Val; - Ch_2_Loc = Ch_1_Loc; - if (Ch_2_Loc != Ch_2_Par_Val) - /* then, executed */ - return (Ident_1); - else { /* not executed */ - Ch_1_Glob = Ch_1_Loc; - return (Ident_2); - } -} /* Func_1 */ - - -Boolean - Func_2(Str_1_Par_Ref, Str_2_Par_Ref) -/*************************************************/ - /* executed once */ - /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ - /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ - - Str_30 Str_1_Par_Ref; - Str_30 Str_2_Par_Ref; -{ - REG One_Thirty Int_Loc; - Capital_Letter Ch_Loc = 0; - - Ireport(0x30020); - - Int_Loc = 2; - while (Int_Loc <= 2) /* loop body executed once */ - if (Func_1(Str_1_Par_Ref[Int_Loc], - Str_2_Par_Ref[Int_Loc + 1]) == Ident_1) - /* then, executed */ - { - Ch_Loc = 'A'; - Int_Loc += 1; - } /* if, while */ - Ireport(0x30021); - - if (Ch_Loc >= 'W' && Ch_Loc < 'Z') - /* then, not executed */ - Int_Loc = 7; - Ireport(0x30022); - if (Ch_Loc == 'R') - /* then, not executed */ - return (true); - else { /* executed */ - Ireport(0x30023); - if (strcmp(Str_1_Par_Ref, Str_2_Par_Ref) > 0) - /* then, not executed */ - { - Int_Loc += 7; - Int_Glob = Int_Loc; - return (true); - } else /* executed */ - return (false); - } /* if Ch_Loc */ -} /* Func_2 */ - - -Boolean - Func_3(Enum_Par_Val) -/***************************/ - /* executed once */ - /* Enum_Par_Val == Ident_3 */ - Enumeration Enum_Par_Val; -{ - Enumeration Enum_Loc; - - Enum_Loc = Enum_Par_Val; - Ireport(0x30030); - if (Enum_Loc == Ident_3) - /* then, executed */ - return (true); - else /* not executed */ - return (false); -} /* Func_3 */ diff --git a/cv32e40x/tests/programs/custom/dhrystone/test.yaml b/cv32e40x/tests/programs/custom/dhrystone/test.yaml deleted file mode 100644 index 80c0764b5d..0000000000 --- a/cv32e40x/tests/programs/custom/dhrystone/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: dhrystone -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Dhrystone benchmarking test diff --git a/cv32e40x/tests/programs/custom/fencei/fencei.c b/cv32e40x/tests/programs/custom/fencei/fencei.c deleted file mode 100644 index 718c7ca75b..0000000000 --- a/cv32e40x/tests/programs/custom/fencei/fencei.c +++ /dev/null @@ -1,135 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 - -#include -#include -#include "corev_uvmt.h" - -#define VP_ENAB_ADDR (CV_VP_FENCEI_TAMPER_BASE + 0) -#define VP_ADDR_ADDR (CV_VP_FENCEI_TAMPER_BASE + 4) -#define VP_DATA_ADDR (CV_VP_FENCEI_TAMPER_BASE + 8) - -static volatile uint32_t *vp_enab_ptr = (void *)VP_ENAB_ADDR; - -static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { - if (actual != expect) { - printf(msg); - printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); - exit(EXIT_FAILURE); - } -} - -int main(void) { - uint32_t tmpint; - register uint32_t reg0; - register uint32_t reg1; - uint32_t tmparr[4]; - - printf("fencei test\n"); - - printf("Sanity check a simple store/load\n"); - tmpint = 0; - __asm__ volatile("sw %0, 0(%1)" : : "r"(0x11223344), "r"(tmpint)); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmpint) : "r"(tmpint)); - assert_or_die(tmpint, 0x11223344, "error: a simple sw/lw should give written value back\n"); - - printf("Check store/fencei/load\n"); - tmpint = 0; - __asm__ volatile("sw %0, 0(%1)" : : "r"(0x22334455), "r"(tmpint)); - __asm__ volatile("fence.i"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmpint) : "r"(tmpint)); - assert_or_die(tmpint, 0x22334455, "error: a fence.i should not abort a sw\n"); - - printf("Check multiple stores\n"); - tmpint = tmparr[0] = tmparr[1] = tmparr[2] = tmparr[3] = 0; - __asm__ volatile("sw %0, 0x0(%1)" : : "r"(0x334455AA), "r"(tmparr[0])); - __asm__ volatile("sw %0, 0x4(%1)" : : "r"(0x334455BB), "r"(tmparr[0])); - __asm__ volatile("sw %0, 0x8(%1)" : : "r"(0x334455CC), "r"(tmparr[0])); - __asm__ volatile("sw %0, 0xC(%1)" : : "r"(0x334455DD), "r"(tmparr[0])); - __asm__ volatile("fence.i"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmpint) : "r"(*tmparr + 0x0)); - assert_or_die(tmpint, 0x334455AA, "error: a fence.i should not abort a sw\n"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmpint) : "r"(*tmparr + 0x4)); - assert_or_die(tmpint, 0x334455BB, "error: a fence.i should not abort a sw\n"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmpint) : "r"(*tmparr + 0x8)); - assert_or_die(tmpint, 0x334455CC, "error: a fence.i should not abort a sw\n"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmpint) : "r"(*tmparr + 0xC)); - assert_or_die(tmpint, 0x334455DD, "error: a fence.i should not abort a sw\n"); - - printf("Check interdigitated stores\n"); - tmpint = tmparr[0] = tmparr[1] = tmparr[2] = tmparr[3] = 0; - __asm__ volatile("sw %0, 0(%1)" : : "r"(0x445566AA), "r"(*tmparr + 0x0)); - __asm__ volatile("fence.i"); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0x445566BB), "r"(*tmparr + 0x4)); - __asm__ volatile("fence.i"); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0x445566CC), "r"(*tmparr + 0x8)); - __asm__ volatile("fence.i"); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0x445566DD), "r"(*tmparr + 0xC)); - __asm__ volatile("fence.i"); - __asm__ volatile("lw %0, 0x0(%1)" : "=r"(tmpint) : "r"(*tmparr)); - assert_or_die(tmpint, 0x445566AA, "error: a fence.i should not abort a sw\n"); - __asm__ volatile("lw %0, 0x4(%1)" : "=r"(tmpint) : "r"(*tmparr)); - assert_or_die(tmpint, 0x445566BB, "error: a fence.i should not abort a sw\n"); - __asm__ volatile("lw %0, 0x8(%1)" : "=r"(tmpint) : "r"(*tmparr)); - assert_or_die(tmpint, 0x445566CC, "error: a fence.i should not abort a sw\n"); - __asm__ volatile("lw %0, 0xC(%1)" : "=r"(tmpint) : "r"(*tmparr)); - assert_or_die(tmpint, 0x445566DD, "error: a fence.i should not abort a sw\n"); - - printf("Check self-modifying code\n"); - reg0 = reg1 = 0; - __asm__ volatile( - // Overwrite "old" instr with "new" instr - " la %0, new \n" - " lw %0, 0(%0) \n" - " la %1, old \n" - " j run \n" - "new: \n" - " addi %0, x0, 234\n" - " j end \n" - "run: \n" - " sw %0, 0(%1) \n" - " fence.i \n" // Can use "nop" instead of fence.i, to see how it otherwise fails - "old: \n" - " addi %0, x0, 123\n" - "end: \n" - : "=r"(reg0), "=r"(reg1)); - assert_or_die(reg0, 234, "overwriting instruction data should be visible after fencei\n"); - - printf("Check env-modifying code\n"); - __asm__ volatile( - " li %0, %2 \n" // Load dummy instr into vp's "data" - " la %1, dummy_instr \n" - " lw %1, 0(%1) \n" - " sw %1, 0(%0) \n" - " li %0, %3 \n" // Load exec address into vp's "addr" - " la %1, exec_instr \n" - " sw %1, 0(%0) \n" - " li %0, %4 \n" // Enable vp - " li %1, 1 \n" - " sw %1, 0(%0) \n" - "dummy_instr: \n" // ... - " addi %0, x0, 222 \n" - " fence.i \n" // (Upon this fencei, vp should swap out exec_instr) - "exec_instr: \n" - " addi %0, x0, 111 \n" // (Should execute dummy_instr instead) - : "=r"(reg0), "=r"(reg1) - : "i"(VP_DATA_ADDR), "i"(VP_ADDR_ADDR), "i"(VP_ENAB_ADDR)); - assert_or_die(reg0, 222, "env should have swapped the exec instruction\n"); - *vp_enab_ptr = 0; // Disable vp - - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/fibonacci/fibonacci.c b/cv32e40x/tests/programs/custom/fibonacci/fibonacci.c deleted file mode 100644 index c803377ea3..0000000000 --- a/cv32e40x/tests/programs/custom/fibonacci/fibonacci.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * - * Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com - * - * The contents of this file are provided under the Software License - * Agreement that you accepted before downloading this file. - * - * This source forms part of the Software and can be used for educational, - * training, and demonstration purposes but cannot be used for derivative - * works except in cases where the derivative works require OVP technology - * to run. - * - * For open source models released under licenses that you can use for - * derivative works, please visit www.OVPworld.org or www.imperas.com - * for the location of the open source models. - * - */ - -#include -#include - -static int fib(int i) { - return (i>1) ? fib(i-1) + fib(i-2) : i; -} - -int main(int argc, char *argv[]) { - - int i; - int num = (argc >= 2) ? atoi((const char *)argv[1]) : 15; - - printf("starting fib(%d)...\n", num); - - for(i=0; i - Fibonacci sequence directed test diff --git a/cv32e40x/tests/programs/custom/generic_exception_test/generic_exception_test.S b/cv32e40x/tests/programs/custom/generic_exception_test/generic_exception_test.S deleted file mode 100644 index e0ecf97b60..0000000000 --- a/cv32e40x/tests/programs/custom/generic_exception_test/generic_exception_test.S +++ /dev/null @@ -1,503 +0,0 @@ -# -# Copyright (C) 2020 by EM Microelectronic US Inc. -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -# -############################################################################### -# -# Generic Exception Test: this directed, manually written test-program covers -# many, but not all Exceptions listed in the CV32E40X -# exceptions verfication plan plus a number of others -# intended to fill holes identified by code coverage. -# -# The pass/fail criteria is determined by checking x26 against MAGIC_NUMBER, -# the value of which is determined by summing the following: -# - Exception code 2 (Illegal Instruction Exceptions (IIE)): 0x1 -# - Exception code 3 (Breakpoint): 0x10 -# - Exception code 11 (Environment call): 0x100 -# If the test has one of each exception code, MAGIC_NUMBER is 0x111 -# -############################################################################### - -#include "corev_uvmt.h" - -.globl _start -.globl main -.globl exit -.global debug -.section .text -.global test_results -.global u_sw_irq_handler - - #define MAGIC_NUMBER 0x2f3 - -test_results: - .word 123456789 -# main test -main: - li x15, 0x00001800 - csrrw x0, mstatus, x15 # redundant in cv32e40x: hardwired PoR value - li x0, 0xf21ee7dc - li x1, 0x80000000 - li x3, 0xccda4374 - li x4, 0x0 - li x5, 0xf4cb539d - li x6, 0x80000000 - li x7, 0x3 - li x8, 0xfdef1f09 - li x9, 0x80000000 - li x10, 0x4 - li x11, 0xf58fad61 - li x12, 0xfb6606db - li x13, 0x0 - li x14, 0x0 - li x16, 0x0 - li x17, 0xf61163af - li x18, 0x0 - li x19, 0x0 - li x20, 0xc552e854 - li x21, 0xc553e854 - li x22, 0xf3ae47cd - li x23, 0x0 - li x24, 0x00012000 - li x25, 0x80000000 - li x26, 0x0 - li x27, 0xffa38c28 - li x28, 0xf915a8c7 - li x29, 0x9 - li x30, 0x0 - li x31, 0x5912efde - li x4, 0x40001104 - csrrc x30, mtvec, x0 -#2220.000 ns: Illegal instruction (core 0) at PC 0x0000017c: - .word(0x00000000) #Exception Code: 2 (illegal instruction) - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - c.ebreak #Exception Code: 3 (breakpoint) - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - ebreak #Exception Code: 3 (breakpoint) - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - ecall #Exception Code: 11 (env call from M-mode) - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - c.addi sp, -8 - sw t0, 4(sp) - li x15, 0x00001808 - csrs mstatus, x15 - lw t0, 4(sp) - c.addi sp, 8 -#6645.000 ns: Illegal instruction (core 0) at PC 0x000001ec: - .word(0x00000000) #Exception Code: 2 - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - c.ebreak #Exception Code: 3 - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - ebreak #Exception Code: 3 - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - ecall #Exception Code: 11 - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - lw x0, 0(x24) #No Exception - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop -#11118.000 ns: Illegal instruction (core 0) at PC 0x00000260: - .word(0x0057179B) #Exception Code: 2 #SLLIW - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop -#12186.000 ns: Illegal instruction (core 0) at PC 0x00000278: - .word(0x0057579B) #Exception Code: 2 #SRLIW - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop -#13254.000 ns: Illegal instruction (core 0) at PC 0x00000290: - .word(0x4057579B) #Exception Code: 2 #SRAIW - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop -#14322.000 ns: Illegal instruction (core 0) at PC 0x000002a8: - csrrc x17, 0x7B0, x0 #Exception Code: 2 #Cannot access DCSR in M mode - li x18, 0x00008000 - or x17, x17, x18 -#15306.000 ns: Illegal instruction (core 0) at PC 0x000002b2: - csrrw x0, 0x7B0, x17 #Exception Code: 2 #Cannot access DCSR in M mode -#16290.000 ns: Illegal instruction (core 0) at PC 0x000002b6: - csrrc x17, 0x7B0, x0 #Exception Code: 2 #Cannot access DCSR in M mode - add x17, x1, x0 - c.addi x17, 12 -#17265.000 ns: Illegal instruction (core 0) at PC 0x000002c0: - csrrw x0, 0x7B1, x17 #Exception Code: 2 #Cannot access DPC in M mode -#18246.000 ns: Illegal instruction (core 0) at PC 0x000002c4: - csrrc x17, 0x7B1, x0 #Exception Code: 2 #Cannot access DPC in M mode - ebreak - nop - nop - csrrc x14, mstatus, x0 - csrrw x0, mstatus, x15 - csrrc x14, mstatus, x0 - nop - nop - -added_by_mike: -############################################################################### -# Randomly generated illegal instructions. Each one adds 0x1 to MAGIC_NUMBER - .word(0x3bc6f92f) - .word(0x5dd26da7) - .word(0xe5607a57) - .word(0x958e4a67) - .word(0x6159607b) - .word(0x6c6b7433) - .word(0x1a6a2b33) - .word(0xd9067c3b) - .word(0xfa133223) - .word(0x6fcbc273) - .word(0x395dd7e7) -# - .word(0xaeabed23) - .word(0xaed5b7a3) - .word(0xaebf4677) - .word(0x3bc6f92f) - .word(0x5dd26da7) - .word(0xe5607a57) - .word(0x958e4a67) - .word(0x6159607b) - .word(0x6c6b7433) - .word(0x1a6a2b33) - .word(0xd9067c3b) - .word(0xfa133223) - .word(0x4b724b57) - .word(0x6fcbc273) - .word(0x395dd7e7) - .word(0x079f0c07) -# - .word(0x57f0f043) - .word(0xc06d0abb) - .word(0x75d8b2fb) - .word(0xd0a96e1b) - .word(0x2e709e13) - .word(0x77048bc3) - .word(0x8b517f2b) - .word(0x34fcb22f) - .word(0xf3d1a2af) - .word(0xd7ac0c9b) - .word(0x2eeb2953) - .word(0x3625c82f) - .word(0x226d459b) - .word(0x1d4d43ab) - .word(0xb7aecccf) - .word(0x1ac1e077) -# - .word(0x25ffc977) - .word(0xceb61647) - .word(0x4284de0f) - .word(0x585f6a87) - .word(0x3d1d4d1b) - .word(0xaf99d353) - .word(0x27a04dc3) - .word(0xc6b46abb) - .word(0x7c18c9b3) - .word(0x8980c387) - .word(0xefff246b) - .word(0xeebb984f) - .word(0x5724448f) - .word(0xc964b70f) - .word(0x58ff393b) - .word(0xaf9ac3a7) -# - .word(0x70f6bf03) - .word(0x9da18a53) - .word(0x6738ef8f) - .word(0xf4f4ba5b) - .word(0xb4208057) - .word(0x72857967) - .word(0x64599d9b) - .word(0x7328b2bb) - .word(0x9fddb933) - .word(0x60628efb) - .word(0xaec951bb) - .word(0xc56f4a27) - .word(0x2e266467) - .word(0xa847620b) - .word(0x5dd26c27) - .word(0xb8ba7523) -# - .word(0x1747bf03) - .word(0x6e4970cb) - .word(0xc00624eb) - .word(0x3847b3bb) - .word(0x0faf5f9b) - .word(0xd168d413) - .word(0x1f6e1d93) - .word(0x834cd51b) - .word(0xf787e7eb) - .word(0x1f9b1a27) - .word(0x270990eb) - .word(0xe78c4473) - .word(0x427706f7) - .word(0xbcd64e2f) - .word(0x17f9256b) - .word(0x4c9cb05b) -# - .word(0x2ec14d9b) - .word(0x974ffc9b) - .word(0xdd91c02f) - .word(0xc6309677) - .word(0xf2ddf1e7) - .word(0xdc656757) - .word(0x8b454423) - .word(0x1305370b) - .word(0x6b235b3b) - .word(0x6d781c53) - .word(0xa4b020eb) - .word(0xf585a0f7) - .word(0xbd5907f3) - .word(0x4d4a9e6b) - .word(0x080f3b7b) - .word(0x3eaccb2f) -# - .word(0x4b724b57) # PULP VECOP instruction - will only cause an IIE if XPULP=0 -############################################################################### -# Target specific code cov holes in the cv32e40x_decoder. -# -# For OPCODE_SYSTEM (instr_rdata[6:0]=='h73), instr_rdata[31:20] must be one of: -# 12'h000 (ecall), 12'h001 (ebreak), -# 12'h002 (uret), 12'h302 (mret) or 12'h7b2 (dret). -# Otherwise it is an illegal instruction (add 0x1 to MAGIC_NUMBER). - .word(0x00300073) - .word(0x00400073) - .word(0x30000073) - .word(0x30100073) - .word(0x30500073) - .word(0x7b000073) - .word(0x7b100073) - .word(0x7b300073) - .word(0xf0000073) -# Reading floating point CSRs:FFLAGS, FRM, FCSR (add 0x1 to MAGIC_NUMBER) - csrrw x0, 0x001, x0 #FFLAGS - csrrw x0, 0x002, x0 #FRM - csrrw x0, 0x003, x0 #FCSR - csrrw x0, 0x807, x0 #FPREC -# Writes to CSRs: MVENDORID, MARCHID, MIMPID, MHARTID (add 0x1 to MAGIC_NUMBER) - csrrw x0, 0xF11, x0 #MVENDORID - csrrw x0, 0xF12, x0 #MARCHID - csrrw x0, 0xF13, x0 #MIMPID - csrrw x0, 0xF14, x0 #MHARTID -# Writes to to any HPM CSRs (add 0x1 to MAGIC_NUMBER) - csrrw x0, 0xC00, x0 #CYCLE - csrrw x0, 0xC02, x0 #INSRET - csrrw x0, 0xC03, x0 #HPMCOUNTER3 - csrrw x0, 0xC80, x0 #CYCLEH - csrrw x0, 0xC82, x0 #INSRETH - csrrw x0, 0xC83, x0 #HPMCOUNTER3H -#Writes to to any User-mode CSRs (add 0x1 to MAGIC_NUMBER) - csrrw x0, 0x000, x0 #USTATUS - csrrw x0, 0x041, x0 #UEPC - csrrw x0, 0x042, x0 #UCAUSE - csrrw x0, 0x005, x0 #UTVEC - csrrw x0, 0x004, x0 #UIE (no specific check of these in the decoder) - csrrw x0, 0x040, x0 #USCRATCH - csrrw x0, 0x043, x0 #UTVAL - csrrw x0, 0x044, x0 #UIP -# p.elw - .word(0x00006003) # add 0x1 to MAGIC_NUMBER - .word(0x00106003) # add 0x1 to MAGIC_NUMBER - .word(0x00206003) # add 0x1 to MAGIC_NUMBER - .word(0x00406003) # add 0x1 to MAGIC_NUMBER - .word(0x00806003) # add 0x1 to MAGIC_NUMBER - .word(0x01006003) # add 0x1 to MAGIC_NUMBER -# uret - uret # add 0x1 to MAGIC_NUMBER -# p.elw - .word(0x02006003) # add 0x1 to MAGIC_NUMBER - .word(0x04006003) # add 0x1 to MAGIC_NUMBER - .word(0x08006003) # add 0x1 to MAGIC_NUMBER - .word(0x10006003) # add 0x1 to MAGIC_NUMBER - .word(0x20006003) # add 0x1 to MAGIC_NUMBER - .word(0x40006003) # add 0x1 to MAGIC_NUMBER - .word(0x80006003) # add 0x1 to MAGIC_NUMBER -# unused fields in fence (these should _not_ add to MAGIC_NUMBER - .word(0x00000F8F) # rd/imm5 =0b11111 - .word(0x000F800F) # rs1 =0b11111 -exit: - lw x18, test_results /* report passed result */ - li x16, MAGIC_NUMBER - beq x26, x16, test_end - li x18, 1 -test_end: - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - j _exit - -u_sw_irq_handler: - addi sp,sp,-120 - sw x1,116(sp) - sw x2,112(sp) - sw x3,108(sp) - sw x4,104(sp) - sw x5,100(sp) - sw x6,96(sp) - sw x7,92(sp) - sw x8,88(sp) - sw x9,84(sp) - sw x10,80(sp) - sw x11,76(sp) - sw x12,72(sp) - sw x13,68(sp) - sw x14,64(sp) - sw x15,60(sp) - sw x16,56(sp) - sw x17,52(sp) - sw x18,48(sp) - sw x19,44(sp) - sw x20,40(sp) - sw x21,36(sp) - sw x22,32(sp) - sw x23,28(sp) - sw x24,24(sp) - sw x25,20(sp) - sw x28,16(sp) - sw x29,12(sp) - sw x30,8(sp) - sw x31,4(sp) - c.addi x27, 1 - csrrc x31, mtvec, x0 - beq x31, x30, continue_check - lui a3, 0x1 - add x26, x26, a3 -continue_check: - li t6, 0xf - csrrc t5, mcause, x0 - and t6, t6, t5 - li t4, 2 - bne t6, t4, _check_3 - addi x26, x26, 0x1 # illegal instruction (exception code 2): add 0x1 to x26 - csrrc s0, mepc, x0 - c.addi s0, 4 - csrrw x0, mepc, s0 - j _end_trap_Generic_Handler_ASM -_check_3: - li t4, 3 - bne t6, t4, _check_11 - addi x26, x26, 0x10 # ebreak: add 0x10 to x26 - csrrc s0, mepc, x0 - c.addi s0, 2 - csrrw x0, mepc, s0 - j _end_trap_Generic_Handler_ASM -_check_11: - li t4, 11 - bne t6, t4, _end_trap_Generic_Handler_ASM - addi x26, x26, 0x100 # ecall: add 0x100 to x26 - csrrc s0, mepc, x0 - c.addi s0, 4 - csrrw x0, mepc, s0 -_end_trap_Generic_Handler_ASM: - lw x1,116(sp) - lw x2,112(sp) - lw x3,108(sp) - lw x4,104(sp) - lw x5,100(sp) - lw x6,96(sp) - lw x7,92(sp) - lw x8,88(sp) - lw x9,84(sp) - lw x10,80(sp) - lw x11,76(sp) - lw x12,72(sp) - lw x13,68(sp) - lw x14,64(sp) - lw x15,60(sp) - lw x16,56(sp) - lw x17,52(sp) - lw x18,48(sp) - lw x19,44(sp) - lw x20,40(sp) - lw x21,36(sp) - lw x22,32(sp) - lw x23,28(sp) - lw x24,24(sp) - lw x25,20(sp) - lw x28,16(sp) - lw x29,12(sp) - lw x30,8(sp) - lw x31,4(sp) - addi sp,sp,120 - mret - -_exit: - j _exit - -debug: - j _exit diff --git a/cv32e40x/tests/programs/custom/hello-world/hello-world.c b/cv32e40x/tests/programs/custom/hello-world/hello-world.c deleted file mode 100644 index 64fb354f48..0000000000 --- a/cv32e40x/tests/programs/custom/hello-world/hello-world.c +++ /dev/null @@ -1,143 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Sanity test for the CV32E40X core. Reads the MVENDORID, MISA, MARCHID and -** MIMPID CSRs and prints some useful (?) -** messages to stdout. Will fail if these -** CSRs do not match expected values. -** -******************************************************************************* -*/ - -#include -#include - -#define EXP_MISA 0x40001104 - -int main(int argc, char *argv[]) -{ - unsigned int misa_rval, mvendorid_rval, marchid_rval, mimpid_rval, mxl; - int reserved, tentative, nonstd, user, super; - - mxl = 0; reserved = 0; tentative = 0; nonstd = 0; user = 0; super = 0; - - /* inline assembly: read mvendorid and misa */ - __asm__ volatile("csrr %0, 0xF11" : "=r"(mvendorid_rval)); - __asm__ volatile("csrr %0, 0x301" : "=r"(misa_rval)); - __asm__ volatile("csrr %0, 0xF12" : "=r"(marchid_rval)); - __asm__ volatile("csrr %0, 0xF13" : "=r"(mimpid_rval)); - - /* Check MVENDORID CSR: 0x602 is the value assigned by JEDEC to the OpenHW Group */ - if (mvendorid_rval != 0x00000602) { - printf("\tERROR: CSR MVENDORID reads as 0x%x - should be 0x00000602 for the OpenHW Group.\n\n", mvendorid_rval); - return EXIT_FAILURE; - } - - /* Check MISA CSR: if its zero, it might not be implemented at all */ - if (misa_rval != EXP_MISA) { - printf("\tERROR: CSR MISA reads as 0x%x - should be 0x%x for this release of CV32E40X!\n\n", misa_rval, EXP_MISA); - return EXIT_FAILURE; - } - - /* Check MARCHID CSR: 0x4 is the value assigned by the RISC-V Foundation to CV32E40X */ - if (marchid_rval != 0x00000014) { - printf("\tERROR: CSR MARCHID reads as 0x%x - should be 0x00000014 for CV32E40X.\n\n", marchid_rval); - return EXIT_FAILURE; - } - - /* Check MIMPID CSR: 0x0 is the value assigned by the OpenHW Group to the first release of CV32E40X */ - if (mimpid_rval != 0x00000000) { - printf("\tERROR: CSR MIMPID reads as 0x%x - should be 0x00000000 for this release of CV32E40X.\n\n", mimpid_rval); - return EXIT_FAILURE; - } - - /* Print a banner to stdout and interpret MISA CSR */ - printf("\nHELLO WORLD!!!\n"); - printf("This is the OpenHW Group CV32E40X CORE-V processor core.\n"); - printf("CV32E40X is a RISC-V ISA compliant core with the following attributes:\n"); - printf("\tmvendorid = 0x%x\n", mvendorid_rval); - printf("\tmarchid = 0x%x\n", marchid_rval); - printf("\tmimpid = 0x%x\n", mimpid_rval); - printf("\tmisa = 0x%x\n", misa_rval); - mxl = ((misa_rval & 0xC0000000) >> 30); // MXL == MISA[31:30] - switch (mxl) { - case 0: printf("\tERROR: MXL cannot be zero!\n"); - return EXIT_FAILURE; - break; - case 1: printf("\tXLEN is 32-bits\n"); - break; - case 2: printf("\tXLEN is 64-bits\n"); - break; - case 3: printf("\tXLEN is 128-bits\n"); - break; - default: printf("\tERROR: mxl (%0d) not in 0..3, your code is broken!\n", mxl); - return EXIT_FAILURE; - } - - printf("\tSupported Instructions Extensions: "); - if ((misa_rval >> 25) & 0x00000001) ++reserved; - if ((misa_rval >> 24) & 0x00000001) ++reserved; - if ((misa_rval >> 23) & 0x00000001) { - printf("X"); - ++nonstd; - } - if ((misa_rval >> 22) & 0x00000001) ++reserved; - if ((misa_rval >> 21) & 0x00000001) ++tentative; - if ((misa_rval >> 20) & 0x00000001) ++user; - if ((misa_rval >> 19) & 0x00000001) ++tentative; - if ((misa_rval >> 18) & 0x00000001) ++super; - if ((misa_rval >> 17) & 0x00000001) ++reserved; - if ((misa_rval >> 16) & 0x00000001) printf("Q"); - if ((misa_rval >> 15) & 0x00000001) ++tentative; - if ((misa_rval >> 14) & 0x00000001) ++reserved; - if ((misa_rval >> 13) & 0x00000001) printf("N"); - if ((misa_rval >> 12) & 0x00000001) printf("M"); - if ((misa_rval >> 11) & 0x00000001) ++tentative; - if ((misa_rval >> 10) & 0x00000001) ++reserved; - if ((misa_rval >> 9) & 0x00000001) printf("J"); - if ((misa_rval >> 8) & 0x00000001) printf("I"); - if ((misa_rval >> 7) & 0x00000001) printf("H"); - if ((misa_rval >> 6) & 0x00000001) printf("G"); - if ((misa_rval >> 5) & 0x00000001) printf("F"); - if ((misa_rval >> 4) & 0x00000001) printf("E"); - if ((misa_rval >> 3) & 0x00000001) printf("D"); - if ((misa_rval >> 2) & 0x00000001) printf("C"); - if ((misa_rval >> 1) & 0x00000001) printf("B"); - if ((misa_rval ) & 0x00000001) printf("A"); - printf("\n"); - if (super) { - printf("\tThis machine supports SUPERVISOR mode.\n"); - } - if (user) { - printf("\tThis machine supports USER mode.\n"); - } - if (nonstd) { - printf("\tThis machine supports non-standard instructions.\n"); - } - if (tentative) { - printf("\tWARNING: %0d tentative instruction extensions are defined!\n", tentative); - } - if (reserved) { - printf("\tERROR: %0d reserved instruction extensions are defined!\n\n", reserved); - return EXIT_FAILURE; - } - else { - printf("\n"); - return EXIT_SUCCESS; - } -} diff --git a/cv32e40x/tests/programs/custom/hello-world/test.yaml b/cv32e40x/tests/programs/custom/hello-world/test.yaml deleted file mode 100644 index 62b7b16e49..0000000000 --- a/cv32e40x/tests/programs/custom/hello-world/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: hello-world -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Simple hello-world sanity test diff --git a/cv32e40x/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c b/cv32e40x/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c deleted file mode 100644 index 306ac8a2c9..0000000000 --- a/cv32e40x/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c +++ /dev/null @@ -1,638 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -** -******************************************************************************* -** -** Performance counter directed test -** -** Very basic sanity check for: -** -** - Count load use hazards -** - Count jump register hazards -** - Count memory read transactions -** - Count memory write transactions -** - Count jumps -** - Count branches (conditional) -** - Count branches taken (conditional) -** - Compressed instructions -** - Retired instructions -** -** Make sure to instantiate cv32e40x_wrapper with the parameter -** NUM_MHPMCOUNTERS = 1 (or higher) -** -******************************************************************************* -*/ - -#include -#include -#include - -static int chck(unsigned int is, unsigned int should) -{ - int err; - err = is == should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -int main(int argc, char *argv[]) -{ - int err_cnt = 0; - - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - volatile unsigned int event; - volatile unsigned int count; - volatile unsigned int minstret; - volatile unsigned int count_while_on; - - volatile unsigned int mcycle_count; - - __asm__ volatile(".option rvc"); - - ////////////////////////////////////////////////////////////// - // Cycle count - printf("\nCycle count"); - - // Setup events and set csrs to 0 - event = EVENT_CYCLES; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB00, 0x0"); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - - // Readback Counter to verify 0 - __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - printf("\nCheck proper zeroization\n"); - err_cnt += chck(minstret, 0); - err_cnt += chck(count, 0); - err_cnt += chck(count, mcycle_count); - - // Enable counters - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("csrr t0, minstret\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - printf("\nCycle count while running = %d", count); - printf("\nMCYCLE counted cycles = %d\n", mcycle_count); - err_cnt += chck(count, mcycle_count); - err_cnt += chck(count, 6); - - ////////////////////////////////////////////////////////////// - // IF_INVALID - printf("\nIF_INVALID"); - - event = EVENT_IF_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("addi t1, x0, 0\n\t\ - addi t0, x0, 5\n\t\ - branch_target_ifinv_1: addi t1, t1, 1\n\t\ - bne t0, t1, branch_target_ifinv_1\n\t\ - nop" \ - : : : "t0", "t1"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4 + (2*5)); - printf("\nUnderutilized cycles on ID-stage due to IF stage = %d\n", count); - err_cnt += chck(count, 4); - - ////////////////////////////////////////////////////////////// - // ID_INVALID - LD_STALL - printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("lw x4, 0(sp)\n\t\ - addi x5, x4, 1\n\t\ - lw x6, 0(sp)\n\t\ - addi x7, x0, 1" \ - : : : "x4", "x5", "x6", "x7"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // ID_INVALID - JR STALL - printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("auipc x4, 0\n\t\ - jalr x0, x4, 8\n\t\ - nop" \ - : : : "x4"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // EX_INVALID - printf("\nEX_INVALID"); - event = EVENT_EX_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("lw x0, 0(x0)"); - __asm__ volatile("lw x31, 0(x31)"); - __asm__ volatile("lw x30, 0(x30)"); - __asm__ volatile("lw x29, 0(x29)"); - __asm__ volatile("lw x28, 0(x28)"); - __asm__ volatile("mulh x0, x0, x0"); // 3 cycles - __asm__ volatile("li x31, 4"); - __asm__ volatile("li x30, 3"); - __asm__ volatile("mulh x0, x31, x30"); // 3 cycles - __asm__ volatile("li x31, 9"); - __asm__ volatile("li x30, 7");; - __asm__ volatile("mulh x0, x31, x30"); // 3 cycles - __asm__ volatile("li x31, 47"); - __asm__ volatile("li x30, 17"); - __asm__ volatile("div x0, x31, x30"); // 32 cycles - __asm__ volatile("li x31, 1"); - __asm__ volatile("li x30, 1"); - __asm__ volatile("div x0, x31, x30"); // 32 cycles - __asm__ volatile("rem x0, x31, x30"); // 32 cycles - __asm__ volatile("lw x0, 0(sp)"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 21); - printf("\nUnderutilized cycles on WB-stage due to EX stage = %d\n", count); - err_cnt += chck(count, 104); - - ////////////////////////////////////////////////////////////// - // WB_INVALID Write port underutilization - - printf("\nWrite port underutilization"); - event = EVENT_WB_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - - __asm__ volatile("li x31, 1\n\t\ - li x30, 1\n\t\ - div x0, x31, x30\n\t\ - lw x29, 0(sp)\n\t\ - sw x29, 0(sp)" \ - : : : "x28", "x29", "x30", "x31"); - - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 6); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck(count, 34); - - ////////////////////////////////////////////////////////////// - // WB_DATA_STALL Write port underutilization due to data_rvalid_i (0) - printf("\nWrite port underutilization due to data_rvalid_i"); - event = EVENT_WB_DATA_STALL; - - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - - // Do not count stall cycles (WB_INVALID) due to multicycle instructions - // and force misaligned store to create data stalls (3 misaligned in the following seq) - __asm__ volatile("li x31, 7\n\t\ - li x30, 3\n\t\ - addi x0, x31, 1\n\t\ - lw x29, 0(sp)\n\t\ - lw x28, -1(sp)\n\t\ - srli x30, x29, 2\n\t\ - slli x30, x30, 2\n\t\ - xori x30, x30, 1\n\t\ - sw x29, 0(x30)\n\t\ - sw x29, 0(sp)\n\t\ - lw x28, -1(sp)\n\t\ - csrr x29, 0xB00\n\t\ - div x0, x31, x30" \ - : : : "x28", "x29", "x30", "x31"); - - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 14); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Retired instruction count (0) - Immediate minstret read - printf("\nRetired instruction count (0)"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("csrr t0, minstret\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on - - printf("\nminstret count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 0); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - ////////////////////////////////////////////////////////////// - // Retired instruction count (1) - minstret read-after-write - printf("\nRetired instruction count (1)"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("csrwi minstret, 0xA\n\t\ - csrr t0, minstret\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0\n\t\ - nop" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // - - printf("\nminstret count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 0xA); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 0xF); - - ////////////////////////////////////////////////////////////// - // Retired instruction count (2) - printf("\nRetired instruction count (2)"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)\n\t\ - addi t0, x0, 5\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0\n\t\ - lw t2, 0(sp)\n\t\ - branch_target: addi t2, t2, 1\n\t\ - addi t1, t1, 1\n\t\ - lw t2, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - bne t0, t1, branch_target\n\t\ - j jump_target\n\t\ - lw t2, 0(sp)\n\t\ - lw t2, 0(sp)\n\t\ - jump_target: nop\n\t\ - nop\n\t\ - nop" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5 + 6*5 + 4 + 1); - - ////////////////////////////////////////////////////////////// - // Count load use hazards - printf("\nCount load use hazards"); - - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x4, 0(sp)\n\t\ - addi x5, x4, 1\n\t\ - lw x6, 0(sp)\n\t\ - addi x7, x0, 1" \ - : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load use hazards count = %d\n", count); - err_cnt += chck(count, 1); // Hazard count is 1 in the absence of interface stalls - - ////////////////////////////////////////////////////////////// - // Count jump register hazards - printf("\nCount Jump register hazards"); - - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0" \ - : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Jump register hazards count = %d\n", count); - err_cnt += chck(count, 1); // Hazard count is 1 in the absence of interface stalls - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - Read while enabled - printf("\nCount memory read transactions (0)"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x0, 0(sp)\n\t\ - csrr t0, mhpmcounter3\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 1); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 1); - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - Write after load event - printf("\nCount memory read transactions (1)"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x0, 0(sp)\n\t\ - csrwi mhpmcounter3, 0xA\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 0xA); - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - printf("\nCount memory read transactions (2)"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x0, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("j jump_target_memread"); // do not count jump in mphmevent3 - __asm__ volatile("nop"); // do not count nop in instret - __asm__ volatile("jump_target_memread:"); - __asm__ volatile("lw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count memory write transactions - printf("\nCount memory write transactions"); - - event = EVENT_DATA_WRITE; // Trigger on stores - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Store count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count jumps - printf("\nCount jumps"); - - event = EVENT_JUMP; // Trigger on jumps - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("j jump_target_0"); // count++ - __asm__ volatile("jump_target_0:"); - __asm__ volatile("j jump_target_1"); // count++ - __asm__ volatile("jump_target_1:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 3); - - printf("Jump count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count branches (conditional) - printf("\nCount branches (conditional)"); - - event = EVENT_BRANCH; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_0"); // count++ - __asm__ volatile("branch_target_0:"); - __asm__ volatile("bne x0, x0, branch_target_1"); // count++ - __asm__ volatile("branch_target_1:"); - __asm__ volatile("beq x0, x0, branch_target_2"); // count++ - __asm__ volatile("branch_target_2:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Branch count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Count branches taken (conditional) - printf("\nCount branches taken (conditional)"); - - event = EVENT_BRANCH_TAKEN; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_3"); // count++ - __asm__ volatile("branch_target_3:"); - __asm__ volatile("bne x0, x0, branch_target_4"); // (not taken) - __asm__ volatile("branch_target_4:"); - __asm__ volatile("beq x0, x0, branch_target_5"); // count++ - __asm__ volatile("branch_target_5:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Branch taken count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Compressed instructions - printf("\nCompressed instructions"); - - event = EVENT_COMP_INSTR; // Trigger on compressed instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("c.addi x15, 1\n\t\ - c.nop\n\t\ - c.addi x15, 1" \ - : : : "x15"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Compressed count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Check for errors - printf("\nDone\n\n"); - - if (err_cnt) - printf("FAILURE. %d errors\n\n", err_cnt); - else - printf("SUCCESS\n\n"); - - return err_cnt; -} diff --git a/cv32e40x/tests/programs/custom/hpmcounter_basic_nostall_test/test.yaml b/cv32e40x/tests/programs/custom/hpmcounter_basic_nostall_test/test.yaml deleted file mode 100644 index bc9b55d055..0000000000 --- a/cv32e40x/tests/programs/custom/hpmcounter_basic_nostall_test/test.yaml +++ /dev/null @@ -1,7 +0,0 @@ -name: hpmcounter_basic_nostall_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - HPM Counter Basic Test, no random obi stalls enabled -plusargs: > - +rand_stall_obi_disable - diff --git a/cv32e40x/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c b/cv32e40x/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c deleted file mode 100644 index be1b3eaaca..0000000000 --- a/cv32e40x/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c +++ /dev/null @@ -1,666 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -** -******************************************************************************* -** -** Performance counter directed test -** -** Very basic sanity check for: -** -** - Count load use hazards -** - Count jump register hazards -** - Count memory read transactions -** - Count memory write transactions -** - Count jumps -** - Count branches (conditional) -** - Count branches taken (conditional) -** - Compressed instructions -** - Retired instructions -** -** Make sure to instantiate cv32e40x_wrapper with the parameter -** NUM_MHPMCOUNTERS = 1 (or higher) -** -******************************************************************************* -*/ - -#include -#include -#include - -#define MAX_STALL_CYCLES 5 - -static int chck(unsigned int is, unsigned int should) -{ - int err; - err = is == should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -static int chck_le(unsigned int is, unsigned int should) -{ - int err; - err = is <= should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -static int chck_with_pos_margin(unsigned int is, unsigned int should, unsigned int margin) -{ - int err; - err = (is >= should) && (is <= should + margin) ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -int main(int argc, char *argv[]) -{ - int err_cnt = 0; - - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - volatile unsigned int event; - volatile unsigned int count; - volatile unsigned int minstret; - volatile unsigned int count_while_on; - - volatile unsigned int mcycle_count; - - __asm__ volatile(".option rvc"); - - ////////////////////////////////////////////////////////////// - // Cycle count - printf("\nCycle count"); - - // Setup events and set csrs to 0 - event = EVENT_CYCLES; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB00, 0x0"); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - - // Readback Counter to verify 0 - __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - printf("\nCheck proper zeroization\n"); - err_cnt += chck(minstret, 0); - err_cnt += chck(count, 0); - err_cnt += chck(count, mcycle_count); - - // Enable counters - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("csrr t0, minstret\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_count)); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - printf("\nCycle count while running = %d", count); - printf("\nMCYCLE counted cycles = %d\n", mcycle_count); - err_cnt += chck(count, mcycle_count); - err_cnt += chck_with_pos_margin(count, 6, 4*MAX_STALL_CYCLES); - - ////////////////////////////////////////////////////////////// - // IF_INVALID - printf("\nIF_INVALID"); - - event = EVENT_IF_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("addi t1, x0, 0\n\t\ - addi t0, x0, 5\n\t\ - branch_target_ifinv_1: addi t1, t1, 1\n\t\ - bne t0, t1, branch_target_ifinv_1\n\t\ - nop" \ - : : : "t0", "t1"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4+(2*5)); - printf("\nUnderutilized cycles on ID-stage due to IF stage = %d\n", count); - - err_cnt += chck_with_pos_margin(count, 4, (4 /*non looped*/ + - 5 /*looped addi*/ + - 4*2 /*taken branches, potenially misaligned*/ + - 2 /*non-taken, potentially misaligned*/)*MAX_STALL_CYCLES); - - ////////////////////////////////////////////////////////////// - // ID_INVALID - LD_STALL - printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("lw x4, 0(sp)\n\t\ - addi x5, x4, 1\n\t\ - lw x6, 0(sp)\n\t\ - addi x7, x0, 1" \ - : : : "x4", "x5", "x6", "x7"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck_with_pos_margin(count, 2, 5*MAX_STALL_CYCLES); - - ////////////////////////////////////////////////////////////// - // ID_INVALID - JR STALL - printf("\nID_INVALID"); - event = EVENT_ID_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("auipc x4, 0\n\t\ - jalr x0, x4, 8\n\t\ - nop" \ - : : : "x4"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - printf("\nUnderutilized cycles on EX-stage due to ID stage = %d\n", count); - err_cnt += chck_with_pos_margin(count, 3, 4*MAX_STALL_CYCLES); - - ////////////////////////////////////////////////////////////// - // EX_INVALID - printf("\nEX_INVALID"); - event = EVENT_EX_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); - - __asm__ volatile("csrwi 0xB02, 0x0"); - __asm__ volatile("csrwi 0xB03, 0x0"); - __asm__ volatile("csrwi 0x320, 0x0"); - - __asm__ volatile("lw x0, 0(x0)"); - __asm__ volatile("lw x31, 0(x31)"); - __asm__ volatile("lw x30, 0(x30)"); - __asm__ volatile("lw x29, 0(x29)"); - __asm__ volatile("lw x28, 0(x28)"); - __asm__ volatile("mulh x0, x0, x0"); // 3 cycles - __asm__ volatile("li x31, 4"); - __asm__ volatile("li x30, 3"); - __asm__ volatile("mulh x0, x31, x30"); // 3 cycles - __asm__ volatile("li x31, 9"); - __asm__ volatile("li x30, 7");; - __asm__ volatile("mulh x0, x31, x30"); // 3 cycles - __asm__ volatile("li x31, 47"); - __asm__ volatile("li x30, 17"); - __asm__ volatile("div x0, x31, x30"); // 32 cycles - __asm__ volatile("li x31, 1"); - __asm__ volatile("li x30, 1"); - __asm__ volatile("div x0, x31, x30"); // 32 cycles - __asm__ volatile("rem x0, x31, x30"); // 32 cycles - __asm__ volatile("lw x0, 0(sp)"); - - __asm__ volatile("csrwi 0x320, 0x1F"); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 21); - printf("\nUnderutilized cycles on WB-stage due to EX stage = %d\n", count); - // -6 due to potential random stalls preventing hazard stalls - err_cnt += chck_with_pos_margin(count, 104 - 6, 21*MAX_STALL_CYCLES + 6); - - ////////////////////////////////////////////////////////////// - // WB_INVALID Write port underutilization - - printf("\nWrite port underutilization"); - event = EVENT_WB_INVALID; - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - - __asm__ volatile("li x31, 1\n\t\ - li x30, 1\n\t\ - div x0, x31, x30\n\t\ - lw x29, 0(sp)\n\t\ - sw x29, 0(sp)" \ - : : : "x28", "x29", "x30", "x31"); - - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 6); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck_with_pos_margin(count, 34, 6*MAX_STALL_CYCLES); - - ////////////////////////////////////////////////////////////// - // WB_DATA_STALL Write port underutilization due to data_rvalid_i (0) - printf("\nWrite port underutilization due to data_rvalid_i"); - event = EVENT_WB_DATA_STALL; - - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - - __asm__ volatile("li x31, 7\n\t\ - li x30, 3\n\t\ - addi x0, x31, 1\n\t\ - lw x29, 0(sp)\n\t\ - lw x28, -1(sp)\n\t\ - srli x30, x29, 2\n\t\ - slli x30, x30, 2\n\t\ - xori x30, x30, 1\n\t\ - sw x29, 0(x30)\n\t\ - sw x29, 0(sp)\n\t\ - lw x28, -1(sp)\n\t\ - csrr x29, 0xB00\n\t\ - div x0, x31, x30" \ - : : : "x28", "x29", "x30", "x31"); - - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 14); - printf("\nWrite port underutilization cycles: %d\n", count); - err_cnt += chck_with_pos_margin(count, 3, 14*MAX_STALL_CYCLES); - - ////////////////////////////////////////////////////////////// - // Retired instruction count (0) - Immediate minstret read - printf("\nRetired instruction count (0)"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - - __asm__ volatile("csrr t0, minstret\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on - - printf("\nminstret count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 0); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - ////////////////////////////////////////////////////////////// - // Retired instruction count (1) - minstret read-after-write - printf("\nRetired instruction count (1)"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("csrwi minstret, 0xA\n\t\ - csrr t0, minstret\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0\n\t\ - nop" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // - - printf("\nminstret count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 0xA); - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 0xF); - - ////////////////////////////////////////////////////////////// - // Retired instruction count (2) - printf("\nRetired instruction count (2)"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)\n\t\ - addi t0, x0, 5\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0\n\t\ - lw t2, 0(sp)\n\t\ - branch_target: addi t2, t2, 1\n\t\ - addi t1, t1, 1\n\t\ - lw t2, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - bne t0, t1, branch_target\n\t\ - j jump_target\n\t\ - lw t2, 0(sp)\n\t\ - lw t2, 0(sp)\n\t\ - jump_target: nop\n\t\ - nop\n\t\ - nop" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5 + 6*5 + 4 + 1); - - ////////////////////////////////////////////////////////////// - // Count load use hazards - printf("\nCount load use hazards"); - - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x4, 0(sp)\n\t\ - addi x5, x4, 1\n\t\ - lw x6, 0(sp)\n\t\ - addi x7, x0, 1" \ - : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load use hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Hazard count is 0 or 1 (0 if due to instruction interface stalls 'use' did not closely follow the load) - - ////////////////////////////////////////////////////////////// - // Count jump register hazards - printf("\nCount Jump register hazards"); - - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0" \ - : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Jump register hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Hazard count is 0 or 1 (0 if due to instruction interface stalls jalr did not closely follow the addi before it) - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - Read while enabled - printf("\nCount memory read transactions (0)"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x0, 0(sp)\n\t\ - csrr t0, mhpmcounter3\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load count while running = %d\n", count_while_on); - err_cnt += chck(count_while_on, 1); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 1); - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - Write after load event - printf("\nCount memory read transactions (1)"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x0, 0(sp)\n\t\ - csrwi mhpmcounter3, 0xA\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - __asm__ volatile("addi %0, t0, 0" : "=r"(count_while_on)); // count_while_on - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 0xA); - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - printf("\nCount memory read transactions (2)"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x0, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("j jump_target_memread"); // do not count jump in mphmevent3 - __asm__ volatile("nop"); // do not count nop in instret - __asm__ volatile("jump_target_memread:"); - __asm__ volatile("lw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count memory write transactions - printf("\nCount memory write transactions"); - - event = EVENT_DATA_WRITE; // Trigger on stores - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Store count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count jumps - printf("\nCount jumps"); - - event = EVENT_JUMP; // Trigger on jumps - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("j jump_target_0"); // count++ - __asm__ volatile("jump_target_0:"); - __asm__ volatile("j jump_target_1"); // count++ - __asm__ volatile("jump_target_1:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 3); - - printf("Jump count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count branches (conditional) - printf("\nCount branches (conditional)"); - - event = EVENT_BRANCH; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_0"); // count++ - __asm__ volatile("branch_target_0:"); - __asm__ volatile("bne x0, x0, branch_target_1"); // count++ - __asm__ volatile("branch_target_1:"); - __asm__ volatile("beq x0, x0, branch_target_2"); // count++ - __asm__ volatile("branch_target_2:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Branch count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Count branches taken (conditional) - printf("\nCount branches taken (conditional)"); - - event = EVENT_BRANCH_TAKEN; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_3"); // count++ - __asm__ volatile("branch_target_3:"); - __asm__ volatile("bne x0, x0, branch_target_4"); // (not taken) - __asm__ volatile("branch_target_4:"); - __asm__ volatile("beq x0, x0, branch_target_5"); // count++ - __asm__ volatile("branch_target_5:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Branch taken count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Compressed instructions - printf("\nCompressed instructions"); - - event = EVENT_COMP_INSTR; // Trigger on compressed instructions - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("c.addi x15, 1\n\t\ - c.nop\n\t\ - c.addi x15, 1" \ - : : : "x15"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Compressed count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Check for errors - printf("\nDone\n\n"); - - if (err_cnt) - printf("FAILURE. %d errors\n\n", err_cnt); - else - printf("SUCCESS\n\n"); - - return err_cnt; -} diff --git a/cv32e40x/tests/programs/custom/hpmcounter_basic_test/test.yaml b/cv32e40x/tests/programs/custom/hpmcounter_basic_test/test.yaml deleted file mode 100644 index fbaa7aa57f..0000000000 --- a/cv32e40x/tests/programs/custom/hpmcounter_basic_test/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: hpmcounter_basic_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - HPM Counter Basic Test (donated by Arjan Bink) diff --git a/cv32e40x/tests/programs/custom/hpmcounter_hazard_test/hpmcounter_hazard_test.c b/cv32e40x/tests/programs/custom/hpmcounter_hazard_test/hpmcounter_hazard_test.c deleted file mode 100644 index b7a6ee2726..0000000000 --- a/cv32e40x/tests/programs/custom/hpmcounter_hazard_test/hpmcounter_hazard_test.c +++ /dev/null @@ -1,148 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -** SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -** -******************************************************************************* -** -** Performance counter directed test -** -** Very basic sanity check for: -** -** - Count load use hazards -** - Count jump register hazards -** -** Make sure to instantiate cv32e40x_wrapper with the parameter -** NUM_MHPMCOUNTERS = 1 (or higher) -** -** Make sure to only run this test without wait states on instr_gnt_i/ -** instr_rvalid_i. The test should tolerate wait states on data_gnt_i/ -** data_rvalid_i. -** -******************************************************************************* -*/ - -#include -#include -#include - -static int chck(unsigned int is, unsigned int should) -{ - int err; - err = is == should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -static int chck_le(unsigned int is, unsigned int should) -{ - int err; - err = is <= should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -int main(int argc, char *argv[]) -{ - int err_cnt = 0; - - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - volatile unsigned int event; - volatile unsigned int count; - volatile unsigned int minstret; - - __asm__ volatile(".option rvc"); - - ////////////////////////////////////////////////////////////// - // Count load use hazards - printf("\nCount load use hazards"); - - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x4, 0(sp)\n\t\ - addi x5, x4, 1\n\t\ - lw x6, 0(sp)\n\t\ - addi x7, x0, 1" \ - : : : "x4", "x5", "x6", "x7"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 5); - - printf("Load use hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Interface stalls can cause this to be 0, otherwise 1 - - ////////////////////////////////////////////////////////////// - // Count jump register hazards - printf("\nCount Jump register hazards"); - - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " :: "r"(event)); // Set mphmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x28, x4, 0x0" \ - : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret); - err_cnt += chck(minstret, 4); - - printf("Jump register hazards count = %d\n", count); - err_cnt += chck_le(count, 1); // Interface stalls can cause this to be 0, otherwise 1 - - ////////////////////////////////////////////////////////////// - // Check for errors - printf("\nDone"); - - if (err_cnt) - printf("FAILURE. %d errors\n\n", err_cnt); - else - printf("SUCCESS\n\n"); - - return err_cnt; -} diff --git a/cv32e40x/tests/programs/custom/hpmcounter_hazard_test/test.yaml b/cv32e40x/tests/programs/custom/hpmcounter_hazard_test/test.yaml deleted file mode 100644 index 2c041e9318..0000000000 --- a/cv32e40x/tests/programs/custom/hpmcounter_hazard_test/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: hpmcounter_hazard_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - HPM Counter Hazard Test (donated by Arjan Bink) diff --git a/cv32e40x/tests/programs/custom/illegal/illegal.c b/cv32e40x/tests/programs/custom/illegal/illegal.c deleted file mode 100644 index 544dab1e8a..0000000000 --- a/cv32e40x/tests/programs/custom/illegal/illegal.c +++ /dev/null @@ -1,42 +0,0 @@ -#include -#include - -// This is an illegal instruction that is not decodable (in the C extension space) -static void illegalCExtOP() { - asm(".short 0x9e41 \n"); - return; -} - -// This is a decodable instruction with an illegal field (rd == 0 in c.addi4spn) -void illegalCExtRdOP() { - asm(".short 0x0000 \n"); - return; -} - -// This is a decodable instruction with an illegal CSR -void illegalCSROP() { - asm volatile("csrr x0, 0x20"); - return; -} - -// This is a decodable instruction in the B extension -void illegalBExtOP() { - asm volatile(".word 0x601e9f13"); -} - -int main () { - printf("Generate an undecodable C extension instruction\n"); - illegalCExtOP(); - - printf("Generate a decoded but illegal C extension instruction\n"); - illegalCExtRdOP(); - - printf("Generate a decoded CSR operation with invalid CSR\n"); - illegalCSROP(); - - printf("Generate a decoded B extension that is unsupported\n"); - illegalBExtOP(); - - printf("Complete illegal instruction - unreachable\n"); - fflush(0); -} diff --git a/cv32e40x/tests/programs/custom/illegal/test.yaml b/cv32e40x/tests/programs/custom/illegal/test.yaml deleted file mode 100644 index 5b58308bd3..0000000000 --- a/cv32e40x/tests/programs/custom/illegal/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: illegal -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Illegal instruction directed test diff --git a/cv32e40x/tests/programs/custom/illegal_instr_test/illegal_instr_test.S b/cv32e40x/tests/programs/custom/illegal_instr_test/illegal_instr_test.S deleted file mode 100644 index d3c7fe83f1..0000000000 --- a/cv32e40x/tests/programs/custom/illegal_instr_test/illegal_instr_test.S +++ /dev/null @@ -1,47829 +0,0 @@ -# -# Copyright (C) EM Microelectronic US Inc. -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. -# -# See the License for the specific language governing permissions and -# limitations under the License. -# -#include "corev_uvmt.h" - -.globl _start -.globl main -.globl exit -.global debug -.section .text -.global test_results -.global u_sw_irq_handler - -test_results: - .word 123456789 - -main: - li t0, (0x1 << 3) - csrs mstatus, t0 - li x5, 0x0 - li x6, 0x6 - li x7, 0x7 - li x8, 0x8 - li x9, 0x9 - li x10, 0xa - li x11, 0xb - li x12, 0xc - li x13, 0xd - li x14, 0xe - li x15, 0xf - li x16, 0x10 - li x17, 0x11 - li x18, 0x12 - li x19, 0x13 - li x20, 0x14 - li x21, 0x15 - li x22, 0x16 - li x23, 0x17 - li x24, 0x18 - li x25, 0x19 - li x28, 0x1c - li x29, 0x1d - li x30, 0x1e - li x31, 0x0 - jal test_bitmanip - jal push_volatile_gpr_stack -.word(0x9d5b136b) -.word(0xfed5cfcb) -.word(0x3d65f2b3) -.word(0xf079c787) -.word(0xbc16c753) -.word(0xe36a5c33) -.word(0xd3208ed3) -.word(0xfd9a7d3b) -.word(0x662e1ed3) -.word(0x43808ca7) -.word(0x53f0dd1b) -.word(0xb031f62b) -.word(0xb1553fb3) -.word(0xb88617af) -.word(0xb92c10e7) -.word(0x6700f3cf) -.word(0x4148b723) -.word(0x33ba9193) -.word(0x2a5ca89b) -.word(0x583af4ab) -.word(0x7d107c23) -.word(0x97710b2f) -.word(0x2be57b87) -.word(0xc0cfe507) -.word(0x3a9aacfb) -.word(0x86a8eaeb) -.word(0x6057e6e7) -.word(0x7618db67) -.word(0x2be76dd3) -.word(0x72e54607) -.word(0xe72b7ad3) -.word(0x5b211433) -.word(0xb7b57d7b) -.word(0xecce38e7) -.word(0x1faf7023) -.word(0x8e6d6cab) -.word(0x34e854af) -.word(0x7e3c6643) -.word(0xff4c4153) -.word(0x3ab32867) -.word(0xd37fcd1b) -.word(0x76f9d04f) -.word(0xe7215207) -.word(0xfe8c8ebb) -.word(0xdea2a36b) -.word(0xa00f5a27) -.word(0x119d3aab) -.word(0x2c28a7fb) -.word(0xea126677) -.word(0x5236657b) -.word(0x7edb1c27) -.word(0xb51a36f7) -.word(0x3c232f2f) -.word(0x496a3477) -.word(0x436f607b) -.word(0x9377f3e7) -.word(0x624ad507) -.word(0x214f4fa3) -.word(0x977ae907) -.word(0xaadc0c07) -.word(0x97d2243b) -.word(0xa1b7e87b) -.word(0x058fdb77) -.word(0x5637944f) -.word(0xc42335db) -.word(0x71d5370b) -.word(0xd0cf07a7) -.word(0x95ad67a3) -.word(0x94c132d7) -.word(0xf747df2f) -.word(0xbbcfff6b) -.word(0xe126196b) -.word(0x1fc81b4b) -.word(0xd8dad76b) -.word(0x06f35e6b) -.word(0x8c533cab) -.word(0xf60c57ab) -.word(0x4fcad3ab) -.word(0x4d7231ab) -.word(0x72088ceb) -.word(0x78d14b53) -.word(0x51544467) -.word(0xc7cdf6af) -.word(0x3aceec2f) -.word(0x44b6b28b) -.word(0x6ae9dcb3) -.word(0xccfcfc2f) -.word(0x16f25ed3) -.word(0x63887ed3) -.word(0x52f3b5ab) -.word(0x08936627) -.word(0x2c40559b) -.word(0xbe1984cb) -.word(0xf82923db) -.word(0x7103be2f) -.word(0x39c4a66b) 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-.word(0x0c50ca2f) -.word(0xf8212b9b) -.word(0x69ac8807) -.word(0xd877f77b) -.word(0x3cf58cf7) -.word(0xd1e39127) -.word(0x30e142ab) -.word(0xc64368d7) -# manually added ill-formed fence instructions -.word(0x0000200f) -.word(0x0000300f) -.word(0x0000400f) -.word(0x0000500f) -.word(0x0000600f) -.word(0x0000700f) -# manually added ill-formed branch instructions -.word(0x00002063) -.word(0x00003063) -.word(0x000020e3) -.word(0x000030e3) -# manually added PULP instructions that are interrupts as illegal when PULP_XPULP=0 -.word(0x42000033) -.word(0x42001033) -.word(0x04002033) -.word(0x04003033) -.word(0x04004033) -.word(0x04005033) -.word(0x04006033) -.word(0x04007033) -.word(0x08005033) - nop -.word(0x14001033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x14002033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x14006033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x14005033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x15001033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x15002033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x15005033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x15006033) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x140010B3) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x140020B3) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x140050B3) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x140060B3) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x150010B3) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x150020B3) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x150060B3) # p.clipr [31:25]==000_1010, [6:0]==011_0011 - nop -.word(0x05000033) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - nop -.word(0x050000B3) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - nop -.word(0x04000033) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - nop -.word(0x040000B3) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - nop -.word(0x05008033) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - nop -.word(0x050080B3) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - nop -.word(0x04008033) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - nop -.word(0x040080B3) # p.abs [31:25]==000_0010, [14:12]==000, [6:0]==011_0011 - - jal check_gpr_integrity -finalize: - li x18, 123456789 - li x19, 0xa55a5aa5 - lw x20,-8(sp) # Attempt to get bitmanip enabled-signature - beq x20,x19,set_exp_bitmanip - li x16, 47595 # This is the number of EXPECTED illegal instructions - beq x31, x16, test_end - j fail -set_exp_bitmanip: - li x16, 47518 # This is the number of EXPECTED instructions if Zba,Zbb,Zbc and Zbs are enabled - beq x31, x16, test_end -fail: - li x18, 1 -test_end: - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - j _exit - -push_volatile_gpr_stack: - addi sp,sp,-92 - sw x3,88(sp) - sw x4,84(sp) - sw x7,76(sp) - sw x8,72(sp) - sw x9,68(sp) - sw x10,64(sp) - sw x11,60(sp) - sw x12,56(sp) - sw x13,52(sp) - sw x14,48(sp) - sw x15,44(sp) - sw x16,40(sp) - sw x17,36(sp) - sw x18,32(sp) - sw x19,28(sp) - sw x20,24(sp) - sw x21,20(sp) - sw x22,16(sp) - sw x23,12(sp) - sw x24,8(sp) - sw x25,4(sp) - ret - -restore_volatile_gpr_stack: - lw x3,88(sp) - lw x4,84(sp) - lw x6,80(sp) - lw x7,76(sp) - lw x8,72(sp) - lw x9,68(sp) - lw x10,64(sp) - lw x11,60(sp) - lw x12,56(sp) - lw x13,52(sp) - lw x14,48(sp) - lw x15,44(sp) - lw x16,40(sp) - lw x17,36(sp) - lw x18,32(sp) - lw x19,28(sp) - lw x20,24(sp) - lw x21,20(sp) - lw x22,16(sp) - lw x23,12(sp) - lw x24,8(sp) - lw x25,4(sp) - addi sp,sp,92 - ret - -check_gpr_integrity: - // The first two are deliberately not checked but popped for consistency - lw x5,88(sp) - lw x5,84(sp) - lw x5,80(sp) - bne x5, x6, fail - lw x5,76(sp) - bne x5, x7, fail - lw x5,72(sp) - bne x5, x8, fail - lw x5,68(sp) - bne x5, x9, fail - lw x5,64(sp) - bne x5, x10, fail - lw x5,60(sp) - bne x5, x11, fail - lw x5,56(sp) - bne x5, x12, fail - lw x5,52(sp) - bne x5, x13, fail - lw x5,48(sp) - bne x5, x14, fail - lw x5,44(sp) - bne x5, x15, fail - lw x5,40(sp) - bne x5, x16, fail - lw x5,36(sp) - bne x5, x17, fail - lw x5,32(sp) - bne x5, x18, fail - lw x5,28(sp) - bne x5, x19, fail - lw x5,24(sp) - bne x5, x20, fail - lw x5,20(sp) - bne x5, x21, fail - lw x5,16(sp) - bne x5, x22, fail - lw x5,12(sp) - bne x5, x23, fail - lw x5,8(sp) - bne x5, x24, fail - lw x5,4(sp) - bne x5, x25, fail - addi sp,sp,92 - ret - -test_bitmanip: - add x3, x1, zero // backup return address - jal push_volatile_gpr_stack - .word(0x612ed793) // Zbb rori - .word(0x4088e233) // Zbb orn - .word(0x0a9e15b3) // Zbc clmul - .word(0x411f61b3) // Zbb orn - .word(0x0b8bbd33) // Zbc clmulh - .word(0x485b5733) // Zbs bext - .word(0x6174ddb3) // Zbb ror - .word(0x69e11d93) // Zbs binvi - .word(0x69041db3) // Zbs binv - .word(0x28ef9093) // Zbs bseti - .word(0x6108d693) // Zbb rori - .word(0x49031f13) // Zbs bclri - .word(0x29ab9db3) // Zbs bset - .word(0x6089d413) // Zbb rori - .word(0x0a202d33) // Zbc clmulr - .word(0x0a5393b3) // Zbc clmul - .word(0x48eb9293) // Zbs bclri - .word(0x48849613) // Zbs bclri - .word(0x60355893) // Zbb rori - .word(0x40fd7e33) // Zbb andn - .word(0x600b1793) // Zbb clz - .word(0x48085c33) // Zbs bext - .word(0x21b1c833) // Zba sh2add - .word(0x207fe233) // Zba sh3add - .word(0x48d59eb3) // Zbs bclr - .word(0x0a0c2a33) // Zbc clmulr - .word(0x29139693) // Zbs bseti - .word(0x492a9c93) // Zbs bclri - .word(0x40c3fdb3) // Zbb andn - .word(0x40756233) // Zbb orn - .word(0x492ad313) // Zbs bexti - .word(0x48535833) // Zbs bext - .word(0x214840b3) // Zba sh2add - .word(0x494cd493) // Zbs bexti - .word(0x219963b3) // Zba sh3add - .word(0x0af1b3b3) // Zbc clmulh - .word(0x40234433) // Zbb xnor - .word(0x20836cb3) // Zba sh3add - .word(0x0a099e33) // Zbc clmul - .word(0x20e86233) // Zba sh3add - .word(0x21e1e5b3) // Zba sh3add - .word(0x0ac23233) // Zbc clmulh - .word(0x20c0a333) // Zba sh1add - .word(0x49b5df33) // Zbs bext - .word(0x408b7533) // Zbb andn - .word(0x0a5e3933) // Zbc clmulh - .word(0x61b591b3) // Zbb rol - .word(0x0bad5d33) // Zbb minu - .word(0x40f5fcb3) // Zbb andn - .word(0x407342b3) // Zbb xnor - .word(0x203dc9b3) // Zba sh2add - .word(0x60e45633) // Zbb ror - .word(0x49305a93) // Zbs bexti - .word(0x0a1537b3) // Zbc clmulh - .word(0x0aa1ef33) // Zbb max - .word(0x692f92b3) // Zbs binv - .word(0x0b0d5e33) // Zbb minu - .word(0x0bd49a33) // Zbc clmul - .word(0x48da5233) // Zbs bext - .word(0x2177c1b3) // Zba sh2add - .word(0x61cb5c93) // Zbb rori - .word(0x21a2e433) // Zba sh3add - .word(0x41f8f8b3) // Zbb andn - .word(0x29ce18b3) // Zbs bset - .word(0x284a1193) // Zbs bseti - .word(0x0bffc233) // Zbb min - .word(0x0bda4533) // Zbb min - .word(0x0b59a333) // Zbc clmulr - .word(0x402e60b3) // Zbb orn - .word(0x2024abb3) // Zba sh1add - .word(0x0afe5db3) // Zbb minu - .word(0x409d63b3) // Zbb orn - .word(0x499cd093) // Zbs bexti - .word(0x0b646433) // Zbb max - .word(0x49a99d33) // Zbs bclr - .word(0x0a5eff33) // Zbb maxu - .word(0x68779c93) // Zbs binvi - li x16, 77 - beq x31, x16, return_to_main // jump if we encountered 77 invalid (bitmanip) instructions) - li x4, 0xa55a5aa5 - sw x4,84(sp) - j return_to_main -return_to_main: - jal restore_volatile_gpr_stack - add x1, x3, zero // restore return address - ret - -u_sw_irq_handler: - li x30, 0xf - csrrc x29, mcause, x0 - and x30, x29, x30 - li x28, 2 - bne x30, x28, _exit - csrrc x27, mepc, x0 - c.addi x27, 4 - csrrw x0, mepc, x27 - c.addi x31, 1 - mret - -_exit: - j _exit - -debug: - j _exit diff --git a/cv32e40x/tests/programs/custom/illegal_instr_test/test.yaml b/cv32e40x/tests/programs/custom/illegal_instr_test/test.yaml deleted file mode 100644 index 9e68dafb5d..0000000000 --- a/cv32e40x/tests/programs/custom/illegal_instr_test/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Test definition YAML for test - -name: illegal_instr_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Script-generated test contributed by em-micro to exercise all (?) illegal instruction types diff --git a/cv32e40x/tests/programs/custom/instr_bus_error/instr_bus_error.c b/cv32e40x/tests/programs/custom/instr_bus_error/instr_bus_error.c deleted file mode 100644 index c24522edc5..0000000000 --- a/cv32e40x/tests/programs/custom/instr_bus_error/instr_bus_error.c +++ /dev/null @@ -1,179 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Basic turnon test for instruction bus faults (errors on OBI-I fetch) -** -******************************************************************************* -*/ - -#include -#include -#include "corev_uvmt.h" - -#define TEST_LOOPS 6 - -// Globals -volatile uint32_t bus_fault_count = 0; -volatile uint32_t bus_fault_count_exp = 3; - -// Special handler for instruction bus faults -void handle_insn_bus_fault(void) { - if (++bus_fault_count == bus_fault_count_exp) { - *CV_VP_OBI_SLV_RESP_I_ERR_VALID = 0; - - asm volatile("fence"); - } - - asm volatile("j end_handler_ret"); -} - -// Test function where first "word-aligned" instruction will be tested -__attribute__((aligned(4))) -void bus_error_func_word_align() { - printf("In the word-aligned bus error func\n"); -} - -// Test function where first "word-aligned" instruction will be tested -__attribute__((aligned(4))) -void bus_error_func_halfword_align() { - asm volatile("c.addi x0,0"); - asm volatile("c.addi x0,0"); - printf("In the halfword-aligned bus error func\n"); -} - -// This is a dummy function to exercise bus errors in the prefetcher to ensure they do not -// propagate to faults. The caller of this function should setup a bus error to occur 4 instructions -// beyond the end of this function. OBI should see the error but the caller should ensure no -// bus faults are seen (via the handler counter) -__attribute__((aligned(4))) -void bus_error_prefetch_func() { - asm volatile("addi x0,x20,0"); - asm volatile("addi x0,x20,0"); - asm volatile("addi x0,x20,0"); -} - -int test_word_aligned_i_error() { - // Call initially without error injection - bus_error_func_word_align(); - - if (bus_fault_count != 0) { - printf("test_word_aligned_i_error(): Received instruction bus faults before injecting\n"); - return EXIT_FAILURE; - } - - // Inject errors via OBI VP and call function - bus_fault_count_exp = 4; - *CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MIN = (uint32_t) bus_error_func_word_align; - *CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MAX = (uint32_t) bus_error_func_word_align; - *CV_VP_OBI_SLV_RESP_I_ERR_VALID = 1; - asm volatile("fence"); - - bus_error_func_word_align(); - - // Verify we received number of faults - if (bus_fault_count != bus_fault_count_exp) { - printf("test_word_aligned_i_error(): Only recevied %lu bus faults, expected %lu\n", bus_fault_count, bus_fault_count_exp); - return EXIT_FAILURE; - } - - bus_fault_count = 0; - - return EXIT_SUCCESS; -} - -int test_halfword_aligned_i_error() { - // Create a new function pointer to point to 1 compressed instruction after - // start of bus_error_func_halfword_align() - void (*bus_error_func_halfword_align_p2)(void) = ((uint32_t) bus_error_func_halfword_align) + 2; - - // Call initially without error injection - (*bus_error_func_halfword_align_p2)(); - - if (bus_fault_count != 0) { - printf("test_halfword_aligned_i_error(): Received instruction bus faults before injecting\n"); - return EXIT_FAILURE; - } - - // Inject errors via OBI VP and call function - bus_fault_count_exp = 5; - *CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MIN = (uint32_t) bus_error_func_halfword_align; - *CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MAX = (uint32_t) bus_error_func_halfword_align; - *CV_VP_OBI_SLV_RESP_I_ERR_VALID = 1; - asm volatile("fence"); - - (*bus_error_func_halfword_align_p2)(); - - // Verify we received number of faults - if (bus_fault_count != bus_fault_count_exp) { - printf("test_halfword_aligned_i_error(): Only recevied %lu bus faults, expected %lu\n", bus_fault_count, bus_fault_count_exp); - return EXIT_FAILURE; - } - - bus_fault_count = 0; - - return EXIT_SUCCESS; -} - -int test_prefetch_i_error() { - - if (bus_fault_count != 0) { - printf("test_prefetch_i_error(): Received instruction bus faults before injecting\n"); - - return EXIT_FAILURE; - } - - // Seed an OBI I error one instruciton past the end of bus_error_prefetch_func (it should contain 4 32-bit instructions) - *CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MIN = ((uint32_t) bus_error_prefetch_func) + 4 * 4; - *CV_VP_OBI_SLV_RESP_I_ERR_ADDR_MAX = ((uint32_t) bus_error_prefetch_func) + 4 * 4; - *CV_VP_OBI_SLV_RESP_I_ERR_VALID = 1; - - bus_fault_count_exp = 1; - bus_error_prefetch_func(); - - if (bus_fault_count != 0) { - printf("test_prefetch_i_error(): Received instruction bus faults on a prefetched but not executed instruction\n"); - - return EXIT_FAILURE; - } - - *CV_VP_OBI_SLV_RESP_I_ERR_VALID = 0; - - return EXIT_SUCCESS; -} - -int main(int argc, char *argv[]) { - printf("Start instr_bus_error test\n"); - - for (int i = 0; i < TEST_LOOPS; i++) { - if (test_word_aligned_i_error() != EXIT_SUCCESS) { - return EXIT_FAILURE; - } - - if (test_halfword_aligned_i_error() != EXIT_SUCCESS) { - return EXIT_FAILURE; - } - - if (test_prefetch_i_error() != EXIT_SUCCESS) { - return EXIT_FAILURE; - } - } - - return EXIT_SUCCESS; -} - - diff --git a/cv32e40x/tests/programs/custom/instr_bus_error/test.yaml b/cv32e40x/tests/programs/custom/instr_bus_error/test.yaml deleted file mode 100644 index 975c2b87a0..0000000000 --- a/cv32e40x/tests/programs/custom/instr_bus_error/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: instr_bus_error -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Directed bus error test diff --git a/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.S b/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.S deleted file mode 100644 index b757411076..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.S +++ /dev/null @@ -1,101 +0,0 @@ -/* Make sure the vector table gets linked into the binary. */ -.global vector_table - -/* Entry point for bare metal programs */ -.section .text.start -.global _start -.type _start, @function - -_start: -/* initialize global pointer */ -.option push -.option norelax -1: auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) -.option pop - -/* initialize stack pointer */ - la sp, __stack_end - -/* clear the bss segment */ - la a0, _edata - la a2, _end - sub a2, a2, a0 - li a1, 0 - call memset - -/* new-style constructors and destructors */ - la a0, __libc_fini_array - call atexit - call __libc_init_array - -/* call main */ -// lw a0, 0(sp) /* a0 = argc */ -// addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ -// li a2, 0 /* a2 = envp = NULL */ -// Initialize these variables to 0. Cannot use argc or argv -// since the stack is not initialized - li a0, 0 - li a1, 0 - li a2, 0 - - call main - tail exit - -.size _start, .-_start - -.global _init -.type _init, @function -.global _fini -.type _fini, @function -_init: -_fini: - /* These don't have to do anything since we use init_array/fini_array. Prevent - missing symbol error */ - ret -.size _init, .-_init -.size _fini, .-_fini - - -// Custom alternate vector table to load at interrupt boostrap address -.section .vectors.alt, "ax" - -.global alt_vector_table -.option norvc -.align 8 - -alt_vector_table: - - j u_sw_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_software_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_timer_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_external_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j m_fast0_irq_handler - j m_fast1_irq_handler - j m_fast2_irq_handler - j m_fast3_irq_handler - j m_fast4_irq_handler - j m_fast5_irq_handler - j m_fast6_irq_handler - j m_fast7_irq_handler - j m_fast8_irq_handler - j m_fast9_irq_handler - j m_fast10_irq_handler - j m_fast11_irq_handler - j m_fast12_irq_handler - j m_fast13_irq_handler - j m_fast14_irq_handler - j m_fast15_irq_handler - diff --git a/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c b/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c deleted file mode 100644 index 4f8b1465ba..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_bootstrap.c +++ /dev/null @@ -1,290 +0,0 @@ -#include -#include -#include -#include - -#include "interrupt_test.h" - -// There is no way to commnicate UVM side information to firmware currently -// so use a fixed value for moving mtvec -// This should be safely away from the code area and yet safely "down" the stack area -#define BOOTSTRAP_MTVEC 0x00000200 - -volatile uint32_t irq_id = 0; -volatile uint32_t irq_id_q[IRQ_NUM]; -volatile uint32_t irq_id_q_ptr = 0; -volatile uint32_t mmcause = 0; -volatile uint32_t active_test = 0; -volatile uint32_t nested_irq = 0; -volatile uint32_t nested_irq_valid = 0; -volatile uint32_t in_direct_handler = 0; - -uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { - FAST15_IRQ_ID , - FAST14_IRQ_ID , - FAST13_IRQ_ID , - FAST12_IRQ_ID , - FAST11_IRQ_ID , - FAST10_IRQ_ID , - FAST9_IRQ_ID , - FAST8_IRQ_ID , - FAST7_IRQ_ID , - FAST6_IRQ_ID , - FAST5_IRQ_ID , - FAST4_IRQ_ID , - FAST3_IRQ_ID , - FAST2_IRQ_ID , - FAST1_IRQ_ID , - FAST0_IRQ_ID , - EXTERNAL_IRQ_ID , - SOFTWARE_IRQ_ID , - TIMER_IRQ_ID -}; - -void delay(int count) { - for (volatile int d = 0; d < count; d++); -} - -void mstatus_mie_enable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - __asm__ volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mstatus_mie_disable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - __asm__ volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mie_enable_all() { - uint32_t mie_mask = (uint32_t) -1; - __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_disable_all() { - uint32_t mie_mask = (uint32_t) -1; - __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_enable(uint32_t irq) { - // Enable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - __asm__ volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); -} - -void mie_disable(uint32_t irq) { - // Disable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - __asm__ volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); -} - -void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { - *TIMER_REG_ADDR = mask; - *TIMER_VAL_ADDR = 1 + cycle_delay; -} - -uint32_t random_num(uint32_t upper_bound, uint32_t lower_bound) { - uint32_t random_num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); - uint32_t num = (random_num % (upper_bound - lower_bound + 1)) + lower_bound; - return num; -} - -uint32_t random_num32() { - uint32_t num = *((volatile int *)CV_VP_RANDOM_NUM_BASE); - return num; -} - -extern void __no_irq_handler(); - -void nested_irq_handler(uint32_t id) { - // First stack mie, mepc and mstatus - // Must be done in critical section with MSTATUS.MIE == 0 - volatile uint32_t mie, mepc, mstatus; - __asm__ volatile("csrr %0, mie" : "=r" (mie)); - __asm__ volatile("csrr %0, mepc" :"=r" (mepc)); - __asm__ volatile("csrr %0, mstatus" : "=r" (mstatus)); - - // Re enable interrupts and create window to enable nested irqs - mstatus_mie_enable(); - for (volatile int i = 0; i < 20; i++); - - // Disable MSTATUS.MIE and restore from critical section - mstatus_mie_disable(); - __asm__ volatile("csrw mie, %0" : : "r" (mie)); - __asm__ volatile("csrw mepc, %0" : : "r" (mepc)); - __asm__ volatile("csrw mstatus, %0" : : "r" (mstatus)); -} - -void generic_irq_handler(uint32_t id) { - __asm__ volatile("csrr %0, mcause": "=r" (mmcause)); - irq_id = id; - - if (active_test == 2 || active_test == 3 || active_test == 4) { - irq_id_q[irq_id_q_ptr++] = id; - } - if (active_test == 3) { - if (nested_irq_valid) { - nested_irq_valid = 0; - mm_ram_assert_irq(0x1 << nested_irq, random_num(10,0)); - } - nested_irq_handler(id); - } -} - -void m_software_irq_handler(void) { generic_irq_handler(SOFTWARE_IRQ_ID); } -void m_timer_irq_handler(void) { generic_irq_handler(TIMER_IRQ_ID); } -void m_external_irq_handler(void) { generic_irq_handler(EXTERNAL_IRQ_ID); } -void m_fast0_irq_handler(void) { generic_irq_handler(FAST0_IRQ_ID); } -void m_fast1_irq_handler(void) { generic_irq_handler(FAST1_IRQ_ID); } -void m_fast2_irq_handler(void) { generic_irq_handler(FAST2_IRQ_ID); } -void m_fast3_irq_handler(void) { generic_irq_handler(FAST3_IRQ_ID); } -void m_fast4_irq_handler(void) { generic_irq_handler(FAST4_IRQ_ID); } -void m_fast5_irq_handler(void) { generic_irq_handler(FAST5_IRQ_ID); } -void m_fast6_irq_handler(void) { generic_irq_handler(FAST6_IRQ_ID); } -void m_fast7_irq_handler(void) { generic_irq_handler(FAST7_IRQ_ID); } -void m_fast8_irq_handler(void) { generic_irq_handler(FAST8_IRQ_ID); } -void m_fast9_irq_handler(void) { generic_irq_handler(FAST9_IRQ_ID); } -void m_fast10_irq_handler(void) { generic_irq_handler(FAST10_IRQ_ID); } -void m_fast11_irq_handler(void) { generic_irq_handler(FAST11_IRQ_ID); } -void m_fast12_irq_handler(void) { generic_irq_handler(FAST12_IRQ_ID); } -void m_fast13_irq_handler(void) { generic_irq_handler(FAST13_IRQ_ID); } -void m_fast14_irq_handler(void) { generic_irq_handler(FAST14_IRQ_ID); } -void m_fast15_irq_handler(void) { generic_irq_handler(FAST15_IRQ_ID); } - -// A Special version of the SW Handler (vector 0) used in the direct mode -__attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void) { - in_direct_handler = 1; - __asm__ volatile("csrr %0, mcause" : "=r" (mmcause)); -} - -int test_mtvec() { - uint32_t mtvec_act; - uint32_t mtvec_exp = BOOTSTRAP_MTVEC | 0x1; - - __asm__ volatile("csrr %0, mtvec" : "=r" (mtvec_act)); - if (mtvec_act != mtvec_exp) { - printf("MTVEC bootstrap failure, exp 0x%08lx, act 0x%08lx\n", mtvec_exp, mtvec_act); - return 1; - } - return EXIT_SUCCESS; -} - -int main(int argc, char *argv[]) { - int retval; - - // Trash the "default" 0 table - for (int i = 0; i < 32; i++) { - volatile uint32_t *ptr = (volatile uint32_t *) (0 + i*4); - *ptr = 0x0; - } - - // Test that mtvec is correct - retval = test_mtvec(); - if (retval != EXIT_SUCCESS) - return retval; - - // Test 1 - retval = test1(); - if (retval != EXIT_SUCCESS) - return retval; -} - -// Test 1 will issue individual interrupts one at a time and ensure that each ISR is entered -int test1() { - printf("TEST 1 - TRIGGER ALL IRQS IN SEQUENCE:\n"); - - active_test = 1; - - if (test1_impl(0) != EXIT_SUCCESS) - return ERR_CODE_TEST_1; - - return EXIT_SUCCESS; -} - -// To share implementation of basic interrupt test with vector relocation tests, -// break out the test 1 implementation here -int test1_impl(int direct_mode) { - for (uint32_t i = 0; i < 32; i++) { -#ifdef DEBUG_MSG - printf("Test1 -> Testing interrupt %lu\n", i); -#endif - for (uint32_t gmie = 0; gmie <= 1; gmie++) { - for (uint32_t mie = 0; mie <= 1; mie++) { - uint32_t mip; - - // Set global MIE - if (gmie) mstatus_mie_enable(); - else mstatus_mie_disable(); - - // Set individual mie - if (mie) mie_enable(i); - else mie_disable(i); - - in_direct_handler = 0; - mmcause = 0; - mm_ram_assert_irq(0x1 << i, 1); - - if (((0x1 << i) & IRQ_MASK) && mie && gmie) { - // Interrupt is valid and enabled - // wait for the irq to be served - while (!mmcause); - - if ((mmcause & (0x1 << 31)) == 0) { - printf("MCAUSE[31] was not set: mmcause = 0x%08lx\n", (uint32_t) mmcause); - - return ERR_CODE_TEST_1; - } - if ((mmcause & MCAUSE_IRQ_MASK) != i) { - printf("MCAUSE reported wrong irq, exp = %lu, act = 0x%08lx", i, mmcause); - - return ERR_CODE_TEST_1; - } - } else { - // Unimplemented interrupts, or is a masked irq, delay a bit, waiting for any mmcause - for (int j = 0; j < 20; j++) { - if (mmcause != 0) { - printf("MMCAUSE = 0x%08lx when unimplmented interrupt %lu first", mmcause, i); - return ERR_CODE_TEST_1; - } - } - } - - // Check MIP - // For unimplemented irqs, this should always be 0 - // For masked irqs, this should always be 0 - // If the IRQ occurred then acking will cause it to clear by here, so do not check - __asm__ volatile ("csrr %0,mip" : "=r" (mip)); - if (((0x1 << i) & IRQ_MASK) && (!mie || !gmie)) { - // Implemented, masked IRQ - if (!(mip & (0x1 << i))) { - printf("MIP for IRQ[%lu] not set\n", i); - return ERR_CODE_TEST_1; - } - } else { - // Unimplemented IRQ - if (mip & (0x1 << i)) { - printf("MIP for unimplemented IRQ[%lu] set\n", i); - return ERR_CODE_TEST_1; - } - } - - // Check flag at direct mode handler - if (((0x1 << i) & IRQ_MASK) && mie && gmie) { - if (direct_mode && !in_direct_handler) { - printf("In direct mode, the direct sw handler was not entered, irq: %lu\n", i); - return ERR_CODE_TEST_1; - } - if (!direct_mode && in_direct_handler) { - printf("In vector mode, the direct sw handler was entered, irq: %lu\n", i); - return ERR_CODE_TEST_1; - } - } - - // Clear vp irq - mm_ram_assert_irq(0, 0); - } - } - } - - return EXIT_SUCCESS; -} - diff --git a/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_test.h b/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_test.h deleted file mode 120000 index 38c4eceb62..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_bootstrap/interrupt_test.h +++ /dev/null @@ -1 +0,0 @@ -../interrupt_test/interrupt_test.h \ No newline at end of file diff --git a/cv32e40x/tests/programs/custom/interrupt_bootstrap/link.ld b/cv32e40x/tests/programs/custom/interrupt_bootstrap/link.ld deleted file mode 100644 index 758e19f344..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_bootstrap/link.ld +++ /dev/null @@ -1,330 +0,0 @@ -/* Script for -z combreloc */ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. - Copyright (C) 2019 ETH Zürich and University of Bologna - Copyright (C) 2020 OpenHW Group - Copying and distribution of this script, with or without modification, - are permitted in any medium without royalty provided the copyright - notice and this notice are preserved. */ - -/* This linker script is adapted from the default linker script for upstream - RISC-V GCC. It has been modified for use in verification of CORE-V cores. -*/ - -OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", - "elf32-littleriscv") -OUTPUT_ARCH(riscv) -ENTRY(_start) - -/* CORE-V */ -MEMORY -{ - /* Our testbench is a bit weird in that we initialize the RAM (thus - allowing initialized sections to be placed there). Infact we dump all - sections to ram. */ - - ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 - dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000 -} - -SECTIONS -{ - /* CORE-V Debugger Code: This section address must be the same as the - DM_HaltAddress parameter in the RTL */ - .debugger (ORIGIN(dbg)): - { - KEEP(*(.debugger)); - } >dbg - .debugger_exception (0x1A111000): - { - KEEP(*(.debugger_exception)); - } >dbg - /* Debugger Stack*/ - .debugger_stack : ALIGN(16) - { - PROVIDE(__debugger_stack_start = .); - . = 0x80; - } >dbg - - - /* NMI interrupt handler fixed entry point */ - PROVIDE(__nmi_address = 0x100000); - - .nmi (__nmi_address): - { - KEEP(*(.nmi)); - } >ram - - - /* CORE-V: we want a fixed entry point */ - PROVIDE(__boot_address = 0x80); - - /* CORE-V: interrupt vectors */ - .vectors (ORIGIN(ram)): - { - PROVIDE(__vector_start = .); - KEEP(*(.vectors)); - } >ram - - /* CORE-V: crt0 init code */ - .init (__boot_address): - { - KEEP (*(SORT_NONE(.init))) - KEEP (*(.text.start)) - } >ram - - PROVIDE(__alt_vector_table = 0x200); - .vectors.alt (__alt_vector_table): - { - KEEP(*(.vectors.alt)); - } >ram - - /* Read-only sections, merged into text segment: */ - PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS; - .interp : { *(.interp) } >ram - .note.gnu.build-id : { *(.note.gnu.build-id) } >ram - .hash : { *(.hash) } >ram - .gnu.hash : { *(.gnu.hash) } >ram - .dynsym : { *(.dynsym) } >ram - .dynstr : { *(.dynstr) } >ram - .gnu.version : { *(.gnu.version) } >ram - .gnu.version_d : { *(.gnu.version_d) } >ram - .gnu.version_r : { *(.gnu.version_r) } >ram - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - PROVIDE_HIDDEN (__rela_iplt_start = .); - *(.rela.iplt) - PROVIDE_HIDDEN (__rela_iplt_end = .); - } >ram - .rela.plt : - { - *(.rela.plt) - } >ram - - .plt : { *(.plt) } - .iplt : { *(.iplt) } - .text : - { - *(.text.unlikely .text.*_unlikely .text.unlikely.*) - *(.text.exit .text.exit.*) - *(.text.startup .text.startup.*) - *(.text.hot .text.hot.*) - *(SORT(.text.sorted.*)) - *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf.em. */ - *(.gnu.warning) - } >ram - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >ram - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram - .rodata1 : { *(.rodata1) } >ram - .sdata2 : - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } >ram - .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram - .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >ram - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram - .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >ram - .gnu_extab : ONLY_IF_RO { *(.gnu_extab*) } >ram - /* These sections are generated by the Sun/Oracle C++ compiler. */ - .exception_ranges : ONLY_IF_RO { *(.exception_ranges*) } - /* Adjust the address for the data segment. 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/* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - /* DWARF Extension. */ - .debug_macro 0 : { *(.debug_macro) } - .debug_addr 0 : { *(.debug_addr) } - .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } -} - diff --git a/cv32e40x/tests/programs/custom/interrupt_bootstrap/test.yaml b/cv32e40x/tests/programs/custom/interrupt_bootstrap/test.yaml deleted file mode 100644 index 16371e980c..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_bootstrap/test.yaml +++ /dev/null @@ -1,7 +0,0 @@ -name: interrupt_bootstrap -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Interrupt directed test for mtvec_addr_i bootstrap pins -plusargs: > - +mtvec_addr=0x00000201 -llvm_cflags: -fno-integrated-as \ No newline at end of file diff --git a/cv32e40x/tests/programs/custom/interrupt_test/README.md b/cv32e40x/tests/programs/custom/interrupt_test/README.md deleted file mode 100644 index daa8e45bb7..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_test/README.md +++ /dev/null @@ -1,3 +0,0 @@ -CV32E40X Core Interrupt Testcases -============================= -This directory contains manually written directed testcases for interrupt testing of CV32E40X. diff --git a/cv32e40x/tests/programs/custom/interrupt_test/interrupt_test.c b/cv32e40x/tests/programs/custom/interrupt_test/interrupt_test.c deleted file mode 100644 index d483ccfa67..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_test/interrupt_test.c +++ /dev/null @@ -1,706 +0,0 @@ -#include -#include -#include - -#include "interrupt_test.h" - -volatile uint32_t irq_id = 0; -volatile uint32_t irq_id_q[IRQ_NUM]; -volatile uint32_t irq_id_q_ptr = 0; -volatile uint32_t mmcause = 0; -volatile uint32_t active_test = 0; -volatile uint32_t nested_irq = 0; -volatile uint32_t nested_irq_valid = 0; -volatile uint32_t in_direct_handler = 0; -volatile uint32_t event; -volatile uint32_t num_taken_interrupts; -volatile uint32_t num_counted_interrupts; - -uint32_t IRQ_ID_PRIORITY [IRQ_NUM] = { - FAST15_IRQ_ID , - FAST14_IRQ_ID , - FAST13_IRQ_ID , - FAST12_IRQ_ID , - FAST11_IRQ_ID , - FAST10_IRQ_ID , - FAST9_IRQ_ID , - FAST8_IRQ_ID , - FAST7_IRQ_ID , - FAST6_IRQ_ID , - FAST5_IRQ_ID , - FAST4_IRQ_ID , - FAST3_IRQ_ID , - FAST2_IRQ_ID , - FAST1_IRQ_ID , - FAST0_IRQ_ID , - EXTERNAL_IRQ_ID , - SOFTWARE_IRQ_ID , - TIMER_IRQ_ID -}; - -// FIXME: Create VP register for a timer on reliable time-base (i.e. cpu clock) -// FIXME: Add to common infrastructure -void delay(int count) { - for (volatile int d = 0; d < count; d++); -} - -void mstatus_mie_enable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mstatus_mie_disable() { - int mie_bit = 0x1 << MSTATUS_MIE_BIT; - asm volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); -} - -void mie_enable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_disable_all() { - uint32_t mie_mask = (uint32_t) -1; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); -} - -void mie_enable(uint32_t irq) { - // Enable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); -} - -void mie_disable(uint32_t irq) { - // Disable the interrupt irq in MIE - uint32_t mie_bit = 0x1 << irq; - asm volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); -} - -void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { - *TIMER_REG_ADDR = mask; - *TIMER_VAL_ADDR = 1 + cycle_delay; -} - -uint32_t random_num(uint32_t upper_bound, uint32_t lower_bound) { - uint32_t random_num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); - uint32_t num = (random_num % (upper_bound - lower_bound + 1)) + lower_bound; - return num; -} - -uint32_t random_num32() { - uint32_t num = *((volatile int *) CV_VP_RANDOM_NUM_BASE); - return num; -} - -extern void __no_irq_handler(); - -void nested_irq_handler(uint32_t id) { - // First stack mie, mepc and mstatus - // Must be done in critical section with MSTATUS.MIE == 0 - volatile uint32_t mie, mepc, mstatus; - asm volatile("csrr %0, mie" : "=r" (mie)); - asm volatile("csrr %0, mepc" :"=r" (mepc)); - asm volatile("csrr %0, mstatus" : "=r" (mstatus)); - - // Re enable interrupts and create window to enable nested irqs - mstatus_mie_enable(); - for (volatile int i = 0; i < 20; i++); - - // Disable MSTATUS.MIE and restore from critical section - mstatus_mie_disable(); - asm volatile("csrw mie, %0" : : "r" (mie)); - asm volatile("csrw mepc, %0" : : "r" (mepc)); - asm volatile("csrw mstatus, %0" : : "r" (mstatus)); -} - -void generic_irq_handler(uint32_t id) { - asm volatile("csrr %0, mcause": "=r" (mmcause)); - asm volatile("csrr %0, 0xB03" : "=r" (num_counted_interrupts)); - irq_id = id; - - // Increment if interrupt - if (mmcause >> 31) { - num_taken_interrupts++; - } - - if (active_test == 2 || active_test == 3 || active_test == 4) { - irq_id_q[irq_id_q_ptr++] = id; - } - if (active_test == 3) { - if (nested_irq_valid) { - nested_irq_valid = 0; - mm_ram_assert_irq(0x1 << nested_irq, random_num(10,0)); - } - nested_irq_handler(id); - } -} - -void m_software_irq_handler(void) { generic_irq_handler(SOFTWARE_IRQ_ID); } -void m_timer_irq_handler(void) { generic_irq_handler(TIMER_IRQ_ID); } -void m_external_irq_handler(void) { generic_irq_handler(EXTERNAL_IRQ_ID); } -void m_fast0_irq_handler(void) { generic_irq_handler(FAST0_IRQ_ID); } -void m_fast1_irq_handler(void) { generic_irq_handler(FAST1_IRQ_ID); } -void m_fast2_irq_handler(void) { generic_irq_handler(FAST2_IRQ_ID); } -void m_fast3_irq_handler(void) { generic_irq_handler(FAST3_IRQ_ID); } -void m_fast4_irq_handler(void) { generic_irq_handler(FAST4_IRQ_ID); } -void m_fast5_irq_handler(void) { generic_irq_handler(FAST5_IRQ_ID); } -void m_fast6_irq_handler(void) { generic_irq_handler(FAST6_IRQ_ID); } -void m_fast7_irq_handler(void) { generic_irq_handler(FAST7_IRQ_ID); } -void m_fast8_irq_handler(void) { generic_irq_handler(FAST8_IRQ_ID); } -void m_fast9_irq_handler(void) { generic_irq_handler(FAST9_IRQ_ID); } -void m_fast10_irq_handler(void) { generic_irq_handler(FAST10_IRQ_ID); } -void m_fast11_irq_handler(void) { generic_irq_handler(FAST11_IRQ_ID); } -void m_fast12_irq_handler(void) { generic_irq_handler(FAST12_IRQ_ID); } -void m_fast13_irq_handler(void) { generic_irq_handler(FAST13_IRQ_ID); } -void m_fast14_irq_handler(void) { generic_irq_handler(FAST14_IRQ_ID); } -void m_fast15_irq_handler(void) { generic_irq_handler(FAST15_IRQ_ID); } - -// A Special version of the SW Handler (vector 0) used in the direct mode -__attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void) { - in_direct_handler = 1; - asm volatile("csrr %0, mcause" : "=r" (mmcause)); - if (mmcause >> 31) { - num_taken_interrupts++; - } -} - - asm ( - ".global alt_vector_table\n" - ".option norvc\n" - ".align 8\n" - "alt_vector_table:\n" - "j u_sw_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_software_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_timer_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_external_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j __no_irq_handler\n" - "j m_fast0_irq_handler\n" - "j m_fast1_irq_handler\n" - "j m_fast2_irq_handler\n" - "j m_fast3_irq_handler\n" - "j m_fast4_irq_handler\n" - "j m_fast5_irq_handler\n" - "j m_fast6_irq_handler\n" - "j m_fast7_irq_handler\n" - "j m_fast8_irq_handler\n" - "j m_fast9_irq_handler\n" - "j m_fast10_irq_handler\n" - "j m_fast11_irq_handler\n" - "j m_fast12_irq_handler\n" - "j m_fast13_irq_handler\n" - "j m_fast14_irq_handler\n" - "j m_fast15_irq_handler\n" - ); - - asm ( - ".global alt_direct_vector_table\n" - ".option norvc\n" - ".align 8\n" - "alt_direct_vector_table:\n" - "j u_sw_direct_irq_handler\n" - ); - - asm ( - ".global alt_direct_ecall_table\n" - ".option norvc\n" - ".align 8\n" - "alt_direct_ecall_table:\n" - "wfi\n" - "j u_sw_irq_handler\n" - ); - -int main(int argc, char *argv[]) { - int retval; - - num_counted_interrupts = 0; - num_taken_interrupts = 0; - - // Enable interrupt performance counter (mhpmcounter3) - event = EVENT_INTR_TAKEN; - __asm__ volatile ("csrw 0x323, %0 " :: "r"(event)); - __asm__ volatile ("csrwi 0xB03, 0x0"); - __asm__ volatile ("csrwi 0x320, 0x0"); - - // Test 1 - retval = test1(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Test 2 - retval = test2(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Test 3 - retval = test3(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Test 4 - retval = test4(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Test 5 - retval = test5(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Test 6 - retval = test6(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Repeat test1 (restore vector mode) - retval = test7(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Try to write mcause (for coverage) - retval = test8(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Test 9 - retval = test9(); - if (retval != EXIT_SUCCESS) { - return retval; - } - - // Clear MIE for final WFI - mie_disable_all(); - - // Check that the interrupt taken counter - if (num_counted_interrupts != num_taken_interrupts) { - printf("mhpmcounter3 (number of events taken) does not match actual interrupts taken: %0d != %0d\n", (int)num_counted_interrupts, (int)num_taken_interrupts); - return ERR_CODE_INTR_CNT; - } - - return EXIT_SUCCESS; -} - -// Test 1 will issue individual interrupts one at a time and ensure that each ISR is entered -int test1() { - printf("TEST 1 - TRIGGER ALL IRQS IN SEQUENCE:\n"); - - active_test = 1; - - if (test1_impl(0) != EXIT_SUCCESS) - return ERR_CODE_TEST_1; - - return EXIT_SUCCESS; -} - -// To share implementation of basic interrupt test with vector relocation tests, -// break out the test 1 implementation here -int test1_impl(int direct_mode) { - for (uint32_t i = 0; i < 32; i++) { -#ifdef DEBUG_MSG - printf("Test1 -> Testing interrupt %lu\n", i); -#endif - for (uint32_t gmie = 0; gmie <= 1; gmie++) { - for (uint32_t mie = 0; mie <= 1; mie++) { - uint32_t mip; - - // Set global MIE - if (gmie) mstatus_mie_enable(); - else mstatus_mie_disable(); - - // Set individual mie - if (mie) mie_enable(i); - else mie_disable(i); - - in_direct_handler = 0; - mmcause = 0; - mm_ram_assert_irq(0x1 << i, 1); - - if (((0x1 << i) & IRQ_MASK) && mie && gmie) { - // Interrupt is valid and enabled - // wait for the irq to be served - while (!mmcause); - - if ((mmcause & (0x1 << 31)) == 0) { - printf("MCAUSE[31] was not set: mmcause = 0x%08lx\n", (uint32_t) mmcause); - - return ERR_CODE_TEST_1; - } - if ((mmcause & MCAUSE_IRQ_MASK) != i) { - printf("MCAUSE reported wrong irq, exp = %lu, act = 0x%08lx", i, mmcause); - - return ERR_CODE_TEST_1; - } - } else { - // Unimplemented interrupts, or is a masked irq, delay a bit, waiting for any mmcause - for (int j = 0; j < 20; j++) { - if (mmcause != 0) { - printf("MMCAUSE = 0x%08lx when unimplmented interrupt %lu first", mmcause, i); - return ERR_CODE_TEST_1; - } - } - } - - // Check MIP - // For unimplemented irqs, this should always be 0 - // For masked irqs, this should always be 0 - // If the IRQ occurred then acking will cause it to clear by here, so do not check - __asm__ volatile ("csrr %0,mip" : "=r" (mip)); - if (((0x1 << i) & IRQ_MASK) && (!mie || !gmie)) { - // Implemented, masked IRQ - if (!(mip & (0x1 << i))) { - printf("MIP for IRQ[%lu] not set\n", i); - return ERR_CODE_TEST_1; - } - } else { - // Unimplemented IRQ - if (mip & (0x1 << i)) { - printf("MIP for unimplemented IRQ[%lu] set\n", i); - return ERR_CODE_TEST_1; - } - } - - // Check flag at direct mode handler - if (((0x1 << i) & IRQ_MASK) && mie && gmie) { - if (direct_mode && !in_direct_handler) { - printf("In direct mode, the direct sw handler was not entered, irq: %lu\n", i); - return ERR_CODE_TEST_1; - } - if (!direct_mode && in_direct_handler) { - printf("In vector mode, the direct sw handler was entered, irq: %lu\n", i); - return ERR_CODE_TEST_1; - } - } - - // Clear vp irq - mm_ram_assert_irq(0, 0); - } - } - } - - return EXIT_SUCCESS; -} - - //------------------------------------------------------------------------------------------------------------------------------------------- - //------------------------------------------------------------------------------------------------------------------------------------------- - -// Test 2 will issue all interrupts at once and check that all interrupt are serviced in priority order -int test2() { - printf("TEST 2 - TRIGGER ALL IRQS AT ONCE:\n"); - active_test = 2; - - // Clear VP irq - mm_ram_assert_irq(0, 0); - - // Enable all interrupts (MIE and MSTATUS.MIE) - uint32_t mie = (uint32_t) -1; - asm volatile("csrw mie, %0" : : "r" (mie)); - mstatus_mie_enable(); - irq_id_q_ptr = 0; - - // Fire all IRQs and give time for them to be handled - mm_ram_assert_irq((uint32_t) -1, 0); - - delay(100); - - for (int i = 0; i < IRQ_NUM; i++) { - // The irq_id_q should now contain interrupt IDs in the same order as IRQ_ID_PRIORITY - if (IRQ_ID_PRIORITY[i] != irq_id_q[i]) { - printf("priority mismatch, index %d, exp %lu, act %lu\n", - i, IRQ_ID_PRIORITY[i], irq_id_q[i]); - return ERR_CODE_TEST_2; - } - } - - return EXIT_SUCCESS; -} - - //------------------------------------------------------------------------------------------------------------------------------------------- - //------------------------------------------------------------------------------------------------------------------------------------------- - -// Test 3 will create nested interrupts -int test3() { - printf("TEST 3 - NESTED INTERRUPTS:\n"); - - // Test 3 is a nested interrupt test - active_test = 3; - - // Enable all interrupts - mm_ram_assert_irq(0, 0); - mie_enable_all(); - mstatus_mie_enable(); - - // Set 2 interrupts - for (uint32_t loop = 0; loop < 50; loop++) { - uint32_t irq[2]; - - // Pick 2 random interrupts - irq[0] = IRQ_ID_PRIORITY[random_num(IRQ_NUM-1, 0)]; - irq[1] = IRQ_ID_PRIORITY[random_num(IRQ_NUM-1, 0)]; - - irq_id_q_ptr = 0; - nested_irq = irq[1]; - nested_irq_valid = 1; - -#ifdef DEBUG_MSG - printf("TEST3: Test nested irqs %lu and %lu\n", irq[0], irq[1]); -#endif - - mm_ram_assert_irq(0x1 << irq[0], 0); - - delay(50); - - if (irq_id_q[0] != irq[0]) { - printf("TEST3, first interrupt exp %lu act %lu\n", irq[0], irq_id_q[0]); - return ERR_CODE_TEST_3; - } - if (irq_id_q[1] != irq[1]) { - printf("TEST3, second interrupt exp %lu act %lu\n", irq[1], irq_id_q[1]); - return ERR_CODE_TEST_3; - } - } - - return EXIT_SUCCESS; -} - - //------------------------------------------------------------------------------------------------------------------------------------------- - //------------------------------------------------------------------------------------------------------------------------------------------- - -// Test 4 will test WFI mode -// Ensures that only MIE-enabled interrupts wake WFI -// Tests that WFI works regardless of MSTATUS.MIE -// Tests that IRQ handler is not entered after WFI unless MSTATUS.MIE is set -int test4() { - printf("TEST 4 - WFI\n"); - - // Test 4 is a WFI test - active_test = 4; - - // Iterate through multiple loops - for (int irq = 0; irq < 32; irq++) { - if (!(((0x1 << irq) & IRQ_MASK))) - continue; - - for (uint32_t gmie = 0; gmie <= 1; gmie++) { - uint32_t rand_irq; - - // Clear MIE and all pending irqs - mie_disable_all(); - mm_ram_assert_irq(0, 0); - - // Select a wakeup interrupt and enable only it - mie_enable(irq); - - // Prep the IRQ ID Q to be empty, we need to detect if any interrupts (or none) taken - irq_id_q[0] = -1; - irq_id_q_ptr = 0; - - // Set the global MSTATUS.MIE - // Note that WFI should ignore this (but subsequent ISR will not be taken if MSTATUS.MIE == 0) - if (gmie) - mstatus_mie_enable(); - else - mstatus_mie_disable(); - - // Assert random batch of irqs (w/o selected irq) - rand_irq = random_num32() & ~(0x1 << irq); - mm_ram_assert_irq(rand_irq, 0); - - delay(2); - - // Random assert "enabled" irq - mm_ram_assert_irq(rand_irq | (0x1 << irq), (random_num32() & 0x3f) + 32); - asm volatile("wfi"); - - - if (gmie) { - // Expected an interrupt taken - if (irq_id_q[0] != irq) { - printf("After WFI, expected to hit an interrupt, but irq_id_q is empty\n"); - return ERR_CODE_TEST_4; - } - } else { - // Expected no interrupt taken - if (irq_id_q[0] != -1) { - printf("After WFI with MSTATUS.MIE == 0, interrupt was taken: %lu\n", irq_id_q[0]); - return ERR_CODE_TEST_4; - } - } - } - } - return EXIT_SUCCESS; -} - -// Test 5 will repeat the basic interrupt test in test 1 -// But with a relocated vector table via mtvec CSR -int test5() { - volatile uint32_t save_mtvec; - int retval; - - printf("TEST 5 - TRIGGER ALL IRQS IN SEQUENCE (RELOCATED MTVEC):\n"); - - active_test = 5; - - asm volatile("csrr %0, mtvec" : "=r" (save_mtvec)); - asm volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_vector_table | (save_mtvec & 0x3))); - - retval = test1_impl(0); - asm volatile("csrw mtvec, %0" : : "r" (save_mtvec)); - if (retval != EXIT_SUCCESS) { - return ERR_CODE_TEST_5; - } - - return EXIT_SUCCESS; -} - -// Test 6 will repeat the basic interrupt test in test 1 -// But with a relocated vector table via mtvec CSR and DIRECT vector mode -int test6() { - volatile uint32_t save_mtvec; - int retval; - - printf("TEST 6 - TRIGGER ALL IRQS IN SEQUENCE (DIRECT-MODE MTVEC):\n"); - - active_test = 6; - - asm volatile("csrr %0, mtvec" : "=r" (save_mtvec)); - asm volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_direct_vector_table)); // Leave mode at 0 - - retval = test1_impl(1); - asm volatile("csrw mtvec, %0" : : "r" (save_mtvec)); - if (retval != EXIT_SUCCESS) { - return ERR_CODE_TEST_6; - } - - return EXIT_SUCCESS; -} - -// Test 7 is a direct repeat of test 1 in vectored mode -int test7() { - printf("TEST 7 - TRIGGER ALL IRQS IN SEQUENCE: (REPEAT VECTOR MODE)\n"); - - active_test = 7; - - if (test1_impl(0) != EXIT_SUCCESS) - return ERR_CODE_TEST_7; - - return EXIT_SUCCESS; -} - -int test8() { - volatile uint32_t mcausew; - volatile uint32_t mcauser; - - // MCAUSE is writable, this simple check tests this and also fufills code coverage - printf("TEST 8 - READ/WRITE TO MCAUSE\n"); - - mcausew = 0x0; - __asm__ volatile("csrw mcause, %0" : : "r"(mcausew)); - __asm__ volatile("csrr %0, mcause" : "=r"(mcauser)); - if (mcauser != 0) { - printf("MCAUSE write-read error, exp: 0x0, act: 0x%lx\n", mcauser); - return EXIT_FAILURE; - } - - mcausew = 0x1f; - __asm__ volatile("csrw mcause, %0" : : "r"(mcausew)); - __asm__ volatile("csrr %0, mcause" : "=r"(mcauser)); - if (mcauser != mcausew) { - printf("MCAUSE write-read error, exp: 0x1f, act: 0x%lx\n", mcauser); - return EXIT_FAILURE; - } - - mcausew = 0x0; - __asm__ volatile("csrw mcause, %0" : : "r"(mcausew)); - __asm__ volatile("csrr %0, mcause" : "=r"(mcauser)); - if (mcauser != 0) { - printf("MCAUSE write-read error, exp: 0x0, act: 0x%lx\n", mcauser); - return EXIT_FAILURE; - } - - return EXIT_SUCCESS; -} - -int test9() { - volatile uint32_t save_mtvec; - printf("TEST 9 - ECALL-WFI Coverage Test\n"); - - active_test = 9; - - asm volatile("csrr %0, mtvec" : "=r" (save_mtvec)); - asm volatile("csrw mtvec, %0" : : "r" ((uint32_t) alt_direct_ecall_table)); // Leave mode at 0 - - mm_ram_assert_irq(0, 0); - - // Iterate through multiple loops - for (int irq = 0; irq < 32; irq++) { - if (!(((0x1 << irq) & IRQ_MASK))) - continue; - - for (uint32_t gmie = 0; gmie <= 0; gmie++) { - uint32_t rand_irq; - - // Clear MIE and all pending irqs - mie_disable_all(); - - // Select a wakeup interrupt and enable only it - mie_enable(irq); - - // Prep the IRQ ID Q to be empty, we need to detect if any interrupts (or none) taken - irq_id_q[0] = -1; - irq_id_q_ptr = 0; - - // Set the global MSTATUS.MIE - // Note that WFI should ignore this (but subsequent ISR will not be taken if MSTATUS.MIE == 0) - if (gmie) - mstatus_mie_enable(); - else - mstatus_mie_disable(); - - // Assert random batch of irqs (w/o selected irq) - rand_irq = random_num32() & ~(0x1 << irq); - mm_ram_assert_irq(rand_irq, 0); - - delay(2); - - // Random assert "enabled" irq - mm_ram_assert_irq(rand_irq | (0x1 << irq), (random_num32() & 0x3f) + 64); - asm volatile("ecall"); - - if (gmie) { - // Expected an interrupt taken - if (irq_id_q[0] != irq) { - printf("After WFI, expected to hit an interrupt, but irq_id_q is empty\n"); - return ERR_CODE_TEST_4; - } - } else { - // Expected no interrupt taken - if (irq_id_q[0] != -1) { - printf("After WFI with MSTATUS.MIE == 0, interrupt was taken: %lu\n", irq_id_q[0]); - return ERR_CODE_TEST_4; - } - } - } - } - - asm volatile("csrw mtvec, %0" : : "r" (save_mtvec)); - - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/interrupt_test/interrupt_test.h b/cv32e40x/tests/programs/custom/interrupt_test/interrupt_test.h deleted file mode 100644 index ebbc09863b..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_test/interrupt_test.h +++ /dev/null @@ -1,115 +0,0 @@ -// This is free and unencumbered software released into the public domain. -// -// Anyone is free to copy, modify, publish, use, compile, sell, or -// distribute this software, either in source code form or as a compiled -// binary, for any purpose, commercial or non-commercial, and by any -// means. - -#ifndef __INTERRUPT_TEST_H__ -#define __INTERRUPT_TEST_H__ - -#include -#include -#include "corev_uvmt.h" -// Enable debug messages, note that this will change test timing -//#define DEBUG_MSG - -#define ERR_CODE_TEST_1 1 -#define ERR_CODE_TEST_2 2 -#define ERR_CODE_TEST_3 3 -#define ERR_CODE_TEST_4 4 -#define ERR_CODE_TEST_5 5 -#define ERR_CODE_TEST_6 6 -#define ERR_CODE_TEST_7 7 - -#define ERR_CODE_INTR_CNT 8 - -#define TIMER_REG_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE)) -#define TIMER_VAL_ADDR ((volatile uint32_t *) (CV_VP_INTR_TIMER_BASE + 4)) - -#define MSTATUS_MIE_BIT 3 - -#define MCAUSE_IRQ_MASK 0x1f - -#define EVENT_INTR_TAKEN (1 << 6) - -#define IRQ_NUM 19 -#define IRQ_MASK 0xFFFF0888 - -#define SOFTWARE_IRQ_ID 3 -#define TIMER_IRQ_ID 7 -#define EXTERNAL_IRQ_ID 11 -#define FAST0_IRQ_ID 16 -#define FAST1_IRQ_ID 17 -#define FAST2_IRQ_ID 18 -#define FAST3_IRQ_ID 19 -#define FAST4_IRQ_ID 20 -#define FAST5_IRQ_ID 21 -#define FAST6_IRQ_ID 22 -#define FAST7_IRQ_ID 23 -#define FAST8_IRQ_ID 24 -#define FAST9_IRQ_ID 25 -#define FAST10_IRQ_ID 26 -#define FAST11_IRQ_ID 27 -#define FAST12_IRQ_ID 28 -#define FAST13_IRQ_ID 29 -#define FAST14_IRQ_ID 30 -#define FAST15_IRQ_ID 31 - -void delay(int count); -void mstatus_mie_enable(); -void mstatus_mie_disable(); -void mie_enable_all(); -void mie_disable_all(); -void mie_enable(uint32_t irq); -void mie_disable(uint32_t irq); -void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay); -uint32_t random_num(uint32_t upper_bound, uint32_t lower_bound); -uint32_t random_num32(); -extern void __no_irq_handler(); -void nested_irq_handler(uint32_t id); -void generic_irq_handler(uint32_t id); - -__attribute__((interrupt ("machine"))) void m_software_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_timer_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_external_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast0_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast1_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast2_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast3_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast4_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast5_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast6_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast7_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast8_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast9_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast10_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast11_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast12_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast13_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast14_irq_handler(void); -__attribute__((interrupt ("machine"))) void m_fast15_irq_handler(void); - -// A Special version of the SW Handler (vector 0) used in the direct mode -__attribute__((interrupt ("machine"))) void u_sw_direct_irq_handler(void); - -extern void alt_vector_table(); -extern void alt_direct_vector_table(); -extern void alt_direct_ecall_table(); - -// Function prototypes for individual tests -int test1(); -int test2(); -int test3(); -int test4(); -int test5(); -int test6(); -int test7(); -int test8(); -int test9(); - -// Test1 (all irqs in sequence) used in multiple tests so break out implementation -int test1_impl(int direct_mode); - -#endif - diff --git a/cv32e40x/tests/programs/custom/interrupt_test/test.yaml b/cv32e40x/tests/programs/custom/interrupt_test/test.yaml deleted file mode 100644 index 189f10cb55..0000000000 --- a/cv32e40x/tests/programs/custom/interrupt_test/test.yaml +++ /dev/null @@ -1,7 +0,0 @@ -name: interrupt_test -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Interrupt directed test - - - diff --git a/cv32e40x/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S b/cv32e40x/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S deleted file mode 100644 index 02b371d7a3..0000000000 --- a/cv32e40x/tests/programs/custom/isa_fcov_holes/isa_fcov_holes.S +++ /dev/null @@ -1,587 +0,0 @@ -# CSR access test -# Generated by gen_csr_test.py (part of riscv-dv) -# Manual edits to fit with BSP and enhance debug -#include "corev_uvmt.h" -.include "user_define.h" -.section .text.start -.globl _start -.section .text -#.include "user_init.s" -.type _start, @function - -_start: - j _start_main - -.globl _start_main -.section .text -_start_main: - - #define EXP_MISA 0x40001104 - -############################################################################### -# Generated code starts... -############################################################################### -_start0: - # mcycle - li x7, 0xa5a5a5a5 - csrrw x12, 2816, x7 - li x7, 0x00000000 - bne x7, x12, csr_fail - li x7, 0x5a5a5a5a - csrrw x12, 2816, x7 - li x7, 0xa5a5a5a5 - bne x7, x12, csr_fail - li x7, 0xd5583a6b - csrrw x12, 2816, x7 - li x7, 0x5a5a5a5a - bne x7, x12, csr_fail - li x7, 0xa5a5a5a5 - csrrs x12, 2816, x7 - li x7, 0xd5583a6b - bne x7, x12, csr_fail - li x7, 0x5a5a5a5a - csrrs x12, 2816, x7 - li x7, 0xf5fdbfef - bne x7, x12, csr_fail - li x7, 0x1ac809f1 - csrrs x12, 2816, x7 - li x7, 0xffffffff - bne x7, x12, csr_fail - li x7, 0xa5a5a5a5 - csrrc x12, 2816, x7 - li x7, 0xffffffff - bne x7, x12, csr_fail - li x7, 0x5a5a5a5a - csrrc x12, 2816, x7 - li x7, 0x5a5a5a5a - bne x7, x12, csr_fail - li x7, 0xe34ffa80 - csrrc x12, 2816, x7 - li x7, 0x00000000 - bne x7, x12, csr_fail - csrrwi x12, 2816, 0b00101 - li x7, 0x00000000 - bne x7, x12, csr_fail - csrrwi x12, 2816, 0b11010 - li x7, 0x00000005 - bne x7, x12, csr_fail - csrrwi x12, 2816, 0b01111 - li x7, 0x0000001a - bne x7, x12, csr_fail - csrrsi x12, 2816, 0b00101 - li x7, 0x0000000f - bne x7, x12, csr_fail - csrrsi x12, 2816, 0b11010 - li x7, 0x0000000f - bne x7, x12, csr_fail - csrrsi x12, 2816, 0b01100 - li x7, 0x0000001f - bne x7, x12, csr_fail - csrrci x12, 2816, 0b00101 - li x7, 0x0000001f - bne x7, x12, csr_fail - csrrci x12, 2816, 0b11010 - li x7, 0x0000001a - bne x7, x12, csr_fail - csrrci x12, 2816, 0b11001 - li x7, 0x00000000 - bne x7, x12, csr_fail - -################################################################################ -# Generated code ends... -################################################################################ -# Hit those coverage holes with manually generated code... -################################################################################ - - # Various rd/rs holes, especially rs1==x0 - li x1, 0xFFFFFFFF - add x2, x0, x4 # hole: rs1==x0 - add x2, x0, x1 - and x2, x25, x26 # hole: rs1==x25 - - lw x2, 0(x0) # hole: load/store with rs1==x0 - lw x3, 4(x0) - add x2, x0, x3 - sw x2, 0(x0) - lw x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail - - li x1, 0xFFFFFFFF - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - lb x2, 0(x0) # hole: load/store with rs1==x0 - lb x3, 4(x0) - add x2, x0, x3 - sb x2, 0(x0) - lb x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail - - li x1, 0xFFFFFFFF - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - lbu x2, 0(x0) # hole: load/store with rs1==x0 - lbu x3, 4(x0) - add x2, x0, x3 - sb x2, 0(x0) - lbu x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail - - li x1, 0xFFFFFFFF - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - lh x2, 0(x0) # hole: load/store with rs1==x0 - lh x3, 4(x0) - add x2, x0, x3 - sh x2, 0(x0) - lh x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail - - li x1, 0xFFFFFFFF - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - lhu x2, 0(x0) # hole: load/store with rs1==x0 - lhu x3, 4(x0) - add x2, x0, x3 - sh x2, 0(x0) - lhu x1, 0(x0) # hole: load/store with rs1==x0 - bne x2, x1, csr_fail - - lw x3, 4(x0) - add x3, x0, x4 # hole: rs1==x0 - sw x2, 0(x0) - sw x2, 4(x0) - - # cross coverage with c.jal - # TODO: how to handle EBREAK, ECALL, WFI, MRET, DRET, C_EBREAK -crosses: - add x3, x2, x1 - c.jal next1 -next1: - addi x3, x2, 1 - c.jal next2 -next2: - and x3, x2, x1 - c.jal next3 -next3: - andi x3, x2, 1 - c.jal next4 -next4: - auipc x3, 1 - c.jal next5 -next5: - li x1, 1 - li x2, 2 - beq x1, x2, crosses - c.jal next6 -next6: - bge x2, x1, crosses - c.jal next7 -next7: - bgeu x2, x1, crosses - c.jal next8 -next8: - blt x1, x2, crosses - c.jal next9 -next9: - bltu x1, x2, crosses - c.jal next10 -next10: - li x1, 1 - li x2, 1 - bne x1, x2, crosses - c.jal next11 -next11: - fence - c.jal next12 -next12: - fence.i - c.jal next13 -next13: - jal next14 -next14: - c.jal next14.1 # whoops! -next14.1: - lla x2, next15 - jalr x2 -next15: - c.jal next16 -next16: - lb x2, 2(x0) - c.jal next17 -next17: - lbu x2, 2(x0) - c.jal next18 -next18: - lhu x2, 2(x0) - c.jal next19 -next19: - lh x2, 2(x0) - c.jal next20 -next20: - lui x2, 5 - c.jal next21 -next21: - lw x2, 2(x0) - c.jal next22 -next22: - or x2, x3, x4 - c.jal next23 -next23: - ori x2, x3, 5 - c.jal next24 -next24: - sb x2, 2(x0) - c.jal next25 -next25: - sh x2, 2(x0) - c.jal next26 -next26: - sll x2, x3, x4 - c.jal next27 -next27: - slli x2, x3, 5 - c.jal next28 -next28: - slt x2, x3, x4 - c.jal next29 -next29: - slti x2, x3, 4 - c.jal next30 -next30: - sltiu x2, x3, 4 - c.jal next31 -next31: - sltu x2, x3, x4 - c.jal next32 -next32: - sra x2, x3, x4 - c.jal next33 -next33: - srai x2, x3, 4 - c.jal next34 -next34: - srl x2, x3, x4 - c.jal next35 -next35: - srli x2, x3, 4 - c.jal next36 -next36: - sub x2, x3, x4 - c.jal next37 -next37: - sw x2, 2(x0) - c.jal next38 -next38: - xor x2, x3, x4 - c.jal next39 -next39: - xori x2, x3, 4 - c.jal next40 -next40: - mul x2, x3, x4 - c.jal next41 -next41: - mulh x2, x3, x4 - c.jal next42 -next42: - mulhu x2, x3, x4 - c.jal next43 -next43: - mulhsu x2, x3, x4 - c.jal next44 -next44: - div x2, x3, x4 - c.jal next45 -next45: - rem x2, x3, x4 - c.jal next46 -next46: - divu x2, x3, x4 - c.jal next47 -next47: - remu x2, x3, x4 - c.jal next48 -next48: - csrrw x7, 0x340, x12 #mscratch - c.jal next49 -next49: - csrrc x7, 0x340, x12 - c.jal next50 -next50: - csrrs x7, 0x340, x12 - c.jal next51 -next51: - csrrwi x7, 0x340, 12 #mscratch - c.jal next52 -next52: - csrrci x7, 0x340, 12 - c.jal next53 -next53: - csrrsi x7, 0x340, 12 - c.jal next54 -next54: - c.lwsp x4, 0(x2) - c.jal next55 -next55: - c.swsp x4, 0(x2) - c.jal next56 -next56: - c.lw a2, 8(a0) - c.jal next57 -next57: - c.sw a2, 8(a0) - c.jal next58 -next58: - li a2, 1 - li a4, 0 - c.beqz a2, crosses - c.jal next59 -next59: - c.bnez a4, crosses - c.jal next60 -next60: - c.j next61 -next61: - c.jal next62 -next62: - lla x2, next63 - c.jr x2 -next63: - c.jal next64 -next64: - c.jal next65 -next65: - lla x2, next66 - c.jalr x2 -next66: - c.jal next67 -next67: - c.li x2, 0 - c.jal next68 -next68: - c.lui x4, 2 - c.jal next69 -next69: - c.addi x2, 0 - c.jal next70 -next70: - c.addi16sp sp, -16 - c.jal next71 -next71: - c.addi4spn a2, sp, 4 - c.jal next72 -next72: - c.mv x4, x3 - c.jal next73 -next73: - c.slli x2, 2 - c.jal next74 -next74: - c.srli a2, 2 - c.jal next75 -next75: - c.srai a2, 2 - c.jal next76 -next76: - c.andi a2, 4 - c.jal next77 -next77: - c.add x2, x4 - c.jal next78 -next78: - c.and a2, a4 - c.jal next79 -next79: - c.or a2, a4 - c.jal next80 -next80: - c.xor a2, a4 - c.jal next81 -next81: - c.sub a2, a4 - c.jal next82 -next82: - - # negative branch - li x1, 0xFFFFFFFF -holes: - beq x0, x1, test_lui0 - li x1, 0x00000000 - srli x2, x0, 0b000100 # hole: rd is never x2 - beq x0, x7, holes # hole: negative branch - li x4, 0x00000002 - jalr x0, x4, 0 # jump to the second nop - nop - nop - nop - -test_lui0: - #first, load gprs with non-zero values - lui x0, 0x0FFFF - lui x1, 0xF0FFF - lui x2, 0xFF0FF - lui x3, 0xFFF0F - lui x4, 0xFFFF0 - lui x5, 0xFFF0F - lui x6, 0xFF0FF - lui x7, 0xF0FFF - lui x8, 0x0FFFF - lui x9, 0xF0FFF - lui x10, 0xFF0FF - lui x11, 0xFFF0F - lui x12, 0xFFFF0 - lui x13, 0xFFF0F - lui x14, 0xFF0FF - lui x15, 0xF0FFF - lui x16, 0x0FFFF - lui x17, 0xF0FFF - lui x18, 0xFF0FF - lui x19, 0xFFFFF - lui x20, 0xFFF0F - lui x21, 0xFFFF0 - lui x22, 0xFFF0F - lui x23, 0xFF0FF - lui x24, 0xF0FFF - lui x25, 0x0FFFF - lui x26, 0xF0FFF - lui x27, 0xFF0FF - lui x28, 0xFFF0F - lui x29, 0xFFFF0 - lui x30, 0xFFF0F - lui x31, 0xFF0FF - - # The infamous load-unsigned-immediate with imm==0 - lui x0, 0 - addi x0, x0, 0 - bne x0, x0, test_fail - lui x1, 0 - bne x1, x0, test_fail - lui x2, 0 - bne x2, x0, test_fail - lui x3, 0 - bne x3, x0, test_fail - lui x4, 0 - bne x4, x0, test_fail - lui x5, 0 - bne x5, x0, test_fail - lui x6, 0 - bne x6, x0, test_fail - lui x7, 0 - bne x7, x0, test_fail - lui x8, 0 - bne x8, x0, test_fail - lui x9, 0 - bne x9, x0, test_fail - lui x10, 0 - bne x10, x0, test_fail - lui x11, 0 - bne x0, x11, test_fail - lui x12, 0 - bne x0, x12, test_fail - lui x13, 0 - bne x0, x13, test_fail - lui x14, 0 - bne x0, x14, test_fail - lui x15, 0 - bne x0, x15, test_fail - lui x16, 0 - bne x0, x16, test_fail - lui x17, 0 - bne x0, x17, test_fail - lui x18, 0 - bne x0, x18, test_fail - lui x19, 0 - bne x0, x19, test_fail - lui x20, 0 - bne x0, x20, test_fail - lui x21, 0 - bne x21, x0, test_fail - lui x22, 0 - bne x0, x22, test_fail - lui x23, 0 - bne x23, x0, test_fail - lui x24, 0 - bne x0, x24, test_fail - lui x25, 0 - bne x25, x0, test_fail - lui x26, 0 - bne x0, x26, test_fail - lui x27, 0 - bne x27, x0, test_fail - lui x28, 6 - beq x0, x28, test_fail # just to see if you're paying attention - lui x29, 0 - bne x29, x0, test_fail - lui x30, 0 - bne x0, x30, test_fail - lui x31, 0 - bne x31, x0, test_fail - lui x28, 0 - bne x0, x28, test_fail # we skipped lui x28, 0 - -test_done: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'D' - sw a1,0(a0) - addi a1,zero,'O' - sw a1,0(a0) - addi a1,zero,'N' - sw a1,0(a0) - addi a1,zero,'E' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - -csr_pass: - li x18, 123456789 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi - -csr_fail: -test_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - - li x18, 1 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi -# -# end -# diff --git a/cv32e40x/tests/programs/custom/isa_fcov_holes/test.yaml b/cv32e40x/tests/programs/custom/isa_fcov_holes/test.yaml deleted file mode 100644 index e15f2ada00..0000000000 --- a/cv32e40x/tests/programs/custom/isa_fcov_holes/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: isa_fcov_holes -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Hand-crafted testcase to fill ISA functional coverage holes diff --git a/cv32e40x/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S b/cv32e40x/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S deleted file mode 100644 index 708d40c9a7..0000000000 --- a/cv32e40x/tests/programs/custom/load_store_rs1_zero/load_store_rs1_zero.S +++ /dev/null @@ -1,142 +0,0 @@ -################################################################################ -# -# Copyright (C) EM Microelectronic US Inc. -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. -# -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 -# -################################################################################ -# - Addresses coverage hole in which load and store instructions are not -# generated for which operand rs1=ZERO. -# - THIS TEST IS SELF CHECKING but should be run against a -# reference model to check results. -# - This test can be abandoned and corev_rand_instr_test should produce -# this combination when https://github.com/google/riscv-dv/issues/752 -# is addressed. -################################################################################ -#include "corev_uvmt.h" - -.include "user_define.h" -.section .text.start -.globl _start -.section .text -.type _start, @function - -_start: - j _start_main - -.globl _start_main -.section .text -_start_main: - -# Verify uncompressed load and store - # Write/read mem[2047]=12, mem[2046]=34, mem[2045]=56, mem[2044]=78 - li a1, 0x12345678 - sw a1, 2044(zero) - lw a2, 2044(zero) - bne a2, a1, test_fail - - # write/read mem[2047]=0x9A with sb and lb (lb does sign extend) - li a3, 0x9A - sb a3, 2047(zero) - li a3, 0xFFFFFF9A # Sign extended expected value - lb a4, 2047(zero) - bne a4, a3, test_fail - - # write/read mem[2047]=0xBC with sb and lbu (lbu does not sign extend) - li a5, 0xBC - sb a5, 2047(zero) - lbu a6, 2047(zero) - bne a5, a6, test_fail - - # write/read mem[2047]=0xDE & mem[2046]=0xF0 with sh and lh (lh does sign extend) - li a7, 0xDEF0 - sh a7, 2046(zero) - li a7, 0xFFFFDEF0 # Sign extended expected value - lh a0, 2046(zero) - bne a7, a0, test_fail - - # write/read mem[2047]=0x81 & mem[2046]=0x23 with sh and lhu (lhu does not sign extend) - li a1, 0x8123 - sh a1, 2046(zero) - lhu a2, 2046(zero) - bne a1, a2, test_fail - -test_done: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'D' - sw a1,0(a0) - addi a1,zero,'O' - sw a1,0(a0) - addi a1,zero,'N' - sw a1,0(a0) - addi a1,zero,'E' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - -test_pass: - li x18, 123456789 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi - -test_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - - li x18, 1 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi -# -# end -# diff --git a/cv32e40x/tests/programs/custom/load_store_rs1_zero/test.yaml b/cv32e40x/tests/programs/custom/load_store_rs1_zero/test.yaml deleted file mode 100644 index 8847229ae2..0000000000 --- a/cv32e40x/tests/programs/custom/load_store_rs1_zero/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: load_store_rs1_zero -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - load and store with rs1=zero diff --git a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S b/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S deleted file mode 100644 index 683df196c7..0000000000 --- a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_1/mhpmcounter29_csr_access_test_1.S +++ /dev/null @@ -1,1099 +0,0 @@ -# -# Copyright (C) EM Microelectronic US Inc. -# Copyright (C) 2020 OpenHW Group -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. -# -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 -# -############################################################################### -# MHPMCOUNTERS29: access testcase for mhpmcounter3..31 CSRs in cv32e40x. -# Notes: -# 1. This test requires NUM_MHPMCOUNTERS set to 29. -# 2. Does not test function - just access. -# 3. FIXME: ISS currently does not set mcountinhibit correctly on reset -# for non-default number of registers, RVVI and RVFI will mismatch if -# sb checking is enabled. -############################################################################### -#include "corev_uvmt.h" - -.globl _start -.globl main -.globl exit -.global debug -.section .text -.global u_sw_irq_handler - - -#define TEST_PASS 123456789 -#define TEST_FAIL 1 -#define VIRT_PERIPH_STATUS_FLAG_ADDR CV_VP_STATUS_FLAGS_BASE -#define EXPECTED_ILLEGAL_INSTRUCTIONS 24 - -main: - li t0, (0x1 << 3) - csrs mstatus, t0 - li x5, 0x0 - li x6, 0x6 - li x7, 0x7 - li x8, 0x8 - li x9, 0x9 - li x10, 0xa - li x11, 0xb - li x12, 0xc - li x13, 0xd - li x14, 0xe - li x15, 0xf - li x16, 0x10 - li x17, 0x11 - li x18, 0x12 - li x19, 0x13 - li x20, 0x14 - li x21, 0x15 - li x22, 0x16 - li x23, 0x17 - li x24, 0x18 - li x25, 0x19 - li x28, 0x1c - li x29, 0x1d - li x30, 0x1e - li x31, 0x0 - addi sp,sp,-84 - sw x6,80(sp) - sw x7,76(sp) - sw x8,72(sp) - sw x9,68(sp) - sw x10,64(sp) - sw x11,60(sp) - sw x12,56(sp) - sw x13,52(sp) - sw x14,48(sp) - sw x15,44(sp) - sw x16,40(sp) - sw x17,36(sp) - sw x18,32(sp) - sw x19,28(sp) - sw x20,24(sp) - sw x21,20(sp) - sw x22,16(sp) - sw x23,12(sp) - sw x24,8(sp) - sw x25,4(sp) -############################################################################### -# Do-nothing reads/writes to mhpmevent3..31, mhpmcounter3..31, mhpmcounterh3..31, -# to ensure that all CSR instructions ping each of these CSRs at least once. - - # mhpmevent3 - csrrci x5, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0x323, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0x323, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0x323, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0x323, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0x323, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmevent4 - csrrci x5, 0x324, 0x0a - csrrc x5, 0x324, x0 - csrrc x0, 0x324, x5 - csrrci x5, 0x324, 0x0a - csrrs x0, 0x324, x5 - csrrsi x0, 0x324, 0x0a - csrrw x0, 0x324, x0 - csrrwi x0, 0x324, 0x0a - - # mhpmevent5 - csrrci x5, 0x325, 0x0a - csrrc x5, 0x325, x0 - csrrc x0, 0x325, x5 - csrrci x5, 0x325, 0x0a - csrrs x0, 0x325, x5 - csrrsi x0, 0x325, 0x0a - csrrw x0, 0x325, x0 - csrrwi x0, 0x325, 0x0a - - # mhpmevent6 - csrrci x5, 0x326, 0x0a - csrrc x5, 0x326, x0 - csrrc x0, 0x326, x5 - csrrci x5, 0x326, 0x0a - csrrs x0, 0x326, x5 - csrrsi x0, 0x326, 0x0a - csrrw x0, 0x326, x0 - csrrwi x0, 0x326, 0x0a - - # mhpmevent7 - csrrci x5, 0x327, 0x0a - csrrc x5, 0x327, x0 - csrrc x0, 0x327, x5 - csrrci x5, 0x327, 0x0a - csrrs x0, 0x327, x5 - csrrsi x0, 0x327, 0x0a - csrrw x0, 0x327, x0 - csrrwi x0, 0x327, 0x0a - - # mhpmevent8 - csrrci x5, 0x328, 0x0a - csrrc x5, 0x328, x0 - csrrc x0, 0x328, x5 - csrrci x5, 0x328, 0x0a - csrrs x0, 0x328, x5 - csrrsi x0, 0x328, 0x0a - csrrw x0, 0x328, x0 - csrrwi x0, 0x328, 0x0a - - # mhpmevent9 - csrrci x5, 0x329, 0x0a - csrrc x5, 0x329, x0 - csrrc x0, 0x329, x5 - csrrci x5, 0x329, 0x0a - csrrs x0, 0x329, x5 - csrrsi x0, 0x329, 0x0a - csrrw x0, 0x329, x0 - csrrwi x0, 0x329, 0x0a - - # mhpmevent10 - csrrci x5, 0x32a, 0x0a - csrrc x5, 0x32a, x0 - csrrc x0, 0x32a, x5 - csrrci x5, 0x32a, 0x0a - csrrs x0, 0x32a, x5 - csrrsi x0, 0x32a, 0x0a - csrrw x0, 0x32a, x0 - csrrwi x0, 0x32a, 0x0a - - # mhpmevent11 - csrrci x5, 0x32b, 0x0a - csrrc x5, 0x32b, x0 - csrrc x0, 0x32b, x5 - csrrci x5, 0x32b, 0x0a - csrrs x0, 0x32b, x5 - csrrsi x0, 0x32b, 0x0a - csrrw x0, 0x32b, x0 - csrrwi x0, 0x32b, 0x0a - - # mhpmevent12 - csrrci x5, 0x32c, 0x0a - csrrc x5, 0x32c, x0 - csrrc x0, 0x32c, x5 - csrrci x5, 0x32c, 0x0a - csrrs x0, 0x32c, x5 - csrrsi x0, 0x32c, 0x0a - csrrw x0, 0x32c, x0 - csrrwi x0, 0x32c, 0x0a - - # mhpmevent13 - csrrci x5, 0x32d, 0x0a - csrrc x5, 0x32d, x0 - csrrc x0, 0x32d, x5 - csrrci x5, 0x32d, 0x0a - csrrs x0, 0x32d, x5 - csrrsi x0, 0x32d, 0x0a - csrrw x0, 0x32d, x0 - csrrwi x0, 0x32d, 0x0a - - # mhpmevent14 - csrrci x5, 0x32e, 0x0a - csrrc x5, 0x32e, x0 - csrrc x0, 0x32e, x5 - csrrci x5, 0x32e, 0x0a - csrrs x0, 0x32e, x5 - csrrsi x0, 0x32e, 0x0a - csrrw x0, 0x32e, x0 - csrrwi x0, 0x32e, 0x0a - - # mhpmevent15 - csrrci x5, 0x32f, 0x0a - csrrc x5, 0x32f, x0 - csrrc x0, 0x32f, x5 - csrrci x5, 0x32f, 0x0a - csrrs x0, 0x32f, x5 - csrrsi x0, 0x32f, 0x0a - csrrw x0, 0x32f, x0 - csrrwi x0, 0x32f, 0x0a - - # mhpmevent16 - csrrci x5, 0x330, 0x0a - csrrc x5, 0x330, x0 - csrrc x0, 0x330, x5 - csrrci x5, 0x330, 0x0a - csrrs x0, 0x330, x5 - csrrsi x0, 0x330, 0x0a - csrrw x0, 0x330, x0 - csrrwi x0, 0x330, 0x0a - - # mhpmevent17 - csrrci x5, 0x331, 0x0a - csrrc x5, 0x331, x0 - csrrc x0, 0x331, x5 - csrrci x5, 0x331, 0x0a - csrrs x0, 0x331, x5 - csrrsi x0, 0x331, 0x0a - csrrw x0, 0x331, x0 - csrrwi x0, 0x331, 0x0a - - # mhpmevent18 - csrrci x5, 0x332, 0x0a - csrrc x5, 0x332, x0 - csrrc x0, 0x332, x5 - csrrci x5, 0x332, 0x0a - csrrs x0, 0x332, x5 - csrrsi x0, 0x332, 0x0a - csrrw x0, 0x332, x0 - csrrwi x0, 0x332, 0x0a - - # mhpmevent19 - csrrci x5, 0x333, 0x0a - csrrc x5, 0x333, x0 - csrrc x0, 0x333, x5 - csrrci x5, 0x333, 0x0a - csrrs x0, 0x333, x5 - csrrsi x0, 0x333, 0x0a - csrrw x0, 0x333, x0 - csrrwi x0, 0x333, 0x0a - - # mhpmevent20 - csrrci x5, 0x334, 0x0a - csrrc x5, 0x334, x0 - csrrc x0, 0x334, x5 - csrrci x5, 0x334, 0x0a - csrrs x0, 0x334, x5 - csrrsi x0, 0x334, 0x0a - csrrw x0, 0x334, x0 - csrrwi x0, 0x334, 0x0a - - # mhpmevent21 - csrrci x5, 0x335, 0x0a - csrrc x5, 0x335, x0 - csrrc x0, 0x335, x5 - csrrci x5, 0x335, 0x0a - csrrs x0, 0x335, x5 - csrrsi x0, 0x335, 0x0a - csrrw x0, 0x335, x0 - csrrwi x0, 0x335, 0x0a - - # mhpmevent22 - csrrci x5, 0x336, 0x0a - csrrc x5, 0x336, x0 - csrrc x0, 0x336, x5 - csrrci x5, 0x336, 0x0a - csrrs x0, 0x336, x5 - csrrsi x0, 0x336, 0x0a - csrrw x0, 0x336, x0 - csrrwi x0, 0x336, 0x0a - - # mhpmevent23 - csrrci x5, 0x337, 0x0a - csrrc x5, 0x337, x0 - csrrc x0, 0x337, x5 - csrrci x5, 0x337, 0x0a - csrrs x0, 0x337, x5 - csrrsi x0, 0x337, 0x0a - csrrw x0, 0x337, x0 - csrrwi x0, 0x337, 0x0a - - # mhpmevent24 - csrrci x5, 0x338, 0x0a - csrrc x5, 0x338, x0 - csrrc x0, 0x338, x5 - csrrci x5, 0x338, 0x0a - csrrs x0, 0x338, x5 - csrrsi x0, 0x338, 0x0a - csrrw x0, 0x338, x0 - csrrwi x0, 0x338, 0x0a - - # mhpmevent25 - csrrci x5, 0x339, 0x0a - csrrc x5, 0x339, x0 - csrrc x0, 0x339, x5 - csrrci x5, 0x339, 0x0a - csrrs x0, 0x339, x5 - csrrsi x0, 0x339, 0x0a - csrrw x0, 0x339, x0 - csrrwi x0, 0x339, 0x0a - - # mhpmevent26 - csrrci x5, 0x33a, 0x0a - csrrc x5, 0x33a, x0 - csrrc x0, 0x33a, x5 - csrrci x5, 0x33a, 0x0a - csrrs x0, 0x33a, x5 - csrrsi x0, 0x33a, 0x0a - csrrw x0, 0x33a, x0 - csrrwi x0, 0x33a, 0x0a - - # mhpmevent27 - csrrci x5, 0x33b, 0x0a - csrrc x5, 0x33b, x0 - csrrc x0, 0x33b, x5 - csrrci x5, 0x33b, 0x0a - csrrs x0, 0x33b, x5 - csrrsi x0, 0x33b, 0x0a - csrrw x0, 0x33b, x0 - csrrwi x0, 0x33b, 0x0a - - # mhpmevent28 - csrrci x5, 0x33c, 0x0a - csrrc x5, 0x33c, x0 - csrrc x0, 0x33c, x5 - csrrci x5, 0x33c, 0x0a - csrrs x0, 0x33c, x5 - csrrsi x0, 0x33c, 0x0a - csrrw x0, 0x33c, x0 - csrrwi x0, 0x33c, 0x0a - - # mhpmevent29 - csrrci x5, 0x33d, 0x0a - csrrc x5, 0x33d, x0 - csrrc x0, 0x33d, x5 - csrrci x5, 0x33d, 0x0a - csrrs x0, 0x33d, x5 - csrrsi x0, 0x33d, 0x0a - csrrw x0, 0x33d, x0 - csrrwi x0, 0x33d, 0x0a - - # mhpmevent30 - csrrci x5, 0x33e, 0x0a - csrrc x5, 0x33e, x0 - csrrc x0, 0x33e, x5 - csrrci x5, 0x33e, 0x0a - csrrs x0, 0x33e, x5 - csrrsi x0, 0x33e, 0x0a - csrrw x0, 0x33e, x0 - csrrwi x0, 0x33e, 0x0a - - # mhpmevent31 - csrrci x5, 0x33f, 0x0a - csrrc x5, 0x33f, x0 - csrrc x0, 0x33f, x5 - csrrci x5, 0x33f, 0x0a - csrrs x0, 0x33f, x5 - csrrsi x0, 0x33f, 0x0a - csrrw x0, 0x33f, x0 - csrrwi x0, 0x33f, 0x0a - - ################ - - # mhpmcounter3 - csrrci x5, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0xB03, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0xB03, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0xB03, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0xB03, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0xB03, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmcounter4 - csrrci x5, 0xB04, 0x0a - csrrc x5, 0xB04, x0 - csrrc x0, 0xB04, x5 - csrrci x5, 0xB04, 0x0a - csrrs x0, 0xB04, x5 - csrrsi x0, 0xB04, 0x0a - csrrw x0, 0xB04, x0 - csrrwi x0, 0xB04, 0x0a - - # mhpmcounter5 - csrrci x5, 0xB05, 0x0a - csrrc x5, 0xB05, x0 - csrrc x0, 0xB05, x5 - csrrci x5, 0xB05, 0x0a - csrrs x0, 0xB05, x5 - csrrsi x0, 0xB05, 0x0a - csrrw x0, 0xB05, x0 - csrrwi x0, 0xB05, 0x0a - - # mhpmcounter6 - csrrci x5, 0xB06, 0x0a - csrrc x5, 0xB06, x0 - csrrc x0, 0xB06, x5 - csrrci x5, 0xB06, 0x0a - csrrs x0, 0xB06, x5 - csrrsi x0, 0xB06, 0x0a - csrrw x0, 0xB06, x0 - csrrwi x0, 0xB06, 0x0a - - # mhpmcounter7 - csrrci x5, 0xB07, 0x0a - csrrc x5, 0xB07, x0 - csrrc x0, 0xB07, x5 - csrrci x5, 0xB07, 0x0a - csrrs x0, 0xB07, x5 - csrrsi x0, 0xB07, 0x0a - csrrw x0, 0xB07, x0 - csrrwi x0, 0xB07, 0x0a - - # mhpmcounter8 - csrrci x5, 0xB08, 0x0a - csrrc x5, 0xB08, x0 - csrrc x0, 0xB08, x5 - csrrci x5, 0xB08, 0x0a - csrrs x0, 0xB08, x5 - csrrsi x0, 0xB08, 0x0a - csrrw x0, 0xB08, x0 - csrrwi x0, 0xB08, 0x0a - - # mhpmcounter9 - csrrci x5, 0xB09, 0x0a - csrrc x5, 0xB09, x0 - csrrc x0, 0xB09, x5 - csrrci x5, 0xB09, 0x0a - csrrs x0, 0xB09, x5 - csrrsi x0, 0xB09, 0x0a - csrrw x0, 0xB09, x0 - csrrwi x0, 0xB09, 0x0a - - # mhpmcounter10 - csrrci x5, 0xB0A, 0x0a - csrrc x5, 0xB0A, x0 - csrrc x0, 0xB0A, x5 - csrrci x5, 0xB0A, 0x0a - csrrs x0, 0xB0A, x5 - csrrsi x0, 0xB0A, 0x0a - csrrw x0, 0xB0A, x0 - csrrwi x0, 0xB0A, 0x0a - - # mhpmcounter11 - csrrci x5, 0xB0B, 0x0a - csrrc x5, 0xB0B, x0 - csrrc x0, 0xB0B, x5 - csrrci x5, 0xB0B, 0x0a - csrrs x0, 0xB0B, x5 - csrrsi x0, 0xB0B, 0x0a - csrrw x0, 0xB0B, x0 - csrrwi x0, 0xB0B, 0x0a - - # mhpmcounter12 - csrrci x5, 0xB0C, 0x0a - csrrc x5, 0xB0C, x0 - csrrc x0, 0xB0C, x5 - csrrci x5, 0xB0C, 0x0a - csrrs x0, 0xB0C, x5 - csrrsi x0, 0xB0C, 0x0a - csrrw x0, 0xB0C, x0 - csrrwi x0, 0xB0C, 0x0a - - # mhpmcounter13 - csrrci x5, 0xB0D, 0x0a - csrrc x5, 0xB0D, x0 - csrrc x0, 0xB0D, x5 - csrrci x5, 0xB0D, 0x0a - csrrs x0, 0xB0D, x5 - csrrsi x0, 0xB0D, 0x0a - csrrw x0, 0xB0D, x0 - csrrwi x0, 0xB0D, 0x0a - - # mhpmcounter14 - csrrci x5, 0xB0E, 0x0a - csrrc x5, 0xB0E, x0 - csrrc x0, 0xB0E, x5 - csrrci x5, 0xB0E, 0x0a - csrrs x0, 0xB0E, x5 - csrrsi x0, 0xB0E, 0x0a - csrrw x0, 0xB0E, x0 - csrrwi x0, 0xB0E, 0x0a - - # mhpmcounter15 - csrrci x5, 0xB0F, 0x0a - csrrc x5, 0xB0F, x0 - csrrc x0, 0xB0F, x5 - csrrci x5, 0xB0F, 0x0a - csrrs x0, 0xB0F, x5 - csrrsi x0, 0xB0F, 0x0a - csrrw x0, 0xB0F, x0 - csrrwi x0, 0xB0F, 0x0a - - # mhpmcounter16 - csrrci x5, 0xB10, 0x0a - csrrc x5, 0xB10, x0 - csrrc x0, 0xB10, x5 - csrrci x5, 0xB10, 0x0a - csrrs x0, 0xB10, x5 - csrrsi x0, 0xB10, 0x0a - csrrw x0, 0xB10, x0 - csrrwi x0, 0xB10, 0x0a - - # mhpmcounter17 - csrrci x5, 0xB11, 0x0a - csrrc x5, 0xB11, x0 - csrrc x0, 0xB11, x5 - csrrci x5, 0xB11, 0x0a - csrrs x0, 0xB11, x5 - csrrsi x0, 0xB11, 0x0a - csrrw x0, 0xB11, x0 - csrrwi x0, 0xB11, 0x0a - - # mhpmcounter18 - csrrci x5, 0xB12, 0x0a - csrrc x5, 0xB12, x0 - csrrc x0, 0xB12, x5 - csrrci x5, 0xB12, 0x0a - csrrs x0, 0xB12, x5 - csrrsi x0, 0xB12, 0x0a - csrrw x0, 0xB12, x0 - csrrwi x0, 0xB12, 0x0a - - # mhpmcounter19 - csrrci x5, 0xB13, 0x0a - csrrc x5, 0xB13, x0 - csrrc x0, 0xB13, x5 - csrrci x5, 0xB13, 0x0a - csrrs x0, 0xB13, x5 - csrrsi x0, 0xB13, 0x0a - csrrw x0, 0xB13, x0 - csrrwi x0, 0xB13, 0x0a - - # mhpmcounter20 - csrrci x5, 0xB14, 0x0a - csrrc x5, 0xB14, x0 - csrrc x0, 0xB14, x5 - csrrci x5, 0xB14, 0x0a - csrrs x0, 0xB14, x5 - csrrsi x0, 0xB14, 0x0a - csrrw x0, 0xB14, x0 - csrrwi x0, 0xB14, 0x0a - - # mhpmcounter21 - csrrci x5, 0xB15, 0x0a - csrrc x5, 0xB15, x0 - csrrc x0, 0xB15, x5 - csrrci x5, 0xB15, 0x0a - csrrs x0, 0xB15, x5 - csrrsi x0, 0xB15, 0x0a - csrrw x0, 0xB15, x0 - csrrwi x0, 0xB15, 0x0a - - # mhpmcounter22 - csrrci x5, 0xB16, 0x0a - csrrc x5, 0xB16, x0 - csrrc x0, 0xB16, x5 - csrrci x5, 0xB16, 0x0a - csrrs x0, 0xB16, x5 - csrrsi x0, 0xB16, 0x0a - csrrw x0, 0xB16, x0 - csrrwi x0, 0xB16, 0x0a - - # mhpmcounter23 - csrrci x5, 0xB17, 0x0a - csrrc x5, 0xB17, x0 - csrrc x0, 0xB17, x5 - csrrci x5, 0xB17, 0x0a - csrrs x0, 0xB17, x5 - csrrsi x0, 0xB17, 0x0a - csrrw x0, 0xB17, x0 - csrrwi x0, 0xB17, 0x0a - - # mhpmcounter24 - csrrci x5, 0xB18, 0x0a - csrrc x5, 0xB18, x0 - csrrc x0, 0xB18, x5 - csrrci x5, 0xB18, 0x0a - csrrs x0, 0xB18, x5 - csrrsi x0, 0xB18, 0x0a - csrrw x0, 0xB18, x0 - csrrwi x0, 0xB18, 0x0a - - # mhpmcounter25 - csrrci x5, 0xB19, 0x0a - csrrc x5, 0xB19, x0 - csrrc x0, 0xB19, x5 - csrrci x5, 0xB19, 0x0a - csrrs x0, 0xB19, x5 - csrrsi x0, 0xB19, 0x0a - csrrw x0, 0xB19, x0 - csrrwi x0, 0xB19, 0x0a - - # mhpmcounter26 - csrrci x5, 0xB1A, 0x0a - csrrc x5, 0xB1A, x0 - csrrc x0, 0xB1A, x5 - csrrci x5, 0xB1A, 0x0a - csrrs x0, 0xB1A, x5 - csrrsi x0, 0xB1A, 0x0a - csrrw x0, 0xB1A, x0 - csrrwi x0, 0xB1A, 0x0a - - # mhpmcounter27 - csrrci x5, 0xB1B, 0x0a - csrrc x5, 0xB1B, x0 - csrrc x0, 0xB1B, x5 - csrrci x5, 0xB1B, 0x0a - csrrs x0, 0xB1B, x5 - csrrsi x0, 0xB1B, 0x0a - csrrw x0, 0xB1B, x0 - csrrwi x0, 0xB1B, 0x0a - - # mhpmcounter28 - csrrci x5, 0xB1C, 0x0a - csrrc x5, 0xB1C, x0 - csrrc x0, 0xB1C, x5 - csrrci x5, 0xB1C, 0x0a - csrrs x0, 0xB1C, x5 - csrrsi x0, 0xB1C, 0x0a - csrrw x0, 0xB1C, x0 - csrrwi x0, 0xB1C, 0x0a - - # mhpmcounter29 - csrrci x5, 0xB1D, 0x0a - csrrc x5, 0xB1D, x0 - csrrc x0, 0xB1D, x5 - csrrci x5, 0xB1D, 0x0a - csrrs x0, 0xB1D, x5 - csrrsi x0, 0xB1D, 0x0a - csrrw x0, 0xB1D, x0 - csrrwi x0, 0xB1D, 0x0a - - # mhpmcounter30 - csrrci x5, 0xB1E, 0x0a - csrrc x5, 0xB1E, x0 - csrrc x0, 0xB1E, x5 - csrrci x5, 0xB1E, 0x0a - csrrs x0, 0xB1E, x5 - csrrsi x0, 0xB1E, 0x0a - csrrw x0, 0xB1E, x0 - csrrwi x0, 0xB1E, 0x0a - - # mhpmcounter31 - csrrci x5, 0xB1F, 0x0a - csrrc x5, 0xB1F, x0 - csrrc x0, 0xB1F, x5 - csrrci x5, 0xB1F, 0x0a - csrrs x0, 0xB1F, x5 - csrrsi x0, 0xB1F, 0x0a - csrrw x0, 0xB1F, x0 - csrrwi x0, 0xB1F, 0x0a - - ################ - - # mhpmcounter3h - csrrci x5, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0xB83, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0xB83, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0xB83, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0xB83, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0xB83, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmcounter4h - csrrci x5, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - csrrc x5, 0xB84, x0 # not illegal instruction: no attempt to write CSR - csrrc x0, 0xB84, x5 # not illegal instruction: attempt to write RW CSR - csrrci x5, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - csrrs x0, 0xB84, x5 # not illegal instruction: attempt to write RW CSR - csrrsi x0, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - csrrw x0, 0xB84, x0 # not illegal instruction: attempt to write RW CSR - csrrwi x0, 0xB84, 0x0a # not illegal instruction: attempt to write RW CSR - - # mhpmcounterh5 - csrrci x5, 0xB85, 0x0a - csrrc x5, 0xB85, x0 - csrrc x0, 0xB85, x5 - csrrci x5, 0xB85, 0x0a - csrrs x0, 0xB85, x5 - csrrsi x0, 0xB85, 0x0a - csrrw x0, 0xB85, x0 - csrrwi x0, 0xB85, 0x0a - - # mhpmcounterh6 - csrrci x5, 0xB86, 0x0a - csrrc x5, 0xB86, x0 - csrrc x0, 0xB86, x5 - csrrci x5, 0xB86, 0x0a - csrrs x0, 0xB86, x5 - csrrsi x0, 0xB86, 0x0a - csrrw x0, 0xB86, x0 - csrrwi x0, 0xB86, 0x0a - - # mhpmcounterh7 - csrrci x5, 0xB87, 0x0a - csrrc x5, 0xB87, x0 - csrrc x0, 0xB87, x5 - csrrci x5, 0xB87, 0x0a - csrrs x0, 0xB87, x5 - csrrsi x0, 0xB87, 0x0a - csrrw x0, 0xB87, x0 - csrrwi x0, 0xB87, 0x0a - - # mhpmcounterh8 - csrrci x5, 0xB88, 0x0a - csrrc x5, 0xB88, x0 - csrrc x0, 0xB88, x5 - csrrci x5, 0xB88, 0x0a - csrrs x0, 0xB88, x5 - csrrsi x0, 0xB88, 0x0a - csrrw x0, 0xB88, x0 - csrrwi x0, 0xB88, 0x0a - - # mhpmcounterh9 - csrrci x5, 0xB89, 0x0a - csrrc x5, 0xB89, x0 - csrrc x0, 0xB89, x5 - csrrci x5, 0xB89, 0x0a - csrrs x0, 0xB89, x5 - csrrsi x0, 0xB89, 0x0a - csrrw x0, 0xB89, x0 - csrrwi x0, 0xB89, 0x0a - - # mhpmcounterh10 - csrrci x5, 0xB8A, 0x0a - csrrc x5, 0xB8A, x0 - csrrc x0, 0xB8A, x5 - csrrci x5, 0xB8A, 0x0a - csrrs x0, 0xB8A, x5 - csrrsi x0, 0xB8A, 0x0a - csrrw x0, 0xB8A, x0 - csrrwi x0, 0xB8A, 0x0a - - # mhpmcounterh11 - csrrci x5, 0xB8B, 0x0a - csrrc x5, 0xB8B, x0 - csrrc x0, 0xB8B, x5 - csrrci x5, 0xB8B, 0x0a - csrrs x0, 0xB8B, x5 - csrrsi x0, 0xB8B, 0x0a - csrrw x0, 0xB8B, x0 - csrrwi x0, 0xB8B, 0x0a - - # mhpmcounterh12 - csrrci x5, 0xB8C, 0x0a - csrrc x5, 0xB8C, x0 - csrrc x0, 0xB8C, x5 - csrrci x5, 0xB8C, 0x0a - csrrs x0, 0xB8C, x5 - csrrsi x0, 0xB8C, 0x0a - csrrw x0, 0xB8C, x0 - csrrwi x0, 0xB8C, 0x0a - - # mhpmcounterh13 - csrrci x5, 0xB8D, 0x0a - csrrc x5, 0xB8D, x0 - csrrc x0, 0xB8D, x5 - csrrci x5, 0xB8D, 0x0a - csrrs x0, 0xB8D, x5 - csrrsi x0, 0xB8D, 0x0a - csrrw x0, 0xB8D, x0 - csrrwi x0, 0xB8D, 0x0a - - # mhpmcounterh14 - csrrci x5, 0xB8E, 0x0a - csrrc x5, 0xB8E, x0 - csrrc x0, 0xB8E, x5 - csrrci x5, 0xB8E, 0x0a - csrrs x0, 0xB8E, x5 - csrrsi x0, 0xB8E, 0x0a - csrrw x0, 0xB8E, x0 - csrrwi x0, 0xB8E, 0x0a - - # mhpmcounterh15 - csrrci x5, 0xB8F, 0x0a - csrrc x5, 0xB8F, x0 - csrrc x0, 0xB8F, x5 - csrrci x5, 0xB8F, 0x0a - csrrs x0, 0xB8F, x5 - csrrsi x0, 0xB8F, 0x0a - csrrw x0, 0xB8F, x0 - csrrwi x0, 0xB8F, 0x0a - - # mhpmcounterh16 - csrrci x5, 0xB90, 0x0a - csrrc x5, 0xB90, x0 - csrrc x0, 0xB90, x5 - csrrci x5, 0xB90, 0x0a - csrrs x0, 0xB90, x5 - csrrsi x0, 0xB90, 0x0a - csrrw x0, 0xB90, x0 - csrrwi x0, 0xB90, 0x0a - - # mhpmcounterh17 - csrrci x5, 0xB91, 0x0a - csrrc x5, 0xB91, x0 - csrrc x0, 0xB91, x5 - csrrci x5, 0xB91, 0x0a - csrrs x0, 0xB91, x5 - csrrsi x0, 0xB91, 0x0a - csrrw x0, 0xB91, x0 - csrrwi x0, 0xB91, 0x0a - - # mhpmcounterh18 - csrrci x5, 0xB92, 0x0a - csrrc x5, 0xB92, x0 - csrrc x0, 0xB92, x5 - csrrci x5, 0xB92, 0x0a - csrrs x0, 0xB92, x5 - csrrsi x0, 0xB92, 0x0a - csrrw x0, 0xB92, x0 - csrrwi x0, 0xB92, 0x0a - - # mhpmcounterh19 - csrrci x5, 0xB93, 0x0a - csrrc x5, 0xB93, x0 - csrrc x0, 0xB93, x5 - csrrci x5, 0xB93, 0x0a - csrrs x0, 0xB93, x5 - csrrsi x0, 0xB93, 0x0a - csrrw x0, 0xB93, x0 - csrrwi x0, 0xB93, 0x0a - - # mhpmcounterh20 - csrrci x5, 0xB94, 0x0a - csrrc x5, 0xB94, x0 - csrrc x0, 0xB94, x5 - csrrci x5, 0xB94, 0x0a - csrrs x0, 0xB94, x5 - csrrsi x0, 0xB94, 0x0a - csrrw x0, 0xB94, x0 - csrrwi x0, 0xB94, 0x0a - - # mhpmcounterh21 - csrrci x5, 0xB95, 0x0a - csrrc x5, 0xB95, x0 - csrrc x0, 0xB95, x5 - csrrci x5, 0xB95, 0x0a - csrrs x0, 0xB95, x5 - csrrsi x0, 0xB95, 0x0a - csrrw x0, 0xB95, x0 - csrrwi x0, 0xB95, 0x0a - - # mhpmcounterh22 - csrrci x5, 0xB96, 0x0a - csrrc x5, 0xB96, x0 - csrrc x0, 0xB96, x5 - csrrci x5, 0xB96, 0x0a - csrrs x0, 0xB96, x5 - csrrsi x0, 0xB96, 0x0a - csrrw x0, 0xB96, x0 - csrrwi x0, 0xB96, 0x0a - - # mhpmcounterh23 - csrrci x5, 0xB97, 0x0a - csrrc x5, 0xB97, x0 - csrrc x0, 0xB97, x5 - csrrci x5, 0xB97, 0x0a - csrrs x0, 0xB97, x5 - csrrsi x0, 0xB97, 0x0a - csrrw x0, 0xB97, x0 - csrrwi x0, 0xB97, 0x0a - - # mhpmcounterh24 - csrrci x5, 0xB98, 0x0a - csrrc x5, 0xB98, x0 - csrrc x0, 0xB98, x5 - csrrci x5, 0xB98, 0x0a - csrrs x0, 0xB98, x5 - csrrsi x0, 0xB98, 0x0a - csrrw x0, 0xB98, x0 - csrrwi x0, 0xB98, 0x0a - - # mhpmcounterh25 - csrrci x5, 0xB99, 0x0a - csrrc x5, 0xB99, x0 - csrrc x0, 0xB99, x5 - csrrci x5, 0xB99, 0x0a - csrrs x0, 0xB99, x5 - csrrsi x0, 0xB99, 0x0a - csrrw x0, 0xB99, x0 - csrrwi x0, 0xB99, 0x0a - - # mhpmcounterh26 - csrrci x5, 0xB9A, 0x0a - csrrc x5, 0xB9A, x0 - csrrc x0, 0xB9A, x5 - csrrci x5, 0xB9A, 0x0a - csrrs x0, 0xB9A, x5 - csrrsi x0, 0xB9A, 0x0a - csrrw x0, 0xB9A, x0 - csrrwi x0, 0xB9A, 0x0a - - # mhpmcounterh27 - csrrci x5, 0xB9B, 0x0a - csrrc x5, 0xB9B, x0 - csrrc x0, 0xB9B, x5 - csrrci x5, 0xB9B, 0x0a - csrrs x0, 0xB9B, x5 - csrrsi x0, 0xB9B, 0x0a - csrrw x0, 0xB9B, x0 - csrrwi x0, 0xB9B, 0x0a - - # mhpmcounterh28 - csrrci x5, 0xB9C, 0x0a - csrrc x5, 0xB9C, x0 - csrrc x0, 0xB9C, x5 - csrrci x5, 0xB9C, 0x0a - csrrs x0, 0xB9C, x5 - csrrsi x0, 0xB9C, 0x0a - csrrw x0, 0xB9C, x0 - csrrwi x0, 0xB9C, 0x0a - - # mhpmcounterh29 - csrrci x5, 0xB9D, 0x0a - csrrc x5, 0xB9D, x0 - csrrc x0, 0xB9D, x5 - csrrci x5, 0xB9D, 0x0a - csrrs x0, 0xB9D, x5 - csrrsi x0, 0xB9D, 0x0a - csrrw x0, 0xB9D, x0 - csrrwi x0, 0xB9D, 0x0a - - # mhpmcounterh30 - csrrci x5, 0xB9E, 0x0a - csrrc x5, 0xB9E, x0 - csrrc x0, 0xB9E, x5 - csrrci x5, 0xB9E, 0x0a - csrrs x0, 0xB9E, x5 - csrrsi x0, 0xB9E, 0x0a - csrrw x0, 0xB9E, x0 - csrrwi x0, 0xB9E, 0x0a - - # mhpmcounterh31 - csrrci x5, 0xB9F, 0x0a - csrrc x5, 0xB9F, x0 - csrrc x0, 0xB9F, x5 - csrrci x5, 0xB9F, 0x0a - csrrs x0, 0xB9F, x5 - csrrsi x0, 0xB9F, 0x0a - csrrw x0, 0xB9F, x0 - csrrwi x0, 0xB9F, 0x0a - -############################################################################### -# Access a few other CSRs, including accesses that throw illegal instruction -# exceptions. - - # mvendorid - csrrc x5, 3857, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3857, x5 # illegal instruction: attempt to write RO CSR - csrrci x5, 3857, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3857, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3857, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3857, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3857, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3857, x0 # not illegal - li x30, 0x00000602 - bne x5, x30, fail - - # marchid - csrrc x5, 3858, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3858, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 3858, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3858, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3858, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3858, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3858, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3858, x0 # not illegal - li x30, 0x00000014 - bne x5, x30, fail - - # mipmid - csrrc x5, 3859, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3859, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3859, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3859, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3859, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3859, x0 # not illegal - li x30, 0x00000000 - bne x5, x30, fail - - # mhartid - csrrc x5, 3860, x0 # not illegal instruction: no attempt to write RO CSR - csrrc x0, 3860, x5 # illegal instruction: attempt to write RO CSR - csrrci x0, 3860, 0x0a # illegal instruction: attempt to write RO CSR - csrrs x0, 3860, x5 # illegal instruction: attempt to write RO CSR - csrrsi x0, 3860, 0x0a # illegal instruction: attempt to write RO CSR - csrrw x0, 3860, x0 # illegal instruction: attempt to write RO CSR - csrrwi x0, 3860, 0x0a # illegal instruction: attempt to write RO CSR - - csrrc x5, 3860, x0 # not illegal - li x30, 0x00000000 - bne x5, x30, fail - -############################################################################### - lw x5,80(sp) - bne x5, x6, fail - lw x5,76(sp) - bne x5, x7, fail - lw x5,72(sp) - bne x5, x8, fail - lw x5,68(sp) - bne x5, x9, fail - lw x5,64(sp) - bne x5, x10, fail - lw x5,60(sp) - bne x5, x11, fail - lw x5,56(sp) - bne x5, x12, fail - lw x5,52(sp) - bne x5, x13, fail - lw x5,48(sp) - bne x5, x14, fail - lw x5,44(sp) - bne x5, x15, fail - lw x5,40(sp) - bne x5, x16, fail - lw x5,36(sp) - bne x5, x17, fail - lw x5,32(sp) - bne x5, x18, fail - lw x5,28(sp) - bne x5, x19, fail - lw x5,24(sp) - bne x5, x20, fail - lw x5,20(sp) - bne x5, x21, fail - lw x5,16(sp) - bne x5, x22, fail - lw x5,12(sp) - bne x5, x23, fail - lw x5,8(sp) - bne x5, x24, fail - lw x5,4(sp) - bne x5, x25, fail - addi sp,sp,84 - li x18, TEST_PASS - li x16, EXPECTED_ILLEGAL_INSTRUCTIONS - beq x31, x16, test_end -csr_fail: -fail: - li x18, TEST_FAIL -test_end: - li x17, VIRT_PERIPH_STATUS_FLAG_ADDR - sw x18,0(x17) - j _exit - -# The "sw_irq_handler" is entered on each illegal instruction. Clears -# mepc and increments the illegal instruction count in x31. -u_sw_irq_handler: - li x30, 0xf - csrrc x29, mcause, x0 - and x30, x29, x30 - li x28, 2 - bne x30, x28, _exit - csrrc x27, mepc, x0 - c.addi x27, 4 - csrrw x0, mepc, x27 - c.addi x31, 1 - mret - -_exit: - j _exit - -debug: - j _exit diff --git a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_1/test.yaml b/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_1/test.yaml deleted file mode 100644 index 8263bbc669..0000000000 --- a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_1/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: mhpmcounter29_csr_access_test_1 -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR access test with NUM_MHPMCOUNTER = 29 (FIXME ISS does not set correct reset value for mcountinhibit) diff --git a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S b/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S deleted file mode 100644 index bedebffd43..0000000000 --- a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_2/mhpmcounter29_csr_access_test_2.S +++ /dev/null @@ -1,5701 +0,0 @@ -# -# Copyright (C) EM Microelectronic US Inc. -# Copyright (C) 2020 OpenHW Group -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. -# -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 -# -############################################################################### -# MHPMCOUNTERS29: access testcase for mhpmcounter3..31 CSRs in cv32e40x. -# Notes: -# 1. This test requires NUM_MHPMCOUNTERS set to 29. -# 2. Does not test function - just access. -# 3. FIXME: ISS currently does not set mcountinhibit correctly on reset -# for non-default number of registers, RVVI and RVFI will mismatch if -# sb checking is enabled. -############################################################################### -#include "corev_uvmt.h" - -.include "user_define.h" -.section .text.start -.globl _start -.section .text -#.include "user_init.s" -.type _start, @function - -_start: - j _start_main - -.globl _start_main -.section .text -_start_main: - - #define EXP_MISA 0x40001104 - - -############################################################################### -# Script generated code to verify write/read access of these CSRs. -#start - # mhpmevent3 - li x12, 0xa5a5a5a5 - csrrw x14, 803, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 803, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x5599ca67 - csrrw x14, 803, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 803, x12 - li x12, 0x0000ca67 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 803, x12 - li x12, 0x0000efe7 - bne x12, x14, csr_fail - li x12, 0x943b6954 - csrrs x14, 803, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 803, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 803, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x7c4c5d22 - csrrc x14, 803, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 803, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 803, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 803, 0b01010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 803, 0b00101 - li x12, 0x0000000a - bne x12, x14, csr_fail - csrrsi x14, 803, 0b11010 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 803, 0b11100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 803, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 803, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 803, 0b10110 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent4 - li x12, 0xa5a5a5a5 - csrrw x14, 804, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 804, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x192b5afa - csrrw x14, 804, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 804, x12 - li x12, 0x00005afa - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 804, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x86015c6d - csrrs x14, 804, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 804, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 804, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x029db46e - csrrc x14, 804, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 804, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 804, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 804, 0b10111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 804, 0b00101 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 804, 0b11010 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 804, 0b11000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 804, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 804, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 804, 0b10111 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent5 - li x12, 0xa5a5a5a5 - csrrw x14, 805, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 805, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xe3ab797d - csrrw x14, 805, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 805, x12 - li x12, 0x0000797d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 805, x12 - li x12, 0x0000fdfd - bne x12, x14, csr_fail - li x12, 0x3d002294 - csrrs x14, 805, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 805, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 805, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x1e882616 - csrrc x14, 805, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 805, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 805, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 805, 0b00001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 805, 0b00101 - li x12, 0x00000001 - bne x12, x14, csr_fail - csrrsi x14, 805, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 805, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 805, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 805, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 805, 0b01001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent6 - li x12, 0xa5a5a5a5 - csrrw x14, 806, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 806, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xbbaff885 - csrrw x14, 806, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 806, x12 - li x12, 0x0000f885 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 806, x12 - li x12, 0x0000fda5 - bne x12, x14, csr_fail - li x12, 0x3c6f2d52 - csrrs x14, 806, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 806, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 806, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x809d900c - csrrc x14, 806, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 806, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 806, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 806, 0b11001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 806, 0b00101 - li x12, 0x00000019 - bne x12, x14, csr_fail - csrrsi x14, 806, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 806, 0b11001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 806, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 806, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 806, 0b11101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent7 - li x12, 0xa5a5a5a5 - csrrw x14, 807, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 807, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xf550d5ab - csrrw x14, 807, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 807, x12 - li x12, 0x0000d5ab - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 807, x12 - li x12, 0x0000f5af - bne x12, x14, csr_fail - li x12, 0xe62f0e49 - csrrs x14, 807, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 807, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 807, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x5f55ce76 - csrrc x14, 807, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 807, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 807, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 807, 0b00100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 807, 0b00101 - li x12, 0x00000004 - bne x12, x14, csr_fail - csrrsi x14, 807, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 807, 0b11001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 807, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 807, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 807, 0b11100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent8 - li x12, 0xa5a5a5a5 - csrrw x14, 808, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 808, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x36cd731a - csrrw x14, 808, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 808, x12 - li x12, 0x0000731a - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 808, x12 - li x12, 0x0000f7bf - bne x12, x14, csr_fail - li x12, 0x578155b4 - csrrs x14, 808, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 808, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 808, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x21794a9c - csrrc x14, 808, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 808, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 808, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 808, 0b11011 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 808, 0b00101 - li x12, 0x0000001b - bne x12, x14, csr_fail - csrrsi x14, 808, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 808, 0b10000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 808, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 808, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 808, 0b11011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent9 - li x12, 0xa5a5a5a5 - csrrw x14, 809, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 809, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x4df46846 - csrrw x14, 809, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 809, x12 - li x12, 0x00006846 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 809, x12 - li x12, 0x0000ede7 - bne x12, x14, csr_fail - li x12, 0x46e6d02b - csrrs x14, 809, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 809, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 809, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xb07c4e41 - csrrc x14, 809, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 809, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 809, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 809, 0b00100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 809, 0b00101 - li x12, 0x00000004 - bne x12, x14, csr_fail - csrrsi x14, 809, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 809, 0b00011 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 809, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 809, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 809, 0b00100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent10 - li x12, 0xa5a5a5a5 - csrrw x14, 810, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 810, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x249666b3 - csrrw x14, 810, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 810, x12 - li x12, 0x000066b3 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 810, x12 - li x12, 0x0000e7b7 - bne x12, x14, csr_fail - li x12, 0x5a36a091 - csrrs x14, 810, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 810, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 810, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xf26df110 - csrrc x14, 810, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 810, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 810, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 810, 0b11001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 810, 0b00101 - li x12, 0x00000019 - bne x12, x14, csr_fail - csrrsi x14, 810, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 810, 0b01100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 810, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 810, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 810, 0b10011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent11 - li x12, 0xa5a5a5a5 - csrrw x14, 811, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 811, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xaf9407ee - csrrw x14, 811, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 811, x12 - li x12, 0x000007ee - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 811, x12 - li x12, 0x0000a7ef - bne x12, x14, csr_fail - li x12, 0x9c1024e8 - csrrs x14, 811, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 811, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 811, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x823a6c57 - csrrc x14, 811, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 811, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 811, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 811, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 811, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 811, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 811, 0b10100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 811, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 811, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 811, 0b11010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent12 - li x12, 0xa5a5a5a5 - csrrw x14, 812, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 812, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xb3cd262d - csrrw x14, 812, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 812, x12 - li x12, 0x0000262d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 812, x12 - li x12, 0x0000a7ad - bne x12, x14, csr_fail - li x12, 0xd44e7e03 - csrrs x14, 812, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 812, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 812, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xfe9717de - csrrc x14, 812, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 812, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 812, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 812, 0b10111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 812, 0b00101 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 812, 0b11010 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 812, 0b01101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 812, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 812, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 812, 0b11011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent13 - li x12, 0xa5a5a5a5 - csrrw x14, 813, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 813, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xeb86004c - csrrw x14, 813, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 813, x12 - li x12, 0x0000004c - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 813, x12 - li x12, 0x0000a5ed - bne x12, x14, csr_fail - li x12, 0x8f03af04 - csrrs x14, 813, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 813, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 813, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xd665472c - csrrc x14, 813, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 813, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 813, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 813, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 813, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 813, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 813, 0b00000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 813, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 813, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 813, 0b00000 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent14 - li x12, 0xa5a5a5a5 - csrrw x14, 814, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 814, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xc25aaf9d - csrrw x14, 814, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 814, x12 - li x12, 0x0000af9d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 814, x12 - li x12, 0x0000afbd - bne x12, x14, csr_fail - li x12, 0x6232f2cf - csrrs x14, 814, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 814, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 814, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xab4c8b27 - csrrc x14, 814, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 814, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 814, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 814, 0b00111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 814, 0b00101 - li x12, 0x00000007 - bne x12, x14, csr_fail - csrrsi x14, 814, 0b11010 - li x12, 0x00000007 - bne x12, x14, csr_fail - csrrsi x14, 814, 0b10001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 814, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 814, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 814, 0b00100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent15 - li x12, 0xa5a5a5a5 - csrrw x14, 815, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 815, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xfc450eb6 - csrrw x14, 815, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 815, x12 - li x12, 0x00000eb6 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 815, x12 - li x12, 0x0000afb7 - bne x12, x14, csr_fail - li x12, 0xdf21d66b - csrrs x14, 815, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 815, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 815, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x5d877b70 - csrrc x14, 815, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 815, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 815, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 815, 0b01111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 815, 0b00101 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 815, 0b11010 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 815, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 815, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 815, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 815, 0b01001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent16 - li x12, 0xa5a5a5a5 - csrrw x14, 816, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 816, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x60c43ac1 - csrrw x14, 816, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 816, x12 - li x12, 0x00003ac1 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 816, x12 - li x12, 0x0000bfe5 - bne x12, x14, csr_fail - li x12, 0xa353dd27 - csrrs x14, 816, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 816, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 816, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x25d46c45 - csrrc x14, 816, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 816, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 816, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 816, 0b01010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 816, 0b00101 - li x12, 0x0000000a - bne x12, x14, csr_fail - csrrsi x14, 816, 0b11010 - li x12, 0x0000000f - bne x12, x14, csr_fail - csrrsi x14, 816, 0b00010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 816, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 816, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 816, 0b00010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent17 - li x12, 0xa5a5a5a5 - csrrw x14, 817, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 817, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x6d77c506 - csrrw x14, 817, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 817, x12 - li x12, 0x0000c506 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 817, x12 - li x12, 0x0000e5a7 - bne x12, x14, csr_fail - li x12, 0x615f4a97 - csrrs x14, 817, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 817, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 817, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xaba4a7c0 - csrrc x14, 817, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 817, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 817, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 817, 0b11101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 817, 0b00101 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 817, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 817, 0b10110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 817, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 817, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 817, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent18 - li x12, 0xa5a5a5a5 - csrrw x14, 818, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 818, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xa006a626 - csrrw x14, 818, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 818, x12 - li x12, 0x0000a626 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 818, x12 - li x12, 0x0000a7a7 - bne x12, x14, csr_fail - li x12, 0x4a2ebbef - csrrs x14, 818, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 818, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 818, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa4d3b6b3 - csrrc x14, 818, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 818, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 818, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 818, 0b00100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 818, 0b00101 - li x12, 0x00000004 - bne x12, x14, csr_fail - csrrsi x14, 818, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 818, 0b01011 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 818, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 818, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 818, 0b00010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent19 - li x12, 0xa5a5a5a5 - csrrw x14, 819, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 819, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x2db1490a - csrrw x14, 819, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 819, x12 - li x12, 0x0000490a - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 819, x12 - li x12, 0x0000edaf - bne x12, x14, csr_fail - li x12, 0x48747d08 - csrrs x14, 819, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 819, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 819, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa0f18bd1 - csrrc x14, 819, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 819, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 819, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 819, 0b11111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 819, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 819, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 819, 0b11110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 819, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 819, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 819, 0b00011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent20 - li x12, 0xa5a5a5a5 - csrrw x14, 820, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 820, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xd9df844d - csrrw x14, 820, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 820, x12 - li x12, 0x0000844d - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 820, x12 - li x12, 0x0000a5ed - bne x12, x14, csr_fail - li x12, 0xde339ea9 - csrrs x14, 820, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 820, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 820, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa6382e89 - csrrc x14, 820, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 820, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 820, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 820, 0b01101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 820, 0b00101 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 820, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 820, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 820, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 820, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 820, 0b01001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent21 - li x12, 0xa5a5a5a5 - csrrw x14, 821, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 821, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x8a23cad8 - csrrw x14, 821, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 821, x12 - li x12, 0x0000cad8 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 821, x12 - li x12, 0x0000effd - bne x12, x14, csr_fail - li x12, 0xe23ee27b - csrrs x14, 821, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 821, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 821, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xce9f2bb9 - csrrc x14, 821, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 821, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 821, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 821, 0b11101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 821, 0b00101 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 821, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 821, 0b01000 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 821, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 821, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 821, 0b11000 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent22 - li x12, 0xa5a5a5a5 - csrrw x14, 822, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 822, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x7942fd02 - csrrw x14, 822, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 822, x12 - li x12, 0x0000fd02 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 822, x12 - li x12, 0x0000fda7 - bne x12, x14, csr_fail - li x12, 0x67a9e836 - csrrs x14, 822, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 822, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 822, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xbd53627f - csrrc x14, 822, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 822, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 822, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 822, 0b00101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 822, 0b00101 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 822, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 822, 0b01010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 822, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 822, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 822, 0b10011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent23 - li x12, 0xa5a5a5a5 - csrrw x14, 823, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 823, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x297f98b8 - csrrw x14, 823, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 823, x12 - li x12, 0x000098b8 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 823, x12 - li x12, 0x0000bdbd - bne x12, x14, csr_fail - li x12, 0x122088b3 - csrrs x14, 823, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 823, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 823, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x848ec6e4 - csrrc x14, 823, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 823, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 823, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 823, 0b00110 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 823, 0b00101 - li x12, 0x00000006 - bne x12, x14, csr_fail - csrrsi x14, 823, 0b11010 - li x12, 0x00000007 - bne x12, x14, csr_fail - csrrsi x14, 823, 0b01111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 823, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 823, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 823, 0b10011 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent24 - li x12, 0xa5a5a5a5 - csrrw x14, 824, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 824, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xf48c6acd - csrrw x14, 824, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 824, x12 - li x12, 0x00006acd - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 824, x12 - li x12, 0x0000efed - bne x12, x14, csr_fail - li x12, 0x32d05494 - csrrs x14, 824, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 824, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 824, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xbc98c71d - csrrc x14, 824, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 824, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 824, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 824, 0b10111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 824, 0b00101 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 824, 0b11010 - li x12, 0x00000017 - bne x12, x14, csr_fail - csrrsi x14, 824, 0b00110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 824, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 824, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 824, 0b00100 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent25 - li x12, 0xa5a5a5a5 - csrrw x14, 825, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 825, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x5f668177 - csrrw x14, 825, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 825, x12 - li x12, 0x00008177 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 825, x12 - li x12, 0x0000a5f7 - bne x12, x14, csr_fail - li x12, 0x73970670 - csrrs x14, 825, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 825, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 825, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa1adae60 - csrrc x14, 825, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 825, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 825, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 825, 0b01001 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 825, 0b00101 - li x12, 0x00000009 - bne x12, x14, csr_fail - csrrsi x14, 825, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 825, 0b01001 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 825, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 825, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 825, 0b10101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent26 - li x12, 0xa5a5a5a5 - csrrw x14, 826, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 826, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xd6668cc8 - csrrw x14, 826, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 826, x12 - li x12, 0x00008cc8 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 826, x12 - li x12, 0x0000aded - bne x12, x14, csr_fail - li x12, 0xbd9ed990 - csrrs x14, 826, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 826, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 826, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xcedecfcd - csrrc x14, 826, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 826, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 826, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 826, 0b11100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 826, 0b00101 - li x12, 0x0000001c - bne x12, x14, csr_fail - csrrsi x14, 826, 0b11010 - li x12, 0x0000001d - bne x12, x14, csr_fail - csrrsi x14, 826, 0b11100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 826, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 826, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 826, 0b10001 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent27 - li x12, 0xa5a5a5a5 - csrrw x14, 827, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 827, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xa425e498 - csrrw x14, 827, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 827, x12 - li x12, 0x0000e498 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 827, x12 - li x12, 0x0000e5bd - bne x12, x14, csr_fail - li x12, 0x3556abe1 - csrrs x14, 827, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 827, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 827, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xbf4d3dd4 - csrrc x14, 827, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 827, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 827, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 827, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 827, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 827, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 827, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 827, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 827, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 827, 0b10111 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent28 - li x12, 0xa5a5a5a5 - csrrw x14, 828, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 828, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x356e8358 - csrrw x14, 828, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 828, x12 - li x12, 0x00008358 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 828, x12 - li x12, 0x0000a7fd - bne x12, x14, csr_fail - li x12, 0x60d5d1c4 - csrrs x14, 828, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 828, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 828, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x3f6d5395 - csrrc x14, 828, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 828, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 828, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 828, 0b00101 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 828, 0b00101 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 828, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrsi x14, 828, 0b01110 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 828, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 828, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 828, 0b11101 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent29 - li x12, 0xa5a5a5a5 - csrrw x14, 829, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 829, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x5f596028 - csrrw x14, 829, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 829, x12 - li x12, 0x00006028 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 829, x12 - li x12, 0x0000e5ad - bne x12, x14, csr_fail - li x12, 0x61430933 - csrrs x14, 829, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 829, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 829, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x6717a138 - csrrc x14, 829, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 829, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 829, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 829, 0b01100 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 829, 0b00101 - li x12, 0x0000000c - bne x12, x14, csr_fail - csrrsi x14, 829, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 829, 0b11100 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 829, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 829, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 829, 0b11110 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent30 - li x12, 0xa5a5a5a5 - csrrw x14, 830, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 830, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0x28c0c58e - csrrw x14, 830, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 830, x12 - li x12, 0x0000c58e - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 830, x12 - li x12, 0x0000e5af - bne x12, x14, csr_fail - li x12, 0x32370e52 - csrrs x14, 830, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 830, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 830, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x8d540cb7 - csrrc x14, 830, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 830, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 830, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 830, 0b11111 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 830, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 830, 0b11010 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrsi x14, 830, 0b10111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 830, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 830, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 830, 0b00010 - li x12, 0x00000000 - bne x12, x14, csr_fail - # mhpmevent31 - li x12, 0xa5a5a5a5 - csrrw x14, 831, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrw x14, 831, x12 - li x12, 0x0000a5a5 - bne x12, x14, csr_fail - li x12, 0xfb37c936 - csrrw x14, 831, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrs x14, 831, x12 - li x12, 0x0000c936 - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrs x14, 831, x12 - li x12, 0x0000edb7 - bne x12, x14, csr_fail - li x12, 0x8e300970 - csrrs x14, 831, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0xa5a5a5a5 - csrrc x14, 831, x12 - li x12, 0x0000ffff - bne x12, x14, csr_fail - li x12, 0x5a5a5a5a - csrrc x14, 831, x12 - li x12, 0x00005a5a - bne x12, x14, csr_fail - li x12, 0x6056a394 - csrrc x14, 831, x12 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 831, 0b00101 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrrwi x14, 831, 0b11010 - li x12, 0x00000005 - bne x12, x14, csr_fail - csrrwi x14, 831, 0b01000 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrsi x14, 831, 0b00101 - li x12, 0x00000008 - bne x12, x14, csr_fail - csrrsi x14, 831, 0b11010 - li x12, 0x0000000d - bne x12, x14, csr_fail - csrrsi x14, 831, 0b11111 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 831, 0b00101 - li x12, 0x0000001f - bne x12, x14, csr_fail - csrrci x14, 831, 0b11010 - li x12, 0x0000001a - bne x12, x14, csr_fail - csrrci x14, 831, 0b00000 - li x12, 0x00000000 - bne x12, x14, csr_fail - csrr x14, 831 - li x12, 0x00000000 - bne x12, x14, csr_fail -############################################################################### - # mhpmcounter3 - li x13, 0xa5a5a5a5 - csrrw x11, 2819, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2819, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x58d817e6 - csrrw x11, 2819, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2819, x13 - li x13, 0x58d817e6 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2819, x13 - li x13, 0xfdfdb7e7 - bne x13, x11, csr_fail - li x13, 0x11b4174c - csrrs x11, 2819, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2819, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2819, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x60f899eb - csrrc x11, 2819, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2819, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2819, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2819, 0b01110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2819, 0b00101 - li x13, 0x0000000e - bne x13, x11, csr_fail - csrrsi x11, 2819, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2819, 0b10011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2819, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2819, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2819, 0b10101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter4 - li x13, 0xa5a5a5a5 - csrrw x11, 2820, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2820, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xd62407a2 - csrrw x11, 2820, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2820, x13 - li x13, 0xd62407a2 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2820, x13 - li x13, 0xf7a5a7a7 - bne x13, x11, csr_fail - li x13, 0xaf7d9050 - csrrs x11, 2820, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2820, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2820, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xab8b9bbc - csrrc x11, 2820, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2820, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2820, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2820, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2820, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2820, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2820, 0b01101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2820, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2820, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2820, 0b01111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter5 - li x13, 0xa5a5a5a5 - csrrw x11, 2821, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2821, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x233a825d - csrrw x11, 2821, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2821, x13 - li x13, 0x233a825d - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2821, x13 - li x13, 0xa7bfa7fd - bne x13, x11, csr_fail - li x13, 0x7e568133 - csrrs x11, 2821, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2821, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2821, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x6edf1ab9 - csrrc x11, 2821, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2821, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2821, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2821, 0b11000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2821, 0b00101 - li x13, 0x00000018 - bne x13, x11, csr_fail - csrrsi x11, 2821, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2821, 0b01001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2821, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2821, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2821, 0b10110 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter6 - li x13, 0xa5a5a5a5 - csrrw x11, 2822, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2822, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xc7a32aad - csrrw x11, 2822, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2822, x13 - li x13, 0xc7a32aad - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2822, x13 - li x13, 0xe7a7afad - bne x13, x11, csr_fail - li x13, 0x9ace7026 - csrrs x11, 2822, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2822, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2822, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xc92bf27a - csrrc x11, 2822, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2822, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2822, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2822, 0b01010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2822, 0b00101 - li x13, 0x0000000a - bne x13, x11, csr_fail - csrrsi x11, 2822, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2822, 0b11011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2822, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2822, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2822, 0b11011 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter7 - li x13, 0xa5a5a5a5 - csrrw x11, 2823, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2823, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x184a572d - csrrw x11, 2823, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2823, x13 - li x13, 0x184a572d - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2823, x13 - li x13, 0xbdeff7ad - bne x13, x11, csr_fail - li x13, 0x85cfd036 - csrrs x11, 2823, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2823, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2823, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x86ac69a6 - csrrc x11, 2823, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2823, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2823, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2823, 0b10011 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2823, 0b00101 - li x13, 0x00000013 - bne x13, x11, csr_fail - csrrsi x11, 2823, 0b11010 - li x13, 0x00000017 - bne x13, x11, csr_fail - csrrsi x11, 2823, 0b10010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2823, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2823, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2823, 0b01111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter8 - li x13, 0xa5a5a5a5 - csrrw x11, 2824, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2824, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x9355a775 - csrrw x11, 2824, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2824, x13 - li x13, 0x9355a775 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2824, x13 - li x13, 0xb7f5a7f5 - bne x13, x11, csr_fail - li x13, 0x9f6de57c - csrrs x11, 2824, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2824, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2824, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x85ec8fd2 - csrrc x11, 2824, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2824, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2824, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2824, 0b01010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2824, 0b00101 - li x13, 0x0000000a - bne x13, x11, csr_fail - csrrsi x11, 2824, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2824, 0b11000 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2824, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2824, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2824, 0b01000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter9 - li x13, 0xa5a5a5a5 - csrrw x11, 2825, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2825, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xb4a0230e - csrrw x11, 2825, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2825, x13 - li x13, 0xb4a0230e - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2825, x13 - li x13, 0xb5a5a7af - bne x13, x11, csr_fail - li x13, 0x882e6ec1 - csrrs x11, 2825, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2825, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2825, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xb5886b83 - csrrc x11, 2825, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2825, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2825, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2825, 0b11101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2825, 0b00101 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2825, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2825, 0b11110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2825, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2825, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2825, 0b11000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter10 - li x13, 0xa5a5a5a5 - csrrw x11, 2826, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2826, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xeb5456ff - csrrw x11, 2826, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2826, x13 - li x13, 0xeb5456ff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2826, x13 - li x13, 0xeff5f7ff - bne x13, x11, csr_fail - li x13, 0xbd1f6642 - csrrs x11, 2826, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2826, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2826, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xfa6e3d89 - csrrc x11, 2826, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2826, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2826, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2826, 0b01110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2826, 0b00101 - li x13, 0x0000000e - bne x13, x11, csr_fail - csrrsi x11, 2826, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2826, 0b00110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2826, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2826, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2826, 0b11010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter11 - li x13, 0xa5a5a5a5 - csrrw x11, 2827, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2827, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xf07058c6 - csrrw x11, 2827, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2827, x13 - li x13, 0xf07058c6 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2827, x13 - li x13, 0xf5f5fde7 - bne x13, x11, csr_fail - li x13, 0x35e3d846 - csrrs x11, 2827, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2827, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2827, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x8a77a20e - csrrc x11, 2827, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2827, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2827, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2827, 0b00001 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2827, 0b00101 - li x13, 0x00000001 - bne x13, x11, csr_fail - csrrsi x11, 2827, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2827, 0b10110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2827, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2827, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2827, 0b11101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter12 - li x13, 0xa5a5a5a5 - csrrw x11, 2828, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2828, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xdbbe17ed - csrrw x11, 2828, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2828, x13 - li x13, 0xdbbe17ed - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2828, x13 - li x13, 0xffbfb7ed - bne x13, x11, csr_fail - li x13, 0x6c87baac - csrrs x11, 2828, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2828, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2828, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x8b90c327 - csrrc x11, 2828, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2828, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2828, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2828, 0b01111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2828, 0b00101 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2828, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2828, 0b10100 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2828, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2828, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2828, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter13 - li x13, 0xa5a5a5a5 - csrrw x11, 2829, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2829, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x6e69c984 - csrrw x11, 2829, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2829, x13 - li x13, 0x6e69c984 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2829, x13 - li x13, 0xefededa5 - bne x13, x11, csr_fail - li x13, 0x9285cadb - csrrs x11, 2829, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2829, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2829, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x51afbfef - csrrc x11, 2829, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2829, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2829, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2829, 0b00101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2829, 0b00101 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2829, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2829, 0b01010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2829, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2829, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2829, 0b11111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter14 - li x13, 0xa5a5a5a5 - csrrw x11, 2830, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2830, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xe045db3e - csrrw x11, 2830, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2830, x13 - li x13, 0xe045db3e - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2830, x13 - li x13, 0xe5e5ffbf - bne x13, x11, csr_fail - li x13, 0xf14d1b59 - csrrs x11, 2830, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2830, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2830, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x44a8f6a6 - csrrc x11, 2830, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2830, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2830, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2830, 0b10010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2830, 0b00101 - li x13, 0x00000012 - bne x13, x11, csr_fail - csrrsi x11, 2830, 0b11010 - li x13, 0x00000017 - bne x13, x11, csr_fail - csrrsi x11, 2830, 0b01001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2830, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2830, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2830, 0b01001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter15 - li x13, 0xa5a5a5a5 - csrrw x11, 2831, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2831, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xb6a578fb - csrrw x11, 2831, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2831, x13 - li x13, 0xb6a578fb - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2831, x13 - li x13, 0xb7a5fdff - bne x13, x11, csr_fail - li x13, 0xc8c54afb - csrrs x11, 2831, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2831, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2831, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x7198a93f - csrrc x11, 2831, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2831, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2831, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2831, 0b11100 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2831, 0b00101 - li x13, 0x0000001c - bne x13, x11, csr_fail - csrrsi x11, 2831, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2831, 0b00011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2831, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2831, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2831, 0b01101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter16 - li x13, 0xa5a5a5a5 - csrrw x11, 2832, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2832, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xf55fd3fa - csrrw x11, 2832, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2832, x13 - li x13, 0xf55fd3fa - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2832, x13 - li x13, 0xf5fff7ff - bne x13, x11, csr_fail - li x13, 0xe2b12d78 - csrrs x11, 2832, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2832, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2832, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x7cb08e77 - csrrc x11, 2832, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2832, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2832, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2832, 0b01111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2832, 0b00101 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2832, 0b11010 - li x13, 0x0000000f - bne x13, x11, csr_fail - csrrsi x11, 2832, 0b11111 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2832, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2832, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2832, 0b01000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter17 - li x13, 0xa5a5a5a5 - csrrw x11, 2833, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2833, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x0c51d700 - csrrw x11, 2833, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2833, x13 - li x13, 0x0c51d700 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2833, x13 - li x13, 0xadf5f7a5 - bne x13, x11, csr_fail - li x13, 0x812bd85e - csrrs x11, 2833, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2833, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2833, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xbc1cacdf - csrrc x11, 2833, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2833, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2833, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2833, 0b11110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2833, 0b00101 - li x13, 0x0000001e - bne x13, x11, csr_fail - csrrsi x11, 2833, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2833, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2833, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2833, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2833, 0b10010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter18 - li x13, 0xa5a5a5a5 - csrrw x11, 2834, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2834, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x27f2b3f5 - csrrw x11, 2834, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2834, x13 - li x13, 0x27f2b3f5 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2834, x13 - li x13, 0xa7f7b7f5 - bne x13, x11, csr_fail - li x13, 0x50daa8a6 - csrrs x11, 2834, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2834, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2834, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xaed090af - csrrc x11, 2834, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2834, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2834, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2834, 0b10101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2834, 0b00101 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2834, 0b11010 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2834, 0b00001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2834, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2834, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2834, 0b11010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter19 - li x13, 0xa5a5a5a5 - csrrw x11, 2835, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2835, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xbb9f11de - csrrw x11, 2835, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2835, x13 - li x13, 0xbb9f11de - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2835, x13 - li x13, 0xbfbfb5ff - bne x13, x11, csr_fail - li x13, 0xb8b44a62 - csrrs x11, 2835, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2835, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2835, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x8cfc8f2d - csrrc x11, 2835, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2835, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2835, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2835, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2835, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2835, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2835, 0b01001 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2835, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2835, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2835, 0b00000 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter20 - li x13, 0xa5a5a5a5 - csrrw x11, 2836, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2836, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x481e52b3 - csrrw x11, 2836, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2836, x13 - li x13, 0x481e52b3 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2836, x13 - li x13, 0xedbff7b7 - bne x13, x11, csr_fail - li x13, 0x6a7ac135 - csrrs x11, 2836, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2836, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2836, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x27c10d05 - csrrc x11, 2836, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2836, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2836, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2836, 0b00110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2836, 0b00101 - li x13, 0x00000006 - bne x13, x11, csr_fail - csrrsi x11, 2836, 0b11010 - li x13, 0x00000007 - bne x13, x11, csr_fail - csrrsi x11, 2836, 0b00110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2836, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2836, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2836, 0b10111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter21 - li x13, 0xa5a5a5a5 - csrrw x11, 2837, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2837, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x7429cf49 - csrrw x11, 2837, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2837, x13 - li x13, 0x7429cf49 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2837, x13 - li x13, 0xf5adefed - bne x13, x11, csr_fail - li x13, 0x9d4886ce - csrrs x11, 2837, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2837, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2837, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x05ddcfef - csrrc x11, 2837, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2837, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2837, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2837, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2837, 0b00101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2837, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2837, 0b00000 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2837, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2837, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2837, 0b00010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter22 - li x13, 0xa5a5a5a5 - csrrw x11, 2838, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2838, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x9d16666a - csrrw x11, 2838, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2838, x13 - li x13, 0x9d16666a - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2838, x13 - li x13, 0xbdb7e7ef - bne x13, x11, csr_fail - li x13, 0x142246a0 - csrrs x11, 2838, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2838, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2838, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x61cde58d - csrrc x11, 2838, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2838, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2838, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2838, 0b00101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2838, 0b00101 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2838, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrsi x11, 2838, 0b11100 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2838, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2838, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2838, 0b11110 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter23 - li x13, 0xa5a5a5a5 - csrrw x11, 2839, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2839, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0xc7a95284 - csrrw x11, 2839, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2839, x13 - li x13, 0xc7a95284 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2839, x13 - li x13, 0xe7adf7a5 - bne x13, x11, csr_fail - li x13, 0xa7e4b1fe - csrrs x11, 2839, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2839, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2839, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xca65a5e3 - csrrc x11, 2839, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2839, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2839, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2839, 0b11000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2839, 0b00101 - li x13, 0x00000018 - bne x13, x11, csr_fail - csrrsi x11, 2839, 0b11010 - li x13, 0x0000001d - bne x13, x11, csr_fail - csrrsi x11, 2839, 0b10111 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2839, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2839, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2839, 0b01011 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter24 - li x13, 0xa5a5a5a5 - csrrw x11, 2840, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2840, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x448a9e22 - csrrw x11, 2840, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2840, x13 - li x13, 0x448a9e22 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2840, x13 - li x13, 0xe5afbfa7 - bne x13, x11, csr_fail - li x13, 0xf4d3cb7f - csrrs x11, 2840, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2840, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2840, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x24425424 - csrrc x11, 2840, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2840, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2840, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2840, 0b00010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2840, 0b00101 - li x13, 0x00000002 - bne x13, x11, csr_fail - csrrsi x11, 2840, 0b11010 - li x13, 0x00000007 - bne x13, x11, csr_fail - csrrsi x11, 2840, 0b11110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2840, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2840, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2840, 0b00001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter25 - li x13, 0xa5a5a5a5 - csrrw x11, 2841, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2841, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x9c79f6e9 - csrrw x11, 2841, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2841, x13 - li x13, 0x9c79f6e9 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2841, x13 - li x13, 0xbdfdf7ed - bne x13, x11, csr_fail - li x13, 0xd9dd54c2 - csrrs x11, 2841, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2841, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2841, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x2711d141 - csrrc x11, 2841, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2841, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2841, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2841, 0b00011 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2841, 0b00101 - li x13, 0x00000003 - bne x13, x11, csr_fail - csrrsi x11, 2841, 0b11010 - li x13, 0x00000007 - bne x13, x11, csr_fail - csrrsi x11, 2841, 0b01100 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2841, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2841, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2841, 0b11101 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter26 - li x13, 0xa5a5a5a5 - csrrw x11, 2842, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2842, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x5443f6a3 - csrrw x11, 2842, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2842, x13 - li x13, 0x5443f6a3 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2842, x13 - li x13, 0xf5e7f7a7 - bne x13, x11, csr_fail - li x13, 0x4a3510d1 - csrrs x11, 2842, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2842, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2842, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0x5a4d1518 - csrrc x11, 2842, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2842, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2842, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2842, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2842, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2842, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2842, 0b11110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2842, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2842, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2842, 0b11011 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter27 - li x13, 0xa5a5a5a5 - csrrw x11, 2843, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2843, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x64d8b2de - csrrw x11, 2843, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2843, x13 - li x13, 0x64d8b2de - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2843, x13 - li x13, 0xe5fdb7ff - bne x13, x11, csr_fail - li x13, 0x9ca8e026 - csrrs x11, 2843, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2843, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2843, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xeee2ae60 - csrrc x11, 2843, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2843, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2843, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2843, 0b10000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2843, 0b00101 - li x13, 0x00000010 - bne x13, x11, csr_fail - csrrsi x11, 2843, 0b11010 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2843, 0b01101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2843, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2843, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2843, 0b11111 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter28 - li x13, 0xa5a5a5a5 - csrrw x11, 2844, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2844, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x2e03ed20 - csrrw x11, 2844, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2844, x13 - li x13, 0x2e03ed20 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2844, x13 - li x13, 0xafa7eda5 - bne x13, x11, csr_fail - li x13, 0x5fe9e959 - csrrs x11, 2844, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2844, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2844, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xf91e6877 - csrrc x11, 2844, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2844, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2844, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2844, 0b01000 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2844, 0b00101 - li x13, 0x00000008 - bne x13, x11, csr_fail - csrrsi x11, 2844, 0b11010 - li x13, 0x0000000d - bne x13, x11, csr_fail - csrrsi x11, 2844, 0b10000 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2844, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2844, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2844, 0b01001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter29 - li x13, 0xa5a5a5a5 - csrrw x11, 2845, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2845, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x499c9ef2 - csrrw x11, 2845, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2845, x13 - li x13, 0x499c9ef2 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2845, x13 - li x13, 0xedbdbff7 - bne x13, x11, csr_fail - li x13, 0xb43b0f6f - csrrs x11, 2845, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2845, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2845, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xe1c1be2d - csrrc x11, 2845, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2845, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2845, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2845, 0b11110 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2845, 0b00101 - li x13, 0x0000001e - bne x13, x11, csr_fail - csrrsi x11, 2845, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2845, 0b01110 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2845, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2845, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2845, 0b11010 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter30 - li x13, 0xa5a5a5a5 - csrrw x11, 2846, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2846, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x7427b2d4 - csrrw x11, 2846, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2846, x13 - li x13, 0x7427b2d4 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2846, x13 - li x13, 0xf5a7b7f5 - bne x13, x11, csr_fail - li x13, 0xf6a36392 - csrrs x11, 2846, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2846, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2846, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xe0384721 - csrrc x11, 2846, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2846, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2846, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2846, 0b10101 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2846, 0b00101 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2846, 0b11010 - li x13, 0x00000015 - bne x13, x11, csr_fail - csrrsi x11, 2846, 0b10010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2846, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2846, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2846, 0b10001 - li x13, 0x00000000 - bne x13, x11, csr_fail - # mhpmcounter31 - li x13, 0xa5a5a5a5 - csrrw x11, 2847, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrw x11, 2847, x13 - li x13, 0xa5a5a5a5 - bne x13, x11, csr_fail - li x13, 0x99220c48 - csrrw x11, 2847, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrs x11, 2847, x13 - li x13, 0x99220c48 - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrs x11, 2847, x13 - li x13, 0xbda7aded - bne x13, x11, csr_fail - li x13, 0x8ae5417c - csrrs x11, 2847, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0xa5a5a5a5 - csrrc x11, 2847, x13 - li x13, 0xffffffff - bne x13, x11, csr_fail - li x13, 0x5a5a5a5a - csrrc x11, 2847, x13 - li x13, 0x5a5a5a5a - bne x13, x11, csr_fail - li x13, 0xfd516423 - csrrc x11, 2847, x13 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2847, 0b00101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrrwi x11, 2847, 0b11010 - li x13, 0x00000005 - bne x13, x11, csr_fail - csrrwi x11, 2847, 0b11111 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrsi x11, 2847, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2847, 0b11010 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrsi x11, 2847, 0b01011 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2847, 0b00101 - li x13, 0x0000001f - bne x13, x11, csr_fail - csrrci x11, 2847, 0b11010 - li x13, 0x0000001a - bne x13, x11, csr_fail - csrrci x11, 2847, 0b10101 - li x13, 0x00000000 - bne x13, x11, csr_fail - csrr x11, 2847 - li x13, 0x00000000 - bne x13, x11, csr_fail -############################################################################### - # mhpmcounterh3 - li x5, 0xa5a5a5a5 - csrrw x15, 2947, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2947, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x3eb0a869 - csrrw x15, 2947, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2947, x5 - li x5, 0x3eb0a869 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2947, x5 - li x5, 0xbfb5aded - bne x5, x15, csr_fail - li x5, 0x080bee67 - csrrs x15, 2947, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2947, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2947, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x31462855 - csrrc x15, 2947, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2947, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2947, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2947, 0b00001 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2947, 0b00101 - li x5, 0x00000001 - bne x5, x15, csr_fail - csrrsi x15, 2947, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrsi x15, 2947, 0b11110 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2947, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2947, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2947, 0b00100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh4 - li x5, 0xa5a5a5a5 - csrrw x15, 2948, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2948, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x4c90ee23 - csrrw x15, 2948, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2948, x5 - li x5, 0x4c90ee23 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2948, x5 - li x5, 0xedb5efa7 - bne x5, x15, csr_fail - li x5, 0x502190eb - csrrs x15, 2948, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2948, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2948, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x5b6fc098 - csrrc x15, 2948, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2948, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2948, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2948, 0b00011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2948, 0b00101 - li x5, 0x00000003 - bne x5, x15, csr_fail - csrrsi x15, 2948, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2948, 0b01011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2948, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2948, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2948, 0b01111 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh5 - li x5, 0xa5a5a5a5 - csrrw x15, 2949, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2949, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x359322b3 - csrrw x15, 2949, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2949, x5 - li x5, 0x359322b3 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2949, x5 - li x5, 0xb5b7a7b7 - bne x5, x15, csr_fail - li x5, 0x7f1393f5 - csrrs x15, 2949, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2949, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2949, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x6b55cf35 - csrrc x15, 2949, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2949, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2949, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2949, 0b01001 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2949, 0b00101 - li x5, 0x00000009 - bne x5, x15, csr_fail - csrrsi x15, 2949, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2949, 0b01010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2949, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2949, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2949, 0b11010 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh6 - li x5, 0xa5a5a5a5 - csrrw x15, 2950, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2950, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x677f9bec - csrrw x15, 2950, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2950, x5 - li x5, 0x677f9bec - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2950, x5 - li x5, 0xe7ffbfed - bne x5, x15, csr_fail - li x5, 0x85c1ef2f - csrrs x15, 2950, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2950, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2950, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x37e60d36 - csrrc x15, 2950, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2950, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2950, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2950, 0b11011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2950, 0b00101 - li x5, 0x0000001b - bne x5, x15, csr_fail - csrrsi x15, 2950, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2950, 0b11111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2950, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2950, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2950, 0b10110 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh7 - li x5, 0xa5a5a5a5 - csrrw x15, 2951, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2951, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xf42a7164 - csrrw x15, 2951, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2951, x5 - li x5, 0xf42a7164 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2951, x5 - li x5, 0xf5aff5e5 - bne x5, x15, csr_fail - li x5, 0xd0928679 - csrrs x15, 2951, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2951, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2951, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xad3fa01c - csrrc x15, 2951, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2951, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2951, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2951, 0b01011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2951, 0b00101 - li x5, 0x0000000b - bne x5, x15, csr_fail - csrrsi x15, 2951, 0b11010 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2951, 0b11100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2951, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2951, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2951, 0b11100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh8 - li x5, 0xa5a5a5a5 - csrrw x15, 2952, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2952, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xe64a378d - csrrw x15, 2952, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2952, x5 - li x5, 0xe64a378d - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2952, x5 - li x5, 0xe7efb7ad - bne x5, x15, csr_fail - li x5, 0xd6ebbc1c - csrrs x15, 2952, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2952, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2952, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x663587a9 - csrrc x15, 2952, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2952, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2952, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2952, 0b11100 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2952, 0b00101 - li x5, 0x0000001c - bne x5, x15, csr_fail - csrrsi x15, 2952, 0b11010 - li x5, 0x0000001d - bne x5, x15, csr_fail - csrrsi x15, 2952, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2952, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2952, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2952, 0b01011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh9 - li x5, 0xa5a5a5a5 - csrrw x15, 2953, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2953, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x1bf9e6dd - csrrw x15, 2953, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2953, x5 - li x5, 0x1bf9e6dd - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2953, x5 - li x5, 0xbffde7fd - bne x5, x15, csr_fail - li x5, 0x67d15643 - csrrs x15, 2953, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2953, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2953, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xbc1e804b - csrrc x15, 2953, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2953, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2953, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2953, 0b00110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2953, 0b00101 - li x5, 0x00000006 - bne x5, x15, csr_fail - csrrsi x15, 2953, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2953, 0b10000 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2953, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2953, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2953, 0b01011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh10 - li x5, 0xa5a5a5a5 - csrrw x15, 2954, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2954, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x19bfdb8a - csrrw x15, 2954, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2954, x5 - li x5, 0x19bfdb8a - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2954, x5 - li x5, 0xbdbfffaf - bne x5, x15, csr_fail - li x5, 0x1dc114af - csrrs x15, 2954, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2954, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2954, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x0948d631 - csrrc x15, 2954, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2954, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2954, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2954, 0b01101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2954, 0b00101 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2954, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2954, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2954, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2954, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2954, 0b10100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh11 - li x5, 0xa5a5a5a5 - csrrw x15, 2955, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2955, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x0bea34fa - csrrw x15, 2955, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2955, x5 - li x5, 0x0bea34fa - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2955, x5 - li x5, 0xafefb5ff - bne x5, x15, csr_fail - li x5, 0xa32b5c5b - csrrs x15, 2955, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2955, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2955, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x77b267a0 - csrrc x15, 2955, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2955, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2955, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2955, 0b00110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2955, 0b00101 - li x5, 0x00000006 - bne x5, x15, csr_fail - csrrsi x15, 2955, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2955, 0b01111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2955, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2955, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2955, 0b10001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh12 - li x5, 0xa5a5a5a5 - csrrw x15, 2956, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2956, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x51b87738 - csrrw x15, 2956, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2956, x5 - li x5, 0x51b87738 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2956, x5 - li x5, 0xf5bdf7bd - bne x5, x15, csr_fail - li x5, 0xef71fa43 - csrrs x15, 2956, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2956, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2956, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x6e04d174 - csrrc x15, 2956, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2956, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2956, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2956, 0b10010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2956, 0b00101 - li x5, 0x00000012 - bne x5, x15, csr_fail - csrrsi x15, 2956, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2956, 0b10111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2956, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2956, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2956, 0b10011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh13 - li x5, 0xa5a5a5a5 - csrrw x15, 2957, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2957, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x4906d0a6 - csrrw x15, 2957, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2957, x5 - li x5, 0x4906d0a6 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2957, x5 - li x5, 0xeda7f5a7 - bne x5, x15, csr_fail - li x5, 0xf643ef2d - csrrs x15, 2957, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2957, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2957, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa6be64e9 - csrrc x15, 2957, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2957, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2957, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2957, 0b10101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2957, 0b00101 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2957, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2957, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2957, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2957, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2957, 0b10011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh14 - li x5, 0xa5a5a5a5 - csrrw x15, 2958, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2958, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x7772d54a - csrrw x15, 2958, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2958, x5 - li x5, 0x7772d54a - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2958, x5 - li x5, 0xf7f7f5ef - bne x5, x15, csr_fail - li x5, 0x5e2d84b5 - csrrs x15, 2958, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2958, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2958, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xfd804e78 - csrrc x15, 2958, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2958, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2958, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2958, 0b01000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2958, 0b00101 - li x5, 0x00000008 - bne x5, x15, csr_fail - csrrsi x15, 2958, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2958, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2958, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2958, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2958, 0b01100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh15 - li x5, 0xa5a5a5a5 - csrrw x15, 2959, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2959, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x2d2f3ca0 - csrrw x15, 2959, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2959, x5 - li x5, 0x2d2f3ca0 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2959, x5 - li x5, 0xadafbda5 - bne x5, x15, csr_fail - li x5, 0xed51c6ed - csrrs x15, 2959, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2959, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2959, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x2b93882f - csrrc x15, 2959, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2959, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2959, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2959, 0b11110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2959, 0b00101 - li x5, 0x0000001e - bne x5, x15, csr_fail - csrrsi x15, 2959, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2959, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2959, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2959, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2959, 0b10101 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh16 - li x5, 0xa5a5a5a5 - csrrw x15, 2960, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2960, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x0b99311d - csrrw x15, 2960, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2960, x5 - li x5, 0x0b99311d - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2960, x5 - li x5, 0xafbdb5bd - bne x5, x15, csr_fail - li x5, 0xa20d6c13 - csrrs x15, 2960, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2960, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2960, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x0e4813b8 - csrrc x15, 2960, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2960, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2960, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2960, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2960, 0b00101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2960, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2960, 0b10100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2960, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2960, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2960, 0b10100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh17 - li x5, 0xa5a5a5a5 - csrrw x15, 2961, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2961, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x8c7062a5 - csrrw x15, 2961, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2961, x5 - li x5, 0x8c7062a5 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2961, x5 - li x5, 0xadf5e7a5 - bne x5, x15, csr_fail - li x5, 0x168b744f - csrrs x15, 2961, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2961, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2961, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x679bf535 - csrrc x15, 2961, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2961, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2961, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2961, 0b01010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2961, 0b00101 - li x5, 0x0000000a - bne x5, x15, csr_fail - csrrsi x15, 2961, 0b11010 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2961, 0b11100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2961, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2961, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2961, 0b11100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh18 - li x5, 0xa5a5a5a5 - csrrw x15, 2962, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2962, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x19175bd2 - csrrw x15, 2962, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2962, x5 - li x5, 0x19175bd2 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2962, x5 - li x5, 0xbdb7fff7 - bne x5, x15, csr_fail - li x5, 0x78e5331f - csrrs x15, 2962, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2962, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2962, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x030c0f19 - csrrc x15, 2962, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2962, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2962, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2962, 0b00001 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2962, 0b00101 - li x5, 0x00000001 - bne x5, x15, csr_fail - csrrsi x15, 2962, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrsi x15, 2962, 0b10001 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2962, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2962, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2962, 0b10000 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh19 - li x5, 0xa5a5a5a5 - csrrw x15, 2963, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2963, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x1d5d199e - csrrw x15, 2963, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2963, x5 - li x5, 0x1d5d199e - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2963, x5 - li x5, 0xbdfdbdbf - bne x5, x15, csr_fail - li x5, 0xebff1c39 - csrrs x15, 2963, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2963, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2963, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x927e647f - csrrc x15, 2963, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2963, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2963, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2963, 0b10011 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2963, 0b00101 - li x5, 0x00000013 - bne x5, x15, csr_fail - csrrsi x15, 2963, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2963, 0b00011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2963, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2963, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2963, 0b10000 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh20 - li x5, 0xa5a5a5a5 - csrrw x15, 2964, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2964, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x7c713b24 - csrrw x15, 2964, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2964, x5 - li x5, 0x7c713b24 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2964, x5 - li x5, 0xfdf5bfa5 - bne x5, x15, csr_fail - li x5, 0x1d6635ee - csrrs x15, 2964, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2964, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2964, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x0968a804 - csrrc x15, 2964, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2964, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2964, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2964, 0b00110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2964, 0b00101 - li x5, 0x00000006 - bne x5, x15, csr_fail - csrrsi x15, 2964, 0b11010 - li x5, 0x00000007 - bne x5, x15, csr_fail - csrrsi x15, 2964, 0b00010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2964, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2964, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2964, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh21 - li x5, 0xa5a5a5a5 - csrrw x15, 2965, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2965, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x612df4ba - csrrw x15, 2965, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2965, x5 - li x5, 0x612df4ba - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2965, x5 - li x5, 0xe5adf5bf - bne x5, x15, csr_fail - li x5, 0x4c97cb48 - csrrs x15, 2965, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2965, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2965, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x7fe2f772 - csrrc x15, 2965, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2965, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2965, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2965, 0b10000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2965, 0b00101 - li x5, 0x00000010 - bne x5, x15, csr_fail - csrrsi x15, 2965, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2965, 0b00010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2965, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2965, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2965, 0b11110 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh22 - li x5, 0xa5a5a5a5 - csrrw x15, 2966, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2966, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xce837a0f - csrrw x15, 2966, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2966, x5 - li x5, 0xce837a0f - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2966, x5 - li x5, 0xefa7ffaf - bne x5, x15, csr_fail - li x5, 0x923e9fde - csrrs x15, 2966, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2966, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2966, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xad473df8 - csrrc x15, 2966, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2966, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2966, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2966, 0b10111 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2966, 0b00101 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2966, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2966, 0b01000 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2966, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2966, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2966, 0b01011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh23 - li x5, 0xa5a5a5a5 - csrrw x15, 2967, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2967, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xe6276ce9 - csrrw x15, 2967, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2967, x5 - li x5, 0xe6276ce9 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2967, x5 - li x5, 0xe7a7eded - bne x5, x15, csr_fail - li x5, 0x30a2bc64 - csrrs x15, 2967, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2967, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2967, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x1993db40 - csrrc x15, 2967, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2967, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2967, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2967, 0b11000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2967, 0b00101 - li x5, 0x00000018 - bne x5, x15, csr_fail - csrrsi x15, 2967, 0b11010 - li x5, 0x0000001d - bne x5, x15, csr_fail - csrrsi x15, 2967, 0b11011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2967, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2967, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2967, 0b11001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh24 - li x5, 0xa5a5a5a5 - csrrw x15, 2968, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2968, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x33aec0ed - csrrw x15, 2968, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2968, x5 - li x5, 0x33aec0ed - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2968, x5 - li x5, 0xb7afe5ed - bne x5, x15, csr_fail - li x5, 0xfa5a4dd9 - csrrs x15, 2968, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2968, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2968, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x16b2cdd0 - csrrc x15, 2968, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2968, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2968, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2968, 0b10000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2968, 0b00101 - li x5, 0x00000010 - bne x5, x15, csr_fail - csrrsi x15, 2968, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2968, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2968, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2968, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2968, 0b01001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh25 - li x5, 0xa5a5a5a5 - csrrw x15, 2969, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2969, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x7981abbb - csrrw x15, 2969, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2969, x5 - li x5, 0x7981abbb - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2969, x5 - li x5, 0xfda5afbf - bne x5, x15, csr_fail - li x5, 0x2a637600 - csrrs x15, 2969, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2969, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2969, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x8e5de396 - csrrc x15, 2969, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2969, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2969, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2969, 0b01111 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2969, 0b00101 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2969, 0b11010 - li x5, 0x0000000f - bne x5, x15, csr_fail - csrrsi x15, 2969, 0b10111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2969, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2969, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2969, 0b11010 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh26 - li x5, 0xa5a5a5a5 - csrrw x15, 2970, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2970, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x453b4cc5 - csrrw x15, 2970, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2970, x5 - li x5, 0x453b4cc5 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2970, x5 - li x5, 0xe5bfede5 - bne x5, x15, csr_fail - li x5, 0x9af3ee1b - csrrs x15, 2970, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2970, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2970, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x9b5af5a0 - csrrc x15, 2970, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2970, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2970, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2970, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2970, 0b00101 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2970, 0b11010 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrsi x15, 2970, 0b11111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2970, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2970, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2970, 0b11011 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh27 - li x5, 0xa5a5a5a5 - csrrw x15, 2971, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2971, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x2ea119f8 - csrrw x15, 2971, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2971, x5 - li x5, 0x2ea119f8 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2971, x5 - li x5, 0xafa5bdfd - bne x5, x15, csr_fail - li x5, 0x263ed361 - csrrs x15, 2971, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2971, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2971, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x3559f480 - csrrc x15, 2971, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2971, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2971, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2971, 0b10010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2971, 0b00101 - li x5, 0x00000012 - bne x5, x15, csr_fail - csrrsi x15, 2971, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2971, 0b01100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2971, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2971, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2971, 0b00001 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh28 - li x5, 0xa5a5a5a5 - csrrw x15, 2972, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2972, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x8e030ab4 - csrrw x15, 2972, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2972, x5 - li x5, 0x8e030ab4 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2972, x5 - li x5, 0xafa7afb5 - bne x5, x15, csr_fail - li x5, 0x1c55a07b - csrrs x15, 2972, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2972, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2972, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x69b45543 - csrrc x15, 2972, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2972, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2972, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2972, 0b01000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2972, 0b00101 - li x5, 0x00000008 - bne x5, x15, csr_fail - csrrsi x15, 2972, 0b11010 - li x5, 0x0000000d - bne x5, x15, csr_fail - csrrsi x15, 2972, 0b11100 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2972, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2972, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2972, 0b10100 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh29 - li x5, 0xa5a5a5a5 - csrrw x15, 2973, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2973, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0xeeaee738 - csrrw x15, 2973, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2973, x5 - li x5, 0xeeaee738 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2973, x5 - li x5, 0xefafe7bd - bne x5, x15, csr_fail - li x5, 0x184d62ef - csrrs x15, 2973, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2973, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2973, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xd1aee09c - csrrc x15, 2973, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2973, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2973, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2973, 0b10000 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2973, 0b00101 - li x5, 0x00000010 - bne x5, x15, csr_fail - csrrsi x15, 2973, 0b11010 - li x5, 0x00000015 - bne x5, x15, csr_fail - csrrsi x15, 2973, 0b00111 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2973, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2973, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2973, 0b11101 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh30 - li x5, 0xa5a5a5a5 - csrrw x15, 2974, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2974, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x11c41528 - csrrw x15, 2974, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2974, x5 - li x5, 0x11c41528 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2974, x5 - li x5, 0xb5e5b5ad - bne x5, x15, csr_fail - li x5, 0xce03cd76 - csrrs x15, 2974, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2974, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2974, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0x8d82832d - csrrc x15, 2974, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2974, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2974, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2974, 0b10010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2974, 0b00101 - li x5, 0x00000012 - bne x5, x15, csr_fail - csrrsi x15, 2974, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2974, 0b00011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2974, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2974, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2974, 0b00000 - li x5, 0x00000000 - bne x5, x15, csr_fail - # mhpmcounterh31 - li x5, 0xa5a5a5a5 - csrrw x15, 2975, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrw x15, 2975, x5 - li x5, 0xa5a5a5a5 - bne x5, x15, csr_fail - li x5, 0x8fbb05fb - csrrw x15, 2975, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrs x15, 2975, x5 - li x5, 0x8fbb05fb - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrs x15, 2975, x5 - li x5, 0xafbfa5ff - bne x5, x15, csr_fail - li x5, 0x4b6a3f57 - csrrs x15, 2975, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0xa5a5a5a5 - csrrc x15, 2975, x5 - li x5, 0xffffffff - bne x5, x15, csr_fail - li x5, 0x5a5a5a5a - csrrc x15, 2975, x5 - li x5, 0x5a5a5a5a - bne x5, x15, csr_fail - li x5, 0xcf06f89a - csrrc x15, 2975, x5 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2975, 0b00101 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrrwi x15, 2975, 0b11010 - li x5, 0x00000005 - bne x5, x15, csr_fail - csrrwi x15, 2975, 0b10110 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrsi x15, 2975, 0b00101 - li x5, 0x00000016 - bne x5, x15, csr_fail - csrrsi x15, 2975, 0b11010 - li x5, 0x00000017 - bne x5, x15, csr_fail - csrrsi x15, 2975, 0b00011 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2975, 0b00101 - li x5, 0x0000001f - bne x5, x15, csr_fail - csrrci x15, 2975, 0b11010 - li x5, 0x0000001a - bne x5, x15, csr_fail - csrrci x15, 2975, 0b00011 - li x5, 0x00000000 - bne x5, x15, csr_fail - csrr x15, 2975 - li x5, 0x00000000 - bne x5, x15, csr_fail - -################################################################################ -# -# Generated code ends... -# -################################################################################ -test_done: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'D' - sw a1,0(a0) - addi a1,zero,'O' - sw a1,0(a0) - addi a1,zero,'N' - sw a1,0(a0) - addi a1,zero,'E' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - -csr_pass: - li x18, 123456789 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi - -csr_fail: - lui a0,print_port>>12 - addi a1,zero,'\n' - sw a1,0(a0) - addi a1,zero,'C' - sw a1,0(a0) - addi a1,zero,'V' - sw a1,0(a0) - addi a1,zero,'3' - sw a1,0(a0) - addi a1,zero,'2' - sw a1,0(a0) - addi a1,zero,' ' - sw a1,0(a0) - addi a1,zero,'F' - sw a1,0(a0) - addi a1,zero,'A' - sw a1,0(a0) - addi a1,zero,'I' - sw a1,0(a0) - addi a1,zero,'L' - sw a1,0(a0) - addi a1,zero,'\n' - sw a1,0(a0) - sw a1,0(a0) - - li x18, 1 - li x17, CV_VP_STATUS_FLAGS_BASE - sw x18,0(x17) - wfi -# -# end -# diff --git a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_2/test.yaml b/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_2/test.yaml deleted file mode 100644 index b6de2a05eb..0000000000 --- a/cv32e40x/tests/programs/custom/mhpmcounter29_csr_access_test_2/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: mhpmcounter29_csr_access_test_2 -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR access test with NUM_MHPMCOUNTER = 29 (FIXME ISS does not set correct reset value for mcountinhibit) diff --git a/cv32e40x/tests/programs/custom/misalign/misalign.c b/cv32e40x/tests/programs/custom/misalign/misalign.c deleted file mode 100644 index 70c72a4843..0000000000 --- a/cv32e40x/tests/programs/custom/misalign/misalign.c +++ /dev/null @@ -1,103 +0,0 @@ -#include -#include -#include - -//#include "../../../core/custom/startup/support.h" -#include "./support.h" - -/* - * Possible misaligned scenarios for 32 bit bus - * - * 1 byte access - * - Never - * - * 2 byte access - * - Address & 0x1 - * if 0x3, then 2 read32() - * - * 4 byte access - * - (Address & 0x1) | (Address & 0x2) - * then 2 read32() - * - * 8 byte access - * - (Address & 0x1) | (Address & 0x2) | (Address & 0x4) - * then 3 read32() - * - */ - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -typedef unsigned long long int u64; - -// 64 bit printf fmt does not work -// use a union and print as 2x32bit -union { - u32 u32v[2]; - u64 u64v; -} u64_32; - -int main () { - printf("Hello World\n"); - printf("Test misaligned load/store\n"); - - u64 u64Load[4]; // 32 bytes - u64 u64Store[4]; // 32 bytes - u8 *pLoad = (u8 *) u64Load; - u8 *pStore = (u8 *) u64Store; - - u32 i; - for (i=0; i<32; i++) { - *(pLoad+i) = i; - } - u8 *cpa; - u16 *spa; - u32 *ipa; - u64 *lpa; - - // Load Test - cpa = pLoad; - for (i=0; i<16; i++) { - spa = (u16 *) cpa; - ipa = (u32 *) cpa; - lpa = (u64 *) cpa; - - printf("\n"); - printf("Store Index=%d off=%d\n", i, i%4); - printf(" (u8 *) = %02X\n", *cpa); - printf(" (u16 *) = %04X\n", *spa); - printf(" (u32 *) = %08X\n", *ipa); - - u64_32.u64v = *lpa; - printf(" (u64 *) = %08X%08X\n", u64_32.u32v[1], u64_32.u32v[0]); - - cpa++; - } - - // Store Test - cpa = pStore; - for (i=0; i<16; i++) { - spa = (u16 *) cpa; - ipa = (u32 *) cpa; - lpa = (u64 *) cpa; - - printf("\n"); - printf("Load Index=%d off=%d\n", i, i%4); - - bzero(cpa, 32); - *spa = *(u16 *)(pLoad + i); - printf(" (u16 *) = %04X\n", *spa); - - bzero(cpa, 32); - *ipa = *(u32 *)(pLoad + i); - printf(" (u32 *) = %08X\n", *ipa); - - bzero(cpa, 32); - *lpa = *(u64 *)(pLoad + i); - u64_32.u64v = *lpa; - printf(" (u64 *) = %08X%08X\n", u64_32.u32v[1], u64_32.u32v[0]); - - cpa++; - } - -} diff --git a/cv32e40x/tests/programs/custom/misalign/support.h b/cv32e40x/tests/programs/custom/misalign/support.h deleted file mode 100644 index 1ac60d958d..0000000000 --- a/cv32e40x/tests/programs/custom/misalign/support.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef _SUPPORT_H_ -#define _SUPPORT_H_ - -int _trap_Generic_Handler(); - -int _trap_Machine_Software_Interrupt(); -int _trap_Machine_Timer_Interrupt(); -int _trap_Machine_External_Interrupt(); - - -void enable_Machine_External_Interrupt(); -void enable_Machine_Timer_Interrupt(); -void enable_Machine_Software_Interrupt(); - -void disable_Machine_External_Interrupt(); -void disable_Machine_Timer_Interrupt(); -void disable_Machine_Software_Interrupt(); - -void enableVEC(); -void setupVEC(); - -void illegalOP(); - -void setINTC_machine_external(int cycles); -void setINTC_machine_timer(int cycles); -void setINTC_machine_software(int cycles); -void _clrINTC_machine_external(); -void _clrINTC_machine_timer(); -void _clrINTC_machine_software(); - -#endif diff --git a/cv32e40x/tests/programs/custom/misalign/test.yaml b/cv32e40x/tests/programs/custom/misalign/test.yaml deleted file mode 100644 index e5b29d86eb..0000000000 --- a/cv32e40x/tests/programs/custom/misalign/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: misalign -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Misaligned instruction directed test diff --git a/cv32e40x/tests/programs/custom/modeled_csr_por/modeled_csr_por.c b/cv32e40x/tests/programs/custom/modeled_csr_por/modeled_csr_por.c deleted file mode 100644 index fdad21150e..0000000000 --- a/cv32e40x/tests/programs/custom/modeled_csr_por/modeled_csr_por.c +++ /dev/null @@ -1,517 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Modeled CSR power-on-reset test: -** Reads the CSRs modeled by the Imperas OVPsim Reference Model and prints -** some useful (?) messages to stdout. Will fail for one of two reasons: -** 1. Step-and-compare against RM mismatch. -** 2. read value does not match the documented PoR value. -** -** This is a manually written prototype of a (planned) generated test-program. -** The primary goals of this test-program is to get proof of life from all CV32E40X -** CSRs and asertain the status of CSR modeling in the OVPsim Reference Model. -** In this prototype, all addresses and expected values are hand-coded. -** -******************************************************************************* -*/ - -#include -#include - -#define EXP_MISA 0x40001104 - -int main(int argc, char *argv[]) -{ - // User CSRs - unsigned int fflags_rval, frm_rval, fcsr_rval; - // User Custom CSRs - unsigned int lpstart0_rval, lpend0_rval, lpcount0_rval, lpstart1_rval, lpend1_rval, lpcount1_rval; - unsigned int fprec_rval, privlv_rval, uhartid_rval; - // Machine CSRs - unsigned int mstatus_rval, misa_rval, mie_rval, mtvec_rval; - unsigned int mcounteren_rval, mcountinhibit_rval, mphmevent_rval[32]; - unsigned int mscratch_rval, mepc_rval, mcause_rval, mtval_rval, mip_rval; - unsigned int tselect_rval, tdata1_rval, tdata2_rval, tdata3_rval, tinfo_rval; - unsigned int mcontext_rval, scontext_rval, dcsr_rval, dpc_rval, dscratch0_rval, dscratch1_rval; - unsigned int mcycle_rval, minstret_rval, mhpmcounter_rval[32], mcycleh_rval; - unsigned int minstreth_rval, mhpmcounterh[32]; - unsigned int mvendorid_rval, marchid_rval, mimpid_rval, mhartid_rval; - - int err_cnt, sum; - - err_cnt = 0; - sum = 0; - - printf("\n\n"); - - // These CSRs only exist if FPU=1 at RTL compile-time. - // Reading these when FPU=0 yields an illegal instruction exception (which is not tested here). - /* - __asm__ volatile("csrr %0, 0x001" : "=r"(fflags_rval)); - __asm__ volatile("csrr %0, 0x002" : "=r"(frm_rval)); - __asm__ volatile("csrr %0, 0x003" : "=r"(fcsr_rval)); - - if (fflags_rval != 0x0) { - printf("ERROR: CSR FFLAGS not zero!\n\n"); - ++err_cnt; - } - if (frm_rval != 0x0) { - printf("ERROR: CSR FRM not zero!\n\n"); - ++err_cnt; - } - if (fcsr_rval != 0x0) { - printf("ERROR: CSR FCSR not zero!\n\n"); - ++err_cnt; - } - */ - - /* - // lpstat0/1, lpend0/1 and lpcount0/1 present when PULP_XPULP=1 - // Not currently modeled. - __asm__ volatile("csrr %0, 0x7C0" : "=r"(lpstart0_rval)); - __asm__ volatile("csrr %0, 0x7C1" : "=r"(lpend0_rval)); - __asm__ volatile("csrr %0, 0x7C2" : "=r"(lpcount0_rval)); - __asm__ volatile("csrr %0, 0x7C4" : "=r"(lpstart1_rval)); - __asm__ volatile("csrr %0, 0x7C5" : "=r"(lpend1_rval)); - __asm__ volatile("csrr %0, 0x7C6" : "=r"(lpcount1_rval)); - - if (lpstart0_rval != 0x0) { - printf("ERROR: CSR LPSTART0 not zero!\n\n"); - ++err_cnt; - } - if (lpend0_rval != 0x0) { - printf("ERROR: CSR LPEND0 not zero!\n\n"); - ++err_cnt; - } - if (lpcount0_rval != 0x0) { - printf("ERROR: CSR LPCOUNT0 not zero!\n\n"); - ++err_cnt; - } - if (lpstart1_rval != 0x0) { - printf("ERROR: CSR LPSTART1 not zero!\n\n"); - ++err_cnt; - } - if (lpend1_rval != 0x0) { - printf("ERROR: CSR LPEND1 not zero!\n\n"); - ++err_cnt; - } - if (lpcount1_rval != 0x0) { - printf("ERROR: CSR LPCOUNT1 not zero!\n\n"); - ++err_cnt; - } - */ - - /* - __asm__ volatile("csrr %0, 0x006" : "=r"(fprec_rval)); // not present because FP=0 - __asm__ volatile("csrr %0, 0xC10" : "=r"(privlv_rval)); // not modeled by the Imperas RM - __asm__ volatile("csrr %0, 0x014" : "=r"(uhartid_rval)); // present because PULP_XPULP=1 - - if (fprec_rval != 0x0) { - printf("ERROR: CSR FPREC not zero!\n\n"); - ++err_cnt; - } - if (privlv_rval != 0x3) { - printf("ERROR: CSR PRIVLV not 0x3!\n\n"); - ++err_cnt; - } - if (uhartid_rval != 0x0) { - printf("ERROR: CSR UHARTID not equal to mhartid_i!\n\n"); - ++err_cnt; - } - */ - - __asm__ volatile("csrr %0, 0x300" : "=r"(mstatus_rval)); - __asm__ volatile("csrr %0, 0x301" : "=r"(misa_rval)); - __asm__ volatile("csrr %0, 0x304" : "=r"(mie_rval)); - __asm__ volatile("csrr %0, 0x305" : "=r"(mtvec_rval)); - - if (mstatus_rval != 0x1800) { - printf("ERROR: CSR MSTATUS not 0x1800!\n\n"); - ++err_cnt; - } - if (misa_rval != EXP_MISA) { - printf("ERROR: CSR MISA not 0x%x!\n\n", EXP_MISA); - ++err_cnt; - } - if (mie_rval != 0x0) { - printf("ERROR: CSR MIE not 0x0!\n\n"); - ++err_cnt; - } - if (mtvec_rval != 0x0001) { - printf("ERROR: CSR MTVEC not 0x0!\n\n"); - ++err_cnt; - } - - //__asm__ volatile("csrr %0, 0x306" : "=r"(mcounteren_rval)); // Not currently modeled - //__asm__ volatile("csrr %0, 0x320" : "=r"(mcountinhibit_rval)); // Modeled, but cannot override PoR - - //if (mcounteren_rval != 0x0) { - // printf("ERROR: CSR MCOUNTEREN not 0x0!\n\n"); - // ++err_cnt; - //} - //if (mcountinhibit_rval != 0xD) { - // printf("ERROR: CSR MCOUNTINHIBIT not 0xD!\n\n"); - // ++err_cnt; - //} - - // This doesn't work because __asm__ is a macro (sigh) - //num = (int)strtol(addr, NULL, 16); - //for (int i=3; i<32; i++) { - // n = sprintf(string, "csrr %%0, 0x%0x", num++); - // printf("%s\n",string); - // __asm__ volatile(string : "=r"(mphmevent_rval[i])); - //} - __asm__ volatile("csrr %0, 0x323" : "=r"(mphmevent_rval[3])); - //__asm__ volatile("csrr %0, 0x324" : "=r"(mphmevent_rval[4])); - //__asm__ volatile("csrr %0, 0x325" : "=r"(mphmevent_rval[5])); - //__asm__ volatile("csrr %0, 0x326" : "=r"(mphmevent_rval[6])); - //__asm__ volatile("csrr %0, 0x327" : "=r"(mphmevent_rval[7])); - //__asm__ volatile("csrr %0, 0x328" : "=r"(mphmevent_rval[8])); - //__asm__ volatile("csrr %0, 0x329" : "=r"(mphmevent_rval[9])); - //__asm__ volatile("csrr %0, 0x32A" : "=r"(mphmevent_rval[10])); - //__asm__ volatile("csrr %0, 0x32B" : "=r"(mphmevent_rval[11])); - //__asm__ volatile("csrr %0, 0x32C" : "=r"(mphmevent_rval[12])); - //__asm__ volatile("csrr %0, 0x32D" : "=r"(mphmevent_rval[13])); - //__asm__ volatile("csrr %0, 0x32E" : "=r"(mphmevent_rval[14])); - //__asm__ volatile("csrr %0, 0x32F" : "=r"(mphmevent_rval[15])); - //__asm__ volatile("csrr %0, 0x330" : "=r"(mphmevent_rval[16])); - //__asm__ volatile("csrr %0, 0x331" : "=r"(mphmevent_rval[17])); - //__asm__ volatile("csrr %0, 0x332" : "=r"(mphmevent_rval[18])); - //__asm__ volatile("csrr %0, 0x333" : "=r"(mphmevent_rval[19])); - //__asm__ volatile("csrr %0, 0x334" : "=r"(mphmevent_rval[20])); - //__asm__ volatile("csrr %0, 0x335" : "=r"(mphmevent_rval[21])); - //__asm__ volatile("csrr %0, 0x336" : "=r"(mphmevent_rval[22])); - //__asm__ volatile("csrr %0, 0x337" : "=r"(mphmevent_rval[23])); - //__asm__ volatile("csrr %0, 0x338" : "=r"(mphmevent_rval[24])); - //__asm__ volatile("csrr %0, 0x339" : "=r"(mphmevent_rval[25])); - //__asm__ volatile("csrr %0, 0x33A" : "=r"(mphmevent_rval[26])); - //__asm__ volatile("csrr %0, 0x33B" : "=r"(mphmevent_rval[27])); - //__asm__ volatile("csrr %0, 0x33C" : "=r"(mphmevent_rval[28])); - //__asm__ volatile("csrr %0, 0x33D" : "=r"(mphmevent_rval[29])); - //__asm__ volatile("csrr %0, 0x33E" : "=r"(mphmevent_rval[30])); - //__asm__ volatile("csrr %0, 0x33F" : "=r"(mphmevent_rval[31])); - - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { - sum += mphmevent_rval[i]; - } - if (sum) { - //printf("ERROR: CSR MPHMEVENT[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MPHMEVENT[3] not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0x340" : "=r"(mscratch_rval)); - __asm__ volatile("csrr %0, 0x341" : "=r"(mepc_rval)); - __asm__ volatile("csrr %0, 0x342" : "=r"(mcause_rval)); - __asm__ volatile("csrr %0, 0x343" : "=r"(mtval_rval)); - __asm__ volatile("csrr %0, 0x344" : "=r"(mip_rval)); - - if (mscratch_rval != 0x0) { - printf("ERROR: CSR MSCRATCH not zero!\n\n"); - ++err_cnt; - } - - if (mepc_rval != 0x0) { - printf("ERROR: CSR MEPC not zero!\n\n"); - ++err_cnt; - } - - if (mcause_rval != 0x0) { - printf("ERROR: CSR MCAUSE not zero!\n\n"); - ++err_cnt; - } - - if (mtval_rval != 0x0) { - printf("ERROR: CSR MTVAL not zero!\n\n"); - ++err_cnt; - } - - if (mip_rval != 0x0) { - printf("ERROR: CSR MIP not zero!\n\n"); - ++err_cnt; - } - - //__asm__ volatile("csrr %0, 0x7A0" : "=r"(tselect_rval)); // unimplemented in model, hardwired to zero - //__asm__ volatile("csrr %0, 0x7A1" : "=r"(tdata1_rval)); // unimplemented in model, hardwired to zero - //__asm__ volatile("csrr %0, 0x7A2" : "=r"(tdata2_rval)); // unimplemented in model, hardwired to zero - //__asm__ volatile("csrr %0, 0x7A3" : "=r"(tdata3_rval)); // unimplemented in model, hardwired to zero - //__asm__ volatile("csrr %0, 0x7A4" : "=r"(tinfo_rval)); // unimplemented in model - - /* - if (tselect_rval != 0x0) { - printf("ERROR: CSR TSELECT not zero!\n\n"); - ++err_cnt; - } - - if (tdata1_rval != 0x28001000) { - printf("ERROR: CSR TDATA1 not 0x28001000!\n\n"); - ++err_cnt; - } - - if (tdata2_rval != 0x0) { - printf("ERROR: CSR TDATA2 not 0x0!\n\n"); - ++err_cnt; - } - - if (tdata3_rval != 0x0) { - printf("ERROR: CSR TDATA3 not 0x0!\n\n"); - ++err_cnt; - } - - if (tinfo_rval != 0x0) { - printf("ERROR: CSR TINFO not 0x0!\n\n"); - ++err_cnt; - } - */ - - //__asm__ volatile("csrr %0, 0x7A8" : "=r"(mcontext_rval)); // unimplemented in model - //__asm__ volatile("csrr %0, 0x7AA" : "=r"(scontext_rval)); // unimplemented in model - //__asm__ volatile("csrr %0, 0x7B0" : "=r"(dcsr_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B1" : "=r"(dpc_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B2" : "=r"(dscratch0_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B3" : "=r"(dscratch1_rval)); // only accessible in Debug mode - - /* - if (mcontext_rval != 0x0) { - printf("ERROR: CSR MCONTEXT not 0x0!\n\n"); - ++err_cnt; - } - - if (scontext_rval != 0x0) { - printf("ERROR: CSR SCONTEXT not 0x0!\n\n"); - ++err_cnt; - } - - if (dcsr_rval != 0x0) { - printf("ERROR: CSR DCSR not 0x0!\n\n"); - ++err_cnt; - } - - if (dpc_rval != 0x0) { - printf("ERROR: CSR DPC not 0x0!\n\n"); - ++err_cnt; - } - - if (dscratch0_rval != 0x0) { - printf("ERROR: CSR DSCRATCH0 not 0x0!\n\n"); - ++err_cnt; - } - - if (dscratch1_rval != 0x0) { - printf("ERROR: CSR DSCRATCH1 not 0x0!\n\n"); - ++err_cnt; - } - */ - - //__asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_rval)); // CSR unimplemented in the model - //__asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // CSR unimplmented in the model - /* - if (mcycle_rval != 0x0) { - printf("ERROR: CSR MCYCLE not 0x0!\n\n"); - ++err_cnt; - } - - if (minstret_rval != 0x0) { - printf("ERROR: CSR MINSTRET not 0x0!\n\n"); - ++err_cnt; - } - */ - - __asm__ volatile("csrr %0, 0xB03" : "=r"(mhpmcounter_rval[3])); - //__asm__ volatile("csrr %0, 0xB04" : "=r"(mhpmcounter_rval[4])); - //__asm__ volatile("csrr %0, 0xB05" : "=r"(mhpmcounter_rval[5])); - //__asm__ volatile("csrr %0, 0xB06" : "=r"(mhpmcounter_rval[6])); - //__asm__ volatile("csrr %0, 0xB07" : "=r"(mhpmcounter_rval[7])); - //__asm__ volatile("csrr %0, 0xB08" : "=r"(mhpmcounter_rval[8])); - //__asm__ volatile("csrr %0, 0xB09" : "=r"(mhpmcounter_rval[9])); - //__asm__ volatile("csrr %0, 0xB0A" : "=r"(mhpmcounter_rval[10])); - //__asm__ volatile("csrr %0, 0xB0B" : "=r"(mhpmcounter_rval[11])); - //__asm__ volatile("csrr %0, 0xB0C" : "=r"(mhpmcounter_rval[12])); - //__asm__ volatile("csrr %0, 0xB0D" : "=r"(mhpmcounter_rval[13])); - //__asm__ volatile("csrr %0, 0xB0E" : "=r"(mhpmcounter_rval[14])); - //__asm__ volatile("csrr %0, 0xB0F" : "=r"(mhpmcounter_rval[15])); - //__asm__ volatile("csrr %0, 0xB10" : "=r"(mhpmcounter_rval[16])); - //__asm__ volatile("csrr %0, 0xB11" : "=r"(mhpmcounter_rval[17])); - //__asm__ volatile("csrr %0, 0xB12" : "=r"(mhpmcounter_rval[18])); - //__asm__ volatile("csrr %0, 0xB13" : "=r"(mhpmcounter_rval[19])); - //__asm__ volatile("csrr %0, 0xB14" : "=r"(mhpmcounter_rval[20])); - //__asm__ volatile("csrr %0, 0xB15" : "=r"(mhpmcounter_rval[21])); - //__asm__ volatile("csrr %0, 0xB16" : "=r"(mhpmcounter_rval[22])); - //__asm__ volatile("csrr %0, 0xB17" : "=r"(mhpmcounter_rval[23])); - //__asm__ volatile("csrr %0, 0xB18" : "=r"(mhpmcounter_rval[24])); - //__asm__ volatile("csrr %0, 0xB19" : "=r"(mhpmcounter_rval[25])); - //__asm__ volatile("csrr %0, 0xB1A" : "=r"(mhpmcounter_rval[26])); - //__asm__ volatile("csrr %0, 0xB1B" : "=r"(mhpmcounter_rval[27])); - //__asm__ volatile("csrr %0, 0xB1C" : "=r"(mhpmcounter_rval[28])); - //__asm__ volatile("csrr %0, 0xB1D" : "=r"(mhpmcounter_rval[29])); - //__asm__ volatile("csrr %0, 0xB1E" : "=r"(mhpmcounter_rval[30])); - //__asm__ volatile("csrr %0, 0xB1F" : "=r"(mhpmcounter_rval[31])); - - sum = 0; - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { - sum += mhpmcounter_rval[i]; - } - if (sum) { - //printf("ERROR: CSR MHPMCOUNTER[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MHPMCOUNTER[3] not 0x0!\n\n"); - ++err_cnt; - } - - //__asm__ volatile("csrr %0, 0xB80" : "=r"(mcycleh_rval)); // CSR unimplemented in the model - /* - if (mcycleh_rval != 0x0) { - printf("ERROR: CSR MCYCLEH not 0x0!\n\n"); - ++err_cnt; - } - */ - - //__asm__ volatile("csrr %0, 0xB82" : "=r"(minstreth_rval)); // CSR unimplemented in the model - /* - if (minstreth_rval != 0x0) { - printf("ERROR: CSR MINSTRETH not 0x0!\n\n"); - ++err_cnt; - } - */ - - __asm__ volatile("csrr %0, 0xB83" : "=r"(mhpmcounterh[3])); - //__asm__ volatile("csrr %0, 0xB84" : "=r"(mhpmcounterh[4])); - //__asm__ volatile("csrr %0, 0xB85" : "=r"(mhpmcounterh[5])); - //__asm__ volatile("csrr %0, 0xB86" : "=r"(mhpmcounterh[6])); - //__asm__ volatile("csrr %0, 0xB87" : "=r"(mhpmcounterh[7])); - //__asm__ volatile("csrr %0, 0xB88" : "=r"(mhpmcounterh[8])); - //__asm__ volatile("csrr %0, 0xB89" : "=r"(mhpmcounterh[9])); - //__asm__ volatile("csrr %0, 0xB8A" : "=r"(mhpmcounterh[10])); - //__asm__ volatile("csrr %0, 0xB8B" : "=r"(mhpmcounterh[11])); - //__asm__ volatile("csrr %0, 0xB8C" : "=r"(mhpmcounterh[12])); - //__asm__ volatile("csrr %0, 0xB8D" : "=r"(mhpmcounterh[13])); - //__asm__ volatile("csrr %0, 0xB8E" : "=r"(mhpmcounterh[14])); - //__asm__ volatile("csrr %0, 0xB8F" : "=r"(mhpmcounterh[15])); - //__asm__ volatile("csrr %0, 0xB90" : "=r"(mhpmcounterh[16])); - //__asm__ volatile("csrr %0, 0xB91" : "=r"(mhpmcounterh[17])); - //__asm__ volatile("csrr %0, 0xB92" : "=r"(mhpmcounterh[18])); - //__asm__ volatile("csrr %0, 0xB93" : "=r"(mhpmcounterh[19])); - //__asm__ volatile("csrr %0, 0xB94" : "=r"(mhpmcounterh[20])); - //__asm__ volatile("csrr %0, 0xB95" : "=r"(mhpmcounterh[21])); - //__asm__ volatile("csrr %0, 0xB96" : "=r"(mhpmcounterh[22])); - //__asm__ volatile("csrr %0, 0xB97" : "=r"(mhpmcounterh[23])); - //__asm__ volatile("csrr %0, 0xB98" : "=r"(mhpmcounterh[24])); - //__asm__ volatile("csrr %0, 0xB99" : "=r"(mhpmcounterh[25])); - //__asm__ volatile("csrr %0, 0xB9A" : "=r"(mhpmcounterh[26])); - //__asm__ volatile("csrr %0, 0xB9B" : "=r"(mhpmcounterh[27])); - //__asm__ volatile("csrr %0, 0xB9C" : "=r"(mhpmcounterh[28])); - //__asm__ volatile("csrr %0, 0xB9D" : "=r"(mhpmcounterh[29])); - //__asm__ volatile("csrr %0, 0xB9E" : "=r"(mhpmcounterh[30])); - //__asm__ volatile("csrr %0, 0xB9F" : "=r"(mhpmcounterh[31])); - - sum = 0; - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { - sum += mhpmcounterh[i]; - } - if (sum) { - //printf("ERROR: CSR MHPMCOUNTERH[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MHPMCOUNTERH[3] not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0xF11" : "=r"(mvendorid_rval)); - __asm__ volatile("csrr %0, 0xF12" : "=r"(marchid_rval)); - __asm__ volatile("csrr %0, 0xF13" : "=r"(mimpid_rval)); - __asm__ volatile("csrr %0, 0xF14" : "=r"(mhartid_rval)); - - if (mvendorid_rval != 0x0602) { - printf("ERROR: CSR MVENDOR not 0x602!\n\n"); - ++err_cnt; - } - - if (marchid_rval != 0x14) { - printf("ERROR: CSR MARCHID not 0x14!\n\n"); - ++err_cnt; - } - - if (mimpid_rval != 0x0) { - printf("ERROR: CSR MIMPLID not zero!\n\n"); - ++err_cnt; - } - - if (mhartid_rval != 0x0) { - printf("ERROR: CSR MHARTID not equal to mhartid_i!\n\n"); - ++err_cnt; - } - - // Print a summary to stdout - printf("\nCSR PoR Test\n"); - //printf("\tfflags = 0x%0x\n", fflags_rval); - //printf("\tfrm = 0x%0x\n", frm_rval); - //printf("\tfcsr = 0x%0x\n", fcsr_rval); - //printf("\tlpstart0 = 0x%0x\n", lpstart0_rval); - //printf("\tlpend0 = 0x%0x\n", lpend0_rval); - //printf("\tlpcount0 = 0x%0x\n", lpcount0_rval); - //printf("\tlpstart1 = 0x%0x\n", lpstart1_rval); - //printf("\tlpend1 = 0x%0x\n", lpend1_rval); - //printf("\tlpcount1 = 0x%0x\n", lpcount1_rval); - //printf("\tprivlv = 0x%0x\n", privlv_rval); - //printf("\tuhartid = 0x%0x\n", uhartid_rval); - printf("\tmstatus = 0x%0x\n", mstatus_rval); - printf("\tmisa = 0x%0x\n", misa_rval); - printf("\tmie = 0x%0x\n", mie_rval); - printf("\tmtvec = 0x%0x\n", mtvec_rval); - //printf("\tmcounteren = 0x%0x\n", mcounteren_rval); - //printf("\tmcountinhibit = 0x%0x\n", mcountinhibit_rval); - printf("\tmphmevent3 = 0x%0x\n", mphmevent_rval[3]); - //printf("\tmphmevent31 = 0x%0x\n", mphmevent_rval[31]); - printf("\tmscratch = 0x%0x\n", mscratch_rval); - printf("\tmepc = 0x%0x\n", mepc_rval); - printf("\tmcause = 0x%0x\n", mcause_rval); - printf("\tmtval = 0x%0x\n", mtval_rval); - printf("\tmip = 0x%0x\n", mip_rval); - //printf("\ttselect = 0x%0x\n", tselect_rval); - //printf("\ttdata1 = 0x%0x\n", tdata1_rval); - //printf("\ttdata2 = 0x%0x\n", tdata2_rval); - //printf("\ttdata3 = 0x%0x\n", tdata3_rval); - //printf("\ttinfo = 0x%0x\n", tinfo_rval); - //printf("\tmcontext = 0x%0x\n", mcontext_rval); - //printf("\tscontext = 0x%0x\n", scontext_rval); - //printf("\tdcsr = 0x%0x\n", dcsr_rval); - //printf("\tdpc = 0x%0x\n", dpc_rval); - //printf("\tdscratch0 = 0x%0x\n", dscratch0_rval); - //printf("\tdscratch1 = 0x%0x\n", dscratch1_rval); - //printf("\tmcycle = 0x%0x\n", mcycle_rval); - //printf("\tminstret = 0x%0x\n", minstret_rval); - printf("\tmhpmcounter3 = 0x%0x\n", mhpmcounter_rval[3]); - //printf("\tmhpmcounter31 = 0x%0x\n", mhpmcounter_rval[31]); - //printf("\tmcycleh = 0x%0x\n", mcycleh_rval); - //printf("\tminstreth = 0x%0x\n", minstreth_rval); - printf("\tmhpmcounterh3 = 0x%0x\n", mhpmcounterh[3]); - //printf("\tmhpmcounterh31= 0x%0x\n", mhpmcounterh[31]); - printf("\tmvendorid = 0x%0x\n", mvendorid_rval); - printf("\tmmarchid = 0x%0x\n", marchid_rval); - printf("\tmimpid = 0x%0x\n", mimpid_rval); - printf("\tmhartid = 0x%0x\n", mhartid_rval); - printf("\n\n"); - - if (!err_cnt) { - return EXIT_SUCCESS; - } else { - // TODO: drive virtual peripheral in TB to signal testcase failure - return EXIT_FAILURE; - } - -} diff --git a/cv32e40x/tests/programs/custom/modeled_csr_por/test.yaml b/cv32e40x/tests/programs/custom/modeled_csr_por/test.yaml deleted file mode 100644 index 58d3c04645..0000000000 --- a/cv32e40x/tests/programs/custom/modeled_csr_por/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: modeled_csr_por -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - CSR Power on reset test diff --git a/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.c b/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.c deleted file mode 100644 index 23f380436f..0000000000 --- a/cv32e40x/tests/programs/custom/perf_counters_instructions/perf_counters_instructions.c +++ /dev/null @@ -1,941 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Performance Counters Basic test: -** -******************************************************************************* - //lw x8, 4(sp)\n\t\ - //lh x8, 4(sp)\n\t\ - //lhu x8, 4(sp)\n\t\ - //lb x8, 4(sp)\n\t\ - //lbu x8, 4(sp)\n\t\ -*/ - -#include -#include - -#ifndef NUM_MPHMCOUNTERS -#define NUM_MHPMCOUNTERS 1 -#endif - -static int chck(unsigned int is, unsigned int should) -{ - int err; - err = is == should ? 0 : 1; - if (err) - printf("fail %d %d\n", is, should); - else - printf("pass\n"); - return err; -} - -static int chck_le(unsigned int is, unsigned int should) -{ - int err; - err = is <= should ? 0 : 1; - if (err) - printf("fail\n"); - else - printf("pass\n"); - return err; -} - -int main(int argc, char *argv[]) -{ - - volatile unsigned int mcycle_rval; - volatile unsigned int minstret_rval; - volatile unsigned int mcountinhibit_rval; - volatile unsigned int mhpmcounter_rval[32]; - volatile unsigned int mhpmevent_rval[32]; - volatile unsigned int mhartid_rval; - volatile unsigned int sum; - volatile unsigned int count; - volatile unsigned int event; - volatile unsigned int err_cnt; - - enum event_e { EVENT_CYCLES = 1 << 0, - EVENT_INSTR = 1 << 1, - EVENT_COMP_INSTR = 1 << 2, - EVENT_JUMP = 1 << 3, - EVENT_BRANCH = 1 << 4, - EVENT_BRANCH_TAKEN = 1 << 5, - EVENT_INTR_TAKEN = 1 << 6, - EVENT_DATA_READ = 1 << 7, - EVENT_DATA_WRITE = 1 << 8, - EVENT_IF_INVALID = 1 << 9, - EVENT_ID_INVALID = 1 << 10, - EVENT_EX_INVALID = 1 << 11, - EVENT_WB_INVALID = 1 << 12, - EVENT_ID_LD_STALL = 1 << 13, - EVENT_ID_JMP_STALL = 1 << 14, - EVENT_WB_DATA_STALL = 1 << 15 }; - - - __asm__ volatile(".option rvc"); - - sum = 0; - err_cnt = 0; - count = 0; - event = 0; - - unsigned int writable_counters_l = 0; - unsigned int writable_counters_h = 0; - unsigned int temp_readable; - - // Check number of implemented counters - // and test read/write by reading and writing all bits of - // the respective counter CSRs - verify that the - // read CSRs that are nonzero match up with the bits read - // from mcountinhibit - __asm__ volatile("addi t1, x0, 0xFFFFFFFF"); - __asm__ volatile("csrrw x0, 0x320, t1"); - - __asm__ volatile("csrw 0xB03, t1"); - __asm__ volatile("csrw 0xB04, t1"); - __asm__ volatile("csrw 0xB05, t1"); - __asm__ volatile("csrw 0xB06, t1"); - __asm__ volatile("csrw 0xB07, t1"); - __asm__ volatile("csrw 0xB08, t1"); - __asm__ volatile("csrw 0xB09, t1"); - __asm__ volatile("csrw 0xB0A, t1"); - __asm__ volatile("csrw 0xB0B, t1"); - __asm__ volatile("csrw 0xB0C, t1"); - __asm__ volatile("csrw 0xB0D, t1"); - __asm__ volatile("csrw 0xB0E, t1"); - __asm__ volatile("csrw 0xB0F, t1"); - __asm__ volatile("csrw 0xB10, t1"); - __asm__ volatile("csrw 0xB11, t1"); - __asm__ volatile("csrw 0xB12, t1"); - __asm__ volatile("csrw 0xB13, t1"); - __asm__ volatile("csrw 0xB14, t1"); - __asm__ volatile("csrw 0xB15, t1"); - __asm__ volatile("csrw 0xB16, t1"); - __asm__ volatile("csrw 0xB17, t1"); - __asm__ volatile("csrw 0xB18, t1"); - __asm__ volatile("csrw 0xB19, t1"); - __asm__ volatile("csrw 0xB1A, t1"); - __asm__ volatile("csrw 0xB1B, t1"); - __asm__ volatile("csrw 0xB1C, t1"); - __asm__ volatile("csrw 0xB1D, t1"); - __asm__ volatile("csrw 0xB1E, t1"); - __asm__ volatile("csrw 0xB1F, t1"); - - __asm__ volatile("csrw 0xB83, t1"); - __asm__ volatile("csrw 0xB84, t1"); - __asm__ volatile("csrw 0xB85, t1"); - __asm__ volatile("csrw 0xB86, t1"); - __asm__ volatile("csrw 0xB87, t1"); - __asm__ volatile("csrw 0xB88, t1"); - __asm__ volatile("csrw 0xB89, t1"); - __asm__ volatile("csrw 0xB8A, t1"); - __asm__ volatile("csrw 0xB8B, t1"); - __asm__ volatile("csrw 0xB8C, t1"); - __asm__ volatile("csrw 0xB8D, t1"); - __asm__ volatile("csrw 0xB8E, t1"); - __asm__ volatile("csrw 0xB8F, t1"); - __asm__ volatile("csrw 0xB90, t1"); - __asm__ volatile("csrw 0xB91, t1"); - __asm__ volatile("csrw 0xB92, t1"); - __asm__ volatile("csrw 0xB93, t1"); - __asm__ volatile("csrw 0xB94, t1"); - __asm__ volatile("csrw 0xB95, t1"); - __asm__ volatile("csrw 0xB96, t1"); - __asm__ volatile("csrw 0xB97, t1"); - __asm__ volatile("csrw 0xB98, t1"); - __asm__ volatile("csrw 0xB99, t1"); - __asm__ volatile("csrw 0xB9A, t1"); - __asm__ volatile("csrw 0xB9B, t1"); - __asm__ volatile("csrw 0xB9C, t1"); - __asm__ volatile("csrw 0xB9D, t1"); - __asm__ volatile("csrw 0xB9E, t1"); - __asm__ volatile("csrw 0xB9F, t1"); - - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr %0, 0xB03" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 3) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB04" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 4) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB05" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 5) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB06" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 6) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB07" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 7) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB08" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 8) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB09" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 9) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0A" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 10) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0B" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 11) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0C" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 12) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0D" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 13) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0E" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 14) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB0F" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 15) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB10" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 16) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB11" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 17) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB12" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 18) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB13" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 19) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB14" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 20) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB15" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 21) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB16" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 22) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB17" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 23) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB18" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 24) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB19" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 25) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1A" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 26) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1B" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 27) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1C" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 28) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1D" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 29) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1E" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 30) : writable_counters_l; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB1F" : "=r"(temp_readable)); - writable_counters_l = temp_readable ? writable_counters_l | (1 << 31) : writable_counters_l; - - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr %0, 0xB83" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 3) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB84" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 4) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB85" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 5) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB86" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 6) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB87" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 7) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB88" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 8) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB89" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 9) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8A" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 10) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8B" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 11) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8C" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 12) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8D" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 13) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8E" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 14) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB8F" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 15) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB90" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 16) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB91" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 17) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB92" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 18) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB93" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 19) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB94" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 20) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB95" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 21) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB96" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 22) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB97" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 23) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB98" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 24) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB99" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 25) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9A" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 26) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9B" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 27) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9C" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 28) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9D" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 29) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9E" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 30) : writable_counters_h; - __asm__ volatile("addi x0, %0, 0" : "=r"(temp_readable)); - __asm__ volatile("csrr t1, 0xB9F" : "=r"(temp_readable)); - writable_counters_h = temp_readable ? writable_counters_h | (1 << 31) : writable_counters_h; - - __asm__ volatile("addi t0, x0, 0"); - __asm__ volatile("csrw 0xB03, t0"); - __asm__ volatile("csrw 0xB04, t0"); - __asm__ volatile("csrw 0xB05, t0"); - __asm__ volatile("csrw 0xB06, t0"); - __asm__ volatile("csrw 0xB07, t0"); - __asm__ volatile("csrw 0xB08, t0"); - __asm__ volatile("csrw 0xB09, t0"); - __asm__ volatile("csrw 0xB0A, t0"); - __asm__ volatile("csrw 0xB0B, t0"); - __asm__ volatile("csrw 0xB0C, t0"); - __asm__ volatile("csrw 0xB0D, t0"); - __asm__ volatile("csrw 0xB0E, t0"); - __asm__ volatile("csrw 0xB0F, t0"); - __asm__ volatile("csrw 0xB10, t0"); - __asm__ volatile("csrw 0xB11, t0"); - __asm__ volatile("csrw 0xB12, t0"); - __asm__ volatile("csrw 0xB13, t0"); - __asm__ volatile("csrw 0xB14, t0"); - __asm__ volatile("csrw 0xB15, t0"); - __asm__ volatile("csrw 0xB16, t0"); - __asm__ volatile("csrw 0xB17, t0"); - __asm__ volatile("csrw 0xB18, t0"); - __asm__ volatile("csrw 0xB19, t0"); - __asm__ volatile("csrw 0xB1A, t0"); - __asm__ volatile("csrw 0xB1B, t0"); - __asm__ volatile("csrw 0xB1C, t0"); - __asm__ volatile("csrw 0xB1D, t0"); - __asm__ volatile("csrw 0xB1E, t0"); - __asm__ volatile("csrw 0xB1F, t0"); - - __asm__ volatile("csrw 0xB83, t0"); - __asm__ volatile("csrw 0xB84, t0"); - __asm__ volatile("csrw 0xB85, t0"); - __asm__ volatile("csrw 0xB86, t0"); - __asm__ volatile("csrw 0xB87, t0"); - __asm__ volatile("csrw 0xB88, t0"); - __asm__ volatile("csrw 0xB89, t0"); - __asm__ volatile("csrw 0xB8A, t0"); - __asm__ volatile("csrw 0xB8B, t0"); - __asm__ volatile("csrw 0xB8C, t0"); - __asm__ volatile("csrw 0xB8D, t0"); - __asm__ volatile("csrw 0xB8E, t0"); - __asm__ volatile("csrw 0xB8F, t0"); - __asm__ volatile("csrw 0xB90, t0"); - __asm__ volatile("csrw 0xB91, t0"); - __asm__ volatile("csrw 0xB92, t0"); - __asm__ volatile("csrw 0xB93, t0"); - __asm__ volatile("csrw 0xB94, t0"); - __asm__ volatile("csrw 0xB95, t0"); - __asm__ volatile("csrw 0xB96, t0"); - __asm__ volatile("csrw 0xB97, t0"); - __asm__ volatile("csrw 0xB98, t0"); - __asm__ volatile("csrw 0xB99, t0"); - __asm__ volatile("csrw 0xB9A, t0"); - __asm__ volatile("csrw 0xB9B, t0"); - __asm__ volatile("csrw 0xB9C, t0"); - __asm__ volatile("csrw 0xB9D, t0"); - __asm__ volatile("csrw 0xB9E, t0"); - __asm__ volatile("csrw 0xB9F, t0"); - - __asm__ volatile("csrr %0, 0x320" : "=r"(mcountinhibit_rval)); - - int v = writable_counters_l & writable_counters_h; - int num_implemented_counters = 0; - if ((mcountinhibit_rval >> 3) && ((writable_counters_l & writable_counters_h) >> 3)) { - printf("\nWritable: %0x", writable_counters_l & writable_counters_h); - for (num_implemented_counters = 0; v; num_implemented_counters++) { - v &= v - 1; - } - printf("\nNumber of detected writable/readable counters: %0d", num_implemented_counters); - } - else { - printf("\nError, writable counters / mcountinhibit mismatch: %0x, %0x", v, mcountinhibit_rval); - err_cnt += 1; - } - - printf("\n\nPerformance Counters Basic Test\n"); - - __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_rval)); - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); - - - __asm__ volatile("csrr %0, 0x320" : "=r"(mcountinhibit_rval)); - - - __asm__ volatile("csrr %0, 0xB03" : "=r"(mhpmcounter_rval[3])); - __asm__ volatile("csrr %0, 0xB04" : "=r"(mhpmcounter_rval[4])); - __asm__ volatile("csrr %0, 0xB05" : "=r"(mhpmcounter_rval[5])); - __asm__ volatile("csrr %0, 0xB06" : "=r"(mhpmcounter_rval[6])); - __asm__ volatile("csrr %0, 0xB07" : "=r"(mhpmcounter_rval[7])); - __asm__ volatile("csrr %0, 0xB08" : "=r"(mhpmcounter_rval[8])); - __asm__ volatile("csrr %0, 0xB09" : "=r"(mhpmcounter_rval[9])); - __asm__ volatile("csrr %0, 0xB0A" : "=r"(mhpmcounter_rval[10])); - __asm__ volatile("csrr %0, 0xB0B" : "=r"(mhpmcounter_rval[11])); - __asm__ volatile("csrr %0, 0xB0C" : "=r"(mhpmcounter_rval[12])); - __asm__ volatile("csrr %0, 0xB0D" : "=r"(mhpmcounter_rval[13])); - __asm__ volatile("csrr %0, 0xB0E" : "=r"(mhpmcounter_rval[14])); - __asm__ volatile("csrr %0, 0xB0F" : "=r"(mhpmcounter_rval[15])); - __asm__ volatile("csrr %0, 0xB10" : "=r"(mhpmcounter_rval[16])); - __asm__ volatile("csrr %0, 0xB11" : "=r"(mhpmcounter_rval[17])); - __asm__ volatile("csrr %0, 0xB12" : "=r"(mhpmcounter_rval[18])); - __asm__ volatile("csrr %0, 0xB13" : "=r"(mhpmcounter_rval[19])); - __asm__ volatile("csrr %0, 0xB14" : "=r"(mhpmcounter_rval[20])); - __asm__ volatile("csrr %0, 0xB15" : "=r"(mhpmcounter_rval[21])); - __asm__ volatile("csrr %0, 0xB16" : "=r"(mhpmcounter_rval[22])); - __asm__ volatile("csrr %0, 0xB17" : "=r"(mhpmcounter_rval[23])); - __asm__ volatile("csrr %0, 0xB18" : "=r"(mhpmcounter_rval[24])); - __asm__ volatile("csrr %0, 0xB19" : "=r"(mhpmcounter_rval[25])); - __asm__ volatile("csrr %0, 0xB1A" : "=r"(mhpmcounter_rval[26])); - __asm__ volatile("csrr %0, 0xB1B" : "=r"(mhpmcounter_rval[27])); - __asm__ volatile("csrr %0, 0xB1C" : "=r"(mhpmcounter_rval[28])); - __asm__ volatile("csrr %0, 0xB1D" : "=r"(mhpmcounter_rval[29])); - __asm__ volatile("csrr %0, 0xB1E" : "=r"(mhpmcounter_rval[30])); - __asm__ volatile("csrr %0, 0xB1F" : "=r"(mhpmcounter_rval[31])); - - - __asm__ volatile("csrr %0, 0x323" : "=r"(mhpmevent_rval[3])); - __asm__ volatile("csrr %0, 0x324" : "=r"(mhpmevent_rval[4])); - __asm__ volatile("csrr %0, 0x325" : "=r"(mhpmevent_rval[5])); - __asm__ volatile("csrr %0, 0x326" : "=r"(mhpmevent_rval[6])); - __asm__ volatile("csrr %0, 0x327" : "=r"(mhpmevent_rval[7])); - __asm__ volatile("csrr %0, 0x328" : "=r"(mhpmevent_rval[8])); - __asm__ volatile("csrr %0, 0x329" : "=r"(mhpmevent_rval[9])); - __asm__ volatile("csrr %0, 0x32A" : "=r"(mhpmevent_rval[10])); - __asm__ volatile("csrr %0, 0x32B" : "=r"(mhpmevent_rval[11])); - __asm__ volatile("csrr %0, 0x32C" : "=r"(mhpmevent_rval[12])); - __asm__ volatile("csrr %0, 0x32D" : "=r"(mhpmevent_rval[13])); - __asm__ volatile("csrr %0, 0x32E" : "=r"(mhpmevent_rval[14])); - __asm__ volatile("csrr %0, 0x32F" : "=r"(mhpmevent_rval[15])); - __asm__ volatile("csrr %0, 0x330" : "=r"(mhpmevent_rval[16])); - __asm__ volatile("csrr %0, 0x331" : "=r"(mhpmevent_rval[17])); - __asm__ volatile("csrr %0, 0x332" : "=r"(mhpmevent_rval[18])); - __asm__ volatile("csrr %0, 0x333" : "=r"(mhpmevent_rval[19])); - __asm__ volatile("csrr %0, 0x334" : "=r"(mhpmevent_rval[20])); - __asm__ volatile("csrr %0, 0x335" : "=r"(mhpmevent_rval[21])); - __asm__ volatile("csrr %0, 0x336" : "=r"(mhpmevent_rval[22])); - __asm__ volatile("csrr %0, 0x337" : "=r"(mhpmevent_rval[23])); - __asm__ volatile("csrr %0, 0x338" : "=r"(mhpmevent_rval[24])); - __asm__ volatile("csrr %0, 0x339" : "=r"(mhpmevent_rval[25])); - __asm__ volatile("csrr %0, 0x33A" : "=r"(mhpmevent_rval[26])); - __asm__ volatile("csrr %0, 0x33B" : "=r"(mhpmevent_rval[27])); - __asm__ volatile("csrr %0, 0x33C" : "=r"(mhpmevent_rval[28])); - __asm__ volatile("csrr %0, 0x33D" : "=r"(mhpmevent_rval[29])); - __asm__ volatile("csrr %0, 0x33E" : "=r"(mhpmevent_rval[30])); - __asm__ volatile("csrr %0, 0x33F" : "=r"(mhpmevent_rval[31])); - - for (int i=3; i<32; i++) { - sum += mhpmevent_rval[i]; - } - if (sum) { - printf("ERROR: CSR MHPMEVENT[3..31] not 0x0!\n\n"); - ++err_cnt; - } - - - sum = 0; - for (int i=3; i<32; i++) { - sum += mhpmcounter_rval[i]; - } - if (sum) { - printf("ERROR: CSR MHPMCOUNTER[3..31] not 0x0!\n\n"); - ++err_cnt; - } - - - if (mcycle_rval != 0x0) { - printf("ERROR: CSR MCYCLE not 0x0!\n\n"); - ++err_cnt; - } - - if (minstret_rval != 0x0) { - printf("ERROR: CSR MINSTRET not 0x0!\n\n"); - ++err_cnt; - } - - if (mcountinhibit_rval != 0xD) { - printf("ERROR: CSR MCOUNTINHIBIT not 0xD!\n\n"); - ++err_cnt; - } - - - printf("MCYCLE Initial Value is %0x\n", mcycle_rval); - printf("MINSTRET Initial Value is %0x\n", minstret_rval); - printf("MCOUNTINHIBIT Initial Value is %0x\n", mcountinhibit_rval); - -////////////////////////////////////////////////////////////// - // To complete code coverage try to write all unimplemented HPMEVENT registers - for (int i = 3; i <= 31; i++) { - volatile unsigned int revent; - volatile unsigned int wevent = (unsigned int) -1; - - - if (i >= NUM_MHPMCOUNTERS+3) { - switch (i) { - case 3: - __asm__ volatile("csrw mhpmevent3, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent3" : "=r"(revent)); - break; - case 4: - __asm__ volatile("csrw mhpmevent4, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent4" : "=r"(revent)); - break; - case 5: - __asm__ volatile("csrw mhpmevent5, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent5" : "=r"(revent)); - break; - case 6: - __asm__ volatile("csrw mhpmevent6, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent6" : "=r"(revent)); - break; - case 7: - __asm__ volatile("csrw mhpmevent7, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent7" : "=r"(revent)); - break; - case 8: - __asm__ volatile("csrw mhpmevent8, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent8" : "=r"(revent)); - break; - case 9: - __asm__ volatile("csrw mhpmevent9, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent9" : "=r"(revent)); - break; - case 10: - __asm__ volatile("csrw mhpmevent10, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent10" : "=r"(revent)); - break; - case 11: - __asm__ volatile("csrw mhpmevent11, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent11" : "=r"(revent)); - break; - case 12: - __asm__ volatile("csrw mhpmevent12, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent12" : "=r"(revent)); - break; - case 13: - __asm__ volatile("csrw mhpmevent13, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent13" : "=r"(revent)); - break; - case 14: - __asm__ volatile("csrw mhpmevent14, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent14" : "=r"(revent)); - break; - case 15: - __asm__ volatile("csrw mhpmevent15, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent15" : "=r"(revent)); - break; - case 16: - __asm__ volatile("csrw mhpmevent16, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent16" : "=r"(revent)); - break; - case 17: - __asm__ volatile("csrw mhpmevent17, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent17" : "=r"(revent)); - break; - case 18: - __asm__ volatile("csrw mhpmevent18, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent18" : "=r"(revent)); - break; - case 19: - __asm__ volatile("csrw mhpmevent19, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent19" : "=r"(revent)); - break; - case 20: - __asm__ volatile("csrw mhpmevent20, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent20" : "=r"(revent)); - break; - case 21: - __asm__ volatile("csrw mhpmevent21, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent21" : "=r"(revent)); - break; - case 22: - __asm__ volatile("csrw mhpmevent22, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent22" : "=r"(revent)); - break; - case 23: - __asm__ volatile("csrw mhpmevent23, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent23" : "=r"(revent)); - break; - case 24: - __asm__ volatile("csrw mhpmevent24, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent24" : "=r"(revent)); - break; - case 25: - __asm__ volatile("csrw mhpmevent25, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent25" : "=r"(revent)); - break; - case 26: - __asm__ volatile("csrw mhpmevent26, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent26" : "=r"(revent)); - break; - case 27: - __asm__ volatile("csrw mhpmevent27, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent27" : "=r"(revent)); - break; - case 28: - __asm__ volatile("csrw mhpmevent28, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent28" : "=r"(revent)); - break; - case 29: - __asm__ volatile("csrw mhpmevent29, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent29" : "=r"(revent)); - break; - case 30: - __asm__ volatile("csrw mhpmevent30, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent30" : "=r"(revent)); - break; - case 31: - __asm__ volatile("csrw mhpmevent31, %0" : : "r"(wevent)); - __asm__ volatile("csrr %0, mhpmevent31" : "=r"(revent)); - break; - } - - if (revent != 0) { - printf("ERROR: MHPMEVENT%d does not read back zero 0x%0x\n", i, revent); - ++err_cnt; - } - } - } - -////////////////////////////////////////////////////////////// - // Count load use hazards - printf("\nCount load use hazards"); - - event = EVENT_ID_LD_STALL; // Trigger on load use hazards - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x4, 0(sp)\n\t\ - addi x5, x4, 1\n\t\ - lw x4, 0(sp)\n\t\ - lw x4, 4(sp)\n\t\ - addi x6, x4, 4\n\t\ - lh x8, 4(sp)\n\t\ - addi x6, x8, 4\n\t\ - lhu x6, 4(sp)\n\t\ - lb x6, 4(sp)\n\t\ - addi x5, x6, 1\n\t\ - lbu x6, 4(sp)\n\t\ - lh x5, 4(sp)\n\t\ - addi x5, x5, 4\n\t\ - addi x7, x0, 1" \ - : : : "x4", "x5", "x6", "x7", "x8"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 15); - - - printf("Load use hazards count = %d\n", count); - - err_cnt += chck_le(count, 5); - - - ////////////////////////////////////////////////////////////// - // Count jump register hazards - printf("\nCount Jump register hazards"); - - event = EVENT_ID_JMP_STALL; // Trigger on jump register hazards - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - lh x4, 4(sp)\n\t\ - addi x4, x4, 10\n\t\ - lw x4, 4(sp)\n\t\ - addi x4, x4, 10\n\t\ - addi x4, x4, 10\n\t\ - addi x4, x4, 10\n\t\ - auipc x4, 0x0\n\t\ - addi x4, x4, 10\n\t\ - jalr x0, x4, 0x0" \ - : : : "x4"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 18); - - printf("Jump register hazards count = %d\n", count); - err_cnt += chck_le(count, 3); // 3 if no instruction if stalls are present - - ////////////////////////////////////////////////////////////// - // Count memory read transactions - printf("\nCount memory read transactions"); - - event = EVENT_DATA_READ; // Trigger on loads - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("lw x4, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("j jump_target_memread"); // do not count jump in mhpmevent3 - __asm__ volatile("nop"); // do not count nop in instret - __asm__ volatile("jump_target_memread:"); - __asm__ volatile("lw x4, 0(sp)"); // count++ - __asm__ volatile("addi x4, x4, 10"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 6); - - printf("Load count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count memory write transactions - printf("\nCount memory write transactions"); - - event = EVENT_DATA_WRITE; // Trigger on stores - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("mulh x0, x0, x0"); - __asm__ volatile("sw x0, 0(sp)"); // count++ - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Store count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count jumps - printf("\nCount jumps"); - - event = EVENT_JUMP; // Trigger on jumps - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("j jump_target_0"); // count++ - __asm__ volatile("jump_target_0:"); - __asm__ volatile("j jump_target_1"); // count++ - __asm__ volatile("jump_target_1:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 3); - - printf("Jump count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Count branches (conditional) - printf("\nCount branches (conditional)"); - - event = EVENT_BRANCH; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_0"); // count++ - __asm__ volatile("branch_target_0:"); - __asm__ volatile("bne x0, x0, branch_target_1"); // count++ - __asm__ volatile("branch_target_1:"); - __asm__ volatile("beq x0, x0, branch_target_2"); // count++ - __asm__ volatile("branch_target_2:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Branch count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Count branches taken (conditional) - printf("\nCount branches taken (conditional)"); - - event = EVENT_BRANCH_TAKEN; // Trigger on on taken branches - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("beq x0, x0, branch_target_3"); // count++ - __asm__ volatile("branch_target_3:"); - __asm__ volatile("bne x0, x0, branch_target_4"); // (not taken) - __asm__ volatile("branch_target_4:"); - __asm__ volatile("beq x0, x0, branch_target_5"); // count++ - __asm__ volatile("branch_target_5:"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Branch taken count = %d\n", count); - err_cnt += chck(count, 2); - - ////////////////////////////////////////////////////////////// - // Compressed instructions - printf("\nCompressed instructions"); - - event = EVENT_COMP_INSTR; // Trigger on compressed instructions - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("c.addi x15, 1\n\t\ - c.nop\n\t\ - c.addi x15, 1" \ - : : : "x15"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 4); - - printf("Compressed count = %d\n", count); - err_cnt += chck(count, 3); - - ////////////////////////////////////////////////////////////// - // Retired instruction count - printf("\nRetired instruction count"); - - event = EVENT_INSTR; // Trigger on retired instructions - __asm__ volatile(".option rvc"); - __asm__ volatile("csrw 0x323, %0 " : : "r"(event)); // Set mhpmevent3 - __asm__ volatile("csrwi 0xB02, 0x0"); // minstret = 0 - __asm__ volatile("csrwi 0xB03, 0x0"); // mhpmcounter3 = 0 - __asm__ volatile("csrwi 0x320, 0x0"); // Enable counters - __asm__ volatile("sw x0, 0(sp)\n\t\ - addi t0, x0, 5\n\t\ - addi t1, x0, 0\n\t\ - addi t2, x0, 0\n\t\ - lw t2, 0(sp)\n\t\ - branch_target: addi t2, t2, 1\n\t\ - addi t1, t1, 1\n\t\ - lw t2, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - sw t1, 0(sp)\n\t\ - bne t0, t1, branch_target\n\t\ - j jump_target\n\t\ - lw t2, 0(sp)\n\t\ - lw t2, 0(sp)\n\t\ - jump_target: nop\n\t\ - nop\n\t\ - nop" \ - : : : "t0", "t1", "t2"); - __asm__ volatile("csrwi 0x320, 0x1F"); // Inhibit mcycle, minstret, mhpmcounter3-4 - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // minstret - __asm__ volatile("csrr %0, 0xB03" : "=r"(count)); // mhpmcounter3 - - printf("\nminstret count = %d\n", minstret_rval); - err_cnt += chck(minstret_rval, 5 + 6*5 + 4 + 1); - - printf("Retired instruction count = %d\n", count); - err_cnt += chck(count, 5 + 6*5 + 4 + 1); - - ////////////////////////////////////////////////////////////// - // Check for errors - printf("\nDone\n"); - - if (err_cnt) - printf("FAILURE. %d errors\n\n", err_cnt); - else - printf("SUCCESS\n\n"); - - return err_cnt; - - - printf("MCYCLE Final Read Value is %0x\n", mcycle_rval); - printf("MINSTRET Final Read Value is %0x\n", minstret_rval); - printf("MCOUNTINHIBIT Final Read Value is %0x\n", mcountinhibit_rval); - printf("MHARTID Final Read Value is %0x\n", mhartid_rval); - - printf("DONE!\n\n"); - -} - diff --git a/cv32e40x/tests/programs/custom/perf_counters_instructions/test.yaml b/cv32e40x/tests/programs/custom/perf_counters_instructions/test.yaml deleted file mode 100644 index 41f2fd970a..0000000000 --- a/cv32e40x/tests/programs/custom/perf_counters_instructions/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: perf_counters_instructions -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Performance Counters Basic Test diff --git a/cv32e40x/tests/programs/custom/pma/README.md b/cv32e40x/tests/programs/custom/pma/README.md deleted file mode 100644 index 0367c97aa0..0000000000 --- a/cv32e40x/tests/programs/custom/pma/README.md +++ /dev/null @@ -1,3 +0,0 @@ -Here are directed tests for the PMA. -It captures the majority of the directed tests specified in the vPlan. -When running, one must specify a config like `make ... CFG=pma`. diff --git a/cv32e40x/tests/programs/custom/pma/pma.c b/cv32e40x/tests/programs/custom/pma/pma.c deleted file mode 100644 index d87b665182..0000000000 --- a/cv32e40x/tests/programs/custom/pma/pma.c +++ /dev/null @@ -1,430 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 - -#include -#include - -#define EXCEPTION_INSN_ACCESS_FAULT 1 -#define EXCEPTION_LOAD_ACCESS_FAULT 5 -#define EXCEPTION_STOREAMO_ACCESS_FAULT 7 -#define MEM_ADDR_0 0 -#define IO_ADDR (0x1A110800 + 16) -#define MEM_ADDR_1 0x1A111000 -#define MTVAL_READ 0 -#define MTBLJALVEC 0 // TODO update when RTL is implemented -#define TBLJ_TARGET_ADDR (IO_ADDR + 8) - -static volatile uint32_t mcause = 0; -static volatile uint32_t mepc = 0; -static volatile uint32_t mtval = 0; -static volatile uint32_t retpc = 0; - -// Exception-causing instructions -static void (*instr_access_fault)(void) = (void (*)(void))IO_ADDR; -void misaligned_store(void) { - uint32_t tmp; - tmp = 0xBBBBBBBB; - __asm__ volatile("sw %0, 1(%1)" : "=r"(tmp) : "r"(IO_ADDR)); -} -void load_misaligned_io(void) {__asm__ volatile("lw t0, 3(%0)" : : "r"(IO_ADDR));} -void load_misaligned_iomem(void) {__asm__ volatile("lw t0, 0(%0)" : : "r"(MEM_ADDR_1 - 3));} -void load_misaligned_memio(void) {__asm__ volatile("lw t0, 0(%0)" : : "r"(IO_ADDR - 1));} -void store_first_access(void) {__asm__ volatile("sw %0, 2(%1)" : : "r"(0x11223344), "r"(IO_ADDR));} -void store_second_access(void) {__asm__ volatile("sw %0, -2(%1)" : : "r"(0x22334455), "r"(MEM_ADDR_1));} - -__attribute__((naked)) -void provoke(void (*f)(void)) { - // Prolog - __asm__ volatile("addi sp,sp,-64"); - __asm__ volatile("sw ra, 0(sp)"); - __asm__ volatile("sw a0, 4(sp)"); - __asm__ volatile("sw a1, 8(sp)"); - __asm__ volatile("sw a2, 12(sp)"); - __asm__ volatile("sw a3, 16(sp)"); - __asm__ volatile("sw a4, 20(sp)"); - __asm__ volatile("sw a5, 24(sp)"); - __asm__ volatile("sw a6, 28(sp)"); - __asm__ volatile("sw a7, 32(sp)"); - __asm__ volatile("sw t0, 36(sp)"); - __asm__ volatile("sw t1, 40(sp)"); - __asm__ volatile("sw t2, 44(sp)"); - __asm__ volatile("sw t3, 48(sp)"); - __asm__ volatile("sw t4, 52(sp)"); - __asm__ volatile("sw t5, 56(sp)"); - __asm__ volatile("sw t6, 60(sp)"); - - // Let trap handler know where to continue - __asm__ volatile("addi %0, ra, 0" : "=r"(retpc)); - - // Call the function that shall trap - f(); - - // Handler must do epilog -} - -static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { - if (actual != expect) { - printf(msg); - printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); - exit(EXIT_FAILURE); - } -} - -__attribute__((naked)) -void u_sw_irq_handler(void) { // overrides a "weak" symbol in the bsp - __asm__ volatile("csrr %0, mcause" : "=r"(mcause)); - __asm__ volatile("csrr %0, mepc" : "=r"(mepc)); - __asm__ volatile("csrr %0, mtval" : "=r"(mtval)); - - __asm__ volatile("csrw mepc, %0" : : "r"(retpc)); - printf("exec in u_sw_irq_handler, mcause=%lx, mepc=%lx, retpc=%lx\n", mcause, mepc, retpc); - - // provoke() did prolog, handler does epilog - __asm__ volatile("lw ra, 0(sp)"); - __asm__ volatile("lw a0, 4(sp)"); - __asm__ volatile("lw a1, 8(sp)"); - __asm__ volatile("lw a2, 12(sp)"); - __asm__ volatile("lw a3, 16(sp)"); - __asm__ volatile("lw a4, 20(sp)"); - __asm__ volatile("lw a5, 24(sp)"); - __asm__ volatile("lw a6, 28(sp)"); - __asm__ volatile("lw a7, 32(sp)"); - __asm__ volatile("lw t0, 36(sp)"); - __asm__ volatile("lw t1, 40(sp)"); - __asm__ volatile("lw t2, 44(sp)"); - __asm__ volatile("lw t3, 48(sp)"); - __asm__ volatile("lw t4, 52(sp)"); - __asm__ volatile("lw t5, 56(sp)"); - __asm__ volatile("lw t6, 60(sp)"); - __asm__ volatile("addi sp,sp,64"); - __asm__ volatile("mret"); -} - -static void reset_volatiles(void) { - mcause = -1; - mepc = -1; - mtval = -1; -} - -static void check_load_vs_regfile(void) { - // within this scope, t0 regs etc should be free to use (ABI, not preserved) - uint32_t tmp; - - // check misaligned in IO - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xAAAAAAAA), "r"(IO_ADDR)); - __asm__ volatile("sw %0, 4(%1)" : : "r"(0xBBBBBBBB), "r"(IO_ADDR)); - __asm__ volatile("li t0, 0x11223344"); - provoke(load_misaligned_io); - __asm__ volatile("mv %0, t0" : "=r"(tmp)); // t0 must be "rd" in load_misaligned_io() - /* TODO enable when RTL is implemented - assert_or_die(tmp, 0x11223344, "error: misaligned IO load shouldn't touch regfile\n"); - */ - - // check misaligned border from IO to MEM - __asm__ volatile("sw %0, -4(%1)" : : "r"(0xAAAAAAAA), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xBBBBBBBB), "r"(MEM_ADDR_1)); - __asm__ volatile("li t0, 0x22334455"); - provoke(load_misaligned_iomem); - __asm__ volatile("mv %0, t0" : "=r"(tmp)); - /* TODO enable when RTL is implemented - assert_or_die(tmp, 0x22334455, "error: misaligned IO/MEM load shouldn't touch regfile\n"); - */ - - // check misaligned border from MEM to IO - __asm__ volatile("sw %0, -4(%1)" : : "r"(0xAAAAAAAA), "r"(IO_ADDR)); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xBBBBBBBB), "r"(IO_ADDR)); - __asm__ volatile("li t0, 0x33445566"); - provoke(load_misaligned_memio); - __asm__ volatile("mv %0, t0" : "=r"(tmp)); - /* TODO enable when RTL is implemented - assert_or_die(tmp, 0x33445566, "error: misaligned MEM/IO load shouldn't touch regfile\n"); - */ - - // TODO can one programmatically confirm that these addresses are indeed in such regions as intended? -} - -static void check_zce_push(void) { - uint32_t defaults[] = {0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD}; - uint32_t sp; - uint32_t ra; - uint32_t tmp; - - // Prologue - __asm__ volatile("mv %0, sp" : "=r"(sp)); // Saving "sp", for we shall tamper with it - - // Setup preparations - __asm__ volatile("mv sp, %0" : : "r"(MEM_ADDR_1 + 4)); // Set "sp" to have room for 1 MEM before entering IO - __asm__ volatile("mv %0, ra" : "=r"(ra)); // Saving "ra" for later use - __asm__ volatile("sw %0, 0(%1)" : : "r"(defaults[0]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -4(%1)" : : "r"(defaults[1]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -8(%1)" : : "r"(defaults[2]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -12(%1)" : : "r"(defaults[3]), "r"(MEM_ADDR_1)); - - // Run the push stimuli - /* TODO enabled when RTL is implemented - __asm__ volatile(".word 0x000240AB"); // TODO "push {ra, s0-s1}, -16" - */ - - // Epilogue - __asm__ volatile("mv sp, %0" : : "r"(sp)); // Better restore this quickly - - // Assert results - /* TODO enabled when RTL is implemented - assert_or_die(mcause, EXCEPTION_STOREAMO_ACCESS_FAULT, "error: bad push should except\n"); - assert_or_die(mepc, (MEM_ADDR_1 - 4), "error: bad push, unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: bad push, unexpected mtval\n"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, ra, "error: PUSH to MEM should SW successfully\n"); - */ - __asm__ volatile("lw %0, -4(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, defaults[1], "error: PUSH to IO should not SW\n"); - __asm__ volatile("lw %0, -8(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, defaults[2], "error: Trailing PUSHes to IO should not SW\n"); -} - -static void check_zce_pop(void) { - uint32_t defaults[] = {0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD}; - register uint32_t sp asm ("s8"); // (ask C to not use the registers needed for testing) - register uint32_t s0 asm ("s9"); - register uint32_t s1 asm ("s10"); - register uint32_t ra asm ("s11"); // Hereby pledge to not intentionally use s11, to prevent ra getting corrupted - uint32_t tmp; - - // Prologue - __asm__ volatile("mv %0, sp" : "=r"(sp)); // Saving "sp", for we shall tamper with it - __asm__ volatile("mv %0, ra" : "=r"(ra)); // Saving "ra", for we shall tamper with it - - // Setup - __asm__ volatile("mv sp, %0" : : "r"(MEM_ADDR_1 + 4 - 16)); // Set previous "sp" to have room for 1 MEM before entering IO - __asm__ volatile("sw %0, 0(%1)" : : "r"(defaults[0]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -4(%1)" : : "r"(defaults[1]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -8(%1)" : : "r"(defaults[2]), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, -12(%1)" : : "r"(defaults[3]), "r"(MEM_ADDR_1)); - __asm__ volatile("mv %0, s0" : "=r"(s0)); // Will check against this later - __asm__ volatile("mv %0, s1" : "=r"(s1)); // Will check against this later - - // Run the instruction - /* TODO enable when RTL is implemented - __asm__ volatile("pop {ra, s0-s1}, 16"); - */ - - // Epilogue 1/2 - __asm__ volatile("mv sp, %0" : : "r"(sp)); - - // Assert results - /* TODO enable when RTL is implemented - assert_or_die(mcause, EXCEPTION_LOAD_ACCESS_FAULT, "error: bad pop should except\n"); - assert_or_die(mepc, (MEM_ADDR_1 - 4), "error: bad pop, unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: bad pop, unexpected mtval\n"); - __asm__ volatile("mv %0, ra" : "=r"(tmp)); - assert_or_die(tmp, defaults[0], "error: POP from MEM should LW ra successfully\n"); - */ - __asm__ volatile("mv %0, s0" : "=r"(tmp)); - assert_or_die(tmp, s0, "error: POP from IO should not LW\n"); - __asm__ volatile("mv %0, s1" : "=r"(tmp)); - assert_or_die(tmp, s1, "error: POP from IO should not continue LWing\n"); - //TODO are assertions good enough that C accidentally using the same registers will either be caught or not be a problem? - - // Epilogue 2/2 - __asm__ volatile("mv ra, %0" : : "r"(ra)); -} - -static int fail_first_tblj(void) { - int mepc = -1; - - /* TODO enable when RTL is implemented - // TODO make sure the target address is non-executable, so we can check if mtval matches first fetch - __asm__ volatile("c.tbljal 0"); - */ - __asm__ volatile("auipc %0, 0" : "=r"(mepc)); - mepc -= 4; - - return mepc; -} - -int main(void) { - uint32_t tmp; - - printf("\nHello, PMA test!\n\n"); - assert_or_die(mcause, 0, "error: mcause variable should initially be 0\n"); - assert_or_die(mepc, 0, "error: mepc variable should initially be 0\n"); - assert_or_die(mtval, 0, "error: mtval variable should initially be 0\n"); - - // TODO "mtval" should in the future not be read-only read-zero. - - - // Exec should only work for "main memory" regions - - reset_volatiles(); - provoke(instr_access_fault); - assert_or_die(mcause, EXCEPTION_INSN_ACCESS_FAULT, "error: expected instruction access fault\n"); - assert_or_die(mepc, IO_ADDR, "error: expected different mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: expected different mtval\n"); - - - // Non-naturally aligned stores to I/O regions - - // sanity check that aligned stores are ok - reset_volatiles(); - tmp = 0xAAAAAAAA; - __asm__ volatile("sw %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, -1, "error: aligned store should not change mcause\n"); - assert_or_die(mepc, -1, "error: aligned store should not change mepc\n"); - assert_or_die(mtval, -1, "error: aligned store should not change mtval\n"); - - // check that misaligned stores except - reset_volatiles(); - provoke(misaligned_store); - assert_or_die(mcause, EXCEPTION_STOREAMO_ACCESS_FAULT, "error: misaligned store unexpected mcause\n"); - //TODO:ropeders fix: assert_or_die(mepc, (IO_ADDR + 1), "error: misaligned store unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: misaligned store unexpected mtval\n"); - - // check that misaligned store to MEM is alright - reset_volatiles(); - tmp = 0xCCCCCCCC; - __asm__ volatile("sw %0, -9(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, -1, "error: misaligned store to main affected mcause\n"); - assert_or_die(mepc, -1, "error: misaligned store to main affected mepc\n"); - assert_or_die(mtval, -1, "error: misaligned store to main affected mtval\n"); - - - // Non-naturally aligned loads within I/O regions - - // sanity check that aligned load is no problem - reset_volatiles(); - tmp = 0; - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); // Depends on "store" test filling memory first - assert_or_die(!tmp, 0, "error: load should not yield zero\n"); // TODO ensure memory content matches - assert_or_die(mcause, -1, "error: natty access should not change mcause\n"); - assert_or_die(mepc, -1, "error: natty access should not change mepc\n"); - assert_or_die(mtval, -1, "error: natty access should not change mtval\n"); - - // check that misaligned load will except - /* TODO enable when RTL is implemented - reset_volatiles(); - __asm__ volatile("lw %0, 5(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, EXCEPTION_LOAD_ACCESS_FAULT, "error: misaligned IO load should except\n"); - assert_or_die(mepc, (IO_ADDR + 5), "error: misaligned IO load unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: misaligned IO load unexpected mtval\n"); - */ - // TODO more kinds of |addr[0:1]? Try LH too? - - // check that misaligned to MEM does not fail - reset_volatiles(); - tmp = 0; - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(0x80)); - assert_or_die(!tmp, 0, "error: load from main should not yield zero\n"); - assert_or_die(mcause, -1, "error: main access should not change mcause\n"); - assert_or_die(mepc, -1, "error: main access should not change mepc\n"); - assert_or_die(mtval, -1, "error: main access should not change mtval\n"); - - - // Misaligned load fault shouldn't touch regfile - - // check that various split load access fault leaves regfile untouched - check_load_vs_regfile(); - - - // Misaligned store fault shouldn't reach bus in second access - - // check IO store failing in first access - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xAAAAAAAA), "r"(IO_ADDR)); - __asm__ volatile("sw %0, 4(%1)" : : "r"(0xBBBBBBBB), "r"(IO_ADDR)); - provoke(store_first_access); - /* TODO enable when RTL is implemented - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(tmp, 0xAAAAAAAA, "error: misaligned first store entered bus\n"); - __asm__ volatile("lw %0, 4(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(tmp, 0xBBBBBBBB, "error: misaligned second store entered bus\n"); - */ - // TODO how to programmatically confirm that these region settings match as intended? - - // check IO to MEM store failing in first access - __asm__ volatile("sw %0, -4(%1)" : : "r"(0xAAAAAAAA), "r"(MEM_ADDR_1)); - __asm__ volatile("sw %0, 0(%1)" : : "r"(0xBBBBBBBB), "r"(MEM_ADDR_1)); - provoke(store_second_access); - /* TODO enable when RTL is implemented - __asm__ volatile("lw %0, -4(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, 0xAAAAAAAA, "error: misaligned IO/MEM first store entered bus\n"); - __asm__ volatile("lw %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - assert_or_die(tmp, 0xBBBBBBBB, "error: misaligned IO/MEM second store entered bus\n"); - */ - // TODO how to programmatically confirm that these region settings match as intended? - - - // Atomics should work only where it is allowed - - // Sanity check that atomic ops (lr/sc) to allowed regions is ok - reset_volatiles(); - /* TODO enable when RTL is implemented - __asm__ volatile("lr.w %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - __asm__ volatile("sc.w %0, %0, 0(%1)" : "=r"(tmp) : "r"(MEM_ADDR_1)); - */ - assert_or_die(mcause, -1, "error: atomics to legal region should not except\n"); - assert_or_die(mepc, -1, "error: atomics to legal region unexpected mepc\n"); - assert_or_die(mtval, -1, "error: atomics to legal region unexpected mtval\n"); - - // Load-reserved to disallowed regions raises precise exception - reset_volatiles(); - /* TODO enable when RTL is implemented - __asm__ volatile("lr.w %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, EXCEPTION_LOAD_ACCESS_FAULT, "error: load-reserved to non-atomic should except\n"); - assert_or_die(mepc, IO_ADDR, "error: load-reserved to non-atomic unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: load-reserved to non-atomic unexpected mtval\n"); - */ - - // Store-conditional to disallowed regions raises precise exception - reset_volatiles(); - /* TODO enable when RTL is implemented - __asm__ volatile("sc.w %0, %0, 0(%1)" : "=r"(tmp) : "r"(IO_ADDR)); - assert_or_die(mcause, EXCEPTION_STOREAMO_ACCESS_FAULT, "error: store-conditional to non-atomic should except\n"); - assert_or_die(mepc, IO_ADDR, "error: store-conditional to non-atomic unexpected mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: store-conditional to non-atomic unexpected mtval\n"); - */ - - - // Check Zce-related PMA features - - // Push instrs should fault to IO but pass for MEM - check_zce_push(); - - // Pop instrs should fault to IO but pass for MEM - check_zce_pop(); - - // Table jump failing first fetch should be the fault of the table jump - reset_volatiles(); - tmp = fail_first_tblj(); - /* TODO enable when RTL is implemented - assert_or_die(mcause, EXCEPTION_INSN_ACCESS_FAULT, "error: tblj failing first should instruction access fault\n"); - assert_or_die(mepc, tmp, "error: tblj first expected different mepc\n"); - assert_or_die(mtval, MTBLJALVEC, "error: tblj first expected different mtval\n"); - */ - - // Table jump failing second fetch should be the fault of the target - reset_volatiles(); - /* TODO enable when RTL is implemented - make sure table is executable but target is not - __asm__ volatile("c.tbljal 1"); - assert_or_die(mcause, EXCEPTION_INSN_ACCESS_FAULT, "error: tblj failing second should instruction access fault\n"); - assert_or_die(mepc, TBLJ_TARGET_ADDR, "error: tblj second expected different mepc\n"); - assert_or_die(mtval, MTVAL_READ, "error: tblj second expected different mtval\n"); - */ - - - printf("\nGoodbye, PMA test!\n\n"); - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/pma/test.yaml b/cv32e40x/tests/programs/custom/pma/test.yaml deleted file mode 100644 index 2ea71a5aa9..0000000000 --- a/cv32e40x/tests/programs/custom/pma/test.yaml +++ /dev/null @@ -1,6 +0,0 @@ -name: pma -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Directed test for the PMA. -plusargs: > - +enable_pma=1 diff --git a/cv32e40x/tests/programs/custom/pma_0reg/README.md b/cv32e40x/tests/programs/custom/pma_0reg/README.md deleted file mode 100644 index 188a647772..0000000000 --- a/cv32e40x/tests/programs/custom/pma_0reg/README.md +++ /dev/null @@ -1,3 +0,0 @@ -Here is a directed test for covering the default PMA behavior when PMA_NUM_REGIONS=0. -When running, the default config (`make` without specifying `CFG=...`) shold be appropriate. -If any defaults are later changed, the important part is that PMA_NUM_REGIONS must be 0. diff --git a/cv32e40x/tests/programs/custom/pma_0reg/pma_0reg.c b/cv32e40x/tests/programs/custom/pma_0reg/pma_0reg.c deleted file mode 100644 index 2b8731ffb2..0000000000 --- a/cv32e40x/tests/programs/custom/pma_0reg/pma_0reg.c +++ /dev/null @@ -1,58 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 - -#include -#include - -#define ADDR 0x1A110800 // Repurposing the dbg section because it is otherwise not occupied in this test - -void u_sw_irq_handler(void) { // overrides a "weak" symbol in the bsp - printf("u_sw_irq_handler: exception occured\n"); - exit(EXIT_FAILURE); -} - -int main(void) { - uint32_t tmp; - - printf("\nhello pma_0reg\n\n"); - - - // Misaligned should pass - - // Misaligned load should pass - __asm__ volatile("lh %0, 7(%1)" : "=r"(tmp) : "r"(ADDR)); // would except and not continue if anything went wrong - - // Misaligned store should pass - __asm__ volatile("sw %0, 9(%1)" : "=r"(tmp) : "r"(ADDR)); - - - // Atomics should pass - - // Load-reserved should pass - /* TODO enable when RTL is implemented - __asm__ volatile("lr.w %0, (%1)" : "=r"(tmp) : "r"(ADDR + 8)); - */ - - // Store-conditional should pass - /* TODO enable when RTL is implemented - __asm__ volatile("sc.w %0, %0, (%1)" : "=r"(tmp) : "r"(ADDR + 12)); - */ - - - printf("\ngoodbye pma_0reg\n\n"); - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/pma_0reg/test.yaml b/cv32e40x/tests/programs/custom/pma_0reg/test.yaml deleted file mode 100644 index e04e947d64..0000000000 --- a/cv32e40x/tests/programs/custom/pma_0reg/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: pma_0reg -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Directed test for the PMA when zero regions are defined. diff --git a/cv32e40x/tests/programs/custom/pma_debug/README.md b/cv32e40x/tests/programs/custom/pma_debug/README.md deleted file mode 100644 index 54cac9b6dc..0000000000 --- a/cv32e40x/tests/programs/custom/pma_debug/README.md +++ /dev/null @@ -1,2 +0,0 @@ -This is a test for the debug-related aspects of the pma. -Run with CFG on command line `make ... CFG=pma_debug`. diff --git a/cv32e40x/tests/programs/custom/pma_debug/pma_debug.c b/cv32e40x/tests/programs/custom/pma_debug/pma_debug.c deleted file mode 100644 index 2fc73952aa..0000000000 --- a/cv32e40x/tests/programs/custom/pma_debug/pma_debug.c +++ /dev/null @@ -1,216 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 - -#include -#include - -#define DEBUG_REQ_CONTROL_REG *(volatile int *) CV_VP_DEBUG_CONTROL_BASE) - -#define DBG_ADDR 0x1A110800 -#define IO_ADDR (DBG_ADDR - 16) -#define IO_ADDR_2 (IO_ADDR + 4) -#define MCAUSE_INSTRUCTION_ACCESS_FAULT 1 -#define MTVAL_READ 0 - -typedef union { - struct { - unsigned int start_delay : 15; // 14: 0 - unsigned int rand_start_delay : 1; // 15 - unsigned int pulse_width : 13; // 28:16 - unsigned int rand_pulse_width : 1; // 29 - unsigned int pulse_mode : 1; // 30 0 = level, 1 = pulse - unsigned int value : 1; // 31 - } fields; - unsigned int bits; -} debug_req_control_t; - -volatile int g_debug_entered = 0; -volatile int g_expect_exception = 0; -volatile int g_expect_dmexcept = 0; - -__attribute__((naked)) -void debugger_epilogue(void) { - asm("la sp, __debugger_stack_start"); - asm("addi sp, sp, 0x80"); // get top of stack region - - asm("lw a0, -8(sp)"); - asm("lw a1, -12(sp)"); - asm("lw a2, -16(sp)"); - asm("lw a3, -20(sp)"); - asm("lw a4, -24(sp)"); - asm("lw a5, -28(sp)"); - asm("lw a6, -32(sp)"); - asm("lw a7, -36(sp)"); - - asm("lw t0, -40(sp)"); - asm("lw t1, -44(sp)"); - asm("lw t2, -48(sp)"); - asm("lw t3, -52(sp)"); - asm("lw t4, -56(sp)"); - asm("lw t5, -60(sp)"); - asm("lw t6, -64(sp)"); - - asm("lw ra, -4(sp)"); - asm("csrr sp, dscratch"); - - __asm__ volatile("dret"); - while (1) - ; -} - -static void assert_or_die(uint32_t actual, uint32_t expect, char *msg) { - if (actual != expect) { - printf(msg); - printf("expected = 0x%lx (%ld), got = 0x%lx (%ld)\n", expect, (int32_t)expect, actual, (int32_t)actual); - exit(EXIT_FAILURE); - } -} - -__attribute__((section(".debugger_exception"))) -void dm_exception(void) { - printf("dm_exception handled"); - g_expect_dmexcept = 0; - debugger_epilogue(); -} - -void u_sw_irq_handler(void) { // overrides a "weak" symbol in the bsp - uint32_t mcause; - - __asm__ volatile("csrr %0, mcause" : "=r"(mcause)); - assert_or_die(mcause, MCAUSE_INSTRUCTION_ACCESS_FAULT, "error: irq, unexpected mcause value\n"); - - return; // should continue test, assuming no intermediary ABI function call touched "ra" -} - -void debugger(void) { - uint32_t dcsr, dpc; - uint32_t mcause, mepc, mtval; - static uint32_t step_enabled = 0; - - g_debug_entered = 1; - - if (!step_enabled) { - __asm__ volatile("csrr %0, dcsr": "=r"(dcsr)); - dcsr |= (1 << 2); - __asm__ volatile("csrw dcsr, %0": : "r"(dcsr)); - } - - // Handle the single-step test - if (g_expect_exception) { - __asm__ volatile("csrr %0, dpc": "=r"(dpc)); - __asm__ volatile("csrr %0, mcause": "=r"(mcause)); - __asm__ volatile("csrr %0, mepc": "=r"(mepc)); - __asm__ volatile("csrr %0, mtval": "=r"(mtval)); - - int exception_handled = - (dpc == (uint32_t)u_sw_irq_handler) - && (mcause == MCAUSE_INSTRUCTION_ACCESS_FAULT) - && (mepc == IO_ADDR) - && (mtval == MTVAL_READ); - - if (exception_handled) { - printf("single-step exception handled\n"); - g_expect_exception = 0; - } - } - - // Handle the dm_exception test - if (g_expect_dmexcept) { - ((void (*)(void))IO_ADDR_2)(); - while (1) - ; - } - - debugger_epilogue(); -} - -__attribute__((naked)) -void debugger_prologue(void) { - // assuming "sp" and "ra" are already saved and set - - asm("sw a0, -8(sp)"); - asm("sw a1, -12(sp)"); - asm("sw a2, -16(sp)"); - asm("sw a3, -20(sp)"); - asm("sw a4, -24(sp)"); - asm("sw a5, -28(sp)"); - asm("sw a6, -32(sp)"); - asm("sw a7, -36(sp)"); - - asm("sw t0, -40(sp)"); - asm("sw t1, -44(sp)"); - asm("sw t2, -48(sp)"); - asm("sw t3, -52(sp)"); - asm("sw t4, -56(sp)"); - asm("sw t5, -60(sp)"); - asm("sw t6, -64(sp)"); - - //asm("addi sp, sp, -64"); - asm("csrr sp, dscratch"); // use "normal" stack, not the tiny debug stack - - debugger(); - while (1) - ; -} - -__attribute__((section(".debugger"), naked)) -void debugger_entry(void) { - asm("csrw dscratch, sp"); - asm("la sp, __debugger_stack_start"); - asm("addi sp, sp, 0x80"); // get top of stack region - asm("sw ra, -4(sp)"); - debugger_prologue(); -} - -int main(void) { - debug_req_control_t debug_req_control; - - // This test could potentially be faster if one enables/disables single-stepping more meticulously. - // It would make the code less clean, but know that it could be possible. - - printf("\nhello pma_debug\n\n"); - - // Enable debug mode and single-stepping - debug_req_control = (debug_req_control_t) { - .fields.start_delay = 0, - .fields.rand_start_delay = 0, - .fields.pulse_width = 5, // FIXME: BUG: one clock pulse cause core to lock up - .fields.rand_pulse_width = 0, - .fields.pulse_mode = 1, - .fields.value = 1, - }; - DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - printf("requested debug mode\n"); - while (!g_debug_entered) - ; - - // Test that pma exception from single-stepping goes back to debug mode as expected - g_expect_exception = 1; - ((void (*)(void))IO_ADDR)(); - if (g_expect_exception) { - assert_or_die(1, 0, "error: debug code should have handled the pma exception\n"); - } - - // Test that pma exception within debug mode goes as expected - g_expect_dmexcept = 1; - if (g_expect_dmexcept) { - assert_or_die(1, 0, "error: should have handled dm_exception test\n"); - } - - printf("\ngoodbye pma_debug\n\n"); - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/programs/custom/pma_debug/test.yaml b/cv32e40x/tests/programs/custom/pma_debug/test.yaml deleted file mode 100644 index e5dbf89501..0000000000 --- a/cv32e40x/tests/programs/custom/pma_debug/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: pma_debug -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Directed test for debug-related aspects of the PMA. diff --git a/cv32e40x/tests/programs/custom/requested_csr_por/requested_csr_por.c b/cv32e40x/tests/programs/custom/requested_csr_por/requested_csr_por.c deleted file mode 100644 index 5cf2f18919..0000000000 --- a/cv32e40x/tests/programs/custom/requested_csr_por/requested_csr_por.c +++ /dev/null @@ -1,441 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** CSR power-on-reset test: Reads the CSRs and prints some useful (?) -** messages to stdout. Will fail if read value does -** not match the documented PoR value. -** -** This is a manually written prototype of a (planned) generated test-program. -** The primary goals of this test-program is to get proof of life from all CV32E40X -** CSRs and asertain the status of CSR modeling in the OVPsim Reference Model. -** In this prototype, all addresses and expected values are hand-coded. -** -******************************************************************************* -*/ - -#include -#include - -#define EXP_MISA 0x40001104 - -int main(int argc, char *argv[]) -{ - // User CSRs - // Not in RM - // unsigned int fflags_rval, frm_rval, fcsr_rval; - // User Custom CSRs - // Not in RM - // unsigned int lpstart0_rval, lpend0_rval, lpcount0_rval, lpstart1_rval, lpend1_rval, lpcount1_rval; - // unsigned int fprec_rval, privlv_rval, uhartid_rval; - // Machine CSRs - unsigned int mstatus_rval, misa_rval, mie_rval, mtvec_rval; - unsigned int mcounteren_rval, mcountinhibit_rval, mphmevent_rval[32]; - unsigned int mscratch_rval, mepc_rval, mcause_rval, mtval_rval, mip_rval; - unsigned int tselect_rval, tdata1_rval, tdata2_rval, tdata3_rval, tinfo_rval; - unsigned int mcontext_rval, scontext_rval, dcsr_rval, dpc_rval, dscratch0_rval, dscratch1_rval; - unsigned int mcycle_rval, minstret_rval, mhpmcounter_rval[32], mcycleh_rval; - unsigned int minstreth_rval, mhpmcounterh[32]; - unsigned int mvendorid_rval, marchid_rval, mimpid_rval, mhartid_rval; - - int err_cnt, sum; - - err_cnt = 0; - sum = 0; - - printf("\n\n"); - - __asm__ volatile("csrr %0, 0x300" : "=r"(mstatus_rval)); - __asm__ volatile("csrr %0, 0x301" : "=r"(misa_rval)); - __asm__ volatile("csrr %0, 0x304" : "=r"(mie_rval)); - __asm__ volatile("csrr %0, 0x305" : "=r"(mtvec_rval)); - - if (mstatus_rval != 0x1800) { - printf("ERROR: CSR MSTATUS not 0x1800!\n\n"); - ++err_cnt; - } - if (misa_rval != EXP_MISA) { - printf("ERROR: CSR MISA not 0x%x!\n\n", EXP_MISA); - ++err_cnt; - } - if (mie_rval != 0x0) { - printf("ERROR: CSR MIE not 0x0!\n\n"); - ++err_cnt; - } - if (mtvec_rval != 0x0001) { - printf("ERROR: CSR MTVEC not 0x0!\n\n"); - ++err_cnt; - } - - // This doesn't work because __asm__ is a macro (sigh) - //num = (int)strtol(addr, NULL, 16); - //for (int i=3; i<32; i++) { - // n = sprintf(string, "csrr %%0, 0x%0x", num++); - // printf("%s\n",string); - // __asm__ volatile(string : "=r"(mphmevent_rval[i])); - //} - __asm__ volatile("csrr %0, 0x323" : "=r"(mphmevent_rval[3])); - //__asm__ volatile("csrr %0, 0x324" : "=r"(mphmevent_rval[4])); - //__asm__ volatile("csrr %0, 0x325" : "=r"(mphmevent_rval[5])); - //__asm__ volatile("csrr %0, 0x326" : "=r"(mphmevent_rval[6])); - //__asm__ volatile("csrr %0, 0x327" : "=r"(mphmevent_rval[7])); - //__asm__ volatile("csrr %0, 0x328" : "=r"(mphmevent_rval[8])); - //__asm__ volatile("csrr %0, 0x329" : "=r"(mphmevent_rval[9])); - //__asm__ volatile("csrr %0, 0x32A" : "=r"(mphmevent_rval[10])); - //__asm__ volatile("csrr %0, 0x32B" : "=r"(mphmevent_rval[11])); - //__asm__ volatile("csrr %0, 0x32C" : "=r"(mphmevent_rval[12])); - //__asm__ volatile("csrr %0, 0x32D" : "=r"(mphmevent_rval[13])); - //__asm__ volatile("csrr %0, 0x32E" : "=r"(mphmevent_rval[14])); - //__asm__ volatile("csrr %0, 0x32F" : "=r"(mphmevent_rval[15])); - //__asm__ volatile("csrr %0, 0x330" : "=r"(mphmevent_rval[16])); - //__asm__ volatile("csrr %0, 0x331" : "=r"(mphmevent_rval[17])); - //__asm__ volatile("csrr %0, 0x332" : "=r"(mphmevent_rval[18])); - //__asm__ volatile("csrr %0, 0x333" : "=r"(mphmevent_rval[19])); - //__asm__ volatile("csrr %0, 0x334" : "=r"(mphmevent_rval[20])); - //__asm__ volatile("csrr %0, 0x335" : "=r"(mphmevent_rval[21])); - //__asm__ volatile("csrr %0, 0x336" : "=r"(mphmevent_rval[22])); - //__asm__ volatile("csrr %0, 0x337" : "=r"(mphmevent_rval[23])); - //__asm__ volatile("csrr %0, 0x338" : "=r"(mphmevent_rval[24])); - //__asm__ volatile("csrr %0, 0x339" : "=r"(mphmevent_rval[25])); - //__asm__ volatile("csrr %0, 0x33A" : "=r"(mphmevent_rval[26])); - //__asm__ volatile("csrr %0, 0x33B" : "=r"(mphmevent_rval[27])); - //__asm__ volatile("csrr %0, 0x33C" : "=r"(mphmevent_rval[28])); - //__asm__ volatile("csrr %0, 0x33D" : "=r"(mphmevent_rval[29])); - //__asm__ volatile("csrr %0, 0x33E" : "=r"(mphmevent_rval[30])); - //__asm__ volatile("csrr %0, 0x33F" : "=r"(mphmevent_rval[31])); - - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { - sum += mphmevent_rval[i]; - } - if (sum) { - //printf("ERROR: CSR MPHMEVENT[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MPHMEVENT[3] not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0x7A0" : "=r"(tselect_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A1" : "=r"(tdata1_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A2" : "=r"(tdata2_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A3" : "=r"(tdata3_rval)); // unimplemented in model, hardwired to zero - __asm__ volatile("csrr %0, 0x7A4" : "=r"(tinfo_rval)); // unimplemented in model - - if (tselect_rval != 0x0) { - printf("ERROR: CSR TSELECT not zero!\n\n"); - ++err_cnt; - } - - if (tdata1_rval != 0x28001040) { - printf("ERROR: CSR TDATA1 not 0x28001040!\n\n"); - ++err_cnt; - } - - if (tdata2_rval != 0x0) { - printf("ERROR: CSR TDATA2 not 0x0!\n\n"); - ++err_cnt; - } - - if (tdata3_rval != 0x0) { - printf("ERROR: CSR TDATA3 not 0x0!\n\n"); - ++err_cnt; - } - - if (tinfo_rval != 0x4) { - printf("ERROR: CSR TINFO not 0x4!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0x7A8" : "=r"(mcontext_rval)); // unimplemented in model - __asm__ volatile("csrr %0, 0x7AA" : "=r"(scontext_rval)); // unimplemented in model - // IMPERAS - Debug mode enabled - //__asm__ volatile("csrr %0, 0x7B0" : "=r"(dcsr_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B1" : "=r"(dpc_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B2" : "=r"(dscratch0_rval)); // only accessible in Debug mode - //__asm__ volatile("csrr %0, 0x7B3" : "=r"(dscratch1_rval)); // only accessible in Debug mode - - if (mcontext_rval != 0x0) { - printf("ERROR: CSR MCONTEXT not 0x0!\n\n"); - ++err_cnt; - } - - if (scontext_rval != 0x0) { - printf("ERROR: CSR SCONTEXT not 0x0!\n\n"); - ++err_cnt; - } - - //if (dcsr_rval != 0x0) { - // printf("ERROR: CSR DCSR not 0x0!\n\n"); - // ++err_cnt; - //} - - //if (dpc_rval != 0x0) { - // printf("ERROR: CSR DPC not 0x0!\n\n"); - // ++err_cnt; - //} - - //if (dscratch0_rval != 0x0) { - // printf("ERROR: CSR DSCRATCH0 not 0x0!\n\n"); - // ++err_cnt; - //} - - //if (dscratch1_rval != 0x0) { - // printf("ERROR: CSR DSCRATCH1 not 0x0!\n\n"); - // ++err_cnt; - //} - - __asm__ volatile("csrr %0, 0xB00" : "=r"(mcycle_rval)); // CSR unimplemented in the model - __asm__ volatile("csrr %0, 0xB02" : "=r"(minstret_rval)); // CSR unimplmented in the model - - if (mcycle_rval != 0x0) { - printf("ERROR: CSR MCYCLE not 0x0!\n\n"); - ++err_cnt; - } - - if (minstret_rval != 0x0) { - printf("ERROR: CSR MINSTRET not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0xB03" : "=r"(mhpmcounter_rval[3])); - //__asm__ volatile("csrr %0, 0xB04" : "=r"(mhpmcounter_rval[4])); - //__asm__ volatile("csrr %0, 0xB05" : "=r"(mhpmcounter_rval[5])); - //__asm__ volatile("csrr %0, 0xB06" : "=r"(mhpmcounter_rval[6])); - //__asm__ volatile("csrr %0, 0xB07" : "=r"(mhpmcounter_rval[7])); - //__asm__ volatile("csrr %0, 0xB08" : "=r"(mhpmcounter_rval[8])); - //__asm__ volatile("csrr %0, 0xB09" : "=r"(mhpmcounter_rval[9])); - //__asm__ volatile("csrr %0, 0xB0A" : "=r"(mhpmcounter_rval[10])); - //__asm__ volatile("csrr %0, 0xB0B" : "=r"(mhpmcounter_rval[11])); - //__asm__ volatile("csrr %0, 0xB0C" : "=r"(mhpmcounter_rval[12])); - //__asm__ volatile("csrr %0, 0xB0D" : "=r"(mhpmcounter_rval[13])); - //__asm__ volatile("csrr %0, 0xB0E" : "=r"(mhpmcounter_rval[14])); - //__asm__ volatile("csrr %0, 0xB0F" : "=r"(mhpmcounter_rval[15])); - //__asm__ volatile("csrr %0, 0xB10" : "=r"(mhpmcounter_rval[16])); - //__asm__ volatile("csrr %0, 0xB11" : "=r"(mhpmcounter_rval[17])); - //__asm__ volatile("csrr %0, 0xB12" : "=r"(mhpmcounter_rval[18])); - //__asm__ volatile("csrr %0, 0xB13" : "=r"(mhpmcounter_rval[19])); - //__asm__ volatile("csrr %0, 0xB14" : "=r"(mhpmcounter_rval[20])); - //__asm__ volatile("csrr %0, 0xB15" : "=r"(mhpmcounter_rval[21])); - //__asm__ volatile("csrr %0, 0xB16" : "=r"(mhpmcounter_rval[22])); - //__asm__ volatile("csrr %0, 0xB17" : "=r"(mhpmcounter_rval[23])); - //__asm__ volatile("csrr %0, 0xB18" : "=r"(mhpmcounter_rval[24])); - //__asm__ volatile("csrr %0, 0xB19" : "=r"(mhpmcounter_rval[25])); - //__asm__ volatile("csrr %0, 0xB1A" : "=r"(mhpmcounter_rval[26])); - //__asm__ volatile("csrr %0, 0xB1B" : "=r"(mhpmcounter_rval[27])); - //__asm__ volatile("csrr %0, 0xB1C" : "=r"(mhpmcounter_rval[28])); - //__asm__ volatile("csrr %0, 0xB1D" : "=r"(mhpmcounter_rval[29])); - //__asm__ volatile("csrr %0, 0xB1E" : "=r"(mhpmcounter_rval[30])); - //__asm__ volatile("csrr %0, 0xB1F" : "=r"(mhpmcounter_rval[31])); - - sum = 0; - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { - sum += mhpmcounter_rval[i]; - } - if (sum) { - //printf("ERROR: CSR MHPMCOUNTER[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MHPMCOUNTER[3] not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0xB80" : "=r"(mcycleh_rval)); // CSR unimplemented in the model - - if (mcycleh_rval != 0x0) { - printf("ERROR: CSR MCYCLEH not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0xB82" : "=r"(minstreth_rval)); // CSR unimplemented in the model - - if (minstreth_rval != 0x0) { - printf("ERROR: CSR MINSTRETH not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0xB83" : "=r"(mhpmcounterh[3])); - //__asm__ volatile("csrr %0, 0xB84" : "=r"(mhpmcounterh[4])); - //__asm__ volatile("csrr %0, 0xB85" : "=r"(mhpmcounterh[5])); - //__asm__ volatile("csrr %0, 0xB86" : "=r"(mhpmcounterh[6])); - //__asm__ volatile("csrr %0, 0xB87" : "=r"(mhpmcounterh[7])); - //__asm__ volatile("csrr %0, 0xB88" : "=r"(mhpmcounterh[8])); - //__asm__ volatile("csrr %0, 0xB89" : "=r"(mhpmcounterh[9])); - //__asm__ volatile("csrr %0, 0xB8A" : "=r"(mhpmcounterh[10])); - //__asm__ volatile("csrr %0, 0xB8B" : "=r"(mhpmcounterh[11])); - //__asm__ volatile("csrr %0, 0xB8C" : "=r"(mhpmcounterh[12])); - //__asm__ volatile("csrr %0, 0xB8D" : "=r"(mhpmcounterh[13])); - //__asm__ volatile("csrr %0, 0xB8E" : "=r"(mhpmcounterh[14])); - //__asm__ volatile("csrr %0, 0xB8F" : "=r"(mhpmcounterh[15])); - //__asm__ volatile("csrr %0, 0xB90" : "=r"(mhpmcounterh[16])); - //__asm__ volatile("csrr %0, 0xB91" : "=r"(mhpmcounterh[17])); - //__asm__ volatile("csrr %0, 0xB92" : "=r"(mhpmcounterh[18])); - //__asm__ volatile("csrr %0, 0xB93" : "=r"(mhpmcounterh[19])); - //__asm__ volatile("csrr %0, 0xB94" : "=r"(mhpmcounterh[20])); - //__asm__ volatile("csrr %0, 0xB95" : "=r"(mhpmcounterh[21])); - //__asm__ volatile("csrr %0, 0xB96" : "=r"(mhpmcounterh[22])); - //__asm__ volatile("csrr %0, 0xB97" : "=r"(mhpmcounterh[23])); - //__asm__ volatile("csrr %0, 0xB98" : "=r"(mhpmcounterh[24])); - //__asm__ volatile("csrr %0, 0xB99" : "=r"(mhpmcounterh[25])); - //__asm__ volatile("csrr %0, 0xB9A" : "=r"(mhpmcounterh[26])); - //__asm__ volatile("csrr %0, 0xB9B" : "=r"(mhpmcounterh[27])); - //__asm__ volatile("csrr %0, 0xB9C" : "=r"(mhpmcounterh[28])); - //__asm__ volatile("csrr %0, 0xB9D" : "=r"(mhpmcounterh[29])); - //__asm__ volatile("csrr %0, 0xB9E" : "=r"(mhpmcounterh[30])); - //__asm__ volatile("csrr %0, 0xB9F" : "=r"(mhpmcounterh[31])); - - sum = 0; - //for (int i=3; i<32; i++) { - for (int i=3; i<4; i++) { - sum += mhpmcounterh[i]; - } - if (sum) { - //printf("ERROR: CSR MHPMCOUNTERH[3..31] not 0x0!\n\n"); - printf("ERROR: CSR MHPMCOUNTERH[3] not 0x0!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0xF11" : "=r"(mvendorid_rval)); - __asm__ volatile("csrr %0, 0xF12" : "=r"(marchid_rval)); - __asm__ volatile("csrr %0, 0xF13" : "=r"(mimpid_rval)); - __asm__ volatile("csrr %0, 0xF14" : "=r"(mhartid_rval)); - - if (mvendorid_rval != 0x0602) { - printf("ERROR: CSR MVENDOR not 0x602!\n\n"); - ++err_cnt; - } - - if (marchid_rval != 0x14) { - printf("ERROR: CSR MARCHID not 0x14!\n\n"); - ++err_cnt; - } - - if (mimpid_rval != 0x0) { - printf("ERROR: CSR MIMPLID not zero!\n\n"); - ++err_cnt; - } - - if (mhartid_rval != 0x0) { - printf("ERROR: CSR MHARTID not equal to mhartid_i!\n\n"); - ++err_cnt; - } - - __asm__ volatile("csrr %0, 0x320" : "=r"(mcountinhibit_rval)); - - if (mcountinhibit_rval != 0xD) { - printf("ERROR: CSR MCOUNTINHIBIT not 0xD!\n\n"); - ++err_cnt; - } - - //__asm__ volatile("csrr %0, 0x306" : "=r"(mcounteren_rval)); // Not currently modeled - - //if (mcounteren_rval != 0x0) { - // printf("ERROR: CSR MCOUNTEREN not 0x0!\n\n"); - // ++err_cnt; - //} - - ///////////////////////////////////////////////////////////////////////////// - // These are read last because there should not have been any events which - // caused these CSRs to be incremented up to this point. - __asm__ volatile("csrr %0, 0x340" : "=r"(mscratch_rval)); - __asm__ volatile("csrr %0, 0x341" : "=r"(mepc_rval)); - __asm__ volatile("csrr %0, 0x342" : "=r"(mcause_rval)); - __asm__ volatile("csrr %0, 0x343" : "=r"(mtval_rval)); // UM says "writes are ignored, reads return 0x0" - // RM says "mtval: Unimplemented CSR (hardwired to zero)" - __asm__ volatile("csrr %0, 0x344" : "=r"(mip_rval)); - - if (mscratch_rval != 0x0) { - printf("ERROR: CSR MSCRATCH not zero!\n\n"); - ++err_cnt; - } - - if (mepc_rval != 0x0) { - printf("ERROR: CSR MEPC not zero!\n\n"); - ++err_cnt; - } - - if (mcause_rval != 0x0) { - printf("ERROR: CSR MCAUSE not zero!\n\n"); - ++err_cnt; - } - - if (mtval_rval != 0x0) { - printf("ERROR: CSR MTVAL not zero!\n\n"); - ++err_cnt; - } - - if (mip_rval != 0x0) { - printf("ERROR: CSR MIP not zero!\n\n"); - ++err_cnt; - } - - ///////////////////////////////////////////////////////////////////////////// - // Print a summary to stdout - printf("\nCSR PoR Test\n"); - //printf("\tfflags = 0x%0x\n", fflags_rval); - //printf("\tfrm = 0x%0x\n", frm_rval); - //printf("\tfcsr = 0x%0x\n", fcsr_rval); - //printf("\tlpstart0 = 0x%0x\n", lpstart0_rval); - //printf("\tlpend0 = 0x%0x\n", lpend0_rval); - //printf("\tlpcount0 = 0x%0x\n", lpcount0_rval); - //printf("\tlpstart1 = 0x%0x\n", lpstart1_rval); - //printf("\tlpend1 = 0x%0x\n", lpend1_rval); - //printf("\tlpcount1 = 0x%0x\n", lpcount1_rval); - //printf("\tprivlv = 0x%0x\n", privlv_rval); - //printf("\tuhartid = 0x%0x\n", uhartid_rval); - printf("\tmstatus = 0x%0x\n", mstatus_rval); - printf("\tmisa = 0x%0x\n", misa_rval); - printf("\tmie = 0x%0x\n", mie_rval); - printf("\tmtvec = 0x%0x\n", mtvec_rval); - //printf("\tmcounteren = 0x%0x\n", mcounteren_rval); - printf("\tmcountinhibit = 0x%0x\n", mcountinhibit_rval); - printf("\tmphmevent3 = 0x%0x\n", mphmevent_rval[3]); - //printf("\tmphmevent31 = 0x%0x\n", mphmevent_rval[31]); - printf("\tmscratch = 0x%0x\n", mscratch_rval); - printf("\tmepc = 0x%0x\n", mepc_rval); - printf("\tmcause = 0x%0x\n", mcause_rval); - printf("\tmtval = 0x%0x\n", mtval_rval); - printf("\tmip = 0x%0x\n", mip_rval); - printf("\ttselect = 0x%0x\n", tselect_rval); - printf("\ttdata1 = 0x%0x\n", tdata1_rval); - printf("\ttdata2 = 0x%0x\n", tdata2_rval); - printf("\ttdata3 = 0x%0x\n", tdata3_rval); - printf("\ttinfo = 0x%0x\n", tinfo_rval); - printf("\tmcontext = 0x%0x\n", mcontext_rval); - printf("\tscontext = 0x%0x\n", scontext_rval); - //printf("\tdcsr = 0x%0x\n", dcsr_rval); - //printf("\tdpc = 0x%0x\n", dpc_rval); - //printf("\tdscratch0 = 0x%0x\n", dscratch0_rval); - //printf("\tdscratch1 = 0x%0x\n", dscratch1_rval); - printf("\tmcycle = 0x%0x\n", mcycle_rval); - printf("\tminstret = 0x%0x\n", minstret_rval); - printf("\tmhpmcounter3 = 0x%0x\n", mhpmcounter_rval[3]); - //printf("\tmhpmcounter31 = 0x%0x\n", mhpmcounter_rval[31]); - printf("\tmcycleh = 0x%0x\n", mcycleh_rval); - printf("\tminstreth = 0x%0x\n", minstreth_rval); - printf("\tmhpmcounterh3 = 0x%0x\n", mhpmcounterh[3]); - //printf("\tmhpmcounterh31= 0x%0x\n", mhpmcounterh[31]); - printf("\tmvendorid = 0x%0x\n", mvendorid_rval); - printf("\tmmarchid = 0x%0x\n", marchid_rval); - printf("\tmimpid = 0x%0x\n", mimpid_rval); - printf("\tmhartid = 0x%0x\n", mhartid_rval); - printf("\n\n"); - - if (!err_cnt) { - return EXIT_SUCCESS; - } else { - return EXIT_FAILURE; - } - -} diff --git a/cv32e40x/tests/programs/custom/requested_csr_por/test.yaml b/cv32e40x/tests/programs/custom/requested_csr_por/test.yaml deleted file mode 100644 index dc85f88724..0000000000 --- a/cv32e40x/tests/programs/custom/requested_csr_por/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: requested_csr_por -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Requested CSR Power-on-reset test diff --git a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S b/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S deleted file mode 100644 index d0cc94486c..0000000000 --- a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_0/riscv_arithmetic_basic_test_0.S +++ /dev/null @@ -1,12326 +0,0 @@ -# BEGIN: riscv-dv -#.include "user_define.h" -#.globl _start -#.section .text -#_start: -# END: riscv-dv -# BEGIN: gtumbush -#include "corev_uvmt.h" -.include "user_define.h" -.section .text.start -.globl _start -.section .text -.type _start, @function - - -_start: - - j _start_main - -.globl _start_main -.section .text -_start_main: -# END: gtumbush -# BEGIN: riscv-dv - csrr x5, mhartid - li x6, 0 - beq x5, x6, 0f - -0: j h0_start -h0_start: - li x30, 0x40001104 - csrw misa, x30 -kernel_sp: - la x13, kernel_stack_end - -trap_vec_init: - la x30, mtvec_handler - ori x30, x30, 1 - csrw 0x305, x30 # MTVEC - -mepc_setup: - la x30, init - csrw mepc, x30 - j init_machine_mode - -init: - li x0, 0xffae545d - li x1, 0xf - li x2, 0xfaea503e - li x3, 0x0 - li x4, 0x997a59f3 - li x5, 0x0 - li x6, 0xf4dc53a8 - li x7, 0x35df9683 - li x8, 0xf1921e04 - li x9, 0xa551247f - li x10, 0xe2a90995 - li x11, 0x80000000 - li x14, 0x80000000 - li x15, 0xc - li x16, 0x0 - li x17, 0x8 - li x18, 0xa083f312 - li x19, 0x80000000 - li x20, 0x5 - li x21, 0x0 - li x22, 0x60e0dbfd - li x23, 0x0 - li x24, 0x9 - li x25, 0x7e6a229e - li x26, 0xfe02b342 - li x27, 0x4a45113b - li x28, 0xf8d2ebf6 - li x29, 0x5 - li x30, 0x80000000 - li x31, 0xf4b85b42 - la x12, user_stack_end -main: li s0, 0x0 #start riscv_int_numeric_corner_stream_39 - li s9, 0x55c5ec2 - li a0, 0x80000000 - li ra, 0xffffffff - li s11, 0xffffffff - li t3, 0x509311f5 - li t6, 0x0 - li a6, 0xffffffff - li s1, 0x80000000 - li a1, 0xffffffff - nop - sub t3, s0, t3 - add ra, a6, s9 - add ra, a6, s9 - nop - addi ra, ra, 999 - remu t6, s1, s0 - sub t3, s0, t3 - auipc t6, 688967 - add ra, a6, s9 - remu t6, s1, s0 - sub t3, s0, t3 - nop - nop - addi ra, ra, 999 - mul t3, t3, t3 - addi ra, ra, 999 - mul t3, t3, t3 - auipc t6, 688967 - lui s0, 195546 - mulhsu a1, s9, a6 - rem ra, t6, ra - nop - nop - mul t3, t3, t3 - auipc t6, 688967 - nop - lui s0, 195546 - lui s0, 195546 #end riscv_int_numeric_corner_stream_39 - li s10, 0x3b187182 #start riscv_int_numeric_corner_stream_17 - li a0, 0xffffffff - li a4, 0x80000000 - li s11, 0x0 - li t3, 0xffffffff - li gp, 0x6bf008b9 - li s5, 0x82079a19 - li s6, 0x4cc65169 - li t5, 0x80000000 - li s2, 0xa39db5a2 - addi s5, s5, 999 - nop - nop - mulhu t3, gp, s5 - mulh s11, a4, t3 - auipc t5, 688967 - mulh s11, a4, t3 - add t3, t3, t3 - nop - lui a0, 195546 - mulhu t3, gp, s5 - lui a0, 195546 - mulhsu a4, s6, a0 - nop - rem s5, a0, gp #end riscv_int_numeric_corner_stream_17 - li s11, 0xfa5b47ab #start riscv_int_numeric_corner_stream_11 - li s6, 0x80000000 - li gp, 0x2c06b99d - li t6, 0x80000000 - li a6, 0x0 - li a7, 0x0 - li sp, 0x80000000 - li t1, 0x0 - li ra, 0x235c6d08 - li s1, 0x757584ff - addi ra, s6, 999 - sub a7, a6, t1 - divu a7, s11, a7 - mulhu s1, t1, a6 - nop - mul t1, s11, s6 - auipc t6, 688967 - nop - mulhsu s1, t1, a6 - mulhsu s1, t1, a6 - nop - nop - rem s6, a6, s1 - sub a7, a6, t1 - nop - mulhu s1, t1, a6 - addi ra, s6, 999 - nop - sub a7, a6, t1 - mulhu s1, t1, a6 - mulhsu s1, t1, a6 - nop #end riscv_int_numeric_corner_stream_11 - li a1, 0x15dda8f2 #start riscv_int_numeric_corner_stream_27 - li ra, 0x89e65545 - li s6, 0x80000000 - li t4, 0x80000000 - li s9, 0xc70d87b5 - li t6, 0xaa63dcb9 - li t1, 0xb3603135 - li a7, 0x80000000 - li s3, 0xf0bfbdcf - li t5, 0x1ca1a70e - rem t5, t1, a1 - sub t1, s9, s6 - mulhu a7, s3, a7 - divu a7, a1, t4 - auipc t6, 688967 - mulh s6, s3, t4 - mulhu a7, s3, a7 - div ra, s3, t1 - lui ra, 195546 - sub t1, s9, s6 - nop - remu s6, a1, t1 - mul t1, t4, t5 - add t5, s6, t4 - mul t1, t4, t5 - mul t1, t4, t5 - mul t1, t4, t5 - sub t1, s9, s6 - addi ra, s6, 999 - nop - mulhu a7, s3, a7 - sub t1, s9, s6 #end riscv_int_numeric_corner_stream_27 - li s11, 0xffffffff #start riscv_int_numeric_corner_stream_25 - li s1, 0xffffffff - li sp, 0xffffffff - li a5, 0x0 - li t0, 0x5238ad9d - li t6, 0x0 - li s8, 0xffffffff - li a7, 0x0 - li t3, 0x80000000 - li a4, 0xf87a1de6 - addi a7, t0, 999 - mulh a7, a7, a7 - nop - mulhu sp, s11, s1 - addi a7, t0, 999 - mulhsu a5, s8, a7 - remu t6, a4, s8 - mulhsu a5, s8, a7 - remu t6, a4, s8 - add a7, sp, a7 - auipc t6, 688967 - nop - nop - mul a4, t3, t3 - nop #end riscv_int_numeric_corner_stream_25 - li a1, 0x0 #start riscv_int_numeric_corner_stream_30 - li t0, 0x80000000 - li s3, 0x7309f479 - li ra, 0x80000000 - li a5, 0xffffffff - li a6, 0x80000000 - li s8, 0x9f9ee8d2 - li a0, 0xbdf31cb0 - li s0, 0xe7fb0dd4 - li sp, 0x80000000 - mulhsu s0, t0, a6 - mulh s3, s8, s8 - nop - nop - mulhsu s0, t0, a6 - sub a6, s0, t0 - nop - mul t0, a5, a0 - mulh s3, s8, s8 - nop - add s3, a1, a6 - mul t0, a5, a0 - addi a6, t0, 999 - add s3, a1, a6 - divu a6, a1, t0 #end riscv_int_numeric_corner_stream_30 - li t5, 0x8abcfca2 #start riscv_int_numeric_corner_stream_12 - li s6, 0x80000000 - li t3, 0x4427d9eb - li t2, 0x80000000 - li t6, 0xffffffff - li s2, 0x0 - li s7, 0x0 - li a5, 0x0 - li ra, 0xbd2bbe3c - li s3, 0x0 - nop - sub ra, t3, s6 - rem t5, t3, a5 - lui ra, 195546 - lui ra, 195546 - add t3, t3, t3 - rem t5, t3, a5 - mulhu t3, a5, ra - div s2, s2, s2 - nop - remu t2, s2, s2 - sub ra, t3, s6 - mulhsu t3, ra, s2 - sub ra, t3, s6 - add t3, t3, t3 - lui ra, 195546 - nop - divu s7, s2, ra - remu t2, s2, s2 - remu t2, s2, s2 - nop - divu s7, s2, ra - add t3, t3, t3 - auipc t6, 688967 - mulhsu t3, ra, s2 - add t3, t3, t3 - auipc t6, 688967 - mulh a5, t3, t3 - addi t2, s6, 999 #end riscv_int_numeric_corner_stream_12 - li a0, 0xef977b58 #start riscv_int_numeric_corner_stream_34 - li a7, 0x0 - li t5, 0xffffffff - li a4, 0xffffffff - li a6, 0xdb294899 - li t0, 0xffffffff - li t3, 0x80000000 - li t4, 0xbc8a01e6 - li t6, 0x80000000 - li s9, 0x80000000 - addi a6, t0, 999 - divu a0, a0, t4 - auipc t6, 688967 - mulhu a6, t0, t0 - mulhsu a0, s9, a7 - divu a0, a0, t4 - addi a6, t0, 999 - addi a6, t0, 999 - divu a0, a0, t4 - remu t0, a0, a0 - mulhsu a0, s9, a7 - add t5, a0, a7 - divu a0, a0, t4 - mulhu a6, t0, t0 - mul s9, t0, t3 - sub a0, t3, a4 - mulh t0, t6, a7 - sub a0, t3, a4 - sub a0, t3, a4 - nop - nop - auipc t6, 688967 - sub a0, t3, a4 - sub a0, t3, a4 - addi a6, t0, 999 - sub a0, t3, a4 #end riscv_int_numeric_corner_stream_34 - li s9, 0x80000000 #start riscv_int_numeric_corner_stream_2 - li a6, 0xdb0dc444 - li s6, 0xc82e2f21 - li t4, 0x80000000 - li a7, 0x3f56d519 - li t2, 0xffffffff - li s3, 0x7d0bc5b6 - li a0, 0xffffffff - li a5, 0x0 - li t0, 0xffffffff - nop - add s3, a0, a7 - auipc t4, 688967 - sub t4, a6, s6 - div t0, a6, a0 - mulh s9, t2, a7 - lui t0, 195546 - add s3, a0, a7 - mulhsu a0, s9, s3 - mul t0, t4, s6 - mul t0, t4, s6 - remu a6, s3, a0 - nop - mulhsu a0, s9, s3 - add s3, a0, a7 - mul t0, t4, s6 - auipc t4, 688967 - nop - addi a6, s6, 999 - nop - auipc t4, 688967 - nop - sub t4, a6, s6 - lui t0, 195546 - sub t4, a6, s6 - div t0, a6, a0 - addi a6, s6, 999 - add s3, a0, a7 #end riscv_int_numeric_corner_stream_2 - li s8, 0x0 #start riscv_int_numeric_corner_stream_35 - li s0, 0x0 - li a5, 0x80000000 - li s2, 0x0 - li s1, 0x80000000 - li a4, 0x80000000 - li t6, 0x0 - li s11, 0x4c56e1cf - li a6, 0x0 - li t5, 0x0 - mulhsu a5, s8, s2 - addi a6, s2, 999 - mulhu s0, a4, s8 - nop - nop - mulhsu a5, s8, s2 - nop - addi a6, s2, 999 - nop - mulh t6, a4, s1 - mulhu s0, a4, s8 - lui s0, 195546 - remu a5, a5, s0 - nop - mulh t6, a4, s1 - add s2, a6, s8 - mulhsu a5, s8, s2 - nop - nop - mulhsu a5, s8, s2 - auipc t6, 688967 - div s2, s2, a4 - mul a4, s1, s8 - auipc t6, 688967 #end riscv_int_numeric_corner_stream_35 - li t3, 0xffffffff #start riscv_int_numeric_corner_stream_5 - li ra, 0x80000000 - li s6, 0x80000000 - li t5, 0xffffffff - li a5, 0x0 - li gp, 0xffffffff - li a7, 0x0 - li s0, 0xffffffff - li t2, 0x7246594c - li s7, 0x0 - auipc t5, 688967 - mulhsu t5, a7, a7 - mulhsu t5, a7, a7 - div ra, s0, t5 - addi s0, t2, 999 - addi s0, t2, 999 - mul s7, t2, s6 - sub t3, t3, s6 - sub t3, t3, s6 - divu a7, gp, a7 - addi s0, t2, 999 - add ra, a5, a7 - auipc t5, 688967 - nop - remu a5, gp, s0 - lui ra, 195546 - div ra, s0, t5 - remu a5, gp, s0 - mulhsu t5, a7, a7 - mulh a7, a7, a7 - add ra, a5, a7 - sub t3, t3, s6 - add ra, a5, a7 - divu a7, gp, a7 - add ra, a5, a7 - mulhsu t5, a7, a7 - sub t3, t3, s6 - div ra, s0, t5 - mulhu s6, gp, s0 #end riscv_int_numeric_corner_stream_5 - li tp, 0x80000000 #start riscv_int_numeric_corner_stream_8 - li sp, 0x57428f37 - li t3, 0x80000000 - li s11, 0x0 - li t0, 0xffffffff - li s5, 0x0 - li a4, 0x0 - li s0, 0xcc190b07 - li t4, 0xffffffff - li s10, 0xffffffff - mul s11, t4, s10 - lui tp, 195546 - sub sp, s0, a4 - mulhu tp, s11, t0 - remu t4, a4, s0 - nop - add s5, a4, t3 - nop - div sp, s11, a4 - rem s0, t4, s0 - nop - auipc t4, 688967 - lui tp, 195546 - nop - nop - auipc t4, 688967 - sub sp, s0, a4 - auipc t4, 688967 - rem s0, t4, s0 - nop #end riscv_int_numeric_corner_stream_8 - li a7, 0xffffffff #start riscv_int_numeric_corner_stream_26 - li a4, 0xc4356872 - li a5, 0x0 - li t4, 0x80000000 - li s6, 0x49020efb - li s0, 0x6825c196 - li tp, 0xd8b9438b - li t2, 0x80000000 - li s9, 0xffffffff - li t1, 0xffffffff - rem a7, tp, s0 - remu t2, s0, s0 - add s9, s0, s9 - nop - add s9, s0, s9 - nop - nop - remu t2, s0, s0 - nop - mulhsu a5, s0, s0 - nop - mul t4, s6, s6 - divu a7, a4, t4 - mul t4, s6, s6 - nop - mulhu tp, a5, s0 - nop - addi tp, s6, 999 - mulh s6, s9, t4 #end riscv_int_numeric_corner_stream_26 - li s6, 0x1b5f179d #start riscv_int_numeric_corner_stream_7 - li s3, 0x80000000 - li s1, 0x0 - li s2, 0x80000000 - li a6, 0x0 - li s11, 0x80000000 - li t3, 0x80000000 - li s0, 0x98e2d452 - li s7, 0x0 - li s10, 0x80000000 - add s1, s10, a6 - lui s0, 195546 - mulhsu s1, s6, s2 - nop - nop - divu a6, s0, s1 - addi a6, s7, 999 - add s1, s10, a6 - mulh t3, s11, t3 - mulh t3, s11, t3 - nop - addi a6, s7, 999 - sub t3, a6, s6 - remu a6, s1, s0 - lui s0, 195546 - lui s0, 195546 - nop - nop - lui s0, 195546 - mulhu s0, s7, s1 - add s1, s10, a6 - mulhu s0, s7, s1 - sub t3, a6, s6 - addi a6, s7, 999 - add s1, s10, a6 - remu a6, s1, s0 #end riscv_int_numeric_corner_stream_7 - li t1, 0xffffffff #start riscv_int_numeric_corner_stream_19 - li a7, 0xffffffff - li a4, 0x0 - li t0, 0x80000000 - li t5, 0x75f28eac - li s10, 0x76ad73b - li a5, 0xdbbd3320 - li tp, 0x0 - li ra, 0xffffffff - li t3, 0x80000000 - mulhsu s10, s10, a7 - mulhsu s10, s10, a7 - rem s10, a5, a4 - nop - nop - lui ra, 195546 - div ra, a5, a4 - nop - auipc t5, 688967 - add s10, a4, a7 - mulhsu s10, s10, a7 - nop - divu t0, s10, a7 - nop - divu t0, s10, a7 - mul ra, t0, s10 #end riscv_int_numeric_corner_stream_19 - li s2, 0x0 #start riscv_int_numeric_corner_stream_33 - li tp, 0x80000000 - li s5, 0x80000000 - li s0, 0x0 - li t3, 0xffffffff - li sp, 0x0 - li s6, 0x80000000 - li t4, 0x0 - li s7, 0x46a46daf - li t5, 0x80000000 - add t3, t5, t3 - addi sp, s5, 999 - div s5, s2, sp - mulhu sp, s2, s0 - addi sp, s5, 999 - add t3, t5, t3 - sub s5, s5, tp - nop - auipc t4, 688967 - nop - nop - auipc t4, 688967 - lui tp, 195546 - nop - rem sp, tp, s0 #end riscv_int_numeric_corner_stream_33 - li t4, 0xffffffff #start riscv_int_numeric_corner_stream_1 - li s2, 0x80000000 - li a5, 0x80000000 - li sp, 0x80000000 - li a6, 0x80000000 - li gp, 0x0 - li s11, 0x0 - li s0, 0x80000000 - li s3, 0x0 - li s8, 0x80000000 - mulhu s0, a5, s0 - lui s0, 195546 - lui s0, 195546 - nop - mulh gp, s3, t4 - div s3, s2, sp - nop - nop - mul a5, t4, s8 - mul a5, t4, s8 - divu s2, s0, t4 - sub sp, s0, a5 - mulhu s0, a5, s0 - div s3, s2, sp - add sp, a6, s8 - add sp, a6, s8 - nop - mulhu s0, a5, s0 - div s3, s2, sp - lui s0, 195546 - nop - nop - nop - sub sp, s0, a5 - mul a5, t4, s8 - add sp, a6, s8 - nop - sub sp, s0, a5 #end riscv_int_numeric_corner_stream_1 - li a4, 0xffffffff #start riscv_int_numeric_corner_stream_9 - li gp, 0x7dbecfed - li s6, 0x80000000 - li s9, 0xffffffff - li t5, 0xffffffff - li sp, 0x0 - li s1, 0x0 - li a5, 0x0 - li t0, 0xffffffff - li t1, 0x1d9b4eae - mulhu sp, t0, t0 - mulh t5, s9, s9 - addi t0, s6, 999 - mul s1, gp, a4 - lui t0, 195546 - auipc t5, 688967 - lui t0, 195546 - add t5, s6, t0 - auipc t5, 688967 - div s9, t0, a4 - lui t0, 195546 - add t5, s6, t0 - divu t0, sp, s9 - lui t0, 195546 - divu t0, sp, s9 - nop - nop - remu t0, sp, sp - addi t0, s6, 999 - lui t0, 195546 - nop - lui t0, 195546 - div s9, t0, a4 - mulhu sp, t0, t0 - addi t0, s6, 999 - auipc t5, 688967 - mulh t5, s9, s9 - divu t0, sp, s9 #end riscv_int_numeric_corner_stream_9 - li a1, 0x69328841 #start riscv_int_numeric_corner_stream_32 - li tp, 0xa511979b - li s8, 0x52bbaa18 - li a5, 0x96eb2b95 - li t0, 0x0 - li s0, 0x80000000 - li s5, 0x90ae797a - li t5, 0x0 - li t1, 0xffffffff - li a0, 0x80000000 - add t0, t5, s8 - add t0, t5, s8 - div a0, a5, t1 - divu s5, a1, s5 - remu tp, a1, a0 - rem s5, tp, s0 - sub t1, s0, t1 - sub t1, s0, t1 - sub t1, s0, t1 - lui tp, 195546 - mulh t5, s5, s5 - mulh t5, s5, s5 - lui tp, 195546 - lui tp, 195546 - nop #end riscv_int_numeric_corner_stream_32 - remu s5, s11, t1 - mul sp, s9, s11 - remu s5, s11, t1 - xori a4, t0, 974 - andi s8, t1, -26 - slli s11, gp, 14 - add s7, s5, a6 - c.xor a1, a2 - c.add t1, a1 - auipc t6, 688967 - c.slli t4, 28 - div t3, t1, t5 - sub s9, s6, s5 - mulhu tp, s3, a4 - c.nop - c.srli a0, 25 - srl a0, s2, a0 - slli s11, gp, 14 - mulh s11, s1, s9 - sra s1, t3, s1 - c.mv a1, s5 - sll t3, s7, a3 - sra s1, t3, s1 - slt t1, a1, a4 - slli s11, gp, 14 - add s7, s5, a6 - c.addi16sp sp, 16 - srai s10, s1, 24 - mulhu tp, s3, a4 - sra s1, t3, s1 - andi s8, t1, -26 - remu s5, s11, t1 - c.and a0, s0 - c.addi s1, 6 - mul sp, s9, s11 - sltu t2, s1, t1 - c.lui a0, 24 - mulhsu gp, a1, s1 - srli s8, t6, 19 - andi s8, t1, -26 - nop - li s8, 0x70979df7 #start riscv_int_numeric_corner_stream_38 - li t6, 0x80000000 - li t4, 0xab935de3 - li s2, 0xffffffff - li s11, 0xffffffff - li tp, 0x0 - li s1, 0x80000000 - li s10, 0xffffffff - li t2, 0x0 - li a1, 0x0 - addi tp, t2, 999 - add s1, s10, s8 - lui tp, 195546 - add s1, s10, s8 - auipc t6, 688967 - mulh t2, t4, t4 - mulhu a1, s10, s1 - mul tp, t2, s2 - remu t4, t2, s8 - lui tp, 195546 - nop - sub t4, s8, tp - remu t4, t2, s8 - addi tp, t2, 999 - mulh t2, t4, t4 #end riscv_int_numeric_corner_stream_38 - div t3, t1, t5 - rem s0, a3, a2 - or s0, a2, a0 - xor t4, s3, t3 - sltu t2, s1, t1 - srl a0, s2, a0 - sltu t2, s1, t1 - c.srli a0, 25 - sll t3, s7, a3 - and a1, t3, a6 - andi s8, t1, -26 - c.lui a0, 24 - div t3, t1, t5 - c.addi s1, 6 - c.add t1, a1 - c.addi s1, 6 - c.li a7, 27 - sub s9, s6, s5 - add s7, s5, a6 - c.mv a1, s5 - sll t3, s7, a3 - remu s5, s11, t1 - c.addi16sp sp, 16 - c.addi16sp sp, 16 - slt t1, a1, a4 - mul sp, s9, s11 - c.addi4spn a4, sp, 288 - ori t5, t2, 999 - c.add t1, a1 - c.lui a0, 24 - divu sp, ra, t0 - slt t1, a1, a4 - c.lui a0, 24 - or s0, a2, a0 - sra s1, t3, s1 - add s7, s5, a6 - sll t3, s7, a3 - sltu t2, s1, t1 - andi s8, t1, -26 - sll t3, s7, a3 - slt t1, a1, a4 - c.xor a1, a2 - andi s8, t1, -26 - srl a0, s2, a0 - and a1, t3, a6 - andi s8, t1, -26 - c.lui a0, 24 - srli s8, t6, 19 - c.lui a0, 24 - lui zero, 195546 - c.lui a0, 24 - lui zero, 195546 - srli s8, t6, 19 - mulhu tp, s3, a4 - c.xor a1, a2 - mulhu tp, s3, a4 - c.srli a0, 25 - c.slli t4, 28 - mulhsu gp, a1, s1 - c.andi a5, -1 - c.or a5, a1 - c.srai s0, 31 - or s0, a2, a0 - sll t3, s7, a3 - div t3, t1, t5 - and a1, t3, a6 - c.add t1, a1 - sll t3, s7, a3 - sra s1, t3, s1 - mulh s11, s1, s9 - nop - rem s0, a3, a2 - c.lui a0, 24 - srai s10, s1, 24 - sll t3, s7, a3 - xor t4, s3, t3 - c.mv a1, s5 - c.mv a1, s5 - c.andi a5, -1 - c.and a0, s0 - c.nop - c.sub s1, a4 - add s7, s5, a6 - sub s9, s6, s5 - c.xor a1, a2 - auipc t6, 688967 - sra s1, t3, s1 - div t3, t1, t5 - rem s0, a3, a2 - ori t5, t2, 999 - c.add t1, a1 - divu sp, ra, t0 - c.mv a1, s5 - c.li a7, 27 - c.slli t4, 28 - xori a4, t0, 974 - xori a4, t0, 974 - c.addi s1, 6 - add s7, s5, a6 - and a1, t3, a6 - mulhsu gp, a1, s1 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - sltu t2, s1, t1 - c.addi16sp sp, 16 - div t3, t1, t5 - slti tp, t6, 301 - sll t3, s7, a3 - sra s1, t3, s1 - nop - slti tp, t6, 301 - sll t3, s7, a3 - div t3, t1, t5 - addi a7, t2, -784 - c.mv a1, s5 - c.and a0, s0 - sltu t2, s1, t1 - sra s1, t3, s1 - c.addi4spn a4, sp, 288 - c.li a7, 27 - sub s9, s6, s5 - c.li a7, 27 - c.addi4spn a4, sp, 288 - c.srai s0, 31 - c.addi s1, 6 - add s7, s5, a6 - c.li a7, 27 - sltiu s6, ra, 913 - slli s11, gp, 14 - srl a0, s2, a0 - or s0, a2, a0 - srai s10, s1, 24 - c.and a0, s0 - ori t5, t2, 999 - mulh s11, s1, s9 - rem s0, a3, a2 - andi s8, t1, -26 - andi s8, t1, -26 - c.nop - c.li a7, 27 - sra s1, t3, s1 - c.or a5, a1 - srli s8, t6, 19 - c.add t1, a1 - sltu t2, s1, t1 - slt t1, a1, a4 - mulh s11, s1, s9 - nop - mulhsu gp, a1, s1 - nop - c.li a7, 27 - c.slli t4, 28 - c.srli a0, 25 - mul sp, s9, s11 - c.srli a0, 25 - mulhu tp, s3, a4 - mulhsu gp, a1, s1 - slli s11, gp, 14 - mulh s11, s1, s9 - xori a4, t0, 974 - c.li a7, 27 - divu sp, ra, t0 - c.srli a0, 25 - auipc t6, 688967 - sub s9, s6, s5 - slt t1, a1, a4 - andi s8, t1, -26 - xor t4, s3, t3 - c.srai s0, 31 - c.slli t4, 28 - ori t5, t2, 999 - ori t5, t2, 999 - div t3, t1, t5 - c.addi16sp sp, 16 - sub s9, s6, s5 - divu sp, ra, t0 - c.add t1, a1 - and a1, t3, a6 - nop - c.slli t4, 28 - lui zero, 195546 - c.nop - c.or a5, a1 - c.nop - c.add t1, a1 - c.slli t4, 28 - slt t1, a1, a4 - sll t3, s7, a3 - sra s1, t3, s1 - sll t3, s7, a3 - srai s10, s1, 24 - c.lui a0, 24 - sltiu s6, ra, 913 - nop - c.addi s1, 6 - c.addi4spn a4, sp, 288 - ori t5, t2, 999 - add s7, s5, a6 - srli s8, t6, 19 - srli s8, t6, 19 - mulh s11, s1, s9 - c.andi a5, -1 - c.or a5, a1 - addi a7, t2, -784 - addi a7, t2, -784 - sltiu s6, ra, 913 - andi s8, t1, -26 - mulhsu gp, a1, s1 - remu s5, s11, t1 - xor t4, s3, t3 - c.addi4spn a4, sp, 288 - slli s11, gp, 14 - andi s8, t1, -26 - slt t1, a1, a4 - c.nop - sra s1, t3, s1 - c.li a7, 27 - add s7, s5, a6 - c.sub s1, a4 - sll t3, s7, a3 - sll t3, s7, a3 - mulhu tp, s3, a4 - divu sp, ra, t0 - slti tp, t6, 301 - c.srai s0, 31 - c.add t1, a1 - c.srai s0, 31 - c.sub s1, a4 - slt t1, a1, a4 - c.sub s1, a4 - addi a7, t2, -784 - c.slli t4, 28 - sra s1, t3, s1 - c.mv a1, s5 - c.li a7, 27 - or s0, a2, a0 - sltiu s6, ra, 913 - slt t1, a1, a4 - c.addi16sp sp, 16 - sll t3, s7, a3 - c.xor a1, a2 - nop - slt t1, a1, a4 - srai s10, s1, 24 - sra s1, t3, s1 - add s7, s5, a6 - c.add t1, a1 - mulhu tp, s3, a4 - c.addi s1, 6 - sltu t2, s1, t1 - addi a7, t2, -784 - c.mv a1, s5 - c.li a7, 27 - div t3, t1, t5 - c.srli a0, 25 - rem s0, a3, a2 - rem s0, a3, a2 - nop - c.li a7, 27 - divu sp, ra, t0 - c.and a0, s0 - auipc t6, 688967 - c.and a0, s0 - c.srai s0, 31 - srl a0, s2, a0 - c.xor a1, a2 - rem s0, a3, a2 - sll t3, s7, a3 - add s7, s5, a6 - sltu t2, s1, t1 - sltu t2, s1, t1 - mulh s11, s1, s9 - c.and a0, s0 - remu s5, s11, t1 - ori t5, t2, 999 - c.mv a1, s5 - sll t3, s7, a3 - mulh s11, s1, s9 - div t3, t1, t5 - mul sp, s9, s11 - c.srai s0, 31 - c.xor a1, a2 - slli s11, gp, 14 - and a1, t3, a6 - c.nop - nop - srli s8, t6, 19 - xori a4, t0, 974 - add s7, s5, a6 - c.slli t4, 28 - sra s1, t3, s1 - c.srli a0, 25 - slti tp, t6, 301 - mulhsu gp, a1, s1 - remu s5, s11, t1 - c.sub s1, a4 - or s0, a2, a0 - xori a4, t0, 974 - divu sp, ra, t0 - c.li a7, 27 - slli s11, gp, 14 - sltu t2, s1, t1 - sltiu s6, ra, 913 - c.lui a0, 24 - remu s5, s11, t1 - mulh s11, s1, s9 - c.sub s1, a4 - srl a0, s2, a0 - slli s11, gp, 14 - ori t5, t2, 999 - c.mv a1, s5 - c.or a5, a1 - slti tp, t6, 301 - c.sub s1, a4 - c.and a0, s0 - c.andi a5, -1 - c.andi a5, -1 - c.li a7, 27 - mulhu tp, s3, a4 - mulhu tp, s3, a4 - c.addi4spn a4, sp, 288 - slli s11, gp, 14 - c.add t1, a1 - sll t3, s7, a3 - slli s11, gp, 14 - mulhsu gp, a1, s1 - srai s10, s1, 24 - mulhu tp, s3, a4 - xori a4, t0, 974 - slti tp, t6, 301 - c.and a0, s0 - c.addi s1, 6 - divu sp, ra, t0 - c.add t1, a1 - c.add t1, a1 - nop - c.and a0, s0 - srli s8, t6, 19 - andi s8, t1, -26 - or s0, a2, a0 - mulhu tp, s3, a4 - sll t3, s7, a3 - c.mv a1, s5 - srl a0, s2, a0 - div t3, t1, t5 - lui zero, 195546 - c.li a7, 27 - c.addi16sp sp, 16 - c.addi s1, 6 - auipc t6, 688967 - mulhsu gp, a1, s1 - nop - slt t1, a1, a4 - ori t5, t2, 999 - c.or a5, a1 - rem s0, a3, a2 - c.sub s1, a4 - andi s8, t1, -26 - c.mv a1, s5 - srli s8, t6, 19 - c.add t1, a1 - sltu t2, s1, t1 - xor t4, s3, t3 - sltiu s6, ra, 913 - srli s8, t6, 19 - c.slli t4, 28 - sub s9, s6, s5 - c.xor a1, a2 - c.xor a1, a2 - slti tp, t6, 301 - nop - mulhu tp, s3, a4 - auipc t6, 688967 - xori a4, t0, 974 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - slt t1, a1, a4 - addi a7, t2, -784 - c.nop - slti tp, t6, 301 - srl a0, s2, a0 - c.xor a1, a2 - divu sp, ra, t0 - srai s10, s1, 24 - div t3, t1, t5 - div t3, t1, t5 - divu sp, ra, t0 - c.nop - lui zero, 195546 - xor t4, s3, t3 - andi s8, t1, -26 - c.or a5, a1 - auipc t6, 688967 - lui zero, 195546 - rem s0, a3, a2 - addi a7, t2, -784 - c.lui a0, 24 - c.andi a5, -1 - slli s11, gp, 14 - and a1, t3, a6 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - mulhsu gp, a1, s1 - ori t5, t2, 999 - mulh s11, s1, s9 - c.addi s1, 6 - and a1, t3, a6 - add s7, s5, a6 - c.slli t4, 28 - mulhsu gp, a1, s1 - xor t4, s3, t3 - slt t1, a1, a4 - sra s1, t3, s1 - addi a7, t2, -784 - c.andi a5, -1 - c.xor a1, a2 - lui zero, 195546 - c.srai s0, 31 - c.nop - or s0, a2, a0 - c.nop - or s0, a2, a0 - auipc t6, 688967 - add s7, s5, a6 - c.add t1, a1 - c.addi4spn a4, sp, 288 - slti tp, t6, 301 - c.xor a1, a2 - auipc t6, 688967 - mulhsu gp, a1, s1 - xori a4, t0, 974 - sra s1, t3, s1 - andi s8, t1, -26 - c.sub s1, a4 - nop - lui zero, 195546 - c.and a0, s0 - c.lui a0, 24 - mulh s11, s1, s9 - c.slli t4, 28 - c.srli a0, 25 - slli s11, gp, 14 - divu sp, ra, t0 - c.slli t4, 28 - xori a4, t0, 974 - c.addi4spn a4, sp, 288 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - sltiu s6, ra, 913 - addi a7, t2, -784 - nop - divu sp, ra, t0 - add s7, s5, a6 - sltiu s6, ra, 913 - c.addi16sp sp, 16 - c.li a7, 27 - c.xor a1, a2 - c.addi16sp sp, 16 - and a1, t3, a6 - c.srai s0, 31 - c.addi16sp sp, 16 - addi a7, t2, -784 - c.srli a0, 25 - c.addi s1, 6 - c.addi16sp sp, 16 - c.or a5, a1 - slli s11, gp, 14 - c.nop - slt t1, a1, a4 - c.addi16sp sp, 16 - xor t4, s3, t3 - sub s9, s6, s5 - slt t1, a1, a4 - div t3, t1, t5 - divu sp, ra, t0 - remu s5, s11, t1 - rem s0, a3, a2 - slt t1, a1, a4 - addi a7, t2, -784 - and a1, t3, a6 - srl a0, s2, a0 - divu sp, ra, t0 - rem s0, a3, a2 - div t3, t1, t5 - xor t4, s3, t3 - srai s10, s1, 24 - andi s8, t1, -26 - slt t1, a1, a4 - sub s9, s6, s5 - c.li a7, 27 - div t3, t1, t5 - lui zero, 195546 - and a1, t3, a6 - c.nop - sub s9, s6, s5 - xor t4, s3, t3 - add s7, s5, a6 - c.andi a5, -1 - c.mv a1, s5 - c.add t1, a1 - rem s0, a3, a2 - xori a4, t0, 974 - c.and a0, s0 - xor t4, s3, t3 - c.srai s0, 31 - c.sub s1, a4 - rem s0, a3, a2 - nop - c.addi s1, 6 - c.sub s1, a4 - c.slli t4, 28 - sub s9, s6, s5 - c.mv a1, s5 - mulh s11, s1, s9 - mul sp, s9, s11 - xor t4, s3, t3 - sll t3, s7, a3 - mul sp, s9, s11 - div t3, t1, t5 - c.andi a5, -1 - mulhsu gp, a1, s1 - c.li a7, 27 - c.slli t4, 28 - divu sp, ra, t0 - auipc t6, 688967 - c.srai s0, 31 - c.addi16sp sp, 16 - c.and a0, s0 - c.sub s1, a4 - sra s1, t3, s1 - xor t4, s3, t3 - c.and a0, s0 - slli s11, gp, 14 - c.slli t4, 28 - srl a0, s2, a0 - c.slli t4, 28 - slli s11, gp, 14 - xor t4, s3, t3 - lui zero, 195546 - addi a7, t2, -784 - c.srai s0, 31 - xor t4, s3, t3 - mulhsu gp, a1, s1 - c.mv a1, s5 - c.lui a0, 24 - c.lui a0, 24 - div t3, t1, t5 - c.li a7, 27 - sltiu s6, ra, 913 - mulhu tp, s3, a4 - slt t1, a1, a4 - lui zero, 195546 - sra s1, t3, s1 - srl a0, s2, a0 - auipc t6, 688967 - ori t5, t2, 999 - c.li a7, 27 - andi s8, t1, -26 - and a1, t3, a6 - rem s0, a3, a2 - c.srli a0, 25 - add s7, s5, a6 - sra s1, t3, s1 - or s0, a2, a0 - c.slli t4, 28 - xori a4, t0, 974 - c.srli a0, 25 - c.addi s1, 6 - c.xor a1, a2 - xori a4, t0, 974 - divu sp, ra, t0 - mulh s11, s1, s9 - c.addi s1, 6 - sll t3, s7, a3 - addi a7, t2, -784 - andi s8, t1, -26 - c.nop - srli s8, t6, 19 - mulh s11, s1, s9 - slt t1, a1, a4 - lui zero, 195546 - c.srai s0, 31 - c.li a7, 27 - sltiu s6, ra, 913 - sltu t2, s1, t1 - divu sp, ra, t0 - mulhu tp, s3, a4 - c.sub s1, a4 - c.srai s0, 31 - c.li a7, 27 - c.slli t4, 28 - c.srli a0, 25 - nop - and a1, t3, a6 - c.xor a1, a2 - xori a4, t0, 974 - c.xor a1, a2 - xori a4, t0, 974 - c.lui a0, 24 - remu s5, s11, t1 - or s0, a2, a0 - mulh s11, s1, s9 - c.add t1, a1 - sltiu s6, ra, 913 - slt t1, a1, a4 - sra s1, t3, s1 - mulhu tp, s3, a4 - c.srai s0, 31 - c.addi16sp sp, 16 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - rem s0, a3, a2 - and a1, t3, a6 - sub s9, s6, s5 - c.andi a5, -1 - divu sp, ra, t0 - c.addi4spn a4, sp, 288 - mulh s11, s1, s9 - c.xor a1, a2 - sltu t2, s1, t1 - div t3, t1, t5 - srai s10, s1, 24 - lui zero, 195546 - c.srli a0, 25 - srli s8, t6, 19 - slli s11, gp, 14 - c.xor a1, a2 - mul sp, s9, s11 - div t3, t1, t5 - c.mv a1, s5 - c.addi16sp sp, 16 - c.lui a0, 24 - c.or a5, a1 - c.lui a0, 24 - c.add t1, a1 - c.andi a5, -1 - li s9, 0x3fdba535 #start riscv_int_numeric_corner_stream_22 - li s3, 0x4c21c560 - li a5, 0x80000000 - li a1, 0xa53a8937 - li s10, 0xd1b05e67 - li t0, 0xa5ee5d42 - li s1, 0x80000000 - li s11, 0xffffffff - li s0, 0x0 - li s5, 0xf87dbd06 - sub s5, s5, t0 - sub s5, s5, t0 - remu s5, s3, s0 - rem s5, a5, s0 - add s1, s10, s9 - lui t0, 195546 - addi t0, s5, 999 - addi t0, s5, 999 - nop - divu s9, s10, s5 - lui t0, 195546 - lui t0, 195546 - lui t0, 195546 - add s1, s10, s9 - nop - sub s5, s5, t0 - nop - nop - sub s5, s5, t0 - sub s5, s5, t0 - mulhsu s0, s0, s3 - auipc s11, 688967 - remu s5, s3, s0 - auipc s11, 688967 - addi t0, s5, 999 #end riscv_int_numeric_corner_stream_22 - addi a7, t2, -784 - c.srai s0, 31 - c.and a0, s0 - c.sub s1, a4 - ori t5, t2, 999 - c.and a0, s0 - mulhu tp, s3, a4 - c.srli a0, 25 - c.andi a5, -1 - mulh s11, s1, s9 - sub s9, s6, s5 - c.nop - slli s11, gp, 14 - sra s1, t3, s1 - lui zero, 195546 - c.or a5, a1 - mulhsu gp, a1, s1 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - c.addi16sp sp, 16 - lui zero, 195546 - c.xor a1, a2 - mulhsu gp, a1, s1 - auipc t6, 688967 - sltu t2, s1, t1 - sltu t2, s1, t1 - c.nop - andi s8, t1, -26 - sll t3, s7, a3 - add s7, s5, a6 - c.sub s1, a4 - c.nop - andi s8, t1, -26 - srl a0, s2, a0 - c.or a5, a1 - divu sp, ra, t0 - remu s5, s11, t1 - c.li a7, 27 - c.srai s0, 31 - c.lui a0, 24 - and a1, t3, a6 - auipc t6, 688967 - or s0, a2, a0 - sltu t2, s1, t1 - c.or a5, a1 - ori t5, t2, 999 - slli s11, gp, 14 - c.srli a0, 25 - auipc t6, 688967 - c.xor a1, a2 - c.and a0, s0 - c.srai s0, 31 - c.and a0, s0 - c.nop - slt t1, a1, a4 - sub s9, s6, s5 - sll t3, s7, a3 - c.li a7, 27 - slt t1, a1, a4 - c.addi s1, 6 - remu s5, s11, t1 - c.addi s1, 6 - mul sp, s9, s11 - addi a7, t2, -784 - c.srli a0, 25 - divu sp, ra, t0 - c.addi16sp sp, 16 - xori a4, t0, 974 - srai s10, s1, 24 - c.li a7, 27 - ori t5, t2, 999 - sll t3, s7, a3 - xor t4, s3, t3 - c.add t1, a1 - sub s9, s6, s5 - div t3, t1, t5 - divu sp, ra, t0 - sra s1, t3, s1 - addi a7, t2, -784 - and a1, t3, a6 - rem s0, a3, a2 - c.add t1, a1 - c.slli t4, 28 - div t3, t1, t5 - remu s5, s11, t1 - rem s0, a3, a2 - or s0, a2, a0 - c.xor a1, a2 - addi a7, t2, -784 - and a1, t3, a6 - c.sub s1, a4 - c.or a5, a1 - c.srli a0, 25 - srli s8, t6, 19 - mulh s11, s1, s9 - slti tp, t6, 301 - addi a7, t2, -784 - srl a0, s2, a0 - add s7, s5, a6 - sub s9, s6, s5 - nop - sltiu s6, ra, 913 - c.xor a1, a2 - srli s8, t6, 19 - slli s11, gp, 14 - srai s10, s1, 24 - mulh s11, s1, s9 - c.slli t4, 28 - c.sub s1, a4 - sltu t2, s1, t1 - srl a0, s2, a0 - sltu t2, s1, t1 - xori a4, t0, 974 - mulh s11, s1, s9 - mulhu tp, s3, a4 - c.addi s1, 6 - c.addi16sp sp, 16 - remu s5, s11, t1 - c.sub s1, a4 - srai s10, s1, 24 - or s0, a2, a0 - lui zero, 195546 - nop - c.xor a1, a2 - add s7, s5, a6 - ori t5, t2, 999 - slti tp, t6, 301 - sltu t2, s1, t1 - auipc t6, 688967 - rem s0, a3, a2 - mul sp, s9, s11 - xor t4, s3, t3 - c.add t1, a1 - c.sub s1, a4 - slli s11, gp, 14 - c.lui a0, 24 - xor t4, s3, t3 - c.srai s0, 31 - divu sp, ra, t0 - sltu t2, s1, t1 - c.srli a0, 25 - mulhsu gp, a1, s1 - c.sub s1, a4 - srai s10, s1, 24 - slt t1, a1, a4 - srai s10, s1, 24 - divu sp, ra, t0 - c.addi s1, 6 - sub s9, s6, s5 - c.slli t4, 28 - slti tp, t6, 301 - xor t4, s3, t3 - c.srli a0, 25 - divu sp, ra, t0 - sra s1, t3, s1 - c.add t1, a1 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - c.addi16sp sp, 16 - auipc t6, 688967 - c.sub s1, a4 - li s6, 0x346d4183 #start riscv_int_numeric_corner_stream_28 - li a6, 0x3f6be97e - li s8, 0x80000000 - li sp, 0x0 - li s10, 0x0 - li s7, 0xf9e194fe - li s11, 0x0 - li s9, 0x2fd4852a - li s0, 0xe7dc72c8 - li a1, 0xffffffff - nop - add s7, sp, s8 - sub sp, s8, s6 - addi s0, s7, 999 - sub sp, s8, s6 - nop - sub sp, s8, s6 - sub sp, s8, s6 - divu s0, s0, s9 - auipc s11, 688967 - lui s0, 195546 - mulhu sp, sp, s8 - nop - nop - mulh s11, s0, s9 - mulh s11, s0, s9 - auipc s11, 688967 - div sp, s10, sp - lui s0, 195546 - add s7, sp, s8 - mul s6, s7, s8 - mulhu sp, sp, s8 - add s7, sp, s8 - nop - sub sp, s8, s6 - auipc s11, 688967 - lui s0, 195546 - rem s7, s0, a1 #end riscv_int_numeric_corner_stream_28 - c.or a5, a1 - xori a4, t0, 974 - sub s9, s6, s5 - sltiu s6, ra, 913 - and a1, t3, a6 - nop - xor t4, s3, t3 - auipc t6, 688967 - c.srai s0, 31 - c.nop - c.srai s0, 31 - c.nop - sra s1, t3, s1 - sltu t2, s1, t1 - c.mv a1, s5 - c.xor a1, a2 - nop - nop - c.add t1, a1 - c.srli a0, 25 - c.xor a1, a2 - add s7, s5, a6 - divu sp, ra, t0 - c.addi16sp sp, 16 - ori t5, t2, 999 - remu s5, s11, t1 - c.mv a1, s5 - c.lui a0, 24 - c.and a0, s0 - mulhsu gp, a1, s1 - c.or a5, a1 - c.addi4spn a4, sp, 288 - sra s1, t3, s1 - nop - c.li a7, 27 - c.li a7, 27 - sra s1, t3, s1 - c.xor a1, a2 - c.nop - mul sp, s9, s11 - and a1, t3, a6 - div t3, t1, t5 - mulh s11, s1, s9 - slt t1, a1, a4 - c.li a7, 27 - slti tp, t6, 301 - c.sub s1, a4 - sltu t2, s1, t1 - c.addi s1, 6 - mulhsu gp, a1, s1 - c.sub s1, a4 - nop - mulhu tp, s3, a4 - lui zero, 195546 - div t3, t1, t5 - c.add t1, a1 - slt t1, a1, a4 - sltiu s6, ra, 913 - sub s9, s6, s5 - c.srai s0, 31 - srli s8, t6, 19 - and a1, t3, a6 - c.slli t4, 28 - sra s1, t3, s1 - andi s8, t1, -26 - srai s10, s1, 24 - sub s9, s6, s5 - srl a0, s2, a0 - or s0, a2, a0 - c.slli t4, 28 - xor t4, s3, t3 - c.srai s0, 31 - mulh s11, s1, s9 - c.li a7, 27 - sltiu s6, ra, 913 - slt t1, a1, a4 - slli s11, gp, 14 - divu sp, ra, t0 - c.addi s1, 6 - c.addi16sp sp, 16 - c.srai s0, 31 - xori a4, t0, 974 - add s7, s5, a6 - c.add t1, a1 - and a1, t3, a6 - mulh s11, s1, s9 - sltu t2, s1, t1 - c.srli a0, 25 - c.andi a5, -1 - slti tp, t6, 301 - div t3, t1, t5 - slt t1, a1, a4 - c.sub s1, a4 - or s0, a2, a0 - remu s5, s11, t1 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - c.nop - c.sub s1, a4 - mulh s11, s1, s9 - c.nop - andi s8, t1, -26 - slt t1, a1, a4 - ori t5, t2, 999 - c.xor a1, a2 - c.add t1, a1 - sll t3, s7, a3 - c.li a7, 27 - auipc t6, 688967 - remu s5, s11, t1 - c.mv a1, s5 - c.srai s0, 31 - div t3, t1, t5 - srli s8, t6, 19 - c.srai s0, 31 - c.add t1, a1 - c.addi s1, 6 - c.srli a0, 25 - c.xor a1, a2 - remu s5, s11, t1 - sub s9, s6, s5 - mulhu tp, s3, a4 - divu sp, ra, t0 - xor t4, s3, t3 - c.slli t4, 28 - c.or a5, a1 - sll t3, s7, a3 - slli s11, gp, 14 - c.andi a5, -1 - srl a0, s2, a0 - sltiu s6, ra, 913 - add s7, s5, a6 - c.li a7, 27 - remu s5, s11, t1 - mulhsu gp, a1, s1 - mulh s11, s1, s9 - remu s5, s11, t1 - c.srli a0, 25 - c.xor a1, a2 - mulh s11, s1, s9 - c.nop - and a1, t3, a6 - sll t3, s7, a3 - divu sp, ra, t0 - slti tp, t6, 301 - slli s11, gp, 14 - div t3, t1, t5 - c.and a0, s0 - c.addi16sp sp, 16 - c.lui a0, 24 - mulhsu gp, a1, s1 - div t3, t1, t5 - auipc t6, 688967 - slli s11, gp, 14 - remu s5, s11, t1 - and a1, t3, a6 - nop - mulh s11, s1, s9 - div t3, t1, t5 - c.or a5, a1 - srai s10, s1, 24 - remu s5, s11, t1 - mulh s11, s1, s9 - c.xor a1, a2 - slli s11, gp, 14 - c.srai s0, 31 - c.lui a0, 24 - auipc t6, 688967 - mulh s11, s1, s9 - c.slli t4, 28 - lui zero, 195546 - c.sub s1, a4 - or s0, a2, a0 - mulhu tp, s3, a4 - c.addi16sp sp, 16 - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - xor t4, s3, t3 - sltu t2, s1, t1 - addi a7, t2, -784 - slli s11, gp, 14 - srl a0, s2, a0 - srai s10, s1, 24 - andi s8, t1, -26 - remu s5, s11, t1 - sra s1, t3, s1 - srli s8, t6, 19 - div t3, t1, t5 - ori t5, t2, 999 - c.srli a0, 25 - lui zero, 195546 - mulhu tp, s3, a4 - c.or a5, a1 - sltu t2, s1, t1 - c.mv a1, s5 - c.add t1, a1 - remu s5, s11, t1 - xor t4, s3, t3 - remu s5, s11, t1 - sll t3, s7, a3 - remu s5, s11, t1 - slti tp, t6, 301 - divu sp, ra, t0 - or s0, a2, a0 - c.xor a1, a2 - addi a7, t2, -784 - sltu t2, s1, t1 - mulhu tp, s3, a4 - c.and a0, s0 - c.slli t4, 28 - slli s11, gp, 14 - sltiu s6, ra, 913 - andi s8, t1, -26 - ori t5, t2, 999 - srli s8, t6, 19 - slti tp, t6, 301 - mulhsu gp, a1, s1 - ori t5, t2, 999 - c.addi16sp sp, 16 - sub s9, s6, s5 - mulhsu gp, a1, s1 - c.li a7, 27 - sltiu s6, ra, 913 - xor t4, s3, t3 - slt t1, a1, a4 - c.addi s1, 6 - c.or a5, a1 - c.add t1, a1 - c.andi a5, -1 - c.xor a1, a2 - mulhu tp, s3, a4 - c.nop - div t3, t1, t5 - mulhsu gp, a1, s1 - c.xor a1, a2 - rem s0, a3, a2 - rem s0, a3, a2 - sltiu s6, ra, 913 - sltu t2, s1, t1 - c.and a0, s0 - mulhu tp, s3, a4 - c.lui a0, 24 - c.sub s1, a4 - c.nop - xor t4, s3, t3 - rem s0, a3, a2 - mulh s11, s1, s9 - c.add t1, a1 - c.addi s1, 6 - c.xor a1, a2 - sub s9, s6, s5 - xor t4, s3, t3 - lui zero, 195546 - addi a7, t2, -784 - or s0, a2, a0 - srai s10, s1, 24 - c.lui a0, 24 - auipc t6, 688967 - c.slli t4, 28 - mulh s11, s1, s9 - slli s11, gp, 14 - slli s11, gp, 14 - andi s8, t1, -26 - c.and a0, s0 - or s0, a2, a0 - c.sub s1, a4 - c.slli t4, 28 - nop - c.or a5, a1 - c.and a0, s0 - c.srai s0, 31 - c.slli t4, 28 - c.addi s1, 6 - slli s11, gp, 14 - mul sp, s9, s11 - c.or a5, a1 - sra s1, t3, s1 - sra s1, t3, s1 - rem s0, a3, a2 - lui zero, 195546 - c.srli a0, 25 - c.nop - sltu t2, s1, t1 - c.li a7, 27 - c.nop - c.srli a0, 25 - srl a0, s2, a0 - c.xor a1, a2 - slti tp, t6, 301 - nop - c.nop - mulhu tp, s3, a4 - sra s1, t3, s1 - mulhu tp, s3, a4 - c.add t1, a1 - c.mv a1, s5 - sltu t2, s1, t1 - sra s1, t3, s1 - sra s1, t3, s1 - c.xor a1, a2 - c.lui a0, 24 - c.add t1, a1 - srl a0, s2, a0 - addi a7, t2, -784 - mulhsu gp, a1, s1 - slt t1, a1, a4 - c.addi16sp sp, 16 - mulhu tp, s3, a4 - sra s1, t3, s1 - c.slli t4, 28 - c.or a5, a1 - slti tp, t6, 301 - c.nop - sra s1, t3, s1 - c.addi16sp sp, 16 - mulh s11, s1, s9 - c.andi a5, -1 - li t2, 0xc4932c7f #start riscv_int_numeric_corner_stream_13 - li t4, 0x2a86312c - li ra, 0x80000000 - li s0, 0x0 - li s2, 0x0 - li t6, 0xc7e65d08 - li a7, 0x836d4acb - li s11, 0xf7833188 - li s8, 0x9b44a905 - li a1, 0x80000000 - auipc t6, 688967 - nop - nop - rem s8, t6, s0 - add ra, s2, a7 - addi ra, t2, 999 - nop - rem s8, t6, s0 - nop - mulhsu s0, t2, a7 - mulhsu s0, t2, a7 - auipc t6, 688967 - mulh t4, t2, a7 - lui ra, 195546 - auipc t6, 688967 - nop - mulhsu s0, t2, a7 - mulhu ra, s11, s0 #end riscv_int_numeric_corner_stream_13 - c.srli a0, 25 - xor t4, s3, t3 - mulhsu gp, a1, s1 - xor t4, s3, t3 - andi s8, t1, -26 - lui zero, 195546 - c.lui a0, 24 - c.srli a0, 25 - sltu t2, s1, t1 - sltiu s6, ra, 913 - srli s8, t6, 19 - sltiu s6, ra, 913 - sra s1, t3, s1 - c.or a5, a1 - srai s10, s1, 24 - srl a0, s2, a0 - xor t4, s3, t3 - c.mv a1, s5 - sltiu s6, ra, 913 - sltiu s6, ra, 913 - c.and a0, s0 - sra s1, t3, s1 - c.and a0, s0 - c.srli a0, 25 - srli s8, t6, 19 - c.addi s1, 6 - andi s8, t1, -26 - or s0, a2, a0 - c.srli a0, 25 - c.xor a1, a2 - slti tp, t6, 301 - auipc t6, 688967 - mulhu tp, s3, a4 - ori t5, t2, 999 - sub s9, s6, s5 - slt t1, a1, a4 - nop - xor t4, s3, t3 - srli s8, t6, 19 - srli s8, t6, 19 - sltiu s6, ra, 913 - sll t3, s7, a3 - auipc t6, 688967 - mulhu tp, s3, a4 - c.add t1, a1 - and a1, t3, a6 - c.xor a1, a2 - sra s1, t3, s1 - srli s8, t6, 19 - mulhu tp, s3, a4 - or s0, a2, a0 - div t3, t1, t5 - c.li a7, 27 - nop - sltiu s6, ra, 913 - andi s8, t1, -26 - c.slli t4, 28 - rem s0, a3, a2 - c.srai s0, 31 - mulhu tp, s3, a4 - xori a4, t0, 974 - slli s11, gp, 14 - lui zero, 195546 - rem s0, a3, a2 - c.nop - or s0, a2, a0 - sra s1, t3, s1 - c.slli t4, 28 - divu sp, ra, t0 - c.mv a1, s5 - srl a0, s2, a0 - c.addi s1, 6 - c.addi4spn a4, sp, 288 - lui zero, 195546 - c.or a5, a1 - remu s5, s11, t1 - c.addi s1, 6 - sltu t2, s1, t1 - sll t3, s7, a3 - mul sp, s9, s11 - mul sp, s9, s11 - c.slli t4, 28 - c.slli t4, 28 - mul sp, s9, s11 - srl a0, s2, a0 - srli s8, t6, 19 - slt t1, a1, a4 - srai s10, s1, 24 - c.addi4spn a4, sp, 288 - c.addi s1, 6 - c.srli a0, 25 - slt t1, a1, a4 - xor t4, s3, t3 - add s7, s5, a6 - div t3, t1, t5 - srli s8, t6, 19 - remu s5, s11, t1 - sra s1, t3, s1 - andi s8, t1, -26 - xori a4, t0, 974 - auipc t6, 688967 - sll t3, s7, a3 - sltu t2, s1, t1 - rem s0, a3, a2 - auipc t6, 688967 - lui zero, 195546 - slli s11, gp, 14 - c.sub s1, a4 - srli s8, t6, 19 - and a1, t3, a6 - srl a0, s2, a0 - c.or a5, a1 - add s7, s5, a6 - mul sp, s9, s11 - c.srai s0, 31 - sltiu s6, ra, 913 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - sltiu s6, ra, 913 - and a1, t3, a6 - srli s8, t6, 19 - xori a4, t0, 974 - auipc t6, 688967 - mulh s11, s1, s9 - c.and a0, s0 - c.andi a5, -1 - sltiu s6, ra, 913 - nop - sll t3, s7, a3 - or s0, a2, a0 - c.xor a1, a2 - rem s0, a3, a2 - sltu t2, s1, t1 - slti tp, t6, 301 - c.xor a1, a2 - sra s1, t3, s1 - mulhsu gp, a1, s1 - c.srai s0, 31 - c.li a7, 27 - c.or a5, a1 - c.srli a0, 25 - or s0, a2, a0 - c.addi16sp sp, 16 - srai s10, s1, 24 - slt t1, a1, a4 - slli s11, gp, 14 - sub s9, s6, s5 - nop - rem s0, a3, a2 - and a1, t3, a6 - c.xor a1, a2 - mulhsu gp, a1, s1 - sltiu s6, ra, 913 - div t3, t1, t5 - c.lui a0, 24 - c.and a0, s0 - c.mv a1, s5 - sra s1, t3, s1 - c.sub s1, a4 - mulh s11, s1, s9 - auipc t6, 688967 - c.addi4spn a4, sp, 288 - add s7, s5, a6 - c.addi4spn a4, sp, 288 - or s0, a2, a0 - c.and a0, s0 - c.li a7, 27 - c.and a0, s0 - slli s11, gp, 14 - sra s1, t3, s1 - auipc t6, 688967 - srli s8, t6, 19 - xor t4, s3, t3 - sub s9, s6, s5 - and a1, t3, a6 - c.srai s0, 31 - c.mv a1, s5 - c.nop - c.xor a1, a2 - sltiu s6, ra, 913 - mul sp, s9, s11 - mul sp, s9, s11 - c.or a5, a1 - c.andi a5, -1 - c.addi16sp sp, 16 - c.li a7, 27 - c.add t1, a1 - sll t3, s7, a3 - sll t3, s7, a3 - c.addi16sp sp, 16 - slti tp, t6, 301 - c.lui a0, 24 - lui zero, 195546 - addi a7, t2, -784 - and a1, t3, a6 - auipc t6, 688967 - srli s8, t6, 19 - c.slli t4, 28 - div t3, t1, t5 - mulh s11, s1, s9 - or s0, a2, a0 - c.nop - mul sp, s9, s11 - c.li a7, 27 - c.nop - rem s0, a3, a2 - mul sp, s9, s11 - auipc t6, 688967 - slli s11, gp, 14 - c.mv a1, s5 - mulh s11, s1, s9 - c.lui a0, 24 - add s7, s5, a6 - mul sp, s9, s11 - srli s8, t6, 19 - xor t4, s3, t3 - sra s1, t3, s1 - c.nop - c.addi16sp sp, 16 - c.srli a0, 25 - xor t4, s3, t3 - mulhu tp, s3, a4 - andi s8, t1, -26 - mulh s11, s1, s9 - rem s0, a3, a2 - srai s10, s1, 24 - srl a0, s2, a0 - sll t3, s7, a3 - xori a4, t0, 974 - c.lui a0, 24 - ori t5, t2, 999 - c.srai s0, 31 - sra s1, t3, s1 - c.srli a0, 25 - xor t4, s3, t3 - c.lui a0, 24 - nop - nop - sub s9, s6, s5 - li tp, 0xc58a97b6 #start riscv_int_numeric_corner_stream_37 - li a7, 0x80000000 - li s5, 0x0 - li gp, 0x80000000 - li a4, 0xf03a9a1f - li ra, 0x0 - li s1, 0x0 - li a0, 0x9166eac1 - li t0, 0xffffffff - li sp, 0x0 - divu tp, s1, s5 - lui tp, 195546 - addi tp, t0, 999 - nop - sub tp, a7, tp - remu sp, gp, a0 - divu tp, s1, s5 - sub tp, a7, tp - rem sp, tp, a0 - sub tp, a7, tp - nop - mulh gp, s5, s5 - nop - div ra, a0, sp - nop #end riscv_int_numeric_corner_stream_37 - c.xor a1, a2 - c.li a7, 27 - c.or a5, a1 - sll t3, s7, a3 - slt t1, a1, a4 - c.nop - div t3, t1, t5 - slti tp, t6, 301 - auipc t6, 688967 - mulhsu gp, a1, s1 - slti tp, t6, 301 - divu sp, ra, t0 - sltiu s6, ra, 913 - c.and a0, s0 - c.xor a1, a2 - auipc t6, 688967 - andi s8, t1, -26 - sra s1, t3, s1 - divu sp, ra, t0 - mulh s11, s1, s9 - c.addi s1, 6 - c.or a5, a1 - c.mv a1, s5 - mulhsu gp, a1, s1 - c.add t1, a1 - c.lui a0, 24 - auipc t6, 688967 - srl a0, s2, a0 - xor t4, s3, t3 - remu s5, s11, t1 - c.nop - srli s8, t6, 19 - add s7, s5, a6 - mulhsu gp, a1, s1 - c.nop - mulh s11, s1, s9 - auipc t6, 688967 - slli s11, gp, 14 - remu s5, s11, t1 - divu sp, ra, t0 - c.add t1, a1 - sub s9, s6, s5 - div t3, t1, t5 - add s7, s5, a6 - addi a7, t2, -784 - sll t3, s7, a3 - c.addi s1, 6 - mulhsu gp, a1, s1 - c.and a0, s0 - lui zero, 195546 - srli s8, t6, 19 - rem s0, a3, a2 - rem s0, a3, a2 - mulh s11, s1, s9 - mulh s11, s1, s9 - c.slli t4, 28 - add s7, s5, a6 - c.or a5, a1 - xor t4, s3, t3 - c.sub s1, a4 - divu sp, ra, t0 - sll t3, s7, a3 - srli s8, t6, 19 - mulhu tp, s3, a4 - c.addi16sp sp, 16 - sub s9, s6, s5 - mulh s11, s1, s9 - c.andi a5, -1 - add s7, s5, a6 - ori t5, t2, 999 - sltiu s6, ra, 913 - c.and a0, s0 - andi s8, t1, -26 - rem s0, a3, a2 - or s0, a2, a0 - c.srai s0, 31 - sub s9, s6, s5 - slti tp, t6, 301 - sltiu s6, ra, 913 - mulh s11, s1, s9 - c.mv a1, s5 - mulhu tp, s3, a4 - mulhsu gp, a1, s1 - slti tp, t6, 301 - c.lui a0, 24 - auipc t6, 688967 - ori t5, t2, 999 - divu sp, ra, t0 - srli s8, t6, 19 - mul sp, s9, s11 - remu s5, s11, t1 - c.add t1, a1 - c.addi4spn a4, sp, 288 - c.addi s1, 6 - xori a4, t0, 974 - c.sub s1, a4 - or s0, a2, a0 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - mulhu tp, s3, a4 - c.xor a1, a2 - xor t4, s3, t3 - c.lui a0, 24 - srli s8, t6, 19 - mulhu tp, s3, a4 - divu sp, ra, t0 - add s7, s5, a6 - ori t5, t2, 999 - mulh s11, s1, s9 - lui zero, 195546 - sltiu s6, ra, 913 - c.addi16sp sp, 16 - xori a4, t0, 974 - xor t4, s3, t3 - c.addi16sp sp, 16 - sra s1, t3, s1 - divu sp, ra, t0 - addi a7, t2, -784 - c.add t1, a1 - divu sp, ra, t0 - nop - xori a4, t0, 974 - ori t5, t2, 999 - addi a7, t2, -784 - c.slli t4, 28 - c.srli a0, 25 - sltiu s6, ra, 913 - sltu t2, s1, t1 - c.li a7, 27 - xori a4, t0, 974 - slt t1, a1, a4 - c.srli a0, 25 - c.srai s0, 31 - c.and a0, s0 - nop - and a1, t3, a6 - sltiu s6, ra, 913 - slt t1, a1, a4 - addi a7, t2, -784 - c.or a5, a1 - xor t4, s3, t3 - c.add t1, a1 - rem s0, a3, a2 - c.andi a5, -1 - slt t1, a1, a4 - nop - xori a4, t0, 974 - sra s1, t3, s1 - slli s11, gp, 14 - andi s8, t1, -26 - xori a4, t0, 974 - c.addi16sp sp, 16 - and a1, t3, a6 - c.slli t4, 28 - srli s8, t6, 19 - slti tp, t6, 301 - srli s8, t6, 19 - or s0, a2, a0 - c.andi a5, -1 - sub s9, s6, s5 - c.addi s1, 6 - c.lui a0, 24 - c.addi16sp sp, 16 - c.nop - divu sp, ra, t0 - or s0, a2, a0 - rem s0, a3, a2 - slli s11, gp, 14 - sltu t2, s1, t1 - c.li a7, 27 - addi a7, t2, -784 - sub s9, s6, s5 - sll t3, s7, a3 - slli s11, gp, 14 - c.addi4spn a4, sp, 288 - c.nop - auipc t6, 688967 - c.srai s0, 31 - srai s10, s1, 24 - sub s9, s6, s5 - c.xor a1, a2 - nop - c.li a7, 27 - sra s1, t3, s1 - c.slli t4, 28 - andi s8, t1, -26 - xor t4, s3, t3 - c.addi s1, 6 - c.or a5, a1 - c.srli a0, 25 - sra s1, t3, s1 - c.slli t4, 28 - sub s9, s6, s5 - c.sub s1, a4 - c.li a7, 27 - xori a4, t0, 974 - nop - rem s0, a3, a2 - slt t1, a1, a4 - or s0, a2, a0 - c.xor a1, a2 - c.mv a1, s5 - c.andi a5, -1 - c.addi16sp sp, 16 - andi s8, t1, -26 - c.andi a5, -1 - andi s8, t1, -26 - auipc t6, 688967 - c.slli t4, 28 - c.srli a0, 25 - sll t3, s7, a3 - auipc t6, 688967 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - c.addi4spn a4, sp, 288 - c.srai s0, 31 - c.addi4spn a4, sp, 288 - srli s8, t6, 19 - c.addi16sp sp, 16 - xor t4, s3, t3 - slli s11, gp, 14 - sltiu s6, ra, 913 - c.lui a0, 24 - divu sp, ra, t0 - xori a4, t0, 974 - xori a4, t0, 974 - sra s1, t3, s1 - div t3, t1, t5 - c.addi s1, 6 - div t3, t1, t5 - sll t3, s7, a3 - sub s9, s6, s5 - nop - add s7, s5, a6 - srli s8, t6, 19 - slli s11, gp, 14 - c.add t1, a1 - sltiu s6, ra, 913 - and a1, t3, a6 - slli s11, gp, 14 - mulh s11, s1, s9 - c.addi4spn a4, sp, 288 - c.addi s1, 6 - c.or a5, a1 - c.or a5, a1 - mul sp, s9, s11 - ori t5, t2, 999 - div t3, t1, t5 - c.addi4spn a4, sp, 288 - c.or a5, a1 - lui zero, 195546 - ori t5, t2, 999 - c.and a0, s0 - c.or a5, a1 - xori a4, t0, 974 - c.add t1, a1 - addi a7, t2, -784 - mulhsu gp, a1, s1 - c.or a5, a1 - slti tp, t6, 301 - mul sp, s9, s11 - andi s8, t1, -26 - c.sub s1, a4 - c.or a5, a1 - c.slli t4, 28 - slt t1, a1, a4 - sltu t2, s1, t1 - sltu t2, s1, t1 - mul sp, s9, s11 - nop - slt t1, a1, a4 - slt t1, a1, a4 - mul sp, s9, s11 - sltu t2, s1, t1 - c.sub s1, a4 - mul sp, s9, s11 - sra s1, t3, s1 - srl a0, s2, a0 - c.addi16sp sp, 16 - div t3, t1, t5 - srai s10, s1, 24 - ori t5, t2, 999 - mulhsu gp, a1, s1 - ori t5, t2, 999 - srai s10, s1, 24 - or s0, a2, a0 - add s7, s5, a6 - mulhu tp, s3, a4 - xor t4, s3, t3 - and a1, t3, a6 - c.sub s1, a4 - c.sub s1, a4 - slli s11, gp, 14 - sra s1, t3, s1 - c.add t1, a1 - srl a0, s2, a0 - c.mv a1, s5 - sub s9, s6, s5 - auipc t6, 688967 - c.add t1, a1 - lui zero, 195546 - c.sub s1, a4 - div t3, t1, t5 - c.slli t4, 28 - c.or a5, a1 - c.addi4spn a4, sp, 288 - c.srai s0, 31 - srl a0, s2, a0 - c.addi16sp sp, 16 - c.xor a1, a2 - c.slli t4, 28 - srai s10, s1, 24 - sll t3, s7, a3 - divu sp, ra, t0 - c.li a7, 27 - sra s1, t3, s1 - mulh s11, s1, s9 - sll t3, s7, a3 - or s0, a2, a0 - c.slli t4, 28 - slt t1, a1, a4 - c.addi s1, 6 - or s0, a2, a0 - c.srai s0, 31 - and a1, t3, a6 - auipc t6, 688967 - lui zero, 195546 - c.xor a1, a2 - sub s9, s6, s5 - or s0, a2, a0 - slti tp, t6, 301 - mulh s11, s1, s9 - xor t4, s3, t3 - remu s5, s11, t1 - srai s10, s1, 24 - slli s11, gp, 14 - sltu t2, s1, t1 - srl a0, s2, a0 - srai s10, s1, 24 - sltu t2, s1, t1 - xori a4, t0, 974 - srl a0, s2, a0 - remu s5, s11, t1 - c.srai s0, 31 - c.xor a1, a2 - c.addi16sp sp, 16 - xor t4, s3, t3 - sltiu s6, ra, 913 - mul sp, s9, s11 - mulh s11, s1, s9 - mulhsu gp, a1, s1 - srli s8, t6, 19 - c.addi4spn a4, sp, 288 - slli s11, gp, 14 - mulhsu gp, a1, s1 - c.nop - c.slli t4, 28 - sub s9, s6, s5 - slt t1, a1, a4 - slli s11, gp, 14 - div t3, t1, t5 - mul sp, s9, s11 - c.srli a0, 25 - c.srai s0, 31 - or s0, a2, a0 - slti tp, t6, 301 - c.addi s1, 6 - srli s8, t6, 19 - and a1, t3, a6 - mul sp, s9, s11 - mulhu tp, s3, a4 - and a1, t3, a6 - c.srli a0, 25 - c.mv a1, s5 - c.and a0, s0 - div t3, t1, t5 - c.nop - sll t3, s7, a3 - add s7, s5, a6 - slti tp, t6, 301 - addi a7, t2, -784 - slt t1, a1, a4 - mulhsu gp, a1, s1 - div t3, t1, t5 - slt t1, a1, a4 - add s7, s5, a6 - c.mv a1, s5 - c.mv a1, s5 - c.addi4spn a4, sp, 288 - add s7, s5, a6 - c.addi s1, 6 - c.srai s0, 31 - c.and a0, s0 - slli s11, gp, 14 - lui zero, 195546 - c.addi4spn a4, sp, 288 - div t3, t1, t5 - mul sp, s9, s11 - c.and a0, s0 - slti tp, t6, 301 - ori t5, t2, 999 - remu s5, s11, t1 - sltu t2, s1, t1 - nop - c.andi a5, -1 - c.add t1, a1 - slt t1, a1, a4 - c.addi s1, 6 - c.addi s1, 6 - sra s1, t3, s1 - c.srai s0, 31 - c.and a0, s0 - slli s11, gp, 14 - add s7, s5, a6 - c.slli t4, 28 - auipc t6, 688967 - c.or a5, a1 - slti tp, t6, 301 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - sra s1, t3, s1 - srai s10, s1, 24 - slli s11, gp, 14 - c.andi a5, -1 - divu sp, ra, t0 - ori t5, t2, 999 - c.mv a1, s5 - add s7, s5, a6 - sll t3, s7, a3 - ori t5, t2, 999 - c.addi16sp sp, 16 - c.slli t4, 28 - c.nop - c.srai s0, 31 - c.li a7, 27 - sub s9, s6, s5 - rem s0, a3, a2 - add s7, s5, a6 - addi a7, t2, -784 - c.mv a1, s5 - c.slli t4, 28 - or s0, a2, a0 - mulh s11, s1, s9 - addi a7, t2, -784 - nop - c.add t1, a1 - c.mv a1, s5 - c.xor a1, a2 - xor t4, s3, t3 - add s7, s5, a6 - ori t5, t2, 999 - sub s9, s6, s5 - remu s5, s11, t1 - divu sp, ra, t0 - auipc t6, 688967 - ori t5, t2, 999 - srai s10, s1, 24 - and a1, t3, a6 - auipc t6, 688967 - sra s1, t3, s1 - div t3, t1, t5 - mulhsu gp, a1, s1 - sltu t2, s1, t1 - c.or a5, a1 - andi s8, t1, -26 - c.nop - c.mv a1, s5 - c.lui a0, 24 - sub s9, s6, s5 - mul sp, s9, s11 - addi a7, t2, -784 - nop - c.xor a1, a2 - srai s10, s1, 24 - c.lui a0, 24 - mulhsu gp, a1, s1 - or s0, a2, a0 - c.addi16sp sp, 16 - sub s9, s6, s5 - c.or a5, a1 - c.slli t4, 28 - ori t5, t2, 999 - srl a0, s2, a0 - divu sp, ra, t0 - c.andi a5, -1 - slti tp, t6, 301 - c.addi s1, 6 - c.add t1, a1 - and a1, t3, a6 - xori a4, t0, 974 - sltu t2, s1, t1 - srl a0, s2, a0 - srli s8, t6, 19 - c.andi a5, -1 - sra s1, t3, s1 - c.li a7, 27 - sltu t2, s1, t1 - c.addi s1, 6 - div t3, t1, t5 - slli s11, gp, 14 - remu s5, s11, t1 - slt t1, a1, a4 - c.andi a5, -1 - ori t5, t2, 999 - sltu t2, s1, t1 - c.nop - auipc t6, 688967 - andi s8, t1, -26 - div t3, t1, t5 - mulhu tp, s3, a4 - xori a4, t0, 974 - addi a7, t2, -784 - sll t3, s7, a3 - c.addi16sp sp, 16 - div t3, t1, t5 - c.xor a1, a2 - andi s8, t1, -26 - c.addi s1, 6 - c.addi s1, 6 - c.nop - xori a4, t0, 974 - remu s5, s11, t1 - c.and a0, s0 - c.slli t4, 28 - c.srli a0, 25 - srai s10, s1, 24 - c.mv a1, s5 - andi s8, t1, -26 - slti tp, t6, 301 - sltu t2, s1, t1 - mul sp, s9, s11 - c.li a7, 27 - srl a0, s2, a0 - c.or a5, a1 - slti tp, t6, 301 - mulhu tp, s3, a4 - mulhu tp, s3, a4 - c.li a7, 27 - sra s1, t3, s1 - c.srli a0, 25 - sll t3, s7, a3 - c.lui a0, 24 - slti tp, t6, 301 - or s0, a2, a0 - slli s11, gp, 14 - addi a7, t2, -784 - auipc t6, 688967 - add s7, s5, a6 - c.addi16sp sp, 16 - c.lui a0, 24 - c.andi a5, -1 - rem s0, a3, a2 - div t3, t1, t5 - and a1, t3, a6 - rem s0, a3, a2 - c.li a7, 27 - srl a0, s2, a0 - mul sp, s9, s11 - c.add t1, a1 - sra s1, t3, s1 - c.mv a1, s5 - rem s0, a3, a2 - srli s8, t6, 19 - c.addi4spn a4, sp, 288 - c.li a7, 27 - slti tp, t6, 301 - sub s9, s6, s5 - c.lui a0, 24 - c.addi4spn a4, sp, 288 - div t3, t1, t5 - slt t1, a1, a4 - rem s0, a3, a2 - c.xor a1, a2 - srli s8, t6, 19 - xori a4, t0, 974 - mulhsu gp, a1, s1 - mulhsu gp, a1, s1 - c.add t1, a1 - div t3, t1, t5 - lui zero, 195546 - c.sub s1, a4 - sub s9, s6, s5 - mulh s11, s1, s9 - slt t1, a1, a4 - remu s5, s11, t1 - slli s11, gp, 14 - rem s0, a3, a2 - divu sp, ra, t0 - xor t4, s3, t3 - sltiu s6, ra, 913 - add s7, s5, a6 - mulhsu gp, a1, s1 - rem s0, a3, a2 - rem s0, a3, a2 - add s7, s5, a6 - or s0, a2, a0 - c.andi a5, -1 - sltiu s6, ra, 913 - c.sub s1, a4 - c.and a0, s0 - c.or a5, a1 - c.add t1, a1 - c.addi4spn a4, sp, 288 - c.add t1, a1 - sub s9, s6, s5 - c.slli t4, 28 - c.srli a0, 25 - addi a7, t2, -784 - lui zero, 195546 - c.or a5, a1 - mulh s11, s1, s9 - c.srli a0, 25 - srli s8, t6, 19 - c.xor a1, a2 - xor t4, s3, t3 - c.mv a1, s5 - sltiu s6, ra, 913 - sll t3, s7, a3 - srli s8, t6, 19 - c.srai s0, 31 - c.or a5, a1 - c.xor a1, a2 - mulhu tp, s3, a4 - c.xor a1, a2 - mulhu tp, s3, a4 - nop - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - c.and a0, s0 - addi a7, t2, -784 - nop - nop - remu s5, s11, t1 - sra s1, t3, s1 - mulhu tp, s3, a4 - c.addi s1, 6 - srl a0, s2, a0 - xor t4, s3, t3 - xor t4, s3, t3 - c.addi4spn a4, sp, 288 - or s0, a2, a0 - xori a4, t0, 974 - mulhsu gp, a1, s1 - c.andi a5, -1 - remu s5, s11, t1 - slli s11, gp, 14 - sub s9, s6, s5 - sub s9, s6, s5 - mulhsu gp, a1, s1 - divu sp, ra, t0 - c.andi a5, -1 - slt t1, a1, a4 - c.andi a5, -1 - srai s10, s1, 24 - ori t5, t2, 999 - c.li a7, 27 - c.lui a0, 24 - c.srai s0, 31 - xor t4, s3, t3 - c.srai s0, 31 - nop - c.addi16sp sp, 16 - or s0, a2, a0 - c.srai s0, 31 - add s7, s5, a6 - sll t3, s7, a3 - srl a0, s2, a0 - slli s11, gp, 14 - c.and a0, s0 - sub s9, s6, s5 - c.slli t4, 28 - slli s11, gp, 14 - add s7, s5, a6 - slli s11, gp, 14 - srli s8, t6, 19 - c.li a7, 27 - c.or a5, a1 - divu sp, ra, t0 - c.srli a0, 25 - slt t1, a1, a4 - mulh s11, s1, s9 - sub s9, s6, s5 - c.add t1, a1 - mulhu tp, s3, a4 - and a1, t3, a6 - c.xor a1, a2 - andi s8, t1, -26 - lui zero, 195546 - c.add t1, a1 - xor t4, s3, t3 - divu sp, ra, t0 - nop - c.or a5, a1 - and a1, t3, a6 - slti tp, t6, 301 - sll t3, s7, a3 - sltu t2, s1, t1 - c.andi a5, -1 - srl a0, s2, a0 - c.mv a1, s5 - slli s11, gp, 14 - c.addi16sp sp, 16 - c.mv a1, s5 - rem s0, a3, a2 - c.addi4spn a4, sp, 288 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - nop - mulh s11, s1, s9 - c.mv a1, s5 - c.or a5, a1 - c.or a5, a1 - xori a4, t0, 974 - c.add t1, a1 - c.addi s1, 6 - c.slli t4, 28 - srli s8, t6, 19 - c.xor a1, a2 - xori a4, t0, 974 - c.slli t4, 28 - c.addi s1, 6 - mulh s11, s1, s9 - srli s8, t6, 19 - slli s11, gp, 14 - c.andi a5, -1 - divu sp, ra, t0 - sltiu s6, ra, 913 - c.li a7, 27 - c.addi s1, 6 - c.nop - c.nop - c.srai s0, 31 - auipc t6, 688967 - xor t4, s3, t3 - c.xor a1, a2 - xor t4, s3, t3 - srli s8, t6, 19 - or s0, a2, a0 - sltiu s6, ra, 913 - c.addi4spn a4, sp, 288 - xor t4, s3, t3 - c.xor a1, a2 - c.add t1, a1 - xor t4, s3, t3 - remu s5, s11, t1 - c.andi a5, -1 - lui zero, 195546 - rem s0, a3, a2 - c.xor a1, a2 - c.or a5, a1 - sll t3, s7, a3 - sll t3, s7, a3 - lui zero, 195546 - sub s9, s6, s5 - slti tp, t6, 301 - and a1, t3, a6 - c.srai s0, 31 - c.mv a1, s5 - add s7, s5, a6 - addi a7, t2, -784 - nop - add s7, s5, a6 - lui zero, 195546 - sub s9, s6, s5 - c.addi4spn a4, sp, 288 - addi a7, t2, -784 - c.srli a0, 25 - xor t4, s3, t3 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - c.lui a0, 24 - sub s9, s6, s5 - rem s0, a3, a2 - mul sp, s9, s11 - sltiu s6, ra, 913 - slt t1, a1, a4 - auipc t6, 688967 - c.andi a5, -1 - c.andi a5, -1 - c.addi s1, 6 - div t3, t1, t5 - mulh s11, s1, s9 - mulhsu gp, a1, s1 - lui zero, 195546 - c.srai s0, 31 - auipc t6, 688967 - c.li a7, 27 - c.sub s1, a4 - add s7, s5, a6 - c.slli t4, 28 - nop - xori a4, t0, 974 - andi s8, t1, -26 - addi a7, t2, -784 - c.sub s1, a4 - c.addi4spn a4, sp, 288 - rem s0, a3, a2 - addi a7, t2, -784 - sltiu s6, ra, 913 - sra s1, t3, s1 - c.srai s0, 31 - c.mv a1, s5 - slti tp, t6, 301 - c.or a5, a1 - rem s0, a3, a2 - c.srli a0, 25 - c.slli t4, 28 - srli s8, t6, 19 - xori a4, t0, 974 - addi a7, t2, -784 - sra s1, t3, s1 - c.and a0, s0 - c.addi4spn a4, sp, 288 - add s7, s5, a6 - mulh s11, s1, s9 - xor t4, s3, t3 - c.and a0, s0 - srli s8, t6, 19 - mulhu tp, s3, a4 - lui zero, 195546 - ori t5, t2, 999 - auipc t6, 688967 - rem s0, a3, a2 - xori a4, t0, 974 - srli s8, t6, 19 - c.addi16sp sp, 16 - addi a7, t2, -784 - sltu t2, s1, t1 - c.nop - mulhu tp, s3, a4 - sub s9, s6, s5 - c.mv a1, s5 - c.addi s1, 6 - andi s8, t1, -26 - mul sp, s9, s11 - c.addi16sp sp, 16 - sltu t2, s1, t1 - mulhsu gp, a1, s1 - slti tp, t6, 301 - nop - c.or a5, a1 - sub s9, s6, s5 - c.li a7, 27 - lui zero, 195546 - c.srai s0, 31 - xori a4, t0, 974 - srl a0, s2, a0 - c.andi a5, -1 - nop - lui zero, 195546 - sll t3, s7, a3 - rem s0, a3, a2 - c.sub s1, a4 - c.srli a0, 25 - srai s10, s1, 24 - slti tp, t6, 301 - srai s10, s1, 24 - add s7, s5, a6 - c.slli t4, 28 - c.li a7, 27 - addi a7, t2, -784 - mulhsu gp, a1, s1 - andi s8, t1, -26 - sltu t2, s1, t1 - auipc t6, 688967 - sltiu s6, ra, 913 - c.and a0, s0 - c.and a0, s0 - slti tp, t6, 301 - c.andi a5, -1 - srli s8, t6, 19 - slti tp, t6, 301 - mulhsu gp, a1, s1 - slti tp, t6, 301 - add s7, s5, a6 - sll t3, s7, a3 - c.li a7, 27 - xor t4, s3, t3 - xor t4, s3, t3 - c.nop - srl a0, s2, a0 - slli s11, gp, 14 - div t3, t1, t5 - srli s8, t6, 19 - and a1, t3, a6 - lui zero, 195546 - andi s8, t1, -26 - mulhu tp, s3, a4 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - sll t3, s7, a3 - lui zero, 195546 - mulhu tp, s3, a4 - andi s8, t1, -26 - divu sp, ra, t0 - c.xor a1, a2 - c.sub s1, a4 - mulhsu gp, a1, s1 - addi a7, t2, -784 - remu s5, s11, t1 - mulh s11, s1, s9 - divu sp, ra, t0 - divu sp, ra, t0 - remu s5, s11, t1 - c.srli a0, 25 - nop - c.srai s0, 31 - xori a4, t0, 974 - srai s10, s1, 24 - nop - sltu t2, s1, t1 - xori a4, t0, 974 - mulhu tp, s3, a4 - c.srai s0, 31 - srai s10, s1, 24 - c.srli a0, 25 - andi s8, t1, -26 - slti tp, t6, 301 - c.srai s0, 31 - c.add t1, a1 - c.addi4spn a4, sp, 288 - c.xor a1, a2 - c.li a7, 27 - sub s9, s6, s5 - sra s1, t3, s1 - c.xor a1, a2 - mul sp, s9, s11 - sltu t2, s1, t1 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - add s7, s5, a6 - lui zero, 195546 - c.add t1, a1 - sub s9, s6, s5 - slt t1, a1, a4 - c.addi16sp sp, 16 - slli s11, gp, 14 - and a1, t3, a6 - sll t3, s7, a3 - or s0, a2, a0 - c.lui a0, 24 - c.addi s1, 6 - mulh s11, s1, s9 - auipc t6, 688967 - andi s8, t1, -26 - nop - rem s0, a3, a2 - srai s10, s1, 24 - c.srli a0, 25 - slt t1, a1, a4 - c.and a0, s0 - srl a0, s2, a0 - c.or a5, a1 - srl a0, s2, a0 - mulhu tp, s3, a4 - sub s9, s6, s5 - sra s1, t3, s1 - rem s0, a3, a2 - c.or a5, a1 - and a1, t3, a6 - mulhsu gp, a1, s1 - div t3, t1, t5 - auipc t6, 688967 - c.and a0, s0 - c.sub s1, a4 - nop - c.slli t4, 28 - add s7, s5, a6 - c.srli a0, 25 - c.lui a0, 24 - c.andi a5, -1 - srai s10, s1, 24 - srli s8, t6, 19 - ori t5, t2, 999 - auipc t6, 688967 - c.addi16sp sp, 16 - addi a7, t2, -784 - srl a0, s2, a0 - c.li a7, 27 - divu sp, ra, t0 - or s0, a2, a0 - and a1, t3, a6 - c.sub s1, a4 - lui zero, 195546 - srai s10, s1, 24 - auipc t6, 688967 - mulhu tp, s3, a4 - or s0, a2, a0 - slli s11, gp, 14 - add s7, s5, a6 - xor t4, s3, t3 - divu sp, ra, t0 - srli s8, t6, 19 - sub s9, s6, s5 - mulhsu gp, a1, s1 - c.sub s1, a4 - slt t1, a1, a4 - c.nop - xori a4, t0, 974 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - xor t4, s3, t3 - slli s11, gp, 14 - srai s10, s1, 24 - sll t3, s7, a3 - or s0, a2, a0 - mul sp, s9, s11 - c.addi s1, 6 - div t3, t1, t5 - c.li a7, 27 - c.srai s0, 31 - addi a7, t2, -784 - andi s8, t1, -26 - c.slli t4, 28 - mulh s11, s1, s9 - mulh s11, s1, s9 - and a1, t3, a6 - srli s8, t6, 19 - c.addi4spn a4, sp, 288 - nop - and a1, t3, a6 - c.slli t4, 28 - divu sp, ra, t0 - c.mv a1, s5 - slt t1, a1, a4 - c.and a0, s0 - c.slli t4, 28 - srai s10, s1, 24 - c.srli a0, 25 - c.addi4spn a4, sp, 288 - xor t4, s3, t3 - xor t4, s3, t3 - c.mv a1, s5 - sltu t2, s1, t1 - c.slli t4, 28 - remu s5, s11, t1 - rem s0, a3, a2 - xori a4, t0, 974 - ori t5, t2, 999 - xor t4, s3, t3 - auipc t6, 688967 - c.addi4spn a4, sp, 288 - or s0, a2, a0 - lui zero, 195546 - mulh s11, s1, s9 - xori a4, t0, 974 - c.srai s0, 31 - c.mv a1, s5 - mulhu tp, s3, a4 - ori t5, t2, 999 - ori t5, t2, 999 - c.addi4spn a4, sp, 288 - and a1, t3, a6 - divu sp, ra, t0 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - c.li a7, 27 - c.srli a0, 25 - divu sp, ra, t0 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - auipc t6, 688967 - slli s11, gp, 14 - and a1, t3, a6 - add s7, s5, a6 - c.add t1, a1 - srli s8, t6, 19 - mulhu tp, s3, a4 - c.sub s1, a4 - xori a4, t0, 974 - c.mv a1, s5 - c.addi s1, 6 - c.srai s0, 31 - srli s8, t6, 19 - remu s5, s11, t1 - c.andi a5, -1 - sltiu s6, ra, 913 - sll t3, s7, a3 - srai s10, s1, 24 - c.andi a5, -1 - srli s8, t6, 19 - divu sp, ra, t0 - addi a7, t2, -784 - srli s8, t6, 19 - srl a0, s2, a0 - remu s5, s11, t1 - sltu t2, s1, t1 - or s0, a2, a0 - andi s8, t1, -26 - and a1, t3, a6 - sltiu s6, ra, 913 - c.mv a1, s5 - auipc t6, 688967 - mulh s11, s1, s9 - c.nop - c.srai s0, 31 - c.addi4spn a4, sp, 288 - c.slli t4, 28 - lui zero, 195546 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - c.nop - c.andi a5, -1 - c.and a0, s0 - sltiu s6, ra, 913 - srli s8, t6, 19 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - srai s10, s1, 24 - sll t3, s7, a3 - add s7, s5, a6 - srl a0, s2, a0 - c.xor a1, a2 - addi a7, t2, -784 - rem s0, a3, a2 - mulhu tp, s3, a4 - slt t1, a1, a4 - c.srai s0, 31 - c.and a0, s0 - mulhu tp, s3, a4 - xor t4, s3, t3 - c.andi a5, -1 - lui zero, 195546 - andi s8, t1, -26 - slti tp, t6, 301 - sra s1, t3, s1 - slli s11, gp, 14 - divu sp, ra, t0 - c.mv a1, s5 - mulhu tp, s3, a4 - c.addi16sp sp, 16 - c.addi s1, 6 - c.sub s1, a4 - c.srli a0, 25 - add s7, s5, a6 - remu s5, s11, t1 - srl a0, s2, a0 - c.srli a0, 25 - sub s9, s6, s5 - c.xor a1, a2 - lui zero, 195546 - mulhu tp, s3, a4 - sltu t2, s1, t1 - auipc t6, 688967 - c.or a5, a1 - c.add t1, a1 - or s0, a2, a0 - mulhsu gp, a1, s1 - sltiu s6, ra, 913 - lui zero, 195546 - c.nop - c.xor a1, a2 - slt t1, a1, a4 - c.add t1, a1 - auipc t6, 688967 - c.srli a0, 25 - c.xor a1, a2 - xor t4, s3, t3 - div t3, t1, t5 - auipc t6, 688967 - c.srli a0, 25 - div t3, t1, t5 - srai s10, s1, 24 - srl a0, s2, a0 - c.srai s0, 31 - srli s8, t6, 19 - rem s0, a3, a2 - sra s1, t3, s1 - and a1, t3, a6 - mulhu tp, s3, a4 - c.srli a0, 25 - mul sp, s9, s11 - xori a4, t0, 974 - sra s1, t3, s1 - c.addi s1, 6 - sll t3, s7, a3 - auipc t6, 688967 - div t3, t1, t5 - add s7, s5, a6 - sll t3, s7, a3 - c.xor a1, a2 - xori a4, t0, 974 - srli s8, t6, 19 - c.li a7, 27 - nop - mulhsu gp, a1, s1 - c.addi4spn a4, sp, 288 - c.xor a1, a2 - slti tp, t6, 301 - rem s0, a3, a2 - c.andi a5, -1 - mulhsu gp, a1, s1 - div t3, t1, t5 - c.addi s1, 6 - remu s5, s11, t1 - c.srai s0, 31 - c.andi a5, -1 - li s3, 0xea294de #start riscv_int_numeric_corner_stream_14 - li s7, 0x80000000 - li s1, 0xffffffff - li tp, 0x80000000 - li s8, 0x80000000 - li s11, 0xef2ff383 - li a6, 0xffffffff - li a5, 0x80000000 - li gp, 0x80000000 - li a1, 0x0 - lui tp, 195546 - addi a6, s7, 999 - addi a6, s7, 999 - addi a6, s7, 999 - nop - nop - nop - mul tp, a6, tp - div gp, s8, gp - div gp, s8, gp - nop - nop - add s3, s11, a6 - lui tp, 195546 - auipc s11, 688967 #end riscv_int_numeric_corner_stream_14 - srai s10, s1, 24 - srai s10, s1, 24 - addi a7, t2, -784 - c.lui a0, 24 - mulhsu gp, a1, s1 - srai s10, s1, 24 - srli s8, t6, 19 - c.li a7, 27 - c.srai s0, 31 - srl a0, s2, a0 - rem s0, a3, a2 - remu s5, s11, t1 - addi a7, t2, -784 - srai s10, s1, 24 - slti tp, t6, 301 - add s7, s5, a6 - c.and a0, s0 - mul sp, s9, s11 - slli s11, gp, 14 - and a1, t3, a6 - slti tp, t6, 301 - c.and a0, s0 - c.mv a1, s5 - add s7, s5, a6 - slt t1, a1, a4 - remu s5, s11, t1 - divu sp, ra, t0 - slli s11, gp, 14 - c.lui a0, 24 - andi s8, t1, -26 - c.addi s1, 6 - srli s8, t6, 19 - and a1, t3, a6 - lui zero, 195546 - c.add t1, a1 - sll t3, s7, a3 - c.slli t4, 28 - xori a4, t0, 974 - c.mv a1, s5 - c.andi a5, -1 - or s0, a2, a0 - slt t1, a1, a4 - slt t1, a1, a4 - sra s1, t3, s1 - srl a0, s2, a0 - add s7, s5, a6 - c.nop - c.addi16sp sp, 16 - sltiu s6, ra, 913 - ori t5, t2, 999 - c.sub s1, a4 - mul sp, s9, s11 - mulhsu gp, a1, s1 - srli s8, t6, 19 - c.srai s0, 31 - or s0, a2, a0 - c.mv a1, s5 - xor t4, s3, t3 - c.nop - srl a0, s2, a0 - addi a7, t2, -784 - auipc t6, 688967 - sltiu s6, ra, 913 - c.or a5, a1 - addi a7, t2, -784 - nop - c.lui a0, 24 - c.lui a0, 24 - c.add t1, a1 - divu sp, ra, t0 - ori t5, t2, 999 - c.nop - c.slli t4, 28 - remu s5, s11, t1 - sltu t2, s1, t1 - rem s0, a3, a2 - c.add t1, a1 - mulhu tp, s3, a4 - sub s9, s6, s5 - srai s10, s1, 24 - srl a0, s2, a0 - sub s9, s6, s5 - c.slli t4, 28 - c.srai s0, 31 - srl a0, s2, a0 - c.or a5, a1 - c.sub s1, a4 - c.li a7, 27 - div t3, t1, t5 - srli s8, t6, 19 - c.addi16sp sp, 16 - lui zero, 195546 - div t3, t1, t5 - c.xor a1, a2 - c.addi16sp sp, 16 - mulhsu gp, a1, s1 - c.or a5, a1 - slti tp, t6, 301 - andi s8, t1, -26 - sra s1, t3, s1 - mul sp, s9, s11 - sra s1, t3, s1 - andi s8, t1, -26 - slti tp, t6, 301 - c.xor a1, a2 - or s0, a2, a0 - c.lui a0, 24 - mulh s11, s1, s9 - nop - c.mv a1, s5 - or s0, a2, a0 - add s7, s5, a6 - nop - srai s10, s1, 24 - mulhu tp, s3, a4 - sra s1, t3, s1 - c.slli t4, 28 - andi s8, t1, -26 - li sp, 0x65e8c87c #start riscv_int_numeric_corner_stream_24 - li s8, 0x0 - li s7, 0x0 - li s11, 0xffffffff - li s0, 0x80000000 - li t1, 0xf2fed3a2 - li gp, 0x933359ef - li t3, 0x80000000 - li s6, 0x80000000 - li a4, 0x31bba2df - sub sp, s8, a4 - remu s7, a4, s0 - rem s8, a4, s0 - lui s0, 195546 - addi s0, s7, 999 - lui s0, 195546 - nop - div gp, s0, a4 - mul gp, s7, s8 - add gp, a4, s8 - sub sp, s8, a4 - rem s8, a4, s0 - remu s7, a4, s0 - add gp, a4, s8 - rem s8, a4, s0 - addi s0, s7, 999 - nop #end riscv_int_numeric_corner_stream_24 - mul sp, s9, s11 - c.mv a1, s5 - c.addi s1, 6 - and a1, t3, a6 - addi a7, t2, -784 - c.li a7, 27 - srai s10, s1, 24 - and a1, t3, a6 - c.add t1, a1 - c.srai s0, 31 - srli s8, t6, 19 - c.andi a5, -1 - c.addi s1, 6 - c.andi a5, -1 - c.addi16sp sp, 16 - mulhu tp, s3, a4 - lui zero, 195546 - sltiu s6, ra, 913 - c.li a7, 27 - sltiu s6, ra, 913 - divu sp, ra, t0 - c.addi s1, 6 - sll t3, s7, a3 - c.addi s1, 6 - c.addi s1, 6 - c.xor a1, a2 - c.srai s0, 31 - xor t4, s3, t3 - addi a7, t2, -784 - xor t4, s3, t3 - sra s1, t3, s1 - nop - mulhsu gp, a1, s1 - c.sub s1, a4 - c.addi s1, 6 - mulhsu gp, a1, s1 - srai s10, s1, 24 - srli s8, t6, 19 - c.xor a1, a2 - c.li a7, 27 - addi a7, t2, -784 - xor t4, s3, t3 - slli s11, gp, 14 - mulhsu gp, a1, s1 - srli s8, t6, 19 - auipc t6, 688967 - add s7, s5, a6 - sra s1, t3, s1 - mulh s11, s1, s9 - add s7, s5, a6 - c.nop - srl a0, s2, a0 - divu sp, ra, t0 - c.slli t4, 28 - c.or a5, a1 - andi s8, t1, -26 - sll t3, s7, a3 - xor t4, s3, t3 - remu s5, s11, t1 - srli s8, t6, 19 - mulhu tp, s3, a4 - c.andi a5, -1 - c.xor a1, a2 - remu s5, s11, t1 - mulhu tp, s3, a4 - add s7, s5, a6 - sll t3, s7, a3 - div t3, t1, t5 - slti tp, t6, 301 - ori t5, t2, 999 - sra s1, t3, s1 - c.andi a5, -1 - c.sub s1, a4 - nop - ori t5, t2, 999 - c.and a0, s0 - sll t3, s7, a3 - c.li a7, 27 - andi s8, t1, -26 - c.and a0, s0 - c.lui a0, 24 - slt t1, a1, a4 - sub s9, s6, s5 - mulhu tp, s3, a4 - srl a0, s2, a0 - srl a0, s2, a0 - slti tp, t6, 301 - rem s0, a3, a2 - divu sp, ra, t0 - c.srai s0, 31 - addi a7, t2, -784 - lui zero, 195546 - c.andi a5, -1 - c.sub s1, a4 - c.nop - lui zero, 195546 - andi s8, t1, -26 - add s7, s5, a6 - or s0, a2, a0 - xori a4, t0, 974 - c.addi16sp sp, 16 - mulhsu gp, a1, s1 - c.andi a5, -1 - or s0, a2, a0 - srai s10, s1, 24 - or s0, a2, a0 - c.addi4spn a4, sp, 288 - srli s8, t6, 19 - mulhsu gp, a1, s1 - div t3, t1, t5 - sub s9, s6, s5 - c.slli t4, 28 - add s7, s5, a6 - srli s8, t6, 19 - nop - andi s8, t1, -26 - c.srli a0, 25 - div t3, t1, t5 - mulh s11, s1, s9 - c.and a0, s0 - slt t1, a1, a4 - slt t1, a1, a4 - add s7, s5, a6 - andi s8, t1, -26 - slti tp, t6, 301 - srl a0, s2, a0 - mul sp, s9, s11 - ori t5, t2, 999 - divu sp, ra, t0 - rem s0, a3, a2 - slti tp, t6, 301 - c.and a0, s0 - c.lui a0, 24 - slli s11, gp, 14 - ori t5, t2, 999 - slt t1, a1, a4 - ori t5, t2, 999 - mulhu tp, s3, a4 - srl a0, s2, a0 - c.andi a5, -1 - c.or a5, a1 - and a1, t3, a6 - add s7, s5, a6 - c.add t1, a1 - sll t3, s7, a3 - c.and a0, s0 - c.slli t4, 28 - c.sub s1, a4 - c.add t1, a1 - c.addi16sp sp, 16 - div t3, t1, t5 - mulh s11, s1, s9 - srli s8, t6, 19 - add s7, s5, a6 - andi s8, t1, -26 - lui zero, 195546 - ori t5, t2, 999 - srli s8, t6, 19 - c.add t1, a1 - xori a4, t0, 974 - remu s5, s11, t1 - c.and a0, s0 - xori a4, t0, 974 - srli s8, t6, 19 - add s7, s5, a6 - divu sp, ra, t0 - and a1, t3, a6 - srai s10, s1, 24 - xori a4, t0, 974 - mul sp, s9, s11 - lui zero, 195546 - slli s11, gp, 14 - srli s8, t6, 19 - andi s8, t1, -26 - mulhsu gp, a1, s1 - divu sp, ra, t0 - slli s11, gp, 14 - c.slli t4, 28 - mulh s11, s1, s9 - andi s8, t1, -26 - srai s10, s1, 24 - addi a7, t2, -784 - add s7, s5, a6 - c.addi16sp sp, 16 - srli s8, t6, 19 - xor t4, s3, t3 - c.srai s0, 31 - sra s1, t3, s1 - slli s11, gp, 14 - ori t5, t2, 999 - c.sub s1, a4 - remu s5, s11, t1 - c.lui a0, 24 - nop - slli s11, gp, 14 - sltu t2, s1, t1 - c.slli t4, 28 - srl a0, s2, a0 - c.srli a0, 25 - mulh s11, s1, s9 - sll t3, s7, a3 - sltu t2, s1, t1 - sll t3, s7, a3 - c.and a0, s0 - c.addi s1, 6 - c.lui a0, 24 - mulh s11, s1, s9 - c.srli a0, 25 - mulhsu gp, a1, s1 - sll t3, s7, a3 - c.srli a0, 25 - srl a0, s2, a0 - slti tp, t6, 301 - add s7, s5, a6 - mulhu tp, s3, a4 - c.nop - xori a4, t0, 974 - c.srai s0, 31 - mul sp, s9, s11 - nop - c.nop - c.li a7, 27 - nop - c.mv a1, s5 - c.xor a1, a2 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - c.addi s1, 6 - srli s8, t6, 19 - c.addi16sp sp, 16 - nop - div t3, t1, t5 - c.or a5, a1 - srai s10, s1, 24 - mul sp, s9, s11 - nop - div t3, t1, t5 - c.xor a1, a2 - srli s8, t6, 19 - remu s5, s11, t1 - sub s9, s6, s5 - c.slli t4, 28 - c.li a7, 27 - srli s8, t6, 19 - c.or a5, a1 - lui zero, 195546 - c.nop - or s0, a2, a0 - c.nop - c.li a7, 27 - c.mv a1, s5 - mulhsu gp, a1, s1 - and a1, t3, a6 - c.addi16sp sp, 16 - slt t1, a1, a4 - div t3, t1, t5 - sra s1, t3, s1 - c.lui a0, 24 - c.li a7, 27 - mul sp, s9, s11 - add s7, s5, a6 - c.nop - add s7, s5, a6 - auipc t6, 688967 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - rem s0, a3, a2 - c.and a0, s0 - sltiu s6, ra, 913 - c.add t1, a1 - mul sp, s9, s11 - xori a4, t0, 974 - c.lui a0, 24 - sll t3, s7, a3 - divu sp, ra, t0 - add s7, s5, a6 - c.lui a0, 24 - slti tp, t6, 301 - mulhsu gp, a1, s1 - rem s0, a3, a2 - c.li a7, 27 - addi a7, t2, -784 - xori a4, t0, 974 - c.andi a5, -1 - srli s8, t6, 19 - srli s8, t6, 19 - c.li a7, 27 - c.addi s1, 6 - divu sp, ra, t0 - c.addi s1, 6 - srl a0, s2, a0 - nop - sll t3, s7, a3 - c.mv a1, s5 - c.addi16sp sp, 16 - mulhu tp, s3, a4 - c.xor a1, a2 - c.addi16sp sp, 16 - add s7, s5, a6 - xor t4, s3, t3 - c.xor a1, a2 - c.add t1, a1 - mulh s11, s1, s9 - sltiu s6, ra, 913 - c.lui a0, 24 - c.xor a1, a2 - div t3, t1, t5 - auipc t6, 688967 - sltiu s6, ra, 913 - lui zero, 195546 - c.lui a0, 24 - c.nop - sub s9, s6, s5 - sltiu s6, ra, 913 - remu s5, s11, t1 - nop - sub s9, s6, s5 - mul sp, s9, s11 - c.slli t4, 28 - slti tp, t6, 301 - slti tp, t6, 301 - xori a4, t0, 974 - sub s9, s6, s5 - sll t3, s7, a3 - c.sub s1, a4 - divu sp, ra, t0 - c.add t1, a1 - mul sp, s9, s11 - div t3, t1, t5 - remu s5, s11, t1 - sltu t2, s1, t1 - ori t5, t2, 999 - srai s10, s1, 24 - ori t5, t2, 999 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - slti tp, t6, 301 - divu sp, ra, t0 - c.andi a5, -1 - c.lui a0, 24 - srli s8, t6, 19 - c.addi s1, 6 - c.xor a1, a2 - sra s1, t3, s1 - c.lui a0, 24 - andi s8, t1, -26 - slli s11, gp, 14 - srli s8, t6, 19 - srli s8, t6, 19 - and a1, t3, a6 - c.xor a1, a2 - slli s11, gp, 14 - and a1, t3, a6 - sltu t2, s1, t1 - srl a0, s2, a0 - slt t1, a1, a4 - c.xor a1, a2 - ori t5, t2, 999 - slti tp, t6, 301 - xori a4, t0, 974 - addi a7, t2, -784 - c.or a5, a1 - mul sp, s9, s11 - slt t1, a1, a4 - srl a0, s2, a0 - mul sp, s9, s11 - c.addi s1, 6 - srai s10, s1, 24 - c.addi4spn a4, sp, 288 - c.and a0, s0 - li s1, 0xffffffff #start riscv_int_numeric_corner_stream_3 - li s0, 0xffffffff - li a1, 0x5e48d745 - li a6, 0xffffffff - li t3, 0xffffffff - li tp, 0x80000000 - li t5, 0xffffffff - li t4, 0x0 - li s6, 0x0 - li s7, 0xffffffff - lui tp, 195546 - add s1, t5, a6 - sub a1, t3, tp - nop - nop - auipc t4, 688967 - remu s7, a1, s0 - remu s7, a1, s0 - auipc t4, 688967 - nop - div s7, a6, s6 - auipc t4, 688967 - auipc t4, 688967 - sub a1, t3, tp - nop - div s7, a6, s6 - add s1, t5, a6 - mulh s7, t4, t4 - auipc t4, 688967 - nop - auipc t4, 688967 - nop - addi tp, s6, 999 - sub a1, t3, tp - remu s7, a1, s0 - nop - mulhu tp, a1, s1 #end riscv_int_numeric_corner_stream_3 - c.mv a1, s5 - add s7, s5, a6 - sltiu s6, ra, 913 - c.add t1, a1 - mulh s11, s1, s9 - add s7, s5, a6 - c.andi a5, -1 - xor t4, s3, t3 - div t3, t1, t5 - srli s8, t6, 19 - or s0, a2, a0 - c.xor a1, a2 - c.addi4spn a4, sp, 288 - c.mv a1, s5 - c.addi s1, 6 - c.addi s1, 6 - srai s10, s1, 24 - c.sub s1, a4 - c.nop - sltiu s6, ra, 913 - srai s10, s1, 24 - c.lui a0, 24 - c.addi16sp sp, 16 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - c.andi a5, -1 - c.xor a1, a2 - c.and a0, s0 - li a6, 0x0 #start riscv_int_numeric_corner_stream_10 - li ra, 0x8ff08a33 - li s2, 0x0 - li s5, 0xffffffff - li a0, 0x44530758 - li s9, 0xffffffff - li t2, 0x0 - li s3, 0x0 - li a7, 0x4391f359 - li sp, 0x0 - rem a0, a6, a0 - nop - nop - sub a6, sp, t2 - lui ra, 195546 - nop - nop - nop - nop - mul t2, s2, a0 - mulhsu a0, a6, a7 - add s9, sp, a7 - mulh s9, t2, s5 - mulhu s9, t2, ra - nop #end riscv_int_numeric_corner_stream_10 - c.srai s0, 31 - or s0, a2, a0 - srl a0, s2, a0 - c.mv a1, s5 - c.and a0, s0 - andi s8, t1, -26 - c.nop - c.sub s1, a4 - srai s10, s1, 24 - c.andi a5, -1 - add s7, s5, a6 - c.li a7, 27 - andi s8, t1, -26 - mulhu tp, s3, a4 - div t3, t1, t5 - c.addi4spn a4, sp, 288 - li t6, 0x0 #start riscv_int_numeric_corner_stream_4 - li tp, 0x5e6c1d6f - li s0, 0xdde826d1 - li a6, 0x80000000 - li ra, 0xadbbc3fe - li s7, 0xffffffff - li s11, 0xffffffff - li a4, 0x24719b7e - li s9, 0x4cd82e1b - li t4, 0x0 - rem s7, t4, s0 - lui tp, 195546 - add ra, a6, s9 - mulhsu a4, s9, a6 - nop - auipc t6, 688967 - mulhu tp, s11, ra - sub t4, a6, tp - add ra, a6, s9 - rem s7, t4, s0 - mulhsu a4, s9, a6 - mulh s7, s7, t4 - mul t4, a6, a6 - nop - addi a6, s7, 999 - divu s0, s0, t4 - divu s0, s0, t4 - lui tp, 195546 #end riscv_int_numeric_corner_stream_4 - remu s5, s11, t1 - slli s11, gp, 14 - c.srai s0, 31 - c.add t1, a1 - addi a7, t2, -784 - remu s5, s11, t1 - sub s9, s6, s5 - slt t1, a1, a4 - c.or a5, a1 - mul sp, s9, s11 - c.srai s0, 31 - sltu t2, s1, t1 - slt t1, a1, a4 - or s0, a2, a0 - sll t3, s7, a3 - rem s0, a3, a2 - c.lui a0, 24 - div t3, t1, t5 - c.lui a0, 24 - slti tp, t6, 301 - c.xor a1, a2 - srli s8, t6, 19 - sltiu s6, ra, 913 - mulhsu gp, a1, s1 - srai s10, s1, 24 - rem s0, a3, a2 - mulhsu gp, a1, s1 - add s7, s5, a6 - mulhsu gp, a1, s1 - sltiu s6, ra, 913 - addi a7, t2, -784 - sll t3, s7, a3 - slt t1, a1, a4 - divu sp, ra, t0 - mulh s11, s1, s9 - sltiu s6, ra, 913 - sltu t2, s1, t1 - xor t4, s3, t3 - xor t4, s3, t3 - rem s0, a3, a2 - slli s11, gp, 14 - c.or a5, a1 - rem s0, a3, a2 - div t3, t1, t5 - remu s5, s11, t1 - c.srli a0, 25 - mulh s11, s1, s9 - add s7, s5, a6 - div t3, t1, t5 - slli s11, gp, 14 - mulhsu gp, a1, s1 - c.srli a0, 25 - slti tp, t6, 301 - xor t4, s3, t3 - xori a4, t0, 974 - slli s11, gp, 14 - c.li a7, 27 - c.nop - srl a0, s2, a0 - c.xor a1, a2 - c.andi a5, -1 - c.li a7, 27 - or s0, a2, a0 - c.nop - srl a0, s2, a0 - srai s10, s1, 24 - c.mv a1, s5 - xori a4, t0, 974 - xori a4, t0, 974 - srl a0, s2, a0 - c.mv a1, s5 - c.or a5, a1 - c.srli a0, 25 - slti tp, t6, 301 - c.srli a0, 25 - srli s8, t6, 19 - c.mv a1, s5 - c.srai s0, 31 - c.nop - nop - slli s11, gp, 14 - srli s8, t6, 19 - srai s10, s1, 24 - c.and a0, s0 - add s7, s5, a6 - c.slli t4, 28 - srli s8, t6, 19 - srl a0, s2, a0 - add s7, s5, a6 - or s0, a2, a0 - mulhsu gp, a1, s1 - c.slli t4, 28 - c.slli t4, 28 - srli s8, t6, 19 - slti tp, t6, 301 - sltiu s6, ra, 913 - remu s5, s11, t1 - srai s10, s1, 24 - c.li a7, 27 - remu s5, s11, t1 - slti tp, t6, 301 - c.nop - sra s1, t3, s1 - c.add t1, a1 - sub s9, s6, s5 - mul sp, s9, s11 - sltiu s6, ra, 913 - slli s11, gp, 14 - srai s10, s1, 24 - lui zero, 195546 - nop - mulh s11, s1, s9 - srl a0, s2, a0 - c.xor a1, a2 - c.lui a0, 24 - srl a0, s2, a0 - c.xor a1, a2 - rem s0, a3, a2 - add s7, s5, a6 - rem s0, a3, a2 - or s0, a2, a0 - c.li a7, 27 - c.li a7, 27 - nop - rem s0, a3, a2 - rem s0, a3, a2 - sltiu s6, ra, 913 - rem s0, a3, a2 - nop - c.or a5, a1 - slt t1, a1, a4 - c.addi s1, 6 - and a1, t3, a6 - or s0, a2, a0 - mul sp, s9, s11 - c.addi4spn a4, sp, 288 - mulhsu gp, a1, s1 - c.srai s0, 31 - addi a7, t2, -784 - mulh s11, s1, s9 - or s0, a2, a0 - srl a0, s2, a0 - c.srli a0, 25 - sltiu s6, ra, 913 - c.addi s1, 6 - addi a7, t2, -784 - srl a0, s2, a0 - c.sub s1, a4 - lui zero, 195546 - xor t4, s3, t3 - c.mv a1, s5 - c.mv a1, s5 - c.mv a1, s5 - c.nop - mulhu tp, s3, a4 - remu s5, s11, t1 - c.sub s1, a4 - c.xor a1, a2 - c.addi16sp sp, 16 - div t3, t1, t5 - and a1, t3, a6 - sll t3, s7, a3 - c.and a0, s0 - sub s9, s6, s5 - remu s5, s11, t1 - c.lui a0, 24 - c.add t1, a1 - c.xor a1, a2 - c.and a0, s0 - sll t3, s7, a3 - sub s9, s6, s5 - slt t1, a1, a4 - c.slli t4, 28 - c.srai s0, 31 - srai s10, s1, 24 - slt t1, a1, a4 - sll t3, s7, a3 - c.andi a5, -1 - c.and a0, s0 - lui zero, 195546 - rem s0, a3, a2 - c.li a7, 27 - sll t3, s7, a3 - ori t5, t2, 999 - mulhsu gp, a1, s1 - c.sub s1, a4 - c.srli a0, 25 - or s0, a2, a0 - add s7, s5, a6 - srli s8, t6, 19 - c.and a0, s0 - c.addi s1, 6 - c.addi s1, 6 - c.lui a0, 24 - c.lui a0, 24 - c.add t1, a1 - c.or a5, a1 - slt t1, a1, a4 - c.srli a0, 25 - auipc t6, 688967 - addi a7, t2, -784 - divu sp, ra, t0 - nop - sra s1, t3, s1 - c.addi4spn a4, sp, 288 - c.slli t4, 28 - and a1, t3, a6 - c.sub s1, a4 - c.srli a0, 25 - lui zero, 195546 - c.mv a1, s5 - srli s8, t6, 19 - c.xor a1, a2 - c.srli a0, 25 - div t3, t1, t5 - slti tp, t6, 301 - c.and a0, s0 - or s0, a2, a0 - c.add t1, a1 - c.addi4spn a4, sp, 288 - lui zero, 195546 - slt t1, a1, a4 - c.sub s1, a4 - sll t3, s7, a3 - slt t1, a1, a4 - xori a4, t0, 974 - mulhsu gp, a1, s1 - c.mv a1, s5 - c.lui a0, 24 - c.nop - sltiu s6, ra, 913 - slt t1, a1, a4 - rem s0, a3, a2 - c.andi a5, -1 - sra s1, t3, s1 - li s1, 0xffffffff #start riscv_int_numeric_corner_stream_20 - li s2, 0x80000000 - li t5, 0x76bbf178 - li s6, 0x80000000 - li s5, 0x80000000 - li ra, 0x0 - li s0, 0x0 - li a5, 0xffffffff - li gp, 0x1b14077b - li a6, 0x0 - lui ra, 195546 - mulh t5, s5, s5 - auipc t5, 688967 - lui ra, 195546 - lui ra, 195546 - mulhu ra, a5, s1 - add s1, a5, a6 - addi a6, s5, 999 - addi a6, s5, 999 - mulh t5, s5, s5 - nop - add s1, a5, a6 - mulhsu a5, s6, a6 - nop - sub s5, a6, s6 - auipc t5, 688967 - add s1, a5, a6 - nop - mul ra, t5, t5 - nop - add s1, a5, a6 - nop - auipc t5, 688967 - rem s0, a5, s0 #end riscv_int_numeric_corner_stream_20 - sltiu s6, ra, 913 - addi a7, t2, -784 - c.srai s0, 31 - divu sp, ra, t0 - auipc t6, 688967 - c.xor a1, a2 - nop - c.srai s0, 31 - sub s9, s6, s5 - c.srai s0, 31 - c.andi a5, -1 - div t3, t1, t5 - c.li a7, 27 - or s0, a2, a0 - mulh s11, s1, s9 - sltiu s6, ra, 913 - mulhsu gp, a1, s1 - c.mv a1, s5 - c.slli t4, 28 - srl a0, s2, a0 - c.mv a1, s5 - mulh s11, s1, s9 - c.or a5, a1 - xor t4, s3, t3 - c.srli a0, 25 - srl a0, s2, a0 - c.sub s1, a4 - sltiu s6, ra, 913 - c.mv a1, s5 - mulhsu gp, a1, s1 - sltiu s6, ra, 913 - lui zero, 195546 - c.andi a5, -1 - sltiu s6, ra, 913 - mulh s11, s1, s9 - xori a4, t0, 974 - c.srai s0, 31 - slt t1, a1, a4 - c.srai s0, 31 - rem s0, a3, a2 - sll t3, s7, a3 - xor t4, s3, t3 - xor t4, s3, t3 - c.addi4spn a4, sp, 288 - c.mv a1, s5 - and a1, t3, a6 - sra s1, t3, s1 - div t3, t1, t5 - c.slli t4, 28 - mulh s11, s1, s9 - c.mv a1, s5 - nop - div t3, t1, t5 - sra s1, t3, s1 - c.addi s1, 6 - c.lui a0, 24 - andi s8, t1, -26 - sltiu s6, ra, 913 - c.slli t4, 28 - sltu t2, s1, t1 - sltiu s6, ra, 913 - c.andi a5, -1 - c.nop - sll t3, s7, a3 - mulh s11, s1, s9 - c.lui a0, 24 - c.lui a0, 24 - mulh s11, s1, s9 - xor t4, s3, t3 - mulhu tp, s3, a4 - or s0, a2, a0 - c.slli t4, 28 - xori a4, t0, 974 - c.addi4spn a4, sp, 288 - mul sp, s9, s11 - c.andi a5, -1 - c.and a0, s0 - c.srai s0, 31 - rem s0, a3, a2 - add s7, s5, a6 - andi s8, t1, -26 - addi a7, t2, -784 - xori a4, t0, 974 - srli s8, t6, 19 - nop - divu sp, ra, t0 - c.and a0, s0 - srai s10, s1, 24 - c.srai s0, 31 - srl a0, s2, a0 - sra s1, t3, s1 - nop - sll t3, s7, a3 - mul sp, s9, s11 - sll t3, s7, a3 - auipc t6, 688967 - c.addi s1, 6 - c.and a0, s0 - mul sp, s9, s11 - rem s0, a3, a2 - srl a0, s2, a0 - c.add t1, a1 - mulhu tp, s3, a4 - and a1, t3, a6 - mulhu tp, s3, a4 - xor t4, s3, t3 - addi a7, t2, -784 - andi s8, t1, -26 - c.addi16sp sp, 16 - srai s10, s1, 24 - sub s9, s6, s5 - andi s8, t1, -26 - or s0, a2, a0 - slt t1, a1, a4 - sltu t2, s1, t1 - c.xor a1, a2 - div t3, t1, t5 - c.or a5, a1 - srli s8, t6, 19 - mulh s11, s1, s9 - div t3, t1, t5 - or s0, a2, a0 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - sra s1, t3, s1 - c.lui a0, 24 - slti tp, t6, 301 - c.xor a1, a2 - xori a4, t0, 974 - ori t5, t2, 999 - c.addi s1, 6 - c.mv a1, s5 - add s7, s5, a6 - srli s8, t6, 19 - c.add t1, a1 - c.srli a0, 25 - divu sp, ra, t0 - c.addi s1, 6 - c.add t1, a1 - c.sub s1, a4 - sra s1, t3, s1 - sltu t2, s1, t1 - xori a4, t0, 974 - slti tp, t6, 301 - c.andi a5, -1 - and a1, t3, a6 - c.srai s0, 31 - divu sp, ra, t0 - c.andi a5, -1 - c.or a5, a1 - slt t1, a1, a4 - c.andi a5, -1 - sltiu s6, ra, 913 - sub s9, s6, s5 - c.li a7, 27 - c.srai s0, 31 - srli s8, t6, 19 - remu s5, s11, t1 - mul sp, s9, s11 - c.or a5, a1 - lui zero, 195546 - c.sub s1, a4 - c.slli t4, 28 - divu sp, ra, t0 - div t3, t1, t5 - andi s8, t1, -26 - sra s1, t3, s1 - c.or a5, a1 - sltiu s6, ra, 913 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - slli s11, gp, 14 - slli s11, gp, 14 - c.xor a1, a2 - addi a7, t2, -784 - and a1, t3, a6 - xori a4, t0, 974 - c.or a5, a1 - slti tp, t6, 301 - divu sp, ra, t0 - div t3, t1, t5 - mul sp, s9, s11 - sltu t2, s1, t1 - sltiu s6, ra, 913 - sub s9, s6, s5 - c.lui a0, 24 - c.sub s1, a4 - auipc t6, 688967 - c.srai s0, 31 - remu s5, s11, t1 - auipc t6, 688967 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - c.andi a5, -1 - sra s1, t3, s1 - div t3, t1, t5 - c.andi a5, -1 - mulhu tp, s3, a4 - mulh s11, s1, s9 - c.add t1, a1 - mulhu tp, s3, a4 - c.addi4spn a4, sp, 288 - slti tp, t6, 301 - sltiu s6, ra, 913 - c.slli t4, 28 - c.srai s0, 31 - c.andi a5, -1 - mulhu tp, s3, a4 - slti tp, t6, 301 - divu sp, ra, t0 - slti tp, t6, 301 - slli s11, gp, 14 - remu s5, s11, t1 - slti tp, t6, 301 - c.and a0, s0 - c.slli t4, 28 - and a1, t3, a6 - c.andi a5, -1 - sltiu s6, ra, 913 - slli s11, gp, 14 - xor t4, s3, t3 - srli s8, t6, 19 - andi s8, t1, -26 - c.addi16sp sp, 16 - sll t3, s7, a3 - c.addi16sp sp, 16 - remu s5, s11, t1 - srli s8, t6, 19 - slli s11, gp, 14 - c.lui a0, 24 - c.addi s1, 6 - or s0, a2, a0 - slli s11, gp, 14 - c.mv a1, s5 - c.add t1, a1 - remu s5, s11, t1 - mul sp, s9, s11 - srl a0, s2, a0 - c.add t1, a1 - sltiu s6, ra, 913 - c.andi a5, -1 - mulhu tp, s3, a4 - lui zero, 195546 - c.srai s0, 31 - slt t1, a1, a4 - c.mv a1, s5 - rem s0, a3, a2 - rem s0, a3, a2 - srai s10, s1, 24 - auipc t6, 688967 - c.nop - and a1, t3, a6 - c.addi16sp sp, 16 - auipc t6, 688967 - div t3, t1, t5 - srai s10, s1, 24 - xor t4, s3, t3 - sra s1, t3, s1 - c.slli t4, 28 - ori t5, t2, 999 - auipc t6, 688967 - addi a7, t2, -784 - slli s11, gp, 14 - mulhsu gp, a1, s1 - and a1, t3, a6 - add s7, s5, a6 - c.xor a1, a2 - xori a4, t0, 974 - c.addi s1, 6 - c.srli a0, 25 - sll t3, s7, a3 - sll t3, s7, a3 - c.add t1, a1 - divu sp, ra, t0 - c.li a7, 27 - srl a0, s2, a0 - mul sp, s9, s11 - c.and a0, s0 - c.or a5, a1 - div t3, t1, t5 - ori t5, t2, 999 - mul sp, s9, s11 - add s7, s5, a6 - c.mv a1, s5 - mulhsu gp, a1, s1 - srli s8, t6, 19 - c.andi a5, -1 - c.add t1, a1 - slli s11, gp, 14 - andi s8, t1, -26 - mulh s11, s1, s9 - or s0, a2, a0 - mul sp, s9, s11 - c.srai s0, 31 - sltu t2, s1, t1 - c.srai s0, 31 - sltu t2, s1, t1 - sub s9, s6, s5 - andi s8, t1, -26 - sll t3, s7, a3 - sub s9, s6, s5 - c.andi a5, -1 - add s7, s5, a6 - slli s11, gp, 14 - div t3, t1, t5 - andi s8, t1, -26 - c.lui a0, 24 - c.slli t4, 28 - c.addi4spn a4, sp, 288 - add s7, s5, a6 - remu s5, s11, t1 - c.nop - xori a4, t0, 974 - add s7, s5, a6 - sltu t2, s1, t1 - c.and a0, s0 - sll t3, s7, a3 - srli s8, t6, 19 - sltiu s6, ra, 913 - mulh s11, s1, s9 - addi a7, t2, -784 - mulh s11, s1, s9 - lui zero, 195546 - c.or a5, a1 - c.xor a1, a2 - mulhsu gp, a1, s1 - srl a0, s2, a0 - auipc t6, 688967 - c.addi s1, 6 - and a1, t3, a6 - or s0, a2, a0 - sltiu s6, ra, 913 - c.addi16sp sp, 16 - lui zero, 195546 - c.lui a0, 24 - c.or a5, a1 - c.mv a1, s5 - c.andi a5, -1 - c.nop - lui zero, 195546 - xori a4, t0, 974 - li s5, 0x80000000 #start riscv_int_numeric_corner_stream_36 - li a5, 0xe22a63ce - li a7, 0x80000000 - li a1, 0xffffffff - li t3, 0x1cea3d51 - li a6, 0x4b0eafba - li a0, 0x36dd1f9f - li t4, 0xffffffff - li a4, 0x80000000 - li ra, 0xffffffff - remu a6, a1, a0 - div ra, a6, a0 - div ra, a6, a0 - mul ra, t4, t3 - lui ra, 195546 - addi ra, s5, 999 - nop - addi ra, s5, 999 - addi ra, s5, 999 - nop - addi ra, s5, 999 - mulhu a6, a4, ra - div ra, a6, a0 - add ra, a6, a7 - nop #end riscv_int_numeric_corner_stream_36 - c.srai s0, 31 - slt t1, a1, a4 - mulh s11, s1, s9 - c.andi a5, -1 - c.and a0, s0 - c.addi16sp sp, 16 - xor t4, s3, t3 - c.srli a0, 25 - sub s9, s6, s5 - c.srli a0, 25 - c.addi s1, 6 - auipc t6, 688967 - mulhsu gp, a1, s1 - ori t5, t2, 999 - srai s10, s1, 24 - c.sub s1, a4 - slti tp, t6, 301 - remu s5, s11, t1 - c.sub s1, a4 - mul sp, s9, s11 - c.or a5, a1 - c.add t1, a1 - or s0, a2, a0 - slli s11, gp, 14 - xor t4, s3, t3 - sra s1, t3, s1 - lui zero, 195546 - ori t5, t2, 999 - c.xor a1, a2 - c.srai s0, 31 - c.mv a1, s5 - slti tp, t6, 301 - sub s9, s6, s5 - mul sp, s9, s11 - mulhsu gp, a1, s1 - srai s10, s1, 24 - rem s0, a3, a2 - slti tp, t6, 301 - xor t4, s3, t3 - sltiu s6, ra, 913 - mulhu tp, s3, a4 - xori a4, t0, 974 - c.li a7, 27 - c.srli a0, 25 - c.nop - sra s1, t3, s1 - sll t3, s7, a3 - c.add t1, a1 - c.nop - slt t1, a1, a4 - mulh s11, s1, s9 - c.and a0, s0 - ori t5, t2, 999 - sll t3, s7, a3 - c.addi16sp sp, 16 - li s8, 0xffffffff #start riscv_int_numeric_corner_stream_29 - li s11, 0x80000000 - li t1, 0xab55c50e - li a0, 0x80000000 - li s10, 0x0 - li s7, 0x1018821 - li s1, 0x9ce6fbd3 - li ra, 0x80000000 - li s3, 0xffffffff - li s9, 0x80000000 - sub ra, s8, t1 - nop - lui ra, 195546 - nop - remu t1, t1, a0 - add s1, a0, s8 - remu t1, t1, a0 - nop - nop - mulhsu s8, s8, s3 - addi ra, s7, 999 - nop - lui ra, 195546 - sub ra, s8, t1 - nop #end riscv_int_numeric_corner_stream_29 - c.li a7, 27 - mulhu tp, s3, a4 - add s7, s5, a6 - add s7, s5, a6 - and a1, t3, a6 - srl a0, s2, a0 - c.srai s0, 31 - c.li a7, 27 - remu s5, s11, t1 - and a1, t3, a6 - mulhu tp, s3, a4 - srli s8, t6, 19 - srai s10, s1, 24 - sltiu s6, ra, 913 - c.addi s1, 6 - xor t4, s3, t3 - c.slli t4, 28 - andi s8, t1, -26 - or s0, a2, a0 - c.sub s1, a4 - c.mv a1, s5 - nop - c.addi4spn a4, sp, 288 - c.xor a1, a2 - divu sp, ra, t0 - c.and a0, s0 - sll t3, s7, a3 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - or s0, a2, a0 - c.andi a5, -1 - remu s5, s11, t1 - rem s0, a3, a2 - lui zero, 195546 - divu sp, ra, t0 - c.xor a1, a2 - nop - srl a0, s2, a0 - mul sp, s9, s11 - sltu t2, s1, t1 - c.sub s1, a4 - or s0, a2, a0 - lui zero, 195546 - c.addi s1, 6 - or s0, a2, a0 - c.addi16sp sp, 16 - nop - auipc t6, 688967 - c.add t1, a1 - mulhu tp, s3, a4 - srai s10, s1, 24 - sltiu s6, ra, 913 - c.or a5, a1 - ori t5, t2, 999 - mulh s11, s1, s9 - c.lui a0, 24 - lui zero, 195546 - slt t1, a1, a4 - sll t3, s7, a3 - c.add t1, a1 - xor t4, s3, t3 - xori a4, t0, 974 - mulhsu gp, a1, s1 - ori t5, t2, 999 - c.mv a1, s5 - lui zero, 195546 - or s0, a2, a0 - c.srai s0, 31 - c.xor a1, a2 - c.sub s1, a4 - xor t4, s3, t3 - srl a0, s2, a0 - c.addi4spn a4, sp, 288 - sltiu s6, ra, 913 - c.nop - slti tp, t6, 301 - sltu t2, s1, t1 - c.xor a1, a2 - rem s0, a3, a2 - divu sp, ra, t0 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - srl a0, s2, a0 - sltu t2, s1, t1 - srai s10, s1, 24 - lui zero, 195546 - c.nop - c.addi s1, 6 - and a1, t3, a6 - lui zero, 195546 - mul sp, s9, s11 - and a1, t3, a6 - c.li a7, 27 - xor t4, s3, t3 - c.and a0, s0 - c.srai s0, 31 - c.lui a0, 24 - c.li a7, 27 - c.and a0, s0 - slti tp, t6, 301 - srli s8, t6, 19 - add s7, s5, a6 - c.nop - andi s8, t1, -26 - div t3, t1, t5 - mulhu tp, s3, a4 - c.srai s0, 31 - and a1, t3, a6 - c.xor a1, a2 - add s7, s5, a6 - remu s5, s11, t1 - slti tp, t6, 301 - slli s11, gp, 14 - nop - sltu t2, s1, t1 - c.addi4spn a4, sp, 288 - c.addi16sp sp, 16 - sll t3, s7, a3 - addi a7, t2, -784 - slt t1, a1, a4 - auipc t6, 688967 - srl a0, s2, a0 - c.slli t4, 28 - c.addi4spn a4, sp, 288 - mulhsu gp, a1, s1 - slti tp, t6, 301 - auipc t6, 688967 - c.slli t4, 28 - mul sp, s9, s11 - sltu t2, s1, t1 - mulhu tp, s3, a4 - lui zero, 195546 - c.srli a0, 25 - c.srai s0, 31 - div t3, t1, t5 - sll t3, s7, a3 - c.and a0, s0 - rem s0, a3, a2 - c.srai s0, 31 - c.add t1, a1 - sltu t2, s1, t1 - c.lui a0, 24 - rem s0, a3, a2 - auipc t6, 688967 - c.srli a0, 25 - c.mv a1, s5 - sltu t2, s1, t1 - srai s10, s1, 24 - c.addi16sp sp, 16 - remu s5, s11, t1 - slli s11, gp, 14 - nop - c.addi s1, 6 - mulh s11, s1, s9 - sra s1, t3, s1 - divu sp, ra, t0 - slli s11, gp, 14 - andi s8, t1, -26 - slt t1, a1, a4 - addi a7, t2, -784 - srli s8, t6, 19 - xori a4, t0, 974 - c.addi s1, 6 - xor t4, s3, t3 - srai s10, s1, 24 - slti tp, t6, 301 - mul sp, s9, s11 - mul sp, s9, s11 - sltu t2, s1, t1 - c.addi s1, 6 - sll t3, s7, a3 - add s7, s5, a6 - c.sub s1, a4 - c.nop - sltiu s6, ra, 913 - c.srai s0, 31 - div t3, t1, t5 - c.nop - div t3, t1, t5 - c.xor a1, a2 - slt t1, a1, a4 - c.srai s0, 31 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - sltu t2, s1, t1 - sltiu s6, ra, 913 - remu s5, s11, t1 - c.addi16sp sp, 16 - mulh s11, s1, s9 - slt t1, a1, a4 - rem s0, a3, a2 - slti tp, t6, 301 - c.mv a1, s5 - ori t5, t2, 999 - c.and a0, s0 - c.xor a1, a2 - sra s1, t3, s1 - c.mv a1, s5 - xor t4, s3, t3 - auipc t6, 688967 - remu s5, s11, t1 - mulhu tp, s3, a4 - sltiu s6, ra, 913 - ori t5, t2, 999 - c.xor a1, a2 - c.addi4spn a4, sp, 288 - ori t5, t2, 999 - slti tp, t6, 301 - c.and a0, s0 - slt t1, a1, a4 - slti tp, t6, 301 - remu s5, s11, t1 - nop - sra s1, t3, s1 - c.mv a1, s5 - mulh s11, s1, s9 - c.nop - c.mv a1, s5 - c.mv a1, s5 - divu sp, ra, t0 - addi a7, t2, -784 - c.nop - and a1, t3, a6 - sra s1, t3, s1 - srl a0, s2, a0 - addi a7, t2, -784 - slli s11, gp, 14 - mul sp, s9, s11 - or s0, a2, a0 - xori a4, t0, 974 - c.li a7, 27 - c.andi a5, -1 - c.addi s1, 6 - rem s0, a3, a2 - c.addi4spn a4, sp, 288 - lui zero, 195546 - c.srli a0, 25 - divu sp, ra, t0 - sltu t2, s1, t1 - and a1, t3, a6 - add s7, s5, a6 - c.nop - div t3, t1, t5 - xor t4, s3, t3 - mulhsu gp, a1, s1 - c.mv a1, s5 - add s7, s5, a6 - c.nop - div t3, t1, t5 - div t3, t1, t5 - c.srai s0, 31 - c.addi s1, 6 - xor t4, s3, t3 - mulh s11, s1, s9 - slti tp, t6, 301 - and a1, t3, a6 - andi s8, t1, -26 - addi a7, t2, -784 - nop - ori t5, t2, 999 - srai s10, s1, 24 - addi a7, t2, -784 - remu s5, s11, t1 - nop - ori t5, t2, 999 - xor t4, s3, t3 - div t3, t1, t5 - auipc t6, 688967 - c.srai s0, 31 - slli s11, gp, 14 - div t3, t1, t5 - c.and a0, s0 - c.addi16sp sp, 16 - c.mv a1, s5 - c.add t1, a1 - c.srai s0, 31 - add s7, s5, a6 - srai s10, s1, 24 - c.mv a1, s5 - srai s10, s1, 24 - mulh s11, s1, s9 - c.andi a5, -1 - or s0, a2, a0 - sltiu s6, ra, 913 - nop - sub s9, s6, s5 - rem s0, a3, a2 - c.mv a1, s5 - srl a0, s2, a0 - slt t1, a1, a4 - mul sp, s9, s11 - c.srli a0, 25 - c.srli a0, 25 - c.andi a5, -1 - c.mv a1, s5 - nop - sll t3, s7, a3 - srai s10, s1, 24 - addi a7, t2, -784 - c.addi s1, 6 - c.slli t4, 28 - c.lui a0, 24 - slli s11, gp, 14 - c.or a5, a1 - mul sp, s9, s11 - mulhsu gp, a1, s1 - div t3, t1, t5 - c.addi16sp sp, 16 - mulh s11, s1, s9 - add s7, s5, a6 - c.addi4spn a4, sp, 288 - sltu t2, s1, t1 - srl a0, s2, a0 - sub s9, s6, s5 - c.addi s1, 6 - slli s11, gp, 14 - c.addi s1, 6 - sltiu s6, ra, 913 - slti tp, t6, 301 - c.xor a1, a2 - and a1, t3, a6 - slt t1, a1, a4 - mulhu tp, s3, a4 - c.and a0, s0 - mulhu tp, s3, a4 - slli s11, gp, 14 - xori a4, t0, 974 - c.sub s1, a4 - remu s5, s11, t1 - c.xor a1, a2 - mulhu tp, s3, a4 - slti tp, t6, 301 - lui zero, 195546 - c.nop - c.nop - c.addi16sp sp, 16 - xor t4, s3, t3 - mulh s11, s1, s9 - srai s10, s1, 24 - c.nop - add s7, s5, a6 - c.nop - xor t4, s3, t3 - c.andi a5, -1 - slt t1, a1, a4 - c.srai s0, 31 - sra s1, t3, s1 - slli s11, gp, 14 - srl a0, s2, a0 - srli s8, t6, 19 - c.li a7, 27 - slti tp, t6, 301 - nop - rem s0, a3, a2 - mulhu tp, s3, a4 - xor t4, s3, t3 - c.sub s1, a4 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - c.or a5, a1 - ori t5, t2, 999 - srl a0, s2, a0 - c.or a5, a1 - c.srai s0, 31 - sra s1, t3, s1 - c.addi s1, 6 - sltiu s6, ra, 913 - addi a7, t2, -784 - sub s9, s6, s5 - sltu t2, s1, t1 - sltu t2, s1, t1 - c.addi s1, 6 - mul sp, s9, s11 - c.nop - auipc t6, 688967 - c.lui a0, 24 - xor t4, s3, t3 - c.slli t4, 28 - c.and a0, s0 - c.srai s0, 31 - c.addi s1, 6 - c.or a5, a1 - slli s11, gp, 14 - mulh s11, s1, s9 - c.sub s1, a4 - srai s10, s1, 24 - sltu t2, s1, t1 - c.addi16sp sp, 16 - srai s10, s1, 24 - sub s9, s6, s5 - and a1, t3, a6 - c.xor a1, a2 - c.add t1, a1 - mulhsu gp, a1, s1 - c.srai s0, 31 - mul sp, s9, s11 - or s0, a2, a0 - divu sp, ra, t0 - c.or a5, a1 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - c.addi16sp sp, 16 - div t3, t1, t5 - add s7, s5, a6 - lui zero, 195546 - c.nop - c.addi s1, 6 - c.sub s1, a4 - c.srli a0, 25 - sra s1, t3, s1 - mul sp, s9, s11 - sltu t2, s1, t1 - sltu t2, s1, t1 - mulh s11, s1, s9 - c.and a0, s0 - c.or a5, a1 - mulh s11, s1, s9 - mul sp, s9, s11 - sra s1, t3, s1 - sub s9, s6, s5 - srl a0, s2, a0 - c.sub s1, a4 - lui zero, 195546 - add s7, s5, a6 - srli s8, t6, 19 - c.srli a0, 25 - c.nop - ori t5, t2, 999 - c.and a0, s0 - c.andi a5, -1 - c.and a0, s0 - c.andi a5, -1 - auipc t6, 688967 - c.add t1, a1 - c.mv a1, s5 - c.or a5, a1 - lui zero, 195546 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - c.sub s1, a4 - c.lui a0, 24 - c.and a0, s0 - srl a0, s2, a0 - c.srai s0, 31 - xori a4, t0, 974 - addi a7, t2, -784 - addi a7, t2, -784 - c.andi a5, -1 - c.srai s0, 31 - c.slli t4, 28 - c.and a0, s0 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - add s7, s5, a6 - divu sp, ra, t0 - mulhsu gp, a1, s1 - xori a4, t0, 974 - c.xor a1, a2 - addi a7, t2, -784 - rem s0, a3, a2 - slt t1, a1, a4 - c.li a7, 27 - c.and a0, s0 - mulhsu gp, a1, s1 - ori t5, t2, 999 - xor t4, s3, t3 - div t3, t1, t5 - c.and a0, s0 - andi s8, t1, -26 - mul sp, s9, s11 - add s7, s5, a6 - or s0, a2, a0 - c.addi s1, 6 - mulh s11, s1, s9 - srai s10, s1, 24 - xori a4, t0, 974 - mulh s11, s1, s9 - c.andi a5, -1 - or s0, a2, a0 - or s0, a2, a0 - slli s11, gp, 14 - c.andi a5, -1 - mul sp, s9, s11 - xori a4, t0, 974 - div t3, t1, t5 - srli s8, t6, 19 - andi s8, t1, -26 - mulh s11, s1, s9 - sub s9, s6, s5 - divu sp, ra, t0 - sub s9, s6, s5 - remu s5, s11, t1 - c.lui a0, 24 - rem s0, a3, a2 - rem s0, a3, a2 - xor t4, s3, t3 - divu sp, ra, t0 - c.mv a1, s5 - lui zero, 195546 - srai s10, s1, 24 - and a1, t3, a6 - addi a7, t2, -784 - c.nop - mulhu tp, s3, a4 - sra s1, t3, s1 - c.xor a1, a2 - c.nop - c.xor a1, a2 - nop - mulhsu gp, a1, s1 - xori a4, t0, 974 - xori a4, t0, 974 - c.andi a5, -1 - nop - xor t4, s3, t3 - xor t4, s3, t3 - lui zero, 195546 - sll t3, s7, a3 - srai s10, s1, 24 - slli s11, gp, 14 - div t3, t1, t5 - and a1, t3, a6 - sub s9, s6, s5 - add s7, s5, a6 - slli s11, gp, 14 - c.li a7, 27 - lui zero, 195546 - c.slli t4, 28 - add s7, s5, a6 - c.slli t4, 28 - srl a0, s2, a0 - c.li a7, 27 - c.mv a1, s5 - c.nop - slt t1, a1, a4 - ori t5, t2, 999 - sltiu s6, ra, 913 - mulh s11, s1, s9 - addi a7, t2, -784 - srli s8, t6, 19 - c.li a7, 27 - mulhsu gp, a1, s1 - c.li a7, 27 - c.srli a0, 25 - srli s8, t6, 19 - sub s9, s6, s5 - c.addi16sp sp, 16 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - c.xor a1, a2 - c.srai s0, 31 - c.add t1, a1 - c.addi16sp sp, 16 - c.sub s1, a4 - lui zero, 195546 - slt t1, a1, a4 - c.sub s1, a4 - c.andi a5, -1 - srl a0, s2, a0 - add s7, s5, a6 - xori a4, t0, 974 - sub s9, s6, s5 - slti tp, t6, 301 - andi s8, t1, -26 - addi a7, t2, -784 - srai s10, s1, 24 - sltiu s6, ra, 913 - c.sub s1, a4 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - c.nop - and a1, t3, a6 - slti tp, t6, 301 - nop - c.srai s0, 31 - c.andi a5, -1 - sltiu s6, ra, 913 - sltiu s6, ra, 913 - rem s0, a3, a2 - or s0, a2, a0 - addi a7, t2, -784 - xor t4, s3, t3 - and a1, t3, a6 - add s7, s5, a6 - slli s11, gp, 14 - auipc t6, 688967 - srai s10, s1, 24 - xor t4, s3, t3 - sra s1, t3, s1 - sltu t2, s1, t1 - sra s1, t3, s1 - c.xor a1, a2 - c.or a5, a1 - remu s5, s11, t1 - sub s9, s6, s5 - c.srai s0, 31 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - and a1, t3, a6 - slt t1, a1, a4 - sra s1, t3, s1 - xor t4, s3, t3 - c.lui a0, 24 - nop - div t3, t1, t5 - andi s8, t1, -26 - c.mv a1, s5 - c.srli a0, 25 - c.li a7, 27 - sll t3, s7, a3 - ori t5, t2, 999 - srai s10, s1, 24 - srai s10, s1, 24 - c.nop - mulh s11, s1, s9 - c.srli a0, 25 - c.andi a5, -1 - srli s8, t6, 19 - auipc t6, 688967 - rem s0, a3, a2 - c.addi16sp sp, 16 - srai s10, s1, 24 - mul sp, s9, s11 - c.and a0, s0 - c.lui a0, 24 - c.or a5, a1 - remu s5, s11, t1 - div t3, t1, t5 - c.add t1, a1 - slt t1, a1, a4 - c.add t1, a1 - c.and a0, s0 - or s0, a2, a0 - srli s8, t6, 19 - lui zero, 195546 - sll t3, s7, a3 - remu s5, s11, t1 - c.lui a0, 24 - mul sp, s9, s11 - slli s11, gp, 14 - ori t5, t2, 999 - mul sp, s9, s11 - slti tp, t6, 301 - mulhsu gp, a1, s1 - remu s5, s11, t1 - c.srai s0, 31 - ori t5, t2, 999 - sltiu s6, ra, 913 - sltu t2, s1, t1 - sltiu s6, ra, 913 - slli s11, gp, 14 - c.and a0, s0 - c.srli a0, 25 - slti tp, t6, 301 - sra s1, t3, s1 - mulh s11, s1, s9 - c.or a5, a1 - nop - mulhu tp, s3, a4 - c.lui a0, 24 - addi a7, t2, -784 - c.li a7, 27 - srai s10, s1, 24 - mulhu tp, s3, a4 - rem s0, a3, a2 - c.li a7, 27 - c.add t1, a1 - c.or a5, a1 - div t3, t1, t5 - sltiu s6, ra, 913 - lui zero, 195546 - c.srai s0, 31 - add s7, s5, a6 - andi s8, t1, -26 - xori a4, t0, 974 - c.add t1, a1 - c.sub s1, a4 - c.sub s1, a4 - sltu t2, s1, t1 - c.and a0, s0 - c.addi s1, 6 - div t3, t1, t5 - xor t4, s3, t3 - nop - andi s8, t1, -26 - and a1, t3, a6 - c.slli t4, 28 - mulhsu gp, a1, s1 - remu s5, s11, t1 - mulhsu gp, a1, s1 - slli s11, gp, 14 - xor t4, s3, t3 - srai s10, s1, 24 - c.xor a1, a2 - ori t5, t2, 999 - c.addi s1, 6 - c.nop - c.slli t4, 28 - mulhsu gp, a1, s1 - c.nop - c.mv a1, s5 - sll t3, s7, a3 - xor t4, s3, t3 - nop - c.mv a1, s5 - slli s11, gp, 14 - xori a4, t0, 974 - andi s8, t1, -26 - xor t4, s3, t3 - c.slli t4, 28 - slt t1, a1, a4 - slt t1, a1, a4 - mulh s11, s1, s9 - c.add t1, a1 - c.lui a0, 24 - mulh s11, s1, s9 - c.addi s1, 6 - c.nop - srli s8, t6, 19 - add s7, s5, a6 - div t3, t1, t5 - sub s9, s6, s5 - nop - slti tp, t6, 301 - c.add t1, a1 - c.mv a1, s5 - c.andi a5, -1 - remu s5, s11, t1 - c.addi16sp sp, 16 - sltiu s6, ra, 913 - auipc t6, 688967 - c.addi s1, 6 - c.mv a1, s5 - sltiu s6, ra, 913 - c.add t1, a1 - c.add t1, a1 - divu sp, ra, t0 - sra s1, t3, s1 - addi a7, t2, -784 - c.sub s1, a4 - c.nop - c.mv a1, s5 - c.srli a0, 25 - sra s1, t3, s1 - c.add t1, a1 - srli s8, t6, 19 - lui zero, 195546 - c.srli a0, 25 - mulh s11, s1, s9 - rem s0, a3, a2 - andi s8, t1, -26 - c.li a7, 27 - auipc t6, 688967 - xori a4, t0, 974 - slti tp, t6, 301 - c.li a7, 27 - srl a0, s2, a0 - c.mv a1, s5 - andi s8, t1, -26 - auipc t6, 688967 - auipc t6, 688967 - slti tp, t6, 301 - sltu t2, s1, t1 - srli s8, t6, 19 - sltiu s6, ra, 913 - srli s8, t6, 19 - c.xor a1, a2 - remu s5, s11, t1 - sltiu s6, ra, 913 - c.or a5, a1 - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - xor t4, s3, t3 - c.mv a1, s5 - and a1, t3, a6 - sltu t2, s1, t1 - c.slli t4, 28 - c.or a5, a1 - c.add t1, a1 - mul sp, s9, s11 - c.li a7, 27 - addi a7, t2, -784 - c.and a0, s0 - add s7, s5, a6 - add s7, s5, a6 - add s7, s5, a6 - srl a0, s2, a0 - sltu t2, s1, t1 - sltiu s6, ra, 913 - sltiu s6, ra, 913 - mulhu tp, s3, a4 - c.slli t4, 28 - c.sub s1, a4 - sra s1, t3, s1 - ori t5, t2, 999 - or s0, a2, a0 - auipc t6, 688967 - add s7, s5, a6 - c.nop - mulhu tp, s3, a4 - add s7, s5, a6 - c.add t1, a1 - sub s9, s6, s5 - c.li a7, 27 - slli s11, gp, 14 - srai s10, s1, 24 - c.addi s1, 6 - xori a4, t0, 974 - add s7, s5, a6 - c.nop - xor t4, s3, t3 - c.addi16sp sp, 16 - xor t4, s3, t3 - srl a0, s2, a0 - mul sp, s9, s11 - sltiu s6, ra, 913 - srai s10, s1, 24 - c.and a0, s0 - andi s8, t1, -26 - c.mv a1, s5 - c.addi16sp sp, 16 - mulhsu gp, a1, s1 - c.sub s1, a4 - auipc t6, 688967 - c.srai s0, 31 - c.or a5, a1 - srai s10, s1, 24 - xori a4, t0, 974 - c.li a7, 27 - divu sp, ra, t0 - srl a0, s2, a0 - srli s8, t6, 19 - c.srai s0, 31 - nop - auipc t6, 688967 - slt t1, a1, a4 - c.and a0, s0 - c.add t1, a1 - mulhu tp, s3, a4 - nop - c.srli a0, 25 - c.srli a0, 25 - c.addi16sp sp, 16 - sltu t2, s1, t1 - c.addi16sp sp, 16 - slti tp, t6, 301 - auipc t6, 688967 - sll t3, s7, a3 - srl a0, s2, a0 - c.li a7, 27 - c.sub s1, a4 - c.srli a0, 25 - c.xor a1, a2 - c.srli a0, 25 - c.li a7, 27 - c.andi a5, -1 - or s0, a2, a0 - mulhu tp, s3, a4 - divu sp, ra, t0 - srai s10, s1, 24 - c.slli t4, 28 - auipc t6, 688967 - rem s0, a3, a2 - sll t3, s7, a3 - slti tp, t6, 301 - remu s5, s11, t1 - c.addi s1, 6 - add s7, s5, a6 - slti tp, t6, 301 - slt t1, a1, a4 - mulhu tp, s3, a4 - mulh s11, s1, s9 - sra s1, t3, s1 - c.addi16sp sp, 16 - xori a4, t0, 974 - mulh s11, s1, s9 - c.and a0, s0 - andi s8, t1, -26 - c.lui a0, 24 - c.or a5, a1 - slt t1, a1, a4 - c.andi a5, -1 - and a1, t3, a6 - c.lui a0, 24 - slli s11, gp, 14 - and a1, t3, a6 - c.addi s1, 6 - slti tp, t6, 301 - auipc t6, 688967 - nop - xori a4, t0, 974 - c.li a7, 27 - c.addi16sp sp, 16 - c.slli t4, 28 - slli s11, gp, 14 - or s0, a2, a0 - c.srai s0, 31 - sub s9, s6, s5 - mulhu tp, s3, a4 - xori a4, t0, 974 - slti tp, t6, 301 - xori a4, t0, 974 - addi a7, t2, -784 - c.and a0, s0 - c.xor a1, a2 - c.sub s1, a4 - slt t1, a1, a4 - mulh s11, s1, s9 - slti tp, t6, 301 - slli s11, gp, 14 - c.sub s1, a4 - xori a4, t0, 974 - rem s0, a3, a2 - sub s9, s6, s5 - c.nop - srl a0, s2, a0 - c.xor a1, a2 - c.and a0, s0 - c.mv a1, s5 - andi s8, t1, -26 - c.srli a0, 25 - c.addi s1, 6 - div t3, t1, t5 - lui zero, 195546 - sub s9, s6, s5 - remu s5, s11, t1 - divu sp, ra, t0 - c.sub s1, a4 - mulhsu gp, a1, s1 - sub s9, s6, s5 - ori t5, t2, 999 - auipc t6, 688967 - andi s8, t1, -26 - auipc t6, 688967 - sra s1, t3, s1 - c.addi4spn a4, sp, 288 - remu s5, s11, t1 - c.addi16sp sp, 16 - srai s10, s1, 24 - sll t3, s7, a3 - andi s8, t1, -26 - c.slli t4, 28 - c.addi s1, 6 - and a1, t3, a6 - rem s0, a3, a2 - and a1, t3, a6 - slt t1, a1, a4 - mul sp, s9, s11 - ori t5, t2, 999 - sll t3, s7, a3 - andi s8, t1, -26 - sub s9, s6, s5 - xori a4, t0, 974 - andi s8, t1, -26 - slti tp, t6, 301 - c.li a7, 27 - c.nop - sll t3, s7, a3 - slti tp, t6, 301 - srai s10, s1, 24 - sltu t2, s1, t1 - sub s9, s6, s5 - divu sp, ra, t0 - c.addi16sp sp, 16 - srai s10, s1, 24 - xor t4, s3, t3 - c.lui a0, 24 - sll t3, s7, a3 - div t3, t1, t5 - c.li a7, 27 - c.or a5, a1 - rem s0, a3, a2 - c.add t1, a1 - lui zero, 195546 - srl a0, s2, a0 - sltiu s6, ra, 913 - srl a0, s2, a0 - xori a4, t0, 974 - slli s11, gp, 14 - slli s11, gp, 14 - ori t5, t2, 999 - sltu t2, s1, t1 - c.slli t4, 28 - or s0, a2, a0 - c.slli t4, 28 - c.lui a0, 24 - srai s10, s1, 24 - xori a4, t0, 974 - remu s5, s11, t1 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - and a1, t3, a6 - srli s8, t6, 19 - srl a0, s2, a0 - c.slli t4, 28 - srli s8, t6, 19 - xori a4, t0, 974 - mulh s11, s1, s9 - c.srai s0, 31 - srli s8, t6, 19 - mul sp, s9, s11 - c.lui a0, 24 - andi s8, t1, -26 - xori a4, t0, 974 - sltu t2, s1, t1 - rem s0, a3, a2 - divu sp, ra, t0 - c.sub s1, a4 - mulh s11, s1, s9 - c.and a0, s0 - mul sp, s9, s11 - c.lui a0, 24 - addi a7, t2, -784 - or s0, a2, a0 - mulh s11, s1, s9 - sltu t2, s1, t1 - slt t1, a1, a4 - auipc t6, 688967 - c.and a0, s0 - mulh s11, s1, s9 - c.li a7, 27 - auipc t6, 688967 - srai s10, s1, 24 - sra s1, t3, s1 - c.slli t4, 28 - addi a7, t2, -784 - c.xor a1, a2 - and a1, t3, a6 - and a1, t3, a6 - c.andi a5, -1 - c.addi s1, 6 - c.add t1, a1 - c.addi16sp sp, 16 - sll t3, s7, a3 - srl a0, s2, a0 - srl a0, s2, a0 - xor t4, s3, t3 - c.and a0, s0 - sub s9, s6, s5 - c.mv a1, s5 - c.li a7, 27 - xor t4, s3, t3 - c.slli t4, 28 - c.srli a0, 25 - xor t4, s3, t3 - add s7, s5, a6 - c.srli a0, 25 - mulhu tp, s3, a4 - c.sub s1, a4 - addi a7, t2, -784 - slti tp, t6, 301 - mulh s11, s1, s9 - c.xor a1, a2 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - sltu t2, s1, t1 - andi s8, t1, -26 - and a1, t3, a6 - c.or a5, a1 - c.srai s0, 31 - sub s9, s6, s5 - c.srai s0, 31 - c.li a7, 27 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - c.srli a0, 25 - remu s5, s11, t1 - srli s8, t6, 19 - c.nop - srl a0, s2, a0 - divu sp, ra, t0 - sra s1, t3, s1 - c.addi s1, 6 - add s7, s5, a6 - remu s5, s11, t1 - or s0, a2, a0 - sub s9, s6, s5 - c.andi a5, -1 - c.lui a0, 24 - c.sub s1, a4 - c.addi4spn a4, sp, 288 - c.andi a5, -1 - div t3, t1, t5 - c.add t1, a1 - slli s11, gp, 14 - c.xor a1, a2 - slli s11, gp, 14 - divu sp, ra, t0 - add s7, s5, a6 - c.xor a1, a2 - c.andi a5, -1 - c.xor a1, a2 - rem s0, a3, a2 - srli s8, t6, 19 - sltiu s6, ra, 913 - xor t4, s3, t3 - divu sp, ra, t0 - auipc t6, 688967 - or s0, a2, a0 - auipc t6, 688967 - slti tp, t6, 301 - slti tp, t6, 301 - or s0, a2, a0 - slti tp, t6, 301 - c.mv a1, s5 - c.slli t4, 28 - slti tp, t6, 301 - c.add t1, a1 - div t3, t1, t5 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - c.li a7, 27 - c.add t1, a1 - srl a0, s2, a0 - c.sub s1, a4 - c.lui a0, 24 - nop - addi a7, t2, -784 - ori t5, t2, 999 - c.li a7, 27 - slli s11, gp, 14 - c.addi4spn a4, sp, 288 - add s7, s5, a6 - c.addi16sp sp, 16 - ori t5, t2, 999 - srai s10, s1, 24 - c.add t1, a1 - addi a7, t2, -784 - addi a7, t2, -784 - c.nop - c.add t1, a1 - c.addi16sp sp, 16 - mul sp, s9, s11 - slti tp, t6, 301 - srl a0, s2, a0 - xor t4, s3, t3 - rem s0, a3, a2 - mulhu tp, s3, a4 - rem s0, a3, a2 - addi a7, t2, -784 - xori a4, t0, 974 - div t3, t1, t5 - xor t4, s3, t3 - srai s10, s1, 24 - sltu t2, s1, t1 - c.andi a5, -1 - c.andi a5, -1 - srl a0, s2, a0 - li t0, 0xffffffff #start riscv_int_numeric_corner_stream_16 - li s0, 0x0 - li tp, 0xffffffff - li s6, 0x80000000 - li s3, 0x80000000 - li t4, 0xffffffff - li a6, 0x80000000 - li sp, 0xa273e7c6 - li a0, 0x35e4306a - li t6, 0xffffffff - mulh s3, s3, t4 - remu t4, t0, s0 - nop - remu t4, t0, s0 - auipc t6, 688967 - div s3, t6, a0 - mulh s3, s3, t4 - remu t4, t0, s0 - mulh s3, s3, t4 - div s3, t6, a0 - sub t0, a6, tp - mul tp, t4, s6 - sub t0, a6, tp - mulhu sp, s3, t0 - add t0, a0, a6 - remu t4, t0, s0 - auipc t6, 688967 - divu a6, a0, t4 - auipc t6, 688967 - lui tp, 195546 - add t0, a0, a6 - div s3, t6, a0 - sub t0, a6, tp - remu t4, t0, s0 - mul tp, t4, s6 - rem s0, t6, s0 - add t0, a0, a6 #end riscv_int_numeric_corner_stream_16 - srai s10, s1, 24 - xori a4, t0, 974 - c.andi a5, -1 - c.mv a1, s5 - sltiu s6, ra, 913 - c.srli a0, 25 - auipc t6, 688967 - slti tp, t6, 301 - srli s8, t6, 19 - srl a0, s2, a0 - c.or a5, a1 - c.add t1, a1 - c.xor a1, a2 - mulhu tp, s3, a4 - remu s5, s11, t1 - div t3, t1, t5 - sltu t2, s1, t1 - slti tp, t6, 301 - c.addi16sp sp, 16 - c.addi s1, 6 - xor t4, s3, t3 - mulh s11, s1, s9 - slt t1, a1, a4 - sltiu s6, ra, 913 - addi a7, t2, -784 - c.mv a1, s5 - and a1, t3, a6 - sltiu s6, ra, 913 - c.nop - and a1, t3, a6 - c.addi s1, 6 - sra s1, t3, s1 - c.addi4spn a4, sp, 288 - slli s11, gp, 14 - nop - mulhu tp, s3, a4 - c.srli a0, 25 - c.addi16sp sp, 16 - c.srai s0, 31 - sltiu s6, ra, 913 - xori a4, t0, 974 - c.add t1, a1 - sll t3, s7, a3 - and a1, t3, a6 - c.andi a5, -1 - c.li a7, 27 - remu s5, s11, t1 - or s0, a2, a0 - or s0, a2, a0 - sltu t2, s1, t1 - c.sub s1, a4 - c.nop - auipc t6, 688967 - add s7, s5, a6 - lui zero, 195546 - c.andi a5, -1 - srli s8, t6, 19 - mulhsu gp, a1, s1 - mul sp, s9, s11 - divu sp, ra, t0 - slli s11, gp, 14 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - c.sub s1, a4 - sltiu s6, ra, 913 - sll t3, s7, a3 - sub s9, s6, s5 - c.slli t4, 28 - sub s9, s6, s5 - c.slli t4, 28 - c.sub s1, a4 - rem s0, a3, a2 - slli s11, gp, 14 - c.lui a0, 24 - mul sp, s9, s11 - c.and a0, s0 - and a1, t3, a6 - rem s0, a3, a2 - and a1, t3, a6 - sltiu s6, ra, 913 - c.srli a0, 25 - sub s9, s6, s5 - sltiu s6, ra, 913 - mulh s11, s1, s9 - c.addi4spn a4, sp, 288 - xor t4, s3, t3 - srli s8, t6, 19 - div t3, t1, t5 - sra s1, t3, s1 - mulh s11, s1, s9 - c.addi s1, 6 - srli s8, t6, 19 - xor t4, s3, t3 - auipc t6, 688967 - srl a0, s2, a0 - slti tp, t6, 301 - c.andi a5, -1 - sltiu s6, ra, 913 - slli s11, gp, 14 - divu sp, ra, t0 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - xor t4, s3, t3 - srai s10, s1, 24 - c.addi4spn a4, sp, 288 - rem s0, a3, a2 - add s7, s5, a6 - c.li a7, 27 - c.xor a1, a2 - nop - mulh s11, s1, s9 - c.add t1, a1 - c.addi s1, 6 - add s7, s5, a6 - srl a0, s2, a0 - sltiu s6, ra, 913 - slli s11, gp, 14 - c.andi a5, -1 - auipc t6, 688967 - c.slli t4, 28 - lui zero, 195546 - c.andi a5, -1 - sltu t2, s1, t1 - c.mv a1, s5 - c.add t1, a1 - divu sp, ra, t0 - c.nop - c.add t1, a1 - andi s8, t1, -26 - c.srli a0, 25 - slt t1, a1, a4 - slli s11, gp, 14 - divu sp, ra, t0 - mul sp, s9, s11 - or s0, a2, a0 - c.nop - mulh s11, s1, s9 - sll t3, s7, a3 - sltiu s6, ra, 913 - c.slli t4, 28 - c.srli a0, 25 - sltiu s6, ra, 913 - slt t1, a1, a4 - c.add t1, a1 - c.add t1, a1 - srl a0, s2, a0 - remu s5, s11, t1 - slti tp, t6, 301 - mulhsu gp, a1, s1 - c.li a7, 27 - c.mv a1, s5 - c.addi4spn a4, sp, 288 - sra s1, t3, s1 - c.lui a0, 24 - sub s9, s6, s5 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - srli s8, t6, 19 - ori t5, t2, 999 - slli s11, gp, 14 - c.andi a5, -1 - c.addi16sp sp, 16 - xori a4, t0, 974 - mulhu tp, s3, a4 - c.addi s1, 6 - ori t5, t2, 999 - rem s0, a3, a2 - xor t4, s3, t3 - addi a7, t2, -784 - sll t3, s7, a3 - div t3, t1, t5 - addi a7, t2, -784 - c.srli a0, 25 - c.nop - add s7, s5, a6 - sra s1, t3, s1 - c.add t1, a1 - c.nop - c.addi16sp sp, 16 - xor t4, s3, t3 - slti tp, t6, 301 - c.or a5, a1 - c.lui a0, 24 - ori t5, t2, 999 - srli s8, t6, 19 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - srl a0, s2, a0 - c.mv a1, s5 - c.or a5, a1 - c.slli t4, 28 - c.add t1, a1 - srl a0, s2, a0 - andi s8, t1, -26 - remu s5, s11, t1 - mulh s11, s1, s9 - sltu t2, s1, t1 - nop - div t3, t1, t5 - mul sp, s9, s11 - c.lui a0, 24 - xor t4, s3, t3 - c.li a7, 27 - srai s10, s1, 24 - srl a0, s2, a0 - c.srai s0, 31 - nop - or s0, a2, a0 - mulhu tp, s3, a4 - sra s1, t3, s1 - andi s8, t1, -26 - mulh s11, s1, s9 - c.nop - div t3, t1, t5 - c.lui a0, 24 - c.addi s1, 6 - c.slli t4, 28 - c.addi16sp sp, 16 - sra s1, t3, s1 - c.slli t4, 28 - xori a4, t0, 974 - c.addi s1, 6 - c.or a5, a1 - mulhu tp, s3, a4 - divu sp, ra, t0 - c.andi a5, -1 - c.sub s1, a4 - mul sp, s9, s11 - slli s11, gp, 14 - xor t4, s3, t3 - srl a0, s2, a0 - c.slli t4, 28 - mulh s11, s1, s9 - div t3, t1, t5 - auipc t6, 688967 - slt t1, a1, a4 - rem s0, a3, a2 - c.sub s1, a4 - rem s0, a3, a2 - sltu t2, s1, t1 - c.nop - sltu t2, s1, t1 - c.xor a1, a2 - andi s8, t1, -26 - c.xor a1, a2 - c.addi16sp sp, 16 - c.mv a1, s5 - sltu t2, s1, t1 - c.or a5, a1 - c.addi16sp sp, 16 - sll t3, s7, a3 - addi a7, t2, -784 - sltiu s6, ra, 913 - xori a4, t0, 974 - c.andi a5, -1 - c.addi16sp sp, 16 - auipc t6, 688967 - c.addi16sp sp, 16 - c.srli a0, 25 - mulhsu gp, a1, s1 - slt t1, a1, a4 - sra s1, t3, s1 - li a5, 0x8e524495 #start riscv_int_numeric_corner_stream_31 - li t1, 0x5dd7b636 - li s5, 0x0 - li t0, 0xa0f522bd - li a4, 0xd3dab263 - li t5, 0x80000000 - li a6, 0x0 - li tp, 0xffffffff - li s8, 0xad0127b4 - li a0, 0x80000000 - add t0, a6, s8 - mulh t5, s5, s5 - rem a5, t0, a0 - divu t0, a0, s5 - mulhsu a5, tp, a6 - nop - nop - mulhsu a5, tp, a6 - lui tp, 195546 - addi a6, s5, 999 - lui tp, 195546 - sub a0, a6, t1 - add t0, a6, s8 - sub a0, a6, t1 - add t0, a6, s8 #end riscv_int_numeric_corner_stream_31 - and a1, t3, a6 - srl a0, s2, a0 - addi a7, t2, -784 - c.lui a0, 24 - c.li a7, 27 - c.addi s1, 6 - slli s11, gp, 14 - andi s8, t1, -26 - c.addi16sp sp, 16 - nop - mulh s11, s1, s9 - andi s8, t1, -26 - sub s9, s6, s5 - srai s10, s1, 24 - auipc t6, 688967 - c.addi4spn a4, sp, 288 - sll t3, s7, a3 - sltu t2, s1, t1 - c.srai s0, 31 - auipc t6, 688967 - c.nop - auipc t6, 688967 - sll t3, s7, a3 - slli s11, gp, 14 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - sra s1, t3, s1 - mulh s11, s1, s9 - c.addi16sp sp, 16 - addi a7, t2, -784 - slli s11, gp, 14 - c.mv a1, s5 - c.lui a0, 24 - mul sp, s9, s11 - lui zero, 195546 - add s7, s5, a6 - c.or a5, a1 - c.lui a0, 24 - c.li a7, 27 - li t4, 0xffffffff #start riscv_int_numeric_corner_stream_0 - li s3, 0x0 - li tp, 0x0 - li a1, 0x0 - li t1, 0x0 - li s10, 0x56c23892 - li s8, 0xffffffff - li a5, 0x0 - li s7, 0x0 - li s6, 0xffffffff - mulh s7, s7, t4 - addi t1, s6, 999 - sub t1, s8, t1 - lui tp, 195546 - rem s8, a5, a1 - nop - add t4, s10, s8 - nop - add t4, s10, s8 - div s3, s10, t1 - mul s3, s7, s8 - auipc t4, 688967 - lui tp, 195546 - nop - nop #end riscv_int_numeric_corner_stream_0 - slli s11, gp, 14 - c.or a5, a1 - remu s5, s11, t1 - and a1, t3, a6 - div t3, t1, t5 - mulh s11, s1, s9 - c.lui a0, 24 - and a1, t3, a6 - srli s8, t6, 19 - c.srli a0, 25 - nop - sub s9, s6, s5 - c.andi a5, -1 - xori a4, t0, 974 - lui zero, 195546 - c.andi a5, -1 - c.andi a5, -1 - c.addi s1, 6 - xori a4, t0, 974 - c.addi16sp sp, 16 - c.srai s0, 31 - c.andi a5, -1 - c.li a7, 27 - auipc t6, 688967 - mul sp, s9, s11 - c.and a0, s0 - srai s10, s1, 24 - or s0, a2, a0 - c.addi16sp sp, 16 - c.li a7, 27 - c.addi16sp sp, 16 - slt t1, a1, a4 - c.srai s0, 31 - c.lui a0, 24 - rem s0, a3, a2 - c.srli a0, 25 - c.addi4spn a4, sp, 288 - rem s0, a3, a2 - c.slli t4, 28 - xor t4, s3, t3 - mulhsu gp, a1, s1 - slli s11, gp, 14 - c.xor a1, a2 - div t3, t1, t5 - andi s8, t1, -26 - rem s0, a3, a2 - nop - div t3, t1, t5 - c.nop - mulhu tp, s3, a4 - c.slli t4, 28 - c.srai s0, 31 - c.and a0, s0 - srai s10, s1, 24 - xori a4, t0, 974 - c.andi a5, -1 - and a1, t3, a6 - c.slli t4, 28 - lui zero, 195546 - auipc t6, 688967 - c.srai s0, 31 - srai s10, s1, 24 - xori a4, t0, 974 - slli s11, gp, 14 - auipc t6, 688967 - mulh s11, s1, s9 - mul sp, s9, s11 - c.or a5, a1 - slt t1, a1, a4 - slli s11, gp, 14 - c.add t1, a1 - srl a0, s2, a0 - slti tp, t6, 301 - ori t5, t2, 999 - rem s0, a3, a2 - mulhsu gp, a1, s1 - c.srli a0, 25 - mul sp, s9, s11 - c.srli a0, 25 - c.slli t4, 28 - c.srai s0, 31 - c.srli a0, 25 - c.srai s0, 31 - slt t1, a1, a4 - c.srai s0, 31 - ori t5, t2, 999 - c.xor a1, a2 - c.xor a1, a2 - c.xor a1, a2 - auipc t6, 688967 - c.add t1, a1 - c.or a5, a1 - slti tp, t6, 301 - mul sp, s9, s11 - c.addi s1, 6 - nop - mulhu tp, s3, a4 - xor t4, s3, t3 - srl a0, s2, a0 - c.srai s0, 31 - c.mv a1, s5 - addi a7, t2, -784 - c.sub s1, a4 - slti tp, t6, 301 - sra s1, t3, s1 - c.sub s1, a4 - sltu t2, s1, t1 - div t3, t1, t5 - mulh s11, s1, s9 - add s7, s5, a6 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - srl a0, s2, a0 - mul sp, s9, s11 - c.xor a1, a2 - c.li a7, 27 - c.mv a1, s5 - sltiu s6, ra, 913 - sll t3, s7, a3 - xori a4, t0, 974 - sra s1, t3, s1 - xori a4, t0, 974 - mulhu tp, s3, a4 - nop - c.add t1, a1 - c.sub s1, a4 - div t3, t1, t5 - ori t5, t2, 999 - andi s8, t1, -26 - c.and a0, s0 - c.addi s1, 6 - sll t3, s7, a3 - div t3, t1, t5 - c.xor a1, a2 - srli s8, t6, 19 - xor t4, s3, t3 - sltiu s6, ra, 913 - addi a7, t2, -784 - lui zero, 195546 - c.add t1, a1 - slli s11, gp, 14 - mulhu tp, s3, a4 - c.and a0, s0 - sra s1, t3, s1 - lui zero, 195546 - c.and a0, s0 - mulh s11, s1, s9 - div t3, t1, t5 - mulh s11, s1, s9 - c.lui a0, 24 - c.xor a1, a2 - mulh s11, s1, s9 - auipc t6, 688967 - srai s10, s1, 24 - c.mv a1, s5 - c.nop - c.mv a1, s5 - div t3, t1, t5 - or s0, a2, a0 - c.add t1, a1 - addi a7, t2, -784 - div t3, t1, t5 - ori t5, t2, 999 - sra s1, t3, s1 - mul sp, s9, s11 - slli s11, gp, 14 - lui zero, 195546 - srli s8, t6, 19 - c.slli t4, 28 - c.srai s0, 31 - c.addi s1, 6 - c.addi4spn a4, sp, 288 - c.addi4spn a4, sp, 288 - srai s10, s1, 24 - or s0, a2, a0 - remu s5, s11, t1 - xor t4, s3, t3 - mulhsu gp, a1, s1 - c.add t1, a1 - xori a4, t0, 974 - sltu t2, s1, t1 - c.addi4spn a4, sp, 288 - slti tp, t6, 301 - div t3, t1, t5 - mulhu tp, s3, a4 - srai s10, s1, 24 - nop - c.slli t4, 28 - ori t5, t2, 999 - sub s9, s6, s5 - add s7, s5, a6 - c.xor a1, a2 - mul sp, s9, s11 - sltu t2, s1, t1 - slti tp, t6, 301 - xor t4, s3, t3 - c.slli t4, 28 - c.lui a0, 24 - auipc t6, 688967 - srl a0, s2, a0 - srli s8, t6, 19 - c.add t1, a1 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - div t3, t1, t5 - ori t5, t2, 999 - mulhu tp, s3, a4 - or s0, a2, a0 - div t3, t1, t5 - divu sp, ra, t0 - c.sub s1, a4 - c.or a5, a1 - c.addi4spn a4, sp, 288 - srl a0, s2, a0 - mulhu tp, s3, a4 - mulhsu gp, a1, s1 - mulhsu gp, a1, s1 - c.add t1, a1 - c.nop - rem s0, a3, a2 - lui zero, 195546 - slti tp, t6, 301 - lui zero, 195546 - c.lui a0, 24 - ori t5, t2, 999 - sub s9, s6, s5 - divu sp, ra, t0 - srl a0, s2, a0 - or s0, a2, a0 - c.xor a1, a2 - c.sub s1, a4 - sll t3, s7, a3 - c.addi s1, 6 - sub s9, s6, s5 - sltu t2, s1, t1 - c.xor a1, a2 - remu s5, s11, t1 - sra s1, t3, s1 - add s7, s5, a6 - c.and a0, s0 - c.sub s1, a4 - srli s8, t6, 19 - slt t1, a1, a4 - c.li a7, 27 - slti tp, t6, 301 - c.nop - sub s9, s6, s5 - ori t5, t2, 999 - c.addi16sp sp, 16 - xor t4, s3, t3 - srai s10, s1, 24 - c.sub s1, a4 - c.andi a5, -1 - c.lui a0, 24 - c.sub s1, a4 - c.addi s1, 6 - c.addi16sp sp, 16 - c.mv a1, s5 - lui zero, 195546 - ori t5, t2, 999 - mulhu tp, s3, a4 - c.mv a1, s5 - mulhsu gp, a1, s1 - slli s11, gp, 14 - or s0, a2, a0 - c.xor a1, a2 - slli s11, gp, 14 - c.slli t4, 28 - or s0, a2, a0 - srli s8, t6, 19 - rem s0, a3, a2 - sll t3, s7, a3 - ori t5, t2, 999 - c.or a5, a1 - srli s8, t6, 19 - add s7, s5, a6 - slt t1, a1, a4 - mul sp, s9, s11 - sltu t2, s1, t1 - andi s8, t1, -26 - srai s10, s1, 24 - lui zero, 195546 - or s0, a2, a0 - mulh s11, s1, s9 - andi s8, t1, -26 - c.slli t4, 28 - sub s9, s6, s5 - addi a7, t2, -784 - c.and a0, s0 - auipc t6, 688967 - c.addi s1, 6 - c.or a5, a1 - c.sub s1, a4 - mulhu tp, s3, a4 - mulhu tp, s3, a4 - lui zero, 195546 - c.lui a0, 24 - and a1, t3, a6 - mulhsu gp, a1, s1 - add s7, s5, a6 - c.li a7, 27 - mulhu tp, s3, a4 - c.mv a1, s5 - xor t4, s3, t3 - c.slli t4, 28 - slli s11, gp, 14 - c.addi s1, 6 - or s0, a2, a0 - c.srai s0, 31 - xor t4, s3, t3 - c.xor a1, a2 - lui zero, 195546 - xori a4, t0, 974 - c.srai s0, 31 - andi s8, t1, -26 - mul sp, s9, s11 - ori t5, t2, 999 - c.srli a0, 25 - div t3, t1, t5 - mul sp, s9, s11 - andi s8, t1, -26 - c.addi16sp sp, 16 - slt t1, a1, a4 - xori a4, t0, 974 - c.srli a0, 25 - mulh s11, s1, s9 - sll t3, s7, a3 - mulh s11, s1, s9 - add s7, s5, a6 - sra s1, t3, s1 - srl a0, s2, a0 - xori a4, t0, 974 - mulhu tp, s3, a4 - c.or a5, a1 - divu sp, ra, t0 - c.lui a0, 24 - slli s11, gp, 14 - c.li a7, 27 - sltu t2, s1, t1 - mulhu tp, s3, a4 - mulhsu gp, a1, s1 - div t3, t1, t5 - mul sp, s9, s11 - c.mv a1, s5 - c.addi16sp sp, 16 - div t3, t1, t5 - and a1, t3, a6 - lui zero, 195546 - xor t4, s3, t3 - sltiu s6, ra, 913 - c.mv a1, s5 - ori t5, t2, 999 - and a1, t3, a6 - sub s9, s6, s5 - srli s8, t6, 19 - c.li a7, 27 - c.slli t4, 28 - remu s5, s11, t1 - c.srai s0, 31 - divu sp, ra, t0 - c.lui a0, 24 - xor t4, s3, t3 - c.slli t4, 28 - mulhsu gp, a1, s1 - slli s11, gp, 14 - c.or a5, a1 - sltiu s6, ra, 913 - c.lui a0, 24 - nop - c.or a5, a1 - xor t4, s3, t3 - and a1, t3, a6 - srli s8, t6, 19 - c.add t1, a1 - srai s10, s1, 24 - sltu t2, s1, t1 - slli s11, gp, 14 - mulhu tp, s3, a4 - slt t1, a1, a4 - xori a4, t0, 974 - nop - sll t3, s7, a3 - lui zero, 195546 - c.sub s1, a4 - nop - sra s1, t3, s1 - c.srli a0, 25 - nop - lui zero, 195546 - c.nop - mulhsu gp, a1, s1 - c.mv a1, s5 - c.sub s1, a4 - sra s1, t3, s1 - slli s11, gp, 14 - c.nop - c.sub s1, a4 - mulhsu gp, a1, s1 - div t3, t1, t5 - c.andi a5, -1 - addi a7, t2, -784 - c.mv a1, s5 - lui zero, 195546 - div t3, t1, t5 - c.srli a0, 25 - c.or a5, a1 - mulh s11, s1, s9 - srli s8, t6, 19 - c.srai s0, 31 - lui zero, 195546 - addi a7, t2, -784 - c.sub s1, a4 - andi s8, t1, -26 - c.slli t4, 28 - sltu t2, s1, t1 - mul sp, s9, s11 - sub s9, s6, s5 - srl a0, s2, a0 - auipc t6, 688967 - c.or a5, a1 - mulh s11, s1, s9 - c.li a7, 27 - mulhu tp, s3, a4 - sltu t2, s1, t1 - c.andi a5, -1 - srai s10, s1, 24 - rem s0, a3, a2 - srli s8, t6, 19 - c.srli a0, 25 - sra s1, t3, s1 - xori a4, t0, 974 - ori t5, t2, 999 - c.li a7, 27 - auipc t6, 688967 - sltiu s6, ra, 913 - addi a7, t2, -784 - c.addi s1, 6 - sub s9, s6, s5 - slli s11, gp, 14 - c.nop - srl a0, s2, a0 - slli s11, gp, 14 - xori a4, t0, 974 - c.or a5, a1 - c.mv a1, s5 - xori a4, t0, 974 - sltu t2, s1, t1 - mulhu tp, s3, a4 - lui zero, 195546 - mulhu tp, s3, a4 - sltiu s6, ra, 913 - sub s9, s6, s5 - sll t3, s7, a3 - c.sub s1, a4 - sltiu s6, ra, 913 - mulhsu gp, a1, s1 - mul sp, s9, s11 - or s0, a2, a0 - c.xor a1, a2 - lui zero, 195546 - c.and a0, s0 - c.slli t4, 28 - sltiu s6, ra, 913 - c.addi4spn a4, sp, 288 - c.lui a0, 24 - slt t1, a1, a4 - sltu t2, s1, t1 - c.lui a0, 24 - sra s1, t3, s1 - andi s8, t1, -26 - sub s9, s6, s5 - c.mv a1, s5 - auipc t6, 688967 - sub s9, s6, s5 - c.sub s1, a4 - c.add t1, a1 - c.sub s1, a4 - rem s0, a3, a2 - slt t1, a1, a4 - mulhsu gp, a1, s1 - c.addi16sp sp, 16 - nop - slli s11, gp, 14 - c.srli a0, 25 - addi a7, t2, -784 - c.slli t4, 28 - srai s10, s1, 24 - c.lui a0, 24 - c.xor a1, a2 - mulhsu gp, a1, s1 - srli s8, t6, 19 - c.slli t4, 28 - c.addi s1, 6 - c.srai s0, 31 - slt t1, a1, a4 - c.lui a0, 24 - and a1, t3, a6 - rem s0, a3, a2 - nop - c.mv a1, s5 - nop - c.andi a5, -1 - rem s0, a3, a2 - c.andi a5, -1 - c.nop - xor t4, s3, t3 - c.addi4spn a4, sp, 288 - mulh s11, s1, s9 - divu sp, ra, t0 - c.and a0, s0 - c.srai s0, 31 - c.li a7, 27 - sra s1, t3, s1 - c.lui a0, 24 - mul sp, s9, s11 - addi a7, t2, -784 - c.mv a1, s5 - c.sub s1, a4 - lui zero, 195546 - c.or a5, a1 - c.lui a0, 24 - srl a0, s2, a0 - c.srli a0, 25 - c.mv a1, s5 - c.slli t4, 28 - c.lui a0, 24 - c.add t1, a1 - c.sub s1, a4 - srl a0, s2, a0 - or s0, a2, a0 - c.xor a1, a2 - nop - c.nop - andi s8, t1, -26 - add s7, s5, a6 - mulh s11, s1, s9 - ori t5, t2, 999 - or s0, a2, a0 - sub s9, s6, s5 - c.add t1, a1 - srli s8, t6, 19 - c.mv a1, s5 - add s7, s5, a6 - c.or a5, a1 - c.and a0, s0 - c.addi16sp sp, 16 - sub s9, s6, s5 - rem s0, a3, a2 - c.mv a1, s5 - c.sub s1, a4 - rem s0, a3, a2 - and a1, t3, a6 - c.sub s1, a4 - mulhu tp, s3, a4 - srai s10, s1, 24 - sltiu s6, ra, 913 - and a1, t3, a6 - and a1, t3, a6 - c.mv a1, s5 - srl a0, s2, a0 - srai s10, s1, 24 - mulhsu gp, a1, s1 - sub s9, s6, s5 - sra s1, t3, s1 - c.andi a5, -1 - addi a7, t2, -784 - xori a4, t0, 974 - c.li a7, 27 - c.and a0, s0 - sll t3, s7, a3 - nop - srai s10, s1, 24 - slli s11, gp, 14 - c.nop - srli s8, t6, 19 - c.addi16sp sp, 16 - addi a7, t2, -784 - mulhsu gp, a1, s1 - c.mv a1, s5 - and a1, t3, a6 - sub s9, s6, s5 - div t3, t1, t5 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - c.slli t4, 28 - c.and a0, s0 - and a1, t3, a6 - c.and a0, s0 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - and a1, t3, a6 - auipc t6, 688967 - addi a7, t2, -784 - c.mv a1, s5 - c.srai s0, 31 - mul sp, s9, s11 - ori t5, t2, 999 - sub s9, s6, s5 - and a1, t3, a6 - mulh s11, s1, s9 - c.and a0, s0 - c.addi s1, 6 - c.srli a0, 25 - c.addi4spn a4, sp, 288 - c.li a7, 27 - sltiu s6, ra, 913 - auipc t6, 688967 - mulhu tp, s3, a4 - c.add t1, a1 - and a1, t3, a6 - c.mv a1, s5 - div t3, t1, t5 - mulh s11, s1, s9 - c.xor a1, a2 - slti tp, t6, 301 - c.xor a1, a2 - c.mv a1, s5 - c.srli a0, 25 - mulh s11, s1, s9 - or s0, a2, a0 - add s7, s5, a6 - srli s8, t6, 19 - auipc t6, 688967 - c.xor a1, a2 - sltu t2, s1, t1 - srai s10, s1, 24 - c.slli t4, 28 - xor t4, s3, t3 - slti tp, t6, 301 - mulh s11, s1, s9 - c.li a7, 27 - slt t1, a1, a4 - auipc t6, 688967 - c.srai s0, 31 - c.srai s0, 31 - xor t4, s3, t3 - mul sp, s9, s11 - slt t1, a1, a4 - slt t1, a1, a4 - c.srli a0, 25 - rem s0, a3, a2 - mulh s11, s1, s9 - c.and a0, s0 - slt t1, a1, a4 - c.lui a0, 24 - c.xor a1, a2 - rem s0, a3, a2 - xor t4, s3, t3 - mul sp, s9, s11 - xori a4, t0, 974 - ori t5, t2, 999 - div t3, t1, t5 - sll t3, s7, a3 - sll t3, s7, a3 - c.addi16sp sp, 16 - sll t3, s7, a3 - slti tp, t6, 301 - div t3, t1, t5 - c.nop - xori a4, t0, 974 - c.andi a5, -1 - slti tp, t6, 301 - c.add t1, a1 - c.li a7, 27 - mulh s11, s1, s9 - c.xor a1, a2 - c.add t1, a1 - sub s9, s6, s5 - c.srli a0, 25 - rem s0, a3, a2 - xor t4, s3, t3 - slli s11, gp, 14 - c.addi16sp sp, 16 - or s0, a2, a0 - mulh s11, s1, s9 - remu s5, s11, t1 - c.add t1, a1 - slti tp, t6, 301 - c.addi16sp sp, 16 - c.srai s0, 31 - c.addi4spn a4, sp, 288 - nop - and a1, t3, a6 - or s0, a2, a0 - xor t4, s3, t3 - c.and a0, s0 - slt t1, a1, a4 - c.addi s1, 6 - c.add t1, a1 - c.addi s1, 6 - srai s10, s1, 24 - sub s9, s6, s5 - c.addi16sp sp, 16 - c.and a0, s0 - c.srli a0, 25 - addi a7, t2, -784 - srli s8, t6, 19 - rem s0, a3, a2 - c.addi s1, 6 - c.nop - c.xor a1, a2 - c.add t1, a1 - c.lui a0, 24 - slli s11, gp, 14 - mul sp, s9, s11 - mulh s11, s1, s9 - sll t3, s7, a3 - c.andi a5, -1 - c.mv a1, s5 - remu s5, s11, t1 - c.addi s1, 6 - rem s0, a3, a2 - addi a7, t2, -784 - sltu t2, s1, t1 - slli s11, gp, 14 - sll t3, s7, a3 - c.srli a0, 25 - c.addi s1, 6 - rem s0, a3, a2 - div t3, t1, t5 - mulhu tp, s3, a4 - c.xor a1, a2 - c.mv a1, s5 - c.lui a0, 24 - c.and a0, s0 - srli s8, t6, 19 - c.nop - mulhu tp, s3, a4 - c.srai s0, 31 - c.addi4spn a4, sp, 288 - nop - and a1, t3, a6 - and a1, t3, a6 - add s7, s5, a6 - sll t3, s7, a3 - xori a4, t0, 974 - andi s8, t1, -26 - lui zero, 195546 - c.mv a1, s5 - and a1, t3, a6 - div t3, t1, t5 - xori a4, t0, 974 - c.mv a1, s5 - sll t3, s7, a3 - and a1, t3, a6 - c.li a7, 27 - c.xor a1, a2 - slt t1, a1, a4 - c.nop - c.slli t4, 28 - lui zero, 195546 - remu s5, s11, t1 - c.andi a5, -1 - remu s5, s11, t1 - srli s8, t6, 19 - c.addi4spn a4, sp, 288 - xori a4, t0, 974 - slli s11, gp, 14 - mulh s11, s1, s9 - c.add t1, a1 - c.addi16sp sp, 16 - c.addi4spn a4, sp, 288 - c.lui a0, 24 - c.srli a0, 25 - add s7, s5, a6 - and a1, t3, a6 - c.addi s1, 6 - c.srai s0, 31 - mulhsu gp, a1, s1 - lui zero, 195546 - add s7, s5, a6 - mul sp, s9, s11 - addi a7, t2, -784 - mulhsu gp, a1, s1 - divu sp, ra, t0 - c.srli a0, 25 - c.slli t4, 28 - andi s8, t1, -26 - div t3, t1, t5 - xor t4, s3, t3 - c.li a7, 27 - auipc t6, 688967 - mulhsu gp, a1, s1 - slt t1, a1, a4 - slti tp, t6, 301 - c.li a7, 27 - andi s8, t1, -26 - ori t5, t2, 999 - mulh s11, s1, s9 - remu s5, s11, t1 - slt t1, a1, a4 - ori t5, t2, 999 - ori t5, t2, 999 - c.sub s1, a4 - sra s1, t3, s1 - srai s10, s1, 24 - add s7, s5, a6 - mul sp, s9, s11 - srl a0, s2, a0 - andi s8, t1, -26 - c.mv a1, s5 - c.nop - c.srai s0, 31 - sltu t2, s1, t1 - c.add t1, a1 - srl a0, s2, a0 - slti tp, t6, 301 - slti tp, t6, 301 - nop - and a1, t3, a6 - mulh s11, s1, s9 - lui zero, 195546 - rem s0, a3, a2 - addi a7, t2, -784 - c.addi s1, 6 - slt t1, a1, a4 - mulh s11, s1, s9 - c.addi s1, 6 - divu sp, ra, t0 - sll t3, s7, a3 - c.lui a0, 24 - slli s11, gp, 14 - c.and a0, s0 - li s7, 0x5c21e8c4 #start riscv_int_numeric_corner_stream_21 - li s11, 0x0 - li a1, 0x0 - li t6, 0x69666040 - li a0, 0x0 - li s3, 0x991745b6 - li tp, 0xce51867e - li a4, 0xffffffff - li sp, 0x5a409975 - li t4, 0xbacb45ac - rem a0, tp, a0 - auipc t6, 688967 - sub tp, t4, tp - nop - div a0, a1, a0 - lui tp, 195546 - mulhsu a0, s11, a0 - nop - addi tp, s7, 999 - mulhsu a0, s11, a0 - mulhu tp, tp, tp - mulhsu a0, s11, a0 - lui tp, 195546 - divu tp, sp, t4 - nop #end riscv_int_numeric_corner_stream_21 - slti tp, t6, 301 - rem s0, a3, a2 - andi s8, t1, -26 - slli s11, gp, 14 - c.mv a1, s5 - andi s8, t1, -26 - mulhsu gp, a1, s1 - ori t5, t2, 999 - nop - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - c.xor a1, a2 - auipc t6, 688967 - slti tp, t6, 301 - c.andi a5, -1 - sra s1, t3, s1 - mul sp, s9, s11 - c.and a0, s0 - c.and a0, s0 - c.li a7, 27 - sub s9, s6, s5 - c.or a5, a1 - auipc t6, 688967 - c.xor a1, a2 - or s0, a2, a0 - li t5, 0xe86da700 #start riscv_int_numeric_corner_stream_15 - li s9, 0x80000000 - li a4, 0xffffffff - li s5, 0xffffffff - li s1, 0x80000000 - li s11, 0xf4dea5f0 - li t4, 0x0 - li s6, 0x4819fc5a - li t2, 0xffffffff - li s0, 0x0 - nop - auipc t5, 688967 - nop - add s11, a4, s9 - add s11, a4, s9 - nop - div s0, s0, a4 - auipc t5, 688967 - addi s5, s5, 999 - div s0, s0, a4 - nop - addi s5, s5, 999 - addi s5, s5, 999 - auipc t5, 688967 - mulhsu t5, s0, s0 - mul a4, t4, t5 - mul a4, t4, t5 - addi s5, s5, 999 - lui s0, 195546 #end riscv_int_numeric_corner_stream_15 - mulhsu gp, a1, s1 - remu s5, s11, t1 - sltiu s6, ra, 913 - nop - sltu t2, s1, t1 - c.nop - sll t3, s7, a3 - c.mv a1, s5 - add s7, s5, a6 - and a1, t3, a6 - mulh s11, s1, s9 - sltiu s6, ra, 913 - div t3, t1, t5 - lui zero, 195546 - nop - c.and a0, s0 - c.srli a0, 25 - srl a0, s2, a0 - remu s5, s11, t1 - sra s1, t3, s1 - c.sub s1, a4 - c.nop - slli s11, gp, 14 - mulhu tp, s3, a4 - c.addi s1, 6 - mulhu tp, s3, a4 - c.addi4spn a4, sp, 288 - xori a4, t0, 974 - c.lui a0, 24 - srai s10, s1, 24 - xori a4, t0, 974 - mul sp, s9, s11 - sltiu s6, ra, 913 - mulhsu gp, a1, s1 - c.nop - rem s0, a3, a2 - sltiu s6, ra, 913 - mulhsu gp, a1, s1 - c.li a7, 27 - addi a7, t2, -784 - c.mv a1, s5 - c.addi4spn a4, sp, 288 - c.or a5, a1 - slt t1, a1, a4 - addi a7, t2, -784 - lui zero, 195546 - c.slli t4, 28 - div t3, t1, t5 - or s0, a2, a0 - and a1, t3, a6 - c.mv a1, s5 - andi s8, t1, -26 - mulhu tp, s3, a4 - c.addi s1, 6 - sll t3, s7, a3 - c.slli t4, 28 - add s7, s5, a6 - nop - or s0, a2, a0 - rem s0, a3, a2 - sltiu s6, ra, 913 - c.add t1, a1 - div t3, t1, t5 - and a1, t3, a6 - sll t3, s7, a3 - c.xor a1, a2 - c.nop - c.nop - c.nop - c.slli t4, 28 - slti tp, t6, 301 - mulhsu gp, a1, s1 - sltu t2, s1, t1 - sltu t2, s1, t1 - c.andi a5, -1 - c.srli a0, 25 - srl a0, s2, a0 - nop - c.srai s0, 31 - sll t3, s7, a3 - and a1, t3, a6 - remu s5, s11, t1 - sra s1, t3, s1 - slli s11, gp, 14 - or s0, a2, a0 - sltiu s6, ra, 913 - c.add t1, a1 - rem s0, a3, a2 - slti tp, t6, 301 - add s7, s5, a6 - srli s8, t6, 19 - c.srli a0, 25 - sll t3, s7, a3 - divu sp, ra, t0 - rem s0, a3, a2 - srl a0, s2, a0 - slt t1, a1, a4 - divu sp, ra, t0 - srli s8, t6, 19 - c.li a7, 27 - ori t5, t2, 999 - c.addi s1, 6 - c.and a0, s0 - remu s5, s11, t1 - c.addi s1, 6 - xori a4, t0, 974 - ori t5, t2, 999 - srl a0, s2, a0 - lui zero, 195546 - srai s10, s1, 24 - ori t5, t2, 999 - rem s0, a3, a2 - c.nop - c.and a0, s0 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - c.xor a1, a2 - ori t5, t2, 999 - slli s11, gp, 14 - c.srli a0, 25 - xor t4, s3, t3 - sltiu s6, ra, 913 - xori a4, t0, 974 - c.xor a1, a2 - and a1, t3, a6 - nop - c.or a5, a1 - c.and a0, s0 - mulhsu gp, a1, s1 - addi a7, t2, -784 - sra s1, t3, s1 - c.add t1, a1 - c.mv a1, s5 - mulhsu gp, a1, s1 - sll t3, s7, a3 - srai s10, s1, 24 - remu s5, s11, t1 - rem s0, a3, a2 - divu sp, ra, t0 - c.li a7, 27 - slt t1, a1, a4 - c.lui a0, 24 - srli s8, t6, 19 - sll t3, s7, a3 - srai s10, s1, 24 - slti tp, t6, 301 - c.sub s1, a4 - c.srli a0, 25 - c.srai s0, 31 - mulhsu gp, a1, s1 - sltu t2, s1, t1 - c.addi4spn a4, sp, 288 - c.or a5, a1 - c.lui a0, 24 - srli s8, t6, 19 - c.addi4spn a4, sp, 288 - srai s10, s1, 24 - c.addi16sp sp, 16 - c.mv a1, s5 - or s0, a2, a0 - add s7, s5, a6 - remu s5, s11, t1 - sll t3, s7, a3 - c.lui a0, 24 - c.andi a5, -1 - mul sp, s9, s11 - sub s9, s6, s5 - add s7, s5, a6 - c.addi16sp sp, 16 - xor t4, s3, t3 - sltu t2, s1, t1 - divu sp, ra, t0 - nop - c.addi s1, 6 - c.mv a1, s5 - lui zero, 195546 - mulh s11, s1, s9 - remu s5, s11, t1 - c.xor a1, a2 - sra s1, t3, s1 - xor t4, s3, t3 - c.lui a0, 24 - sll t3, s7, a3 - c.addi16sp sp, 16 - sra s1, t3, s1 - c.andi a5, -1 - slti tp, t6, 301 - and a1, t3, a6 - sub s9, s6, s5 - c.addi4spn a4, sp, 288 - c.and a0, s0 - c.addi s1, 6 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - c.nop - c.andi a5, -1 - addi a7, t2, -784 - sltu t2, s1, t1 - c.srai s0, 31 - remu s5, s11, t1 - sltiu s6, ra, 913 - c.add t1, a1 - ori t5, t2, 999 - xor t4, s3, t3 - xori a4, t0, 974 - sra s1, t3, s1 - c.srli a0, 25 - mulhsu gp, a1, s1 - c.slli t4, 28 - c.addi4spn a4, sp, 288 - srl a0, s2, a0 - div t3, t1, t5 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - sltu t2, s1, t1 - mulhsu gp, a1, s1 - slti tp, t6, 301 - c.lui a0, 24 - xor t4, s3, t3 - c.xor a1, a2 - c.li a7, 27 - div t3, t1, t5 - c.slli t4, 28 - c.li a7, 27 - c.add t1, a1 - c.xor a1, a2 - rem s0, a3, a2 - rem s0, a3, a2 - c.and a0, s0 - mulhu tp, s3, a4 - c.addi16sp sp, 16 - nop - or s0, a2, a0 - mulh s11, s1, s9 - c.srli a0, 25 - srai s10, s1, 24 - ori t5, t2, 999 - sub s9, s6, s5 - c.nop - mul sp, s9, s11 - andi s8, t1, -26 - c.add t1, a1 - sll t3, s7, a3 - c.sub s1, a4 - ori t5, t2, 999 - c.sub s1, a4 - add s7, s5, a6 - c.addi s1, 6 - and a1, t3, a6 - mulh s11, s1, s9 - srli s8, t6, 19 - c.or a5, a1 - srai s10, s1, 24 - remu s5, s11, t1 - c.andi a5, -1 - srli s8, t6, 19 - add s7, s5, a6 - sll t3, s7, a3 - sltu t2, s1, t1 - c.andi a5, -1 - c.or a5, a1 - c.and a0, s0 - xor t4, s3, t3 - c.addi16sp sp, 16 - add s7, s5, a6 - remu s5, s11, t1 - c.sub s1, a4 - c.sub s1, a4 - sltiu s6, ra, 913 - remu s5, s11, t1 - c.andi a5, -1 - c.and a0, s0 - slli s11, gp, 14 - c.addi16sp sp, 16 - c.mv a1, s5 - ori t5, t2, 999 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - c.xor a1, a2 - srai s10, s1, 24 - and a1, t3, a6 - sltiu s6, ra, 913 - c.li a7, 27 - rem s0, a3, a2 - c.srli a0, 25 - divu sp, ra, t0 - slli s11, gp, 14 - or s0, a2, a0 - lui zero, 195546 - c.sub s1, a4 - xor t4, s3, t3 - slti tp, t6, 301 - c.addi16sp sp, 16 - c.add t1, a1 - mulh s11, s1, s9 - srai s10, s1, 24 - slti tp, t6, 301 - remu s5, s11, t1 - nop - sll t3, s7, a3 - nop - ori t5, t2, 999 - c.add t1, a1 - mul sp, s9, s11 - c.sub s1, a4 - c.srai s0, 31 - auipc t6, 688967 - mulhsu gp, a1, s1 - div t3, t1, t5 - add s7, s5, a6 - srl a0, s2, a0 - c.mv a1, s5 - addi a7, t2, -784 - mulhsu gp, a1, s1 - c.mv a1, s5 - mulhsu gp, a1, s1 - c.or a5, a1 - mulhu tp, s3, a4 - slt t1, a1, a4 - slti tp, t6, 301 - slli s11, gp, 14 - or s0, a2, a0 - slt t1, a1, a4 - sltiu s6, ra, 913 - c.li a7, 27 - add s7, s5, a6 - srli s8, t6, 19 - xori a4, t0, 974 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - slt t1, a1, a4 - c.addi s1, 6 - auipc t6, 688967 - sltu t2, s1, t1 - mulhu tp, s3, a4 - sltiu s6, ra, 913 - sub s9, s6, s5 - sll t3, s7, a3 - c.xor a1, a2 - slli s11, gp, 14 - c.srli a0, 25 - slti tp, t6, 301 - rem s0, a3, a2 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - nop - add s7, s5, a6 - rem s0, a3, a2 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - andi s8, t1, -26 - mulhsu gp, a1, s1 - c.or a5, a1 - add s7, s5, a6 - div t3, t1, t5 - c.nop - mulhsu gp, a1, s1 - remu s5, s11, t1 - c.addi4spn a4, sp, 288 - mulhu tp, s3, a4 - c.nop - addi a7, t2, -784 - c.sub s1, a4 - rem s0, a3, a2 - c.slli t4, 28 - c.sub s1, a4 - slti tp, t6, 301 - sltiu s6, ra, 913 - c.or a5, a1 - mul sp, s9, s11 - c.andi a5, -1 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - c.andi a5, -1 - or s0, a2, a0 - c.add t1, a1 - mulh s11, s1, s9 - andi s8, t1, -26 - c.andi a5, -1 - c.mv a1, s5 - addi a7, t2, -784 - slli s11, gp, 14 - c.xor a1, a2 - sltiu s6, ra, 913 - c.slli t4, 28 - or s0, a2, a0 - auipc t6, 688967 - srl a0, s2, a0 - c.add t1, a1 - c.addi s1, 6 - remu s5, s11, t1 - c.addi s1, 6 - c.mv a1, s5 - ori t5, t2, 999 - c.andi a5, -1 - srl a0, s2, a0 - srl a0, s2, a0 - div t3, t1, t5 - srai s10, s1, 24 - c.xor a1, a2 - divu sp, ra, t0 - div t3, t1, t5 - lui zero, 195546 - c.xor a1, a2 - c.addi s1, 6 - ori t5, t2, 999 - c.lui a0, 24 - srai s10, s1, 24 - lui zero, 195546 - xori a4, t0, 974 - sltu t2, s1, t1 - c.li a7, 27 - c.sub s1, a4 - c.and a0, s0 - c.addi s1, 6 - xori a4, t0, 974 - c.srli a0, 25 - c.lui a0, 24 - c.addi s1, 6 - c.andi a5, -1 - c.mv a1, s5 - c.addi s1, 6 - srai s10, s1, 24 - srai s10, s1, 24 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - c.and a0, s0 - mulh s11, s1, s9 - andi s8, t1, -26 - lui zero, 195546 - remu s5, s11, t1 - lui zero, 195546 - xori a4, t0, 974 - c.slli t4, 28 - add s7, s5, a6 - andi s8, t1, -26 - c.xor a1, a2 - slli s11, gp, 14 - xori a4, t0, 974 - sra s1, t3, s1 - mulh s11, s1, s9 - c.mv a1, s5 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - srl a0, s2, a0 - mulhsu gp, a1, s1 - divu sp, ra, t0 - xor t4, s3, t3 - sltiu s6, ra, 913 - c.sub s1, a4 - rem s0, a3, a2 - sra s1, t3, s1 - c.xor a1, a2 - or s0, a2, a0 - sltiu s6, ra, 913 - addi a7, t2, -784 - c.srli a0, 25 - c.nop - sll t3, s7, a3 - c.li a7, 27 - or s0, a2, a0 - srli s8, t6, 19 - sltiu s6, ra, 913 - sltu t2, s1, t1 - sll t3, s7, a3 - auipc t6, 688967 - mul sp, s9, s11 - sltu t2, s1, t1 - c.andi a5, -1 - srli s8, t6, 19 - nop - srai s10, s1, 24 - xor t4, s3, t3 - c.or a5, a1 - sra s1, t3, s1 - slti tp, t6, 301 - c.srli a0, 25 - remu s5, s11, t1 - add s7, s5, a6 - or s0, a2, a0 - auipc t6, 688967 - xori a4, t0, 974 - divu sp, ra, t0 - mulhu tp, s3, a4 - slli s11, gp, 14 - c.srli a0, 25 - srl a0, s2, a0 - c.xor a1, a2 - mul sp, s9, s11 - srai s10, s1, 24 - srli s8, t6, 19 - mulhu tp, s3, a4 - c.slli t4, 28 - nop - c.or a5, a1 - c.li a7, 27 - c.addi s1, 6 - c.nop - sltiu s6, ra, 913 - mulhu tp, s3, a4 - c.sub s1, a4 - c.lui a0, 24 - c.addi16sp sp, 16 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - xor t4, s3, t3 - slti tp, t6, 301 - and a1, t3, a6 - auipc t6, 688967 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - slt t1, a1, a4 - c.addi s1, 6 - mul sp, s9, s11 - sub s9, s6, s5 - c.srai s0, 31 - mul sp, s9, s11 - sltiu s6, ra, 913 - remu s5, s11, t1 - mulh s11, s1, s9 - c.srai s0, 31 - c.addi s1, 6 - mulhsu gp, a1, s1 - srai s10, s1, 24 - remu s5, s11, t1 - sra s1, t3, s1 - c.xor a1, a2 - c.xor a1, a2 - sltu t2, s1, t1 - sltiu s6, ra, 913 - sra s1, t3, s1 - c.li a7, 27 - sub s9, s6, s5 - xor t4, s3, t3 - c.lui a0, 24 - c.and a0, s0 - c.addi16sp sp, 16 - xori a4, t0, 974 - c.addi16sp sp, 16 - slli s11, gp, 14 - slti tp, t6, 301 - c.addi16sp sp, 16 - c.lui a0, 24 - and a1, t3, a6 - lui zero, 195546 - lui zero, 195546 - remu s5, s11, t1 - mul sp, s9, s11 - c.addi s1, 6 - c.addi4spn a4, sp, 288 - c.nop - c.xor a1, a2 - c.li a7, 27 - sltu t2, s1, t1 - xor t4, s3, t3 - c.sub s1, a4 - c.nop - auipc t6, 688967 - remu s5, s11, t1 - srl a0, s2, a0 - c.srai s0, 31 - c.nop - lui zero, 195546 - xor t4, s3, t3 - sub s9, s6, s5 - c.li a7, 27 - sltiu s6, ra, 913 - sub s9, s6, s5 - mulhu tp, s3, a4 - sll t3, s7, a3 - sra s1, t3, s1 - and a1, t3, a6 - sra s1, t3, s1 - add s7, s5, a6 - c.andi a5, -1 - or s0, a2, a0 - c.slli t4, 28 - c.and a0, s0 - mulh s11, s1, s9 - c.sub s1, a4 - c.andi a5, -1 - xor t4, s3, t3 - remu s5, s11, t1 - c.or a5, a1 - andi s8, t1, -26 - slt t1, a1, a4 - srai s10, s1, 24 - auipc t6, 688967 - div t3, t1, t5 - mulhsu gp, a1, s1 - and a1, t3, a6 - c.and a0, s0 - rem s0, a3, a2 - remu s5, s11, t1 - mulh s11, s1, s9 - auipc t6, 688967 - mulh s11, s1, s9 - divu sp, ra, t0 - mulhsu gp, a1, s1 - slt t1, a1, a4 - sltiu s6, ra, 913 - ori t5, t2, 999 - c.nop - mulh s11, s1, s9 - or s0, a2, a0 - xori a4, t0, 974 - slli s11, gp, 14 - mulhsu gp, a1, s1 - c.lui a0, 24 - c.nop - xor t4, s3, t3 - mulhsu gp, a1, s1 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - c.and a0, s0 - andi s8, t1, -26 - add s7, s5, a6 - auipc t6, 688967 - sltiu s6, ra, 913 - andi s8, t1, -26 - divu sp, ra, t0 - c.nop - c.nop - div t3, t1, t5 - c.sub s1, a4 - andi s8, t1, -26 - ori t5, t2, 999 - xor t4, s3, t3 - c.lui a0, 24 - sltu t2, s1, t1 - c.srai s0, 31 - c.lui a0, 24 - c.addi s1, 6 - rem s0, a3, a2 - srli s8, t6, 19 - slt t1, a1, a4 - and a1, t3, a6 - auipc t6, 688967 - c.and a0, s0 - srli s8, t6, 19 - add s7, s5, a6 - c.andi a5, -1 - c.srli a0, 25 - sll t3, s7, a3 - c.li a7, 27 - c.andi a5, -1 - lui zero, 195546 - c.lui a0, 24 - sub s9, s6, s5 - srl a0, s2, a0 - mul sp, s9, s11 - and a1, t3, a6 - c.srai s0, 31 - c.addi16sp sp, 16 - c.andi a5, -1 - andi s8, t1, -26 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - c.or a5, a1 - nop - c.sub s1, a4 - sll t3, s7, a3 - c.lui a0, 24 - sll t3, s7, a3 - c.andi a5, -1 - sll t3, s7, a3 - c.add t1, a1 - add s7, s5, a6 - srai s10, s1, 24 - xor t4, s3, t3 - c.nop - auipc t6, 688967 - c.andi a5, -1 - c.srli a0, 25 - c.srli a0, 25 - xori a4, t0, 974 - c.li a7, 27 - xor t4, s3, t3 - sra s1, t3, s1 - nop - c.addi s1, 6 - srai s10, s1, 24 - xor t4, s3, t3 - c.xor a1, a2 - c.and a0, s0 - lui zero, 195546 - c.li a7, 27 - mulhu tp, s3, a4 - c.srai s0, 31 - c.lui a0, 24 - sub s9, s6, s5 - xor t4, s3, t3 - addi a7, t2, -784 - c.lui a0, 24 - c.srli a0, 25 - c.and a0, s0 - c.addi s1, 6 - xor t4, s3, t3 - c.xor a1, a2 - auipc t6, 688967 - c.addi s1, 6 - mul sp, s9, s11 - ori t5, t2, 999 - c.addi s1, 6 - or s0, a2, a0 - c.addi16sp sp, 16 - c.srli a0, 25 - c.lui a0, 24 - mul sp, s9, s11 - ori t5, t2, 999 - c.or a5, a1 - c.mv a1, s5 - div t3, t1, t5 - c.srai s0, 31 - mulhsu gp, a1, s1 - c.andi a5, -1 - c.li a7, 27 - div t3, t1, t5 - xor t4, s3, t3 - sltiu s6, ra, 913 - c.sub s1, a4 - sll t3, s7, a3 - mulhsu gp, a1, s1 - ori t5, t2, 999 - srli s8, t6, 19 - remu s5, s11, t1 - sltu t2, s1, t1 - c.srai s0, 31 - c.nop - c.li a7, 27 - mul sp, s9, s11 - sltu t2, s1, t1 - slt t1, a1, a4 - c.li a7, 27 - rem s0, a3, a2 - c.or a5, a1 - c.slli t4, 28 - srl a0, s2, a0 - remu s5, s11, t1 - lui zero, 195546 - auipc t6, 688967 - c.mv a1, s5 - ori t5, t2, 999 - rem s0, a3, a2 - sub s9, s6, s5 - divu sp, ra, t0 - andi s8, t1, -26 - and a1, t3, a6 - srl a0, s2, a0 - div t3, t1, t5 - li s8, 0xffffffff #start riscv_int_numeric_corner_stream_18 - li a1, 0xffffffff - li t2, 0xc2599e47 - li s7, 0xf8b0bfea - li a6, 0x0 - li t5, 0xffffffff - li t6, 0x71c3cd1f - li s6, 0x80000000 - li t3, 0x80000000 - li s0, 0x0 - auipc t6, 688967 - remu s7, t2, s0 - add a1, t3, t3 - add a1, t3, t3 - mul s7, s0, s8 - div a6, s8, s6 - auipc t6, 688967 - remu s7, t2, s0 - sub t2, s0, t3 - lui s0, 195546 - mulh s7, s7, t3 - auipc t6, 688967 - addi s0, t2, 999 - remu s7, t2, s0 - mul s7, s0, s8 #end riscv_int_numeric_corner_stream_18 - auipc t6, 688967 - slt t1, a1, a4 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - slti tp, t6, 301 - slli s11, gp, 14 - mulhu tp, s3, a4 - xori a4, t0, 974 - c.addi4spn a4, sp, 288 - remu s5, s11, t1 - c.xor a1, a2 - div t3, t1, t5 - c.mv a1, s5 - auipc t6, 688967 - c.or a5, a1 - srl a0, s2, a0 - c.lui a0, 24 - slti tp, t6, 301 - divu sp, ra, t0 - div t3, t1, t5 - c.andi a5, -1 - c.xor a1, a2 - c.sub s1, a4 - mulhsu gp, a1, s1 - xor t4, s3, t3 - and a1, t3, a6 - c.addi16sp sp, 16 - sra s1, t3, s1 - slt t1, a1, a4 - mulhsu gp, a1, s1 - srai s10, s1, 24 - mulhsu gp, a1, s1 - nop - mulhsu gp, a1, s1 - add s7, s5, a6 - c.addi16sp sp, 16 - ori t5, t2, 999 - auipc t6, 688967 - addi a7, t2, -784 - lui zero, 195546 - and a1, t3, a6 - c.add t1, a1 - ori t5, t2, 999 - c.mv a1, s5 - c.srai s0, 31 - sll t3, s7, a3 - c.addi16sp sp, 16 - mul sp, s9, s11 - rem s0, a3, a2 - c.or a5, a1 - xori a4, t0, 974 - div t3, t1, t5 - mulhu tp, s3, a4 - div t3, t1, t5 - mulh s11, s1, s9 - c.mv a1, s5 - mulhsu gp, a1, s1 - c.and a0, s0 - add s7, s5, a6 - c.addi s1, 6 - c.mv a1, s5 - c.slli t4, 28 - sltiu s6, ra, 913 - add s7, s5, a6 - c.nop - auipc t6, 688967 - c.srai s0, 31 - srli s8, t6, 19 - c.srli a0, 25 - c.addi16sp sp, 16 - c.slli t4, 28 - nop - nop - c.add t1, a1 - srli s8, t6, 19 - c.slli t4, 28 - c.srai s0, 31 - xor t4, s3, t3 - c.addi s1, 6 - lui zero, 195546 - andi s8, t1, -26 - mul sp, s9, s11 - c.and a0, s0 - c.srli a0, 25 - mulhu tp, s3, a4 - c.addi16sp sp, 16 - lui zero, 195546 - c.xor a1, a2 - c.addi s1, 6 - c.addi s1, 6 - divu sp, ra, t0 - divu sp, ra, t0 - c.srai s0, 31 - slli s11, gp, 14 - c.xor a1, a2 - c.and a0, s0 - slt t1, a1, a4 - c.mv a1, s5 - c.and a0, s0 - c.nop - c.li a7, 27 - mulhu tp, s3, a4 - c.and a0, s0 - c.srli a0, 25 - sra s1, t3, s1 - xor t4, s3, t3 - c.add t1, a1 - srli s8, t6, 19 - slli s11, gp, 14 - c.and a0, s0 - c.addi4spn a4, sp, 288 - srai s10, s1, 24 - and a1, t3, a6 - c.andi a5, -1 - srli s8, t6, 19 - div t3, t1, t5 - ori t5, t2, 999 - andi s8, t1, -26 - c.and a0, s0 - add s7, s5, a6 - div t3, t1, t5 - srai s10, s1, 24 - mulh s11, s1, s9 - mulh s11, s1, s9 - c.xor a1, a2 - c.addi16sp sp, 16 - c.slli t4, 28 - srai s10, s1, 24 - mulh s11, s1, s9 - sll t3, s7, a3 - c.xor a1, a2 - rem s0, a3, a2 - auipc t6, 688967 - srai s10, s1, 24 - c.add t1, a1 - remu s5, s11, t1 - c.slli t4, 28 - c.sub s1, a4 - c.lui a0, 24 - and a1, t3, a6 - c.addi4spn a4, sp, 288 - c.srli a0, 25 - ori t5, t2, 999 - slli s11, gp, 14 - sra s1, t3, s1 - c.lui a0, 24 - auipc t6, 688967 - c.or a5, a1 - slli s11, gp, 14 - c.addi16sp sp, 16 - sub s9, s6, s5 - mulhsu gp, a1, s1 - ori t5, t2, 999 - c.add t1, a1 - remu s5, s11, t1 - srai s10, s1, 24 - c.mv a1, s5 - sub s9, s6, s5 - mulhu tp, s3, a4 - auipc t6, 688967 - nop - srai s10, s1, 24 - c.andi a5, -1 - ori t5, t2, 999 - slli s11, gp, 14 - c.li a7, 27 - c.li a7, 27 - xor t4, s3, t3 - srli s8, t6, 19 - lui zero, 195546 - c.and a0, s0 - srai s10, s1, 24 - add s7, s5, a6 - mulh s11, s1, s9 - c.mv a1, s5 - divu sp, ra, t0 - c.sub s1, a4 - c.slli t4, 28 - sra s1, t3, s1 - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - and a1, t3, a6 - srai s10, s1, 24 - lui zero, 195546 - c.srai s0, 31 - nop - sll t3, s7, a3 - c.addi4spn a4, sp, 288 - mulhu tp, s3, a4 - srli s8, t6, 19 - sltiu s6, ra, 913 - c.nop - ori t5, t2, 999 - div t3, t1, t5 - srl a0, s2, a0 - c.and a0, s0 - sra s1, t3, s1 - c.add t1, a1 - sltu t2, s1, t1 - remu s5, s11, t1 - c.slli t4, 28 - sra s1, t3, s1 - mulhsu gp, a1, s1 - sra s1, t3, s1 - c.addi16sp sp, 16 - c.mv a1, s5 - c.addi s1, 6 - xor t4, s3, t3 - mulhu tp, s3, a4 - rem s0, a3, a2 - c.addi16sp sp, 16 - lui zero, 195546 - c.addi16sp sp, 16 - lui zero, 195546 - rem s0, a3, a2 - mulh s11, s1, s9 - xor t4, s3, t3 - c.or a5, a1 - c.lui a0, 24 - sub s9, s6, s5 - rem s0, a3, a2 - mulh s11, s1, s9 - srli s8, t6, 19 - c.addi16sp sp, 16 - mulh s11, s1, s9 - c.nop - c.srli a0, 25 - remu s5, s11, t1 - c.addi s1, 6 - andi s8, t1, -26 - slt t1, a1, a4 - remu s5, s11, t1 - or s0, a2, a0 - srai s10, s1, 24 - ori t5, t2, 999 - slti tp, t6, 301 - slti tp, t6, 301 - c.srli a0, 25 - sltiu s6, ra, 913 - c.nop - c.addi16sp sp, 16 - lui zero, 195546 - andi s8, t1, -26 - remu s5, s11, t1 - c.andi a5, -1 - c.slli t4, 28 - srai s10, s1, 24 - add s7, s5, a6 - or s0, a2, a0 - srl a0, s2, a0 - c.srli a0, 25 - nop - c.lui a0, 24 - c.slli t4, 28 - c.srai s0, 31 - div t3, t1, t5 - c.and a0, s0 - auipc t6, 688967 - sll t3, s7, a3 - c.slli t4, 28 - c.or a5, a1 - rem s0, a3, a2 - srai s10, s1, 24 - add s7, s5, a6 - c.andi a5, -1 - c.add t1, a1 - rem s0, a3, a2 - auipc t6, 688967 - c.srli a0, 25 - c.sub s1, a4 - ori t5, t2, 999 - addi a7, t2, -784 - sltiu s6, ra, 913 - sltu t2, s1, t1 - srai s10, s1, 24 - lui zero, 195546 - sra s1, t3, s1 - c.slli t4, 28 - and a1, t3, a6 - c.nop - divu sp, ra, t0 - c.addi16sp sp, 16 - sra s1, t3, s1 - divu sp, ra, t0 - div t3, t1, t5 - c.andi a5, -1 - c.srai s0, 31 - c.li a7, 27 - c.lui a0, 24 - mulhsu gp, a1, s1 - sltiu s6, ra, 913 - div t3, t1, t5 - andi s8, t1, -26 - mulhu tp, s3, a4 - srai s10, s1, 24 - or s0, a2, a0 - c.slli t4, 28 - slti tp, t6, 301 - srl a0, s2, a0 - slti tp, t6, 301 - srai s10, s1, 24 - c.srli a0, 25 - sub s9, s6, s5 - srl a0, s2, a0 - xori a4, t0, 974 - c.srai s0, 31 - div t3, t1, t5 - divu sp, ra, t0 - slt t1, a1, a4 - addi a7, t2, -784 - mulhu tp, s3, a4 - or s0, a2, a0 - mulh s11, s1, s9 - c.xor a1, a2 - rem s0, a3, a2 - sll t3, s7, a3 - sltiu s6, ra, 913 - remu s5, s11, t1 - mulhsu gp, a1, s1 - rem s0, a3, a2 - c.srai s0, 31 - c.or a5, a1 - mulhsu gp, a1, s1 - and a1, t3, a6 - mulhu tp, s3, a4 - c.and a0, s0 - c.srai s0, 31 - mulh s11, s1, s9 - srli s8, t6, 19 - div t3, t1, t5 - srli s8, t6, 19 - srl a0, s2, a0 - sltiu s6, ra, 913 - add s7, s5, a6 - and a1, t3, a6 - c.srai s0, 31 - and a1, t3, a6 - c.addi s1, 6 - srl a0, s2, a0 - c.srli a0, 25 - sra s1, t3, s1 - sra s1, t3, s1 - and a1, t3, a6 - c.srai s0, 31 - mulh s11, s1, s9 - div t3, t1, t5 - c.srli a0, 25 - or s0, a2, a0 - slli s11, gp, 14 - and a1, t3, a6 - sltiu s6, ra, 913 - div t3, t1, t5 - add s7, s5, a6 - c.addi s1, 6 - srl a0, s2, a0 - srl a0, s2, a0 - slti tp, t6, 301 - c.addi16sp sp, 16 - mulhu tp, s3, a4 - rem s0, a3, a2 - c.mv a1, s5 - lui zero, 195546 - slt t1, a1, a4 - c.slli t4, 28 - slti tp, t6, 301 - auipc t6, 688967 - c.li a7, 27 - c.or a5, a1 - sub s9, s6, s5 - ori t5, t2, 999 - slli s11, gp, 14 - nop - c.nop - mul sp, s9, s11 - c.or a5, a1 - c.mv a1, s5 - sub s9, s6, s5 - xor t4, s3, t3 - andi s8, t1, -26 - auipc t6, 688967 - xori a4, t0, 974 - srai s10, s1, 24 - c.mv a1, s5 - and a1, t3, a6 - c.li a7, 27 - sra s1, t3, s1 - remu s5, s11, t1 - c.lui a0, 24 - addi a7, t2, -784 - c.andi a5, -1 - c.addi16sp sp, 16 - c.andi a5, -1 - sll t3, s7, a3 - c.sub s1, a4 - c.addi16sp sp, 16 - div t3, t1, t5 - nop - remu s5, s11, t1 - lui zero, 195546 - rem s0, a3, a2 - sltiu s6, ra, 913 - div t3, t1, t5 - c.addi s1, 6 - auipc t6, 688967 - sltu t2, s1, t1 - c.slli t4, 28 - srai s10, s1, 24 - sll t3, s7, a3 - div t3, t1, t5 - nop - ori t5, t2, 999 - c.srli a0, 25 - slt t1, a1, a4 - nop - c.nop - c.add t1, a1 - slti tp, t6, 301 - c.add t1, a1 - sltu t2, s1, t1 - div t3, t1, t5 - slli s11, gp, 14 - c.srai s0, 31 - sltu t2, s1, t1 - mulhu tp, s3, a4 - c.slli t4, 28 - slt t1, a1, a4 - c.mv a1, s5 - slli s11, gp, 14 - xori a4, t0, 974 - c.addi16sp sp, 16 - mulhu tp, s3, a4 - srli s8, t6, 19 - slti tp, t6, 301 - mulhsu gp, a1, s1 - c.srai s0, 31 - auipc t6, 688967 - srai s10, s1, 24 - mulhu tp, s3, a4 - c.andi a5, -1 - srl a0, s2, a0 - and a1, t3, a6 - srl a0, s2, a0 - slt t1, a1, a4 - sltu t2, s1, t1 - c.slli t4, 28 - c.or a5, a1 - rem s0, a3, a2 - addi a7, t2, -784 - c.and a0, s0 - andi s8, t1, -26 - c.lui a0, 24 - ori t5, t2, 999 - c.lui a0, 24 - c.lui a0, 24 - auipc t6, 688967 - auipc t6, 688967 - c.and a0, s0 - and a1, t3, a6 - slt t1, a1, a4 - rem s0, a3, a2 - addi a7, t2, -784 - and a1, t3, a6 - c.or a5, a1 - c.addi s1, 6 - rem s0, a3, a2 - c.addi16sp sp, 16 - sll t3, s7, a3 - xori a4, t0, 974 - add s7, s5, a6 - c.slli t4, 28 - c.nop - c.or a5, a1 - srli s8, t6, 19 - sra s1, t3, s1 - ori t5, t2, 999 - xor t4, s3, t3 - c.andi a5, -1 - sll t3, s7, a3 - c.lui a0, 24 - c.or a5, a1 - mulhu tp, s3, a4 - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - andi s8, t1, -26 - c.lui a0, 24 - c.add t1, a1 - and a1, t3, a6 - sll t3, s7, a3 - c.li a7, 27 - mulhsu gp, a1, s1 - mulhu tp, s3, a4 - ori t5, t2, 999 - srli s8, t6, 19 - srai s10, s1, 24 - srai s10, s1, 24 - or s0, a2, a0 - div t3, t1, t5 - mulh s11, s1, s9 - c.nop - ori t5, t2, 999 - c.andi a5, -1 - c.srli a0, 25 - nop - sub s9, s6, s5 - c.addi4spn a4, sp, 288 - mulhsu gp, a1, s1 - andi s8, t1, -26 - sltiu s6, ra, 913 - divu sp, ra, t0 - c.addi4spn a4, sp, 288 - c.srai s0, 31 - lui zero, 195546 - slt t1, a1, a4 - auipc t6, 688967 - c.slli t4, 28 - addi a7, t2, -784 - slt t1, a1, a4 - srl a0, s2, a0 - div t3, t1, t5 - c.li a7, 27 - c.andi a5, -1 - c.addi s1, 6 - lui zero, 195546 - slli s11, gp, 14 - andi s8, t1, -26 - auipc t6, 688967 - sltu t2, s1, t1 - srai s10, s1, 24 - c.nop - c.mv a1, s5 - xori a4, t0, 974 - c.or a5, a1 - ori t5, t2, 999 - sltu t2, s1, t1 - c.nop - c.slli t4, 28 - lui zero, 195546 - c.addi16sp sp, 16 - c.add t1, a1 - slt t1, a1, a4 - div t3, t1, t5 - c.slli t4, 28 - addi a7, t2, -784 - sltu t2, s1, t1 - mulhu tp, s3, a4 - c.addi16sp sp, 16 - c.xor a1, a2 - remu s5, s11, t1 - rem s0, a3, a2 - remu s5, s11, t1 - c.addi s1, 6 - auipc t6, 688967 - c.mv a1, s5 - sub s9, s6, s5 - add s7, s5, a6 - sltiu s6, ra, 913 - nop - srai s10, s1, 24 - sub s9, s6, s5 - srai s10, s1, 24 - addi a7, t2, -784 - srli s8, t6, 19 - mulh s11, s1, s9 - srai s10, s1, 24 - c.andi a5, -1 - c.li a7, 27 - c.nop - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - lui zero, 195546 - c.xor a1, a2 - sll t3, s7, a3 - addi a7, t2, -784 - slti tp, t6, 301 - addi a7, t2, -784 - c.addi4spn a4, sp, 288 - c.xor a1, a2 - c.and a0, s0 - mulhu tp, s3, a4 - c.and a0, s0 - sll t3, s7, a3 - xor t4, s3, t3 - c.addi s1, 6 - sltiu s6, ra, 913 - lui zero, 195546 - or s0, a2, a0 - divu sp, ra, t0 - add s7, s5, a6 - c.xor a1, a2 - c.add t1, a1 - c.srai s0, 31 - c.xor a1, a2 - srl a0, s2, a0 - xor t4, s3, t3 - slti tp, t6, 301 - sub s9, s6, s5 - slli s11, gp, 14 - sltiu s6, ra, 913 - slti tp, t6, 301 - sltiu s6, ra, 913 - remu s5, s11, t1 - sub s9, s6, s5 - div t3, t1, t5 - c.srli a0, 25 - c.nop - c.srli a0, 25 - nop - xori a4, t0, 974 - xor t4, s3, t3 - c.addi s1, 6 - sltiu s6, ra, 913 - sltiu s6, ra, 913 - slti tp, t6, 301 - c.nop - c.or a5, a1 - nop - auipc t6, 688967 - sltiu s6, ra, 913 - auipc t6, 688967 - add s7, s5, a6 - nop - c.andi a5, -1 - c.add t1, a1 - xor t4, s3, t3 - slt t1, a1, a4 - slli s11, gp, 14 - c.srai s0, 31 - slt t1, a1, a4 - c.addi s1, 6 - addi a7, t2, -784 - rem s0, a3, a2 - c.sub s1, a4 - srli s8, t6, 19 - c.add t1, a1 - addi a7, t2, -784 - c.slli t4, 28 - c.addi16sp sp, 16 - c.or a5, a1 - c.nop - andi s8, t1, -26 - xori a4, t0, 974 - c.lui a0, 24 - andi s8, t1, -26 - c.addi16sp sp, 16 - c.add t1, a1 - c.slli t4, 28 - addi a7, t2, -784 - sltiu s6, ra, 913 - slti tp, t6, 301 - xori a4, t0, 974 - addi a7, t2, -784 - srl a0, s2, a0 - auipc t6, 688967 - lui zero, 195546 - c.srli a0, 25 - sll t3, s7, a3 - sltu t2, s1, t1 - c.sub s1, a4 - addi a7, t2, -784 - c.andi a5, -1 - slt t1, a1, a4 - c.andi a5, -1 - c.or a5, a1 - addi a7, t2, -784 - c.sub s1, a4 - slt t1, a1, a4 - andi s8, t1, -26 - c.slli t4, 28 - c.li a7, 27 - c.sub s1, a4 - or s0, a2, a0 - auipc t6, 688967 - c.srai s0, 31 - c.srai s0, 31 - c.add t1, a1 - divu sp, ra, t0 - c.slli t4, 28 - c.slli t4, 28 - c.or a5, a1 - lui zero, 195546 - lui zero, 195546 - auipc t6, 688967 - auipc t6, 688967 - sra s1, t3, s1 - c.lui a0, 24 - rem s0, a3, a2 - c.slli t4, 28 - c.nop - sub s9, s6, s5 - addi a7, t2, -784 - slti tp, t6, 301 - mulh s11, s1, s9 - c.mv a1, s5 - c.slli t4, 28 - xori a4, t0, 974 - sra s1, t3, s1 - sll t3, s7, a3 - c.andi a5, -1 - mulhu tp, s3, a4 - and a1, t3, a6 - c.li a7, 27 - c.li a7, 27 - andi s8, t1, -26 - slli s11, gp, 14 - ori t5, t2, 999 - mul sp, s9, s11 - c.xor a1, a2 - sltiu s6, ra, 913 - addi a7, t2, -784 - c.or a5, a1 - c.or a5, a1 - nop - c.addi16sp sp, 16 - srli s8, t6, 19 - or s0, a2, a0 - div t3, t1, t5 - addi a7, t2, -784 - srli s8, t6, 19 - c.srli a0, 25 - andi s8, t1, -26 - rem s0, a3, a2 - c.and a0, s0 - c.li a7, 27 - mulhu tp, s3, a4 - slti tp, t6, 301 - div t3, t1, t5 - div t3, t1, t5 - sub s9, s6, s5 - c.add t1, a1 - c.mv a1, s5 - rem s0, a3, a2 - c.lui a0, 24 - xori a4, t0, 974 - slli s11, gp, 14 - c.addi16sp sp, 16 - c.xor a1, a2 - or s0, a2, a0 - sll t3, s7, a3 - ori t5, t2, 999 - sra s1, t3, s1 - c.addi16sp sp, 16 - slti tp, t6, 301 - xori a4, t0, 974 - divu sp, ra, t0 - c.lui a0, 24 - sltiu s6, ra, 913 - mulhsu gp, a1, s1 - add s7, s5, a6 - c.nop - c.srli a0, 25 - mulh s11, s1, s9 - and a1, t3, a6 - add s7, s5, a6 - c.srai s0, 31 - remu s5, s11, t1 - sll t3, s7, a3 - c.mv a1, s5 - c.and a0, s0 - c.andi a5, -1 - c.addi s1, 6 - c.addi s1, 6 - c.add t1, a1 - ori t5, t2, 999 - srl a0, s2, a0 - srl a0, s2, a0 - srli s8, t6, 19 - ori t5, t2, 999 - c.or a5, a1 - or s0, a2, a0 - c.xor a1, a2 - and a1, t3, a6 - remu s5, s11, t1 - ori t5, t2, 999 - srai s10, s1, 24 - mulhsu gp, a1, s1 - auipc t6, 688967 - c.mv a1, s5 - srai s10, s1, 24 - mulhsu gp, a1, s1 - addi a7, t2, -784 - or s0, a2, a0 - sltu t2, s1, t1 - c.or a5, a1 - c.srli a0, 25 - sltu t2, s1, t1 - c.srli a0, 25 - sltiu s6, ra, 913 - c.or a5, a1 - c.li a7, 27 - srl a0, s2, a0 - ori t5, t2, 999 - mulhu tp, s3, a4 - c.addi16sp sp, 16 - c.srli a0, 25 - or s0, a2, a0 - or s0, a2, a0 - slt t1, a1, a4 - c.mv a1, s5 - c.nop - and a1, t3, a6 - slli s11, gp, 14 - andi s8, t1, -26 - div t3, t1, t5 - nop - c.andi a5, -1 - addi a7, t2, -784 - c.or a5, a1 - andi s8, t1, -26 - c.lui a0, 24 - slli s11, gp, 14 - lui zero, 195546 - or s0, a2, a0 - divu sp, ra, t0 - c.or a5, a1 - slli s11, gp, 14 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - slti tp, t6, 301 - mulhu tp, s3, a4 - c.srli a0, 25 - slt t1, a1, a4 - remu s5, s11, t1 - c.addi s1, 6 - mul sp, s9, s11 - divu sp, ra, t0 - and a1, t3, a6 - c.addi16sp sp, 16 - c.addi16sp sp, 16 - lui zero, 195546 - sra s1, t3, s1 - c.lui a0, 24 - c.and a0, s0 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - sltu t2, s1, t1 - or s0, a2, a0 - srli s8, t6, 19 - c.mv a1, s5 - srai s10, s1, 24 - c.nop - slti tp, t6, 301 - slt t1, a1, a4 - sll t3, s7, a3 - c.lui a0, 24 - or s0, a2, a0 - c.li a7, 27 - c.nop - c.add t1, a1 - c.and a0, s0 - sub s9, s6, s5 - xori a4, t0, 974 - c.li a7, 27 - mulh s11, s1, s9 - div t3, t1, t5 - sra s1, t3, s1 - andi s8, t1, -26 - mul sp, s9, s11 - c.and a0, s0 - lui zero, 195546 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - c.and a0, s0 - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - c.slli t4, 28 - mulhu tp, s3, a4 - auipc t6, 688967 - mulh s11, s1, s9 - or s0, a2, a0 - c.addi4spn a4, sp, 288 - c.lui a0, 24 - divu sp, ra, t0 - and a1, t3, a6 - andi s8, t1, -26 - xor t4, s3, t3 - c.addi4spn a4, sp, 288 - add s7, s5, a6 - c.addi16sp sp, 16 - srai s10, s1, 24 - c.sub s1, a4 - slti tp, t6, 301 - xor t4, s3, t3 - c.addi s1, 6 - remu s5, s11, t1 - slt t1, a1, a4 - divu sp, ra, t0 - div t3, t1, t5 - lui zero, 195546 - c.lui a0, 24 - nop - c.xor a1, a2 - c.addi4spn a4, sp, 288 - c.add t1, a1 - addi a7, t2, -784 - or s0, a2, a0 - c.xor a1, a2 - c.xor a1, a2 - mul sp, s9, s11 - c.add t1, a1 - c.nop - c.xor a1, a2 - div t3, t1, t5 - c.or a5, a1 - divu sp, ra, t0 - ori t5, t2, 999 - c.srai s0, 31 - c.addi s1, 6 - mul sp, s9, s11 - divu sp, ra, t0 - c.addi s1, 6 - mul sp, s9, s11 - sll t3, s7, a3 - andi s8, t1, -26 - ori t5, t2, 999 - slti tp, t6, 301 - mul sp, s9, s11 - slti tp, t6, 301 - slti tp, t6, 301 - addi a7, t2, -784 - xor t4, s3, t3 - divu sp, ra, t0 - or s0, a2, a0 - rem s0, a3, a2 - c.andi a5, -1 - andi s8, t1, -26 - c.srai s0, 31 - nop - sll t3, s7, a3 - sltiu s6, ra, 913 - srli s8, t6, 19 - sll t3, s7, a3 - c.srli a0, 25 - c.and a0, s0 - lui zero, 195546 - c.slli t4, 28 - c.addi16sp sp, 16 - c.addi4spn a4, sp, 288 - and a1, t3, a6 - c.srai s0, 31 - ori t5, t2, 999 - srai s10, s1, 24 - srli s8, t6, 19 - addi a7, t2, -784 - or s0, a2, a0 - nop - mul sp, s9, s11 - c.and a0, s0 - c.or a5, a1 - c.slli t4, 28 - mul sp, s9, s11 - xor t4, s3, t3 - or s0, a2, a0 - sltiu s6, ra, 913 - c.add t1, a1 - c.addi s1, 6 - srai s10, s1, 24 - c.li a7, 27 - c.srai s0, 31 - sltu t2, s1, t1 - srl a0, s2, a0 - andi s8, t1, -26 - c.slli t4, 28 - c.nop - srai s10, s1, 24 - c.mv a1, s5 - divu sp, ra, t0 - srai s10, s1, 24 - c.srli a0, 25 - c.srai s0, 31 - mulhsu gp, a1, s1 - sra s1, t3, s1 - c.nop - slt t1, a1, a4 - c.sub s1, a4 - c.or a5, a1 - or s0, a2, a0 - ori t5, t2, 999 - slli s11, gp, 14 - add s7, s5, a6 - div t3, t1, t5 - slt t1, a1, a4 - xor t4, s3, t3 - slt t1, a1, a4 - ori t5, t2, 999 - slt t1, a1, a4 - c.sub s1, a4 - c.slli t4, 28 - addi a7, t2, -784 - mulhu tp, s3, a4 - sub s9, s6, s5 - mulhsu gp, a1, s1 - sll t3, s7, a3 - c.li a7, 27 - slt t1, a1, a4 - c.srli a0, 25 - c.xor a1, a2 - xori a4, t0, 974 - add s7, s5, a6 - remu s5, s11, t1 - c.slli t4, 28 - c.and a0, s0 - c.sub s1, a4 - nop - add s7, s5, a6 - slt t1, a1, a4 - mulh s11, s1, s9 - andi s8, t1, -26 - mulhu tp, s3, a4 - c.add t1, a1 - mulhu tp, s3, a4 - slt t1, a1, a4 - mulh s11, s1, s9 - addi a7, t2, -784 - sra s1, t3, s1 - sub s9, s6, s5 - sll t3, s7, a3 - mulhsu gp, a1, s1 - mul sp, s9, s11 - xori a4, t0, 974 - remu s5, s11, t1 - lui zero, 195546 - srli s8, t6, 19 - c.or a5, a1 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - c.slli t4, 28 - slt t1, a1, a4 - sltu t2, s1, t1 - c.nop - xori a4, t0, 974 - c.sub s1, a4 - c.addi s1, 6 - mulhsu gp, a1, s1 - c.nop - lui zero, 195546 - c.lui a0, 24 - xori a4, t0, 974 - or s0, a2, a0 - div t3, t1, t5 - c.addi s1, 6 - c.add t1, a1 - c.slli t4, 28 - mulhu tp, s3, a4 - remu s5, s11, t1 - andi s8, t1, -26 - div t3, t1, t5 - andi s8, t1, -26 - sltu t2, s1, t1 - sub s9, s6, s5 - c.sub s1, a4 - or s0, a2, a0 - c.nop - andi s8, t1, -26 - slti tp, t6, 301 - lui zero, 195546 - sltiu s6, ra, 913 - mulhu tp, s3, a4 - c.addi4spn a4, sp, 288 - div t3, t1, t5 - sltu t2, s1, t1 - xor t4, s3, t3 - or s0, a2, a0 - andi s8, t1, -26 - mulh s11, s1, s9 - c.or a5, a1 - xori a4, t0, 974 - slli s11, gp, 14 - slt t1, a1, a4 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - srl a0, s2, a0 - c.slli t4, 28 - rem s0, a3, a2 - mul sp, s9, s11 - mulhsu gp, a1, s1 - nop - c.and a0, s0 - addi a7, t2, -784 - c.mv a1, s5 - c.srai s0, 31 - div t3, t1, t5 - srli s8, t6, 19 - sra s1, t3, s1 - c.srli a0, 25 - mulhsu gp, a1, s1 - c.mv a1, s5 - c.xor a1, a2 - xori a4, t0, 974 - remu s5, s11, t1 - c.add t1, a1 - li ra, 0xffffffff #start riscv_int_numeric_corner_stream_23 - li a5, 0x80000000 - li s6, 0xffffffff - li a6, 0x80000000 - li a7, 0xffffffff - li t3, 0x0 - li a4, 0xaa2a5c0 - li t4, 0x80000000 - li s5, 0x0 - li t0, 0x0 - sub a4, t3, a4 - lui ra, 195546 - nop - nop - add t0, ra, a7 - auipc t4, 688967 - add t0, ra, a7 - nop - auipc t4, 688967 - mulh ra, a5, s5 - nop - mulhsu a5, ra, ra - sub a4, t3, a4 - nop - div a6, a6, a4 - mul a4, t4, t3 - rem a7, a5, a4 - div a6, a6, a4 - div a6, a6, a4 - sub a4, t3, a4 - mulhsu a5, ra, ra - nop - mulhu ra, a5, t0 #end riscv_int_numeric_corner_stream_23 - c.nop - mulhu tp, s3, a4 - sll t3, s7, a3 - sltu t2, s1, t1 - c.mv a1, s5 - c.srai s0, 31 - c.sub s1, a4 - c.add t1, a1 - xori a4, t0, 974 - xor t4, s3, t3 - sltiu s6, ra, 913 - sub s9, s6, s5 - div t3, t1, t5 - sll t3, s7, a3 - c.lui a0, 24 - c.li a7, 27 - c.andi a5, -1 - srl a0, s2, a0 - auipc t6, 688967 - divu sp, ra, t0 - addi a7, t2, -784 - mulhu tp, s3, a4 - c.nop - addi a7, t2, -784 - slti tp, t6, 301 - remu s5, s11, t1 - c.or a5, a1 - c.add t1, a1 - c.add t1, a1 - c.xor a1, a2 - mulh s11, s1, s9 - auipc t6, 688967 - div t3, t1, t5 - and a1, t3, a6 - addi a7, t2, -784 - slti tp, t6, 301 - rem s0, a3, a2 - ori t5, t2, 999 - c.li a7, 27 - sll t3, s7, a3 - slt t1, a1, a4 - c.lui a0, 24 - mulhu tp, s3, a4 - sra s1, t3, s1 - srai s10, s1, 24 - c.add t1, a1 - lui zero, 195546 - sll t3, s7, a3 - slti tp, t6, 301 - c.or a5, a1 - divu sp, ra, t0 - add s7, s5, a6 - sll t3, s7, a3 - c.addi s1, 6 - lui zero, 195546 - slli s11, gp, 14 - mulh s11, s1, s9 - lui zero, 195546 - or s0, a2, a0 - div t3, t1, t5 - mulhu tp, s3, a4 - c.and a0, s0 - slli s11, gp, 14 - c.srai s0, 31 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - divu sp, ra, t0 - xori a4, t0, 974 - divu sp, ra, t0 - sub s9, s6, s5 - c.srli a0, 25 - c.srli a0, 25 - mulhsu gp, a1, s1 - auipc t6, 688967 - c.li a7, 27 - sltu t2, s1, t1 - c.mv a1, s5 - mulhsu gp, a1, s1 - srl a0, s2, a0 - rem s0, a3, a2 - andi s8, t1, -26 - c.addi16sp sp, 16 - slti tp, t6, 301 - auipc t6, 688967 - sra s1, t3, s1 - c.srai s0, 31 - mulhsu gp, a1, s1 - div t3, t1, t5 - andi s8, t1, -26 - sra s1, t3, s1 - div t3, t1, t5 - sra s1, t3, s1 - c.addi4spn a4, sp, 288 - sltiu s6, ra, 913 - div t3, t1, t5 - div t3, t1, t5 - srai s10, s1, 24 - c.addi s1, 6 - c.add t1, a1 - sltu t2, s1, t1 - nop - mul sp, s9, s11 - or s0, a2, a0 - andi s8, t1, -26 - remu s5, s11, t1 - mulh s11, s1, s9 - c.lui a0, 24 - c.srli a0, 25 - addi a7, t2, -784 - add s7, s5, a6 - c.or a5, a1 - div t3, t1, t5 - srai s10, s1, 24 - srai s10, s1, 24 - and a1, t3, a6 - c.addi s1, 6 - and a1, t3, a6 - rem s0, a3, a2 - andi s8, t1, -26 - c.addi16sp sp, 16 - c.xor a1, a2 - c.li a7, 27 - sub s9, s6, s5 - c.slli t4, 28 - ori t5, t2, 999 - lui zero, 195546 - mulhu tp, s3, a4 - slti tp, t6, 301 - c.li a7, 27 - c.srai s0, 31 - c.mv a1, s5 - sll t3, s7, a3 - sltiu s6, ra, 913 - slti tp, t6, 301 - lui zero, 195546 - c.srai s0, 31 - div t3, t1, t5 - rem s0, a3, a2 - mulhsu gp, a1, s1 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - c.nop - c.mv a1, s5 - c.lui a0, 24 - c.and a0, s0 - sll t3, s7, a3 - c.add t1, a1 - srai s10, s1, 24 - c.xor a1, a2 - mulhsu gp, a1, s1 - srl a0, s2, a0 - srli s8, t6, 19 - sll t3, s7, a3 - slli s11, gp, 14 - c.srai s0, 31 - c.slli t4, 28 - add s7, s5, a6 - mulhsu gp, a1, s1 - c.or a5, a1 - add s7, s5, a6 - c.and a0, s0 - c.lui a0, 24 - sltiu s6, ra, 913 - div t3, t1, t5 - nop - c.nop - lui zero, 195546 - slt t1, a1, a4 - and a1, t3, a6 - slti tp, t6, 301 - or s0, a2, a0 - c.add t1, a1 - rem s0, a3, a2 - andi s8, t1, -26 - andi s8, t1, -26 - c.addi s1, 6 - mulhsu gp, a1, s1 - divu sp, ra, t0 - add s7, s5, a6 - srai s10, s1, 24 - divu sp, ra, t0 - sll t3, s7, a3 - and a1, t3, a6 - c.andi a5, -1 - divu sp, ra, t0 - remu s5, s11, t1 - c.lui a0, 24 - srli s8, t6, 19 - div t3, t1, t5 - c.add t1, a1 - c.li a7, 27 - div t3, t1, t5 - divu sp, ra, t0 - slt t1, a1, a4 - c.lui a0, 24 - c.srli a0, 25 - sub s9, s6, s5 - c.mv a1, s5 - mul sp, s9, s11 - c.srai s0, 31 - andi s8, t1, -26 - div t3, t1, t5 - sltu t2, s1, t1 - c.srli a0, 25 - auipc t6, 688967 - sub s9, s6, s5 - sub s9, s6, s5 - sll t3, s7, a3 - and a1, t3, a6 - c.and a0, s0 - sltiu s6, ra, 913 - ori t5, t2, 999 - c.addi4spn a4, sp, 288 - c.mv a1, s5 - srl a0, s2, a0 - c.and a0, s0 - mul sp, s9, s11 - mulh s11, s1, s9 - c.and a0, s0 - srli s8, t6, 19 - c.nop - srl a0, s2, a0 - and a1, t3, a6 - srli s8, t6, 19 - c.li a7, 27 - remu s5, s11, t1 - xori a4, t0, 974 - ori t5, t2, 999 - c.li a7, 27 - c.nop - remu s5, s11, t1 - c.mv a1, s5 - mul sp, s9, s11 - c.nop - srl a0, s2, a0 - xor t4, s3, t3 - c.andi a5, -1 - c.srli a0, 25 - div t3, t1, t5 - slti tp, t6, 301 - rem s0, a3, a2 - c.mv a1, s5 - c.li a7, 27 - or s0, a2, a0 - c.li a7, 27 - c.xor a1, a2 - mulhu tp, s3, a4 - sub s9, s6, s5 - sltiu s6, ra, 913 - add s7, s5, a6 - andi s8, t1, -26 - ori t5, t2, 999 - c.xor a1, a2 - slli s11, gp, 14 - c.addi4spn a4, sp, 288 - rem s0, a3, a2 - and a1, t3, a6 - add s7, s5, a6 - andi s8, t1, -26 - sub s9, s6, s5 - and a1, t3, a6 - mulh s11, s1, s9 - xor t4, s3, t3 - c.add t1, a1 - c.addi16sp sp, 16 - mul sp, s9, s11 - c.addi16sp sp, 16 - add s7, s5, a6 - sltiu s6, ra, 913 - sltu t2, s1, t1 - remu s5, s11, t1 - sll t3, s7, a3 - remu s5, s11, t1 - c.andi a5, -1 - slt t1, a1, a4 - lui zero, 195546 - rem s0, a3, a2 - c.mv a1, s5 - mulh s11, s1, s9 - c.or a5, a1 - c.li a7, 27 - nop - c.srli a0, 25 - or s0, a2, a0 - remu s5, s11, t1 - lui zero, 195546 - sltiu s6, ra, 913 - c.srai s0, 31 - c.srai s0, 31 - c.srai s0, 31 - c.slli t4, 28 - c.li a7, 27 - xor t4, s3, t3 - mul sp, s9, s11 - c.add t1, a1 - mul sp, s9, s11 - c.addi4spn a4, sp, 288 - srli s8, t6, 19 - sltiu s6, ra, 913 - and a1, t3, a6 - div t3, t1, t5 - addi a7, t2, -784 - xori a4, t0, 974 - c.addi s1, 6 - divu sp, ra, t0 - c.lui a0, 24 - c.mv a1, s5 - c.lui a0, 24 - sra s1, t3, s1 - sub s9, s6, s5 - c.srli a0, 25 - c.li a7, 27 - c.add t1, a1 - c.addi s1, 6 - mulhu tp, s3, a4 - srl a0, s2, a0 - nop - c.add t1, a1 - c.srai s0, 31 - lui zero, 195546 - sra s1, t3, s1 - c.xor a1, a2 - divu sp, ra, t0 - ori t5, t2, 999 - nop - slli s11, gp, 14 - divu sp, ra, t0 - c.and a0, s0 - ori t5, t2, 999 - c.nop - c.xor a1, a2 - c.mv a1, s5 - c.addi16sp sp, 16 - c.mv a1, s5 - xori a4, t0, 974 - sub s9, s6, s5 - c.add t1, a1 - mulhu tp, s3, a4 - xori a4, t0, 974 - or s0, a2, a0 - remu s5, s11, t1 - srai s10, s1, 24 - slt t1, a1, a4 - c.and a0, s0 - c.mv a1, s5 - sll t3, s7, a3 - xori a4, t0, 974 - c.srli a0, 25 - slti tp, t6, 301 - or s0, a2, a0 - c.srli a0, 25 - c.mv a1, s5 - mulh s11, s1, s9 - c.addi16sp sp, 16 - xori a4, t0, 974 - sra s1, t3, s1 - sub s9, s6, s5 - mulh s11, s1, s9 - mul sp, s9, s11 - c.slli t4, 28 - addi a7, t2, -784 - c.slli t4, 28 - addi a7, t2, -784 - c.li a7, 27 - c.mv a1, s5 - slti tp, t6, 301 - slti tp, t6, 301 - c.or a5, a1 - div t3, t1, t5 - add s7, s5, a6 - c.sub s1, a4 - lui zero, 195546 - mul sp, s9, s11 - ori t5, t2, 999 - c.addi s1, 6 - c.nop - sll t3, s7, a3 - c.sub s1, a4 - auipc t6, 688967 - c.add t1, a1 - c.srai s0, 31 - c.add t1, a1 - srl a0, s2, a0 - slti tp, t6, 301 - sltu t2, s1, t1 - and a1, t3, a6 - srai s10, s1, 24 - lui zero, 195546 - sra s1, t3, s1 - c.addi4spn a4, sp, 288 - sll t3, s7, a3 - srl a0, s2, a0 - sra s1, t3, s1 - mulhsu gp, a1, s1 - mulh s11, s1, s9 - c.addi16sp sp, 16 - mul sp, s9, s11 - xor t4, s3, t3 - c.and a0, s0 - c.mv a1, s5 - c.srai s0, 31 - c.addi16sp sp, 16 - c.srli a0, 25 - div t3, t1, t5 - srai s10, s1, 24 - sub s9, s6, s5 - srai s10, s1, 24 - rem s0, a3, a2 - xor t4, s3, t3 - mul sp, s9, s11 - c.lui a0, 24 - and a1, t3, a6 - sltiu s6, ra, 913 - xori a4, t0, 974 - xor t4, s3, t3 - sra s1, t3, s1 - c.xor a1, a2 - c.addi s1, 6 - xori a4, t0, 974 - c.mv a1, s5 - xori a4, t0, 974 - sub s9, s6, s5 - c.and a0, s0 - sra s1, t3, s1 - mulh s11, s1, s9 - addi a7, t2, -784 - slli s11, gp, 14 - nop - auipc t6, 688967 - c.addi4spn a4, sp, 288 - c.lui a0, 24 - c.addi s1, 6 - addi a7, t2, -784 - lui zero, 195546 - addi a7, t2, -784 - and a1, t3, a6 - or s0, a2, a0 - sra s1, t3, s1 - slti tp, t6, 301 - srl a0, s2, a0 - c.sub s1, a4 - c.add t1, a1 - ori t5, t2, 999 - c.addi4spn a4, sp, 288 - remu s5, s11, t1 - slli s11, gp, 14 - or s0, a2, a0 - andi s8, t1, -26 - andi s8, t1, -26 - sltiu s6, ra, 913 - auipc t6, 688967 - rem s0, a3, a2 - c.li a7, 27 - mulh s11, s1, s9 - sra s1, t3, s1 - c.xor a1, a2 - srl a0, s2, a0 - remu s5, s11, t1 - add s7, s5, a6 - auipc t6, 688967 - c.lui a0, 24 - c.and a0, s0 - slli s11, gp, 14 - add s7, s5, a6 - c.andi a5, -1 - rem s0, a3, a2 - srai s10, s1, 24 - c.addi4spn a4, sp, 288 - sll t3, s7, a3 - c.addi16sp sp, 16 - sltu t2, s1, t1 - andi s8, t1, -26 - c.mv a1, s5 - c.lui a0, 24 - c.nop - c.nop - remu s5, s11, t1 - addi a7, t2, -784 - slt t1, a1, a4 - or s0, a2, a0 - c.sub s1, a4 - mulhsu gp, a1, s1 - c.andi a5, -1 - c.addi s1, 6 - slt t1, a1, a4 - mulh s11, s1, s9 - ori t5, t2, 999 - mulhu tp, s3, a4 - c.sub s1, a4 - c.srai s0, 31 - sub s9, s6, s5 - lui zero, 195546 - c.addi16sp sp, 16 - xori a4, t0, 974 - c.lui a0, 24 - lui zero, 195546 - lui zero, 195546 - addi a7, t2, -784 - srli s8, t6, 19 - nop - andi s8, t1, -26 - c.andi a5, -1 - c.lui a0, 24 - mulhsu gp, a1, s1 - srai s10, s1, 24 - sll t3, s7, a3 - remu s5, s11, t1 - divu sp, ra, t0 - c.add t1, a1 - remu s5, s11, t1 - c.add t1, a1 - sub s9, s6, s5 - c.sub s1, a4 - c.li a7, 27 - divu sp, ra, t0 - lui zero, 195546 - c.mv a1, s5 - slli s11, gp, 14 - c.addi4spn a4, sp, 288 - divu sp, ra, t0 - sll t3, s7, a3 - xori a4, t0, 974 - remu s5, s11, t1 - c.add t1, a1 - lui zero, 195546 - mulhu tp, s3, a4 - c.addi s1, 6 - add s7, s5, a6 - ori t5, t2, 999 - c.or a5, a1 - mulhsu gp, a1, s1 - xor t4, s3, t3 - slt t1, a1, a4 - c.xor a1, a2 - c.or a5, a1 - sra s1, t3, s1 - auipc t6, 688967 - c.lui a0, 24 - c.add t1, a1 - c.and a0, s0 - sub s9, s6, s5 - c.mv a1, s5 - div t3, t1, t5 - or s0, a2, a0 - divu sp, ra, t0 - c.andi a5, -1 - slt t1, a1, a4 - xor t4, s3, t3 - xori a4, t0, 974 - srli s8, t6, 19 - c.slli t4, 28 - mulhu tp, s3, a4 - ori t5, t2, 999 - srli s8, t6, 19 - slli s11, gp, 14 - c.xor a1, a2 - c.and a0, s0 - add s7, s5, a6 - and a1, t3, a6 - mulhu tp, s3, a4 - srai s10, s1, 24 - slti tp, t6, 301 - c.andi a5, -1 - mulh s11, s1, s9 - c.srai s0, 31 - slti tp, t6, 301 - srl a0, s2, a0 - slli s11, gp, 14 - c.lui a0, 24 - srai s10, s1, 24 - c.srai s0, 31 - xor t4, s3, t3 - div t3, t1, t5 - rem s0, a3, a2 - mulhsu gp, a1, s1 - div t3, t1, t5 - c.and a0, s0 - rem s0, a3, a2 - andi s8, t1, -26 - c.and a0, s0 - c.nop - div t3, t1, t5 - div t3, t1, t5 - div t3, t1, t5 - c.andi a5, -1 - c.addi s1, 6 - slti tp, t6, 301 - mulhu tp, s3, a4 - xori a4, t0, 974 - add s7, s5, a6 - slti tp, t6, 301 - sltu t2, s1, t1 - c.li a7, 27 - sra s1, t3, s1 - c.add t1, a1 - c.addi4spn a4, sp, 288 - div t3, t1, t5 - c.xor a1, a2 - c.lui a0, 24 - c.slli t4, 28 - and a1, t3, a6 - slt t1, a1, a4 - sll t3, s7, a3 - auipc t6, 688967 - sll t3, s7, a3 - c.sub s1, a4 - ori t5, t2, 999 - nop - mulh s11, s1, s9 - c.addi s1, 6 - nop - c.nop - sltiu s6, ra, 913 - addi a7, t2, -784 - or s0, a2, a0 - or s0, a2, a0 - c.li a7, 27 - srl a0, s2, a0 - mulhsu gp, a1, s1 - mulhsu gp, a1, s1 - xor t4, s3, t3 - c.li a7, 27 - c.addi s1, 6 - nop - slti tp, t6, 301 - c.addi16sp sp, 16 - nop - srli s8, t6, 19 - nop - lui zero, 195546 - divu sp, ra, t0 - addi a7, t2, -784 - slti tp, t6, 301 - c.slli t4, 28 - c.addi16sp sp, 16 - c.slli t4, 28 - sltiu s6, ra, 913 - or s0, a2, a0 - c.mv a1, s5 - ori t5, t2, 999 - addi a7, t2, -784 - remu s5, s11, t1 - c.addi s1, 6 - c.add t1, a1 - c.or a5, a1 - c.addi4spn a4, sp, 288 - c.addi s1, 6 - c.addi16sp sp, 16 - c.addi16sp sp, 16 - mul sp, s9, s11 - sltiu s6, ra, 913 - ori t5, t2, 999 - sra s1, t3, s1 - c.lui a0, 24 - slt t1, a1, a4 - mulh s11, s1, s9 - andi s8, t1, -26 - slt t1, a1, a4 - xori a4, t0, 974 - mulhu tp, s3, a4 - add s7, s5, a6 - c.li a7, 27 - srl a0, s2, a0 - c.and a0, s0 - c.slli t4, 28 - add s7, s5, a6 - c.or a5, a1 - c.andi a5, -1 - remu s5, s11, t1 - srl a0, s2, a0 - c.addi4spn a4, sp, 288 - c.li a7, 27 - srli s8, t6, 19 - c.xor a1, a2 - addi a7, t2, -784 - c.lui a0, 24 - div t3, t1, t5 - lui zero, 195546 - c.lui a0, 24 - c.xor a1, a2 - xor t4, s3, t3 - c.lui a0, 24 - c.lui a0, 24 - sra s1, t3, s1 - c.sub s1, a4 - sltiu s6, ra, 913 - slli s11, gp, 14 - c.nop - div t3, t1, t5 - andi s8, t1, -26 - remu s5, s11, t1 - c.srai s0, 31 - sltiu s6, ra, 913 - slti tp, t6, 301 - sltiu s6, ra, 913 - sub s9, s6, s5 - sub s9, s6, s5 - c.nop - c.mv a1, s5 - c.addi s1, 6 - srl a0, s2, a0 - sltu t2, s1, t1 - xori a4, t0, 974 - auipc t6, 688967 - slti tp, t6, 301 - or s0, a2, a0 - sra s1, t3, s1 - srli s8, t6, 19 - div t3, t1, t5 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - andi s8, t1, -26 - srli s8, t6, 19 - sll t3, s7, a3 - remu s5, s11, t1 - nop - nop - c.or a5, a1 - and a1, t3, a6 - or s0, a2, a0 - c.addi s1, 6 - addi a7, t2, -784 - c.lui a0, 24 - c.srli a0, 25 - sltu t2, s1, t1 - srl a0, s2, a0 - sltiu s6, ra, 913 - sra s1, t3, s1 - c.sub s1, a4 - mulhsu gp, a1, s1 - xori a4, t0, 974 - c.nop - xor t4, s3, t3 - andi s8, t1, -26 - c.and a0, s0 - c.add t1, a1 - sll t3, s7, a3 - slti tp, t6, 301 - rem s0, a3, a2 - mulhsu gp, a1, s1 - slt t1, a1, a4 - c.srai s0, 31 - sll t3, s7, a3 - auipc t6, 688967 - c.add t1, a1 - lui zero, 195546 - addi a7, t2, -784 - slli s11, gp, 14 - xor t4, s3, t3 - c.lui a0, 24 - sra s1, t3, s1 - c.add t1, a1 - mulhsu gp, a1, s1 - c.nop - xor t4, s3, t3 - xori a4, t0, 974 - srl a0, s2, a0 - c.li a7, 27 - sltiu s6, ra, 913 - or s0, a2, a0 - c.or a5, a1 - mulh s11, s1, s9 - andi s8, t1, -26 - rem s0, a3, a2 - lui zero, 195546 - c.slli t4, 28 - sll t3, s7, a3 - c.srai s0, 31 - srli s8, t6, 19 - c.slli t4, 28 - c.addi16sp sp, 16 - slti tp, t6, 301 - c.addi s1, 6 - c.srli a0, 25 - mulhsu gp, a1, s1 - sra s1, t3, s1 - c.lui a0, 24 - lui zero, 195546 - c.srai s0, 31 - auipc t6, 688967 - xori a4, t0, 974 - auipc t6, 688967 - c.add t1, a1 - auipc t6, 688967 - srli s8, t6, 19 - addi a7, t2, -784 - mulh s11, s1, s9 - auipc t6, 688967 - slt t1, a1, a4 - slt t1, a1, a4 - mulhsu gp, a1, s1 - c.andi a5, -1 - c.lui a0, 24 - c.andi a5, -1 - c.sub s1, a4 - addi a7, t2, -784 - nop - sll t3, s7, a3 - add s7, s5, a6 - sltiu s6, ra, 913 - c.addi4spn a4, sp, 288 - c.or a5, a1 - addi a7, t2, -784 - andi s8, t1, -26 - c.li a7, 27 - andi s8, t1, -26 - c.mv a1, s5 - srl a0, s2, a0 - c.slli t4, 28 - srli s8, t6, 19 - sra s1, t3, s1 - c.and a0, s0 - sltu t2, s1, t1 - c.xor a1, a2 - sra s1, t3, s1 - div t3, t1, t5 - c.addi s1, 6 - c.andi a5, -1 - auipc t6, 688967 - divu sp, ra, t0 - and a1, t3, a6 - srli s8, t6, 19 - mulhu tp, s3, a4 - c.addi4spn a4, sp, 288 - mulhsu gp, a1, s1 - xor t4, s3, t3 - c.add t1, a1 - add s7, s5, a6 - srli s8, t6, 19 - auipc t6, 688967 - auipc t6, 688967 - srl a0, s2, a0 - c.add t1, a1 - slti tp, t6, 301 - sltu t2, s1, t1 - andi s8, t1, -26 - c.li a7, 27 - or s0, a2, a0 - srli s8, t6, 19 - xori a4, t0, 974 - rem s0, a3, a2 - c.or a5, a1 - srai s10, s1, 24 - c.srli a0, 25 - srai s10, s1, 24 - sra s1, t3, s1 - andi s8, t1, -26 - srai s10, s1, 24 - mulhsu gp, a1, s1 - sltiu s6, ra, 913 - c.srli a0, 25 - c.andi a5, -1 - c.or a5, a1 - slt t1, a1, a4 - xori a4, t0, 974 - slti tp, t6, 301 - sltu t2, s1, t1 - c.addi16sp sp, 16 - nop - xor t4, s3, t3 - c.addi16sp sp, 16 - rem s0, a3, a2 - sltu t2, s1, t1 - c.nop - xor t4, s3, t3 - mulhu tp, s3, a4 - ori t5, t2, 999 - c.or a5, a1 - c.addi s1, 6 - c.addi4spn a4, sp, 288 - c.addi s1, 6 - c.srli a0, 25 - sll t3, s7, a3 - addi a7, t2, -784 - c.or a5, a1 - sll t3, s7, a3 - mulhu tp, s3, a4 - auipc t6, 688967 - mulhsu gp, a1, s1 - rem s0, a3, a2 - nop - mulh s11, s1, s9 - srl a0, s2, a0 - mulhu tp, s3, a4 - mulh s11, s1, s9 - mul sp, s9, s11 - div t3, t1, t5 - srl a0, s2, a0 - srli s8, t6, 19 - andi s8, t1, -26 - c.addi16sp sp, 16 - sub s9, s6, s5 - c.mv a1, s5 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - ori t5, t2, 999 - divu sp, ra, t0 - c.addi4spn a4, sp, 288 - lui zero, 195546 - divu sp, ra, t0 - slli s11, gp, 14 - andi s8, t1, -26 - mul sp, s9, s11 - c.addi4spn a4, sp, 288 - mul sp, s9, s11 - c.li a7, 27 - c.addi16sp sp, 16 - srli s8, t6, 19 - auipc t6, 688967 - srai s10, s1, 24 - srl a0, s2, a0 - slli s11, gp, 14 - mulh s11, s1, s9 - lui zero, 195546 - srl a0, s2, a0 - sltu t2, s1, t1 - div t3, t1, t5 - srli s8, t6, 19 - sltiu s6, ra, 913 - sltu t2, s1, t1 - mulhsu gp, a1, s1 - c.li a7, 27 - sltiu s6, ra, 913 - c.or a5, a1 - c.or a5, a1 - andi s8, t1, -26 - c.addi s1, 6 - c.srai s0, 31 - divu sp, ra, t0 - add s7, s5, a6 - slti tp, t6, 301 - or s0, a2, a0 - divu sp, ra, t0 - remu s5, s11, t1 - c.and a0, s0 - c.or a5, a1 - c.srli a0, 25 - ori t5, t2, 999 - slli s11, gp, 14 - c.srli a0, 25 - c.lui a0, 24 - xori a4, t0, 974 - slt t1, a1, a4 - mulhsu gp, a1, s1 - and a1, t3, a6 - srl a0, s2, a0 - c.sub s1, a4 - andi s8, t1, -26 - c.addi16sp sp, 16 - c.nop - c.lui a0, 24 - ori t5, t2, 999 - mulhu tp, s3, a4 - mul sp, s9, s11 - ori t5, t2, 999 - c.add t1, a1 - srli s8, t6, 19 - remu s5, s11, t1 - c.sub s1, a4 - slt t1, a1, a4 - or s0, a2, a0 - c.srai s0, 31 - lui zero, 195546 - slt t1, a1, a4 - srli s8, t6, 19 - sll t3, s7, a3 - nop - add s7, s5, a6 - c.sub s1, a4 - slt t1, a1, a4 - sub s9, s6, s5 - slli s11, gp, 14 - add s7, s5, a6 - c.sub s1, a4 - mulhu tp, s3, a4 - div t3, t1, t5 - remu s5, s11, t1 - c.mv a1, s5 - c.addi4spn a4, sp, 288 - div t3, t1, t5 - c.addi4spn a4, sp, 288 - mulhu tp, s3, a4 - c.mv a1, s5 - mulhsu gp, a1, s1 - addi a7, t2, -784 - slli s11, gp, 14 - rem s0, a3, a2 - xor t4, s3, t3 - ori t5, t2, 999 - mulhsu gp, a1, s1 - c.srai s0, 31 - c.and a0, s0 - sra s1, t3, s1 - xori a4, t0, 974 - add s7, s5, a6 - c.and a0, s0 - ori t5, t2, 999 - sra s1, t3, s1 - srai s10, s1, 24 - mul sp, s9, s11 - mulhsu gp, a1, s1 - mulhsu gp, a1, s1 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - remu s5, s11, t1 - or s0, a2, a0 - srai s10, s1, 24 - slti tp, t6, 301 - sltu t2, s1, t1 - remu s5, s11, t1 - sub s9, s6, s5 - c.or a5, a1 - mulhsu gp, a1, s1 - sub s9, s6, s5 - sltiu s6, ra, 913 - slt t1, a1, a4 - mul sp, s9, s11 - addi a7, t2, -784 - c.srli a0, 25 - srai s10, s1, 24 - c.addi s1, 6 - mulhu tp, s3, a4 - div t3, t1, t5 - srl a0, s2, a0 - sltiu s6, ra, 913 - sub s9, s6, s5 - c.addi16sp sp, 16 - add s7, s5, a6 - add s7, s5, a6 - sll t3, s7, a3 - xor t4, s3, t3 - add s7, s5, a6 - and a1, t3, a6 - c.lui a0, 24 - c.li a7, 27 - div t3, t1, t5 - divu sp, ra, t0 - c.addi4spn a4, sp, 288 - slt t1, a1, a4 - auipc t6, 688967 - slti tp, t6, 301 - srli s8, t6, 19 - nop - ori t5, t2, 999 - c.nop - sub s9, s6, s5 - slt t1, a1, a4 - c.or a5, a1 - xori a4, t0, 974 - mulhu tp, s3, a4 - sltiu s6, ra, 913 - c.mv a1, s5 - auipc t6, 688967 - sltu t2, s1, t1 - slli s11, gp, 14 - c.slli t4, 28 - c.and a0, s0 - c.sub s1, a4 - sltu t2, s1, t1 - c.nop - mul sp, s9, s11 - c.slli t4, 28 - divu sp, ra, t0 - slli s11, gp, 14 - sub s9, s6, s5 - xor t4, s3, t3 - c.sub s1, a4 - slti tp, t6, 301 - sub s9, s6, s5 - sltiu s6, ra, 913 - srl a0, s2, a0 - srli s8, t6, 19 - remu s5, s11, t1 - c.srai s0, 31 - srli s8, t6, 19 - addi a7, t2, -784 - c.and a0, s0 - slt t1, a1, a4 - srl a0, s2, a0 - mulhsu gp, a1, s1 - c.addi16sp sp, 16 - xor t4, s3, t3 - sltiu s6, ra, 913 - sub s9, s6, s5 - c.add t1, a1 - c.srli a0, 25 - ori t5, t2, 999 - mul sp, s9, s11 - sll t3, s7, a3 - or s0, a2, a0 - lui zero, 195546 - srl a0, s2, a0 - or s0, a2, a0 - c.mv a1, s5 - add s7, s5, a6 - xori a4, t0, 974 - c.and a0, s0 - lui zero, 195546 - add s7, s5, a6 - add s7, s5, a6 - srli s8, t6, 19 - srai s10, s1, 24 - rem s0, a3, a2 - mulh s11, s1, s9 - c.andi a5, -1 - slti tp, t6, 301 - or s0, a2, a0 - c.slli t4, 28 - srl a0, s2, a0 - srli s8, t6, 19 - c.sub s1, a4 - sltiu s6, ra, 913 - xori a4, t0, 974 - slti tp, t6, 301 - slli s11, gp, 14 - remu s5, s11, t1 - sra s1, t3, s1 - sub s9, s6, s5 - slli s11, gp, 14 - lui zero, 195546 - lui zero, 195546 - rem s0, a3, a2 - rem s0, a3, a2 - divu sp, ra, t0 - rem s0, a3, a2 - sltu t2, s1, t1 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - c.srli a0, 25 - xori a4, t0, 974 - addi a7, t2, -784 - c.or a5, a1 - rem s0, a3, a2 - add s7, s5, a6 - srai s10, s1, 24 - srli s8, t6, 19 - sltu t2, s1, t1 - c.nop - add s7, s5, a6 - c.lui a0, 24 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - auipc t6, 688967 - mulhu tp, s3, a4 - c.li a7, 27 - andi s8, t1, -26 - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - sltu t2, s1, t1 - c.or a5, a1 - c.li a7, 27 - sltiu s6, ra, 913 - ori t5, t2, 999 - c.xor a1, a2 - c.andi a5, -1 - c.mv a1, s5 - ori t5, t2, 999 - auipc t6, 688967 - c.nop - c.add t1, a1 - mulhsu gp, a1, s1 - c.andi a5, -1 - mulhsu gp, a1, s1 - remu s5, s11, t1 - divu sp, ra, t0 - c.li a7, 27 - c.slli t4, 28 - c.li a7, 27 - slt t1, a1, a4 - sltu t2, s1, t1 - xor t4, s3, t3 - c.li a7, 27 - c.li a7, 27 - xor t4, s3, t3 - c.andi a5, -1 - remu s5, s11, t1 - add s7, s5, a6 - slt t1, a1, a4 - and a1, t3, a6 - c.slli t4, 28 - mulhu tp, s3, a4 - c.add t1, a1 - mulhsu gp, a1, s1 - mulhsu gp, a1, s1 - c.mv a1, s5 - mulh s11, s1, s9 - sub s9, s6, s5 - mul sp, s9, s11 - lui zero, 195546 - srl a0, s2, a0 - and a1, t3, a6 - c.addi16sp sp, 16 - mul sp, s9, s11 - remu s5, s11, t1 - c.xor a1, a2 - c.addi16sp sp, 16 - c.addi16sp sp, 16 - or s0, a2, a0 - or s0, a2, a0 - lui zero, 195546 - slt t1, a1, a4 - c.lui a0, 24 - c.andi a5, -1 - rem s0, a3, a2 - c.addi s1, 6 - c.add t1, a1 - sltu t2, s1, t1 - c.lui a0, 24 - c.srai s0, 31 - mulh s11, s1, s9 - srai s10, s1, 24 - xori a4, t0, 974 - andi s8, t1, -26 - andi s8, t1, -26 - c.li a7, 27 - srai s10, s1, 24 - mul sp, s9, s11 - c.mv a1, s5 - lui zero, 195546 - mulhu tp, s3, a4 - nop - auipc t6, 688967 - nop - c.srli a0, 25 - c.li a7, 27 - nop - mul sp, s9, s11 - c.nop - mulh s11, s1, s9 - lui zero, 195546 - c.srai s0, 31 - c.lui a0, 24 - c.slli t4, 28 - slt t1, a1, a4 - add s7, s5, a6 - and a1, t3, a6 - c.addi4spn a4, sp, 288 - c.addi4spn a4, sp, 288 - div t3, t1, t5 - c.lui a0, 24 - add s7, s5, a6 - lui zero, 195546 - div t3, t1, t5 - slti tp, t6, 301 - c.addi4spn a4, sp, 288 - srai s10, s1, 24 - rem s0, a3, a2 - c.lui a0, 24 - slli s11, gp, 14 - c.xor a1, a2 - andi s8, t1, -26 - sltiu s6, ra, 913 - lui zero, 195546 - sltiu s6, ra, 913 - xori a4, t0, 974 - and a1, t3, a6 - and a1, t3, a6 - sub s9, s6, s5 - rem s0, a3, a2 - c.slli t4, 28 - c.li a7, 27 - c.xor a1, a2 - nop - divu sp, ra, t0 - c.addi16sp sp, 16 - c.nop - auipc t6, 688967 - c.mv a1, s5 - xor t4, s3, t3 - and a1, t3, a6 - srl a0, s2, a0 - slli s11, gp, 14 - addi a7, t2, -784 - andi s8, t1, -26 - c.xor a1, a2 - mulhu tp, s3, a4 - c.addi4spn a4, sp, 288 - srai s10, s1, 24 - c.add t1, a1 - srli s8, t6, 19 - c.slli t4, 28 - c.srai s0, 31 - c.slli t4, 28 - addi a7, t2, -784 - srl a0, s2, a0 - c.srli a0, 25 - sltiu s6, ra, 913 - c.xor a1, a2 - sll t3, s7, a3 - auipc t6, 688967 - c.andi a5, -1 - slti tp, t6, 301 - xori a4, t0, 974 - c.mv a1, s5 - remu s5, s11, t1 - c.srli a0, 25 - c.add t1, a1 - xori a4, t0, 974 - sltu t2, s1, t1 - remu s5, s11, t1 - auipc t6, 688967 - addi a7, t2, -784 - c.and a0, s0 - c.add t1, a1 - mulhsu gp, a1, s1 - srl a0, s2, a0 - addi a7, t2, -784 - andi s8, t1, -26 - mul sp, s9, s11 - sub s9, s6, s5 - c.andi a5, -1 - c.andi a5, -1 - slti tp, t6, 301 - ori t5, t2, 999 - c.lui a0, 24 - c.slli t4, 28 - srli s8, t6, 19 - c.add t1, a1 - and a1, t3, a6 - xor t4, s3, t3 - c.addi4spn a4, sp, 288 - c.mv a1, s5 - sra s1, t3, s1 - lui zero, 195546 - andi s8, t1, -26 - sll t3, s7, a3 - c.xor a1, a2 - xori a4, t0, 974 - srli s8, t6, 19 - c.and a0, s0 - c.li a7, 27 - slt t1, a1, a4 - c.addi4spn a4, sp, 288 - c.addi4spn a4, sp, 288 - sltiu s6, ra, 913 - c.addi4spn a4, sp, 288 - mul sp, s9, s11 - c.mv a1, s5 - nop - add s7, s5, a6 - remu s5, s11, t1 - c.xor a1, a2 - c.andi a5, -1 - lui zero, 195546 - or s0, a2, a0 - remu s5, s11, t1 - slti tp, t6, 301 - sub s9, s6, s5 - c.nop - andi s8, t1, -26 - auipc t6, 688967 - c.slli t4, 28 - mulh s11, s1, s9 - sltiu s6, ra, 913 - and a1, t3, a6 - lui zero, 195546 - slti tp, t6, 301 - c.mv a1, s5 - sll t3, s7, a3 - xori a4, t0, 974 - nop - c.li a7, 27 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - c.mv a1, s5 - div t3, t1, t5 - c.and a0, s0 - sub s9, s6, s5 - mulhu tp, s3, a4 - or s0, a2, a0 - div t3, t1, t5 - srli s8, t6, 19 - c.xor a1, a2 - srai s10, s1, 24 - slt t1, a1, a4 - c.slli t4, 28 - c.addi16sp sp, 16 - c.or a5, a1 - c.sub s1, a4 - mulh s11, s1, s9 - sub s9, s6, s5 - sub s9, s6, s5 - lui zero, 195546 - mulhsu gp, a1, s1 - addi a7, t2, -784 - slti tp, t6, 301 - c.add t1, a1 - srli s8, t6, 19 - slli s11, gp, 14 - mulhsu gp, a1, s1 - c.and a0, s0 - srli s8, t6, 19 - c.addi s1, 6 - or s0, a2, a0 - sll t3, s7, a3 - remu s5, s11, t1 - ori t5, t2, 999 - c.addi4spn a4, sp, 288 - c.and a0, s0 - sltiu s6, ra, 913 - ori t5, t2, 999 - sub s9, s6, s5 - sra s1, t3, s1 - c.add t1, a1 - add s7, s5, a6 - srl a0, s2, a0 - sub s9, s6, s5 - sra s1, t3, s1 - xor t4, s3, t3 - c.slli t4, 28 - slti tp, t6, 301 - ori t5, t2, 999 - mul sp, s9, s11 - and a1, t3, a6 - mulhu tp, s3, a4 - auipc t6, 688967 - addi a7, t2, -784 - c.li a7, 27 - mulhu tp, s3, a4 - slt t1, a1, a4 - c.andi a5, -1 - c.lui a0, 24 - srai s10, s1, 24 - remu s5, s11, t1 - c.lui a0, 24 - c.andi a5, -1 - sll t3, s7, a3 - mulhsu gp, a1, s1 - c.addi s1, 6 - c.mv a1, s5 - c.slli t4, 28 - c.slli t4, 28 - srl a0, s2, a0 - c.or a5, a1 - div t3, t1, t5 - sltiu s6, ra, 913 - srli s8, t6, 19 - c.lui a0, 24 - c.sub s1, a4 - c.lui a0, 24 - c.addi4spn a4, sp, 288 - mulh s11, s1, s9 - or s0, a2, a0 - sltu t2, s1, t1 - c.xor a1, a2 - remu s5, s11, t1 - c.and a0, s0 - add s7, s5, a6 - divu sp, ra, t0 - remu s5, s11, t1 - c.add t1, a1 - c.and a0, s0 - mulhu tp, s3, a4 - c.or a5, a1 - and a1, t3, a6 - sra s1, t3, s1 - c.andi a5, -1 - sltu t2, s1, t1 - c.xor a1, a2 - srl a0, s2, a0 - sub s9, s6, s5 - c.lui a0, 24 - sub s9, s6, s5 - ori t5, t2, 999 - sltu t2, s1, t1 - or s0, a2, a0 - sub s9, s6, s5 - sll t3, s7, a3 - slti tp, t6, 301 - andi s8, t1, -26 - mul sp, s9, s11 - ori t5, t2, 999 - ori t5, t2, 999 - addi a7, t2, -784 - c.srli a0, 25 - srli s8, t6, 19 - nop - c.xor a1, a2 - c.sub s1, a4 - c.xor a1, a2 - mulhu tp, s3, a4 - mulh s11, s1, s9 - c.srai s0, 31 - divu sp, ra, t0 - c.andi a5, -1 - sra s1, t3, s1 - c.lui a0, 24 - c.srai s0, 31 - c.or a5, a1 - remu s5, s11, t1 - auipc t6, 688967 - mulhu tp, s3, a4 - mul sp, s9, s11 - slt t1, a1, a4 - c.srli a0, 25 - c.and a0, s0 - mulhu tp, s3, a4 - xor t4, s3, t3 - lui zero, 195546 - sltu t2, s1, t1 - c.mv a1, s5 - c.nop - xori a4, t0, 974 - c.add t1, a1 - slt t1, a1, a4 - c.nop - sltu t2, s1, t1 - c.srai s0, 31 - rem s0, a3, a2 - mulh s11, s1, s9 - mulhsu gp, a1, s1 - slli s11, gp, 14 - c.slli t4, 28 - mulhsu gp, a1, s1 - sub s9, s6, s5 - c.and a0, s0 - c.or a5, a1 - slli s11, gp, 14 - c.andi a5, -1 - c.srli a0, 25 - rem s0, a3, a2 - and a1, t3, a6 - c.and a0, s0 - sltiu s6, ra, 913 - slt t1, a1, a4 - srl a0, s2, a0 - nop - mul sp, s9, s11 - c.nop - sltiu s6, ra, 913 - sll t3, s7, a3 - c.nop - c.sub s1, a4 - c.nop - srl a0, s2, a0 - c.mv a1, s5 - slt t1, a1, a4 - sltu t2, s1, t1 - c.nop - divu sp, ra, t0 - c.addi16sp sp, 16 - c.lui a0, 24 - c.nop - c.addi16sp sp, 16 - slt t1, a1, a4 - c.srai s0, 31 - remu s5, s11, t1 - mulhsu gp, a1, s1 - slt t1, a1, a4 - sub s9, s6, s5 - slt t1, a1, a4 - c.li a7, 27 - addi a7, t2, -784 - xor t4, s3, t3 - add s7, s5, a6 - c.slli t4, 28 - ori t5, t2, 999 - srli s8, t6, 19 - slt t1, a1, a4 - sub s9, s6, s5 - rem s0, a3, a2 - ori t5, t2, 999 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - add s7, s5, a6 - c.sub s1, a4 - c.addi s1, 6 - mulh s11, s1, s9 - lui zero, 195546 - c.addi16sp sp, 16 - div t3, t1, t5 - c.addi4spn a4, sp, 288 - c.addi16sp sp, 16 - sltu t2, s1, t1 - ori t5, t2, 999 - c.nop - c.addi16sp sp, 16 - c.or a5, a1 - auipc t6, 688967 - lui zero, 195546 - c.add t1, a1 - c.srli a0, 25 - c.srli a0, 25 - divu sp, ra, t0 - c.addi4spn a4, sp, 288 - c.nop - c.addi16sp sp, 16 - rem s0, a3, a2 - c.nop - remu s5, s11, t1 - c.mv a1, s5 - mulhsu gp, a1, s1 - add s7, s5, a6 - mulhu tp, s3, a4 - sll t3, s7, a3 - sltiu s6, ra, 913 - c.lui a0, 24 - xor t4, s3, t3 - c.srai s0, 31 - c.and a0, s0 - auipc t6, 688967 - xori a4, t0, 974 - c.mv a1, s5 - add s7, s5, a6 - xori a4, t0, 974 - sll t3, s7, a3 - xor t4, s3, t3 - xor t4, s3, t3 - slli s11, gp, 14 - c.lui a0, 24 - c.addi16sp sp, 16 - srai s10, s1, 24 - mulhsu gp, a1, s1 - addi a7, t2, -784 - or s0, a2, a0 - c.addi s1, 6 - c.addi4spn a4, sp, 288 - sub s9, s6, s5 - slli s11, gp, 14 - sra s1, t3, s1 - sltu t2, s1, t1 - add s7, s5, a6 - srli s8, t6, 19 - c.or a5, a1 - remu s5, s11, t1 - c.srai s0, 31 - divu sp, ra, t0 - c.xor a1, a2 - ori t5, t2, 999 - c.add t1, a1 - mulh s11, s1, s9 - or s0, a2, a0 - addi a7, t2, -784 - c.addi16sp sp, 16 - srl a0, s2, a0 - divu sp, ra, t0 - sra s1, t3, s1 - c.sub s1, a4 - addi a7, t2, -784 - c.addi16sp sp, 16 - mul sp, s9, s11 - sll t3, s7, a3 - c.addi s1, 6 - mulh s11, s1, s9 - mul sp, s9, s11 - sltiu s6, ra, 913 - srai s10, s1, 24 - srli s8, t6, 19 - c.sub s1, a4 - andi s8, t1, -26 - c.srli a0, 25 - c.xor a1, a2 - sub s9, s6, s5 - c.nop - c.addi4spn a4, sp, 288 - c.andi a5, -1 - srl a0, s2, a0 - c.or a5, a1 - andi s8, t1, -26 - c.slli t4, 28 - xori a4, t0, 974 - c.andi a5, -1 - xori a4, t0, 974 - xor t4, s3, t3 - c.slli t4, 28 - c.li a7, 27 - c.lui a0, 24 - add s7, s5, a6 - mulhsu gp, a1, s1 - srl a0, s2, a0 - andi s8, t1, -26 - srl a0, s2, a0 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - lui zero, 195546 - c.andi a5, -1 - lui zero, 195546 - nop - remu s5, s11, t1 - divu sp, ra, t0 - c.or a5, a1 - andi s8, t1, -26 - c.mv a1, s5 - addi a7, t2, -784 - slli s11, gp, 14 - addi a7, t2, -784 - ori t5, t2, 999 - slti tp, t6, 301 - mulhsu gp, a1, s1 - c.srai s0, 31 - mulhsu gp, a1, s1 - c.sub s1, a4 - sub s9, s6, s5 - srli s8, t6, 19 - add s7, s5, a6 - add s7, s5, a6 - srai s10, s1, 24 - mulh s11, s1, s9 - and a1, t3, a6 - c.or a5, a1 - c.mv a1, s5 - sub s9, s6, s5 - mulhu tp, s3, a4 - c.sub s1, a4 - c.li a7, 27 - c.or a5, a1 - c.addi s1, 6 - sll t3, s7, a3 - mulhsu gp, a1, s1 - xori a4, t0, 974 - andi s8, t1, -26 - c.and a0, s0 - slli s11, gp, 14 - addi a7, t2, -784 - c.srai s0, 31 - c.addi4spn a4, sp, 288 - c.xor a1, a2 - xor t4, s3, t3 - divu sp, ra, t0 - auipc t6, 688967 - c.add t1, a1 - add s7, s5, a6 - c.andi a5, -1 - sra s1, t3, s1 - addi a7, t2, -784 - and a1, t3, a6 - c.mv a1, s5 - c.and a0, s0 - remu s5, s11, t1 - sltu t2, s1, t1 - c.add t1, a1 - add s7, s5, a6 - xor t4, s3, t3 - rem s0, a3, a2 - c.and a0, s0 - ori t5, t2, 999 - c.addi s1, 6 - c.srli a0, 25 - div t3, t1, t5 - c.xor a1, a2 - c.sub s1, a4 - div t3, t1, t5 - srl a0, s2, a0 - slti tp, t6, 301 - c.or a5, a1 - c.sub s1, a4 - mulhu tp, s3, a4 - mulhsu gp, a1, s1 - c.li a7, 27 - c.nop - lui zero, 195546 - addi a7, t2, -784 - andi s8, t1, -26 - addi a7, t2, -784 - c.add t1, a1 - slti tp, t6, 301 - sub s9, s6, s5 - sll t3, s7, a3 - xori a4, t0, 974 - rem s0, a3, a2 - sltiu s6, ra, 913 - c.mv a1, s5 - andi s8, t1, -26 - andi s8, t1, -26 - nop - srai s10, s1, 24 - xori a4, t0, 974 - nop - c.slli t4, 28 - auipc t6, 688967 - c.srai s0, 31 - sub s9, s6, s5 - mulhsu gp, a1, s1 - divu sp, ra, t0 - sra s1, t3, s1 - srai s10, s1, 24 - sll t3, s7, a3 - div t3, t1, t5 - addi a7, t2, -784 - or s0, a2, a0 - sra s1, t3, s1 - divu sp, ra, t0 - mulhu tp, s3, a4 - c.slli t4, 28 - c.slli t4, 28 - slt t1, a1, a4 - c.mv a1, s5 - srli s8, t6, 19 - li s5, 0x0 #start riscv_int_numeric_corner_stream_6 - li s11, 0x80000000 - li s3, 0xd6366199 - li s7, 0x80000000 - li t6, 0xffffffff - li tp, 0xffffffff - li a1, 0x80000000 - li t5, 0x0 - li s9, 0x0 - li s6, 0x80000000 - addi tp, s5, 999 - nop - nop - mulh a1, s7, s5 - mulhu s9, tp, tp - addi tp, s5, 999 - remu s5, s11, s6 - addi tp, s5, 999 - lui tp, 195546 - rem t5, tp, a1 - div s3, s3, t5 - mul s5, s6, t5 - sub s5, s5, tp - div s3, s3, t5 - mul s5, s6, t5 #end riscv_int_numeric_corner_stream_6 - c.xor a1, a2 - sra s1, t3, s1 - slti tp, t6, 301 - xori a4, t0, 974 - c.sub s1, a4 - xor t4, s3, t3 - c.andi a5, -1 - c.addi4spn a4, sp, 288 - mulh s11, s1, s9 - srai s10, s1, 24 - c.lui a0, 24 - mulh s11, s1, s9 - auipc t6, 688967 - div t3, t1, t5 - srai s10, s1, 24 - c.or a5, a1 - mulhsu gp, a1, s1 - ori t5, t2, 999 - c.xor a1, a2 - mulhsu gp, a1, s1 - c.mv a1, s5 - mulhu tp, s3, a4 - nop - c.xor a1, a2 - nop - c.addi16sp sp, 16 - c.or a5, a1 - c.addi s1, 6 - add s7, s5, a6 - c.li a7, 27 - xor t4, s3, t3 - remu s5, s11, t1 - mulhsu gp, a1, s1 - srai s10, s1, 24 - c.li a7, 27 - c.nop - addi a7, t2, -784 - sll t3, s7, a3 - slt t1, a1, a4 - addi a7, t2, -784 - c.srai s0, 31 - c.lui a0, 24 - c.or a5, a1 - mulhu tp, s3, a4 - slti tp, t6, 301 - mul sp, s9, s11 - c.mv a1, s5 - mulhsu gp, a1, s1 - ori t5, t2, 999 - slti tp, t6, 301 - auipc t6, 688967 - xor t4, s3, t3 - c.srai s0, 31 - auipc t6, 688967 - mulhsu gp, a1, s1 - c.andi a5, -1 - xor t4, s3, t3 - auipc t6, 688967 - c.srai s0, 31 - c.or a5, a1 - divu sp, ra, t0 - c.nop - div t3, t1, t5 - mulhu tp, s3, a4 - c.srli a0, 25 - rem s0, a3, a2 - mulh s11, s1, s9 - ori t5, t2, 999 - srl a0, s2, a0 - c.or a5, a1 - sltu t2, s1, t1 - c.mv a1, s5 - c.add t1, a1 - sra s1, t3, s1 - sltiu s6, ra, 913 - sra s1, t3, s1 - slli s11, gp, 14 - c.srai s0, 31 - c.and a0, s0 - c.andi a5, -1 - slt t1, a1, a4 - sub s9, s6, s5 - srli s8, t6, 19 - sltu t2, s1, t1 - slti tp, t6, 301 - c.li a7, 27 - mulhu tp, s3, a4 - c.andi a5, -1 - sll t3, s7, a3 - mulhu tp, s3, a4 - divu sp, ra, t0 - andi s8, t1, -26 - add s7, s5, a6 - c.srli a0, 25 - xori a4, t0, 974 - c.lui a0, 24 - c.and a0, s0 - auipc t6, 688967 - divu sp, ra, t0 - divu sp, ra, t0 - sra s1, t3, s1 - slti tp, t6, 301 - ori t5, t2, 999 - mulhu tp, s3, a4 - or s0, a2, a0 - srl a0, s2, a0 - slti tp, t6, 301 - xori a4, t0, 974 - srai s10, s1, 24 - xori a4, t0, 974 - sub s9, s6, s5 - c.slli t4, 28 - add s7, s5, a6 - c.slli t4, 28 - c.add t1, a1 - srai s10, s1, 24 - c.srai s0, 31 - mulh s11, s1, s9 - lui zero, 195546 - c.xor a1, a2 - mulhsu gp, a1, s1 - add s7, s5, a6 - lui zero, 195546 - c.nop - c.xor a1, a2 - mul sp, s9, s11 - lui zero, 195546 - sltiu s6, ra, 913 - sub s9, s6, s5 - slt t1, a1, a4 - c.addi16sp sp, 16 - slli s11, gp, 14 - c.li a7, 27 - c.mv a1, s5 - slli s11, gp, 14 - c.slli t4, 28 - c.slli t4, 28 - addi a7, t2, -784 - c.srli a0, 25 - srli s8, t6, 19 - srl a0, s2, a0 - sub s9, s6, s5 - c.andi a5, -1 - sub s9, s6, s5 - c.xor a1, a2 - c.slli t4, 28 - c.srai s0, 31 - div t3, t1, t5 - slli s11, gp, 14 - c.addi s1, 6 - sll t3, s7, a3 - c.lui a0, 24 - c.addi4spn a4, sp, 288 - andi s8, t1, -26 - c.li a7, 27 - and a1, t3, a6 - c.nop - c.addi4spn a4, sp, 288 - c.addi4spn a4, sp, 288 - c.sub s1, a4 - srai s10, s1, 24 - c.lui a0, 24 - srli s8, t6, 19 - c.lui a0, 24 - c.addi4spn a4, sp, 288 - c.and a0, s0 - c.andi a5, -1 - srai s10, s1, 24 - auipc t6, 688967 - c.nop - sll t3, s7, a3 - nop - remu s5, s11, t1 - c.add t1, a1 - divu sp, ra, t0 - divu sp, ra, t0 - c.and a0, s0 - srai s10, s1, 24 - c.andi a5, -1 - divu sp, ra, t0 - slti tp, t6, 301 - c.or a5, a1 - mul sp, s9, s11 - or s0, a2, a0 - mul sp, s9, s11 - slt t1, a1, a4 - c.sub s1, a4 - sub s9, s6, s5 - mulhu tp, s3, a4 - sub s9, s6, s5 - srli s8, t6, 19 - andi s8, t1, -26 - add s7, s5, a6 - c.addi s1, 6 - div t3, t1, t5 - and a1, t3, a6 - divu sp, ra, t0 - slt t1, a1, a4 - srli s8, t6, 19 - sltiu s6, ra, 913 - sub s9, s6, s5 - nop - c.srli a0, 25 - c.slli t4, 28 - mulh s11, s1, s9 - c.addi16sp sp, 16 - c.or a5, a1 - lui zero, 195546 - c.slli t4, 28 - ori t5, t2, 999 - mulhu tp, s3, a4 - c.li a7, 27 - c.add t1, a1 - c.and a0, s0 - c.lui a0, 24 - c.addi16sp sp, 16 - srai s10, s1, 24 - xori a4, t0, 974 - ori t5, t2, 999 - and a1, t3, a6 - andi s8, t1, -26 - c.and a0, s0 - rem s0, a3, a2 - c.slli t4, 28 - c.srli a0, 25 - sub s9, s6, s5 - mul sp, s9, s11 - c.li a7, 27 - sll t3, s7, a3 - srl a0, s2, a0 - c.lui a0, 24 - sra s1, t3, s1 - c.srli a0, 25 - or s0, a2, a0 - c.srai s0, 31 - mul sp, s9, s11 - c.lui a0, 24 - mulh s11, s1, s9 - sltu t2, s1, t1 - xor t4, s3, t3 - c.andi a5, -1 - c.and a0, s0 - c.addi s1, 6 - sll t3, s7, a3 - c.xor a1, a2 - c.li a7, 27 - c.mv a1, s5 - c.srai s0, 31 - rem s0, a3, a2 - c.srli a0, 25 - c.nop - mulhu tp, s3, a4 - lui zero, 195546 - c.sub s1, a4 - ori t5, t2, 999 - srli s8, t6, 19 - c.nop - slti tp, t6, 301 - div t3, t1, t5 - c.srai s0, 31 - sra s1, t3, s1 - c.srai s0, 31 - c.addi16sp sp, 16 - c.addi s1, 6 - mulhu tp, s3, a4 - c.nop - slt t1, a1, a4 - addi a7, t2, -784 - rem s0, a3, a2 - c.addi4spn a4, sp, 288 - xor t4, s3, t3 - srli s8, t6, 19 - mulh s11, s1, s9 - slli s11, gp, 14 - sll t3, s7, a3 - c.lui a0, 24 - and a1, t3, a6 - remu s5, s11, t1 - or s0, a2, a0 - sra s1, t3, s1 - srl a0, s2, a0 - slli s11, gp, 14 - and a1, t3, a6 - srai s10, s1, 24 - mulhsu gp, a1, s1 - c.nop - mulh s11, s1, s9 - c.slli t4, 28 - div t3, t1, t5 - andi s8, t1, -26 - xori a4, t0, 974 - or s0, a2, a0 - c.xor a1, a2 - xor t4, s3, t3 - c.sub s1, a4 - c.srai s0, 31 - c.sub s1, a4 - mulhu tp, s3, a4 - slt t1, a1, a4 - c.li a7, 27 - and a1, t3, a6 - sltiu s6, ra, 913 - mulh s11, s1, s9 - mulh s11, s1, s9 - c.srai s0, 31 - c.lui a0, 24 - sll t3, s7, a3 - c.add t1, a1 - srai s10, s1, 24 - remu s5, s11, t1 - addi a7, t2, -784 - j fast_exit - -#Start: Extracted from riscv_compliance_tests/riscv_test.h -fast_exit: - /* print "\nDONE\n\n" */ - lui a0,print_port>>12 - addi a1,zero,'D' - addi a2,zero,'O' - addi a3,zero,'N' - addi a4,zero,'E' - addi a5,zero,'\n' - sw a5,0(a0) - sw a1,0(a0) - sw a2,0(a0) - sw a3,0(a0) - sw a4,0(a0) - sw a5,0(a0) - sw a5,0(a0) - - li a0, CV_VP_STATUS_FLAGS_BASE - lw a1, test_results /* report result */ - sw a1,0(a0) - - wfi /* we are done */ -##End: Extracted from riscv_compliance_tests/riscv_test.h - - j test_done -test_done: - li gp, 1 - ecall -write_tohost: - sw gp, tohost, t5 - -_exit: - j write_tohost - -init_machine_mode: - li x30, 0x1800 - csrw 0x300, x30 # MSTATUS - li x30, 0x0 - csrw 0x304, x30 # MIE - mret -instr_end: - nop - -.section .data -.align 6; .global tohost; tohost: .dword 0; -.align 6; .global fromhost; fromhost: .dword 0; -.section .user_stack,"aw",@progbits; -.align 2 -user_stack_start: -.rept 4999 -.4byte 0x0 -.endr -user_stack_end: -.4byte 0x0 -.align 2 -kernel_instr_start: -.text -mmode_intr_vector_1: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_2: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_3: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_4: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_5: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_6: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_7: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_8: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_9: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_10: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_11: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_12: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_13: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_14: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_15: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x342 # MCAUSE - srli x30, x30, 0x1f - beqz x30, 1f - j mmode_intr_handler - 1: j test_done - -.align 2 -mtvec_handler: - .option norvc; - j mmode_exception_handler - j mmode_intr_vector_1 - j mmode_intr_vector_2 - j mmode_intr_vector_3 - j mmode_intr_vector_4 - j mmode_intr_vector_5 - j mmode_intr_vector_6 - j mmode_intr_vector_7 - j mmode_intr_vector_8 - j mmode_intr_vector_9 - j mmode_intr_vector_10 - j mmode_intr_vector_11 - j mmode_intr_vector_12 - j mmode_intr_vector_13 - j mmode_intr_vector_14 - j mmode_intr_vector_15 - .option rvc; - -mmode_exception_handler: - csrrw x12, 0x340, x12 - add x12, x13, zero - 1: addi x12, x12, -124 - sw x1, 4(x12) - sw x2, 8(x12) - sw x3, 12(x12) - sw x4, 16(x12) - sw x5, 20(x12) - sw x6, 24(x12) - sw x7, 28(x12) - sw x8, 32(x12) - sw x9, 36(x12) - sw x10, 40(x12) - sw x11, 44(x12) - sw x12, 48(x12) - sw x13, 52(x12) - sw x14, 56(x12) - sw x15, 60(x12) - sw x16, 64(x12) - sw x17, 68(x12) - sw x18, 72(x12) - sw x19, 76(x12) - sw x20, 80(x12) - sw x21, 84(x12) - sw x22, 88(x12) - sw x23, 92(x12) - sw x24, 96(x12) - sw x25, 100(x12) - sw x26, 104(x12) - sw x27, 108(x12) - sw x28, 112(x12) - sw x29, 116(x12) - sw x30, 120(x12) - sw x31, 124(x12) - csrr x30, 0x341 # MEPC - csrr x30, 0x342 # MCAUSE - li x22, 0x3 # BREAKPOINT - beq x30, x22, ebreak_handler - li x22, 0x8 # ECALL_UMODE - beq x30, x22, ecall_handler - li x22, 0x9 # ECALL_SMODE - beq x30, x22, ecall_handler - li x22, 0xb # ECALL_MMODE - beq x30, x22, ecall_handler - li x22, 0x1 - beq x30, x22, instr_fault_handler - li x22, 0x5 - beq x30, x22, load_fault_handler - li x22, 0x7 - beq x30, x22, store_fault_handler - li x22, 0xc - beq x30, x22, pt_fault_handler - li x22, 0xd - beq x30, x22, pt_fault_handler - li x22, 0xf - beq x30, x22, pt_fault_handler - li x22, 0x2 # ILLEGAL_INSTRUCTION - beq x30, x22, illegal_instr_handler - csrr x22, 0x343 # MTVAL - 1: jal x1, test_done - -ecall_handler: - la x30, _start - sw x0, 0(x30) - sw x1, 4(x30) - sw x2, 8(x30) - sw x3, 12(x30) - sw x4, 16(x30) - sw x5, 20(x30) - sw x6, 24(x30) - sw x7, 28(x30) - sw x8, 32(x30) - sw x9, 36(x30) - sw x10, 40(x30) - sw x11, 44(x30) - sw x12, 48(x30) - sw x13, 52(x30) - sw x14, 56(x30) - sw x15, 60(x30) - sw x16, 64(x30) - sw x17, 68(x30) - sw x18, 72(x30) - sw x19, 76(x30) - sw x20, 80(x30) - sw x21, 84(x30) - sw x22, 88(x30) - sw x23, 92(x30) - sw x24, 96(x30) - sw x25, 100(x30) - sw x26, 104(x30) - sw x27, 108(x30) - sw x28, 112(x30) - sw x29, 116(x30) - sw x30, 120(x30) - sw x31, 124(x30) - j write_tohost -instr_fault_handler: - lw x1, 4(x12) - lw x2, 8(x12) - lw x3, 12(x12) - lw x4, 16(x12) - lw x5, 20(x12) - lw x6, 24(x12) - lw x7, 28(x12) - lw x8, 32(x12) - lw x9, 36(x12) - lw x10, 40(x12) - lw x11, 44(x12) - lw x12, 48(x12) - lw x13, 52(x12) - lw x14, 56(x12) - lw x15, 60(x12) - lw x16, 64(x12) - lw x17, 68(x12) - lw x18, 72(x12) - lw x19, 76(x12) - lw x20, 80(x12) - lw x21, 84(x12) - lw x22, 88(x12) - lw x23, 92(x12) - lw x24, 96(x12) - lw x25, 100(x12) - lw x26, 104(x12) - lw x27, 108(x12) - lw x28, 112(x12) - lw x29, 116(x12) - lw x30, 120(x12) - lw x31, 124(x12) - addi x12, x12, 124 - add x13, x12, zero - csrrw x12, 0x340, x12 - mret - -load_fault_handler: - lw x1, 4(x12) - lw x2, 8(x12) - lw x3, 12(x12) - lw x4, 16(x12) - lw x5, 20(x12) - lw x6, 24(x12) - lw x7, 28(x12) - lw x8, 32(x12) - lw x9, 36(x12) - lw x10, 40(x12) - lw x11, 44(x12) - lw x12, 48(x12) - lw x13, 52(x12) - lw x14, 56(x12) - lw x15, 60(x12) - lw x16, 64(x12) - lw x17, 68(x12) - lw x18, 72(x12) - lw x19, 76(x12) - lw x20, 80(x12) - lw x21, 84(x12) - lw x22, 88(x12) - lw x23, 92(x12) - lw x24, 96(x12) - lw x25, 100(x12) - lw x26, 104(x12) - lw x27, 108(x12) - lw x28, 112(x12) - lw x29, 116(x12) - lw x30, 120(x12) - lw x31, 124(x12) - addi x12, x12, 124 - add x13, x12, zero - csrrw x12, 0x340, x12 - mret - -store_fault_handler: - lw x1, 4(x12) - lw x2, 8(x12) - lw x3, 12(x12) - lw x4, 16(x12) - lw x5, 20(x12) - lw x6, 24(x12) - lw x7, 28(x12) - lw x8, 32(x12) - lw x9, 36(x12) - lw x10, 40(x12) - lw x11, 44(x12) - lw x12, 48(x12) - lw x13, 52(x12) - lw x14, 56(x12) - lw x15, 60(x12) - lw x16, 64(x12) - lw x17, 68(x12) - lw x18, 72(x12) - lw x19, 76(x12) - lw x20, 80(x12) - lw x21, 84(x12) - lw x22, 88(x12) - lw x23, 92(x12) - lw x24, 96(x12) - lw x25, 100(x12) - lw x26, 104(x12) - lw x27, 108(x12) - lw x28, 112(x12) - lw x29, 116(x12) - lw x30, 120(x12) - lw x31, 124(x12) - addi x12, x12, 124 - add x13, x12, zero - csrrw x12, 0x340, x12 - mret - -ebreak_handler: - csrr x30, mepc - addi x30, x30, 4 - csrw mepc, x30 - lw x1, 4(x12) - lw x2, 8(x12) - lw x3, 12(x12) - lw x4, 16(x12) - lw x5, 20(x12) - lw x6, 24(x12) - lw x7, 28(x12) - lw x8, 32(x12) - lw x9, 36(x12) - lw x10, 40(x12) - lw x11, 44(x12) - lw x12, 48(x12) - lw x13, 52(x12) - lw x14, 56(x12) - lw x15, 60(x12) - lw x16, 64(x12) - lw x17, 68(x12) - lw x18, 72(x12) - lw x19, 76(x12) - lw x20, 80(x12) - lw x21, 84(x12) - lw x22, 88(x12) - lw x23, 92(x12) - lw x24, 96(x12) - lw x25, 100(x12) - lw x26, 104(x12) - lw x27, 108(x12) - lw x28, 112(x12) - lw x29, 116(x12) - lw x30, 120(x12) - lw x31, 124(x12) - addi x12, x12, 124 - add x13, x12, zero - csrrw x12, 0x340, x12 - mret - -illegal_instr_handler: - csrr x30, mepc - addi x30, x30, 4 - csrw mepc, x30 - lw x1, 4(x12) - lw x2, 8(x12) - lw x3, 12(x12) - lw x4, 16(x12) - lw x5, 20(x12) - lw x6, 24(x12) - lw x7, 28(x12) - lw x8, 32(x12) - lw x9, 36(x12) - lw x10, 40(x12) - lw x11, 44(x12) - lw x12, 48(x12) - lw x13, 52(x12) - lw x14, 56(x12) - lw x15, 60(x12) - lw x16, 64(x12) - lw x17, 68(x12) - lw x18, 72(x12) - lw x19, 76(x12) - lw x20, 80(x12) - lw x21, 84(x12) - lw x22, 88(x12) - lw x23, 92(x12) - lw x24, 96(x12) - lw x25, 100(x12) - lw x26, 104(x12) - lw x27, 108(x12) - lw x28, 112(x12) - lw x29, 116(x12) - lw x30, 120(x12) - lw x31, 124(x12) - addi x12, x12, 124 - add x13, x12, zero - csrrw x12, 0x340, x12 - mret - -pt_fault_handler: - nop - -.align 2 -mmode_intr_handler: - csrr x30, 0x300 # MSTATUS; - csrr x30, 0x304 # MIE; - csrr x30, 0x344 # MIP; - csrrc x30, 0x344, x30 # MIP; - lw x1, 4(x12) - lw x2, 8(x12) - lw x3, 12(x12) - lw x4, 16(x12) - lw x5, 20(x12) - lw x6, 24(x12) - lw x7, 28(x12) - lw x8, 32(x12) - lw x9, 36(x12) - lw x10, 40(x12) - lw x11, 44(x12) - lw x12, 48(x12) - lw x13, 52(x12) - lw x14, 56(x12) - lw x15, 60(x12) - lw x16, 64(x12) - lw x17, 68(x12) - lw x18, 72(x12) - lw x19, 76(x12) - lw x20, 80(x12) - lw x21, 84(x12) - lw x22, 88(x12) - lw x23, 92(x12) - lw x24, 96(x12) - lw x25, 100(x12) - lw x26, 104(x12) - lw x27, 108(x12) - lw x28, 112(x12) - lw x29, 116(x12) - lw x30, 120(x12) - lw x31, 124(x12) - addi x12, x12, 124 - add x13, x12, zero - csrrw x12, 0x340, x12 - mret; - -kernel_instr_end: nop -.section .kernel_stack,"aw",@progbits; -.align 2 -kernel_stack_start: -.rept 3999 -.4byte 0x0 -.endr -kernel_stack_end: -.4byte 0x0 diff --git a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_0/test.yaml b/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_0/test.yaml deleted file mode 100644 index a208d186f5..0000000000 --- a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_0/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: riscv_arithmetic_basic_test_0 -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Basic sanity arithmetic test 0 diff --git a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S b/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S deleted file mode 100644 index cd7b8c5455..0000000000 --- a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_1/riscv_arithmetic_basic_test_1.S +++ /dev/null @@ -1,12372 +0,0 @@ -# BEGIN: riscv-dv -#.include "user_define.h" -#.globl _start -#.section .text -#_start: -# END: riscv-dv -# BEGIN: gtumbush -#include "corev_uvmt.h" - -.include "user_define.h" -.section .text.start -.globl _start -.section .text -.type _start, @function - -_start: - - j _start_main - -.globl _start_main -.section .text -_start_main: -# END: gtumbush -# BEGIN: riscv-dv - csrr x5, mhartid - li x6, 0 - beq x5, x6, 0f - -0: j h0_start -h0_start: - li x10, 0x40001104 - csrw misa, x10 -kernel_sp: - la x31, kernel_stack_end - -trap_vec_init: - la x10, mtvec_handler - ori x10, x10, 1 - csrw 0x305, x10 # MTVEC - -mepc_setup: - la x10, init - csrw mepc, x10 - j init_machine_mode - -init: - li x0, 0xfd790eda - li x1, 0x80000000 - li x2, 0x6 - li x3, 0x0 - li x4, 0x80000000 - li x5, 0xe - li x6, 0x87c36d9 - li x7, 0xb - li x8, 0x80000000 - li x9, 0x9 - li x10, 0xf510029d - li x11, 0x47cc0565 - li x12, 0x80000000 - li x13, 0x80000000 - li x14, 0x0 - li x16, 0xf03e6cd8 - li x17, 0x9 - li x18, 0x0 - li x19, 0x0 - li x20, 0xfb21c919 - li x21, 0x8b56ef7a - li x22, 0xd10cbf06 - li x23, 0xfdbec9f2 - li x24, 0xf34f30bf - li x25, 0x7 - li x26, 0x0 - li x27, 0xf61c9318 - li x28, 0x5 - li x29, 0xf7e30b15 - li x30, 0x15a65931 - la x15, user_stack_end -main: li s7, 0xffffffff #start riscv_int_numeric_corner_stream_10 - li t2, 0x80000000 - li tp, 0x80000000 - li a6, 0x3ac3aef8 - li s11, 0xffffffff - li s6, 0x4ad1c1ff - li s8, 0x80000000 - li a2, 0x80000000 - li a0, 0xffffffff - li s10, 0x80000000 - auipc a0, 11691 - nop - nop - add s6, tp, s6 - divu a0, s6, s8 - div a6, a2, t2 - divu a0, s6, s8 - nop - nop - divu a0, s6, s8 - mul a2, tp, a0 - divu a0, s6, s8 - sub a0, a0, s8 - div a6, a2, t2 - lui s6, 985951 - nop - nop - nop - add s6, tp, s6 - remu s8, s6, a2 - mul a2, tp, a0 - mulh s8, s7, tp - mulhsu tp, a2, s11 - div a6, a2, t2 - mul a2, tp, a0 #end riscv_int_numeric_corner_stream_10 - li t5, 0x0 #start riscv_int_numeric_corner_stream_19 - li s3, 0x80000000 - li t4, 0xed3ad258 - li a7, 0xffffffff - li s6, 0x0 - li s2, 0xffffffff - li s7, 0x80000000 - li t0, 0xd203cab0 - li a4, 0x9c87e90b - li s5, 0x80000000 - divu a7, a4, a7 - nop - auipc t4, 11691 - mulhsu t4, t0, t0 - auipc t4, 11691 - lui s6, 985951 - rem a7, t0, a4 - lui s6, 985951 - nop - add s3, s7, t5 - add s3, s7, t5 - addi a4, s3, -40 - add s3, s7, t5 - auipc t4, 11691 - nop #end riscv_int_numeric_corner_stream_19 - li s4, 0x0 #start riscv_int_numeric_corner_stream_31 - li a6, 0x4efe2548 - li sp, 0x0 - li s11, 0x80000000 - li s9, 0x80000000 - li s3, 0xcacc4459 - li a4, 0xffffffff - li a0, 0xffffffff - li gp, 0x80000000 - li t1, 0x3b7b50de - mulh s11, gp, gp - add s3, s11, a4 - rem s4, a6, a4 - lui gp, 985951 - lui gp, 985951 - mulhsu s4, a0, gp - add s3, s11, a4 - nop - mulhu s9, a4, a4 - lui gp, 985951 - lui gp, 985951 - addi s9, s3, -40 - sub a0, s9, s9 - nop - remu s9, s4, a4 - mulhsu s4, a0, gp - addi s9, s3, -40 - div a0, s9, gp - mul t1, s4, a4 - divu s4, a0, s9 - nop - mul t1, s4, a4 - nop - addi s9, s3, -40 #end riscv_int_numeric_corner_stream_31 - li tp, 0x80000000 #start riscv_int_numeric_corner_stream_39 - li t1, 0xffffffff - li s7, 0x80000000 - li a3, 0x80000000 - li s2, 0x0 - li s6, 0x80000000 - li sp, 0x80000000 - li gp, 0xdce02feb - li s11, 0x0 - li s1, 0x80000000 - remu a3, s11, s2 - rem a3, s2, t1 - sub s6, a3, s11 - auipc s1, 11691 - rem a3, s2, t1 - sub s6, a3, s11 - addi s11, s11, -40 - auipc s1, 11691 - nop - lui gp, 985951 - rem a3, s2, t1 - div tp, s11, gp - sub s6, a3, s11 - nop - add t1, sp, s6 - nop - mulhsu s7, sp, gp - sub s6, a3, s11 - nop - nop - addi s11, s11, -40 - nop - div tp, s11, gp - add t1, sp, s6 - mulhsu s7, sp, gp - mulhu s1, a3, s7 - mul tp, tp, a3 - add t1, sp, s6 - div tp, s11, gp - addi s11, s11, -40 #end riscv_int_numeric_corner_stream_39 - li s8, 0xffffffff #start riscv_int_numeric_corner_stream_36 - li t3, 0xc9ee93a5 - li a2, 0x80000000 - li t1, 0x98dfc66b - li t0, 0x1878354d - li s11, 0x80000000 - li t4, 0xffffffff - li gp, 0x80000000 - li tp, 0x80000000 - li s9, 0xfc3b413b - sub gp, gp, s9 - addi a2, s11, -40 - auipc a2, 11691 - lui t1, 985951 - mulhsu t1, t1, t0 - addi a2, s11, -40 - divu a2, t1, s9 - add t4, t0, t1 - mulhu tp, a2, t4 - mul gp, t1, a2 - add t4, t0, t1 - nop - lui t1, 985951 - nop - div a2, t4, gp #end riscv_int_numeric_corner_stream_36 - li s1, 0xffffffff #start riscv_int_numeric_corner_stream_3 - li a6, 0x79e3b252 - li s11, 0x0 - li s6, 0x80000000 - li a3, 0x80000000 - li gp, 0xffffffff - li t2, 0x2004d0a7 - li s3, 0x5a561351 - li s2, 0xffffffff - li t1, 0x80000000 - mulhsu s6, a3, gp - mulhu s11, a6, s6 - auipc s1, 11691 - mulh t2, t2, a3 - add s6, t1, s6 - divu s2, t2, a6 - mulhsu s6, a3, gp - nop - div a6, s6, t2 - mulhu s11, a6, s6 - divu s2, t2, a6 - nop - mulhsu s6, a3, gp - rem a6, a6, t2 - add s6, t1, s6 - auipc s1, 11691 - lui s3, 985951 - addi s11, s11, -40 - add s6, t1, s6 - nop - mulh t2, t2, a3 - div a6, s6, t2 - add s6, t1, s6 - mulhu s11, a6, s6 - nop #end riscv_int_numeric_corner_stream_3 - li tp, 0x80000000 #start riscv_int_numeric_corner_stream_34 - li t1, 0xffffffff - li s6, 0xbb2d7d7d - li t5, 0x80000000 - li a7, 0xbd53de38 - li s4, 0x80000000 - li gp, 0x80000000 - li a2, 0x80000000 - li t2, 0x80000000 - li t0, 0x80000000 - nop - add t2, t1, t5 - nop - rem a7, s4, t2 - add t2, t1, t5 - divu tp, gp, a7 - nop - div s4, a7, t2 - addi t0, s6, -40 - addi t0, s6, -40 - add t2, t1, t5 - mulhu t0, s6, t5 - auipc a2, 11691 - sub t5, a7, t5 - addi t0, s6, -40 - addi t0, s6, -40 #end riscv_int_numeric_corner_stream_34 - li s4, 0x80000000 #start riscv_int_numeric_corner_stream_28 - li s10, 0x636d4c95 - li a4, 0x0 - li t0, 0x8a8a1c6c - li t3, 0x281c157a - li t5, 0x0 - li a0, 0x9aabfa88 - li s6, 0x0 - li s3, 0x3fbbf7da - li t2, 0x534dc5c2 - nop - mulhsu t2, t5, s3 - mulhu s3, s6, t5 - addi a0, s10, -40 - add s3, t2, a4 - divu a0, a4, s3 - sub s10, a4, s10 - mul t3, s6, t3 - addi a0, s10, -40 - addi a0, s10, -40 - div s4, s10, t2 - addi a0, s10, -40 - auipc t3, 11691 - addi a0, s10, -40 - sub s10, a4, s10 - nop #end riscv_int_numeric_corner_stream_28 - li s2, 0x80000000 #start riscv_int_numeric_corner_stream_7 - li s7, 0x80000000 - li s1, 0xffffffff - li a0, 0x80000000 - li a7, 0x0 - li s0, 0x80000000 - li a2, 0x689cd09d - li s6, 0x3e6ea5e0 - li ra, 0x0 - li a6, 0xffffffff - lui s6, 985951 - div a2, s7, ra - mulhu a7, s1, s7 - nop - divu a0, s6, a7 - auipc s0, 11691 - add s7, a0, s6 - nop - auipc s0, 11691 - auipc s0, 11691 - auipc s0, 11691 - auipc s0, 11691 - nop - sub s6, a0, a7 - nop #end riscv_int_numeric_corner_stream_7 - li a3, 0xffffffff #start riscv_int_numeric_corner_stream_29 - li t5, 0xde4c99ec - li t4, 0x0 - li s5, 0xffffffff - li s7, 0x80000000 - li s11, 0x0 - li a7, 0x0 - li s3, 0xce081e9d - li ra, 0x3fa8bcfc - li t3, 0xffffffff - mulhu a7, ra, t5 - nop - mulhu a7, ra, t5 - lui s11, 985951 - mul s3, s7, a3 - remu s11, s7, t3 - nop - lui s11, 985951 - auipc a3, 11691 - nop - mul s3, s7, a3 - lui s11, 985951 - nop - nop - div t3, s5, s3 - nop - nop - add t5, s7, t5 - remu s11, s7, t3 - remu s11, s7, t3 - addi t5, s7, -40 - remu s11, s7, t3 - remu s11, s7, t3 - sub s11, t5, t3 - nop #end riscv_int_numeric_corner_stream_29 - li t2, 0xae086eb9 #start riscv_int_numeric_corner_stream_22 - li s0, 0x0 - li tp, 0x80000000 - li t4, 0x80000000 - li ra, 0x0 - li a0, 0x80000000 - li s4, 0x80000000 - li s7, 0x0 - li a2, 0x0 - li s11, 0x0 - mulhu ra, a2, t4 - addi ra, s7, -40 - addi ra, s7, -40 - div s4, tp, t2 - mul a2, s4, a0 - add s7, s7, a0 - add s7, s7, a0 - nop - nop - add s7, s7, a0 - lui s7, 985951 - nop - nop - mulhsu s7, s7, ra - divu s0, a0, s11 - addi ra, s7, -40 - divu s0, a0, s11 - lui s7, 985951 - nop - mulhu ra, a2, t4 - lui s7, 985951 - add s7, s7, a0 - mulh s4, t4, tp - add s7, s7, a0 #end riscv_int_numeric_corner_stream_22 - li s5, 0xffffffff #start riscv_int_numeric_corner_stream_4 - li t5, 0x0 - li s7, 0x80000000 - li sp, 0xffffffff - li s2, 0x80000000 - li a0, 0x0 - li s1, 0x80000000 - li s9, 0x0 - li s11, 0xffffffff - li gp, 0xeaed74f6 - divu s9, a0, s9 - nop - mul gp, s5, a0 - lui gp, 985951 - rem s9, s2, a0 - mulhsu s7, sp, gp - div s5, s9, gp - addi a0, s11, -40 - div s5, s9, gp - mulhu s1, gp, t5 - lui gp, 985951 - lui gp, 985951 - divu s9, a0, s9 - nop - add t5, s2, t5 - div s5, s9, gp #end riscv_int_numeric_corner_stream_4 - li t3, 0x407c80ae #start riscv_int_numeric_corner_stream_8 - li a4, 0x0 - li s11, 0x0 - li s8, 0x9c296067 - li t5, 0x80000000 - li gp, 0x80000000 - li s9, 0x0 - li a0, 0x80000000 - li s3, 0x0 - li s10, 0x80000000 - divu s9, a4, s9 - nop - mulhu s9, a4, t5 - mulhu s9, a4, t5 - lui s3, 985951 - mulhu s9, a4, t5 - lui s3, 985951 - sub s8, t5, s8 - add gp, s11, t5 - mul gp, t3, a4 - sub s8, t5, s8 - sub s8, t5, s8 - divu s9, a4, s9 - mul gp, t3, a4 - mul gp, t3, a4 - div a0, t5, gp - auipc a0, 11691 - remu gp, t5, s10 - divu s9, a4, s9 - nop - add gp, s11, t5 - nop - mulhu s9, a4, t5 - sub s8, t5, s8 - mulh s11, gp, gp - mulhu s9, a4, t5 - mulhsu s3, a0, gp #end riscv_int_numeric_corner_stream_8 - li ra, 0x80000000 #start riscv_int_numeric_corner_stream_12 - li t2, 0x80000000 - li t4, 0x0 - li s5, 0xc8b5b745 - li t0, 0x0 - li s0, 0xaf19864a - li s9, 0x0 - li s3, 0xffffffff - li s7, 0x80000000 - li s1, 0xdb76c9dc - sub s0, s0, s9 - lui t2, 985951 - addi s9, s3, -40 - addi s9, s3, -40 - mulh t0, s7, t0 - mulhu ra, s1, s7 - nop - nop - nop - nop - remu s7, s3, s0 - add t4, s5, s0 - remu s7, s3, s0 - divu s0, t2, s9 - auipc s0, 11691 - mulhsu s7, s7, ra - addi s9, s3, -40 - auipc s0, 11691 - addi s9, s3, -40 - add t4, s5, s0 - nop - mulh t0, s7, t0 - mulh t0, s7, t0 - nop - nop - div s9, s1, s3 #end riscv_int_numeric_corner_stream_12 - li t4, 0x80000000 #start riscv_int_numeric_corner_stream_26 - li a3, 0x0 - li s2, 0xa091fb6 - li t5, 0xffffffff - li a4, 0x0 - li s0, 0x80000000 - li s3, 0x0 - li t2, 0xffffffff - li s1, 0x80000000 - li s9, 0x80000000 - mulhsu t2, s0, s3 - nop - remu a3, s3, a4 - nop - div t4, a3, s3 - add s2, t2, a4 - lui s3, 985951 - mul s0, a3, a4 - add s2, t2, a4 - mulh a3, s3, a3 - div t4, a3, s3 - mul s0, a3, a4 - add s2, t2, a4 - divu a3, a4, s9 - add s2, t2, a4 - sub s9, s9, t5 - nop #end riscv_int_numeric_corner_stream_26 - li t0, 0x0 #start riscv_int_numeric_corner_stream_30 - li t4, 0x0 - li s0, 0x0 - li gp, 0x80000000 - li t5, 0x0 - li t2, 0x0 - li s2, 0x34fc9f73 - li t3, 0x80000000 - li a3, 0x12997968 - li a4, 0x80000000 - mul t3, t3, a4 - mulhsu t2, s0, t0 - sub gp, gp, t3 - sub gp, gp, t3 - nop - divu s0, gp, s2 - mulh t3, t4, t0 - nop - lui gp, 985951 - remu t3, gp, a4 - mulhu t0, a3, t5 - nop - lui gp, 985951 - auipc s0, 11691 - nop - mulh t3, t4, t0 - remu t3, gp, a4 - mulhu t0, a3, t5 - mulhsu t2, s0, t0 - addi t4, s2, -40 #end riscv_int_numeric_corner_stream_30 - li a2, 0xffffffff #start riscv_int_numeric_corner_stream_32 - li t3, 0xffffffff - li t4, 0x80000000 - li t1, 0xffffffff - li a0, 0x96d8c8c7 - li sp, 0x80000000 - li s11, 0x75e0c140 - li a4, 0xa697830b - li s0, 0x80000000 - li s9, 0xffffffff - divu sp, a4, s9 - mulhu t4, a0, t4 - rem t4, sp, a4 - addi sp, s11, -40 - mul a4, a2, a4 - mul a4, a2, a4 - div a2, t4, sp - add t3, t4, a4 - addi sp, s11, -40 - rem t4, sp, a4 - nop - add t3, t4, a4 - add t3, t4, a4 - remu s0, t4, a2 - divu sp, a4, s9 - auipc s0, 11691 - auipc s0, 11691 - divu sp, a4, s9 - divu sp, a4, s9 - addi sp, s11, -40 - nop - sub t1, sp, s9 - mulh t4, s11, s0 - auipc s0, 11691 - nop #end riscv_int_numeric_corner_stream_32 - remu s6, s3, t1 - div s7, gp, a4 - c.xor a4, a5 - and s6, t2, a4 - sra s9, s4, t5 - c.slli t5, 22 - c.or a0, a2 - srl t1, tp, zero - addi gp, s8, -298 - or a4, a4, zero - addi gp, s8, -298 - mulh s1, t4, s11 - or a4, a4, zero - or a4, a4, zero - c.li s11, -1 - sltu s3, a6, a4 - div s7, gp, a4 - mulhu s4, a6, t3 - srl t1, tp, zero - c.nop - c.add t3, t1 - slt a0, s5, s11 - addi gp, s8, -298 - div s7, gp, a4 - srai a4, a3, 0 - c.addi s9, -1 - and s6, t2, a4 - c.addi16sp sp, -16 - slt a0, s5, s11 - srl t1, tp, zero - c.sub s0, s1 - or a4, a4, zero - srli zero, a0, 13 - sub s0, t3, gp - c.andi s1, 31 - c.or a0, a2 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - c.addi s9, -1 - nop - sub s0, t3, gp - c.sub s0, s1 - slti tp, a1, -167 - c.mv a2, a0 - c.slli t5, 22 - sltiu s3, tp, 300 - sltu s3, a6, a4 - sll s8, s0, s6 - auipc s1, 11691 - sra s9, s4, t5 - c.mv a2, a0 - addi gp, s8, -298 - mulhsu tp, t5, a6 - mulhsu tp, t5, a6 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - sll s8, s0, s6 - c.srai s1, 28 - slt a0, s5, s11 - xori t3, t1, -721 - c.xor a4, a5 - auipc s1, 11691 - slti tp, a1, -167 - ori tp, a0, -848 - c.nop - c.lui a6, 24 - c.andi s1, 31 - sub s0, t3, gp - and s6, t2, a4 - mulh s1, t4, s11 - c.add t3, t1 - c.andi s1, 31 - sltiu s3, tp, 300 - c.mv a2, a0 - c.mv a2, a0 - sltu s3, a6, a4 - c.addi16sp sp, -16 - sra s9, s4, t5 - mulhu s4, a6, t3 - c.or a0, a2 - andi t0, a3, 147 - ori tp, a0, -848 - slli a2, a4, 25 - c.addi4spn a2, sp, 528 - remu s6, s3, t1 - c.xor a4, a5 - c.sub s0, s1 - mul tp, s2, t5 - srl t1, tp, zero - div s7, gp, a4 - mulhu s4, a6, t3 - andi t0, a3, 147 - mulhsu tp, t5, a6 - c.andi s1, 31 - srai a4, a3, 0 - rem a2, s2, s9 - c.slli t5, 22 - rem a2, s2, s9 - c.and a4, s1 - c.addi s9, -1 - c.andi s1, 31 - mul tp, s2, t5 - c.li s11, -1 - sub s0, t3, gp - c.srli a4, 9 - and s6, t2, a4 - andi t0, a3, 147 - sll s8, s0, s6 - c.srli a4, 9 - c.xor a4, a5 - sltiu s3, tp, 300 - srl t1, tp, zero - mul tp, s2, t5 - c.and a4, s1 - nop - slti tp, a1, -167 - slti tp, a1, -167 - add s4, a7, s6 - c.mv a2, a0 - mulh s1, t4, s11 - c.srai s1, 28 - srai a4, a3, 0 - srli zero, a0, 13 - srl t1, tp, zero - c.or a0, a2 - andi t0, a3, 147 - c.nop - divu tp, s5, t4 - c.sub s0, s1 - c.srli a4, 9 - mulh s1, t4, s11 - c.mv a2, a0 - nop - addi gp, s8, -298 - c.sub s0, s1 - c.lui a6, 24 - sltu s3, a6, a4 - sltiu s3, tp, 300 - slti tp, a1, -167 - c.andi s1, 31 - c.mv a2, a0 - c.nop - slt a0, s5, s11 - xor s11, zero, s7 - addi gp, s8, -298 - divu tp, s5, t4 - c.xor a4, a5 - c.li s11, -1 - add s4, a7, s6 - sra s9, s4, t5 - addi gp, s8, -298 - c.andi s1, 31 - c.mv a2, a0 - addi gp, s8, -298 - c.srli a4, 9 - c.or a0, a2 - srli zero, a0, 13 - mulh s1, t4, s11 - remu s6, s3, t1 - mulh s1, t4, s11 - ori tp, a0, -848 - c.slli t5, 22 - nop - divu tp, s5, t4 - sltiu s3, tp, 300 - mul tp, s2, t5 - sltiu s3, tp, 300 - c.addi16sp sp, -16 - rem a2, s2, s9 - srai a4, a3, 0 - c.nop - ori tp, a0, -848 - mul tp, s2, t5 - srl t1, tp, zero - lui s3, 985951 - mulhu s4, a6, t3 - andi t0, a3, 147 - add s4, a7, s6 - xori t3, t1, -721 - c.add t3, t1 - div s7, gp, a4 - c.slli t5, 22 - srai a4, a3, 0 - c.addi16sp sp, -16 - c.sub s0, s1 - slli a2, a4, 25 - lui s3, 985951 - sra s9, s4, t5 - mul tp, s2, t5 - slt a0, s5, s11 - c.srli a4, 9 - c.srai s1, 28 - srli zero, a0, 13 - remu s6, s3, t1 - div s7, gp, a4 - xor s11, zero, s7 - div s7, gp, a4 - slt a0, s5, s11 - sub s0, t3, gp - c.li s11, -1 - lui s3, 985951 - srai a4, a3, 0 - c.li s11, -1 - c.xor a4, a5 - c.srli a4, 9 - c.xor a4, a5 - c.mv a2, a0 - c.nop - and s6, t2, a4 - c.nop - c.addi4spn a2, sp, 528 - c.andi s1, 31 - c.lui a6, 24 - c.add t3, t1 - add s4, a7, s6 - c.addi16sp sp, -16 - c.srli a4, 9 - c.sub s0, s1 - c.or a0, a2 - rem a2, s2, s9 - c.and a4, s1 - slt a0, s5, s11 - divu tp, s5, t4 - c.mv a2, a0 - sll s8, s0, s6 - div s7, gp, a4 - add s4, a7, s6 - c.nop - c.add t3, t1 - c.lui a6, 24 - c.li s11, -1 - addi gp, s8, -298 - div s7, gp, a4 - c.nop - c.sub s0, s1 - divu tp, s5, t4 - or a4, a4, zero - addi gp, s8, -298 - c.nop - c.addi s9, -1 - c.slli t5, 22 - andi t0, a3, 147 - c.srai s1, 28 - c.add t3, t1 - c.nop - ori tp, a0, -848 - xor s11, zero, s7 - c.slli t5, 22 - mulh s1, t4, s11 - c.addi4spn a2, sp, 528 - c.andi s1, 31 - srl t1, tp, zero - auipc s1, 11691 - c.li s11, -1 - c.addi16sp sp, -16 - slt a0, s5, s11 - add s4, a7, s6 - ori tp, a0, -848 - sub s0, t3, gp - srai a4, a3, 0 - nop - remu s6, s3, t1 - sll s8, s0, s6 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - slt a0, s5, s11 - add s4, a7, s6 - add s4, a7, s6 - c.xor a4, a5 - lui s3, 985951 - c.srli a4, 9 - mulhu s4, a6, t3 - c.srai s1, 28 - lui s3, 985951 - srl t1, tp, zero - mul tp, s2, t5 - slt a0, s5, s11 - sra s9, s4, t5 - sll s8, s0, s6 - slt a0, s5, s11 - ori tp, a0, -848 - addi gp, s8, -298 - remu s6, s3, t1 - mulhu s4, a6, t3 - and s6, t2, a4 - c.srai s1, 28 - c.xor a4, a5 - srl t1, tp, zero - c.addi16sp sp, -16 - addi gp, s8, -298 - nop - remu s6, s3, t1 - lui s3, 985951 - c.li s11, -1 - c.mv a2, a0 - add s4, a7, s6 - lui s3, 985951 - remu s6, s3, t1 - c.srai s1, 28 - sub s0, t3, gp - slti tp, a1, -167 - slti tp, a1, -167 - srl t1, tp, zero - lui s3, 985951 - c.sub s0, s1 - sltu s3, a6, a4 - srai a4, a3, 0 - mulhu s4, a6, t3 - andi t0, a3, 147 - c.addi4spn a2, sp, 528 - mulhsu tp, t5, a6 - c.slli t5, 22 - c.lui a6, 24 - sltiu s3, tp, 300 - ori tp, a0, -848 - li s6, 0x7616aea9 #start riscv_int_numeric_corner_stream_0 - li t5, 0xffffffff - li s5, 0x0 - li s4, 0xffffffff - li t2, 0x80000000 - li a4, 0x15ad0402 - li s7, 0x80000000 - li t0, 0x53566214 - li t3, 0xa62661f - li gp, 0xffffffff - rem a4, s4, a4 - mulhu s7, s6, t5 - nop - mulhsu s7, t5, gp - mulh gp, s7, t0 - auipc t3, 11691 - add s5, s7, t5 - nop - rem a4, s4, a4 - nop - nop - nop - sub gp, a4, s5 - addi a4, s7, -40 - remu a4, gp, s6 - remu a4, gp, s6 - nop #end riscv_int_numeric_corner_stream_0 - div s7, gp, a4 - sltiu s3, tp, 300 - c.srai s1, 28 - c.srli a4, 9 - sll s8, s0, s6 - and s6, t2, a4 - c.addi s9, -1 - sltu s3, a6, a4 - c.add t3, t1 - c.slli t5, 22 - srai a4, a3, 0 - c.nop - c.sub s0, s1 - slli a2, a4, 25 - c.andi s1, 31 - auipc s1, 11691 - c.andi s1, 31 - or a4, a4, zero - andi t0, a3, 147 - xori t3, t1, -721 - c.sub s0, s1 - srai a4, a3, 0 - sltiu s3, tp, 300 - srli zero, a0, 13 - div s7, gp, a4 - slt a0, s5, s11 - c.andi s1, 31 - sub s0, t3, gp - lui s3, 985951 - sltu s3, a6, a4 - mulhu s4, a6, t3 - sltiu s3, tp, 300 - slti tp, a1, -167 - sltiu s3, tp, 300 - c.addi s9, -1 - li a6, 0x80000000 #start riscv_int_numeric_corner_stream_35 - li s6, 0x80000000 - li a2, 0x0 - li gp, 0xffffffff - li t5, 0x80000000 - li a0, 0x33b488ff - li s2, 0x80000000 - li s3, 0x0 - li t1, 0xa27585b5 - li sp, 0xffffffff - rem gp, s2, t1 - add s6, s3, t5 - nop - nop - sub t5, a6, t5 - remu t1, t5, a2 - sub t5, a6, t5 - sub t5, a6, t5 - auipc a2, 11691 - div a2, a0, gp - mul a2, t1, a2 - add s6, s3, t5 - mulhsu t5, t5, gp - nop - nop - mulhsu t5, t5, gp - mulhu t5, s6, t5 - add s6, s3, t5 - add s6, s3, t5 - nop #end riscv_int_numeric_corner_stream_35 - slti tp, a1, -167 - auipc s1, 11691 - srli zero, a0, 13 - c.sub s0, s1 - auipc s1, 11691 - slt a0, s5, s11 - rem a2, s2, s9 - c.lui a6, 24 - c.srai s1, 28 - andi t0, a3, 147 - add s4, a7, s6 - nop - xori t3, t1, -721 - c.lui a6, 24 - andi t0, a3, 147 - c.srai s1, 28 - c.add t3, t1 - c.lui a6, 24 - c.srai s1, 28 - ori tp, a0, -848 - c.andi s1, 31 - c.li s11, -1 - c.addi s9, -1 - srli zero, a0, 13 - sll s8, s0, s6 - c.lui a6, 24 - slt a0, s5, s11 - sll s8, s0, s6 - c.addi s9, -1 - mulhu s4, a6, t3 - slti tp, a1, -167 - div s7, gp, a4 - c.xor a4, a5 - sll s8, s0, s6 - remu s6, s3, t1 - xor s11, zero, s7 - nop - lui s3, 985951 - mul tp, s2, t5 - c.add t3, t1 - add s4, a7, s6 - sub s0, t3, gp - andi t0, a3, 147 - srai a4, a3, 0 - remu s6, s3, t1 - c.add t3, t1 - ori tp, a0, -848 - c.sub s0, s1 - c.nop - add s4, a7, s6 - c.addi s9, -1 - slti tp, a1, -167 - mul tp, s2, t5 - mulhu s4, a6, t3 - sltiu s3, tp, 300 - divu tp, s5, t4 - mulhu s4, a6, t3 - srli zero, a0, 13 - sra s9, s4, t5 - c.li s11, -1 - add s4, a7, s6 - rem a2, s2, s9 - c.addi s9, -1 - xor s11, zero, s7 - c.nop - addi gp, s8, -298 - c.and a4, s1 - mulhsu tp, t5, a6 - mulhsu tp, t5, a6 - c.and a4, s1 - xori t3, t1, -721 - div s7, gp, a4 - sltiu s3, tp, 300 - c.mv a2, a0 - slti tp, a1, -167 - sub s0, t3, gp - sub s0, t3, gp - c.mv a2, a0 - c.addi4spn a2, sp, 528 - c.and a4, s1 - c.srli a4, 9 - remu s6, s3, t1 - c.li s11, -1 - srl t1, tp, zero - remu s6, s3, t1 - mulh s1, t4, s11 - mulhu s4, a6, t3 - remu s6, s3, t1 - c.slli t5, 22 - c.sub s0, s1 - slli a2, a4, 25 - sll s8, s0, s6 - slti tp, a1, -167 - c.andi s1, 31 - srai a4, a3, 0 - c.addi16sp sp, -16 - c.nop - c.addi s9, -1 - sll s8, s0, s6 - c.addi16sp sp, -16 - c.mv a2, a0 - c.lui a6, 24 - mulh s1, t4, s11 - mulhsu tp, t5, a6 - auipc s1, 11691 - c.sub s0, s1 - c.add t3, t1 - slt a0, s5, s11 - slt a0, s5, s11 - auipc s1, 11691 - mulhsu tp, t5, a6 - srai a4, a3, 0 - slli a2, a4, 25 - c.addi16sp sp, -16 - mul tp, s2, t5 - srl t1, tp, zero - auipc s1, 11691 - slli a2, a4, 25 - slti tp, a1, -167 - sra s9, s4, t5 - div s7, gp, a4 - sll s8, s0, s6 - c.addi s9, -1 - slti tp, a1, -167 - c.sub s0, s1 - c.srai s1, 28 - mulhu s4, a6, t3 - c.and a4, s1 - xor s11, zero, s7 - slli a2, a4, 25 - divu tp, s5, t4 - c.srli a4, 9 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - mulhsu tp, t5, a6 - c.andi s1, 31 - srai a4, a3, 0 - ori tp, a0, -848 - mul tp, s2, t5 - sub s0, t3, gp - remu s6, s3, t1 - andi t0, a3, 147 - sltiu s3, tp, 300 - and s6, t2, a4 - c.and a4, s1 - sltu s3, a6, a4 - sltiu s3, tp, 300 - slt a0, s5, s11 - c.add t3, t1 - nop - or a4, a4, zero - xori t3, t1, -721 - xor s11, zero, s7 - c.lui a6, 24 - c.slli t5, 22 - xor s11, zero, s7 - sra s9, s4, t5 - slli a2, a4, 25 - divu tp, s5, t4 - srl t1, tp, zero - c.srli a4, 9 - srl t1, tp, zero - sltiu s3, tp, 300 - mul tp, s2, t5 - c.and a4, s1 - c.li s11, -1 - c.li s11, -1 - c.or a0, a2 - c.srai s1, 28 - or a4, a4, zero - c.xor a4, a5 - mulh s1, t4, s11 - c.li s11, -1 - lui s3, 985951 - c.addi4spn a2, sp, 528 - c.srli a4, 9 - andi t0, a3, 147 - c.mv a2, a0 - and s6, t2, a4 - slt a0, s5, s11 - nop - slli a2, a4, 25 - slti tp, a1, -167 - add s4, a7, s6 - divu tp, s5, t4 - slti tp, a1, -167 - mul tp, s2, t5 - ori tp, a0, -848 - c.addi s9, -1 - sltu s3, a6, a4 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - c.li s11, -1 - mulhsu tp, t5, a6 - andi t0, a3, 147 - c.mv a2, a0 - c.srli a4, 9 - slti tp, a1, -167 - xori t3, t1, -721 - c.addi s9, -1 - divu tp, s5, t4 - sub s0, t3, gp - srai a4, a3, 0 - c.addi4spn a2, sp, 528 - andi t0, a3, 147 - sltu s3, a6, a4 - c.srli a4, 9 - and s6, t2, a4 - c.nop - mulhu s4, a6, t3 - c.sub s0, s1 - sltu s3, a6, a4 - and s6, t2, a4 - slti tp, a1, -167 - c.and a4, s1 - c.lui a6, 24 - c.srli a4, 9 - div s7, gp, a4 - addi gp, s8, -298 - xori t3, t1, -721 - sll s8, s0, s6 - c.or a0, a2 - c.srai s1, 28 - c.add t3, t1 - mulhsu tp, t5, a6 - add s4, a7, s6 - mulhsu tp, t5, a6 - c.srai s1, 28 - sra s9, s4, t5 - sll s8, s0, s6 - xor s11, zero, s7 - nop - mulhsu tp, t5, a6 - lui s3, 985951 - xor s11, zero, s7 - mulh s1, t4, s11 - srai a4, a3, 0 - c.lui a6, 24 - sra s9, s4, t5 - and s6, t2, a4 - c.li s11, -1 - li s7, 0x0 #start riscv_int_numeric_corner_stream_38 - li s0, 0xedd3f26b - li tp, 0x0 - li gp, 0x0 - li t0, 0x0 - li s8, 0xffffffff - li s6, 0xffffffff - li s11, 0x6e0f303b - li t4, 0xffffffff - li t5, 0xce724ebd - remu s8, s11, tp - sub s11, gp, s8 - mulhu s7, s6, t5 - nop - div s8, tp, t0 - nop - add s6, tp, t5 - nop - sub s11, gp, s8 - nop - nop - addi t0, s11, -40 - nop - add s6, tp, t5 - divu s0, gp, s8 - lui gp, 985951 - sub s11, gp, s8 - nop - nop - mulhu s7, s6, t5 - mul s8, s6, s0 - sub s11, gp, s8 - mulh t0, s7, tp - rem t4, s8, gp - mulhsu t5, s7, gp - nop - mulhu s7, s6, t5 - addi t0, s11, -40 #end riscv_int_numeric_corner_stream_38 - or a4, a4, zero - c.sub s0, s1 - c.sub s0, s1 - c.or a0, a2 - c.li s11, -1 - c.srai s1, 28 - rem a2, s2, s9 - c.slli t5, 22 - c.andi s1, 31 - mulhsu tp, t5, a6 - div s7, gp, a4 - srli zero, a0, 13 - srli zero, a0, 13 - c.addi16sp sp, -16 - c.or a0, a2 - rem a2, s2, s9 - xor s11, zero, s7 - lui s3, 985951 - xori t3, t1, -721 - c.xor a4, a5 - c.slli t5, 22 - sra s9, s4, t5 - sltiu s3, tp, 300 - li s2, 0x0 #start riscv_int_numeric_corner_stream_2 - li sp, 0x80000000 - li s10, 0x80000000 - li t4, 0x5378c6be - li a4, 0x80000000 - li s0, 0x80000000 - li s8, 0x63562bed - li s3, 0x80000000 - li t1, 0xffffffff - li s11, 0xffffffff - remu s2, s10, a4 - lui s3, 985951 - auipc s0, 11691 - nop - nop - nop - nop - lui s3, 985951 - sub t1, sp, s8 - auipc s0, 11691 - mul t1, t4, a4 - nop - sub t1, sp, s8 - add t1, t4, a4 - rem t1, s2, a4 - nop - nop - mulhu t4, t4, t4 - add t1, t4, a4 - nop - remu s2, s10, a4 - nop - divu t4, a4, s8 - lui s3, 985951 #end riscv_int_numeric_corner_stream_2 - c.addi s9, -1 - div s7, gp, a4 - andi t0, a3, 147 - sltiu s3, tp, 300 - or a4, a4, zero - c.addi16sp sp, -16 - andi t0, a3, 147 - c.srai s1, 28 - c.add t3, t1 - auipc s1, 11691 - andi t0, a3, 147 - remu s6, s3, t1 - c.and a4, s1 - c.addi4spn a2, sp, 528 - c.mv a2, a0 - c.srli a4, 9 - c.slli t5, 22 - mulhu s4, a6, t3 - mulh s1, t4, s11 - or a4, a4, zero - c.li s11, -1 - mulhu s4, a6, t3 - sll s8, s0, s6 - div s7, gp, a4 - slti tp, a1, -167 - srli zero, a0, 13 - add s4, a7, s6 - divu tp, s5, t4 - remu s6, s3, t1 - c.and a4, s1 - div s7, gp, a4 - c.lui a6, 24 - sltu s3, a6, a4 - c.sub s0, s1 - c.add t3, t1 - c.and a4, s1 - sltu s3, a6, a4 - c.lui a6, 24 - or a4, a4, zero - mulh s1, t4, s11 - rem a2, s2, s9 - c.andi s1, 31 - c.slli t5, 22 - divu tp, s5, t4 - xor s11, zero, s7 - and s6, t2, a4 - sltiu s3, tp, 300 - mulh s1, t4, s11 - xori t3, t1, -721 - xor s11, zero, s7 - mulhu s4, a6, t3 - c.srai s1, 28 - divu tp, s5, t4 - c.and a4, s1 - xori t3, t1, -721 - c.or a0, a2 - remu s6, s3, t1 - c.srli a4, 9 - c.slli t5, 22 - c.sub s0, s1 - c.andi s1, 31 - c.li s11, -1 - xori t3, t1, -721 - divu tp, s5, t4 - mulhsu tp, t5, a6 - xor s11, zero, s7 - c.addi16sp sp, -16 - c.add t3, t1 - rem a2, s2, s9 - sra s9, s4, t5 - c.srai s1, 28 - slti tp, a1, -167 - sra s9, s4, t5 - sll s8, s0, s6 - sltiu s3, tp, 300 - andi t0, a3, 147 - nop - c.addi s9, -1 - c.or a0, a2 - c.srai s1, 28 - ori tp, a0, -848 - c.srai s1, 28 - or a4, a4, zero - c.li s11, -1 - mulh s1, t4, s11 - c.addi4spn a2, sp, 528 - c.li s11, -1 - ori tp, a0, -848 - c.or a0, a2 - c.addi s9, -1 - xor s11, zero, s7 - add s4, a7, s6 - c.andi s1, 31 - remu s6, s3, t1 - mulh s1, t4, s11 - xor s11, zero, s7 - c.mv a2, a0 - c.add t3, t1 - c.andi s1, 31 - nop - c.srli a4, 9 - addi gp, s8, -298 - remu s6, s3, t1 - c.sub s0, s1 - c.or a0, a2 - xor s11, zero, s7 - ori tp, a0, -848 - c.slli t5, 22 - nop - c.add t3, t1 - c.srai s1, 28 - c.srai s1, 28 - slt a0, s5, s11 - xor s11, zero, s7 - c.addi16sp sp, -16 - or a4, a4, zero - c.lui a6, 24 - mulhu s4, a6, t3 - slti tp, a1, -167 - c.addi4spn a2, sp, 528 - sub s0, t3, gp - c.mv a2, a0 - slti tp, a1, -167 - and s6, t2, a4 - c.or a0, a2 - divu tp, s5, t4 - c.nop - mul tp, s2, t5 - c.sub s0, s1 - srai a4, a3, 0 - c.li s11, -1 - c.lui a6, 24 - c.xor a4, a5 - rem a2, s2, s9 - or a4, a4, zero - c.slli t5, 22 - sltu s3, a6, a4 - sltu s3, a6, a4 - div s7, gp, a4 - mulhsu tp, t5, a6 - rem a2, s2, s9 - c.addi16sp sp, -16 - c.xor a4, a5 - c.or a0, a2 - c.or a0, a2 - addi gp, s8, -298 - auipc s1, 11691 - srai a4, a3, 0 - c.addi16sp sp, -16 - srl t1, tp, zero - c.addi s9, -1 - or a4, a4, zero - lui s3, 985951 - srli zero, a0, 13 - addi gp, s8, -298 - c.andi s1, 31 - c.mv a2, a0 - addi gp, s8, -298 - c.or a0, a2 - andi t0, a3, 147 - sltu s3, a6, a4 - sra s9, s4, t5 - srl t1, tp, zero - sltu s3, a6, a4 - srai a4, a3, 0 - xori t3, t1, -721 - mulhu s4, a6, t3 - sll s8, s0, s6 - c.xor a4, a5 - div s7, gp, a4 - c.addi4spn a2, sp, 528 - div s7, gp, a4 - c.li s11, -1 - ori tp, a0, -848 - c.addi16sp sp, -16 - c.slli t5, 22 - sltiu s3, tp, 300 - c.slli t5, 22 - c.addi16sp sp, -16 - slt a0, s5, s11 - lui s3, 985951 - remu s6, s3, t1 - c.addi s9, -1 - c.li s11, -1 - mulh s1, t4, s11 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - and s6, t2, a4 - slti tp, a1, -167 - div s7, gp, a4 - c.andi s1, 31 - c.mv a2, a0 - div s7, gp, a4 - ori tp, a0, -848 - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - add s4, a7, s6 - lui s3, 985951 - ori tp, a0, -848 - sra s9, s4, t5 - srai a4, a3, 0 - div s7, gp, a4 - c.lui a6, 24 - c.addi4spn a2, sp, 528 - c.add t3, t1 - c.li s11, -1 - ori tp, a0, -848 - rem a2, s2, s9 - srai a4, a3, 0 - c.addi16sp sp, -16 - remu s6, s3, t1 - mulhu s4, a6, t3 - slt a0, s5, s11 - mulhsu tp, t5, a6 - divu tp, s5, t4 - mulh s1, t4, s11 - div s7, gp, a4 - c.and a4, s1 - c.srli a4, 9 - xor s11, zero, s7 - ori tp, a0, -848 - c.addi4spn a2, sp, 528 - c.li s11, -1 - divu tp, s5, t4 - c.srli a4, 9 - auipc s1, 11691 - or a4, a4, zero - sltu s3, a6, a4 - c.mv a2, a0 - auipc s1, 11691 - and s6, t2, a4 - c.srai s1, 28 - c.srli a4, 9 - c.li s11, -1 - srl t1, tp, zero - mulh s1, t4, s11 - c.andi s1, 31 - andi t0, a3, 147 - slt a0, s5, s11 - auipc s1, 11691 - c.nop - c.slli t5, 22 - c.lui a6, 24 - mul tp, s2, t5 - slt a0, s5, s11 - nop - auipc s1, 11691 - xori t3, t1, -721 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - mulh s1, t4, s11 - or a4, a4, zero - add s4, a7, s6 - c.srli a4, 9 - mulhsu tp, t5, a6 - sltu s3, a6, a4 - ori tp, a0, -848 - c.andi s1, 31 - sra s9, s4, t5 - srli zero, a0, 13 - sltiu s3, tp, 300 - or a4, a4, zero - srl t1, tp, zero - sub s0, t3, gp - c.lui a6, 24 - remu s6, s3, t1 - srli zero, a0, 13 - slt a0, s5, s11 - c.srli a4, 9 - c.addi4spn a2, sp, 528 - mulh s1, t4, s11 - add s4, a7, s6 - sll s8, s0, s6 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - c.addi16sp sp, -16 - sra s9, s4, t5 - c.and a4, s1 - c.add t3, t1 - mulh s1, t4, s11 - c.xor a4, a5 - sra s9, s4, t5 - srl t1, tp, zero - rem a2, s2, s9 - andi t0, a3, 147 - c.add t3, t1 - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - c.xor a4, a5 - ori tp, a0, -848 - sub s0, t3, gp - nop - c.srli a4, 9 - addi gp, s8, -298 - rem a2, s2, s9 - remu s6, s3, t1 - c.slli t5, 22 - c.addi s9, -1 - auipc s1, 11691 - c.srai s1, 28 - slt a0, s5, s11 - andi t0, a3, 147 - c.srli a4, 9 - sll s8, s0, s6 - slt a0, s5, s11 - slt a0, s5, s11 - c.mv a2, a0 - add s4, a7, s6 - c.slli t5, 22 - sltiu s3, tp, 300 - andi t0, a3, 147 - srli zero, a0, 13 - srai a4, a3, 0 - c.li s11, -1 - div s7, gp, a4 - sub s0, t3, gp - mulhu s4, a6, t3 - srai a4, a3, 0 - add s4, a7, s6 - sltu s3, a6, a4 - andi t0, a3, 147 - addi gp, s8, -298 - mul tp, s2, t5 - c.mv a2, a0 - c.addi s9, -1 - nop - mulh s1, t4, s11 - c.sub s0, s1 - xor s11, zero, s7 - mulhsu tp, t5, a6 - slli a2, a4, 25 - srli zero, a0, 13 - srl t1, tp, zero - slt a0, s5, s11 - c.sub s0, s1 - c.addi4spn a2, sp, 528 - sltiu s3, tp, 300 - c.mv a2, a0 - c.or a0, a2 - sll s8, s0, s6 - c.srai s1, 28 - div s7, gp, a4 - xor s11, zero, s7 - xor s11, zero, s7 - srli zero, a0, 13 - c.addi16sp sp, -16 - sub s0, t3, gp - mulh s1, t4, s11 - slli a2, a4, 25 - mulhsu tp, t5, a6 - remu s6, s3, t1 - c.li s11, -1 - sltu s3, a6, a4 - c.addi16sp sp, -16 - c.lui a6, 24 - sll s8, s0, s6 - c.nop - c.xor a4, a5 - addi gp, s8, -298 - slti tp, a1, -167 - xor s11, zero, s7 - xori t3, t1, -721 - c.slli t5, 22 - sltiu s3, tp, 300 - c.lui a6, 24 - and s6, t2, a4 - andi t0, a3, 147 - c.sub s0, s1 - div s7, gp, a4 - c.srai s1, 28 - mulhsu tp, t5, a6 - c.and a4, s1 - c.add t3, t1 - c.or a0, a2 - c.addi s9, -1 - sra s9, s4, t5 - xori t3, t1, -721 - sll s8, s0, s6 - sll s8, s0, s6 - sub s0, t3, gp - c.or a0, a2 - sltu s3, a6, a4 - xor s11, zero, s7 - xor s11, zero, s7 - c.srli a4, 9 - xor s11, zero, s7 - c.slli t5, 22 - xor s11, zero, s7 - c.or a0, a2 - c.or a0, a2 - sltu s3, a6, a4 - remu s6, s3, t1 - c.andi s1, 31 - slti tp, a1, -167 - srl t1, tp, zero - c.andi s1, 31 - addi gp, s8, -298 - c.nop - mulh s1, t4, s11 - add s4, a7, s6 - c.addi s9, -1 - srl t1, tp, zero - c.li s11, -1 - mulh s1, t4, s11 - c.mv a2, a0 - sltu s3, a6, a4 - mulh s1, t4, s11 - xori t3, t1, -721 - srai a4, a3, 0 - remu s6, s3, t1 - slli a2, a4, 25 - c.addi16sp sp, -16 - lui s3, 985951 - c.sub s0, s1 - addi gp, s8, -298 - add s4, a7, s6 - addi gp, s8, -298 - add s4, a7, s6 - div s7, gp, a4 - sub s0, t3, gp - sub s0, t3, gp - c.andi s1, 31 - c.or a0, a2 - c.lui a6, 24 - slli a2, a4, 25 - ori tp, a0, -848 - ori tp, a0, -848 - or a4, a4, zero - addi gp, s8, -298 - sra s9, s4, t5 - or a4, a4, zero - srl t1, tp, zero - xor s11, zero, s7 - c.sub s0, s1 - c.mv a2, a0 - sub s0, t3, gp - add s4, a7, s6 - ori tp, a0, -848 - rem a2, s2, s9 - sll s8, s0, s6 - sub s0, t3, gp - remu s6, s3, t1 - sub s0, t3, gp - srai a4, a3, 0 - xori t3, t1, -721 - srl t1, tp, zero - c.add t3, t1 - c.or a0, a2 - ori tp, a0, -848 - and s6, t2, a4 - sra s9, s4, t5 - srai a4, a3, 0 - xor s11, zero, s7 - c.mv a2, a0 - srl t1, tp, zero - andi t0, a3, 147 - remu s6, s3, t1 - c.lui a6, 24 - c.and a4, s1 - xor s11, zero, s7 - c.slli t5, 22 - rem a2, s2, s9 - mul tp, s2, t5 - c.sub s0, s1 - auipc s1, 11691 - add s4, a7, s6 - div s7, gp, a4 - xori t3, t1, -721 - mulhu s4, a6, t3 - c.addi s9, -1 - c.and a4, s1 - c.andi s1, 31 - c.mv a2, a0 - xori t3, t1, -721 - mulhsu tp, t5, a6 - c.mv a2, a0 - andi t0, a3, 147 - slli a2, a4, 25 - rem a2, s2, s9 - sub s0, t3, gp - c.andi s1, 31 - c.nop - slli a2, a4, 25 - ori tp, a0, -848 - add s4, a7, s6 - srli zero, a0, 13 - c.srli a4, 9 - ori tp, a0, -848 - mulhu s4, a6, t3 - c.sub s0, s1 - remu s6, s3, t1 - xor s11, zero, s7 - or a4, a4, zero - lui s3, 985951 - c.addi16sp sp, -16 - c.srai s1, 28 - c.mv a2, a0 - rem a2, s2, s9 - slti tp, a1, -167 - remu s6, s3, t1 - slti tp, a1, -167 - divu tp, s5, t4 - srai a4, a3, 0 - remu s6, s3, t1 - c.mv a2, a0 - c.andi s1, 31 - sll s8, s0, s6 - c.or a0, a2 - c.addi16sp sp, -16 - c.xor a4, a5 - sltiu s3, tp, 300 - mul tp, s2, t5 - auipc s1, 11691 - c.mv a2, a0 - c.xor a4, a5 - mul tp, s2, t5 - c.srli a4, 9 - sll s8, s0, s6 - c.addi16sp sp, -16 - or a4, a4, zero - c.sub s0, s1 - sll s8, s0, s6 - divu tp, s5, t4 - rem a2, s2, s9 - c.addi4spn a2, sp, 528 - c.and a4, s1 - c.andi s1, 31 - sub s0, t3, gp - c.slli t5, 22 - sub s0, t3, gp - c.addi4spn a2, sp, 528 - sltiu s3, tp, 300 - c.xor a4, a5 - c.lui a6, 24 - c.nop - c.mv a2, a0 - addi gp, s8, -298 - slli a2, a4, 25 - c.mv a2, a0 - addi gp, s8, -298 - ori tp, a0, -848 - mulhu s4, a6, t3 - add s4, a7, s6 - divu tp, s5, t4 - nop - lui s3, 985951 - c.srli a4, 9 - sub s0, t3, gp - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - c.nop - srl t1, tp, zero - c.add t3, t1 - c.addi16sp sp, -16 - c.addi16sp sp, -16 - sltiu s3, tp, 300 - slti tp, a1, -167 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - or a4, a4, zero - mulhu s4, a6, t3 - c.slli t5, 22 - c.and a4, s1 - c.mv a2, a0 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - sra s9, s4, t5 - slti tp, a1, -167 - srl t1, tp, zero - auipc s1, 11691 - c.lui a6, 24 - addi gp, s8, -298 - sltiu s3, tp, 300 - c.or a0, a2 - remu s6, s3, t1 - mulh s1, t4, s11 - divu tp, s5, t4 - div s7, gp, a4 - srai a4, a3, 0 - sltiu s3, tp, 300 - c.addi4spn a2, sp, 528 - lui s3, 985951 - c.srli a4, 9 - divu tp, s5, t4 - nop - ori tp, a0, -848 - c.or a0, a2 - c.srli a4, 9 - lui s3, 985951 - c.mv a2, a0 - c.add t3, t1 - auipc s1, 11691 - c.srli a4, 9 - c.li s11, -1 - sra s9, s4, t5 - c.xor a4, a5 - c.and a4, s1 - srl t1, tp, zero - mulhu s4, a6, t3 - c.andi s1, 31 - mul tp, s2, t5 - c.slli t5, 22 - srai a4, a3, 0 - rem a2, s2, s9 - sra s9, s4, t5 - auipc s1, 11691 - c.addi16sp sp, -16 - xor s11, zero, s7 - c.srli a4, 9 - xor s11, zero, s7 - xor s11, zero, s7 - divu tp, s5, t4 - slli a2, a4, 25 - c.nop - lui s3, 985951 - mulh s1, t4, s11 - addi gp, s8, -298 - remu s6, s3, t1 - c.srai s1, 28 - c.addi16sp sp, -16 - c.add t3, t1 - c.li s11, -1 - mulh s1, t4, s11 - rem a2, s2, s9 - sltu s3, a6, a4 - mulhsu tp, t5, a6 - srl t1, tp, zero - nop - c.or a0, a2 - c.xor a4, a5 - and s6, t2, a4 - srli zero, a0, 13 - remu s6, s3, t1 - rem a2, s2, s9 - or a4, a4, zero - xori t3, t1, -721 - and s6, t2, a4 - srl t1, tp, zero - c.slli t5, 22 - c.add t3, t1 - slti tp, a1, -167 - nop - mulhu s4, a6, t3 - c.or a0, a2 - sub s0, t3, gp - c.srai s1, 28 - mul tp, s2, t5 - c.srai s1, 28 - c.srai s1, 28 - c.slli t5, 22 - c.andi s1, 31 - c.and a4, s1 - and s6, t2, a4 - c.or a0, a2 - sltiu s3, tp, 300 - auipc s1, 11691 - divu tp, s5, t4 - c.and a4, s1 - srli zero, a0, 13 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - and s6, t2, a4 - srl t1, tp, zero - ori tp, a0, -848 - slli a2, a4, 25 - and s6, t2, a4 - c.mv a2, a0 - srli zero, a0, 13 - c.and a4, s1 - nop - auipc s1, 11691 - addi gp, s8, -298 - remu s6, s3, t1 - slli a2, a4, 25 - mulh s1, t4, s11 - c.addi4spn a2, sp, 528 - add s4, a7, s6 - slt a0, s5, s11 - remu s6, s3, t1 - srli zero, a0, 13 - sltiu s3, tp, 300 - auipc s1, 11691 - srli zero, a0, 13 - srli zero, a0, 13 - mul tp, s2, t5 - ori tp, a0, -848 - c.or a0, a2 - srai a4, a3, 0 - sltiu s3, tp, 300 - slti tp, a1, -167 - sub s0, t3, gp - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - auipc s1, 11691 - mul tp, s2, t5 - c.xor a4, a5 - andi t0, a3, 147 - xori t3, t1, -721 - c.add t3, t1 - div s7, gp, a4 - c.srli a4, 9 - or a4, a4, zero - c.srli a4, 9 - div s7, gp, a4 - c.andi s1, 31 - slti tp, a1, -167 - sra s9, s4, t5 - andi t0, a3, 147 - divu tp, s5, t4 - srli zero, a0, 13 - slt a0, s5, s11 - c.add t3, t1 - mulh s1, t4, s11 - slti tp, a1, -167 - srli zero, a0, 13 - addi gp, s8, -298 - srl t1, tp, zero - slti tp, a1, -167 - nop - c.sub s0, s1 - c.xor a4, a5 - c.addi16sp sp, -16 - mulh s1, t4, s11 - andi t0, a3, 147 - auipc s1, 11691 - c.sub s0, s1 - mulhsu tp, t5, a6 - or a4, a4, zero - c.xor a4, a5 - c.slli t5, 22 - and s6, t2, a4 - mulhu s4, a6, t3 - srai a4, a3, 0 - sub s0, t3, gp - c.nop - srl t1, tp, zero - xori t3, t1, -721 - mulhu s4, a6, t3 - lui s3, 985951 - c.nop - c.li s11, -1 - mulh s1, t4, s11 - lui s3, 985951 - mul tp, s2, t5 - c.lui a6, 24 - c.sub s0, s1 - rem a2, s2, s9 - c.and a4, s1 - slt a0, s5, s11 - slli a2, a4, 25 - sltiu s3, tp, 300 - slli a2, a4, 25 - andi t0, a3, 147 - lui s3, 985951 - addi gp, s8, -298 - remu s6, s3, t1 - c.or a0, a2 - auipc s1, 11691 - c.andi s1, 31 - c.addi s9, -1 - c.add t3, t1 - c.addi s9, -1 - c.or a0, a2 - c.sub s0, s1 - c.addi s9, -1 - c.nop - lui s3, 985951 - sra s9, s4, t5 - andi t0, a3, 147 - sltiu s3, tp, 300 - c.add t3, t1 - xor s11, zero, s7 - div s7, gp, a4 - c.li s11, -1 - sll s8, s0, s6 - addi gp, s8, -298 - c.srai s1, 28 - c.nop - c.srli a4, 9 - andi t0, a3, 147 - c.li s11, -1 - addi gp, s8, -298 - c.add t3, t1 - andi t0, a3, 147 - sltu s3, a6, a4 - c.addi16sp sp, -16 - sltiu s3, tp, 300 - sub s0, t3, gp - slt a0, s5, s11 - c.and a4, s1 - or a4, a4, zero - c.add t3, t1 - sub s0, t3, gp - sll s8, s0, s6 - xori t3, t1, -721 - c.addi s9, -1 - slli a2, a4, 25 - add s4, a7, s6 - sltiu s3, tp, 300 - slt a0, s5, s11 - or a4, a4, zero - c.addi16sp sp, -16 - mulhsu tp, t5, a6 - nop - srl t1, tp, zero - sll s8, s0, s6 - c.slli t5, 22 - srli zero, a0, 13 - addi gp, s8, -298 - c.andi s1, 31 - xor s11, zero, s7 - c.srli a4, 9 - c.andi s1, 31 - sub s0, t3, gp - c.andi s1, 31 - add s4, a7, s6 - xor s11, zero, s7 - c.add t3, t1 - remu s6, s3, t1 - c.sub s0, s1 - add s4, a7, s6 - auipc s1, 11691 - xor s11, zero, s7 - c.sub s0, s1 - slti tp, a1, -167 - c.addi4spn a2, sp, 528 - auipc s1, 11691 - c.or a0, a2 - srli zero, a0, 13 - remu s6, s3, t1 - c.addi4spn a2, sp, 528 - slt a0, s5, s11 - mul tp, s2, t5 - sub s0, t3, gp - c.and a4, s1 - and s6, t2, a4 - srl t1, tp, zero - c.li s11, -1 - slti tp, a1, -167 - c.addi4spn a2, sp, 528 - c.addi4spn a2, sp, 528 - nop - sltiu s3, tp, 300 - sub s0, t3, gp - mulhu s4, a6, t3 - slli a2, a4, 25 - sra s9, s4, t5 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - c.lui a6, 24 - sra s9, s4, t5 - divu tp, s5, t4 - slli a2, a4, 25 - remu s6, s3, t1 - c.add t3, t1 - c.srli a4, 9 - or a4, a4, zero - c.add t3, t1 - auipc s1, 11691 - lui s3, 985951 - srli zero, a0, 13 - c.slli t5, 22 - auipc s1, 11691 - add s4, a7, s6 - andi t0, a3, 147 - c.slli t5, 22 - sll s8, s0, s6 - slli a2, a4, 25 - c.nop - c.srai s1, 28 - xori t3, t1, -721 - or a4, a4, zero - c.lui a6, 24 - slti tp, a1, -167 - c.lui a6, 24 - mulhsu tp, t5, a6 - c.add t3, t1 - srli zero, a0, 13 - c.sub s0, s1 - c.sub s0, s1 - divu tp, s5, t4 - mulh s1, t4, s11 - srl t1, tp, zero - mulh s1, t4, s11 - mulhsu tp, t5, a6 - addi gp, s8, -298 - c.or a0, a2 - sll s8, s0, s6 - c.slli t5, 22 - mulh s1, t4, s11 - or a4, a4, zero - slli a2, a4, 25 - slti tp, a1, -167 - mulhu s4, a6, t3 - remu s6, s3, t1 - xor s11, zero, s7 - lui s3, 985951 - c.andi s1, 31 - c.and a4, s1 - sll s8, s0, s6 - remu s6, s3, t1 - c.li s11, -1 - auipc s1, 11691 - c.add t3, t1 - sub s0, t3, gp - slt a0, s5, s11 - c.sub s0, s1 - c.srai s1, 28 - addi gp, s8, -298 - andi t0, a3, 147 - addi gp, s8, -298 - xori t3, t1, -721 - rem a2, s2, s9 - c.nop - nop - mulhsu tp, t5, a6 - sub s0, t3, gp - c.addi s9, -1 - srli zero, a0, 13 - c.nop - andi t0, a3, 147 - c.li s11, -1 - c.nop - c.lui a6, 24 - mul tp, s2, t5 - and s6, t2, a4 - slti tp, a1, -167 - nop - slti tp, a1, -167 - sltiu s3, tp, 300 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - andi t0, a3, 147 - lui s3, 985951 - c.addi s9, -1 - xor s11, zero, s7 - slti tp, a1, -167 - c.xor a4, a5 - div s7, gp, a4 - ori tp, a0, -848 - div s7, gp, a4 - sub s0, t3, gp - sltiu s3, tp, 300 - xor s11, zero, s7 - mulh s1, t4, s11 - c.add t3, t1 - c.sub s0, s1 - slti tp, a1, -167 - c.andi s1, 31 - sll s8, s0, s6 - c.andi s1, 31 - sra s9, s4, t5 - rem a2, s2, s9 - sub s0, t3, gp - mulhsu tp, t5, a6 - add s4, a7, s6 - xor s11, zero, s7 - sub s0, t3, gp - rem a2, s2, s9 - auipc s1, 11691 - divu tp, s5, t4 - c.xor a4, a5 - c.srli a4, 9 - c.or a0, a2 - c.add t3, t1 - c.mv a2, a0 - ori tp, a0, -848 - slt a0, s5, s11 - mulh s1, t4, s11 - addi gp, s8, -298 - lui s3, 985951 - div s7, gp, a4 - rem a2, s2, s9 - c.addi s9, -1 - c.xor a4, a5 - mul tp, s2, t5 - add s4, a7, s6 - mul tp, s2, t5 - mulh s1, t4, s11 - c.sub s0, s1 - sub s0, t3, gp - sra s9, s4, t5 - sll s8, s0, s6 - nop - xori t3, t1, -721 - mul tp, s2, t5 - divu tp, s5, t4 - c.or a0, a2 - srl t1, tp, zero - c.addi s9, -1 - mulh s1, t4, s11 - c.or a0, a2 - srai a4, a3, 0 - mul tp, s2, t5 - sll s8, s0, s6 - sltiu s3, tp, 300 - c.slli t5, 22 - c.andi s1, 31 - c.and a4, s1 - c.xor a4, a5 - c.xor a4, a5 - sltu s3, a6, a4 - slt a0, s5, s11 - ori tp, a0, -848 - c.add t3, t1 - c.lui a6, 24 - auipc s1, 11691 - and s6, t2, a4 - c.li s11, -1 - mulh s1, t4, s11 - mul tp, s2, t5 - mulhsu tp, t5, a6 - divu tp, s5, t4 - add s4, a7, s6 - c.srai s1, 28 - rem a2, s2, s9 - mulhsu tp, t5, a6 - remu s6, s3, t1 - lui s3, 985951 - remu s6, s3, t1 - sra s9, s4, t5 - sltiu s3, tp, 300 - c.addi s9, -1 - lui s3, 985951 - lui s3, 985951 - andi t0, a3, 147 - slt a0, s5, s11 - c.add t3, t1 - andi t0, a3, 147 - add s4, a7, s6 - andi t0, a3, 147 - sltu s3, a6, a4 - c.sub s0, s1 - andi t0, a3, 147 - c.add t3, t1 - c.sub s0, s1 - c.slli t5, 22 - srl t1, tp, zero - lui s3, 985951 - slli a2, a4, 25 - sltu s3, a6, a4 - c.mv a2, a0 - mulh s1, t4, s11 - c.sub s0, s1 - addi gp, s8, -298 - c.li s11, -1 - slli a2, a4, 25 - nop - add s4, a7, s6 - nop - sra s9, s4, t5 - c.li s11, -1 - c.srli a4, 9 - sub s0, t3, gp - nop - c.slli t5, 22 - mulhsu tp, t5, a6 - c.addi16sp sp, -16 - c.or a0, a2 - lui s3, 985951 - c.srli a4, 9 - slti tp, a1, -167 - c.nop - c.addi4spn a2, sp, 528 - c.srai s1, 28 - c.xor a4, a5 - c.xor a4, a5 - slti tp, a1, -167 - or a4, a4, zero - sll s8, s0, s6 - xor s11, zero, s7 - c.mv a2, a0 - c.addi16sp sp, -16 - sra s9, s4, t5 - mul tp, s2, t5 - c.xor a4, a5 - auipc s1, 11691 - xori t3, t1, -721 - slli a2, a4, 25 - srli zero, a0, 13 - slli a2, a4, 25 - sltiu s3, tp, 300 - c.xor a4, a5 - c.or a0, a2 - addi gp, s8, -298 - c.addi16sp sp, -16 - c.srai s1, 28 - or a4, a4, zero - and s6, t2, a4 - c.sub s0, s1 - c.xor a4, a5 - c.add t3, t1 - mulh s1, t4, s11 - mulhsu tp, t5, a6 - slti tp, a1, -167 - c.srai s1, 28 - c.li s11, -1 - slti tp, a1, -167 - sub s0, t3, gp - lui s3, 985951 - c.sub s0, s1 - rem a2, s2, s9 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - c.nop - mulh s1, t4, s11 - c.addi s9, -1 - c.sub s0, s1 - auipc s1, 11691 - xor s11, zero, s7 - mulh s1, t4, s11 - c.lui a6, 24 - mulh s1, t4, s11 - c.andi s1, 31 - c.addi4spn a2, sp, 528 - mulh s1, t4, s11 - c.addi s9, -1 - c.addi s9, -1 - and s6, t2, a4 - c.li s11, -1 - addi gp, s8, -298 - srai a4, a3, 0 - c.mv a2, a0 - mulhsu tp, t5, a6 - xor s11, zero, s7 - xori t3, t1, -721 - c.xor a4, a5 - or a4, a4, zero - auipc s1, 11691 - c.srli a4, 9 - slli a2, a4, 25 - rem a2, s2, s9 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - c.xor a4, a5 - c.srai s1, 28 - divu tp, s5, t4 - sll s8, s0, s6 - c.xor a4, a5 - andi t0, a3, 147 - slli a2, a4, 25 - c.slli t5, 22 - slti tp, a1, -167 - c.slli t5, 22 - divu tp, s5, t4 - srl t1, tp, zero - div s7, gp, a4 - xor s11, zero, s7 - c.slli t5, 22 - remu s6, s3, t1 - c.mv a2, a0 - lui s3, 985951 - c.srli a4, 9 - c.slli t5, 22 - c.or a0, a2 - c.addi16sp sp, -16 - mulh s1, t4, s11 - c.or a0, a2 - c.lui a6, 24 - c.addi4spn a2, sp, 528 - c.add t3, t1 - nop - divu tp, s5, t4 - c.li s11, -1 - add s4, a7, s6 - c.slli t5, 22 - lui s3, 985951 - c.addi4spn a2, sp, 528 - sltu s3, a6, a4 - mulhsu tp, t5, a6 - auipc s1, 11691 - sll s8, s0, s6 - c.mv a2, a0 - xor s11, zero, s7 - srai a4, a3, 0 - c.mv a2, a0 - mulhsu tp, t5, a6 - xor s11, zero, s7 - auipc s1, 11691 - nop - remu s6, s3, t1 - divu tp, s5, t4 - slli a2, a4, 25 - xori t3, t1, -721 - c.srli a4, 9 - auipc s1, 11691 - rem a2, s2, s9 - c.xor a4, a5 - sltiu s3, tp, 300 - addi gp, s8, -298 - slti tp, a1, -167 - srai a4, a3, 0 - xori t3, t1, -721 - xor s11, zero, s7 - c.and a4, s1 - sra s9, s4, t5 - c.li s11, -1 - sltiu s3, tp, 300 - slt a0, s5, s11 - sltiu s3, tp, 300 - addi gp, s8, -298 - sltiu s3, tp, 300 - lui s3, 985951 - divu tp, s5, t4 - divu tp, s5, t4 - mul tp, s2, t5 - and s6, t2, a4 - ori tp, a0, -848 - c.lui a6, 24 - srli zero, a0, 13 - mul tp, s2, t5 - sll s8, s0, s6 - sub s0, t3, gp - srli zero, a0, 13 - c.andi s1, 31 - andi t0, a3, 147 - slt a0, s5, s11 - lui s3, 985951 - srai a4, a3, 0 - auipc s1, 11691 - slt a0, s5, s11 - ori tp, a0, -848 - sltu s3, a6, a4 - divu tp, s5, t4 - ori tp, a0, -848 - c.nop - div s7, gp, a4 - c.addi s9, -1 - c.slli t5, 22 - mul tp, s2, t5 - c.addi16sp sp, -16 - addi gp, s8, -298 - rem a2, s2, s9 - c.addi s9, -1 - sub s0, t3, gp - c.lui a6, 24 - or a4, a4, zero - rem a2, s2, s9 - srl t1, tp, zero - slli a2, a4, 25 - sll s8, s0, s6 - c.xor a4, a5 - divu tp, s5, t4 - slli a2, a4, 25 - or a4, a4, zero - mulh s1, t4, s11 - c.xor a4, a5 - c.addi16sp sp, -16 - c.mv a2, a0 - c.andi s1, 31 - slli a2, a4, 25 - and s6, t2, a4 - c.and a4, s1 - c.or a0, a2 - divu tp, s5, t4 - andi t0, a3, 147 - c.srai s1, 28 - mulh s1, t4, s11 - c.xor a4, a5 - remu s6, s3, t1 - mulhsu tp, t5, a6 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - ori tp, a0, -848 - rem a2, s2, s9 - sltiu s3, tp, 300 - c.and a4, s1 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - mulh s1, t4, s11 - or a4, a4, zero - c.li s11, -1 - c.mv a2, a0 - sll s8, s0, s6 - c.or a0, a2 - slli a2, a4, 25 - srli zero, a0, 13 - lui s3, 985951 - slti tp, a1, -167 - c.srai s1, 28 - c.srli a4, 9 - c.slli t5, 22 - c.sub s0, s1 - c.lui a6, 24 - c.addi16sp sp, -16 - and s6, t2, a4 - c.and a4, s1 - c.sub s0, s1 - srli zero, a0, 13 - c.srai s1, 28 - c.lui a6, 24 - mulhu s4, a6, t3 - c.sub s0, s1 - remu s6, s3, t1 - div s7, gp, a4 - sltu s3, a6, a4 - sll s8, s0, s6 - c.andi s1, 31 - sltiu s3, tp, 300 - mulh s1, t4, s11 - c.srli a4, 9 - sltiu s3, tp, 300 - c.srli a4, 9 - xori t3, t1, -721 - c.slli t5, 22 - mul tp, s2, t5 - c.srli a4, 9 - rem a2, s2, s9 - ori tp, a0, -848 - remu s6, s3, t1 - mulhu s4, a6, t3 - ori tp, a0, -848 - or a4, a4, zero - c.addi16sp sp, -16 - c.andi s1, 31 - c.lui a6, 24 - div s7, gp, a4 - c.slli t5, 22 - srai a4, a3, 0 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - c.nop - c.sub s0, s1 - sub s0, t3, gp - c.srai s1, 28 - sltu s3, a6, a4 - c.li s11, -1 - slt a0, s5, s11 - sll s8, s0, s6 - sll s8, s0, s6 - xori t3, t1, -721 - remu s6, s3, t1 - or a4, a4, zero - c.srli a4, 9 - xor s11, zero, s7 - div s7, gp, a4 - c.xor a4, a5 - c.slli t5, 22 - auipc s1, 11691 - remu s6, s3, t1 - c.addi s9, -1 - sltu s3, a6, a4 - c.add t3, t1 - remu s6, s3, t1 - c.sub s0, s1 - divu tp, s5, t4 - c.xor a4, a5 - sra s9, s4, t5 - c.xor a4, a5 - mulhu s4, a6, t3 - auipc s1, 11691 - sll s8, s0, s6 - andi t0, a3, 147 - sltiu s3, tp, 300 - c.srli a4, 9 - lui s3, 985951 - c.or a0, a2 - srli zero, a0, 13 - c.lui a6, 24 - rem a2, s2, s9 - nop - mulhsu tp, t5, a6 - lui s3, 985951 - lui s3, 985951 - add s4, a7, s6 - c.or a0, a2 - c.add t3, t1 - c.addi16sp sp, -16 - c.slli t5, 22 - slti tp, a1, -167 - c.sub s0, s1 - srli zero, a0, 13 - slli a2, a4, 25 - c.lui a6, 24 - xor s11, zero, s7 - c.srai s1, 28 - c.add t3, t1 - slti tp, a1, -167 - sll s8, s0, s6 - sltiu s3, tp, 300 - c.andi s1, 31 - mulh s1, t4, s11 - sltiu s3, tp, 300 - srai a4, a3, 0 - mul tp, s2, t5 - sra s9, s4, t5 - slti tp, a1, -167 - c.xor a4, a5 - auipc s1, 11691 - sltiu s3, tp, 300 - c.and a4, s1 - c.addi16sp sp, -16 - sltu s3, a6, a4 - c.addi16sp sp, -16 - c.nop - sub s0, t3, gp - sltiu s3, tp, 300 - c.addi4spn a2, sp, 528 - sltiu s3, tp, 300 - slt a0, s5, s11 - c.xor a4, a5 - slli a2, a4, 25 - c.srli a4, 9 - auipc s1, 11691 - c.andi s1, 31 - c.andi s1, 31 - sub s0, t3, gp - c.srli a4, 9 - xori t3, t1, -721 - c.add t3, t1 - xor s11, zero, s7 - c.or a0, a2 - c.sub s0, s1 - slti tp, a1, -167 - srli zero, a0, 13 - c.sub s0, s1 - slli a2, a4, 25 - c.andi s1, 31 - c.nop - srli zero, a0, 13 - mulhu s4, a6, t3 - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - slli a2, a4, 25 - c.add t3, t1 - c.addi s9, -1 - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - c.slli t5, 22 - sra s9, s4, t5 - c.mv a2, a0 - or a4, a4, zero - auipc s1, 11691 - c.andi s1, 31 - c.srai s1, 28 - divu tp, s5, t4 - sltiu s3, tp, 300 - srai a4, a3, 0 - mulh s1, t4, s11 - xori t3, t1, -721 - ori tp, a0, -848 - c.or a0, a2 - auipc s1, 11691 - srai a4, a3, 0 - srai a4, a3, 0 - c.xor a4, a5 - sra s9, s4, t5 - auipc s1, 11691 - lui s3, 985951 - c.srli a4, 9 - slti tp, a1, -167 - sltu s3, a6, a4 - c.addi4spn a2, sp, 528 - sltiu s3, tp, 300 - divu tp, s5, t4 - sub s0, t3, gp - c.mv a2, a0 - addi gp, s8, -298 - c.addi4spn a2, sp, 528 - ori tp, a0, -848 - mulhsu tp, t5, a6 - remu s6, s3, t1 - sltu s3, a6, a4 - xor s11, zero, s7 - c.add t3, t1 - c.addi s9, -1 - c.addi4spn a2, sp, 528 - c.li s11, -1 - lui s3, 985951 - sll s8, s0, s6 - c.li s11, -1 - nop - c.li s11, -1 - slt a0, s5, s11 - addi gp, s8, -298 - slli a2, a4, 25 - xori t3, t1, -721 - remu s6, s3, t1 - divu tp, s5, t4 - c.srli a4, 9 - c.mv a2, a0 - div s7, gp, a4 - srl t1, tp, zero - srli zero, a0, 13 - c.xor a4, a5 - c.mv a2, a0 - ori tp, a0, -848 - c.xor a4, a5 - c.xor a4, a5 - c.xor a4, a5 - c.li s11, -1 - mul tp, s2, t5 - sll s8, s0, s6 - c.srai s1, 28 - c.and a4, s1 - and s6, t2, a4 - slli a2, a4, 25 - c.lui a6, 24 - mulhsu tp, t5, a6 - ori tp, a0, -848 - xor s11, zero, s7 - c.nop - srli zero, a0, 13 - sltiu s3, tp, 300 - divu tp, s5, t4 - mulh s1, t4, s11 - c.and a4, s1 - srli zero, a0, 13 - c.xor a4, a5 - c.slli t5, 22 - c.mv a2, a0 - c.or a0, a2 - c.srai s1, 28 - c.or a0, a2 - nop - or a4, a4, zero - ori tp, a0, -848 - xor s11, zero, s7 - slti tp, a1, -167 - sltiu s3, tp, 300 - or a4, a4, zero - slt a0, s5, s11 - c.add t3, t1 - srai a4, a3, 0 - add s4, a7, s6 - divu tp, s5, t4 - ori tp, a0, -848 - mul tp, s2, t5 - sub s0, t3, gp - c.addi4spn a2, sp, 528 - ori tp, a0, -848 - addi gp, s8, -298 - mulhsu tp, t5, a6 - c.slli t5, 22 - c.mv a2, a0 - sltu s3, a6, a4 - sltiu s3, tp, 300 - and s6, t2, a4 - and s6, t2, a4 - c.slli t5, 22 - ori tp, a0, -848 - srli zero, a0, 13 - sltiu s3, tp, 300 - rem a2, s2, s9 - srai a4, a3, 0 - or a4, a4, zero - c.srai s1, 28 - andi t0, a3, 147 - srl t1, tp, zero - c.srai s1, 28 - slli a2, a4, 25 - c.mv a2, a0 - add s4, a7, s6 - c.mv a2, a0 - c.li s11, -1 - srli zero, a0, 13 - ori tp, a0, -848 - sub s0, t3, gp - and s6, t2, a4 - divu tp, s5, t4 - slt a0, s5, s11 - c.addi s9, -1 - c.addi s9, -1 - andi t0, a3, 147 - slti tp, a1, -167 - slt a0, s5, s11 - xor s11, zero, s7 - sll s8, s0, s6 - c.nop - mul tp, s2, t5 - mulhu s4, a6, t3 - c.li s11, -1 - c.addi4spn a2, sp, 528 - c.mv a2, a0 - c.andi s1, 31 - divu tp, s5, t4 - srli zero, a0, 13 - ori tp, a0, -848 - xori t3, t1, -721 - add s4, a7, s6 - c.andi s1, 31 - div s7, gp, a4 - xor s11, zero, s7 - sub s0, t3, gp - c.lui a6, 24 - addi gp, s8, -298 - add s4, a7, s6 - ori tp, a0, -848 - c.slli t5, 22 - c.addi16sp sp, -16 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - ori tp, a0, -848 - c.andi s1, 31 - mulh s1, t4, s11 - c.lui a6, 24 - srli zero, a0, 13 - c.lui a6, 24 - sltu s3, a6, a4 - slti tp, a1, -167 - c.srli a4, 9 - c.addi s9, -1 - c.mv a2, a0 - c.nop - slt a0, s5, s11 - add s4, a7, s6 - andi t0, a3, 147 - slt a0, s5, s11 - mulhsu tp, t5, a6 - sltu s3, a6, a4 - add s4, a7, s6 - divu tp, s5, t4 - c.nop - slli a2, a4, 25 - ori tp, a0, -848 - sll s8, s0, s6 - xor s11, zero, s7 - mul tp, s2, t5 - add s4, a7, s6 - addi gp, s8, -298 - c.and a4, s1 - c.sub s0, s1 - c.slli t5, 22 - remu s6, s3, t1 - c.srai s1, 28 - xor s11, zero, s7 - div s7, gp, a4 - c.mv a2, a0 - slti tp, a1, -167 - c.nop - and s6, t2, a4 - c.nop - rem a2, s2, s9 - c.srai s1, 28 - xori t3, t1, -721 - and s6, t2, a4 - slli a2, a4, 25 - c.xor a4, a5 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - slli a2, a4, 25 - srli zero, a0, 13 - div s7, gp, a4 - add s4, a7, s6 - add s4, a7, s6 - nop - slt a0, s5, s11 - mul tp, s2, t5 - c.srli a4, 9 - lui s3, 985951 - xor s11, zero, s7 - c.addi4spn a2, sp, 528 - addi gp, s8, -298 - sll s8, s0, s6 - slli a2, a4, 25 - sll s8, s0, s6 - mulhsu tp, t5, a6 - srl t1, tp, zero - sltu s3, a6, a4 - add s4, a7, s6 - c.addi s9, -1 - c.addi16sp sp, -16 - mulh s1, t4, s11 - mulhsu tp, t5, a6 - slli a2, a4, 25 - c.lui a6, 24 - srli zero, a0, 13 - c.li s11, -1 - add s4, a7, s6 - slt a0, s5, s11 - c.srai s1, 28 - c.nop - c.mv a2, a0 - ori tp, a0, -848 - c.xor a4, a5 - c.mv a2, a0 - div s7, gp, a4 - mulhu s4, a6, t3 - nop - mulhu s4, a6, t3 - c.andi s1, 31 - c.sub s0, s1 - c.addi s9, -1 - c.nop - or a4, a4, zero - xori t3, t1, -721 - ori tp, a0, -848 - srli zero, a0, 13 - slt a0, s5, s11 - or a4, a4, zero - ori tp, a0, -848 - auipc s1, 11691 - remu s6, s3, t1 - sll s8, s0, s6 - and s6, t2, a4 - c.addi s9, -1 - mul tp, s2, t5 - c.nop - xor s11, zero, s7 - and s6, t2, a4 - srl t1, tp, zero - c.slli t5, 22 - mul tp, s2, t5 - c.add t3, t1 - and s6, t2, a4 - slli a2, a4, 25 - or a4, a4, zero - mulhu s4, a6, t3 - slt a0, s5, s11 - mulhu s4, a6, t3 - c.and a4, s1 - c.nop - srai a4, a3, 0 - c.nop - slti tp, a1, -167 - c.addi16sp sp, -16 - c.xor a4, a5 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - lui s3, 985951 - c.nop - addi gp, s8, -298 - mulh s1, t4, s11 - remu s6, s3, t1 - sltiu s3, tp, 300 - c.mv a2, a0 - c.li s11, -1 - c.addi4spn a2, sp, 528 - div s7, gp, a4 - rem a2, s2, s9 - xor s11, zero, s7 - c.addi16sp sp, -16 - c.and a4, s1 - c.srli a4, 9 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - c.xor a4, a5 - mulh s1, t4, s11 - andi t0, a3, 147 - mul tp, s2, t5 - or a4, a4, zero - slli a2, a4, 25 - xor s11, zero, s7 - c.li s11, -1 - c.and a4, s1 - sra s9, s4, t5 - sra s9, s4, t5 - divu tp, s5, t4 - srli zero, a0, 13 - xor s11, zero, s7 - divu tp, s5, t4 - sra s9, s4, t5 - andi t0, a3, 147 - add s4, a7, s6 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - sra s9, s4, t5 - remu s6, s3, t1 - c.add t3, t1 - sub s0, t3, gp - andi t0, a3, 147 - addi gp, s8, -298 - c.andi s1, 31 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - add s4, a7, s6 - c.xor a4, a5 - mulhsu tp, t5, a6 - srl t1, tp, zero - mulh s1, t4, s11 - div s7, gp, a4 - c.lui a6, 24 - sub s0, t3, gp - divu tp, s5, t4 - add s4, a7, s6 - rem a2, s2, s9 - sll s8, s0, s6 - auipc s1, 11691 - c.or a0, a2 - andi t0, a3, 147 - xori t3, t1, -721 - c.addi s9, -1 - c.addi16sp sp, -16 - c.andi s1, 31 - c.sub s0, s1 - sll s8, s0, s6 - c.lui a6, 24 - li t5, 0xffffffff #start riscv_int_numeric_corner_stream_21 - li a7, 0x0 - li s10, 0xffffffff - li s4, 0xca55fb0b - li s0, 0x39cd0672 - li t1, 0x16661571 - li sp, 0x3c77746c - li a0, 0xa8989e13 - li t2, 0xffffffff - li gp, 0x0 - nop - remu a7, gp, t1 - sub s10, a0, s10 - mulh gp, t2, t1 - mulh gp, t2, t1 - remu a7, gp, t1 - mul s0, t1, s0 - nop - mulhsu t2, s0, a7 - lui t1, 985951 - auipc s0, 11691 - sub s10, a0, s10 - lui t1, 985951 - remu a7, gp, t1 - divu sp, t2, a7 #end riscv_int_numeric_corner_stream_21 - remu s6, s3, t1 - and s6, t2, a4 - mulhsu tp, t5, a6 - mulh s1, t4, s11 - sra s9, s4, t5 - c.sub s0, s1 - divu tp, s5, t4 - c.li s11, -1 - c.xor a4, a5 - lui s3, 985951 - auipc s1, 11691 - slt a0, s5, s11 - c.addi4spn a2, sp, 528 - c.addi s9, -1 - srai a4, a3, 0 - sltiu s3, tp, 300 - c.sub s0, s1 - c.or a0, a2 - remu s6, s3, t1 - xor s11, zero, s7 - c.slli t5, 22 - ori tp, a0, -848 - div s7, gp, a4 - sub s0, t3, gp - c.li s11, -1 - c.addi16sp sp, -16 - sltu s3, a6, a4 - c.or a0, a2 - c.srli a4, 9 - c.addi s9, -1 - c.and a4, s1 - c.addi16sp sp, -16 - divu tp, s5, t4 - div s7, gp, a4 - c.mv a2, a0 - divu tp, s5, t4 - c.or a0, a2 - sltu s3, a6, a4 - slt a0, s5, s11 - c.lui a6, 24 - slti tp, a1, -167 - c.slli t5, 22 - sub s0, t3, gp - ori tp, a0, -848 - or a4, a4, zero - auipc s1, 11691 - divu tp, s5, t4 - srl t1, tp, zero - slli a2, a4, 25 - mul tp, s2, t5 - andi t0, a3, 147 - remu s6, s3, t1 - or a4, a4, zero - c.addi4spn a2, sp, 528 - c.slli t5, 22 - srai a4, a3, 0 - srli zero, a0, 13 - c.slli t5, 22 - srai a4, a3, 0 - addi gp, s8, -298 - xor s11, zero, s7 - c.nop - div s7, gp, a4 - addi gp, s8, -298 - srai a4, a3, 0 - srl t1, tp, zero - slt a0, s5, s11 - remu s6, s3, t1 - nop - addi gp, s8, -298 - addi gp, s8, -298 - c.srai s1, 28 - remu s6, s3, t1 - sll s8, s0, s6 - c.li s11, -1 - nop - slt a0, s5, s11 - c.lui a6, 24 - nop - c.xor a4, a5 - slti tp, a1, -167 - addi gp, s8, -298 - c.mv a2, a0 - slli a2, a4, 25 - add s4, a7, s6 - c.xor a4, a5 - add s4, a7, s6 - mulhu s4, a6, t3 - remu s6, s3, t1 - srai a4, a3, 0 - addi gp, s8, -298 - divu tp, s5, t4 - c.addi16sp sp, -16 - mulhu s4, a6, t3 - c.andi s1, 31 - c.andi s1, 31 - slli a2, a4, 25 - sll s8, s0, s6 - c.addi16sp sp, -16 - mul tp, s2, t5 - remu s6, s3, t1 - ori tp, a0, -848 - srli zero, a0, 13 - c.addi16sp sp, -16 - c.nop - rem a2, s2, s9 - srl t1, tp, zero - c.li s11, -1 - c.srai s1, 28 - c.or a0, a2 - add s4, a7, s6 - sll s8, s0, s6 - c.slli t5, 22 - div s7, gp, a4 - srli zero, a0, 13 - slti tp, a1, -167 - add s4, a7, s6 - slli a2, a4, 25 - mulhsu tp, t5, a6 - c.li s11, -1 - mulhu s4, a6, t3 - c.sub s0, s1 - c.addi16sp sp, -16 - c.srli a4, 9 - and s6, t2, a4 - rem a2, s2, s9 - srl t1, tp, zero - xor s11, zero, s7 - xor s11, zero, s7 - c.xor a4, a5 - or a4, a4, zero - ori tp, a0, -848 - remu s6, s3, t1 - c.li s11, -1 - sub s0, t3, gp - c.addi4spn a2, sp, 528 - andi t0, a3, 147 - sltu s3, a6, a4 - c.li s11, -1 - sll s8, s0, s6 - c.srai s1, 28 - rem a2, s2, s9 - mulh s1, t4, s11 - slti tp, a1, -167 - srli zero, a0, 13 - c.sub s0, s1 - c.add t3, t1 - srl t1, tp, zero - addi gp, s8, -298 - c.mv a2, a0 - mulhsu tp, t5, a6 - ori tp, a0, -848 - xori t3, t1, -721 - xor s11, zero, s7 - sll s8, s0, s6 - mulh s1, t4, s11 - andi t0, a3, 147 - andi t0, a3, 147 - divu tp, s5, t4 - rem a2, s2, s9 - mul tp, s2, t5 - divu tp, s5, t4 - sltiu s3, tp, 300 - c.add t3, t1 - divu tp, s5, t4 - c.or a0, a2 - c.nop - auipc s1, 11691 - c.slli t5, 22 - div s7, gp, a4 - mulhsu tp, t5, a6 - addi gp, s8, -298 - c.srli a4, 9 - ori tp, a0, -848 - srai a4, a3, 0 - srai a4, a3, 0 - lui s3, 985951 - xor s11, zero, s7 - slli a2, a4, 25 - andi t0, a3, 147 - andi t0, a3, 147 - mulhu s4, a6, t3 - c.xor a4, a5 - lui s3, 985951 - c.srai s1, 28 - slli a2, a4, 25 - srl t1, tp, zero - andi t0, a3, 147 - div s7, gp, a4 - lui s3, 985951 - c.andi s1, 31 - srli zero, a0, 13 - sub s0, t3, gp - c.addi s9, -1 - ori tp, a0, -848 - c.xor a4, a5 - srli zero, a0, 13 - mulhsu tp, t5, a6 - slli a2, a4, 25 - nop - c.or a0, a2 - mul tp, s2, t5 - srl t1, tp, zero - auipc s1, 11691 - c.mv a2, a0 - sll s8, s0, s6 - addi gp, s8, -298 - remu s6, s3, t1 - mulhsu tp, t5, a6 - div s7, gp, a4 - sltiu s3, tp, 300 - add s4, a7, s6 - rem a2, s2, s9 - c.xor a4, a5 - c.add t3, t1 - addi gp, s8, -298 - add s4, a7, s6 - xori t3, t1, -721 - c.li s11, -1 - xori t3, t1, -721 - mulhu s4, a6, t3 - mul tp, s2, t5 - sll s8, s0, s6 - c.andi s1, 31 - xor s11, zero, s7 - mulh s1, t4, s11 - sra s9, s4, t5 - sltiu s3, tp, 300 - c.or a0, a2 - xor s11, zero, s7 - div s7, gp, a4 - rem a2, s2, s9 - add s4, a7, s6 - sltu s3, a6, a4 - rem a2, s2, s9 - c.addi16sp sp, -16 - c.srli a4, 9 - c.add t3, t1 - c.nop - c.mv a2, a0 - c.add t3, t1 - divu tp, s5, t4 - remu s6, s3, t1 - slt a0, s5, s11 - slli a2, a4, 25 - div s7, gp, a4 - c.sub s0, s1 - slti tp, a1, -167 - mul tp, s2, t5 - sll s8, s0, s6 - srai a4, a3, 0 - slti tp, a1, -167 - c.srai s1, 28 - srai a4, a3, 0 - sll s8, s0, s6 - nop - c.li s11, -1 - srli zero, a0, 13 - slli a2, a4, 25 - sltu s3, a6, a4 - c.xor a4, a5 - slli a2, a4, 25 - c.and a4, s1 - c.and a4, s1 - nop - lui s3, 985951 - c.addi16sp sp, -16 - srl t1, tp, zero - or a4, a4, zero - c.srli a4, 9 - mulhsu tp, t5, a6 - or a4, a4, zero - sltu s3, a6, a4 - c.addi16sp sp, -16 - divu tp, s5, t4 - c.sub s0, s1 - or a4, a4, zero - and s6, t2, a4 - div s7, gp, a4 - slt a0, s5, s11 - sltiu s3, tp, 300 - c.mv a2, a0 - c.addi16sp sp, -16 - mulhu s4, a6, t3 - c.xor a4, a5 - and s6, t2, a4 - c.or a0, a2 - c.lui a6, 24 - c.andi s1, 31 - sra s9, s4, t5 - nop - remu s6, s3, t1 - c.addi16sp sp, -16 - c.addi s9, -1 - c.li s11, -1 - divu tp, s5, t4 - c.addi s9, -1 - divu tp, s5, t4 - ori tp, a0, -848 - srl t1, tp, zero - sra s9, s4, t5 - c.addi4spn a2, sp, 528 - xori t3, t1, -721 - andi t0, a3, 147 - addi gp, s8, -298 - xori t3, t1, -721 - mulhsu tp, t5, a6 - c.or a0, a2 - divu tp, s5, t4 - li ra, 0xffffffff #start riscv_int_numeric_corner_stream_20 - li t1, 0xcb010afa - li s1, 0xffffffff - li s7, 0x0 - li s5, 0x80000000 - li sp, 0x0 - li gp, 0x80000000 - li a6, 0x0 - li a2, 0x80000000 - li s6, 0x0 - divu a2, gp, a6 - addi s1, gp, -40 - nop - auipc s1, 11691 - divu a2, gp, a6 - add s7, t1, s6 - sub sp, a2, s5 - nop - div a6, s6, gp - lui gp, 985951 - add s7, t1, s6 - remu a2, s6, a2 - lui gp, 985951 - rem a2, sp, t1 - mul t1, s6, s1 #end riscv_int_numeric_corner_stream_20 - lui s3, 985951 - xor s11, zero, s7 - srai a4, a3, 0 - c.andi s1, 31 - srl t1, tp, zero - addi gp, s8, -298 - mulhsu tp, t5, a6 - rem a2, s2, s9 - and s6, t2, a4 - mul tp, s2, t5 - mulhsu tp, t5, a6 - srai a4, a3, 0 - mul tp, s2, t5 - mulhsu tp, t5, a6 - lui s3, 985951 - andi t0, a3, 147 - c.srai s1, 28 - c.slli t5, 22 - mulhu s4, a6, t3 - srli zero, a0, 13 - mulh s1, t4, s11 - xor s11, zero, s7 - auipc s1, 11691 - c.sub s0, s1 - divu tp, s5, t4 - mul tp, s2, t5 - c.slli t5, 22 - mul tp, s2, t5 - add s4, a7, s6 - xor s11, zero, s7 - c.li s11, -1 - srl t1, tp, zero - addi gp, s8, -298 - remu s6, s3, t1 - xori t3, t1, -721 - lui s3, 985951 - sltiu s3, tp, 300 - c.or a0, a2 - c.nop - c.slli t5, 22 - andi t0, a3, 147 - slli a2, a4, 25 - c.addi16sp sp, -16 - sra s9, s4, t5 - srl t1, tp, zero - divu tp, s5, t4 - c.add t3, t1 - mulhsu tp, t5, a6 - xor s11, zero, s7 - rem a2, s2, s9 - c.addi s9, -1 - srli zero, a0, 13 - xori t3, t1, -721 - sll s8, s0, s6 - remu s6, s3, t1 - c.add t3, t1 - c.slli t5, 22 - mulh s1, t4, s11 - sra s9, s4, t5 - srli zero, a0, 13 - div s7, gp, a4 - c.andi s1, 31 - slli a2, a4, 25 - add s4, a7, s6 - c.lui a6, 24 - c.srli a4, 9 - c.srli a4, 9 - sll s8, s0, s6 - or a4, a4, zero - c.addi16sp sp, -16 - srai a4, a3, 0 - auipc s1, 11691 - slti tp, a1, -167 - and s6, t2, a4 - mulhsu tp, t5, a6 - remu s6, s3, t1 - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - sub s0, t3, gp - srli zero, a0, 13 - c.and a4, s1 - andi t0, a3, 147 - srl t1, tp, zero - c.and a4, s1 - mulhsu tp, t5, a6 - c.xor a4, a5 - c.xor a4, a5 - slt a0, s5, s11 - add s4, a7, s6 - addi gp, s8, -298 - c.add t3, t1 - sltiu s3, tp, 300 - c.srli a4, 9 - or a4, a4, zero - srl t1, tp, zero - addi gp, s8, -298 - divu tp, s5, t4 - and s6, t2, a4 - c.and a4, s1 - nop - c.li s11, -1 - srl t1, tp, zero - auipc s1, 11691 - slli a2, a4, 25 - rem a2, s2, s9 - slt a0, s5, s11 - sll s8, s0, s6 - divu tp, s5, t4 - srli zero, a0, 13 - c.or a0, a2 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - c.or a0, a2 - mulhu s4, a6, t3 - c.srai s1, 28 - c.sub s0, s1 - remu s6, s3, t1 - c.slli t5, 22 - nop - andi t0, a3, 147 - and s6, t2, a4 - sub s0, t3, gp - c.slli t5, 22 - mul tp, s2, t5 - c.nop - lui s3, 985951 - c.srli a4, 9 - sltu s3, a6, a4 - mulhsu tp, t5, a6 - slli a2, a4, 25 - div s7, gp, a4 - slli a2, a4, 25 - c.add t3, t1 - li a3, 0x510d6db9 #start riscv_int_numeric_corner_stream_1 - li a0, 0xfea2006a - li tp, 0xbb5a5c20 - li t4, 0x0 - li t2, 0x80000000 - li s0, 0x0 - li ra, 0xffffffff - li s8, 0x0 - li gp, 0x1880902 - li a4, 0xffffffff - nop - addi ra, gp, -40 - sub a0, ra, t4 - auipc s0, 11691 - rem t4, gp, t2 - auipc s0, 11691 - nop - auipc s0, 11691 - nop - mulhsu a4, s0, ra - nop - nop - auipc s0, 11691 - nop - mulh s8, t4, tp #end riscv_int_numeric_corner_stream_1 - c.addi16sp sp, -16 - c.mv a2, a0 - nop - mul tp, s2, t5 - c.addi16sp sp, -16 - li s10, 0x0 #start riscv_int_numeric_corner_stream_9 - li s5, 0x80000000 - li a7, 0xe1480c42 - li s3, 0x80000000 - li tp, 0xa7f765d2 - li gp, 0x51c5e20f - li t0, 0x6b1abb01 - li t5, 0x0 - li ra, 0xf5603a3b - li s0, 0xa5cf641c - divu s0, gp, a7 - mul gp, s3, s0 - addi s10, s10, -40 - mulhu s0, s0, t5 - nop - lui s3, 985951 - add t5, tp, t5 - mulhsu t5, s3, ra - add t5, tp, t5 - nop - nop - nop - nop - nop - addi s10, s10, -40 #end riscv_int_numeric_corner_stream_9 - c.sub s0, s1 - c.srli a4, 9 - c.srli a4, 9 - c.slli t5, 22 - c.addi4spn a2, sp, 528 - mul tp, s2, t5 - slli a2, a4, 25 - c.srai s1, 28 - c.srai s1, 28 - c.and a4, s1 - c.mv a2, a0 - sltiu s3, tp, 300 - c.andi s1, 31 - c.xor a4, a5 - c.and a4, s1 - and s6, t2, a4 - sltiu s3, tp, 300 - srl t1, tp, zero - c.addi16sp sp, -16 - c.addi4spn a2, sp, 528 - slt a0, s5, s11 - srli zero, a0, 13 - c.li s11, -1 - c.addi s9, -1 - and s6, t2, a4 - mulh s1, t4, s11 - c.srli a4, 9 - c.srli a4, 9 - or a4, a4, zero - sll s8, s0, s6 - c.nop - c.li s11, -1 - sra s9, s4, t5 - and s6, t2, a4 - srl t1, tp, zero - c.lui a6, 24 - mul tp, s2, t5 - mulh s1, t4, s11 - add s4, a7, s6 - c.srli a4, 9 - c.and a4, s1 - c.add t3, t1 - c.and a4, s1 - xori t3, t1, -721 - c.srli a4, 9 - mulhu s4, a6, t3 - srai a4, a3, 0 - c.srai s1, 28 - sltu s3, a6, a4 - slti tp, a1, -167 - srai a4, a3, 0 - addi gp, s8, -298 - c.srai s1, 28 - remu s6, s3, t1 - lui s3, 985951 - remu s6, s3, t1 - sub s0, t3, gp - add s4, a7, s6 - xori t3, t1, -721 - mul tp, s2, t5 - mulhsu tp, t5, a6 - c.andi s1, 31 - ori tp, a0, -848 - c.or a0, a2 - c.nop - slli a2, a4, 25 - c.srli a4, 9 - sll s8, s0, s6 - srli zero, a0, 13 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - lui s3, 985951 - rem a2, s2, s9 - mulhu s4, a6, t3 - c.or a0, a2 - rem a2, s2, s9 - c.li s11, -1 - rem a2, s2, s9 - srli zero, a0, 13 - c.li s11, -1 - andi t0, a3, 147 - xor s11, zero, s7 - c.lui a6, 24 - c.andi s1, 31 - c.add t3, t1 - or a4, a4, zero - divu tp, s5, t4 - c.addi s9, -1 - c.sub s0, s1 - c.li s11, -1 - sub s0, t3, gp - slt a0, s5, s11 - c.srai s1, 28 - c.srli a4, 9 - c.li s11, -1 - c.addi s9, -1 - slli a2, a4, 25 - sll s8, s0, s6 - divu tp, s5, t4 - andi t0, a3, 147 - divu tp, s5, t4 - auipc s1, 11691 - c.or a0, a2 - c.addi4spn a2, sp, 528 - mulh s1, t4, s11 - xor s11, zero, s7 - xori t3, t1, -721 - or a4, a4, zero - c.sub s0, s1 - slti tp, a1, -167 - divu tp, s5, t4 - mulh s1, t4, s11 - sll s8, s0, s6 - c.nop - c.mv a2, a0 - srl t1, tp, zero - sll s8, s0, s6 - sub s0, t3, gp - c.sub s0, s1 - c.lui a6, 24 - c.mv a2, a0 - xori t3, t1, -721 - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - c.mv a2, a0 - c.sub s0, s1 - c.or a0, a2 - c.andi s1, 31 - ori tp, a0, -848 - sub s0, t3, gp - c.nop - srl t1, tp, zero - or a4, a4, zero - add s4, a7, s6 - sltu s3, a6, a4 - addi gp, s8, -298 - andi t0, a3, 147 - c.li s11, -1 - c.slli t5, 22 - c.lui a6, 24 - c.slli t5, 22 - c.and a4, s1 - srli zero, a0, 13 - srl t1, tp, zero - c.slli t5, 22 - xori t3, t1, -721 - andi t0, a3, 147 - sltu s3, a6, a4 - c.andi s1, 31 - sll s8, s0, s6 - or a4, a4, zero - or a4, a4, zero - c.andi s1, 31 - rem a2, s2, s9 - add s4, a7, s6 - mul tp, s2, t5 - c.and a4, s1 - sra s9, s4, t5 - c.addi s9, -1 - c.sub s0, s1 - c.slli t5, 22 - slti tp, a1, -167 - sra s9, s4, t5 - andi t0, a3, 147 - or a4, a4, zero - c.xor a4, a5 - ori tp, a0, -848 - srl t1, tp, zero - c.sub s0, s1 - c.slli t5, 22 - lui s3, 985951 - addi gp, s8, -298 - xor s11, zero, s7 - lui s3, 985951 - ori tp, a0, -848 - sll s8, s0, s6 - c.or a0, a2 - or a4, a4, zero - remu s6, s3, t1 - c.slli t5, 22 - c.mv a2, a0 - c.addi s9, -1 - div s7, gp, a4 - srl t1, tp, zero - andi t0, a3, 147 - c.addi s9, -1 - mul tp, s2, t5 - c.sub s0, s1 - div s7, gp, a4 - c.srli a4, 9 - sll s8, s0, s6 - nop - sub s0, t3, gp - c.xor a4, a5 - c.li s11, -1 - divu tp, s5, t4 - c.slli t5, 22 - sltiu s3, tp, 300 - mulhsu tp, t5, a6 - nop - mulhu s4, a6, t3 - andi t0, a3, 147 - xor s11, zero, s7 - c.slli t5, 22 - c.mv a2, a0 - c.or a0, a2 - auipc s1, 11691 - or a4, a4, zero - c.srai s1, 28 - c.and a4, s1 - c.sub s0, s1 - and s6, t2, a4 - and s6, t2, a4 - mulh s1, t4, s11 - div s7, gp, a4 - divu tp, s5, t4 - add s4, a7, s6 - srai a4, a3, 0 - xor s11, zero, s7 - slli a2, a4, 25 - srli zero, a0, 13 - c.srai s1, 28 - andi t0, a3, 147 - c.addi16sp sp, -16 - srai a4, a3, 0 - c.addi s9, -1 - add s4, a7, s6 - mul tp, s2, t5 - c.slli t5, 22 - c.li s11, -1 - mulhsu tp, t5, a6 - slti tp, a1, -167 - divu tp, s5, t4 - c.and a4, s1 - c.li s11, -1 - c.srai s1, 28 - c.nop - xori t3, t1, -721 - xori t3, t1, -721 - ori tp, a0, -848 - srli zero, a0, 13 - c.li s11, -1 - c.xor a4, a5 - lui s3, 985951 - c.mv a2, a0 - c.andi s1, 31 - c.slli t5, 22 - c.li s11, -1 - c.srai s1, 28 - slt a0, s5, s11 - slti tp, a1, -167 - xori t3, t1, -721 - divu tp, s5, t4 - c.and a4, s1 - lui s3, 985951 - rem a2, s2, s9 - sll s8, s0, s6 - sll s8, s0, s6 - c.add t3, t1 - mul tp, s2, t5 - slt a0, s5, s11 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - sltu s3, a6, a4 - srai a4, a3, 0 - c.andi s1, 31 - xori t3, t1, -721 - mulh s1, t4, s11 - nop - sra s9, s4, t5 - slt a0, s5, s11 - c.srai s1, 28 - sub s0, t3, gp - c.srli a4, 9 - remu s6, s3, t1 - nop - slti tp, a1, -167 - sra s9, s4, t5 - slli a2, a4, 25 - srl t1, tp, zero - sltiu s3, tp, 300 - c.add t3, t1 - sltu s3, a6, a4 - slt a0, s5, s11 - addi gp, s8, -298 - srli zero, a0, 13 - divu tp, s5, t4 - sltu s3, a6, a4 - c.srli a4, 9 - divu tp, s5, t4 - sltu s3, a6, a4 - c.sub s0, s1 - slli a2, a4, 25 - c.mv a2, a0 - andi t0, a3, 147 - c.nop - c.li s11, -1 - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - mulhu s4, a6, t3 - lui s3, 985951 - xori t3, t1, -721 - and s6, t2, a4 - lui s3, 985951 - c.srli a4, 9 - divu tp, s5, t4 - c.or a0, a2 - c.addi16sp sp, -16 - c.add t3, t1 - c.add t3, t1 - divu tp, s5, t4 - mulhu s4, a6, t3 - remu s6, s3, t1 - sra s9, s4, t5 - c.li s11, -1 - c.slli t5, 22 - lui s3, 985951 - mul tp, s2, t5 - c.lui a6, 24 - slli a2, a4, 25 - c.mv a2, a0 - c.nop - slti tp, a1, -167 - c.lui a6, 24 - c.addi16sp sp, -16 - mulhsu tp, t5, a6 - c.li s11, -1 - and s6, t2, a4 - rem a2, s2, s9 - sltiu s3, tp, 300 - c.addi16sp sp, -16 - rem a2, s2, s9 - c.li s11, -1 - or a4, a4, zero - c.or a0, a2 - and s6, t2, a4 - c.addi16sp sp, -16 - c.xor a4, a5 - or a4, a4, zero - sra s9, s4, t5 - rem a2, s2, s9 - mulh s1, t4, s11 - lui s3, 985951 - c.addi4spn a2, sp, 528 - srl t1, tp, zero - srl t1, tp, zero - sub s0, t3, gp - srli zero, a0, 13 - srl t1, tp, zero - xor s11, zero, s7 - c.xor a4, a5 - srl t1, tp, zero - c.slli t5, 22 - rem a2, s2, s9 - andi t0, a3, 147 - auipc s1, 11691 - mulh s1, t4, s11 - and s6, t2, a4 - c.srai s1, 28 - sltiu s3, tp, 300 - sltu s3, a6, a4 - sltiu s3, tp, 300 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - ori tp, a0, -848 - or a4, a4, zero - c.addi s9, -1 - add s4, a7, s6 - div s7, gp, a4 - mul tp, s2, t5 - andi t0, a3, 147 - auipc s1, 11691 - c.lui a6, 24 - mul tp, s2, t5 - slt a0, s5, s11 - rem a2, s2, s9 - add s4, a7, s6 - c.and a4, s1 - srai a4, a3, 0 - sltiu s3, tp, 300 - addi gp, s8, -298 - and s6, t2, a4 - c.slli t5, 22 - c.sub s0, s1 - sll s8, s0, s6 - srli zero, a0, 13 - slt a0, s5, s11 - slti tp, a1, -167 - xor s11, zero, s7 - nop - divu tp, s5, t4 - c.or a0, a2 - mul tp, s2, t5 - srai a4, a3, 0 - mul tp, s2, t5 - sub s0, t3, gp - ori tp, a0, -848 - srai a4, a3, 0 - nop - srai a4, a3, 0 - or a4, a4, zero - srl t1, tp, zero - xor s11, zero, s7 - slt a0, s5, s11 - c.li s11, -1 - c.li s11, -1 - c.addi16sp sp, -16 - xori t3, t1, -721 - c.addi s9, -1 - c.add t3, t1 - c.andi s1, 31 - remu s6, s3, t1 - and s6, t2, a4 - sltiu s3, tp, 300 - c.li s11, -1 - ori tp, a0, -848 - mul tp, s2, t5 - rem a2, s2, s9 - c.addi s9, -1 - mulhu s4, a6, t3 - or a4, a4, zero - sltiu s3, tp, 300 - mulh s1, t4, s11 - c.srai s1, 28 - mul tp, s2, t5 - andi t0, a3, 147 - c.xor a4, a5 - c.xor a4, a5 - sll s8, s0, s6 - auipc s1, 11691 - sra s9, s4, t5 - rem a2, s2, s9 - c.addi4spn a2, sp, 528 - c.add t3, t1 - mulhu s4, a6, t3 - c.sub s0, s1 - lui s3, 985951 - addi gp, s8, -298 - div s7, gp, a4 - mul tp, s2, t5 - slli a2, a4, 25 - slli a2, a4, 25 - c.srai s1, 28 - c.srai s1, 28 - slt a0, s5, s11 - slli a2, a4, 25 - slt a0, s5, s11 - c.and a4, s1 - c.srai s1, 28 - andi t0, a3, 147 - sra s9, s4, t5 - remu s6, s3, t1 - c.mv a2, a0 - sll s8, s0, s6 - c.sub s0, s1 - mulhu s4, a6, t3 - c.srai s1, 28 - c.lui a6, 24 - lui s3, 985951 - lui s3, 985951 - xori t3, t1, -721 - slli a2, a4, 25 - c.sub s0, s1 - c.addi16sp sp, -16 - sltiu s3, tp, 300 - slti tp, a1, -167 - c.xor a4, a5 - lui s3, 985951 - c.or a0, a2 - ori tp, a0, -848 - c.and a4, s1 - c.xor a4, a5 - xori t3, t1, -721 - c.mv a2, a0 - sltu s3, a6, a4 - c.xor a4, a5 - sub s0, t3, gp - mul tp, s2, t5 - sra s9, s4, t5 - xor s11, zero, s7 - ori tp, a0, -848 - xor s11, zero, s7 - c.andi s1, 31 - divu tp, s5, t4 - mulh s1, t4, s11 - div s7, gp, a4 - c.add t3, t1 - lui s3, 985951 - add s4, a7, s6 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - andi t0, a3, 147 - srl t1, tp, zero - c.sub s0, s1 - andi t0, a3, 147 - slt a0, s5, s11 - c.and a4, s1 - sub s0, t3, gp - c.addi16sp sp, -16 - mulhsu tp, t5, a6 - sltu s3, a6, a4 - nop - mulhu s4, a6, t3 - slt a0, s5, s11 - sub s0, t3, gp - c.andi s1, 31 - mul tp, s2, t5 - slti tp, a1, -167 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - or a4, a4, zero - c.mv a2, a0 - c.xor a4, a5 - div s7, gp, a4 - sra s9, s4, t5 - c.andi s1, 31 - divu tp, s5, t4 - nop - c.mv a2, a0 - c.xor a4, a5 - and s6, t2, a4 - add s4, a7, s6 - remu s6, s3, t1 - slti tp, a1, -167 - c.nop - mulhu s4, a6, t3 - div s7, gp, a4 - c.addi s9, -1 - c.li s11, -1 - srl t1, tp, zero - slti tp, a1, -167 - c.addi4spn a2, sp, 528 - c.addi16sp sp, -16 - rem a2, s2, s9 - sltu s3, a6, a4 - divu tp, s5, t4 - rem a2, s2, s9 - c.slli t5, 22 - srl t1, tp, zero - c.sub s0, s1 - c.and a4, s1 - mul tp, s2, t5 - sltiu s3, tp, 300 - c.andi s1, 31 - srai a4, a3, 0 - sll s8, s0, s6 - rem a2, s2, s9 - ori tp, a0, -848 - remu s6, s3, t1 - srl t1, tp, zero - lui s3, 985951 - slti tp, a1, -167 - auipc s1, 11691 - c.li s11, -1 - ori tp, a0, -848 - mulhu s4, a6, t3 - slt a0, s5, s11 - xori t3, t1, -721 - srai a4, a3, 0 - slti tp, a1, -167 - c.add t3, t1 - sll s8, s0, s6 - add s4, a7, s6 - mulhu s4, a6, t3 - mulhsu tp, t5, a6 - c.addi4spn a2, sp, 528 - c.nop - c.or a0, a2 - add s4, a7, s6 - auipc s1, 11691 - srli zero, a0, 13 - sll s8, s0, s6 - sub s0, t3, gp - c.lui a6, 24 - c.slli t5, 22 - slti tp, a1, -167 - c.sub s0, s1 - c.srai s1, 28 - divu tp, s5, t4 - c.addi16sp sp, -16 - sra s9, s4, t5 - c.xor a4, a5 - sltiu s3, tp, 300 - remu s6, s3, t1 - sll s8, s0, s6 - c.srai s1, 28 - srl t1, tp, zero - ori tp, a0, -848 - c.addi4spn a2, sp, 528 - sltiu s3, tp, 300 - mulh s1, t4, s11 - sltu s3, a6, a4 - c.addi16sp sp, -16 - c.sub s0, s1 - c.slli t5, 22 - c.sub s0, s1 - xor s11, zero, s7 - or a4, a4, zero - c.li s11, -1 - add s4, a7, s6 - slli a2, a4, 25 - and s6, t2, a4 - ori tp, a0, -848 - c.add t3, t1 - c.mv a2, a0 - c.sub s0, s1 - c.lui a6, 24 - c.sub s0, s1 - c.and a4, s1 - c.addi4spn a2, sp, 528 - xor s11, zero, s7 - slti tp, a1, -167 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - c.srli a4, 9 - mulhsu tp, t5, a6 - slt a0, s5, s11 - slti tp, a1, -167 - nop - ori tp, a0, -848 - add s4, a7, s6 - xor s11, zero, s7 - mul tp, s2, t5 - remu s6, s3, t1 - nop - sra s9, s4, t5 - srl t1, tp, zero - c.andi s1, 31 - addi gp, s8, -298 - rem a2, s2, s9 - c.slli t5, 22 - c.or a0, a2 - mulhu s4, a6, t3 - xor s11, zero, s7 - c.sub s0, s1 - or a4, a4, zero - mul tp, s2, t5 - or a4, a4, zero - c.addi s9, -1 - mulhsu tp, t5, a6 - sltu s3, a6, a4 - c.addi s9, -1 - sltiu s3, tp, 300 - remu s6, s3, t1 - sub s0, t3, gp - c.addi s9, -1 - c.and a4, s1 - div s7, gp, a4 - c.andi s1, 31 - lui s3, 985951 - nop - srai a4, a3, 0 - sltiu s3, tp, 300 - sub s0, t3, gp - srai a4, a3, 0 - c.addi4spn a2, sp, 528 - c.nop - addi gp, s8, -298 - c.srai s1, 28 - and s6, t2, a4 - sltu s3, a6, a4 - c.slli t5, 22 - mulhsu tp, t5, a6 - srl t1, tp, zero - slt a0, s5, s11 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - c.and a4, s1 - sub s0, t3, gp - c.add t3, t1 - and s6, t2, a4 - andi t0, a3, 147 - remu s6, s3, t1 - remu s6, s3, t1 - srli zero, a0, 13 - srli zero, a0, 13 - c.li s11, -1 - c.and a4, s1 - c.addi s9, -1 - c.sub s0, s1 - and s6, t2, a4 - addi gp, s8, -298 - c.lui a6, 24 - c.xor a4, a5 - c.addi16sp sp, -16 - sltu s3, a6, a4 - mul tp, s2, t5 - srai a4, a3, 0 - c.and a4, s1 - srli zero, a0, 13 - sll s8, s0, s6 - auipc s1, 11691 - sub s0, t3, gp - c.addi16sp sp, -16 - auipc s1, 11691 - c.addi s9, -1 - nop - mulhsu tp, t5, a6 - c.addi s9, -1 - c.slli t5, 22 - addi gp, s8, -298 - c.srli a4, 9 - slti tp, a1, -167 - addi gp, s8, -298 - divu tp, s5, t4 - sltiu s3, tp, 300 - mul tp, s2, t5 - and s6, t2, a4 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - c.lui a6, 24 - ori tp, a0, -848 - c.addi s9, -1 - mulh s1, t4, s11 - srl t1, tp, zero - auipc s1, 11691 - slt a0, s5, s11 - c.nop - c.srli a4, 9 - andi t0, a3, 147 - add s4, a7, s6 - nop - c.sub s0, s1 - mul tp, s2, t5 - sltu s3, a6, a4 - lui s3, 985951 - div s7, gp, a4 - xor s11, zero, s7 - sra s9, s4, t5 - sltu s3, a6, a4 - c.nop - sltiu s3, tp, 300 - auipc s1, 11691 - c.addi16sp sp, -16 - ori tp, a0, -848 - sra s9, s4, t5 - xor s11, zero, s7 - mulh s1, t4, s11 - c.addi16sp sp, -16 - slt a0, s5, s11 - lui s3, 985951 - c.srai s1, 28 - c.li s11, -1 - c.addi4spn a2, sp, 528 - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - mul tp, s2, t5 - sltiu s3, tp, 300 - c.li s11, -1 - xori t3, t1, -721 - rem a2, s2, s9 - add s4, a7, s6 - c.li s11, -1 - andi t0, a3, 147 - slt a0, s5, s11 - xori t3, t1, -721 - mulh s1, t4, s11 - slli a2, a4, 25 - c.nop - sltu s3, a6, a4 - c.or a0, a2 - mulhsu tp, t5, a6 - srl t1, tp, zero - mulhu s4, a6, t3 - slli a2, a4, 25 - srai a4, a3, 0 - srli zero, a0, 13 - add s4, a7, s6 - slti tp, a1, -167 - mulhsu tp, t5, a6 - div s7, gp, a4 - xor s11, zero, s7 - c.nop - c.mv a2, a0 - c.addi16sp sp, -16 - xor s11, zero, s7 - or a4, a4, zero - xor s11, zero, s7 - sltiu s3, tp, 300 - sll s8, s0, s6 - remu s6, s3, t1 - remu s6, s3, t1 - c.nop - addi gp, s8, -298 - c.slli t5, 22 - c.and a4, s1 - sltiu s3, tp, 300 - sltu s3, a6, a4 - c.mv a2, a0 - mulhu s4, a6, t3 - c.mv a2, a0 - c.xor a4, a5 - c.xor a4, a5 - sltiu s3, tp, 300 - slli a2, a4, 25 - c.li s11, -1 - andi t0, a3, 147 - c.add t3, t1 - remu s6, s3, t1 - c.addi s9, -1 - c.xor a4, a5 - c.or a0, a2 - sll s8, s0, s6 - c.srli a4, 9 - remu s6, s3, t1 - srli zero, a0, 13 - nop - c.xor a4, a5 - auipc s1, 11691 - c.and a4, s1 - sltiu s3, tp, 300 - c.lui a6, 24 - xori t3, t1, -721 - mulh s1, t4, s11 - c.srli a4, 9 - c.addi s9, -1 - auipc s1, 11691 - and s6, t2, a4 - c.or a0, a2 - mulhsu tp, t5, a6 - mulh s1, t4, s11 - sltu s3, a6, a4 - slt a0, s5, s11 - xor s11, zero, s7 - c.addi4spn a2, sp, 528 - c.srai s1, 28 - add s4, a7, s6 - addi gp, s8, -298 - sub s0, t3, gp - divu tp, s5, t4 - mulh s1, t4, s11 - mulhsu tp, t5, a6 - c.srli a4, 9 - andi t0, a3, 147 - auipc s1, 11691 - lui s3, 985951 - sltiu s3, tp, 300 - c.and a4, s1 - c.andi s1, 31 - rem a2, s2, s9 - sltu s3, a6, a4 - div s7, gp, a4 - c.xor a4, a5 - divu tp, s5, t4 - slti tp, a1, -167 - c.addi16sp sp, -16 - c.addi16sp sp, -16 - and s6, t2, a4 - or a4, a4, zero - slti tp, a1, -167 - slt a0, s5, s11 - c.addi4spn a2, sp, 528 - c.srli a4, 9 - xor s11, zero, s7 - sra s9, s4, t5 - c.slli t5, 22 - c.or a0, a2 - nop - rem a2, s2, s9 - remu s6, s3, t1 - c.li s11, -1 - c.addi16sp sp, -16 - c.lui a6, 24 - li sp, 0x80000000 #start riscv_int_numeric_corner_stream_25 - li s3, 0x80000000 - li s1, 0x0 - li t2, 0x80000000 - li t5, 0x80000000 - li a2, 0x80000000 - li gp, 0x80000000 - li t3, 0x80000000 - li a3, 0x80000000 - li s5, 0xffffffff - rem a2, sp, t2 - addi s1, s3, -40 - mulhu s5, sp, t5 - mulhsu t5, t2, gp - remu s1, s3, a2 - rem a2, sp, t2 - lui s3, 985951 - mul t2, a2, a3 - remu s1, s3, a2 - add t5, sp, t5 - nop - mulhu s5, sp, t5 - lui s3, 985951 - lui s3, 985951 - sub sp, s1, t3 - sub sp, s1, t3 - sub sp, s1, t3 - remu s1, s3, a2 - mulhu s5, sp, t5 #end riscv_int_numeric_corner_stream_25 - c.li s11, -1 - xori t3, t1, -721 - c.andi s1, 31 - sra s9, s4, t5 - slt a0, s5, s11 - ori tp, a0, -848 - c.and a4, s1 - c.addi16sp sp, -16 - remu s6, s3, t1 - mulhsu tp, t5, a6 - mulhsu tp, t5, a6 - c.slli t5, 22 - c.lui a6, 24 - sll s8, s0, s6 - mulhsu tp, t5, a6 - mulhsu tp, t5, a6 - c.li s11, -1 - mulhsu tp, t5, a6 - div s7, gp, a4 - nop - c.addi4spn a2, sp, 528 - slt a0, s5, s11 - xor s11, zero, s7 - c.addi s9, -1 - nop - sub s0, t3, gp - nop - add s4, a7, s6 - ori tp, a0, -848 - c.slli t5, 22 - srai a4, a3, 0 - mulh s1, t4, s11 - srl t1, tp, zero - ori tp, a0, -848 - c.slli t5, 22 - c.li s11, -1 - c.srli a4, 9 - c.lui a6, 24 - c.mv a2, a0 - remu s6, s3, t1 - c.addi s9, -1 - or a4, a4, zero - divu tp, s5, t4 - sub s0, t3, gp - xori t3, t1, -721 - c.andi s1, 31 - srli zero, a0, 13 - sltiu s3, tp, 300 - srai a4, a3, 0 - slt a0, s5, s11 - c.lui a6, 24 - c.or a0, a2 - c.addi16sp sp, -16 - c.or a0, a2 - andi t0, a3, 147 - c.or a0, a2 - c.nop - xori t3, t1, -721 - xori t3, t1, -721 - remu s6, s3, t1 - slt a0, s5, s11 - c.li s11, -1 - c.addi s9, -1 - c.sub s0, s1 - srl t1, tp, zero - mulhsu tp, t5, a6 - xori t3, t1, -721 - add s4, a7, s6 - sll s8, s0, s6 - slli a2, a4, 25 - mulhu s4, a6, t3 - ori tp, a0, -848 - c.lui a6, 24 - c.srai s1, 28 - slt a0, s5, s11 - nop - sltu s3, a6, a4 - add s4, a7, s6 - auipc s1, 11691 - c.li s11, -1 - rem a2, s2, s9 - xori t3, t1, -721 - c.li s11, -1 - sll s8, s0, s6 - c.andi s1, 31 - rem a2, s2, s9 - c.xor a4, a5 - c.add t3, t1 - sltiu s3, tp, 300 - c.lui a6, 24 - c.li s11, -1 - and s6, t2, a4 - mulhsu tp, t5, a6 - c.addi s9, -1 - slti tp, a1, -167 - mulhsu tp, t5, a6 - add s4, a7, s6 - c.or a0, a2 - c.lui a6, 24 - mul tp, s2, t5 - c.li s11, -1 - c.srli a4, 9 - mulhsu tp, t5, a6 - ori tp, a0, -848 - remu s6, s3, t1 - c.nop - sra s9, s4, t5 - nop - c.slli t5, 22 - auipc s1, 11691 - and s6, t2, a4 - remu s6, s3, t1 - mulhu s4, a6, t3 - mulhsu tp, t5, a6 - c.srai s1, 28 - c.sub s0, s1 - c.srli a4, 9 - ori tp, a0, -848 - slti tp, a1, -167 - c.slli t5, 22 - srai a4, a3, 0 - rem a2, s2, s9 - c.and a4, s1 - addi gp, s8, -298 - c.and a4, s1 - slli a2, a4, 25 - lui s3, 985951 - andi t0, a3, 147 - c.sub s0, s1 - div s7, gp, a4 - srl t1, tp, zero - remu s6, s3, t1 - sltu s3, a6, a4 - addi gp, s8, -298 - remu s6, s3, t1 - c.addi4spn a2, sp, 528 - slt a0, s5, s11 - add s4, a7, s6 - divu tp, s5, t4 - mul tp, s2, t5 - andi t0, a3, 147 - c.addi s9, -1 - ori tp, a0, -848 - addi gp, s8, -298 - c.sub s0, s1 - add s4, a7, s6 - ori tp, a0, -848 - divu tp, s5, t4 - slli a2, a4, 25 - xor s11, zero, s7 - xori t3, t1, -721 - c.sub s0, s1 - srai a4, a3, 0 - srai a4, a3, 0 - andi t0, a3, 147 - c.addi s9, -1 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - div s7, gp, a4 - c.slli t5, 22 - div s7, gp, a4 - c.sub s0, s1 - c.xor a4, a5 - c.srai s1, 28 - c.and a4, s1 - c.mv a2, a0 - ori tp, a0, -848 - c.mv a2, a0 - srl t1, tp, zero - nop - c.xor a4, a5 - c.addi s9, -1 - or a4, a4, zero - c.srai s1, 28 - sra s9, s4, t5 - rem a2, s2, s9 - and s6, t2, a4 - c.or a0, a2 - nop - c.addi4spn a2, sp, 528 - xori t3, t1, -721 - remu s6, s3, t1 - sub s0, t3, gp - c.lui a6, 24 - addi gp, s8, -298 - addi gp, s8, -298 - add s4, a7, s6 - xori t3, t1, -721 - and s6, t2, a4 - xor s11, zero, s7 - xori t3, t1, -721 - c.srli a4, 9 - li s10, 0x0 #start riscv_int_numeric_corner_stream_13 - li s7, 0x0 - li a4, 0xffffffff - li s8, 0xffffffff - li t4, 0x1fef3313 - li a6, 0x0 - li s5, 0x80000000 - li a2, 0x0 - li s4, 0x5e753a47 - li s1, 0x80000000 - mulhu a2, a4, t4 - mul a4, s4, a4 - nop - nop - nop - nop - lui s7, 985951 - lui s7, 985951 - lui s7, 985951 - nop - lui s7, 985951 - divu s10, a4, s8 - sub s10, a4, s8 - lui s7, 985951 - div s1, t4, a6 - sub s10, a4, s8 - addi s1, s10, -40 - mulhsu a4, s1, s5 - add s4, a2, s10 - mul a4, s4, a4 - divu s10, a4, s8 - lui s7, 985951 - mulh a4, s1, s1 - lui s7, 985951 - nop - remu a4, s10, a4 - add s4, a2, s10 - addi s1, s10, -40 - nop #end riscv_int_numeric_corner_stream_13 - mulhsu tp, t5, a6 - ori tp, a0, -848 - or a4, a4, zero - mul tp, s2, t5 - or a4, a4, zero - auipc s1, 11691 - add s4, a7, s6 - lui s3, 985951 - c.srli a4, 9 - c.li s11, -1 - and s6, t2, a4 - sltiu s3, tp, 300 - c.addi s9, -1 - c.lui a6, 24 - sub s0, t3, gp - slli a2, a4, 25 - add s4, a7, s6 - lui s3, 985951 - mulhsu tp, t5, a6 - sll s8, s0, s6 - auipc s1, 11691 - c.slli t5, 22 - c.and a4, s1 - c.addi4spn a2, sp, 528 - c.nop - slti tp, a1, -167 - srl t1, tp, zero - sub s0, t3, gp - c.addi s9, -1 - c.lui a6, 24 - c.or a0, a2 - c.sub s0, s1 - c.or a0, a2 - ori tp, a0, -848 - mul tp, s2, t5 - sltu s3, a6, a4 - or a4, a4, zero - c.nop - auipc s1, 11691 - sltu s3, a6, a4 - c.add t3, t1 - c.srai s1, 28 - c.li s11, -1 - c.xor a4, a5 - mul tp, s2, t5 - auipc s1, 11691 - c.lui a6, 24 - c.andi s1, 31 - xor s11, zero, s7 - mulh s1, t4, s11 - addi gp, s8, -298 - c.and a4, s1 - c.and a4, s1 - mulhu s4, a6, t3 - slti tp, a1, -167 - mulhsu tp, t5, a6 - andi t0, a3, 147 - or a4, a4, zero - addi gp, s8, -298 - c.li s11, -1 - c.li s11, -1 - mulh s1, t4, s11 - nop - divu tp, s5, t4 - or a4, a4, zero - slti tp, a1, -167 - add s4, a7, s6 - addi gp, s8, -298 - xor s11, zero, s7 - c.addi s9, -1 - c.add t3, t1 - sltu s3, a6, a4 - mul tp, s2, t5 - mul tp, s2, t5 - divu tp, s5, t4 - andi t0, a3, 147 - nop - c.andi s1, 31 - add s4, a7, s6 - and s6, t2, a4 - slt a0, s5, s11 - divu tp, s5, t4 - xori t3, t1, -721 - xori t3, t1, -721 - xor s11, zero, s7 - sltu s3, a6, a4 - remu s6, s3, t1 - xori t3, t1, -721 - c.andi s1, 31 - c.slli t5, 22 - mulhsu tp, t5, a6 - div s7, gp, a4 - auipc s1, 11691 - xori t3, t1, -721 - add s4, a7, s6 - slli a2, a4, 25 - c.nop - auipc s1, 11691 - c.xor a4, a5 - sra s9, s4, t5 - addi gp, s8, -298 - and s6, t2, a4 - c.addi s9, -1 - c.and a4, s1 - sll s8, s0, s6 - add s4, a7, s6 - sll s8, s0, s6 - c.srai s1, 28 - c.or a0, a2 - mul tp, s2, t5 - sub s0, t3, gp - c.add t3, t1 - xor s11, zero, s7 - remu s6, s3, t1 - nop - c.srli a4, 9 - sll s8, s0, s6 - slt a0, s5, s11 - c.addi16sp sp, -16 - auipc s1, 11691 - c.andi s1, 31 - c.sub s0, s1 - c.srai s1, 28 - srl t1, tp, zero - nop - lui s3, 985951 - sub s0, t3, gp - c.andi s1, 31 - ori tp, a0, -848 - mulhu s4, a6, t3 - c.or a0, a2 - mulhu s4, a6, t3 - auipc s1, 11691 - srli zero, a0, 13 - sra s9, s4, t5 - slti tp, a1, -167 - c.addi s9, -1 - c.mv a2, a0 - c.li s11, -1 - c.addi4spn a2, sp, 528 - c.nop - divu tp, s5, t4 - sll s8, s0, s6 - srl t1, tp, zero - mulhsu tp, t5, a6 - rem a2, s2, s9 - slli a2, a4, 25 - c.addi16sp sp, -16 - sub s0, t3, gp - sltiu s3, tp, 300 - c.nop - srl t1, tp, zero - c.andi s1, 31 - c.add t3, t1 - sltu s3, a6, a4 - remu s6, s3, t1 - slt a0, s5, s11 - and s6, t2, a4 - c.srli a4, 9 - sltu s3, a6, a4 - auipc s1, 11691 - and s6, t2, a4 - rem a2, s2, s9 - slt a0, s5, s11 - rem a2, s2, s9 - srli zero, a0, 13 - mul tp, s2, t5 - or a4, a4, zero - c.xor a4, a5 - div s7, gp, a4 - c.sub s0, s1 - c.slli t5, 22 - slli a2, a4, 25 - srl t1, tp, zero - mulhu s4, a6, t3 - c.srli a4, 9 - divu tp, s5, t4 - c.xor a4, a5 - srai a4, a3, 0 - slt a0, s5, s11 - c.addi16sp sp, -16 - c.li s11, -1 - xori t3, t1, -721 - c.addi4spn a2, sp, 528 - c.lui a6, 24 - c.srli a4, 9 - sltiu s3, tp, 300 - c.addi s9, -1 - xor s11, zero, s7 - c.and a4, s1 - slt a0, s5, s11 - xori t3, t1, -721 - c.xor a4, a5 - slti tp, a1, -167 - remu s6, s3, t1 - c.and a4, s1 - remu s6, s3, t1 - add s4, a7, s6 - c.lui a6, 24 - c.or a0, a2 - xor s11, zero, s7 - slti tp, a1, -167 - sub s0, t3, gp - c.addi4spn a2, sp, 528 - c.addi s9, -1 - c.mv a2, a0 - xor s11, zero, s7 - remu s6, s3, t1 - srli zero, a0, 13 - remu s6, s3, t1 - div s7, gp, a4 - c.add t3, t1 - c.mv a2, a0 - c.addi16sp sp, -16 - c.srli a4, 9 - lui s3, 985951 - mulhu s4, a6, t3 - c.srli a4, 9 - c.slli t5, 22 - sltu s3, a6, a4 - sub s0, t3, gp - sub s0, t3, gp - slti tp, a1, -167 - c.li s11, -1 - sltiu s3, tp, 300 - and s6, t2, a4 - slli a2, a4, 25 - slt a0, s5, s11 - slti tp, a1, -167 - sra s9, s4, t5 - c.add t3, t1 - c.slli t5, 22 - srai a4, a3, 0 - add s4, a7, s6 - ori tp, a0, -848 - c.sub s0, s1 - sltu s3, a6, a4 - addi gp, s8, -298 - remu s6, s3, t1 - add s4, a7, s6 - c.mv a2, a0 - srl t1, tp, zero - c.or a0, a2 - c.slli t5, 22 - sll s8, s0, s6 - c.or a0, a2 - and s6, t2, a4 - slti tp, a1, -167 - c.add t3, t1 - nop - c.mv a2, a0 - sll s8, s0, s6 - rem a2, s2, s9 - c.or a0, a2 - lui s3, 985951 - sll s8, s0, s6 - sltu s3, a6, a4 - xori t3, t1, -721 - c.or a0, a2 - andi t0, a3, 147 - addi gp, s8, -298 - sltu s3, a6, a4 - c.addi16sp sp, -16 - c.andi s1, 31 - or a4, a4, zero - c.srai s1, 28 - c.mv a2, a0 - sltu s3, a6, a4 - sltu s3, a6, a4 - divu tp, s5, t4 - divu tp, s5, t4 - c.or a0, a2 - c.andi s1, 31 - mulh s1, t4, s11 - c.nop - slti tp, a1, -167 - slt a0, s5, s11 - c.or a0, a2 - div s7, gp, a4 - c.addi16sp sp, -16 - c.srli a4, 9 - c.xor a4, a5 - c.lui a6, 24 - nop - xori t3, t1, -721 - sub s0, t3, gp - c.li s11, -1 - slli a2, a4, 25 - c.or a0, a2 - mul tp, s2, t5 - nop - auipc s1, 11691 - xori t3, t1, -721 - srli zero, a0, 13 - c.srai s1, 28 - srl t1, tp, zero - auipc s1, 11691 - lui s3, 985951 - slt a0, s5, s11 - c.add t3, t1 - and s6, t2, a4 - auipc s1, 11691 - add s4, a7, s6 - c.andi s1, 31 - remu s6, s3, t1 - slli a2, a4, 25 - c.slli t5, 22 - c.li s11, -1 - slli a2, a4, 25 - mulh s1, t4, s11 - srli zero, a0, 13 - srl t1, tp, zero - mul tp, s2, t5 - slt a0, s5, s11 - sltiu s3, tp, 300 - xori t3, t1, -721 - and s6, t2, a4 - c.lui a6, 24 - add s4, a7, s6 - c.addi4spn a2, sp, 528 - slt a0, s5, s11 - c.xor a4, a5 - mul tp, s2, t5 - c.addi16sp sp, -16 - nop - andi t0, a3, 147 - xor s11, zero, s7 - lui s3, 985951 - lui s3, 985951 - andi t0, a3, 147 - mulhu s4, a6, t3 - c.srli a4, 9 - c.srai s1, 28 - sltu s3, a6, a4 - or a4, a4, zero - mulh s1, t4, s11 - c.mv a2, a0 - c.andi s1, 31 - mulh s1, t4, s11 - remu s6, s3, t1 - rem a2, s2, s9 - c.add t3, t1 - sltu s3, a6, a4 - c.srai s1, 28 - c.andi s1, 31 - c.and a4, s1 - and s6, t2, a4 - xor s11, zero, s7 - c.addi4spn a2, sp, 528 - addi gp, s8, -298 - c.srli a4, 9 - c.nop - lui s3, 985951 - andi t0, a3, 147 - c.slli t5, 22 - addi gp, s8, -298 - auipc s1, 11691 - c.li s11, -1 - slli a2, a4, 25 - andi t0, a3, 147 - auipc s1, 11691 - mulhsu tp, t5, a6 - srli zero, a0, 13 - c.li s11, -1 - sra s9, s4, t5 - c.lui a6, 24 - c.addi16sp sp, -16 - c.mv a2, a0 - div s7, gp, a4 - srli zero, a0, 13 - rem a2, s2, s9 - c.mv a2, a0 - and s6, t2, a4 - c.li s11, -1 - divu tp, s5, t4 - c.slli t5, 22 - c.addi4spn a2, sp, 528 - slti tp, a1, -167 - c.xor a4, a5 - sltu s3, a6, a4 - c.lui a6, 24 - c.lui a6, 24 - sll s8, s0, s6 - addi gp, s8, -298 - sltiu s3, tp, 300 - add s4, a7, s6 - slli a2, a4, 25 - lui s3, 985951 - ori tp, a0, -848 - remu s6, s3, t1 - and s6, t2, a4 - c.add t3, t1 - and s6, t2, a4 - c.andi s1, 31 - div s7, gp, a4 - c.addi16sp sp, -16 - auipc s1, 11691 - slli a2, a4, 25 - srai a4, a3, 0 - c.srai s1, 28 - xori t3, t1, -721 - mulhsu tp, t5, a6 - auipc s1, 11691 - c.and a4, s1 - c.li s11, -1 - div s7, gp, a4 - sra s9, s4, t5 - c.nop - c.or a0, a2 - c.xor a4, a5 - xor s11, zero, s7 - slt a0, s5, s11 - addi gp, s8, -298 - mulhu s4, a6, t3 - sub s0, t3, gp - mulhu s4, a6, t3 - ori tp, a0, -848 - mulhu s4, a6, t3 - c.slli t5, 22 - srai a4, a3, 0 - sltu s3, a6, a4 - c.addi16sp sp, -16 - xor s11, zero, s7 - sll s8, s0, s6 - divu tp, s5, t4 - c.xor a4, a5 - slti tp, a1, -167 - sltiu s3, tp, 300 - c.sub s0, s1 - addi gp, s8, -298 - c.add t3, t1 - slli a2, a4, 25 - srai a4, a3, 0 - c.lui a6, 24 - nop - c.addi16sp sp, -16 - sra s9, s4, t5 - c.andi s1, 31 - or a4, a4, zero - xori t3, t1, -721 - lui s3, 985951 - c.addi4spn a2, sp, 528 - sra s9, s4, t5 - divu tp, s5, t4 - sra s9, s4, t5 - sra s9, s4, t5 - sub s0, t3, gp - ori tp, a0, -848 - mulhsu tp, t5, a6 - c.li s11, -1 - c.xor a4, a5 - srli zero, a0, 13 - sltu s3, a6, a4 - c.sub s0, s1 - li s1, 0xfb847450 #start riscv_int_numeric_corner_stream_27 - li tp, 0x80000000 - li t0, 0xffffffff - li a2, 0x0 - li ra, 0xa187a44a - li t1, 0x80000000 - li gp, 0xffffffff - li a0, 0xffffffff - li sp, 0x0 - li s11, 0xffffffff - nop - divu t0, a0, s11 - nop - lui t1, 985951 - add t1, tp, a2 - rem tp, sp, t1 - divu t0, a0, s11 - mulh a2, tp, tp - mulh a2, tp, tp - mulhu ra, ra, t1 - nop - rem tp, sp, t1 - lui t1, 985951 - addi tp, s11, -40 - remu a2, s11, a0 - mulhu ra, ra, t1 - nop - mulhsu t0, t0, ra - nop - lui t1, 985951 - auipc s1, 11691 - rem tp, sp, t1 - add t1, tp, a2 - nop - mulhsu t0, t0, ra - divu t0, a0, s11 - nop #end riscv_int_numeric_corner_stream_27 - c.or a0, a2 - or a4, a4, zero - slli a2, a4, 25 - c.sub s0, s1 - c.andi s1, 31 - c.li s11, -1 - remu s6, s3, t1 - div s7, gp, a4 - c.add t3, t1 - srli zero, a0, 13 - xor s11, zero, s7 - divu tp, s5, t4 - or a4, a4, zero - add s4, a7, s6 - c.nop - auipc s1, 11691 - c.andi s1, 31 - addi gp, s8, -298 - c.addi s9, -1 - c.xor a4, a5 - sub s0, t3, gp - or a4, a4, zero - c.add t3, t1 - slt a0, s5, s11 - c.addi16sp sp, -16 - remu s6, s3, t1 - add s4, a7, s6 - addi gp, s8, -298 - mulhu s4, a6, t3 - c.add t3, t1 - c.addi s9, -1 - c.lui a6, 24 - slt a0, s5, s11 - c.srai s1, 28 - c.xor a4, a5 - c.xor a4, a5 - srl t1, tp, zero - addi gp, s8, -298 - sltu s3, a6, a4 - ori tp, a0, -848 - ori tp, a0, -848 - c.xor a4, a5 - c.li s11, -1 - andi t0, a3, 147 - xori t3, t1, -721 - slt a0, s5, s11 - sub s0, t3, gp - auipc s1, 11691 - c.sub s0, s1 - sra s9, s4, t5 - sltiu s3, tp, 300 - mul tp, s2, t5 - xori t3, t1, -721 - or a4, a4, zero - c.srai s1, 28 - mul tp, s2, t5 - or a4, a4, zero - c.srli a4, 9 - srl t1, tp, zero - div s7, gp, a4 - andi t0, a3, 147 - c.mv a2, a0 - addi gp, s8, -298 - divu tp, s5, t4 - nop - c.li s11, -1 - ori tp, a0, -848 - div s7, gp, a4 - c.andi s1, 31 - c.mv a2, a0 - andi t0, a3, 147 - sll s8, s0, s6 - c.xor a4, a5 - mulhsu tp, t5, a6 - mul tp, s2, t5 - sra s9, s4, t5 - srli zero, a0, 13 - rem a2, s2, s9 - c.mv a2, a0 - and s6, t2, a4 - mulhsu tp, t5, a6 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - mulh s1, t4, s11 - c.nop - c.mv a2, a0 - div s7, gp, a4 - xori t3, t1, -721 - or a4, a4, zero - sll s8, s0, s6 - addi gp, s8, -298 - sltiu s3, tp, 300 - sra s9, s4, t5 - slli a2, a4, 25 - slti tp, a1, -167 - div s7, gp, a4 - xori t3, t1, -721 - c.addi s9, -1 - slti tp, a1, -167 - mulhsu tp, t5, a6 - sra s9, s4, t5 - nop - ori tp, a0, -848 - slt a0, s5, s11 - c.nop - xor s11, zero, s7 - c.nop - c.andi s1, 31 - srl t1, tp, zero - mulh s1, t4, s11 - slti tp, a1, -167 - sra s9, s4, t5 - slti tp, a1, -167 - div s7, gp, a4 - c.lui a6, 24 - nop - c.nop - mul tp, s2, t5 - c.and a4, s1 - c.li s11, -1 - slli a2, a4, 25 - c.li s11, -1 - mul tp, s2, t5 - c.sub s0, s1 - c.srli a4, 9 - srai a4, a3, 0 - div s7, gp, a4 - slti tp, a1, -167 - c.and a4, s1 - c.nop - c.or a0, a2 - c.lui a6, 24 - slt a0, s5, s11 - c.addi s9, -1 - c.and a4, s1 - slti tp, a1, -167 - sll s8, s0, s6 - ori tp, a0, -848 - add s4, a7, s6 - c.andi s1, 31 - srli zero, a0, 13 - divu tp, s5, t4 - c.andi s1, 31 - mul tp, s2, t5 - c.srai s1, 28 - srl t1, tp, zero - c.sub s0, s1 - slti tp, a1, -167 - c.slli t5, 22 - srai a4, a3, 0 - c.slli t5, 22 - nop - slt a0, s5, s11 - lui s3, 985951 - mul tp, s2, t5 - mulhsu tp, t5, a6 - mulh s1, t4, s11 - sltu s3, a6, a4 - sub s0, t3, gp - sra s9, s4, t5 - c.or a0, a2 - add s4, a7, s6 - sra s9, s4, t5 - auipc s1, 11691 - c.add t3, t1 - c.srli a4, 9 - mulhu s4, a6, t3 - xori t3, t1, -721 - c.and a4, s1 - c.srai s1, 28 - xori t3, t1, -721 - addi gp, s8, -298 - c.mv a2, a0 - ori tp, a0, -848 - c.addi16sp sp, -16 - c.andi s1, 31 - mulhsu tp, t5, a6 - c.nop - sltiu s3, tp, 300 - auipc s1, 11691 - c.add t3, t1 - srl t1, tp, zero - remu s6, s3, t1 - c.srli a4, 9 - c.nop - rem a2, s2, s9 - c.slli t5, 22 - add s4, a7, s6 - sll s8, s0, s6 - c.andi s1, 31 - srai a4, a3, 0 - ori tp, a0, -848 - srli zero, a0, 13 - lui s3, 985951 - mulhu s4, a6, t3 - mulh s1, t4, s11 - li a4, 0xffffffff #start riscv_int_numeric_corner_stream_24 - li t3, 0x8f5c3da4 - li a6, 0xffffffff - li a3, 0x71372280 - li s8, 0xbcdedf11 - li t5, 0xffffffff - li a2, 0xffffffff - li t0, 0xffffffff - li s11, 0x80000000 - li ra, 0xffffffff - mulhu ra, a3, t5 - lui s11, 985951 - addi t0, s11, -40 - divu s11, t5, s8 - mulhu ra, a3, t5 - nop - remu t5, a4, a4 - add t3, a2, t5 - addi t0, s11, -40 - nop - divu s11, t5, s8 - div s8, a2, ra - nop - mulhsu t0, a2, ra - sub a6, t5, s8 - mulh s8, s11, a2 - mulhu ra, a3, t5 - lui s11, 985951 - addi t0, s11, -40 - nop - lui s11, 985951 - div s8, a2, ra - addi t0, s11, -40 - sub a6, t5, s8 - addi t0, s11, -40 - div s8, a2, ra - mulhsu t0, a2, ra #end riscv_int_numeric_corner_stream_24 - slti tp, a1, -167 - slti tp, a1, -167 - add s4, a7, s6 - xor s11, zero, s7 - c.lui a6, 24 - div s7, gp, a4 - c.and a4, s1 - mulhu s4, a6, t3 - xori t3, t1, -721 - c.slli t5, 22 - c.add t3, t1 - c.mv a2, a0 - ori tp, a0, -848 - slt a0, s5, s11 - c.or a0, a2 - c.and a4, s1 - srai a4, a3, 0 - auipc s1, 11691 - rem a2, s2, s9 - or a4, a4, zero - c.slli t5, 22 - c.add t3, t1 - div s7, gp, a4 - c.or a0, a2 - mulhu s4, a6, t3 - divu tp, s5, t4 - slli a2, a4, 25 - c.xor a4, a5 - div s7, gp, a4 - andi t0, a3, 147 - div s7, gp, a4 - xor s11, zero, s7 - slli a2, a4, 25 - sltu s3, a6, a4 - c.andi s1, 31 - ori tp, a0, -848 - xori t3, t1, -721 - add s4, a7, s6 - c.or a0, a2 - c.li s11, -1 - or a4, a4, zero - c.andi s1, 31 - mul tp, s2, t5 - mulh s1, t4, s11 - sub s0, t3, gp - xori t3, t1, -721 - andi t0, a3, 147 - c.addi s9, -1 - nop - c.srli a4, 9 - c.or a0, a2 - lui s3, 985951 - xori t3, t1, -721 - divu tp, s5, t4 - c.or a0, a2 - mulhu s4, a6, t3 - xor s11, zero, s7 - c.srli a4, 9 - c.or a0, a2 - mulh s1, t4, s11 - ori tp, a0, -848 - srl t1, tp, zero - nop - c.slli t5, 22 - add s4, a7, s6 - c.srai s1, 28 - add s4, a7, s6 - c.srli a4, 9 - nop - srl t1, tp, zero - sra s9, s4, t5 - c.srai s1, 28 - c.xor a4, a5 - c.add t3, t1 - c.add t3, t1 - srai a4, a3, 0 - ori tp, a0, -848 - nop - mulh s1, t4, s11 - c.li s11, -1 - remu s6, s3, t1 - addi gp, s8, -298 - sltiu s3, tp, 300 - andi t0, a3, 147 - sub s0, t3, gp - mul tp, s2, t5 - mulhsu tp, t5, a6 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - sra s9, s4, t5 - mul tp, s2, t5 - c.addi16sp sp, -16 - sub s0, t3, gp - divu tp, s5, t4 - slt a0, s5, s11 - c.or a0, a2 - and s6, t2, a4 - c.or a0, a2 - mulh s1, t4, s11 - or a4, a4, zero - ori tp, a0, -848 - c.nop - sll s8, s0, s6 - rem a2, s2, s9 - nop - sltiu s3, tp, 300 - c.andi s1, 31 - nop - slt a0, s5, s11 - slt a0, s5, s11 - c.mv a2, a0 - c.and a4, s1 - srai a4, a3, 0 - sltu s3, a6, a4 - c.andi s1, 31 - xor s11, zero, s7 - divu tp, s5, t4 - c.sub s0, s1 - or a4, a4, zero - nop - c.addi16sp sp, -16 - c.add t3, t1 - srai a4, a3, 0 - c.lui a6, 24 - or a4, a4, zero - c.slli t5, 22 - c.slli t5, 22 - div s7, gp, a4 - mulh s1, t4, s11 - srl t1, tp, zero - or a4, a4, zero - c.or a0, a2 - and s6, t2, a4 - c.li s11, -1 - sltiu s3, tp, 300 - mulhu s4, a6, t3 - c.lui a6, 24 - srl t1, tp, zero - lui s3, 985951 - c.mv a2, a0 - ori tp, a0, -848 - sltiu s3, tp, 300 - remu s6, s3, t1 - addi gp, s8, -298 - c.lui a6, 24 - c.and a4, s1 - and s6, t2, a4 - mulh s1, t4, s11 - sub s0, t3, gp - c.or a0, a2 - addi gp, s8, -298 - c.li s11, -1 - or a4, a4, zero - mul tp, s2, t5 - sltiu s3, tp, 300 - srai a4, a3, 0 - c.addi4spn a2, sp, 528 - auipc s1, 11691 - add s4, a7, s6 - remu s6, s3, t1 - sll s8, s0, s6 - slt a0, s5, s11 - rem a2, s2, s9 - addi gp, s8, -298 - sll s8, s0, s6 - xori t3, t1, -721 - xor s11, zero, s7 - srli zero, a0, 13 - div s7, gp, a4 - slli a2, a4, 25 - c.add t3, t1 - c.addi16sp sp, -16 - c.slli t5, 22 - nop - c.addi4spn a2, sp, 528 - sll s8, s0, s6 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - addi gp, s8, -298 - auipc s1, 11691 - lui s3, 985951 - sra s9, s4, t5 - c.addi4spn a2, sp, 528 - c.mv a2, a0 - remu s6, s3, t1 - and s6, t2, a4 - sltu s3, a6, a4 - slti tp, a1, -167 - mul tp, s2, t5 - sltiu s3, tp, 300 - xor s11, zero, s7 - srl t1, tp, zero - mulh s1, t4, s11 - or a4, a4, zero - rem a2, s2, s9 - c.nop - slli a2, a4, 25 - xori t3, t1, -721 - add s4, a7, s6 - srl t1, tp, zero - addi gp, s8, -298 - slt a0, s5, s11 - c.lui a6, 24 - and s6, t2, a4 - andi t0, a3, 147 - slti tp, a1, -167 - c.addi16sp sp, -16 - c.srli a4, 9 - add s4, a7, s6 - c.addi4spn a2, sp, 528 - c.or a0, a2 - sra s9, s4, t5 - c.li s11, -1 - div s7, gp, a4 - c.li s11, -1 - and s6, t2, a4 - srli zero, a0, 13 - or a4, a4, zero - srl t1, tp, zero - c.mv a2, a0 - c.mv a2, a0 - lui s3, 985951 - c.andi s1, 31 - and s6, t2, a4 - andi t0, a3, 147 - mulhu s4, a6, t3 - mulh s1, t4, s11 - mulhu s4, a6, t3 - or a4, a4, zero - addi gp, s8, -298 - or a4, a4, zero - divu tp, s5, t4 - andi t0, a3, 147 - sll s8, s0, s6 - c.and a4, s1 - sltu s3, a6, a4 - c.addi s9, -1 - divu tp, s5, t4 - xori t3, t1, -721 - auipc s1, 11691 - sub s0, t3, gp - slti tp, a1, -167 - c.andi s1, 31 - ori tp, a0, -848 - and s6, t2, a4 - xori t3, t1, -721 - slli a2, a4, 25 - addi gp, s8, -298 - mulh s1, t4, s11 - andi t0, a3, 147 - add s4, a7, s6 - c.or a0, a2 - rem a2, s2, s9 - slti tp, a1, -167 - auipc s1, 11691 - andi t0, a3, 147 - srli zero, a0, 13 - mulhu s4, a6, t3 - sra s9, s4, t5 - c.addi16sp sp, -16 - sub s0, t3, gp - c.or a0, a2 - c.mv a2, a0 - c.srai s1, 28 - sub s0, t3, gp - xor s11, zero, s7 - nop - c.srli a4, 9 - or a4, a4, zero - andi t0, a3, 147 - or a4, a4, zero - c.or a0, a2 - slli a2, a4, 25 - slti tp, a1, -167 - c.xor a4, a5 - c.srli a4, 9 - xor s11, zero, s7 - sll s8, s0, s6 - c.lui a6, 24 - slt a0, s5, s11 - mulhu s4, a6, t3 - sra s9, s4, t5 - mulhu s4, a6, t3 - c.add t3, t1 - li s6, 0x80000000 #start riscv_int_numeric_corner_stream_33 - li a3, 0x3f59d3a4 - li tp, 0x92610f89 - li a2, 0x0 - li gp, 0xffffffff - li s4, 0xffffffff - li t0, 0xffffffff - li t2, 0xaade8403 - li a6, 0xbb5b45cc - li s5, 0xffffffff - sub a2, a6, s5 - nop - nop - mulhsu s6, t2, gp - add s5, s6, s6 - add s5, s6, s6 - rem a6, a6, t2 - nop - sub a2, a6, s5 - mulh s5, a2, tp - add s5, s6, s6 - lui gp, 985951 - divu tp, gp, a6 - add s5, s6, s6 - nop - remu a6, t2, a2 #end riscv_int_numeric_corner_stream_33 - slli a2, a4, 25 - sll s8, s0, s6 - slt a0, s5, s11 - slli a2, a4, 25 - or a4, a4, zero - c.srai s1, 28 - c.mv a2, a0 - sltu s3, a6, a4 - slli a2, a4, 25 - div s7, gp, a4 - addi gp, s8, -298 - mul tp, s2, t5 - slt a0, s5, s11 - rem a2, s2, s9 - c.li s11, -1 - c.addi16sp sp, -16 - divu tp, s5, t4 - c.addi4spn a2, sp, 528 - c.addi16sp sp, -16 - c.addi16sp sp, -16 - c.slli t5, 22 - srai a4, a3, 0 - c.mv a2, a0 - mulhu s4, a6, t3 - c.nop - slti tp, a1, -167 - mul tp, s2, t5 - xor s11, zero, s7 - slt a0, s5, s11 - xor s11, zero, s7 - ori tp, a0, -848 - c.addi s9, -1 - divu tp, s5, t4 - mulhu s4, a6, t3 - addi gp, s8, -298 - sll s8, s0, s6 - divu tp, s5, t4 - divu tp, s5, t4 - c.add t3, t1 - andi t0, a3, 147 - mul tp, s2, t5 - addi gp, s8, -298 - c.nop - c.sub s0, s1 - mulhsu tp, t5, a6 - mulh s1, t4, s11 - mulhu s4, a6, t3 - nop - mulhsu tp, t5, a6 - ori tp, a0, -848 - and s6, t2, a4 - mul tp, s2, t5 - c.sub s0, s1 - slt a0, s5, s11 - xor s11, zero, s7 - lui s3, 985951 - slli a2, a4, 25 - mulhu s4, a6, t3 - sltiu s3, tp, 300 - c.addi16sp sp, -16 - xor s11, zero, s7 - mulhu s4, a6, t3 - c.add t3, t1 - c.slli t5, 22 - remu s6, s3, t1 - mulhu s4, a6, t3 - xori t3, t1, -721 - c.addi s9, -1 - srai a4, a3, 0 - div s7, gp, a4 - c.nop - sub s0, t3, gp - add s4, a7, s6 - rem a2, s2, s9 - slti tp, a1, -167 - lui s3, 985951 - c.srli a4, 9 - c.li s11, -1 - sll s8, s0, s6 - slt a0, s5, s11 - xor s11, zero, s7 - nop - srli zero, a0, 13 - c.srli a4, 9 - div s7, gp, a4 - sltu s3, a6, a4 - mul tp, s2, t5 - srli zero, a0, 13 - add s4, a7, s6 - div s7, gp, a4 - c.or a0, a2 - mulh s1, t4, s11 - c.xor a4, a5 - c.addi s9, -1 - slti tp, a1, -167 - srl t1, tp, zero - slt a0, s5, s11 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - mul tp, s2, t5 - c.addi s9, -1 - srli zero, a0, 13 - srl t1, tp, zero - sll s8, s0, s6 - sltiu s3, tp, 300 - c.sub s0, s1 - c.addi4spn a2, sp, 528 - or a4, a4, zero - c.nop - mulhu s4, a6, t3 - c.andi s1, 31 - nop - div s7, gp, a4 - c.sub s0, s1 - auipc s1, 11691 - slli a2, a4, 25 - mulh s1, t4, s11 - divu tp, s5, t4 - c.li s11, -1 - srl t1, tp, zero - c.li s11, -1 - c.lui a6, 24 - sltiu s3, tp, 300 - c.srai s1, 28 - slti tp, a1, -167 - ori tp, a0, -848 - c.nop - srl t1, tp, zero - c.srai s1, 28 - div s7, gp, a4 - mulh s1, t4, s11 - mulh s1, t4, s11 - div s7, gp, a4 - sll s8, s0, s6 - c.nop - c.srai s1, 28 - mulhsu tp, t5, a6 - c.add t3, t1 - mulh s1, t4, s11 - remu s6, s3, t1 - xor s11, zero, s7 - add s4, a7, s6 - c.mv a2, a0 - sra s9, s4, t5 - c.addi s9, -1 - divu tp, s5, t4 - and s6, t2, a4 - add s4, a7, s6 - sub s0, t3, gp - sltu s3, a6, a4 - nop - mulh s1, t4, s11 - xor s11, zero, s7 - c.addi16sp sp, -16 - lui s3, 985951 - c.slli t5, 22 - c.li s11, -1 - sra s9, s4, t5 - c.addi16sp sp, -16 - c.lui a6, 24 - divu tp, s5, t4 - xor s11, zero, s7 - div s7, gp, a4 - lui s3, 985951 - sra s9, s4, t5 - slli a2, a4, 25 - sra s9, s4, t5 - add s4, a7, s6 - sltu s3, a6, a4 - remu s6, s3, t1 - c.lui a6, 24 - sll s8, s0, s6 - srl t1, tp, zero - addi gp, s8, -298 - addi gp, s8, -298 - c.sub s0, s1 - nop - mulhsu tp, t5, a6 - c.xor a4, a5 - c.li s11, -1 - rem a2, s2, s9 - c.li s11, -1 - xor s11, zero, s7 - c.addi4spn a2, sp, 528 - add s4, a7, s6 - c.add t3, t1 - slti tp, a1, -167 - andi t0, a3, 147 - remu s6, s3, t1 - c.srai s1, 28 - sll s8, s0, s6 - c.srli a4, 9 - c.srai s1, 28 - c.lui a6, 24 - srl t1, tp, zero - sll s8, s0, s6 - c.and a4, s1 - sll s8, s0, s6 - c.andi s1, 31 - rem a2, s2, s9 - slli a2, a4, 25 - c.or a0, a2 - c.add t3, t1 - rem a2, s2, s9 - slli a2, a4, 25 - c.srai s1, 28 - or a4, a4, zero - and s6, t2, a4 - c.lui a6, 24 - sltu s3, a6, a4 - c.nop - srl t1, tp, zero - c.or a0, a2 - addi gp, s8, -298 - add s4, a7, s6 - div s7, gp, a4 - c.li s11, -1 - andi t0, a3, 147 - sra s9, s4, t5 - slt a0, s5, s11 - sub s0, t3, gp - c.srli a4, 9 - mulhu s4, a6, t3 - c.li s11, -1 - mul tp, s2, t5 - sra s9, s4, t5 - sub s0, t3, gp - mul tp, s2, t5 - c.addi s9, -1 - remu s6, s3, t1 - c.addi16sp sp, -16 - lui s3, 985951 - div s7, gp, a4 - c.andi s1, 31 - c.lui a6, 24 - lui s3, 985951 - slt a0, s5, s11 - rem a2, s2, s9 - mulh s1, t4, s11 - sra s9, s4, t5 - mulh s1, t4, s11 - xor s11, zero, s7 - mulh s1, t4, s11 - add s4, a7, s6 - slli a2, a4, 25 - c.addi s9, -1 - c.srli a4, 9 - c.srai s1, 28 - mul tp, s2, t5 - c.xor a4, a5 - or a4, a4, zero - rem a2, s2, s9 - slti tp, a1, -167 - ori tp, a0, -848 - sltu s3, a6, a4 - c.addi s9, -1 - div s7, gp, a4 - srl t1, tp, zero - c.nop - and s6, t2, a4 - c.addi4spn a2, sp, 528 - sub s0, t3, gp - slt a0, s5, s11 - srai a4, a3, 0 - sra s9, s4, t5 - c.lui a6, 24 - c.add t3, t1 - sub s0, t3, gp - c.srli a4, 9 - mul tp, s2, t5 - slt a0, s5, s11 - mul tp, s2, t5 - div s7, gp, a4 - c.sub s0, s1 - c.add t3, t1 - remu s6, s3, t1 - nop - srai a4, a3, 0 - c.add t3, t1 - c.addi16sp sp, -16 - c.sub s0, s1 - srl t1, tp, zero - mulhsu tp, t5, a6 - lui s3, 985951 - add s4, a7, s6 - c.addi4spn a2, sp, 528 - add s4, a7, s6 - sltiu s3, tp, 300 - xori t3, t1, -721 - sltiu s3, tp, 300 - divu tp, s5, t4 - and s6, t2, a4 - c.li s11, -1 - mul tp, s2, t5 - c.xor a4, a5 - sltu s3, a6, a4 - addi gp, s8, -298 - c.or a0, a2 - c.addi s9, -1 - mul tp, s2, t5 - slti tp, a1, -167 - xori t3, t1, -721 - ori tp, a0, -848 - c.sub s0, s1 - srai a4, a3, 0 - ori tp, a0, -848 - ori tp, a0, -848 - c.sub s0, s1 - lui s3, 985951 - c.li s11, -1 - c.mv a2, a0 - c.addi4spn a2, sp, 528 - or a4, a4, zero - nop - div s7, gp, a4 - mulhsu tp, t5, a6 - xor s11, zero, s7 - rem a2, s2, s9 - c.and a4, s1 - c.andi s1, 31 - c.addi s9, -1 - sra s9, s4, t5 - c.mv a2, a0 - xor s11, zero, s7 - c.slli t5, 22 - srai a4, a3, 0 - c.srai s1, 28 - div s7, gp, a4 - c.srli a4, 9 - rem a2, s2, s9 - c.mv a2, a0 - c.srli a4, 9 - c.nop - c.lui a6, 24 - mulhsu tp, t5, a6 - lui s3, 985951 - c.nop - mulhu s4, a6, t3 - ori tp, a0, -848 - auipc s1, 11691 - mulhu s4, a6, t3 - add s4, a7, s6 - c.andi s1, 31 - c.addi4spn a2, sp, 528 - c.addi4spn a2, sp, 528 - c.andi s1, 31 - srli zero, a0, 13 - sll s8, s0, s6 - slti tp, a1, -167 - sltu s3, a6, a4 - c.add t3, t1 - xori t3, t1, -721 - add s4, a7, s6 - c.addi16sp sp, -16 - xori t3, t1, -721 - c.lui a6, 24 - nop - rem a2, s2, s9 - sltu s3, a6, a4 - rem a2, s2, s9 - rem a2, s2, s9 - c.slli t5, 22 - c.mv a2, a0 - c.mv a2, a0 - slt a0, s5, s11 - slti tp, a1, -167 - srli zero, a0, 13 - lui s3, 985951 - auipc s1, 11691 - divu tp, s5, t4 - srli zero, a0, 13 - mul tp, s2, t5 - c.srli a4, 9 - andi t0, a3, 147 - c.slli t5, 22 - srl t1, tp, zero - mulhu s4, a6, t3 - slt a0, s5, s11 - andi t0, a3, 147 - c.or a0, a2 - c.addi16sp sp, -16 - add s4, a7, s6 - nop - divu tp, s5, t4 - addi gp, s8, -298 - nop - srli zero, a0, 13 - srai a4, a3, 0 - nop - c.nop - c.srli a4, 9 - mulh s1, t4, s11 - xori t3, t1, -721 - sll s8, s0, s6 - c.and a4, s1 - nop - c.xor a4, a5 - c.xor a4, a5 - lui s3, 985951 - sltu s3, a6, a4 - and s6, t2, a4 - add s4, a7, s6 - and s6, t2, a4 - c.sub s0, s1 - mul tp, s2, t5 - srai a4, a3, 0 - slt a0, s5, s11 - c.andi s1, 31 - c.add t3, t1 - slt a0, s5, s11 - divu tp, s5, t4 - c.xor a4, a5 - c.mv a2, a0 - div s7, gp, a4 - c.xor a4, a5 - c.add t3, t1 - slt a0, s5, s11 - c.andi s1, 31 - div s7, gp, a4 - div s7, gp, a4 - xor s11, zero, s7 - c.srai s1, 28 - nop - addi gp, s8, -298 - sra s9, s4, t5 - c.addi s9, -1 - addi gp, s8, -298 - c.xor a4, a5 - c.add t3, t1 - sltiu s3, tp, 300 - srl t1, tp, zero - ori tp, a0, -848 - c.srli a4, 9 - slli a2, a4, 25 - sll s8, s0, s6 - add s4, a7, s6 - c.addi16sp sp, -16 - srli zero, a0, 13 - srai a4, a3, 0 - add s4, a7, s6 - srl t1, tp, zero - andi t0, a3, 147 - c.srli a4, 9 - c.nop - sltiu s3, tp, 300 - c.srli a4, 9 - slli a2, a4, 25 - lui s3, 985951 - xor s11, zero, s7 - mulh s1, t4, s11 - divu tp, s5, t4 - mul tp, s2, t5 - c.andi s1, 31 - srli zero, a0, 13 - c.nop - xor s11, zero, s7 - rem a2, s2, s9 - c.addi s9, -1 - c.add t3, t1 - srli zero, a0, 13 - nop - xori t3, t1, -721 - c.xor a4, a5 - c.slli t5, 22 - c.andi s1, 31 - slli a2, a4, 25 - srl t1, tp, zero - sltiu s3, tp, 300 - slti tp, a1, -167 - mulhsu tp, t5, a6 - c.slli t5, 22 - or a4, a4, zero - slti tp, a1, -167 - srai a4, a3, 0 - add s4, a7, s6 - c.addi16sp sp, -16 - slti tp, a1, -167 - c.lui a6, 24 - mulhsu tp, t5, a6 - c.xor a4, a5 - slt a0, s5, s11 - auipc s1, 11691 - nop - ori tp, a0, -848 - sub s0, t3, gp - and s6, t2, a4 - xori t3, t1, -721 - slli a2, a4, 25 - c.lui a6, 24 - srli zero, a0, 13 - srl t1, tp, zero - c.addi s9, -1 - sltu s3, a6, a4 - div s7, gp, a4 - c.sub s0, s1 - slli a2, a4, 25 - srai a4, a3, 0 - or a4, a4, zero - c.li s11, -1 - mulhu s4, a6, t3 - srl t1, tp, zero - lui s3, 985951 - divu tp, s5, t4 - auipc s1, 11691 - c.nop - add s4, a7, s6 - srli zero, a0, 13 - div s7, gp, a4 - c.slli t5, 22 - srli zero, a0, 13 - mulhu s4, a6, t3 - c.srli a4, 9 - c.sub s0, s1 - andi t0, a3, 147 - divu tp, s5, t4 - mul tp, s2, t5 - mul tp, s2, t5 - slti tp, a1, -167 - srli zero, a0, 13 - sra s9, s4, t5 - c.mv a2, a0 - c.sub s0, s1 - sub s0, t3, gp - xor s11, zero, s7 - or a4, a4, zero - auipc s1, 11691 - c.srli a4, 9 - divu tp, s5, t4 - c.sub s0, s1 - rem a2, s2, s9 - slli a2, a4, 25 - c.sub s0, s1 - c.addi s9, -1 - nop - sltiu s3, tp, 300 - c.xor a4, a5 - c.andi s1, 31 - rem a2, s2, s9 - c.lui a6, 24 - and s6, t2, a4 - slli a2, a4, 25 - c.lui a6, 24 - add s4, a7, s6 - c.slli t5, 22 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - sll s8, s0, s6 - srai a4, a3, 0 - srl t1, tp, zero - c.mv a2, a0 - srai a4, a3, 0 - c.add t3, t1 - c.mv a2, a0 - srai a4, a3, 0 - c.mv a2, a0 - ori tp, a0, -848 - sll s8, s0, s6 - sltiu s3, tp, 300 - addi gp, s8, -298 - rem a2, s2, s9 - addi gp, s8, -298 - nop - add s4, a7, s6 - c.srli a4, 9 - c.andi s1, 31 - c.slli t5, 22 - c.srli a4, 9 - ori tp, a0, -848 - andi t0, a3, 147 - divu tp, s5, t4 - addi gp, s8, -298 - c.addi4spn a2, sp, 528 - c.mv a2, a0 - xor s11, zero, s7 - nop - xori t3, t1, -721 - or a4, a4, zero - c.xor a4, a5 - ori tp, a0, -848 - srl t1, tp, zero - mulhsu tp, t5, a6 - xori t3, t1, -721 - c.mv a2, a0 - addi gp, s8, -298 - sll s8, s0, s6 - and s6, t2, a4 - slti tp, a1, -167 - c.add t3, t1 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - c.sub s0, s1 - and s6, t2, a4 - c.andi s1, 31 - slti tp, a1, -167 - c.lui a6, 24 - c.srli a4, 9 - sltu s3, a6, a4 - c.xor a4, a5 - xor s11, zero, s7 - sltiu s3, tp, 300 - add s4, a7, s6 - c.xor a4, a5 - slti tp, a1, -167 - mulhsu tp, t5, a6 - c.slli t5, 22 - c.sub s0, s1 - c.srai s1, 28 - c.xor a4, a5 - c.lui a6, 24 - c.and a4, s1 - srl t1, tp, zero - c.add t3, t1 - c.and a4, s1 - c.sub s0, s1 - div s7, gp, a4 - c.nop - ori tp, a0, -848 - xori t3, t1, -721 - c.addi4spn a2, sp, 528 - ori tp, a0, -848 - add s4, a7, s6 - c.addi s9, -1 - c.srli a4, 9 - mul tp, s2, t5 - and s6, t2, a4 - sll s8, s0, s6 - andi t0, a3, 147 - divu tp, s5, t4 - c.and a4, s1 - auipc s1, 11691 - c.srli a4, 9 - mulhsu tp, t5, a6 - rem a2, s2, s9 - c.addi s9, -1 - mul tp, s2, t5 - and s6, t2, a4 - lui s3, 985951 - addi gp, s8, -298 - nop - xori t3, t1, -721 - slli a2, a4, 25 - c.addi16sp sp, -16 - sltu s3, a6, a4 - xori t3, t1, -721 - andi t0, a3, 147 - c.add t3, t1 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - remu s6, s3, t1 - or a4, a4, zero - mulhsu tp, t5, a6 - addi gp, s8, -298 - c.mv a2, a0 - slt a0, s5, s11 - c.li s11, -1 - c.srai s1, 28 - srli zero, a0, 13 - c.andi s1, 31 - ori tp, a0, -848 - c.srli a4, 9 - and s6, t2, a4 - mulh s1, t4, s11 - mulhu s4, a6, t3 - nop - c.add t3, t1 - rem a2, s2, s9 - srli zero, a0, 13 - srli zero, a0, 13 - auipc s1, 11691 - mulhsu tp, t5, a6 - srl t1, tp, zero - auipc s1, 11691 - mul tp, s2, t5 - c.sub s0, s1 - c.xor a4, a5 - c.andi s1, 31 - c.xor a4, a5 - ori tp, a0, -848 - c.sub s0, s1 - div s7, gp, a4 - c.addi16sp sp, -16 - srl t1, tp, zero - c.lui a6, 24 - remu s6, s3, t1 - c.slli t5, 22 - c.add t3, t1 - li s10, 0x80000000 #start riscv_int_numeric_corner_stream_16 - li s7, 0x0 - li t3, 0x0 - li s4, 0x80000000 - li a0, 0x0 - li a6, 0xffffffff - li s8, 0x80000000 - li a2, 0x24121a76 - li ra, 0xffffffff - li tp, 0xffffffff - divu a0, s10, s8 - div s8, s8, ra - mulhsu t3, t3, ra - addi ra, s10, -40 - rem a6, a2, a0 - nop - add s4, tp, s10 - rem a6, a2, a0 - nop - addi ra, s10, -40 - sub s10, a0, s8 - add s4, tp, s10 - sub s10, a0, s8 - mul tp, s4, t3 - nop - remu tp, s4, a2 - mul tp, s4, t3 - mul tp, s4, t3 - divu a0, s10, s8 - remu tp, s4, a2 - auipc a2, 11691 - sub s10, a0, s8 - mulhu ra, a2, t3 - addi ra, s10, -40 - lui s7, 985951 - mulhu ra, a2, t3 - rem a6, a2, a0 - mulh t3, s7, tp - mulhu ra, a2, t3 #end riscv_int_numeric_corner_stream_16 - nop - c.mv a2, a0 - remu s6, s3, t1 - slti tp, a1, -167 - addi gp, s8, -298 - sltiu s3, tp, 300 - sub s0, t3, gp - slti tp, a1, -167 - addi gp, s8, -298 - sltiu s3, tp, 300 - c.xor a4, a5 - c.lui a6, 24 - mulhsu tp, t5, a6 - auipc s1, 11691 - remu s6, s3, t1 - c.mv a2, a0 - auipc s1, 11691 - mulhsu tp, t5, a6 - c.mv a2, a0 - srl t1, tp, zero - and s6, t2, a4 - lui s3, 985951 - srli zero, a0, 13 - remu s6, s3, t1 - c.addi16sp sp, -16 - remu s6, s3, t1 - nop - mul tp, s2, t5 - mulh s1, t4, s11 - sub s0, t3, gp - slt a0, s5, s11 - addi gp, s8, -298 - and s6, t2, a4 - addi gp, s8, -298 - xori t3, t1, -721 - slti tp, a1, -167 - mulhu s4, a6, t3 - sub s0, t3, gp - div s7, gp, a4 - c.lui a6, 24 - add s4, a7, s6 - slli a2, a4, 25 - sltu s3, a6, a4 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - mul tp, s2, t5 - srl t1, tp, zero - sltiu s3, tp, 300 - srli zero, a0, 13 - addi gp, s8, -298 - mulh s1, t4, s11 - and s6, t2, a4 - ori tp, a0, -848 - div s7, gp, a4 - and s6, t2, a4 - srl t1, tp, zero - xori t3, t1, -721 - c.slli t5, 22 - slti tp, a1, -167 - c.srli a4, 9 - c.nop - c.or a0, a2 - sra s9, s4, t5 - addi gp, s8, -298 - div s7, gp, a4 - slti tp, a1, -167 - sra s9, s4, t5 - c.xor a4, a5 - mul tp, s2, t5 - c.srai s1, 28 - c.andi s1, 31 - andi t0, a3, 147 - xor s11, zero, s7 - c.srai s1, 28 - nop - or a4, a4, zero - sll s8, s0, s6 - mulh s1, t4, s11 - sub s0, t3, gp - mul tp, s2, t5 - c.nop - remu s6, s3, t1 - sub s0, t3, gp - or a4, a4, zero - c.li s11, -1 - c.lui a6, 24 - c.and a4, s1 - sll s8, s0, s6 - sll s8, s0, s6 - or a4, a4, zero - lui s3, 985951 - auipc s1, 11691 - slli a2, a4, 25 - andi t0, a3, 147 - c.addi16sp sp, -16 - div s7, gp, a4 - div s7, gp, a4 - srl t1, tp, zero - sra s9, s4, t5 - srl t1, tp, zero - c.andi s1, 31 - sltu s3, a6, a4 - xor s11, zero, s7 - c.addi s9, -1 - nop - div s7, gp, a4 - sltu s3, a6, a4 - add s4, a7, s6 - srai a4, a3, 0 - addi gp, s8, -298 - c.xor a4, a5 - c.add t3, t1 - c.lui a6, 24 - andi t0, a3, 147 - andi t0, a3, 147 - xor s11, zero, s7 - c.sub s0, s1 - remu s6, s3, t1 - divu tp, s5, t4 - andi t0, a3, 147 - srai a4, a3, 0 - mulhsu tp, t5, a6 - c.xor a4, a5 - c.mv a2, a0 - auipc s1, 11691 - slli a2, a4, 25 - c.add t3, t1 - srl t1, tp, zero - xori t3, t1, -721 - c.li s11, -1 - slti tp, a1, -167 - c.lui a6, 24 - c.srai s1, 28 - c.li s11, -1 - c.mv a2, a0 - remu s6, s3, t1 - srl t1, tp, zero - c.li s11, -1 - c.addi4spn a2, sp, 528 - xori t3, t1, -721 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - c.lui a6, 24 - c.andi s1, 31 - sltiu s3, tp, 300 - c.and a4, s1 - c.xor a4, a5 - sra s9, s4, t5 - srli zero, a0, 13 - ori tp, a0, -848 - sub s0, t3, gp - divu tp, s5, t4 - c.xor a4, a5 - auipc s1, 11691 - or a4, a4, zero - srli zero, a0, 13 - c.addi4spn a2, sp, 528 - c.srai s1, 28 - c.or a0, a2 - c.andi s1, 31 - sra s9, s4, t5 - sll s8, s0, s6 - c.mv a2, a0 - slti tp, a1, -167 - srli zero, a0, 13 - c.or a0, a2 - sltiu s3, tp, 300 - slt a0, s5, s11 - rem a2, s2, s9 - c.and a4, s1 - slt a0, s5, s11 - sltu s3, a6, a4 - c.li s11, -1 - sra s9, s4, t5 - c.nop - andi t0, a3, 147 - c.slli t5, 22 - sltu s3, a6, a4 - mulhu s4, a6, t3 - and s6, t2, a4 - sltu s3, a6, a4 - mulhu s4, a6, t3 - nop - mul tp, s2, t5 - c.andi s1, 31 - c.addi4spn a2, sp, 528 - c.srai s1, 28 - divu tp, s5, t4 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - c.slli t5, 22 - c.lui a6, 24 - c.addi16sp sp, -16 - c.srli a4, 9 - sra s9, s4, t5 - slli a2, a4, 25 - sll s8, s0, s6 - c.slli t5, 22 - c.lui a6, 24 - auipc s1, 11691 - ori tp, a0, -848 - srl t1, tp, zero - rem a2, s2, s9 - c.li s11, -1 - c.sub s0, s1 - mulh s1, t4, s11 - slti tp, a1, -167 - nop - c.andi s1, 31 - c.sub s0, s1 - xor s11, zero, s7 - c.srai s1, 28 - c.srai s1, 28 - srai a4, a3, 0 - sll s8, s0, s6 - c.addi4spn a2, sp, 528 - srl t1, tp, zero - c.addi4spn a2, sp, 528 - slti tp, a1, -167 - c.addi16sp sp, -16 - slti tp, a1, -167 - sll s8, s0, s6 - c.andi s1, 31 - sra s9, s4, t5 - nop - add s4, a7, s6 - c.lui a6, 24 - remu s6, s3, t1 - c.lui a6, 24 - c.and a4, s1 - rem a2, s2, s9 - c.srai s1, 28 - div s7, gp, a4 - sll s8, s0, s6 - div s7, gp, a4 - nop - xori t3, t1, -721 - sltiu s3, tp, 300 - c.lui a6, 24 - slli a2, a4, 25 - xori t3, t1, -721 - addi gp, s8, -298 - div s7, gp, a4 - andi t0, a3, 147 - mul tp, s2, t5 - xori t3, t1, -721 - c.addi s9, -1 - srai a4, a3, 0 - c.addi s9, -1 - auipc s1, 11691 - mul tp, s2, t5 - and s6, t2, a4 - c.xor a4, a5 - srli zero, a0, 13 - slti tp, a1, -167 - addi gp, s8, -298 - srl t1, tp, zero - div s7, gp, a4 - ori tp, a0, -848 - xor s11, zero, s7 - c.and a4, s1 - rem a2, s2, s9 - c.li s11, -1 - sub s0, t3, gp - c.mv a2, a0 - srl t1, tp, zero - c.addi s9, -1 - c.sub s0, s1 - and s6, t2, a4 - slt a0, s5, s11 - c.srli a4, 9 - sub s0, t3, gp - c.andi s1, 31 - sll s8, s0, s6 - sltiu s3, tp, 300 - add s4, a7, s6 - sltu s3, a6, a4 - nop - srli zero, a0, 13 - c.lui a6, 24 - rem a2, s2, s9 - c.andi s1, 31 - srl t1, tp, zero - c.or a0, a2 - xori t3, t1, -721 - c.lui a6, 24 - xor s11, zero, s7 - divu tp, s5, t4 - c.addi4spn a2, sp, 528 - sra s9, s4, t5 - mulh s1, t4, s11 - c.andi s1, 31 - mulh s1, t4, s11 - sltu s3, a6, a4 - c.addi4spn a2, sp, 528 - and s6, t2, a4 - c.addi16sp sp, -16 - slli a2, a4, 25 - mul tp, s2, t5 - addi gp, s8, -298 - c.srai s1, 28 - ori tp, a0, -848 - nop - c.and a4, s1 - c.nop - c.srli a4, 9 - divu tp, s5, t4 - c.nop - slt a0, s5, s11 - slli a2, a4, 25 - nop - ori tp, a0, -848 - sra s9, s4, t5 - remu s6, s3, t1 - addi gp, s8, -298 - sll s8, s0, s6 - sll s8, s0, s6 - slli a2, a4, 25 - nop - c.sub s0, s1 - c.slli t5, 22 - xor s11, zero, s7 - c.srai s1, 28 - or a4, a4, zero - c.li s11, -1 - c.lui a6, 24 - c.or a0, a2 - sltiu s3, tp, 300 - or a4, a4, zero - srli zero, a0, 13 - sll s8, s0, s6 - mulh s1, t4, s11 - sub s0, t3, gp - slt a0, s5, s11 - c.addi16sp sp, -16 - c.addi16sp sp, -16 - c.addi s9, -1 - nop - c.sub s0, s1 - c.addi16sp sp, -16 - slli a2, a4, 25 - mulhu s4, a6, t3 - ori tp, a0, -848 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - c.srai s1, 28 - c.nop - div s7, gp, a4 - sra s9, s4, t5 - xor s11, zero, s7 - sub s0, t3, gp - add s4, a7, s6 - c.li s11, -1 - add s4, a7, s6 - sra s9, s4, t5 - c.andi s1, 31 - sub s0, t3, gp - c.add t3, t1 - c.lui a6, 24 - xor s11, zero, s7 - ori tp, a0, -848 - mulhu s4, a6, t3 - c.mv a2, a0 - c.lui a6, 24 - c.add t3, t1 - sltiu s3, tp, 300 - c.srli a4, 9 - div s7, gp, a4 - c.mv a2, a0 - c.srli a4, 9 - nop - c.add t3, t1 - sltu s3, a6, a4 - c.sub s0, s1 - c.slli t5, 22 - c.and a4, s1 - rem a2, s2, s9 - slli a2, a4, 25 - divu tp, s5, t4 - c.nop - lui s3, 985951 - andi t0, a3, 147 - div s7, gp, a4 - lui s3, 985951 - c.addi4spn a2, sp, 528 - addi gp, s8, -298 - sltu s3, a6, a4 - srli zero, a0, 13 - xor s11, zero, s7 - mulhsu tp, t5, a6 - c.srli a4, 9 - c.slli t5, 22 - sltu s3, a6, a4 - add s4, a7, s6 - c.mv a2, a0 - c.addi s9, -1 - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - ori tp, a0, -848 - lui s3, 985951 - c.srai s1, 28 - auipc s1, 11691 - c.addi s9, -1 - slli a2, a4, 25 - nop - div s7, gp, a4 - auipc s1, 11691 - c.sub s0, s1 - c.sub s0, s1 - srli zero, a0, 13 - c.li s11, -1 - c.li s11, -1 - add s4, a7, s6 - nop - addi gp, s8, -298 - lui s3, 985951 - c.mv a2, a0 - c.mv a2, a0 - ori tp, a0, -848 - sll s8, s0, s6 - c.slli t5, 22 - c.srai s1, 28 - c.addi16sp sp, -16 - and s6, t2, a4 - c.slli t5, 22 - c.slli t5, 22 - mulh s1, t4, s11 - xor s11, zero, s7 - c.lui a6, 24 - c.slli t5, 22 - remu s6, s3, t1 - add s4, a7, s6 - div s7, gp, a4 - sltiu s3, tp, 300 - c.lui a6, 24 - c.or a0, a2 - c.nop - rem a2, s2, s9 - c.srli a4, 9 - sltiu s3, tp, 300 - slli a2, a4, 25 - auipc s1, 11691 - c.sub s0, s1 - c.addi16sp sp, -16 - or a4, a4, zero - xor s11, zero, s7 - c.li s11, -1 - c.li s11, -1 - and s6, t2, a4 - c.li s11, -1 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - c.srli a4, 9 - mulhsu tp, t5, a6 - srai a4, a3, 0 - xor s11, zero, s7 - auipc s1, 11691 - sltiu s3, tp, 300 - add s4, a7, s6 - add s4, a7, s6 - c.srai s1, 28 - c.srai s1, 28 - nop - c.addi s9, -1 - mulhsu tp, t5, a6 - slli a2, a4, 25 - c.add t3, t1 - rem a2, s2, s9 - srai a4, a3, 0 - c.addi4spn a2, sp, 528 - c.slli t5, 22 - rem a2, s2, s9 - c.xor a4, a5 - c.addi4spn a2, sp, 528 - or a4, a4, zero - slti tp, a1, -167 - addi gp, s8, -298 - rem a2, s2, s9 - c.srli a4, 9 - c.or a0, a2 - c.addi16sp sp, -16 - srai a4, a3, 0 - c.addi16sp sp, -16 - mul tp, s2, t5 - srai a4, a3, 0 - divu tp, s5, t4 - lui s3, 985951 - c.srli a4, 9 - remu s6, s3, t1 - xor s11, zero, s7 - sll s8, s0, s6 - c.slli t5, 22 - sll s8, s0, s6 - c.li s11, -1 - c.addi s9, -1 - srl t1, tp, zero - lui s3, 985951 - c.mv a2, a0 - srl t1, tp, zero - mulh s1, t4, s11 - srli zero, a0, 13 - c.lui a6, 24 - mulh s1, t4, s11 - c.srli a4, 9 - sltiu s3, tp, 300 - xori t3, t1, -721 - slti tp, a1, -167 - c.srai s1, 28 - sltu s3, a6, a4 - remu s6, s3, t1 - c.andi s1, 31 - c.addi s9, -1 - mulhsu tp, t5, a6 - c.mv a2, a0 - addi gp, s8, -298 - c.srai s1, 28 - andi t0, a3, 147 - srli zero, a0, 13 - srl t1, tp, zero - mulhsu tp, t5, a6 - mulh s1, t4, s11 - c.xor a4, a5 - c.slli t5, 22 - addi gp, s8, -298 - div s7, gp, a4 - c.srli a4, 9 - c.slli t5, 22 - c.li s11, -1 - c.and a4, s1 - mul tp, s2, t5 - c.addi16sp sp, -16 - c.and a4, s1 - c.lui a6, 24 - c.addi16sp sp, -16 - srl t1, tp, zero - slti tp, a1, -167 - ori tp, a0, -848 - sltu s3, a6, a4 - c.srai s1, 28 - sltiu s3, tp, 300 - c.slli t5, 22 - slti tp, a1, -167 - and s6, t2, a4 - auipc s1, 11691 - div s7, gp, a4 - c.sub s0, s1 - c.li s11, -1 - divu tp, s5, t4 - c.addi4spn a2, sp, 528 - or a4, a4, zero - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - c.lui a6, 24 - auipc s1, 11691 - div s7, gp, a4 - c.lui a6, 24 - sll s8, s0, s6 - div s7, gp, a4 - c.nop - add s4, a7, s6 - mulhu s4, a6, t3 - mul tp, s2, t5 - div s7, gp, a4 - c.slli t5, 22 - nop - addi gp, s8, -298 - andi t0, a3, 147 - slli a2, a4, 25 - slli a2, a4, 25 - c.xor a4, a5 - c.and a4, s1 - div s7, gp, a4 - srli zero, a0, 13 - c.or a0, a2 - add s4, a7, s6 - c.srai s1, 28 - c.and a4, s1 - slt a0, s5, s11 - nop - srli zero, a0, 13 - addi gp, s8, -298 - sra s9, s4, t5 - c.sub s0, s1 - slti tp, a1, -167 - sltiu s3, tp, 300 - c.addi s9, -1 - auipc s1, 11691 - sltu s3, a6, a4 - slti tp, a1, -167 - c.slli t5, 22 - c.and a4, s1 - c.addi s9, -1 - c.addi s9, -1 - sltu s3, a6, a4 - sub s0, t3, gp - slti tp, a1, -167 - remu s6, s3, t1 - slti tp, a1, -167 - c.addi16sp sp, -16 - srli zero, a0, 13 - andi t0, a3, 147 - remu s6, s3, t1 - mulh s1, t4, s11 - xori t3, t1, -721 - srli zero, a0, 13 - c.addi s9, -1 - add s4, a7, s6 - srai a4, a3, 0 - auipc s1, 11691 - srl t1, tp, zero - c.nop - c.and a4, s1 - c.and a4, s1 - c.slli t5, 22 - c.add t3, t1 - sra s9, s4, t5 - or a4, a4, zero - mulhsu tp, t5, a6 - c.addi16sp sp, -16 - remu s6, s3, t1 - c.addi4spn a2, sp, 528 - mul tp, s2, t5 - srli zero, a0, 13 - andi t0, a3, 147 - mul tp, s2, t5 - c.add t3, t1 - xor s11, zero, s7 - add s4, a7, s6 - divu tp, s5, t4 - slti tp, a1, -167 - and s6, t2, a4 - sltiu s3, tp, 300 - sra s9, s4, t5 - div s7, gp, a4 - c.or a0, a2 - sltu s3, a6, a4 - nop - mulhu s4, a6, t3 - sll s8, s0, s6 - sll s8, s0, s6 - c.li s11, -1 - lui s3, 985951 - xor s11, zero, s7 - c.addi s9, -1 - c.li s11, -1 - sll s8, s0, s6 - mulh s1, t4, s11 - xor s11, zero, s7 - srai a4, a3, 0 - rem a2, s2, s9 - slt a0, s5, s11 - srl t1, tp, zero - lui s3, 985951 - lui s3, 985951 - srai a4, a3, 0 - div s7, gp, a4 - slt a0, s5, s11 - c.nop - auipc s1, 11691 - c.slli t5, 22 - srli zero, a0, 13 - c.nop - sltu s3, a6, a4 - xori t3, t1, -721 - sll s8, s0, s6 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - sub s0, t3, gp - or a4, a4, zero - c.addi4spn a2, sp, 528 - mulhu s4, a6, t3 - mul tp, s2, t5 - lui s3, 985951 - mulhu s4, a6, t3 - nop - add s4, a7, s6 - div s7, gp, a4 - sub s0, t3, gp - srl t1, tp, zero - andi t0, a3, 147 - c.sub s0, s1 - lui s3, 985951 - xori t3, t1, -721 - auipc s1, 11691 - srai a4, a3, 0 - li a0, 0x0 #start riscv_int_numeric_corner_stream_23 - li tp, 0x2182c967 - li t1, 0x0 - li s7, 0xffffffff - li sp, 0x78213fcb - li a7, 0x80000000 - li s4, 0x90f3ffac - li a2, 0xffffffff - li s1, 0x80000000 - li s9, 0x9d674d41 - addi tp, s7, -40 - lui s7, 985951 - mulh s4, s9, tp - divu a2, a0, a7 - mulhsu t1, a2, a7 - divu a2, a0, a7 - nop - mulhu a7, s1, s7 - add sp, tp, t1 - sub s9, s1, s9 - auipc s1, 11691 - nop - lui s7, 985951 - mulhu a7, s1, s7 - lui s7, 985951 - auipc s1, 11691 - add sp, tp, t1 - lui s7, 985951 - nop - sub s9, s1, s9 - lui s7, 985951 - divu a2, a0, a7 - mulh s4, s9, tp - mul a2, s4, a0 - add sp, tp, t1 - mulhu a7, s1, s7 - mulh s4, s9, tp - mulhu a7, s1, s7 #end riscv_int_numeric_corner_stream_23 - xor s11, zero, s7 - c.lui a6, 24 - srl t1, tp, zero - c.sub s0, s1 - c.li s11, -1 - remu s6, s3, t1 - slt a0, s5, s11 - mul tp, s2, t5 - divu tp, s5, t4 - sll s8, s0, s6 - xor s11, zero, s7 - slli a2, a4, 25 - c.srai s1, 28 - c.xor a4, a5 - auipc s1, 11691 - c.nop - sltiu s3, tp, 300 - c.lui a6, 24 - divu tp, s5, t4 - nop - ori tp, a0, -848 - c.add t3, t1 - slt a0, s5, s11 - c.add t3, t1 - sltiu s3, tp, 300 - remu s6, s3, t1 - c.nop - mulh s1, t4, s11 - sltu s3, a6, a4 - ori tp, a0, -848 - mul tp, s2, t5 - mulhu s4, a6, t3 - srli zero, a0, 13 - c.sub s0, s1 - mulhu s4, a6, t3 - sltu s3, a6, a4 - or a4, a4, zero - c.nop - c.srli a4, 9 - nop - c.or a0, a2 - c.addi s9, -1 - c.slli t5, 22 - c.srli a4, 9 - xor s11, zero, s7 - slti tp, a1, -167 - lui s3, 985951 - mulh s1, t4, s11 - div s7, gp, a4 - c.slli t5, 22 - divu tp, s5, t4 - and s6, t2, a4 - c.srai s1, 28 - c.sub s0, s1 - and s6, t2, a4 - sltu s3, a6, a4 - c.or a0, a2 - add s4, a7, s6 - div s7, gp, a4 - mul tp, s2, t5 - srl t1, tp, zero - mul tp, s2, t5 - c.srli a4, 9 - c.slli t5, 22 - c.and a4, s1 - divu tp, s5, t4 - c.andi s1, 31 - sltu s3, a6, a4 - and s6, t2, a4 - sll s8, s0, s6 - sra s9, s4, t5 - c.srai s1, 28 - c.addi16sp sp, -16 - srli zero, a0, 13 - c.nop - sltiu s3, tp, 300 - c.addi4spn a2, sp, 528 - c.addi4spn a2, sp, 528 - mulhsu tp, t5, a6 - c.xor a4, a5 - sltiu s3, tp, 300 - addi gp, s8, -298 - div s7, gp, a4 - slti tp, a1, -167 - or a4, a4, zero - c.sub s0, s1 - c.li s11, -1 - srl t1, tp, zero - div s7, gp, a4 - sll s8, s0, s6 - srai a4, a3, 0 - mulhu s4, a6, t3 - sra s9, s4, t5 - c.slli t5, 22 - srai a4, a3, 0 - c.addi4spn a2, sp, 528 - auipc s1, 11691 - lui s3, 985951 - div s7, gp, a4 - c.addi4spn a2, sp, 528 - divu tp, s5, t4 - ori tp, a0, -848 - slti tp, a1, -167 - auipc s1, 11691 - srli zero, a0, 13 - c.add t3, t1 - auipc s1, 11691 - c.lui a6, 24 - remu s6, s3, t1 - nop - c.srai s1, 28 - xor s11, zero, s7 - c.sub s0, s1 - sltu s3, a6, a4 - slt a0, s5, s11 - and s6, t2, a4 - c.andi s1, 31 - mulh s1, t4, s11 - c.or a0, a2 - sra s9, s4, t5 - xori t3, t1, -721 - c.li s11, -1 - xor s11, zero, s7 - auipc s1, 11691 - or a4, a4, zero - addi gp, s8, -298 - c.nop - slli a2, a4, 25 - c.or a0, a2 - c.sub s0, s1 - ori tp, a0, -848 - c.nop - div s7, gp, a4 - c.lui a6, 24 - c.mv a2, a0 - c.mv a2, a0 - c.addi s9, -1 - slli a2, a4, 25 - slli a2, a4, 25 - c.and a4, s1 - addi gp, s8, -298 - slt a0, s5, s11 - c.andi s1, 31 - mul tp, s2, t5 - c.addi16sp sp, -16 - srli zero, a0, 13 - divu tp, s5, t4 - c.mv a2, a0 - c.addi s9, -1 - c.mv a2, a0 - sub s0, t3, gp - srai a4, a3, 0 - c.or a0, a2 - sub s0, t3, gp - sub s0, t3, gp - srai a4, a3, 0 - c.slli t5, 22 - slli a2, a4, 25 - srli zero, a0, 13 - c.srai s1, 28 - remu s6, s3, t1 - c.or a0, a2 - c.lui a6, 24 - sltu s3, a6, a4 - c.addi16sp sp, -16 - c.mv a2, a0 - c.and a4, s1 - sra s9, s4, t5 - c.addi4spn a2, sp, 528 - sub s0, t3, gp - srl t1, tp, zero - c.srai s1, 28 - andi t0, a3, 147 - srl t1, tp, zero - c.lui a6, 24 - c.andi s1, 31 - slli a2, a4, 25 - srli zero, a0, 13 - remu s6, s3, t1 - mulhu s4, a6, t3 - remu s6, s3, t1 - c.lui a6, 24 - slli a2, a4, 25 - nop - c.mv a2, a0 - lui s3, 985951 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - slli a2, a4, 25 - auipc s1, 11691 - mul tp, s2, t5 - c.add t3, t1 - remu s6, s3, t1 - c.addi16sp sp, -16 - add s4, a7, s6 - slti tp, a1, -167 - mulhsu tp, t5, a6 - srli zero, a0, 13 - slli a2, a4, 25 - c.srli a4, 9 - sra s9, s4, t5 - c.add t3, t1 - c.add t3, t1 - mulhu s4, a6, t3 - mulhsu tp, t5, a6 - slli a2, a4, 25 - rem a2, s2, s9 - c.or a0, a2 - c.and a4, s1 - c.andi s1, 31 - auipc s1, 11691 - sub s0, t3, gp - c.srli a4, 9 - rem a2, s2, s9 - remu s6, s3, t1 - sll s8, s0, s6 - c.and a4, s1 - sll s8, s0, s6 - sltiu s3, tp, 300 - div s7, gp, a4 - xori t3, t1, -721 - srai a4, a3, 0 - sltu s3, a6, a4 - c.mv a2, a0 - sub s0, t3, gp - rem a2, s2, s9 - c.li s11, -1 - c.xor a4, a5 - mulhu s4, a6, t3 - srai a4, a3, 0 - slt a0, s5, s11 - slli a2, a4, 25 - mulhsu tp, t5, a6 - mul tp, s2, t5 - slt a0, s5, s11 - c.andi s1, 31 - c.xor a4, a5 - c.and a4, s1 - srai a4, a3, 0 - sll s8, s0, s6 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - and s6, t2, a4 - c.li s11, -1 - add s4, a7, s6 - c.or a0, a2 - c.nop - c.and a4, s1 - sll s8, s0, s6 - c.lui a6, 24 - slli a2, a4, 25 - addi gp, s8, -298 - c.addi4spn a2, sp, 528 - xor s11, zero, s7 - c.xor a4, a5 - remu s6, s3, t1 - c.andi s1, 31 - remu s6, s3, t1 - lui s3, 985951 - c.lui a6, 24 - remu s6, s3, t1 - c.and a4, s1 - c.srai s1, 28 - mul tp, s2, t5 - sltiu s3, tp, 300 - sll s8, s0, s6 - addi gp, s8, -298 - or a4, a4, zero - sub s0, t3, gp - slti tp, a1, -167 - sltu s3, a6, a4 - c.andi s1, 31 - add s4, a7, s6 - c.addi s9, -1 - mulhu s4, a6, t3 - div s7, gp, a4 - sub s0, t3, gp - xori t3, t1, -721 - sra s9, s4, t5 - rem a2, s2, s9 - c.or a0, a2 - c.slli t5, 22 - auipc s1, 11691 - slt a0, s5, s11 - xor s11, zero, s7 - c.andi s1, 31 - divu tp, s5, t4 - auipc s1, 11691 - mul tp, s2, t5 - xori t3, t1, -721 - slli a2, a4, 25 - c.nop - xor s11, zero, s7 - remu s6, s3, t1 - rem a2, s2, s9 - slli a2, a4, 25 - addi gp, s8, -298 - sub s0, t3, gp - sub s0, t3, gp - sll s8, s0, s6 - or a4, a4, zero - c.xor a4, a5 - c.or a0, a2 - c.li s11, -1 - c.add t3, t1 - c.or a0, a2 - sub s0, t3, gp - xori t3, t1, -721 - div s7, gp, a4 - sltiu s3, tp, 300 - add s4, a7, s6 - sltu s3, a6, a4 - srli zero, a0, 13 - srli zero, a0, 13 - c.xor a4, a5 - sltu s3, a6, a4 - c.addi16sp sp, -16 - c.addi16sp sp, -16 - mulhu s4, a6, t3 - slli a2, a4, 25 - c.srai s1, 28 - mulh s1, t4, s11 - c.nop - slt a0, s5, s11 - c.xor a4, a5 - mulhsu tp, t5, a6 - c.srli a4, 9 - divu tp, s5, t4 - mul tp, s2, t5 - c.lui a6, 24 - mul tp, s2, t5 - c.lui a6, 24 - c.slli t5, 22 - c.mv a2, a0 - mul tp, s2, t5 - lui s3, 985951 - c.sub s0, s1 - div s7, gp, a4 - c.slli t5, 22 - sra s9, s4, t5 - c.mv a2, a0 - c.addi4spn a2, sp, 528 - add s4, a7, s6 - c.and a4, s1 - c.srai s1, 28 - c.sub s0, s1 - remu s6, s3, t1 - addi gp, s8, -298 - sra s9, s4, t5 - srl t1, tp, zero - c.xor a4, a5 - lui s3, 985951 - srl t1, tp, zero - c.slli t5, 22 - c.or a0, a2 - remu s6, s3, t1 - c.add t3, t1 - andi t0, a3, 147 - c.or a0, a2 - andi t0, a3, 147 - slti tp, a1, -167 - mulhu s4, a6, t3 - mul tp, s2, t5 - c.slli t5, 22 - xor s11, zero, s7 - c.srai s1, 28 - sltu s3, a6, a4 - rem a2, s2, s9 - and s6, t2, a4 - srl t1, tp, zero - addi gp, s8, -298 - c.lui a6, 24 - or a4, a4, zero - li ra, 0x0 #start riscv_int_numeric_corner_stream_11 - li t2, 0xffffffff - li t5, 0xad6c0f11 - li tp, 0xa4f40228 - li a6, 0x0 - li s0, 0xffffffff - li a0, 0xffffffff - li s3, 0x80000000 - li t0, 0x0 - li a4, 0x8965d238 - mulhu t5, a6, t5 - sub a6, ra, t5 - divu a0, a4, a6 - lui s3, 985951 - nop - lui s3, 985951 - remu s0, t5, a4 - lui s3, 985951 - lui s3, 985951 - div a6, s3, t2 - nop - mulhsu t5, s0, ra - mul t2, s3, s0 - nop - addi ra, s3, -40 #end riscv_int_numeric_corner_stream_11 - sub s0, t3, gp - xori t3, t1, -721 - c.addi s9, -1 - c.slli t5, 22 - and s6, t2, a4 - mul tp, s2, t5 - srai a4, a3, 0 - mulhu s4, a6, t3 - c.and a4, s1 - srli zero, a0, 13 - add s4, a7, s6 - sll s8, s0, s6 - srli zero, a0, 13 - c.nop - c.addi16sp sp, -16 - divu tp, s5, t4 - c.lui a6, 24 - c.lui a6, 24 - srli zero, a0, 13 - add s4, a7, s6 - rem a2, s2, s9 - srli zero, a0, 13 - and s6, t2, a4 - and s6, t2, a4 - sltiu s3, tp, 300 - auipc s1, 11691 - mulh s1, t4, s11 - remu s6, s3, t1 - c.mv a2, a0 - c.lui a6, 24 - add s4, a7, s6 - c.addi s9, -1 - c.add t3, t1 - auipc s1, 11691 - c.mv a2, a0 - or a4, a4, zero - c.and a4, s1 - sll s8, s0, s6 - and s6, t2, a4 - c.or a0, a2 - auipc s1, 11691 - xor s11, zero, s7 - nop - mulhu s4, a6, t3 - mulhsu tp, t5, a6 - rem a2, s2, s9 - mul tp, s2, t5 - c.and a4, s1 - c.srli a4, 9 - c.srli a4, 9 - add s4, a7, s6 - slt a0, s5, s11 - rem a2, s2, s9 - sltu s3, a6, a4 - or a4, a4, zero - mulhsu tp, t5, a6 - mulhu s4, a6, t3 - c.mv a2, a0 - mul tp, s2, t5 - add s4, a7, s6 - c.andi s1, 31 - div s7, gp, a4 - sub s0, t3, gp - add s4, a7, s6 - c.nop - lui s3, 985951 - srli zero, a0, 13 - c.srli a4, 9 - c.addi s9, -1 - lui s3, 985951 - xori t3, t1, -721 - rem a2, s2, s9 - divu tp, s5, t4 - c.addi16sp sp, -16 - srl t1, tp, zero - slt a0, s5, s11 - nop - sll s8, s0, s6 - c.xor a4, a5 - mulh s1, t4, s11 - srai a4, a3, 0 - or a4, a4, zero - c.srli a4, 9 - addi gp, s8, -298 - rem a2, s2, s9 - mul tp, s2, t5 - divu tp, s5, t4 - srai a4, a3, 0 - sltiu s3, tp, 300 - ori tp, a0, -848 - div s7, gp, a4 - xor s11, zero, s7 - add s4, a7, s6 - mulh s1, t4, s11 - div s7, gp, a4 - c.mv a2, a0 - sltiu s3, tp, 300 - mulhu s4, a6, t3 - c.lui a6, 24 - c.addi16sp sp, -16 - c.and a4, s1 - xori t3, t1, -721 - andi t0, a3, 147 - addi gp, s8, -298 - rem a2, s2, s9 - c.addi4spn a2, sp, 528 - andi t0, a3, 147 - addi gp, s8, -298 - slli a2, a4, 25 - mulhsu tp, t5, a6 - c.srai s1, 28 - mulhsu tp, t5, a6 - sll s8, s0, s6 - c.add t3, t1 - slti tp, a1, -167 - slli a2, a4, 25 - mul tp, s2, t5 - c.li s11, -1 - sltu s3, a6, a4 - c.or a0, a2 - auipc s1, 11691 - sub s0, t3, gp - c.addi s9, -1 - mulhsu tp, t5, a6 - c.add t3, t1 - ori tp, a0, -848 - mulh s1, t4, s11 - rem a2, s2, s9 - sltiu s3, tp, 300 - srl t1, tp, zero - c.and a4, s1 - div s7, gp, a4 - nop - c.slli t5, 22 - c.addi s9, -1 - xor s11, zero, s7 - div s7, gp, a4 - c.or a0, a2 - slli a2, a4, 25 - c.xor a4, a5 - sltu s3, a6, a4 - mulh s1, t4, s11 - c.addi4spn a2, sp, 528 - sub s0, t3, gp - ori tp, a0, -848 - nop - sltiu s3, tp, 300 - lui s3, 985951 - sltiu s3, tp, 300 - c.lui a6, 24 - sltu s3, a6, a4 - sltiu s3, tp, 300 - add s4, a7, s6 - c.addi4spn a2, sp, 528 - remu s6, s3, t1 - c.andi s1, 31 - xor s11, zero, s7 - rem a2, s2, s9 - sra s9, s4, t5 - c.sub s0, s1 - c.addi16sp sp, -16 - sll s8, s0, s6 - slti tp, a1, -167 - srli zero, a0, 13 - div s7, gp, a4 - c.addi16sp sp, -16 - c.andi s1, 31 - xor s11, zero, s7 - auipc s1, 11691 - c.andi s1, 31 - ori tp, a0, -848 - rem a2, s2, s9 - srli zero, a0, 13 - c.nop - mulh s1, t4, s11 - rem a2, s2, s9 - add s4, a7, s6 - sltu s3, a6, a4 - c.or a0, a2 - c.addi16sp sp, -16 - slt a0, s5, s11 - divu tp, s5, t4 - sra s9, s4, t5 - divu tp, s5, t4 - c.addi16sp sp, -16 - c.andi s1, 31 - c.addi4spn a2, sp, 528 - mulh s1, t4, s11 - sll s8, s0, s6 - c.sub s0, s1 - c.srli a4, 9 - mulh s1, t4, s11 - c.and a4, s1 - mulhsu tp, t5, a6 - srli zero, a0, 13 - sra s9, s4, t5 - div s7, gp, a4 - c.or a0, a2 - mulh s1, t4, s11 - rem a2, s2, s9 - add s4, a7, s6 - mulh s1, t4, s11 - mulh s1, t4, s11 - c.or a0, a2 - srli zero, a0, 13 - c.addi16sp sp, -16 - xori t3, t1, -721 - c.or a0, a2 - mulhsu tp, t5, a6 - xori t3, t1, -721 - slli a2, a4, 25 - auipc s1, 11691 - divu tp, s5, t4 - c.srli a4, 9 - c.and a4, s1 - lui s3, 985951 - or a4, a4, zero - or a4, a4, zero - nop - li s8, 0x80000000 #start riscv_int_numeric_corner_stream_14 - li a0, 0x0 - li a3, 0x0 - li s2, 0x80000000 - li sp, 0xffffffff - li s10, 0xffffffff - li s4, 0x80000000 - li s1, 0xc60aaa38 - li s6, 0xffffffff - li t2, 0x0 - mulh a3, t2, t2 - lui t2, 985951 - remu s4, s10, a0 - addi a0, s6, -40 - div s4, a3, t2 - mulhu s10, s1, s6 - addi a0, s6, -40 - sub s4, s1, s8 - sub s4, s1, s8 - auipc s1, 11691 - div s4, a3, t2 - sub s4, s1, s8 - remu s4, s10, a0 - nop - nop - remu s4, s10, a0 - addi a0, s6, -40 - mulhsu s4, a3, s1 - add s6, sp, s6 - nop - mulh a3, t2, t2 - rem s4, s2, t2 - nop - add s6, sp, s6 - sub s4, s1, s8 - mulhsu s4, a3, s1 - mulh a3, t2, t2 - sub s4, s1, s8 - div s4, a3, t2 #end riscv_int_numeric_corner_stream_14 - c.srai s1, 28 - mulh s1, t4, s11 - sra s9, s4, t5 - c.sub s0, s1 - c.and a4, s1 - c.li s11, -1 - c.li s11, -1 - mul tp, s2, t5 - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - ori tp, a0, -848 - mulhu s4, a6, t3 - c.addi4spn a2, sp, 528 - c.addi4spn a2, sp, 528 - divu tp, s5, t4 - lui s3, 985951 - srl t1, tp, zero - sltu s3, a6, a4 - c.or a0, a2 - srai a4, a3, 0 - sll s8, s0, s6 - slti tp, a1, -167 - c.srli a4, 9 - mulhsu tp, t5, a6 - mulhu s4, a6, t3 - mul tp, s2, t5 - remu s6, s3, t1 - sub s0, t3, gp - sub s0, t3, gp - c.add t3, t1 - c.xor a4, a5 - c.mv a2, a0 - nop - sra s9, s4, t5 - mulh s1, t4, s11 - mulhu s4, a6, t3 - rem a2, s2, s9 - xori t3, t1, -721 - auipc s1, 11691 - mulhsu tp, t5, a6 - slt a0, s5, s11 - mulhsu tp, t5, a6 - sra s9, s4, t5 - and s6, t2, a4 - div s7, gp, a4 - div s7, gp, a4 - slli a2, a4, 25 - div s7, gp, a4 - xori t3, t1, -721 - andi t0, a3, 147 - srl t1, tp, zero - c.li s11, -1 - sltiu s3, tp, 300 - andi t0, a3, 147 - xori t3, t1, -721 - sltiu s3, tp, 300 - slti tp, a1, -167 - rem a2, s2, s9 - xori t3, t1, -721 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - sll s8, s0, s6 - c.nop - ori tp, a0, -848 - mulhsu tp, t5, a6 - c.srai s1, 28 - slti tp, a1, -167 - mulh s1, t4, s11 - divu tp, s5, t4 - auipc s1, 11691 - srai a4, a3, 0 - c.lui a6, 24 - slli a2, a4, 25 - rem a2, s2, s9 - c.xor a4, a5 - or a4, a4, zero - c.and a4, s1 - c.mv a2, a0 - addi gp, s8, -298 - andi t0, a3, 147 - slti tp, a1, -167 - c.xor a4, a5 - c.li s11, -1 - add s4, a7, s6 - c.addi16sp sp, -16 - add s4, a7, s6 - c.or a0, a2 - c.and a4, s1 - div s7, gp, a4 - c.mv a2, a0 - sltiu s3, tp, 300 - nop - srl t1, tp, zero - slli a2, a4, 25 - remu s6, s3, t1 - andi t0, a3, 147 - slli a2, a4, 25 - c.slli t5, 22 - c.nop - srl t1, tp, zero - c.addi16sp sp, -16 - slli a2, a4, 25 - c.addi16sp sp, -16 - add s4, a7, s6 - sub s0, t3, gp - c.sub s0, s1 - srli zero, a0, 13 - mulh s1, t4, s11 - slt a0, s5, s11 - srl t1, tp, zero - xor s11, zero, s7 - mulh s1, t4, s11 - rem a2, s2, s9 - sub s0, t3, gp - div s7, gp, a4 - sll s8, s0, s6 - c.xor a4, a5 - c.mv a2, a0 - c.add t3, t1 - slt a0, s5, s11 - srl t1, tp, zero - srli zero, a0, 13 - sltiu s3, tp, 300 - andi t0, a3, 147 - mulhu s4, a6, t3 - c.li s11, -1 - lui s3, 985951 - rem a2, s2, s9 - c.addi s9, -1 - c.lui a6, 24 - remu s6, s3, t1 - srai a4, a3, 0 - c.and a4, s1 - andi t0, a3, 147 - add s4, a7, s6 - c.nop - c.sub s0, s1 - or a4, a4, zero - remu s6, s3, t1 - xori t3, t1, -721 - addi gp, s8, -298 - c.nop - divu tp, s5, t4 - div s7, gp, a4 - or a4, a4, zero - c.addi4spn a2, sp, 528 - c.xor a4, a5 - c.add t3, t1 - c.or a0, a2 - add s4, a7, s6 - c.and a4, s1 - or a4, a4, zero - srl t1, tp, zero - sltu s3, a6, a4 - slt a0, s5, s11 - nop - srli zero, a0, 13 - nop - c.andi s1, 31 - c.xor a4, a5 - c.xor a4, a5 - mulhu s4, a6, t3 - mulhsu tp, t5, a6 - andi t0, a3, 147 - srli zero, a0, 13 - mulhu s4, a6, t3 - sll s8, s0, s6 - c.or a0, a2 - sltu s3, a6, a4 - divu tp, s5, t4 - mulh s1, t4, s11 - sltiu s3, tp, 300 - c.or a0, a2 - auipc s1, 11691 - mulhu s4, a6, t3 - srai a4, a3, 0 - c.srai s1, 28 - c.slli t5, 22 - add s4, a7, s6 - div s7, gp, a4 - c.sub s0, s1 - or a4, a4, zero - mulh s1, t4, s11 - sra s9, s4, t5 - c.mv a2, a0 - srl t1, tp, zero - c.srli a4, 9 - sub s0, t3, gp - or a4, a4, zero - sra s9, s4, t5 - xor s11, zero, s7 - andi t0, a3, 147 - c.slli t5, 22 - mul tp, s2, t5 - lui s3, 985951 - c.addi s9, -1 - c.mv a2, a0 - slli a2, a4, 25 - c.xor a4, a5 - c.srai s1, 28 - addi gp, s8, -298 - sub s0, t3, gp - sltiu s3, tp, 300 - slt a0, s5, s11 - c.slli t5, 22 - xor s11, zero, s7 - sub s0, t3, gp - and s6, t2, a4 - xor s11, zero, s7 - lui s3, 985951 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - or a4, a4, zero - c.addi16sp sp, -16 - c.slli t5, 22 - slti tp, a1, -167 - lui s3, 985951 - mulh s1, t4, s11 - slti tp, a1, -167 - sub s0, t3, gp - c.srli a4, 9 - c.srai s1, 28 - and s6, t2, a4 - divu tp, s5, t4 - slli a2, a4, 25 - auipc s1, 11691 - remu s6, s3, t1 - sub s0, t3, gp - srli zero, a0, 13 - c.addi16sp sp, -16 - c.mv a2, a0 - c.addi4spn a2, sp, 528 - or a4, a4, zero - xori t3, t1, -721 - addi gp, s8, -298 - divu tp, s5, t4 - add s4, a7, s6 - mulh s1, t4, s11 - nop - andi t0, a3, 147 - auipc s1, 11691 - sll s8, s0, s6 - c.add t3, t1 - c.srai s1, 28 - nop - c.sub s0, s1 - li ra, 0xe770c156 #start riscv_int_numeric_corner_stream_18 - li s2, 0xd7ebdf2c - li t0, 0xffffffff - li a0, 0x0 - li s11, 0x0 - li a6, 0xffffffff - li s10, 0xffffffff - li s5, 0xffffffff - li s3, 0xffffffff - li s1, 0x461213ee - nop - mulhu ra, a6, s5 - divu ra, a0, a6 - nop - rem s5, s1, a0 - mulhsu t0, s5, ra - add s11, a0, s10 - add s11, a0, s10 - mulh t0, t0, t0 - divu ra, a0, a6 - sub ra, a0, s10 - nop - addi s1, s3, -40 - lui s3, 985951 - divu ra, a0, a6 - sub ra, a0, s10 - nop - add s11, a0, s10 - auipc s1, 11691 - div t0, s1, t0 - sub ra, a0, s10 - remu s10, a0, s2 - mul s2, s3, s1 - sub ra, a0, s10 - auipc s1, 11691 - sub ra, a0, s10 #end riscv_int_numeric_corner_stream_18 - c.sub s0, s1 - srl t1, tp, zero - andi t0, a3, 147 - c.addi16sp sp, -16 - div s7, gp, a4 - div s7, gp, a4 - rem a2, s2, s9 - c.addi s9, -1 - c.srli a4, 9 - c.srli a4, 9 - or a4, a4, zero - c.mv a2, a0 - c.addi s9, -1 - c.slli t5, 22 - slli a2, a4, 25 - c.and a4, s1 - c.andi s1, 31 - c.nop - c.or a0, a2 - slli a2, a4, 25 - c.andi s1, 31 - sltu s3, a6, a4 - sltu s3, a6, a4 - c.addi4spn a2, sp, 528 - nop - slti tp, a1, -167 - c.xor a4, a5 - remu s6, s3, t1 - remu s6, s3, t1 - slt a0, s5, s11 - lui s3, 985951 - andi t0, a3, 147 - lui s3, 985951 - mulhu s4, a6, t3 - c.srli a4, 9 - c.addi s9, -1 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - c.xor a4, a5 - remu s6, s3, t1 - remu s6, s3, t1 - add s4, a7, s6 - sra s9, s4, t5 - c.srai s1, 28 - c.nop - remu s6, s3, t1 - srl t1, tp, zero - ori tp, a0, -848 - c.nop - c.addi s9, -1 - c.sub s0, s1 - c.srai s1, 28 - or a4, a4, zero - rem a2, s2, s9 - c.and a4, s1 - srli zero, a0, 13 - c.and a4, s1 - auipc s1, 11691 - srai a4, a3, 0 - c.nop - xor s11, zero, s7 - mulhu s4, a6, t3 - c.slli t5, 22 - c.srli a4, 9 - slti tp, a1, -167 - c.lui a6, 24 - sub s0, t3, gp - addi gp, s8, -298 - srli zero, a0, 13 - srl t1, tp, zero - xor s11, zero, s7 - c.mv a2, a0 - ori tp, a0, -848 - c.srli a4, 9 - or a4, a4, zero - xori t3, t1, -721 - rem a2, s2, s9 - c.add t3, t1 - mulh s1, t4, s11 - c.addi s9, -1 - rem a2, s2, s9 - and s6, t2, a4 - srl t1, tp, zero - c.add t3, t1 - c.srli a4, 9 - srli zero, a0, 13 - slti tp, a1, -167 - mulhsu tp, t5, a6 - auipc s1, 11691 - and s6, t2, a4 - c.sub s0, s1 - srl t1, tp, zero - ori tp, a0, -848 - mulh s1, t4, s11 - c.li s11, -1 - c.li s11, -1 - slti tp, a1, -167 - div s7, gp, a4 - sll s8, s0, s6 - lui s3, 985951 - mulhu s4, a6, t3 - sll s8, s0, s6 - andi t0, a3, 147 - mulhsu tp, t5, a6 - sltu s3, a6, a4 - and s6, t2, a4 - auipc s1, 11691 - srai a4, a3, 0 - rem a2, s2, s9 - nop - c.sub s0, s1 - srl t1, tp, zero - add s4, a7, s6 - c.lui a6, 24 - mul tp, s2, t5 - mulhu s4, a6, t3 - c.addi4spn a2, sp, 528 - c.sub s0, s1 - or a4, a4, zero - c.sub s0, s1 - xori t3, t1, -721 - add s4, a7, s6 - c.slli t5, 22 - ori tp, a0, -848 - c.addi s9, -1 - auipc s1, 11691 - slli a2, a4, 25 - c.lui a6, 24 - slli a2, a4, 25 - srl t1, tp, zero - sub s0, t3, gp - ori tp, a0, -848 - slt a0, s5, s11 - nop - sltu s3, a6, a4 - mulhu s4, a6, t3 - c.srai s1, 28 - mul tp, s2, t5 - nop - c.addi16sp sp, -16 - c.and a4, s1 - ori tp, a0, -848 - slli a2, a4, 25 - c.srai s1, 28 - xor s11, zero, s7 - c.srli a4, 9 - srai a4, a3, 0 - mulhsu tp, t5, a6 - addi gp, s8, -298 - srli zero, a0, 13 - c.addi4spn a2, sp, 528 - c.sub s0, s1 - sltu s3, a6, a4 - xori t3, t1, -721 - sltu s3, a6, a4 - c.li s11, -1 - c.nop - c.srai s1, 28 - div s7, gp, a4 - c.addi16sp sp, -16 - c.mv a2, a0 - c.and a4, s1 - sltu s3, a6, a4 - c.srai s1, 28 - xori t3, t1, -721 - sra s9, s4, t5 - c.addi s9, -1 - addi gp, s8, -298 - c.nop - div s7, gp, a4 - nop - srli zero, a0, 13 - ori tp, a0, -848 - add s4, a7, s6 - c.slli t5, 22 - auipc s1, 11691 - mul tp, s2, t5 - c.slli t5, 22 - slt a0, s5, s11 - sll s8, s0, s6 - and s6, t2, a4 - add s4, a7, s6 - mul tp, s2, t5 - mulhu s4, a6, t3 - slli a2, a4, 25 - c.mv a2, a0 - sra s9, s4, t5 - c.addi4spn a2, sp, 528 - srl t1, tp, zero - c.addi16sp sp, -16 - c.addi16sp sp, -16 - andi t0, a3, 147 - remu s6, s3, t1 - mul tp, s2, t5 - c.slli t5, 22 - c.addi16sp sp, -16 - sll s8, s0, s6 - slti tp, a1, -167 - auipc s1, 11691 - mul tp, s2, t5 - nop - c.add t3, t1 - or a4, a4, zero - sltu s3, a6, a4 - remu s6, s3, t1 - remu s6, s3, t1 - auipc s1, 11691 - remu s6, s3, t1 - andi t0, a3, 147 - or a4, a4, zero - srl t1, tp, zero - c.slli t5, 22 - remu s6, s3, t1 - c.and a4, s1 - sltu s3, a6, a4 - sub s0, t3, gp - c.addi s9, -1 - ori tp, a0, -848 - addi gp, s8, -298 - mulh s1, t4, s11 - c.mv a2, a0 - auipc s1, 11691 - c.and a4, s1 - c.slli t5, 22 - c.xor a4, a5 - sra s9, s4, t5 - c.srai s1, 28 - add s4, a7, s6 - auipc s1, 11691 - mul tp, s2, t5 - srai a4, a3, 0 - srai a4, a3, 0 - c.add t3, t1 - c.andi s1, 31 - sltu s3, a6, a4 - c.xor a4, a5 - c.lui a6, 24 - srl t1, tp, zero - xori t3, t1, -721 - lui s3, 985951 - div s7, gp, a4 - srli zero, a0, 13 - divu tp, s5, t4 - add s4, a7, s6 - srli zero, a0, 13 - c.srai s1, 28 - xori t3, t1, -721 - sltu s3, a6, a4 - c.lui a6, 24 - sub s0, t3, gp - c.or a0, a2 - mulhsu tp, t5, a6 - c.li s11, -1 - add s4, a7, s6 - slt a0, s5, s11 - andi t0, a3, 147 - mulhsu tp, t5, a6 - and s6, t2, a4 - c.lui a6, 24 - c.addi16sp sp, -16 - remu s6, s3, t1 - sll s8, s0, s6 - c.addi16sp sp, -16 - c.lui a6, 24 - c.li s11, -1 - c.sub s0, s1 - sra s9, s4, t5 - srli zero, a0, 13 - slli a2, a4, 25 - divu tp, s5, t4 - mulh s1, t4, s11 - c.addi16sp sp, -16 - auipc s1, 11691 - c.nop - slti tp, a1, -167 - add s4, a7, s6 - xori t3, t1, -721 - c.addi4spn a2, sp, 528 - mulh s1, t4, s11 - xor s11, zero, s7 - slti tp, a1, -167 - c.srai s1, 28 - c.srli a4, 9 - and s6, t2, a4 - auipc s1, 11691 - or a4, a4, zero - remu s6, s3, t1 - div s7, gp, a4 - c.xor a4, a5 - div s7, gp, a4 - c.and a4, s1 - slli a2, a4, 25 - c.addi s9, -1 - c.xor a4, a5 - c.slli t5, 22 - addi gp, s8, -298 - c.xor a4, a5 - and s6, t2, a4 - c.srli a4, 9 - srl t1, tp, zero - mulhu s4, a6, t3 - addi gp, s8, -298 - c.li s11, -1 - sub s0, t3, gp - c.addi4spn a2, sp, 528 - and s6, t2, a4 - xori t3, t1, -721 - c.srli a4, 9 - slt a0, s5, s11 - addi gp, s8, -298 - slt a0, s5, s11 - c.slli t5, 22 - xori t3, t1, -721 - srli zero, a0, 13 - c.andi s1, 31 - mulhu s4, a6, t3 - sltiu s3, tp, 300 - slli a2, a4, 25 - mulhsu tp, t5, a6 - c.addi4spn a2, sp, 528 - divu tp, s5, t4 - xor s11, zero, s7 - c.addi16sp sp, -16 - c.andi s1, 31 - divu tp, s5, t4 - c.nop - slli a2, a4, 25 - srl t1, tp, zero - div s7, gp, a4 - slli a2, a4, 25 - add s4, a7, s6 - c.or a0, a2 - lui s3, 985951 - nop - c.slli t5, 22 - c.or a0, a2 - or a4, a4, zero - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - c.srai s1, 28 - div s7, gp, a4 - divu tp, s5, t4 - c.addi4spn a2, sp, 528 - and s6, t2, a4 - mulhsu tp, t5, a6 - or a4, a4, zero - mulh s1, t4, s11 - rem a2, s2, s9 - c.addi4spn a2, sp, 528 - c.srai s1, 28 - remu s6, s3, t1 - rem a2, s2, s9 - addi gp, s8, -298 - c.sub s0, s1 - andi t0, a3, 147 - mulhu s4, a6, t3 - c.slli t5, 22 - c.li s11, -1 - divu tp, s5, t4 - add s4, a7, s6 - c.addi4spn a2, sp, 528 - auipc s1, 11691 - and s6, t2, a4 - c.addi s9, -1 - mulh s1, t4, s11 - and s6, t2, a4 - xor s11, zero, s7 - sltu s3, a6, a4 - rem a2, s2, s9 - c.slli t5, 22 - c.sub s0, s1 - c.addi4spn a2, sp, 528 - c.mv a2, a0 - mulhsu tp, t5, a6 - c.add t3, t1 - sltiu s3, tp, 300 - c.add t3, t1 - c.andi s1, 31 - srli zero, a0, 13 - c.li s11, -1 - div s7, gp, a4 - sra s9, s4, t5 - remu s6, s3, t1 - sub s0, t3, gp - c.srai s1, 28 - c.and a4, s1 - c.mv a2, a0 - c.srli a4, 9 - c.srli a4, 9 - c.sub s0, s1 - add s4, a7, s6 - c.nop - c.mv a2, a0 - or a4, a4, zero - c.and a4, s1 - c.lui a6, 24 - c.addi s9, -1 - sltu s3, a6, a4 - c.or a0, a2 - divu tp, s5, t4 - sltiu s3, tp, 300 - slli a2, a4, 25 - rem a2, s2, s9 - addi gp, s8, -298 - and s6, t2, a4 - xori t3, t1, -721 - sll s8, s0, s6 - and s6, t2, a4 - slli a2, a4, 25 - c.srli a4, 9 - c.xor a4, a5 - and s6, t2, a4 - ori tp, a0, -848 - ori tp, a0, -848 - c.sub s0, s1 - andi t0, a3, 147 - c.or a0, a2 - srli zero, a0, 13 - c.and a4, s1 - c.srli a4, 9 - c.addi4spn a2, sp, 528 - c.andi s1, 31 - c.li s11, -1 - c.mv a2, a0 - xor s11, zero, s7 - and s6, t2, a4 - c.addi s9, -1 - c.srli a4, 9 - c.addi4spn a2, sp, 528 - mulhu s4, a6, t3 - c.or a0, a2 - c.srai s1, 28 - c.srli a4, 9 - c.xor a4, a5 - c.li s11, -1 - auipc s1, 11691 - and s6, t2, a4 - lui s3, 985951 - c.slli t5, 22 - xori t3, t1, -721 - ori tp, a0, -848 - remu s6, s3, t1 - sra s9, s4, t5 - c.addi s9, -1 - c.or a0, a2 - sub s0, t3, gp - rem a2, s2, s9 - c.srli a4, 9 - c.nop - c.sub s0, s1 - rem a2, s2, s9 - c.lui a6, 24 - lui s3, 985951 - mulhsu tp, t5, a6 - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - srai a4, a3, 0 - sltu s3, a6, a4 - divu tp, s5, t4 - mulhsu tp, t5, a6 - c.xor a4, a5 - remu s6, s3, t1 - sra s9, s4, t5 - c.srli a4, 9 - slli a2, a4, 25 - c.or a0, a2 - xori t3, t1, -721 - c.or a0, a2 - divu tp, s5, t4 - or a4, a4, zero - c.lui a6, 24 - mul tp, s2, t5 - rem a2, s2, s9 - c.addi16sp sp, -16 - slt a0, s5, s11 - c.srli a4, 9 - c.addi16sp sp, -16 - and s6, t2, a4 - sub s0, t3, gp - c.srai s1, 28 - c.addi s9, -1 - sltu s3, a6, a4 - c.add t3, t1 - c.slli t5, 22 - mulhu s4, a6, t3 - srai a4, a3, 0 - srl t1, tp, zero - ori tp, a0, -848 - ori tp, a0, -848 - srai a4, a3, 0 - mulhsu tp, t5, a6 - sltiu s3, tp, 300 - c.sub s0, s1 - c.li s11, -1 - slt a0, s5, s11 - c.addi4spn a2, sp, 528 - c.and a4, s1 - c.addi16sp sp, -16 - sll s8, s0, s6 - sltiu s3, tp, 300 - mulhsu tp, t5, a6 - mul tp, s2, t5 - c.sub s0, s1 - c.mv a2, a0 - c.srli a4, 9 - andi t0, a3, 147 - c.andi s1, 31 - xor s11, zero, s7 - slli a2, a4, 25 - c.mv a2, a0 - nop - mulh s1, t4, s11 - c.and a4, s1 - auipc s1, 11691 - sltu s3, a6, a4 - or a4, a4, zero - andi t0, a3, 147 - sub s0, t3, gp - c.addi4spn a2, sp, 528 - add s4, a7, s6 - xori t3, t1, -721 - c.srli a4, 9 - mulhsu tp, t5, a6 - addi gp, s8, -298 - c.srli a4, 9 - divu tp, s5, t4 - rem a2, s2, s9 - div s7, gp, a4 - mul tp, s2, t5 - ori tp, a0, -848 - c.addi16sp sp, -16 - c.nop - div s7, gp, a4 - c.srli a4, 9 - c.andi s1, 31 - divu tp, s5, t4 - slli a2, a4, 25 - li s10, 0x3b7c3fe7 #start riscv_int_numeric_corner_stream_37 - li ra, 0x7aa9128f - li t1, 0xffffffff - li t0, 0x0 - li s4, 0x0 - li s0, 0x0 - li s7, 0x0 - li a2, 0xd2381f93 - li s6, 0x4a083316 - li a4, 0xffffffff - auipc s0, 11691 - nop - add s4, s7, a4 - div s4, s4, t0 - mulhu t0, s6, s7 - add s4, s7, a4 - rem s4, ra, a4 - nop - addi ra, s10, -40 - nop - rem s4, ra, a4 - mulh s10, s7, a2 - sub s10, ra, s10 - lui s7, 985951 - mulhsu a4, a4, ra - divu s0, t1, s10 - nop - nop - nop - nop - nop - mulhu t0, s6, s7 - rem s4, ra, a4 - rem s4, ra, a4 - nop - mul t1, s4, a2 - lui s7, 985951 - rem s4, ra, a4 - remu t0, a2, a2 #end riscv_int_numeric_corner_stream_37 - c.srli a4, 9 - c.addi16sp sp, -16 - or a4, a4, zero - lui s3, 985951 - sra s9, s4, t5 - mulhu s4, a6, t3 - srai a4, a3, 0 - c.andi s1, 31 - c.add t3, t1 - c.nop - srai a4, a3, 0 - divu tp, s5, t4 - mulhsu tp, t5, a6 - slti tp, a1, -167 - add s4, a7, s6 - c.nop - ori tp, a0, -848 - sra s9, s4, t5 - slt a0, s5, s11 - srli zero, a0, 13 - c.sub s0, s1 - rem a2, s2, s9 - c.li s11, -1 - sltiu s3, tp, 300 - and s6, t2, a4 - xori t3, t1, -721 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - ori tp, a0, -848 - c.lui a6, 24 - xori t3, t1, -721 - auipc s1, 11691 - c.lui a6, 24 - sub s0, t3, gp - mulhsu tp, t5, a6 - c.and a4, s1 - c.nop - auipc s1, 11691 - mulhsu tp, t5, a6 - c.slli t5, 22 - c.add t3, t1 - sub s0, t3, gp - mulhsu tp, t5, a6 - add s4, a7, s6 - and s6, t2, a4 - div s7, gp, a4 - ori tp, a0, -848 - c.srli a4, 9 - add s4, a7, s6 - lui s3, 985951 - andi t0, a3, 147 - ori tp, a0, -848 - srai a4, a3, 0 - c.xor a4, a5 - or a4, a4, zero - srli zero, a0, 13 - c.li s11, -1 - div s7, gp, a4 - c.li s11, -1 - sub s0, t3, gp - nop - c.sub s0, s1 - c.xor a4, a5 - divu tp, s5, t4 - div s7, gp, a4 - mulhu s4, a6, t3 - add s4, a7, s6 - c.srli a4, 9 - andi t0, a3, 147 - c.lui a6, 24 - slti tp, a1, -167 - xori t3, t1, -721 - sll s8, s0, s6 - sll s8, s0, s6 - c.srli a4, 9 - c.xor a4, a5 - c.srai s1, 28 - c.srli a4, 9 - c.sub s0, s1 - addi gp, s8, -298 - srli zero, a0, 13 - mul tp, s2, t5 - sll s8, s0, s6 - c.and a4, s1 - addi gp, s8, -298 - c.xor a4, a5 - slt a0, s5, s11 - c.and a4, s1 - c.li s11, -1 - remu s6, s3, t1 - c.xor a4, a5 - c.or a0, a2 - rem a2, s2, s9 - c.addi16sp sp, -16 - c.addi16sp sp, -16 - c.lui a6, 24 - c.and a4, s1 - c.srai s1, 28 - lui s3, 985951 - mulhsu tp, t5, a6 - xor s11, zero, s7 - sub s0, t3, gp - ori tp, a0, -848 - lui s3, 985951 - lui s3, 985951 - sub s0, t3, gp - c.or a0, a2 - sltiu s3, tp, 300 - c.and a4, s1 - mulhsu tp, t5, a6 - srai a4, a3, 0 - c.nop - rem a2, s2, s9 - mulhsu tp, t5, a6 - and s6, t2, a4 - and s6, t2, a4 - slt a0, s5, s11 - c.addi16sp sp, -16 - lui s3, 985951 - c.srai s1, 28 - ori tp, a0, -848 - rem a2, s2, s9 - c.slli t5, 22 - sltiu s3, tp, 300 - c.srai s1, 28 - c.addi16sp sp, -16 - c.srai s1, 28 - slti tp, a1, -167 - add s4, a7, s6 - mulhu s4, a6, t3 - add s4, a7, s6 - c.nop - srl t1, tp, zero - rem a2, s2, s9 - c.addi s9, -1 - c.mv a2, a0 - c.add t3, t1 - mulhu s4, a6, t3 - andi t0, a3, 147 - srli zero, a0, 13 - mulhsu tp, t5, a6 - addi gp, s8, -298 - c.add t3, t1 - c.add t3, t1 - divu tp, s5, t4 - lui s3, 985951 - remu s6, s3, t1 - rem a2, s2, s9 - mulhu s4, a6, t3 - c.srli a4, 9 - srai a4, a3, 0 - c.srai s1, 28 - div s7, gp, a4 - c.mv a2, a0 - xor s11, zero, s7 - c.sub s0, s1 - c.xor a4, a5 - c.xor a4, a5 - slli a2, a4, 25 - srai a4, a3, 0 - slti tp, a1, -167 - c.sub s0, s1 - and s6, t2, a4 - nop - slti tp, a1, -167 - sra s9, s4, t5 - mulh s1, t4, s11 - c.addi16sp sp, -16 - srl t1, tp, zero - c.slli t5, 22 - sll s8, s0, s6 - sub s0, t3, gp - sll s8, s0, s6 - sra s9, s4, t5 - c.lui a6, 24 - mulhu s4, a6, t3 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - and s6, t2, a4 - nop - slt a0, s5, s11 - c.srai s1, 28 - mul tp, s2, t5 - c.srli a4, 9 - c.lui a6, 24 - c.slli t5, 22 - c.add t3, t1 - sltu s3, a6, a4 - c.srli a4, 9 - c.srli a4, 9 - divu tp, s5, t4 - c.slli t5, 22 - c.xor a4, a5 - c.sub s0, s1 - and s6, t2, a4 - sra s9, s4, t5 - c.addi s9, -1 - c.srli a4, 9 - rem a2, s2, s9 - andi t0, a3, 147 - srai a4, a3, 0 - rem a2, s2, s9 - sltu s3, a6, a4 - c.srai s1, 28 - addi gp, s8, -298 - or a4, a4, zero - srai a4, a3, 0 - c.nop - rem a2, s2, s9 - remu s6, s3, t1 - slt a0, s5, s11 - c.andi s1, 31 - ori tp, a0, -848 - add s4, a7, s6 - xor s11, zero, s7 - c.srli a4, 9 - sltu s3, a6, a4 - mulhu s4, a6, t3 - nop - c.srai s1, 28 - sltu s3, a6, a4 - divu tp, s5, t4 - slti tp, a1, -167 - slti tp, a1, -167 - rem a2, s2, s9 - c.srli a4, 9 - divu tp, s5, t4 - c.mv a2, a0 - nop - slt a0, s5, s11 - c.nop - mulhsu tp, t5, a6 - c.addi s9, -1 - sra s9, s4, t5 - sltiu s3, tp, 300 - c.srai s1, 28 - auipc s1, 11691 - sltiu s3, tp, 300 - c.lui a6, 24 - addi gp, s8, -298 - c.addi16sp sp, -16 - sra s9, s4, t5 - srai a4, a3, 0 - ori tp, a0, -848 - c.xor a4, a5 - sltu s3, a6, a4 - c.or a0, a2 - and s6, t2, a4 - mulhsu tp, t5, a6 - c.nop - slt a0, s5, s11 - mul tp, s2, t5 - c.nop - c.and a4, s1 - sltiu s3, tp, 300 - divu tp, s5, t4 - c.andi s1, 31 - c.andi s1, 31 - c.slli t5, 22 - slt a0, s5, s11 - mulhsu tp, t5, a6 - and s6, t2, a4 - rem a2, s2, s9 - sub s0, t3, gp - c.li s11, -1 - nop - c.srli a4, 9 - xor s11, zero, s7 - sltiu s3, tp, 300 - sll s8, s0, s6 - c.addi16sp sp, -16 - sub s0, t3, gp - c.li s11, -1 - and s6, t2, a4 - c.and a4, s1 - remu s6, s3, t1 - c.xor a4, a5 - mulh s1, t4, s11 - c.lui a6, 24 - srl t1, tp, zero - rem a2, s2, s9 - c.addi4spn a2, sp, 528 - c.lui a6, 24 - slt a0, s5, s11 - slti tp, a1, -167 - and s6, t2, a4 - c.sub s0, s1 - sltiu s3, tp, 300 - srl t1, tp, zero - andi t0, a3, 147 - andi t0, a3, 147 - c.and a4, s1 - auipc s1, 11691 - divu tp, s5, t4 - auipc s1, 11691 - addi gp, s8, -298 - c.addi4spn a2, sp, 528 - slli a2, a4, 25 - c.addi4spn a2, sp, 528 - c.or a0, a2 - c.andi s1, 31 - lui s3, 985951 - srl t1, tp, zero - sll s8, s0, s6 - sltiu s3, tp, 300 - c.li s11, -1 - c.or a0, a2 - c.srai s1, 28 - auipc s1, 11691 - mulhsu tp, t5, a6 - and s6, t2, a4 - mulh s1, t4, s11 - sub s0, t3, gp - mulhu s4, a6, t3 - xor s11, zero, s7 - c.addi s9, -1 - add s4, a7, s6 - c.li s11, -1 - remu s6, s3, t1 - addi gp, s8, -298 - sub s0, t3, gp - srl t1, tp, zero - c.sub s0, s1 - c.mv a2, a0 - c.addi4spn a2, sp, 528 - add s4, a7, s6 - srai a4, a3, 0 - srl t1, tp, zero - c.mv a2, a0 - xori t3, t1, -721 - nop - lui s3, 985951 - andi t0, a3, 147 - xor s11, zero, s7 - srai a4, a3, 0 - c.srli a4, 9 - c.addi s9, -1 - and s6, t2, a4 - c.addi s9, -1 - c.add t3, t1 - sra s9, s4, t5 - c.nop - sltiu s3, tp, 300 - xori t3, t1, -721 - slli a2, a4, 25 - divu tp, s5, t4 - srli zero, a0, 13 - c.add t3, t1 - rem a2, s2, s9 - divu tp, s5, t4 - c.lui a6, 24 - sll s8, s0, s6 - nop - slli a2, a4, 25 - divu tp, s5, t4 - remu s6, s3, t1 - c.addi4spn a2, sp, 528 - ori tp, a0, -848 - or a4, a4, zero - c.xor a4, a5 - c.addi4spn a2, sp, 528 - sltiu s3, tp, 300 - addi gp, s8, -298 - nop - srai a4, a3, 0 - addi gp, s8, -298 - sltiu s3, tp, 300 - lui s3, 985951 - slti tp, a1, -167 - c.li s11, -1 - sltu s3, a6, a4 - remu s6, s3, t1 - or a4, a4, zero - rem a2, s2, s9 - slli a2, a4, 25 - c.addi16sp sp, -16 - c.xor a4, a5 - slti tp, a1, -167 - c.addi4spn a2, sp, 528 - or a4, a4, zero - div s7, gp, a4 - sltu s3, a6, a4 - lui s3, 985951 - slli a2, a4, 25 - c.slli t5, 22 - c.addi4spn a2, sp, 528 - nop - sub s0, t3, gp - ori tp, a0, -848 - c.li s11, -1 - srli zero, a0, 13 - slti tp, a1, -167 - srai a4, a3, 0 - c.lui a6, 24 - slti tp, a1, -167 - c.mv a2, a0 - c.sub s0, s1 - mulh s1, t4, s11 - c.addi4spn a2, sp, 528 - mulhsu tp, t5, a6 - lui s3, 985951 - mul tp, s2, t5 - c.lui a6, 24 - nop - c.sub s0, s1 - div s7, gp, a4 - c.addi s9, -1 - remu s6, s3, t1 - c.andi s1, 31 - c.and a4, s1 - c.or a0, a2 - lui s3, 985951 - mulhsu tp, t5, a6 - div s7, gp, a4 - c.slli t5, 22 - sltu s3, a6, a4 - c.and a4, s1 - c.or a0, a2 - mulh s1, t4, s11 - c.addi s9, -1 - ori tp, a0, -848 - divu tp, s5, t4 - or a4, a4, zero - mulh s1, t4, s11 - lui s3, 985951 - c.or a0, a2 - sll s8, s0, s6 - c.add t3, t1 - ori tp, a0, -848 - ori tp, a0, -848 - sltu s3, a6, a4 - nop - mul tp, s2, t5 - c.xor a4, a5 - sub s0, t3, gp - mulhu s4, a6, t3 - c.andi s1, 31 - lui s3, 985951 - c.slli t5, 22 - c.addi4spn a2, sp, 528 - c.sub s0, s1 - div s7, gp, a4 - slli a2, a4, 25 - c.nop - add s4, a7, s6 - c.slli t5, 22 - c.addi4spn a2, sp, 528 - c.or a0, a2 - div s7, gp, a4 - andi t0, a3, 147 - c.lui a6, 24 - andi t0, a3, 147 - c.lui a6, 24 - or a4, a4, zero - auipc s1, 11691 - sll s8, s0, s6 - nop - c.addi s9, -1 - xori t3, t1, -721 - slt a0, s5, s11 - remu s6, s3, t1 - sub s0, t3, gp - srl t1, tp, zero - sltu s3, a6, a4 - c.slli t5, 22 - c.mv a2, a0 - sra s9, s4, t5 - sra s9, s4, t5 - sub s0, t3, gp - slli a2, a4, 25 - c.srai s1, 28 - addi gp, s8, -298 - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - mul tp, s2, t5 - sub s0, t3, gp - sltiu s3, tp, 300 - c.nop - c.srai s1, 28 - c.addi16sp sp, -16 - and s6, t2, a4 - c.nop - c.addi s9, -1 - auipc s1, 11691 - srli zero, a0, 13 - srl t1, tp, zero - srai a4, a3, 0 - sra s9, s4, t5 - slt a0, s5, s11 - mulhu s4, a6, t3 - rem a2, s2, s9 - nop - ori tp, a0, -848 - xor s11, zero, s7 - c.mv a2, a0 - slti tp, a1, -167 - addi gp, s8, -298 - c.srli a4, 9 - lui s3, 985951 - c.nop - sub s0, t3, gp - srl t1, tp, zero - c.or a0, a2 - div s7, gp, a4 - sll s8, s0, s6 - srai a4, a3, 0 - slt a0, s5, s11 - sra s9, s4, t5 - rem a2, s2, s9 - c.sub s0, s1 - rem a2, s2, s9 - sra s9, s4, t5 - c.srai s1, 28 - sub s0, t3, gp - c.or a0, a2 - mulh s1, t4, s11 - c.addi s9, -1 - addi gp, s8, -298 - c.slli t5, 22 - c.xor a4, a5 - c.sub s0, s1 - sltiu s3, tp, 300 - c.addi16sp sp, -16 - mulh s1, t4, s11 - mulhu s4, a6, t3 - c.add t3, t1 - c.or a0, a2 - addi gp, s8, -298 - sra s9, s4, t5 - sltiu s3, tp, 300 - c.add t3, t1 - c.lui a6, 24 - slti tp, a1, -167 - add s4, a7, s6 - mulhsu tp, t5, a6 - c.sub s0, s1 - c.and a4, s1 - ori tp, a0, -848 - or a4, a4, zero - srai a4, a3, 0 - c.xor a4, a5 - c.li s11, -1 - mulh s1, t4, s11 - andi t0, a3, 147 - div s7, gp, a4 - c.addi s9, -1 - sltu s3, a6, a4 - ori tp, a0, -848 - andi t0, a3, 147 - srli zero, a0, 13 - c.lui a6, 24 - rem a2, s2, s9 - c.or a0, a2 - divu tp, s5, t4 - xor s11, zero, s7 - c.srli a4, 9 - auipc s1, 11691 - c.nop - mul tp, s2, t5 - div s7, gp, a4 - lui s3, 985951 - andi t0, a3, 147 - c.or a0, a2 - slt a0, s5, s11 - slt a0, s5, s11 - c.addi4spn a2, sp, 528 - mulhu s4, a6, t3 - c.addi16sp sp, -16 - sltiu s3, tp, 300 - andi t0, a3, 147 - xor s11, zero, s7 - lui s3, 985951 - c.lui a6, 24 - slt a0, s5, s11 - c.and a4, s1 - c.add t3, t1 - sltiu s3, tp, 300 - sltu s3, a6, a4 - divu tp, s5, t4 - div s7, gp, a4 - slli a2, a4, 25 - c.addi16sp sp, -16 - c.srai s1, 28 - mulhu s4, a6, t3 - srl t1, tp, zero - addi gp, s8, -298 - sub s0, t3, gp - c.addi s9, -1 - auipc s1, 11691 - c.lui a6, 24 - sra s9, s4, t5 - c.slli t5, 22 - srli zero, a0, 13 - sll s8, s0, s6 - remu s6, s3, t1 - addi gp, s8, -298 - nop - mulh s1, t4, s11 - slti tp, a1, -167 - srl t1, tp, zero - c.srai s1, 28 - or a4, a4, zero - c.add t3, t1 - nop - mulh s1, t4, s11 - mulh s1, t4, s11 - srl t1, tp, zero - mulh s1, t4, s11 - xori t3, t1, -721 - mulhu s4, a6, t3 - c.nop - c.andi s1, 31 - mul tp, s2, t5 - addi gp, s8, -298 - add s4, a7, s6 - slt a0, s5, s11 - xor s11, zero, s7 - div s7, gp, a4 - slli a2, a4, 25 - c.andi s1, 31 - or a4, a4, zero - c.and a4, s1 - c.srai s1, 28 - andi t0, a3, 147 - add s4, a7, s6 - sub s0, t3, gp - div s7, gp, a4 - mulhu s4, a6, t3 - c.srli a4, 9 - c.and a4, s1 - c.or a0, a2 - mulhsu tp, t5, a6 - c.andi s1, 31 - c.addi16sp sp, -16 - c.and a4, s1 - rem a2, s2, s9 - lui s3, 985951 - ori tp, a0, -848 - c.srli a4, 9 - c.srai s1, 28 - c.addi s9, -1 - c.add t3, t1 - auipc s1, 11691 - xori t3, t1, -721 - divu tp, s5, t4 - lui s3, 985951 - c.nop - c.srai s1, 28 - auipc s1, 11691 - srl t1, tp, zero - c.addi16sp sp, -16 - mul tp, s2, t5 - srl t1, tp, zero - c.nop - sltu s3, a6, a4 - div s7, gp, a4 - andi t0, a3, 147 - sra s9, s4, t5 - lui s3, 985951 - c.slli t5, 22 - sra s9, s4, t5 - srli zero, a0, 13 - auipc s1, 11691 - mul tp, s2, t5 - mul tp, s2, t5 - sltu s3, a6, a4 - c.mv a2, a0 - mulhsu tp, t5, a6 - divu tp, s5, t4 - c.addi s9, -1 - xori t3, t1, -721 - rem a2, s2, s9 - c.xor a4, a5 - mulh s1, t4, s11 - srai a4, a3, 0 - sra s9, s4, t5 - c.addi s9, -1 - c.mv a2, a0 - slti tp, a1, -167 - c.nop - mulh s1, t4, s11 - slli a2, a4, 25 - ori tp, a0, -848 - or a4, a4, zero - addi gp, s8, -298 - slt a0, s5, s11 - sll s8, s0, s6 - srli zero, a0, 13 - c.lui a6, 24 - srl t1, tp, zero - mulh s1, t4, s11 - c.srli a4, 9 - ori tp, a0, -848 - mul tp, s2, t5 - sra s9, s4, t5 - c.or a0, a2 - slti tp, a1, -167 - ori tp, a0, -848 - c.and a4, s1 - c.srli a4, 9 - c.srli a4, 9 - mulhu s4, a6, t3 - c.sub s0, s1 - lui s3, 985951 - slli a2, a4, 25 - sub s0, t3, gp - sll s8, s0, s6 - c.and a4, s1 - sltu s3, a6, a4 - rem a2, s2, s9 - srl t1, tp, zero - remu s6, s3, t1 - or a4, a4, zero - c.srai s1, 28 - slt a0, s5, s11 - sll s8, s0, s6 - xor s11, zero, s7 - rem a2, s2, s9 - auipc s1, 11691 - sub s0, t3, gp - mulhsu tp, t5, a6 - lui s3, 985951 - andi t0, a3, 147 - remu s6, s3, t1 - or a4, a4, zero - lui s3, 985951 - sra s9, s4, t5 - sltu s3, a6, a4 - srai a4, a3, 0 - c.srai s1, 28 - c.srai s1, 28 - lui s3, 985951 - c.li s11, -1 - rem a2, s2, s9 - c.sub s0, s1 - mul tp, s2, t5 - c.addi4spn a2, sp, 528 - divu tp, s5, t4 - sltu s3, a6, a4 - ori tp, a0, -848 - sltu s3, a6, a4 - c.or a0, a2 - c.lui a6, 24 - slt a0, s5, s11 - lui s3, 985951 - mul tp, s2, t5 - mulhsu tp, t5, a6 - c.srli a4, 9 - c.xor a4, a5 - add s4, a7, s6 - rem a2, s2, s9 - sltiu s3, tp, 300 - sra s9, s4, t5 - c.srai s1, 28 - c.andi s1, 31 - c.sub s0, s1 - and s6, t2, a4 - and s6, t2, a4 - c.lui a6, 24 - mulhsu tp, t5, a6 - and s6, t2, a4 - c.addi s9, -1 - remu s6, s3, t1 - c.li s11, -1 - xor s11, zero, s7 - c.and a4, s1 - sltu s3, a6, a4 - xor s11, zero, s7 - sltiu s3, tp, 300 - c.addi4spn a2, sp, 528 - div s7, gp, a4 - c.lui a6, 24 - andi t0, a3, 147 - c.slli t5, 22 - c.srli a4, 9 - divu tp, s5, t4 - slt a0, s5, s11 - auipc s1, 11691 - slti tp, a1, -167 - c.sub s0, s1 - c.xor a4, a5 - ori tp, a0, -848 - auipc s1, 11691 - xor s11, zero, s7 - rem a2, s2, s9 - c.srai s1, 28 - slti tp, a1, -167 - mulhu s4, a6, t3 - mulhsu tp, t5, a6 - c.mv a2, a0 - c.addi s9, -1 - c.addi16sp sp, -16 - c.slli t5, 22 - sltu s3, a6, a4 - sltiu s3, tp, 300 - add s4, a7, s6 - auipc s1, 11691 - add s4, a7, s6 - c.or a0, a2 - auipc s1, 11691 - srli zero, a0, 13 - sra s9, s4, t5 - srl t1, tp, zero - c.andi s1, 31 - and s6, t2, a4 - c.or a0, a2 - c.li s11, -1 - xor s11, zero, s7 - mul tp, s2, t5 - c.and a4, s1 - div s7, gp, a4 - div s7, gp, a4 - lui s3, 985951 - or a4, a4, zero - add s4, a7, s6 - auipc s1, 11691 - c.andi s1, 31 - c.mv a2, a0 - sll s8, s0, s6 - div s7, gp, a4 - sltu s3, a6, a4 - lui s3, 985951 - slti tp, a1, -167 - or a4, a4, zero - slti tp, a1, -167 - slt a0, s5, s11 - c.andi s1, 31 - xor s11, zero, s7 - divu tp, s5, t4 - div s7, gp, a4 - lui s3, 985951 - c.add t3, t1 - c.srli a4, 9 - mulhsu tp, t5, a6 - remu s6, s3, t1 - sll s8, s0, s6 - srl t1, tp, zero - mulh s1, t4, s11 - slti tp, a1, -167 - c.srai s1, 28 - c.add t3, t1 - addi gp, s8, -298 - xori t3, t1, -721 - c.srli a4, 9 - sltu s3, a6, a4 - c.slli t5, 22 - c.sub s0, s1 - remu s6, s3, t1 - c.and a4, s1 - srai a4, a3, 0 - srai a4, a3, 0 - mulhu s4, a6, t3 - c.srai s1, 28 - add s4, a7, s6 - and s6, t2, a4 - srli zero, a0, 13 - xor s11, zero, s7 - sltu s3, a6, a4 - xor s11, zero, s7 - remu s6, s3, t1 - srli zero, a0, 13 - sub s0, t3, gp - c.or a0, a2 - sltu s3, a6, a4 - slli a2, a4, 25 - c.and a4, s1 - c.mv a2, a0 - sll s8, s0, s6 - xor s11, zero, s7 - mul tp, s2, t5 - sra s9, s4, t5 - sub s0, t3, gp - sll s8, s0, s6 - divu tp, s5, t4 - srli zero, a0, 13 - rem a2, s2, s9 - c.lui a6, 24 - mulhsu tp, t5, a6 - c.srai s1, 28 - and s6, t2, a4 - mulhu s4, a6, t3 - srli zero, a0, 13 - c.srli a4, 9 - c.addi4spn a2, sp, 528 - c.slli t5, 22 - c.mv a2, a0 - c.sub s0, s1 - sub s0, t3, gp - c.add t3, t1 - srli zero, a0, 13 - c.mv a2, a0 - c.li s11, -1 - div s7, gp, a4 - divu tp, s5, t4 - c.or a0, a2 - mul tp, s2, t5 - remu s6, s3, t1 - c.sub s0, s1 - slli a2, a4, 25 - c.srai s1, 28 - c.xor a4, a5 - nop - xor s11, zero, s7 - or a4, a4, zero - srl t1, tp, zero - mul tp, s2, t5 - nop - add s4, a7, s6 - srli zero, a0, 13 - srl t1, tp, zero - sub s0, t3, gp - and s6, t2, a4 - c.andi s1, 31 - xori t3, t1, -721 - mulhsu tp, t5, a6 - xori t3, t1, -721 - c.add t3, t1 - sra s9, s4, t5 - c.xor a4, a5 - auipc s1, 11691 - mulh s1, t4, s11 - c.andi s1, 31 - c.addi16sp sp, -16 - mulhu s4, a6, t3 - c.srli a4, 9 - add s4, a7, s6 - mulh s1, t4, s11 - c.nop - c.srai s1, 28 - rem a2, s2, s9 - srai a4, a3, 0 - c.lui a6, 24 - or a4, a4, zero - sub s0, t3, gp - add s4, a7, s6 - sll s8, s0, s6 - xor s11, zero, s7 - c.add t3, t1 - c.xor a4, a5 - c.slli t5, 22 - slti tp, a1, -167 - c.addi s9, -1 - mulh s1, t4, s11 - srli zero, a0, 13 - addi gp, s8, -298 - sub s0, t3, gp - and s6, t2, a4 - div s7, gp, a4 - c.addi16sp sp, -16 - sltiu s3, tp, 300 - xor s11, zero, s7 - xor s11, zero, s7 - andi t0, a3, 147 - sltiu s3, tp, 300 - sltiu s3, tp, 300 - c.slli t5, 22 - srl t1, tp, zero - divu tp, s5, t4 - c.srai s1, 28 - sltu s3, a6, a4 - nop - div s7, gp, a4 - c.addi4spn a2, sp, 528 - c.addi16sp sp, -16 - c.addi s9, -1 - c.addi s9, -1 - c.srai s1, 28 - addi gp, s8, -298 - c.sub s0, s1 - slt a0, s5, s11 - ori tp, a0, -848 - remu s6, s3, t1 - c.sub s0, s1 - divu tp, s5, t4 - add s4, a7, s6 - and s6, t2, a4 - slli a2, a4, 25 - c.mv a2, a0 - lui s3, 985951 - c.lui a6, 24 - lui s3, 985951 - c.xor a4, a5 - xori t3, t1, -721 - c.andi s1, 31 - or a4, a4, zero - sra s9, s4, t5 - c.nop - andi t0, a3, 147 - ori tp, a0, -848 - remu s6, s3, t1 - c.addi s9, -1 - mul tp, s2, t5 - divu tp, s5, t4 - sltu s3, a6, a4 - c.nop - ori tp, a0, -848 - addi gp, s8, -298 - xori t3, t1, -721 - and s6, t2, a4 - sltiu s3, tp, 300 - sll s8, s0, s6 - c.addi16sp sp, -16 - sra s9, s4, t5 - srai a4, a3, 0 - c.or a0, a2 - srli zero, a0, 13 - c.srli a4, 9 - remu s6, s3, t1 - sltiu s3, tp, 300 - slt a0, s5, s11 - c.srli a4, 9 - c.slli t5, 22 - c.sub s0, s1 - slli a2, a4, 25 - sltu s3, a6, a4 - divu tp, s5, t4 - slli a2, a4, 25 - srai a4, a3, 0 - or a4, a4, zero - and s6, t2, a4 - slli a2, a4, 25 - slti tp, a1, -167 - c.slli t5, 22 - mulh s1, t4, s11 - andi t0, a3, 147 - or a4, a4, zero - andi t0, a3, 147 - sltu s3, a6, a4 - and s6, t2, a4 - or a4, a4, zero - xori t3, t1, -721 - c.srai s1, 28 - c.lui a6, 24 - mul tp, s2, t5 - sub s0, t3, gp - mul tp, s2, t5 - mulh s1, t4, s11 - lui s3, 985951 - lui s3, 985951 - andi t0, a3, 147 - c.xor a4, a5 - slti tp, a1, -167 - add s4, a7, s6 - andi t0, a3, 147 - lui s3, 985951 - sltiu s3, tp, 300 - srai a4, a3, 0 - slti tp, a1, -167 - mulhsu tp, t5, a6 - c.sub s0, s1 - c.sub s0, s1 - div s7, gp, a4 - c.srai s1, 28 - c.li s11, -1 - c.addi4spn a2, sp, 528 - c.addi4spn a2, sp, 528 - c.andi s1, 31 - mulh s1, t4, s11 - c.sub s0, s1 - c.srli a4, 9 - mulhsu tp, t5, a6 - addi gp, s8, -298 - slti tp, a1, -167 - srl t1, tp, zero - addi gp, s8, -298 - c.li s11, -1 - c.srli a4, 9 - c.addi16sp sp, -16 - c.addi16sp sp, -16 - ori tp, a0, -848 - nop - and s6, t2, a4 - mulhsu tp, t5, a6 - c.srli a4, 9 - rem a2, s2, s9 - mulhsu tp, t5, a6 - c.addi4spn a2, sp, 528 - mul tp, s2, t5 - sltu s3, a6, a4 - sra s9, s4, t5 - c.addi16sp sp, -16 - c.srai s1, 28 - sra s9, s4, t5 - c.lui a6, 24 - rem a2, s2, s9 - sltu s3, a6, a4 - divu tp, s5, t4 - rem a2, s2, s9 - sll s8, s0, s6 - srl t1, tp, zero - c.mv a2, a0 - and s6, t2, a4 - c.nop - remu s6, s3, t1 - srli zero, a0, 13 - mulhsu tp, t5, a6 - c.or a0, a2 - c.addi4spn a2, sp, 528 - c.slli t5, 22 - mulh s1, t4, s11 - divu tp, s5, t4 - slt a0, s5, s11 - srl t1, tp, zero - c.andi s1, 31 - and s6, t2, a4 - sltiu s3, tp, 300 - mulh s1, t4, s11 - c.li s11, -1 - rem a2, s2, s9 - mulhu s4, a6, t3 - c.li s11, -1 - mul tp, s2, t5 - srl t1, tp, zero - and s6, t2, a4 - rem a2, s2, s9 - sra s9, s4, t5 - c.andi s1, 31 - auipc s1, 11691 - c.sub s0, s1 - c.addi s9, -1 - mul tp, s2, t5 - addi gp, s8, -298 - sll s8, s0, s6 - or a4, a4, zero - c.and a4, s1 - c.srli a4, 9 - c.addi s9, -1 - c.and a4, s1 - slti tp, a1, -167 - c.andi s1, 31 - and s6, t2, a4 - c.addi4spn a2, sp, 528 - c.xor a4, a5 - nop - c.li s11, -1 - xor s11, zero, s7 - c.sub s0, s1 - add s4, a7, s6 - c.sub s0, s1 - c.sub s0, s1 - and s6, t2, a4 - sra s9, s4, t5 - c.or a0, a2 - c.addi4spn a2, sp, 528 - mulh s1, t4, s11 - mulhu s4, a6, t3 - nop - srai a4, a3, 0 - c.srli a4, 9 - c.xor a4, a5 - and s6, t2, a4 - c.mv a2, a0 - c.addi s9, -1 - or a4, a4, zero - srai a4, a3, 0 - ori tp, a0, -848 - xor s11, zero, s7 - c.or a0, a2 - mul tp, s2, t5 - c.and a4, s1 - sll s8, s0, s6 - slli a2, a4, 25 - srl t1, tp, zero - add s4, a7, s6 - slti tp, a1, -167 - c.and a4, s1 - add s4, a7, s6 - c.mv a2, a0 - nop - sltu s3, a6, a4 - c.or a0, a2 - c.sub s0, s1 - c.srai s1, 28 - ori tp, a0, -848 - sub s0, t3, gp - c.addi16sp sp, -16 - c.mv a2, a0 - slti tp, a1, -167 - sra s9, s4, t5 - and s6, t2, a4 - c.addi16sp sp, -16 - sltu s3, a6, a4 - addi gp, s8, -298 - div s7, gp, a4 - mulh s1, t4, s11 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - sra s9, s4, t5 - c.li s11, -1 - c.srai s1, 28 - remu s6, s3, t1 - andi t0, a3, 147 - sltu s3, a6, a4 - divu tp, s5, t4 - remu s6, s3, t1 - ori tp, a0, -848 - xori t3, t1, -721 - c.and a4, s1 - srl t1, tp, zero - slt a0, s5, s11 - nop - mulhsu tp, t5, a6 - c.nop - div s7, gp, a4 - mul tp, s2, t5 - srli zero, a0, 13 - nop - ori tp, a0, -848 - rem a2, s2, s9 - slt a0, s5, s11 - srl t1, tp, zero - c.srai s1, 28 - c.addi4spn a2, sp, 528 - c.srli a4, 9 - rem a2, s2, s9 - sltu s3, a6, a4 - andi t0, a3, 147 - srli zero, a0, 13 - remu s6, s3, t1 - div s7, gp, a4 - addi gp, s8, -298 - addi gp, s8, -298 - sra s9, s4, t5 - c.addi16sp sp, -16 - add s4, a7, s6 - sltu s3, a6, a4 - srai a4, a3, 0 - c.add t3, t1 - c.xor a4, a5 - li s7, 0xffffffff #start riscv_int_numeric_corner_stream_6 - li a3, 0xffffffff - li s5, 0x80000000 - li s4, 0xbb59ec9c - li s6, 0xffffffff - li t5, 0x0 - li s10, 0xffffffff - li s9, 0x80000000 - li gp, 0xffffffff - li s0, 0x80000000 - sub s10, gp, s10 - nop - auipc s0, 11691 - mul s0, s4, a3 - add gp, s7, t5 - remu s10, s7, s0 - sub s10, gp, s10 - mulhsu t5, s0, gp - nop - mulhu s5, a3, t5 - div s0, t5, gp - auipc s0, 11691 - rem s4, s0, gp - remu s10, s7, s0 - mulhu s5, a3, t5 - nop - nop - add gp, s7, t5 - nop - sub s10, gp, s10 - divu s0, gp, s9 - addi s9, s10, -40 - nop - divu s0, gp, s9 - lui gp, 985951 - mulhsu t5, s0, gp #end riscv_int_numeric_corner_stream_6 - sll s8, s0, s6 - c.addi4spn a2, sp, 528 - xor s11, zero, s7 - srai a4, a3, 0 - c.nop - mul tp, s2, t5 - slli a2, a4, 25 - mulhu s4, a6, t3 - srai a4, a3, 0 - sra s9, s4, t5 - c.li s11, -1 - c.slli t5, 22 - or a4, a4, zero - xori t3, t1, -721 - slli a2, a4, 25 - c.lui a6, 24 - sra s9, s4, t5 - sub s0, t3, gp - slli a2, a4, 25 - lui s3, 985951 - c.lui a6, 24 - slti tp, a1, -167 - slti tp, a1, -167 - mulhu s4, a6, t3 - c.and a4, s1 - lui s3, 985951 - lui s3, 985951 - mul tp, s2, t5 - divu tp, s5, t4 - add s4, a7, s6 - auipc s1, 11691 - mulhu s4, a6, t3 - sll s8, s0, s6 - mulh s1, t4, s11 - li t3, 0x0 #start riscv_int_numeric_corner_stream_5 - li s1, 0xffffffff - li a2, 0x80000000 - li s2, 0xeedf868b - li s6, 0x0 - li s0, 0xc9175766 - li a4, 0xffffffff - li a7, 0xd8542073 - li sp, 0x80000000 - li a0, 0xffffffff - auipc s1, 11691 - mulh a7, a4, a2 - mulhu a7, s1, s6 - remu sp, s6, a4 - remu sp, s6, a4 - mulhsu a4, t3, a7 - divu sp, a4, a7 - rem a2, sp, a4 - mulhu a7, s1, s6 - nop - nop - auipc s1, 11691 - nop - mulhu a7, s1, s6 - auipc s1, 11691 - divu sp, a4, a7 - nop #end riscv_int_numeric_corner_stream_5 - sltiu s3, tp, 300 - c.srli a4, 9 - sra s9, s4, t5 - lui s3, 985951 - and s6, t2, a4 - c.add t3, t1 - c.addi16sp sp, -16 - divu tp, s5, t4 - andi t0, a3, 147 - addi gp, s8, -298 - c.xor a4, a5 - andi t0, a3, 147 - sub s0, t3, gp - slti tp, a1, -167 - sra s9, s4, t5 - rem a2, s2, s9 - c.li s11, -1 - rem a2, s2, s9 - remu s6, s3, t1 - c.and a4, s1 - nop - mul tp, s2, t5 - add s4, a7, s6 - srai a4, a3, 0 - c.addi16sp sp, -16 - mulh s1, t4, s11 - andi t0, a3, 147 - auipc s1, 11691 - mulhu s4, a6, t3 - sub s0, t3, gp - lui s3, 985951 - c.lui a6, 24 - slti tp, a1, -167 - andi t0, a3, 147 - addi gp, s8, -298 - c.nop - sll s8, s0, s6 - c.or a0, a2 - ori tp, a0, -848 - remu s6, s3, t1 - rem a2, s2, s9 - c.or a0, a2 - slt a0, s5, s11 - c.and a4, s1 - auipc s1, 11691 - c.sub s0, s1 - addi gp, s8, -298 - sub s0, t3, gp - c.srai s1, 28 - c.and a4, s1 - srl t1, tp, zero - nop - lui s3, 985951 - c.or a0, a2 - ori tp, a0, -848 - c.slli t5, 22 - addi gp, s8, -298 - c.xor a4, a5 - xori t3, t1, -721 - c.slli t5, 22 - srl t1, tp, zero - sub s0, t3, gp - remu s6, s3, t1 - c.or a0, a2 - sll s8, s0, s6 - slti tp, a1, -167 - c.mv a2, a0 - c.mv a2, a0 - mulh s1, t4, s11 - srai a4, a3, 0 - remu s6, s3, t1 - add s4, a7, s6 - srai a4, a3, 0 - c.srli a4, 9 - li t5, 0x0 #start riscv_int_numeric_corner_stream_15 - li s1, 0x0 - li s5, 0x351e7347 - li s8, 0x80000000 - li a4, 0x0 - li a0, 0x9f5dafc5 - li s0, 0xffffffff - li s3, 0x80000000 - li a6, 0xffffffff - li t3, 0xae935f1a - sub s8, s1, s8 - mulhsu t5, a0, s5 - addi s1, s3, -40 - mul a4, a4, a4 - nop - nop - sub s8, s1, s8 - sub s8, s1, s8 - addi s1, s3, -40 - nop - div s3, t3, s3 - mulh a4, s1, s1 - auipc s0, 11691 - lui s3, 985951 - nop - rem s5, s3, a4 #end riscv_int_numeric_corner_stream_15 - c.addi16sp sp, -16 - remu s6, s3, t1 - divu tp, s5, t4 - c.slli t5, 22 - lui s3, 985951 - c.addi s9, -1 - c.andi s1, 31 - c.addi16sp sp, -16 - srai a4, a3, 0 - sub s0, t3, gp - slt a0, s5, s11 - srl t1, tp, zero - c.and a4, s1 - c.slli t5, 22 - slli a2, a4, 25 - nop - c.lui a6, 24 - sra s9, s4, t5 - c.srai s1, 28 - c.li s11, -1 - c.and a4, s1 - and s6, t2, a4 - mulhu s4, a6, t3 - divu tp, s5, t4 - c.li s11, -1 - c.addi4spn a2, sp, 528 - c.addi16sp sp, -16 - and s6, t2, a4 - div s7, gp, a4 - slli a2, a4, 25 - rem a2, s2, s9 - rem a2, s2, s9 - sltiu s3, tp, 300 - c.sub s0, s1 - c.sub s0, s1 - lui s3, 985951 - sub s0, t3, gp - add s4, a7, s6 - c.and a4, s1 - c.li s11, -1 - rem a2, s2, s9 - c.xor a4, a5 - c.srai s1, 28 - mulh s1, t4, s11 - div s7, gp, a4 - slti tp, a1, -167 - xor s11, zero, s7 - mulh s1, t4, s11 - c.or a0, a2 - add s4, a7, s6 - div s7, gp, a4 - c.srli a4, 9 - remu s6, s3, t1 - nop - c.li s11, -1 - c.or a0, a2 - c.addi16sp sp, -16 - sub s0, t3, gp - c.li s11, -1 - c.srli a4, 9 - or a4, a4, zero - srai a4, a3, 0 - srai a4, a3, 0 - and s6, t2, a4 - srli zero, a0, 13 - srl t1, tp, zero - xori t3, t1, -721 - ori tp, a0, -848 - c.or a0, a2 - c.mv a2, a0 - div s7, gp, a4 - ori tp, a0, -848 - sltiu s3, tp, 300 - c.lui a6, 24 - c.add t3, t1 - nop - sub s0, t3, gp - sltiu s3, tp, 300 - slli a2, a4, 25 - c.li s11, -1 - sll s8, s0, s6 - add s4, a7, s6 - andi t0, a3, 147 - lui s3, 985951 - or a4, a4, zero - c.and a4, s1 - c.lui a6, 24 - slt a0, s5, s11 - c.add t3, t1 - sltu s3, a6, a4 - or a4, a4, zero - c.addi4spn a2, sp, 528 - add s4, a7, s6 - add s4, a7, s6 - addi gp, s8, -298 - c.addi s9, -1 - auipc s1, 11691 - rem a2, s2, s9 - and s6, t2, a4 - c.or a0, a2 - mulh s1, t4, s11 - divu tp, s5, t4 - c.li s11, -1 - c.addi s9, -1 - c.addi16sp sp, -16 - srli zero, a0, 13 - or a4, a4, zero - c.and a4, s1 - c.addi16sp sp, -16 - sra s9, s4, t5 - sltu s3, a6, a4 - c.li s11, -1 - sltiu s3, tp, 300 - addi gp, s8, -298 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - c.srai s1, 28 - sll s8, s0, s6 - c.addi4spn a2, sp, 528 - c.andi s1, 31 - xori t3, t1, -721 - add s4, a7, s6 - srai a4, a3, 0 - srli zero, a0, 13 - andi t0, a3, 147 - rem a2, s2, s9 - srl t1, tp, zero - sub s0, t3, gp - c.slli t5, 22 - mul tp, s2, t5 - slti tp, a1, -167 - xori t3, t1, -721 - c.addi16sp sp, -16 - auipc s1, 11691 - c.xor a4, a5 - and s6, t2, a4 - andi t0, a3, 147 - c.li s11, -1 - andi t0, a3, 147 - andi t0, a3, 147 - c.lui a6, 24 - xor s11, zero, s7 - slti tp, a1, -167 - c.srai s1, 28 - sltiu s3, tp, 300 - c.addi4spn a2, sp, 528 - add s4, a7, s6 - div s7, gp, a4 - c.addi4spn a2, sp, 528 - c.andi s1, 31 - c.slli t5, 22 - ori tp, a0, -848 - rem a2, s2, s9 - c.mv a2, a0 - mulhu s4, a6, t3 - ori tp, a0, -848 - ori tp, a0, -848 - nop - c.add t3, t1 - xori t3, t1, -721 - c.mv a2, a0 - c.nop - remu s6, s3, t1 - nop - mulh s1, t4, s11 - c.add t3, t1 - c.slli t5, 22 - c.srli a4, 9 - c.xor a4, a5 - xori t3, t1, -721 - mulhsu tp, t5, a6 - c.addi16sp sp, -16 - add s4, a7, s6 - mulhsu tp, t5, a6 - c.sub s0, s1 - c.srli a4, 9 - srl t1, tp, zero - auipc s1, 11691 - sub s0, t3, gp - mulh s1, t4, s11 - mulhsu tp, t5, a6 - slt a0, s5, s11 - c.nop - c.slli t5, 22 - c.addi16sp sp, -16 - mul tp, s2, t5 - c.lui a6, 24 - c.addi4spn a2, sp, 528 - or a4, a4, zero - divu tp, s5, t4 - c.lui a6, 24 - mulhsu tp, t5, a6 - c.addi s9, -1 - slt a0, s5, s11 - ori tp, a0, -848 - ori tp, a0, -848 - sll s8, s0, s6 - slti tp, a1, -167 - nop - auipc s1, 11691 - srai a4, a3, 0 - sra s9, s4, t5 - sltu s3, a6, a4 - sub s0, t3, gp - c.srai s1, 28 - c.mv a2, a0 - c.addi s9, -1 - add s4, a7, s6 - c.xor a4, a5 - c.slli t5, 22 - ori tp, a0, -848 - ori tp, a0, -848 - c.mv a2, a0 - c.and a4, s1 - add s4, a7, s6 - remu s6, s3, t1 - xor s11, zero, s7 - c.xor a4, a5 - srli zero, a0, 13 - sub s0, t3, gp - c.sub s0, s1 - c.mv a2, a0 - or a4, a4, zero - auipc s1, 11691 - c.slli t5, 22 - ori tp, a0, -848 - mulhsu tp, t5, a6 - sra s9, s4, t5 - slti tp, a1, -167 - add s4, a7, s6 - slt a0, s5, s11 - auipc s1, 11691 - addi gp, s8, -298 - lui s3, 985951 - c.addi16sp sp, -16 - mulhsu tp, t5, a6 - c.slli t5, 22 - c.add t3, t1 - sltu s3, a6, a4 - rem a2, s2, s9 - c.li s11, -1 - c.srli a4, 9 - xor s11, zero, s7 - slt a0, s5, s11 - remu s6, s3, t1 - c.nop - or a4, a4, zero - auipc s1, 11691 - c.slli t5, 22 - slt a0, s5, s11 - c.andi s1, 31 - or a4, a4, zero - sub s0, t3, gp - lui s3, 985951 - c.addi16sp sp, -16 - add s4, a7, s6 - nop - div s7, gp, a4 - auipc s1, 11691 - c.li s11, -1 - mulh s1, t4, s11 - and s6, t2, a4 - sub s0, t3, gp - srai a4, a3, 0 - and s6, t2, a4 - slli a2, a4, 25 - add s4, a7, s6 - c.mv a2, a0 - sltu s3, a6, a4 - c.addi s9, -1 - rem a2, s2, s9 - c.mv a2, a0 - add s4, a7, s6 - sra s9, s4, t5 - xori t3, t1, -721 - srai a4, a3, 0 - c.slli t5, 22 - c.andi s1, 31 - c.lui a6, 24 - xori t3, t1, -721 - or a4, a4, zero - mulhsu tp, t5, a6 - auipc s1, 11691 - srli zero, a0, 13 - mulh s1, t4, s11 - srai a4, a3, 0 - c.nop - xori t3, t1, -721 - sltu s3, a6, a4 - c.addi s9, -1 - c.nop - c.addi16sp sp, -16 - add s4, a7, s6 - sltiu s3, tp, 300 - sra s9, s4, t5 - c.addi s9, -1 - or a4, a4, zero - c.andi s1, 31 - c.andi s1, 31 - or a4, a4, zero - c.addi16sp sp, -16 - or a4, a4, zero - sra s9, s4, t5 - rem a2, s2, s9 - slt a0, s5, s11 - c.addi s9, -1 - c.andi s1, 31 - sll s8, s0, s6 - c.addi4spn a2, sp, 528 - c.addi s9, -1 - c.srli a4, 9 - mulhu s4, a6, t3 - and s6, t2, a4 - div s7, gp, a4 - c.and a4, s1 - addi gp, s8, -298 - c.andi s1, 31 - nop - c.xor a4, a5 - c.and a4, s1 - c.sub s0, s1 - div s7, gp, a4 - and s6, t2, a4 - sub s0, t3, gp - c.and a4, s1 - c.srli a4, 9 - mulhsu tp, t5, a6 - remu s6, s3, t1 - c.srai s1, 28 - addi gp, s8, -298 - and s6, t2, a4 - c.add t3, t1 - lui s3, 985951 - add s4, a7, s6 - ori tp, a0, -848 - c.addi4spn a2, sp, 528 - mulhsu tp, t5, a6 - sub s0, t3, gp - c.and a4, s1 - remu s6, s3, t1 - mul tp, s2, t5 - mulhu s4, a6, t3 - c.addi s9, -1 - mulh s1, t4, s11 - remu s6, s3, t1 - addi gp, s8, -298 - c.and a4, s1 - lui s3, 985951 - c.xor a4, a5 - div s7, gp, a4 - c.andi s1, 31 - c.mv a2, a0 - add s4, a7, s6 - slti tp, a1, -167 - sll s8, s0, s6 - c.li s11, -1 - auipc s1, 11691 - divu tp, s5, t4 - c.andi s1, 31 - sub s0, t3, gp - c.addi16sp sp, -16 - remu s6, s3, t1 - xor s11, zero, s7 - srli zero, a0, 13 - and s6, t2, a4 - c.addi s9, -1 - mulhu s4, a6, t3 - xor s11, zero, s7 - or a4, a4, zero - c.srli a4, 9 - xori t3, t1, -721 - ori tp, a0, -848 - mulh s1, t4, s11 - xori t3, t1, -721 - sltiu s3, tp, 300 - or a4, a4, zero - addi gp, s8, -298 - rem a2, s2, s9 - mulhsu tp, t5, a6 - div s7, gp, a4 - c.or a0, a2 - c.srai s1, 28 - mul tp, s2, t5 - c.sub s0, s1 - c.add t3, t1 - divu tp, s5, t4 - c.addi s9, -1 - mulh s1, t4, s11 - auipc s1, 11691 - nop - c.nop - c.nop - div s7, gp, a4 - or a4, a4, zero - srli zero, a0, 13 - nop - remu s6, s3, t1 - addi gp, s8, -298 - auipc s1, 11691 - c.srli a4, 9 - andi t0, a3, 147 - sltiu s3, tp, 300 - or a4, a4, zero - c.and a4, s1 - auipc s1, 11691 - c.mv a2, a0 - sub s0, t3, gp - xori t3, t1, -721 - c.li s11, -1 - c.nop - srl t1, tp, zero - auipc s1, 11691 - andi t0, a3, 147 - c.sub s0, s1 - nop - c.add t3, t1 - div s7, gp, a4 - slti tp, a1, -167 - c.nop - mulhu s4, a6, t3 - slli a2, a4, 25 - sltiu s3, tp, 300 - nop - auipc s1, 11691 - c.andi s1, 31 - xor s11, zero, s7 - xori t3, t1, -721 - remu s6, s3, t1 - mulhsu tp, t5, a6 - srli zero, a0, 13 - mulh s1, t4, s11 - c.and a4, s1 - mulh s1, t4, s11 - sltiu s3, tp, 300 - ori tp, a0, -848 - c.li s11, -1 - c.andi s1, 31 - c.addi4spn a2, sp, 528 - c.add t3, t1 - c.and a4, s1 - sltu s3, a6, a4 - c.srai s1, 28 - xori t3, t1, -721 - srai a4, a3, 0 - nop - mulhu s4, a6, t3 - add s4, a7, s6 - c.srai s1, 28 - c.or a0, a2 - xor s11, zero, s7 - auipc s1, 11691 - sra s9, s4, t5 - andi t0, a3, 147 - sltiu s3, tp, 300 - srl t1, tp, zero - slt a0, s5, s11 - c.li s11, -1 - sra s9, s4, t5 - xor s11, zero, s7 - mulhsu tp, t5, a6 - c.addi16sp sp, -16 - c.xor a4, a5 - c.li s11, -1 - c.lui a6, 24 - c.mv a2, a0 - lui s3, 985951 - div s7, gp, a4 - xor s11, zero, s7 - and s6, t2, a4 - sra s9, s4, t5 - ori tp, a0, -848 - or a4, a4, zero - c.lui a6, 24 - c.addi4spn a2, sp, 528 - sra s9, s4, t5 - slt a0, s5, s11 - c.slli t5, 22 - c.or a0, a2 - mulhsu tp, t5, a6 - mulhsu tp, t5, a6 - srli zero, a0, 13 - slt a0, s5, s11 - c.slli t5, 22 - remu s6, s3, t1 - c.nop - c.nop - srl t1, tp, zero - srai a4, a3, 0 - c.mv a2, a0 - xor s11, zero, s7 - and s6, t2, a4 - srai a4, a3, 0 - c.lui a6, 24 - nop - sub s0, t3, gp - c.nop - mulh s1, t4, s11 - slti tp, a1, -167 - sltiu s3, tp, 300 - sub s0, t3, gp - xori t3, t1, -721 - c.andi s1, 31 - remu s6, s3, t1 - c.sub s0, s1 - sltu s3, a6, a4 - addi gp, s8, -298 - slli a2, a4, 25 - div s7, gp, a4 - c.or a0, a2 - mul tp, s2, t5 - c.or a0, a2 - divu tp, s5, t4 - rem a2, s2, s9 - slt a0, s5, s11 - c.srai s1, 28 - sll s8, s0, s6 - c.add t3, t1 - c.add t3, t1 - srai a4, a3, 0 - sltu s3, a6, a4 - mul tp, s2, t5 - sltiu s3, tp, 300 - c.and a4, s1 - srai a4, a3, 0 - sltu s3, a6, a4 - c.srli a4, 9 - slti tp, a1, -167 - srai a4, a3, 0 - sltiu s3, tp, 300 - c.slli t5, 22 - sll s8, s0, s6 - andi t0, a3, 147 - ori tp, a0, -848 - srli zero, a0, 13 - mul tp, s2, t5 - c.li s11, -1 - ori tp, a0, -848 - nop - c.xor a4, a5 - add s4, a7, s6 - sltu s3, a6, a4 - slli a2, a4, 25 - xor s11, zero, s7 - nop - c.li s11, -1 - nop - c.andi s1, 31 - slti tp, a1, -167 - rem a2, s2, s9 - c.srai s1, 28 - c.mv a2, a0 - mulhsu tp, t5, a6 - c.sub s0, s1 - c.xor a4, a5 - slti tp, a1, -167 - xori t3, t1, -721 - slli a2, a4, 25 - mulhsu tp, t5, a6 - c.lui a6, 24 - auipc s1, 11691 - div s7, gp, a4 - div s7, gp, a4 - xor s11, zero, s7 - c.slli t5, 22 - c.addi16sp sp, -16 - c.sub s0, s1 - sll s8, s0, s6 - add s4, a7, s6 - sltiu s3, tp, 300 - slt a0, s5, s11 - xori t3, t1, -721 - xor s11, zero, s7 - sltiu s3, tp, 300 - divu tp, s5, t4 - sra s9, s4, t5 - xori t3, t1, -721 - c.and a4, s1 - c.addi4spn a2, sp, 528 - c.and a4, s1 - andi t0, a3, 147 - c.add t3, t1 - ori tp, a0, -848 - lui s3, 985951 - nop - mulh s1, t4, s11 - remu s6, s3, t1 - sub s0, t3, gp - sub s0, t3, gp - c.srai s1, 28 - c.addi4spn a2, sp, 528 - c.addi s9, -1 - xori t3, t1, -721 - and s6, t2, a4 - divu tp, s5, t4 - c.xor a4, a5 - divu tp, s5, t4 - lui s3, 985951 - lui s3, 985951 - ori tp, a0, -848 - remu s6, s3, t1 - c.srai s1, 28 - c.srli a4, 9 - nop - c.and a4, s1 - c.andi s1, 31 - andi t0, a3, 147 - lui s3, 985951 - or a4, a4, zero - add s4, a7, s6 - auipc s1, 11691 - slt a0, s5, s11 - remu s6, s3, t1 - slli a2, a4, 25 - sll s8, s0, s6 - remu s6, s3, t1 - c.or a0, a2 - remu s6, s3, t1 - slti tp, a1, -167 - slt a0, s5, s11 - c.slli t5, 22 - srai a4, a3, 0 - mulh s1, t4, s11 - c.add t3, t1 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - sltiu s3, tp, 300 - c.xor a4, a5 - auipc s1, 11691 - srai a4, a3, 0 - srl t1, tp, zero - addi gp, s8, -298 - rem a2, s2, s9 - slti tp, a1, -167 - slti tp, a1, -167 - ori tp, a0, -848 - sra s9, s4, t5 - slli a2, a4, 25 - or a4, a4, zero - ori tp, a0, -848 - addi gp, s8, -298 - nop - c.addi4spn a2, sp, 528 - xor s11, zero, s7 - mulhu s4, a6, t3 - c.srai s1, 28 - ori tp, a0, -848 - add s4, a7, s6 - c.add t3, t1 - or a4, a4, zero - c.xor a4, a5 - c.xor a4, a5 - c.addi4spn a2, sp, 528 - c.xor a4, a5 - xor s11, zero, s7 - c.addi4spn a2, sp, 528 - add s4, a7, s6 - sltiu s3, tp, 300 - srai a4, a3, 0 - sra s9, s4, t5 - auipc s1, 11691 - mul tp, s2, t5 - auipc s1, 11691 - remu s6, s3, t1 - mulh s1, t4, s11 - and s6, t2, a4 - sltiu s3, tp, 300 - sltiu s3, tp, 300 - andi t0, a3, 147 - slti tp, a1, -167 - slti tp, a1, -167 - srl t1, tp, zero - c.nop - addi gp, s8, -298 - mulhsu tp, t5, a6 - xor s11, zero, s7 - mulhu s4, a6, t3 - ori tp, a0, -848 - sll s8, s0, s6 - c.andi s1, 31 - or a4, a4, zero - mulhsu tp, t5, a6 - div s7, gp, a4 - sll s8, s0, s6 - slti tp, a1, -167 - divu tp, s5, t4 - and s6, t2, a4 - sll s8, s0, s6 - remu s6, s3, t1 - rem a2, s2, s9 - auipc s1, 11691 - c.xor a4, a5 - c.srai s1, 28 - sltu s3, a6, a4 - c.sub s0, s1 - nop - c.srli a4, 9 - srl t1, tp, zero - mulhsu tp, t5, a6 - c.srli a4, 9 - ori tp, a0, -848 - c.or a0, a2 - and s6, t2, a4 - xori t3, t1, -721 - c.srli a4, 9 - xor s11, zero, s7 - mul tp, s2, t5 - c.lui a6, 24 - c.mv a2, a0 - c.slli t5, 22 - c.sub s0, s1 - mul tp, s2, t5 - mulhu s4, a6, t3 - c.or a0, a2 - nop - ori tp, a0, -848 - slli a2, a4, 25 - xor s11, zero, s7 - mul tp, s2, t5 - rem a2, s2, s9 - auipc s1, 11691 - mulh s1, t4, s11 - sra s9, s4, t5 - c.srai s1, 28 - c.addi4spn a2, sp, 528 - rem a2, s2, s9 - div s7, gp, a4 - slli a2, a4, 25 - andi t0, a3, 147 - c.or a0, a2 - c.srli a4, 9 - c.add t3, t1 - sltu s3, a6, a4 - remu s6, s3, t1 - nop - c.add t3, t1 - slli a2, a4, 25 - c.andi s1, 31 - sra s9, s4, t5 - divu tp, s5, t4 - srl t1, tp, zero - and s6, t2, a4 - mulhsu tp, t5, a6 - c.and a4, s1 - divu tp, s5, t4 - c.sub s0, s1 - c.or a0, a2 - div s7, gp, a4 - auipc s1, 11691 - sltiu s3, tp, 300 - sltiu s3, tp, 300 - divu tp, s5, t4 - srli zero, a0, 13 - and s6, t2, a4 - c.addi s9, -1 - mulhu s4, a6, t3 - andi t0, a3, 147 - c.slli t5, 22 - srli zero, a0, 13 - c.addi s9, -1 - divu tp, s5, t4 - c.sub s0, s1 - sltu s3, a6, a4 - c.srli a4, 9 - srli zero, a0, 13 - ori tp, a0, -848 - auipc s1, 11691 - mulhu s4, a6, t3 - sltiu s3, tp, 300 - mulh s1, t4, s11 - c.srai s1, 28 - nop - c.andi s1, 31 - c.mv a2, a0 - c.addi16sp sp, -16 - mulhsu tp, t5, a6 - c.mv a2, a0 - c.lui a6, 24 - c.sub s0, s1 - sub s0, t3, gp - c.slli t5, 22 - mulhu s4, a6, t3 - c.srai s1, 28 - c.li s11, -1 - divu tp, s5, t4 - srli zero, a0, 13 - c.lui a6, 24 - srl t1, tp, zero - or a4, a4, zero - c.srli a4, 9 - c.slli t5, 22 - lui s3, 985951 - div s7, gp, a4 - c.or a0, a2 - sra s9, s4, t5 - lui s3, 985951 - srai a4, a3, 0 - divu tp, s5, t4 - c.mv a2, a0 - c.mv a2, a0 - auipc s1, 11691 - c.xor a4, a5 - c.li s11, -1 - xor s11, zero, s7 - c.mv a2, a0 - andi t0, a3, 147 - c.and a4, s1 - c.srai s1, 28 - ori tp, a0, -848 - c.nop - c.and a4, s1 - c.addi16sp sp, -16 - ori tp, a0, -848 - srli zero, a0, 13 - and s6, t2, a4 - sltiu s3, tp, 300 - sll s8, s0, s6 - c.and a4, s1 - sra s9, s4, t5 - li s3, 0x9fc4ed12 #start riscv_int_numeric_corner_stream_17 - li a4, 0xffffffff - li s8, 0x0 - li sp, 0x29cafa7d - li t4, 0x7b501a29 - li s6, 0xda2565da - li s0, 0xffffffff - li t2, 0x80000000 - li a6, 0xffffffff - li a3, 0x2fd7c225 - sub s8, s8, s8 - nop - rem t4, a6, a4 - mulhsu t2, s0, s3 - nop - divu s8, s6, a6 - sub s8, s8, s8 - nop - lui s3, 985951 - div t4, a3, t2 - sub s8, s8, s8 - mul t2, s8, a4 - nop - div t4, a3, t2 - rem t4, a6, a4 - add t2, t4, a4 #end riscv_int_numeric_corner_stream_17 - sltu s3, a6, a4 - auipc s1, 11691 - sltu s3, a6, a4 - remu s6, s3, t1 - div s7, gp, a4 - mul tp, s2, t5 - andi t0, a3, 147 - c.add t3, t1 - andi t0, a3, 147 - mulhsu tp, t5, a6 - c.mv a2, a0 - ori tp, a0, -848 - nop - mulh s1, t4, s11 - sltu s3, a6, a4 - xor s11, zero, s7 - slli a2, a4, 25 - c.addi4spn a2, sp, 528 - c.nop - nop - c.addi16sp sp, -16 - and s6, t2, a4 - c.addi s9, -1 - slti tp, a1, -167 - xori t3, t1, -721 - mulh s1, t4, s11 - c.srai s1, 28 - and s6, t2, a4 - srai a4, a3, 0 - c.addi16sp sp, -16 - sltiu s3, tp, 300 - c.addi16sp sp, -16 - div s7, gp, a4 - c.li s11, -1 - divu tp, s5, t4 - c.srai s1, 28 - or a4, a4, zero - mul tp, s2, t5 - c.nop - c.and a4, s1 - srai a4, a3, 0 - c.li s11, -1 - nop - c.srai s1, 28 - c.lui a6, 24 - sra s9, s4, t5 - c.or a0, a2 - c.addi s9, -1 - c.addi4spn a2, sp, 528 - c.srai s1, 28 - c.addi16sp sp, -16 - c.lui a6, 24 - srl t1, tp, zero - c.addi s9, -1 - nop - c.lui a6, 24 - sltiu s3, tp, 300 - xor s11, zero, s7 - sltu s3, a6, a4 - and s6, t2, a4 - c.andi s1, 31 - andi t0, a3, 147 - sll s8, s0, s6 - mulhsu tp, t5, a6 - srli zero, a0, 13 - srai a4, a3, 0 - sll s8, s0, s6 - and s6, t2, a4 - sltiu s3, tp, 300 - slt a0, s5, s11 - add s4, a7, s6 - slli a2, a4, 25 - xori t3, t1, -721 - c.or a0, a2 - slli a2, a4, 25 - xori t3, t1, -721 - mulhsu tp, t5, a6 - and s6, t2, a4 - div s7, gp, a4 - mul tp, s2, t5 - or a4, a4, zero - sltu s3, a6, a4 - c.srai s1, 28 - srli zero, a0, 13 - andi t0, a3, 147 - sra s9, s4, t5 - xori t3, t1, -721 - srli zero, a0, 13 - slti tp, a1, -167 - and s6, t2, a4 - slt a0, s5, s11 - sltiu s3, tp, 300 - c.or a0, a2 - slti tp, a1, -167 - ori tp, a0, -848 - c.addi s9, -1 - srai a4, a3, 0 - slti tp, a1, -167 - and s6, t2, a4 - srl t1, tp, zero - divu tp, s5, t4 - remu s6, s3, t1 - c.sub s0, s1 - c.xor a4, a5 - c.and a4, s1 - mul tp, s2, t5 - or a4, a4, zero - lui s3, 985951 - c.addi16sp sp, -16 - andi t0, a3, 147 - sub s0, t3, gp - srli zero, a0, 13 - mulh s1, t4, s11 - xori t3, t1, -721 - ori tp, a0, -848 - c.srli a4, 9 - c.addi16sp sp, -16 - divu tp, s5, t4 - ori tp, a0, -848 - c.xor a4, a5 - mulhu s4, a6, t3 - c.or a0, a2 - xor s11, zero, s7 - mulh s1, t4, s11 - srai a4, a3, 0 - c.srai s1, 28 - mulhu s4, a6, t3 - div s7, gp, a4 - sub s0, t3, gp - c.lui a6, 24 - auipc s1, 11691 - c.addi4spn a2, sp, 528 - div s7, gp, a4 - c.mv a2, a0 - mulhsu tp, t5, a6 - c.srli a4, 9 - srli zero, a0, 13 - c.xor a4, a5 - add s4, a7, s6 - mul tp, s2, t5 - slt a0, s5, s11 - mulhu s4, a6, t3 - mulhu s4, a6, t3 - srli zero, a0, 13 - or a4, a4, zero - mulh s1, t4, s11 - nop - ori tp, a0, -848 - srli zero, a0, 13 - rem a2, s2, s9 - srli zero, a0, 13 - c.li s11, -1 - slti tp, a1, -167 - c.andi s1, 31 - sltu s3, a6, a4 - srai a4, a3, 0 - c.srai s1, 28 - c.srai s1, 28 - remu s6, s3, t1 - slti tp, a1, -167 - c.xor a4, a5 - c.addi16sp sp, -16 - srl t1, tp, zero - addi gp, s8, -298 - slti tp, a1, -167 - remu s6, s3, t1 - mulhu s4, a6, t3 - addi gp, s8, -298 - remu s6, s3, t1 - c.nop - c.srai s1, 28 - slt a0, s5, s11 - c.srai s1, 28 - andi t0, a3, 147 - mulhsu tp, t5, a6 - xori t3, t1, -721 - c.and a4, s1 - srai a4, a3, 0 - nop - c.srai s1, 28 - auipc s1, 11691 - rem a2, s2, s9 - or a4, a4, zero - sltu s3, a6, a4 - and s6, t2, a4 - addi gp, s8, -298 - divu tp, s5, t4 - mulhsu tp, t5, a6 - c.srai s1, 28 - sltu s3, a6, a4 - c.or a0, a2 - rem a2, s2, s9 - c.xor a4, a5 - sra s9, s4, t5 - auipc s1, 11691 - slli a2, a4, 25 - c.and a4, s1 - mulhsu tp, t5, a6 - srl t1, tp, zero - slti tp, a1, -167 - c.xor a4, a5 - c.sub s0, s1 - and s6, t2, a4 - xori t3, t1, -721 - mulhu s4, a6, t3 - divu tp, s5, t4 - srli zero, a0, 13 - andi t0, a3, 147 - auipc s1, 11691 - auipc s1, 11691 - andi t0, a3, 147 - sub s0, t3, gp - srai a4, a3, 0 - or a4, a4, zero - srai a4, a3, 0 - c.nop - c.and a4, s1 - c.and a4, s1 - ori tp, a0, -848 - mulhu s4, a6, t3 - divu tp, s5, t4 - ori tp, a0, -848 - sll s8, s0, s6 - slti tp, a1, -167 - nop - and s6, t2, a4 - lui s3, 985951 - c.or a0, a2 - slt a0, s5, s11 - srai a4, a3, 0 - c.srai s1, 28 - div s7, gp, a4 - c.srli a4, 9 - c.li s11, -1 - srl t1, tp, zero - c.li s11, -1 - divu tp, s5, t4 - lui s3, 985951 - c.addi s9, -1 - c.nop - xori t3, t1, -721 - srai a4, a3, 0 - c.and a4, s1 - andi t0, a3, 147 - sra s9, s4, t5 - c.srai s1, 28 - c.add t3, t1 - nop - lui s3, 985951 - c.and a4, s1 - c.add t3, t1 - c.nop - c.andi s1, 31 - c.nop - slli a2, a4, 25 - c.slli t5, 22 - srli zero, a0, 13 - lui s3, 985951 - slti tp, a1, -167 - c.addi16sp sp, -16 - c.slli t5, 22 - srl t1, tp, zero - #j test_done - j fast_exit -#Start: Extracted from riscv_compliance_tests/riscv_test.h -fast_exit: - /* print "\nDONE\n\n" */ - lui a0,print_port>>12 - addi a1,zero,'D' - addi a2,zero,'O' - addi a3,zero,'N' - addi a4,zero,'E' - addi a5,zero,'\n' - sw a5,0(a0) - sw a1,0(a0) - sw a2,0(a0) - sw a3,0(a0) - sw a4,0(a0) - sw a5,0(a0) - sw a5,0(a0) - - li a0, CV_VP_STATUS_FLAGS_BASE - lw a1, test_results /* report result */ - sw a1,0(a0) - - wfi /* we are done */ -##End: Extracted from riscv_compliance_tests/riscv_test.h - -test_done: - li gp, 1 - ecall -write_tohost: - sw gp, tohost, t5 - -_exit: - j write_tohost - -init_machine_mode: - li x10, 0x1800 - csrw 0x300, x10 # MSTATUS - li x10, 0x0 - csrw 0x304, x10 # MIE - mret -instr_end: - nop - -.section .data -.align 6; .global tohost; tohost: .dword 0; -.align 6; .global fromhost; fromhost: .dword 0; -.section .user_stack,"aw",@progbits; -.align 2 -user_stack_start: -.rept 4999 -.4byte 0x0 -.endr -user_stack_end: -.4byte 0x0 -.align 2 -kernel_instr_start: -.text -mmode_intr_vector_1: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_2: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_3: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_4: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_5: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_6: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_7: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_8: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_9: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_10: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_11: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_12: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_13: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_14: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -mmode_intr_vector_15: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x342 # MCAUSE - srli x10, x10, 0x1f - beqz x10, 1f - j mmode_intr_handler - 1: j test_done - -.align 2 -mtvec_handler: - .option norvc; - j mmode_exception_handler - j mmode_intr_vector_1 - j mmode_intr_vector_2 - j mmode_intr_vector_3 - j mmode_intr_vector_4 - j mmode_intr_vector_5 - j mmode_intr_vector_6 - j mmode_intr_vector_7 - j mmode_intr_vector_8 - j mmode_intr_vector_9 - j mmode_intr_vector_10 - j mmode_intr_vector_11 - j mmode_intr_vector_12 - j mmode_intr_vector_13 - j mmode_intr_vector_14 - j mmode_intr_vector_15 - .option rvc; - -mmode_exception_handler: - csrrw x15, 0x340, x15 - add x15, x31, zero - 1: addi x15, x15, -124 - sw x1, 4(x15) - sw x2, 8(x15) - sw x3, 12(x15) - sw x4, 16(x15) - sw x5, 20(x15) - sw x6, 24(x15) - sw x7, 28(x15) - sw x8, 32(x15) - sw x9, 36(x15) - sw x10, 40(x15) - sw x11, 44(x15) - sw x12, 48(x15) - sw x13, 52(x15) - sw x14, 56(x15) - sw x15, 60(x15) - sw x16, 64(x15) - sw x17, 68(x15) - sw x18, 72(x15) - sw x19, 76(x15) - sw x20, 80(x15) - sw x21, 84(x15) - sw x22, 88(x15) - sw x23, 92(x15) - sw x24, 96(x15) - sw x25, 100(x15) - sw x26, 104(x15) - sw x27, 108(x15) - sw x28, 112(x15) - sw x29, 116(x15) - sw x30, 120(x15) - sw x31, 124(x15) - csrr x10, 0x341 # MEPC - csrr x10, 0x342 # MCAUSE - li x2, 0x3 # BREAKPOINT - beq x10, x2, ebreak_handler - li x2, 0x8 # ECALL_UMODE - beq x10, x2, ecall_handler - li x2, 0x9 # ECALL_SMODE - beq x10, x2, ecall_handler - li x2, 0xb # ECALL_MMODE - beq x10, x2, ecall_handler - li x2, 0x1 - beq x10, x2, instr_fault_handler - li x2, 0x5 - beq x10, x2, load_fault_handler - li x2, 0x7 - beq x10, x2, store_fault_handler - li x2, 0xc - beq x10, x2, pt_fault_handler - li x2, 0xd - beq x10, x2, pt_fault_handler - li x2, 0xf - beq x10, x2, pt_fault_handler - li x2, 0x2 # ILLEGAL_INSTRUCTION - beq x10, x2, illegal_instr_handler - csrr x2, 0x343 # MTVAL - 1: jal x1, test_done - -ecall_handler: - la x10, _start - sw x0, 0(x10) - sw x1, 4(x10) - sw x2, 8(x10) - sw x3, 12(x10) - sw x4, 16(x10) - sw x5, 20(x10) - sw x6, 24(x10) - sw x7, 28(x10) - sw x8, 32(x10) - sw x9, 36(x10) - sw x10, 40(x10) - sw x11, 44(x10) - sw x12, 48(x10) - sw x13, 52(x10) - sw x14, 56(x10) - sw x15, 60(x10) - sw x16, 64(x10) - sw x17, 68(x10) - sw x18, 72(x10) - sw x19, 76(x10) - sw x20, 80(x10) - sw x21, 84(x10) - sw x22, 88(x10) - sw x23, 92(x10) - sw x24, 96(x10) - sw x25, 100(x10) - sw x26, 104(x10) - sw x27, 108(x10) - sw x28, 112(x10) - sw x29, 116(x10) - sw x30, 120(x10) - sw x31, 124(x10) - j write_tohost -instr_fault_handler: - lw x1, 4(x15) - lw x2, 8(x15) - lw x3, 12(x15) - lw x4, 16(x15) - lw x5, 20(x15) - lw x6, 24(x15) - lw x7, 28(x15) - lw x8, 32(x15) - lw x9, 36(x15) - lw x10, 40(x15) - lw x11, 44(x15) - lw x12, 48(x15) - lw x13, 52(x15) - lw x14, 56(x15) - lw x15, 60(x15) - lw x16, 64(x15) - lw x17, 68(x15) - lw x18, 72(x15) - lw x19, 76(x15) - lw x20, 80(x15) - lw x21, 84(x15) - lw x22, 88(x15) - lw x23, 92(x15) - lw x24, 96(x15) - lw x25, 100(x15) - lw x26, 104(x15) - lw x27, 108(x15) - lw x28, 112(x15) - lw x29, 116(x15) - lw x30, 120(x15) - lw x31, 124(x15) - addi x15, x15, 124 - add x31, x15, zero - csrrw x15, 0x340, x15 - mret - -load_fault_handler: - lw x1, 4(x15) - lw x2, 8(x15) - lw x3, 12(x15) - lw x4, 16(x15) - lw x5, 20(x15) - lw x6, 24(x15) - lw x7, 28(x15) - lw x8, 32(x15) - lw x9, 36(x15) - lw x10, 40(x15) - lw x11, 44(x15) - lw x12, 48(x15) - lw x13, 52(x15) - lw x14, 56(x15) - lw x15, 60(x15) - lw x16, 64(x15) - lw x17, 68(x15) - lw x18, 72(x15) - lw x19, 76(x15) - lw x20, 80(x15) - lw x21, 84(x15) - lw x22, 88(x15) - lw x23, 92(x15) - lw x24, 96(x15) - lw x25, 100(x15) - lw x26, 104(x15) - lw x27, 108(x15) - lw x28, 112(x15) - lw x29, 116(x15) - lw x30, 120(x15) - lw x31, 124(x15) - addi x15, x15, 124 - add x31, x15, zero - csrrw x15, 0x340, x15 - mret - -store_fault_handler: - lw x1, 4(x15) - lw x2, 8(x15) - lw x3, 12(x15) - lw x4, 16(x15) - lw x5, 20(x15) - lw x6, 24(x15) - lw x7, 28(x15) - lw x8, 32(x15) - lw x9, 36(x15) - lw x10, 40(x15) - lw x11, 44(x15) - lw x12, 48(x15) - lw x13, 52(x15) - lw x14, 56(x15) - lw x15, 60(x15) - lw x16, 64(x15) - lw x17, 68(x15) - lw x18, 72(x15) - lw x19, 76(x15) - lw x20, 80(x15) - lw x21, 84(x15) - lw x22, 88(x15) - lw x23, 92(x15) - lw x24, 96(x15) - lw x25, 100(x15) - lw x26, 104(x15) - lw x27, 108(x15) - lw x28, 112(x15) - lw x29, 116(x15) - lw x30, 120(x15) - lw x31, 124(x15) - addi x15, x15, 124 - add x31, x15, zero - csrrw x15, 0x340, x15 - mret - -ebreak_handler: - csrr x10, mepc - addi x10, x10, 4 - csrw mepc, x10 - lw x1, 4(x15) - lw x2, 8(x15) - lw x3, 12(x15) - lw x4, 16(x15) - lw x5, 20(x15) - lw x6, 24(x15) - lw x7, 28(x15) - lw x8, 32(x15) - lw x9, 36(x15) - lw x10, 40(x15) - lw x11, 44(x15) - lw x12, 48(x15) - lw x13, 52(x15) - lw x14, 56(x15) - lw x15, 60(x15) - lw x16, 64(x15) - lw x17, 68(x15) - lw x18, 72(x15) - lw x19, 76(x15) - lw x20, 80(x15) - lw x21, 84(x15) - lw x22, 88(x15) - lw x23, 92(x15) - lw x24, 96(x15) - lw x25, 100(x15) - lw x26, 104(x15) - lw x27, 108(x15) - lw x28, 112(x15) - lw x29, 116(x15) - lw x30, 120(x15) - lw x31, 124(x15) - addi x15, x15, 124 - add x31, x15, zero - csrrw x15, 0x340, x15 - mret - -illegal_instr_handler: - csrr x10, mepc - addi x10, x10, 4 - csrw mepc, x10 - lw x1, 4(x15) - lw x2, 8(x15) - lw x3, 12(x15) - lw x4, 16(x15) - lw x5, 20(x15) - lw x6, 24(x15) - lw x7, 28(x15) - lw x8, 32(x15) - lw x9, 36(x15) - lw x10, 40(x15) - lw x11, 44(x15) - lw x12, 48(x15) - lw x13, 52(x15) - lw x14, 56(x15) - lw x15, 60(x15) - lw x16, 64(x15) - lw x17, 68(x15) - lw x18, 72(x15) - lw x19, 76(x15) - lw x20, 80(x15) - lw x21, 84(x15) - lw x22, 88(x15) - lw x23, 92(x15) - lw x24, 96(x15) - lw x25, 100(x15) - lw x26, 104(x15) - lw x27, 108(x15) - lw x28, 112(x15) - lw x29, 116(x15) - lw x30, 120(x15) - lw x31, 124(x15) - addi x15, x15, 124 - add x31, x15, zero - csrrw x15, 0x340, x15 - mret - -pt_fault_handler: - nop - -.align 2 -mmode_intr_handler: - csrr x10, 0x300 # MSTATUS; - csrr x10, 0x304 # MIE; - csrr x10, 0x344 # MIP; - csrrc x10, 0x344, x10 # MIP; - lw x1, 4(x15) - lw x2, 8(x15) - lw x3, 12(x15) - lw x4, 16(x15) - lw x5, 20(x15) - lw x6, 24(x15) - lw x7, 28(x15) - lw x8, 32(x15) - lw x9, 36(x15) - lw x10, 40(x15) - lw x11, 44(x15) - lw x12, 48(x15) - lw x13, 52(x15) - lw x14, 56(x15) - lw x15, 60(x15) - lw x16, 64(x15) - lw x17, 68(x15) - lw x18, 72(x15) - lw x19, 76(x15) - lw x20, 80(x15) - lw x21, 84(x15) - lw x22, 88(x15) - lw x23, 92(x15) - lw x24, 96(x15) - lw x25, 100(x15) - lw x26, 104(x15) - lw x27, 108(x15) - lw x28, 112(x15) - lw x29, 116(x15) - lw x30, 120(x15) - lw x31, 124(x15) - addi x15, x15, 124 - add x31, x15, zero - csrrw x15, 0x340, x15 - mret; - -kernel_instr_end: nop -.section .kernel_stack,"aw",@progbits; -.align 2 -kernel_stack_start: -.rept 3999 -.4byte 0x0 -.endr -kernel_stack_end: -.4byte 0x0 diff --git a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_1/test.yaml b/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_1/test.yaml deleted file mode 100644 index e954a5a9db..0000000000 --- a/cv32e40x/tests/programs/custom/riscv_arithmetic_basic_test_1/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: riscv_arithmetic_basic_test_1 -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Basic sanity arithmetic test 1 diff --git a/cv32e40x/tests/programs/custom/riscv_ebreak_test_0/riscv_ebreak_test_0.S b/cv32e40x/tests/programs/custom/riscv_ebreak_test_0/riscv_ebreak_test_0.S deleted file mode 100644 index 9cc66a6384..0000000000 --- a/cv32e40x/tests/programs/custom/riscv_ebreak_test_0/riscv_ebreak_test_0.S +++ /dev/null @@ -1,18057 +0,0 @@ -#include "corev_uvmt.h" -.include "user_define.h" - -.section .text.start -.global _start -.type _start, @function - -_start: - j _start_main - - -.globl _start_main -.section .text -_start_main: - li x0, 0xf21ee7dc - li x1, 0x80000000 - li x2, 0xfd183497 - li x3, 0xccda4374 - li x4, 0x0 - li x5, 0xf4cb539d - li x6, 0x80000000 - li x7, 0x3 - li x8, 0xfdef1f09 - li x9, 0x80000000 - li x10, 0x4 - li x11, 0xf58fad61 - li x12, 0xfb6606db - li x13, 0x0 - li x14, 0xf0cee247 - li x15, 0x0 - li x16, 0xff7811b4 - li x17, 0xf61163af - li x18, 0x0 - li x19, 0x0 - li x20, 0x0 - li x21, 0xc552e854 - li x22, 0xf3ae47cd - li x23, 0xc356d985 - li x24, 0x0 - li x25, 0x80000000 - li x26, 0xaad8efdc - li x27, 0xffa38c28 - li x28, 0xf915a8c7 - li x29, 0x9 - li x30, 0x5 - li x31, 0x5912efde - li x4, 0x40001104 - csrw misa, x4 -kernel_sp: - la x24, _kernel_stack_end - -trap_vec_init: - la x4, mtvec_handler - ori x4, x4, 0 - csrw 0x305, x4 # MTVEC - -mepc_setup: - la x4, _init - csrw mepc, x4 - j init_machine_mode - -_init: - la x2, _user_stack_end -_main: la s1, region_2+5617 #start riscv_load_store_rand_instr_stream_9 - sb s5, 64(s1) - div s2, a2, t4 - andi a2, t6, -398 - or a3, a0, ra - lb t0, 174(s1) - sltiu s6, a3, -222 - c.add t5, t3 - csrrs t3, 0x340, s2 - csrrc a4, 0x340, s9 - addi t4, a3, 802 - c.srli a5, 5 - divu s0, s0, t6 - lb a7, -148(s1) - slli zero, zero, 23 - mul s6, t6, t2 - mulh a2, s10, s7 - lb t5, 88(s1) - andi s2, a5, 363 - csrrs s10, 0x340, s11 - addi a5, t3, -80 - mulh t6, t3, s0 - divu s7, s3, a5 - lb tp, -56(s1) - lbu s6, -121(s1) - sb s10, 152(s1) - lb a6, 96(s1) - csrrc t3, 0x340, zero - c.lui a0, 20 - c.andi a3, -13 - c.and s0, a2 - csrrci t3, 0x340, 29 - and t3, s6, t5 - sb s4, -178(s1) - c.slli s5, 27 - xori t3, t5, -788 - c.mv a2, t1 - sb s4, 164(s1) #end riscv_load_store_rand_instr_stream_9 - la t3, region_3+468 #start riscv_hazard_instr_stream_7 - sb zero, -29(t3) - lbu s11, -7(t3) - c.lui s7, 31 - lb zero, 16(t3) - sh s0, -34(t3) - lbu a1, 25(t3) - srai s11, s0, 24 - lw a1, -20(t3) - csrrw a1, 0x340, s7 - sb s11, -53(t3) - csrrsi s11, 0x340, 8 - lb s0, -63(t3) - srl s7, s0, a4 - c.srai s0, 13 - c.sub s0, a4 - lbu zero, 21(t3) - sw s0, 40(t3) - xor s11, s11, s7 - lhu s11, -12(t3) - lbu a1, 25(t3) - lh a4, -64(t3) - or a4, a1, zero - lbu s11, 25(t3) - lb a1, -16(t3) - lbu a4, 42(t3) - lbu s7, -60(t3) - lb zero, -63(t3) - lb a4, -47(t3) - sb s7, -54(t3) - lhu s7, -60(t3) - sb a4, 7(t3) - lbu s11, -35(t3) - xori s7, s11, 785 - sb s0, -49(t3) - lb zero, 17(t3) - lbu s11, 17(t3) - lb zero, -25(t3) - lb zero, 3(t3) - lbu s7, 9(t3) - lb s7, 30(t3) #end riscv_hazard_instr_stream_7 - la a1, region_2+6211 #start load_store_instr_stream_0 - la t1, region_0+2527 #start load_store_instr_stream_2 - la s10, region_1+10809 #start load_store_instr_stream_1 - sh a0, -3(s10) - lb zero, -2(s10) - lbu s4, -39(a1) - sw s3, -163(t1) - lw s3, -193(s10) - lh a0, -189(t1) - lh t0, 173(s10) - lbu s1, 1(t1) - lb a0, 46(s10) - sb s11, 16(t1) - lhu a5, -37(a1) - lb s0, 59(a1) - sb a3, -137(t1) - sb s9, 83(t1) #end load_store_instr_stream_2 - lhu t0, -135(s10) - lb s3, 31(a1) - lh s4, 41(a1) - lhu s1, -9(s10) - lbu t0, -111(s10) - sb s4, 24(s10) #end load_store_instr_stream_1 - lb s4, 55(a1) #end load_store_instr_stream_0 - la a5, region_4+3214 #start load_store_instr_stream_0 - lhu s0, 162(a5) - la t5, region_1+10813 #start load_store_instr_stream_1 - lbu tp, 193(a5) - sh s7, -917(t5) - lb t4, 86(t5) - lbu t1, -20(a5) - lh s1, -184(a5) - sb t2, -753(t5) - sb t1, 234(a5) - sb t1, 17(a5) - lb s6, -296(t5) - lbu a2, -159(a5) - sb t4, -906(t5) - lhu gp, 265(t5) #end load_store_instr_stream_1 - lbu t0, 63(a5) - lb zero, 115(a5) #end load_store_instr_stream_0 - la a5, region_3+329 #start riscv_hazard_instr_stream_11 - xor s7, tp, s3 - mul t2, s7, s3 - sb t2, -255(a5) - lbu s7, -157(a5) - lb t2, -285(a5) - ori s7, s3, -404 - lbu gp, -228(a5) - slti t2, s7, 372 - sw t2, 95(a5) - lb s7, 52(a5) - c.andi a4, 0 - xor tp, gp, s3 - sb tp, 34(a5) - sh gp, -5(a5) - lh tp, 49(a5) - lb s3, -242(a5) - lui s3, 893729 - mul s7, tp, tp - slti tp, t2, 743 - lw s3, -85(a5) - lbu tp, -208(a5) - lb s7, -36(a5) - sub s7, a4, gp - lb s7, -146(a5) - auipc s7, 957020 - c.li s7, 12 - mul s7, t2, s3 - sub s3, a4, a4 - lbu t2, -125(a5) - sb s7, 116(a5) - sh tp, -135(a5) - c.li a4, 21 - slt s7, gp, t2 - sb t2, -24(a5) - c.xor a4, a4 - lh gp, -135(a5) - lb tp, -173(a5) - .4byte 0x00100073 # ebreak - lhu tp, 181(a5) - slti tp, gp, -96 - lhu s3, -217(a5) - mulhsu tp, gp, a4 - lb t2, -96(a5) #end riscv_hazard_instr_stream_11 - la s10, region_3+266 #start riscv_hazard_instr_stream_5 - lui s1, 886275 - sll t2, a5, a7 - c.xor s1, s1 - c.xor a5, s1 - srl a7, s6, s1 - c.add s2, s1 - lb t2, -234(s10) - csrrci a5, 0x340, 14 - lw t2, 14(s10) - sb s1, -249(s10) - lb a7, 73(s10) - slti a5, s2, -62 - c.mv s6, a7 - lw a5, -162(s10) - lb a5, -48(s10) - lbu a7, 201(s10) - lui s1, 444853 - lbu s6, -210(s10) - sltu s2, t2, s6 - c.mv a5, s2 - slti a5, s1, -643 - or s1, s2, s6 - lbu s6, -135(s10) - rem s1, s1, a5 - csrrsi s2, 0x340, 8 - auipc s1, 518882 - lbu s1, -246(s10) - c.sub a5, a5 - c.slli t2, 6 - sw s6, -226(s10) - c.srai a5, 2 - csrrw t2, 0x340, s2 - lui s1, 170373 - xori a7, s1, -806 - lbu a7, 239(s10) #end riscv_hazard_instr_stream_5 - la a5, region_1+2555 #start riscv_hazard_instr_stream_2 - .4byte 0x00100073 # ebreak - lb t1, 932(a5) - srli t1, t0, 27 - lhu a1, -481(a5) - lbu t1, 391(a5) - c.slli t0, 31 - sh a3, -639(a5) - slli t3, s4, 24 - c.sub a1, a3 - sb t3, -542(a5) - csrrci a3, 0x340, 5 - csrrwi s4, 0x340, 14 - add t1, a3, t0 - lb a1, 86(a5) - mulhu t3, t1, s4 - xori a1, a3, 416 - c.srai a3, 22 - mulhsu t3, a1, a3 - c.add t3, t1 - sb s4, -975(a5) - sltu s4, a1, t0 - div t1, s4, t0 - c.slli t0, 1 - sb t1, -174(a5) - add t0, t1, a1 - lb s4, 302(a5) - lh s4, -997(a5) - divu t0, a3, t0 - ori a1, t3, 689 - lb t1, 782(a5) - lh t3, 29(a5) - xori s4, s4, 662 - srli t0, t3, 17 - lh a3, 637(a5) - mulh t0, s4, s4 - lb a3, -355(a5) #end riscv_hazard_instr_stream_2 - la t3, region_0+1354 #start riscv_hazard_instr_stream_10 - c.sub a1, a0 - rem t5, a1, t5 - sh s10, 72(t3) - lb a7, 83(t3) - c.slli a0, 11 - lui t5, 903409 - sb s7, -213(t3) - c.or a0, a1 - lbu a7, 79(t3) - sh a7, 74(t3) - sub s7, a0, a7 - lb a7, 81(t3) - sb t5, -5(t3) - addi a0, s7, 226 - lw a0, -130(t3) - csrrci s7, 0x340, 13 - sb s10, 37(t3) - sb s10, -57(t3) - csrrw a1, 0x340, s7 - csrrw s7, 0x340, s10 - slli a0, a7, 9 - sb s10, -143(t3) - csrrs t5, 0x340, t5 - lhu a0, -218(t3) - c.or a0, a1 - lw a0, -2(t3) - div t5, s7, a7 - lw a7, 206(t3) - lbu a0, 148(t3) - lb a1, 161(t3) - addi t5, a7, -704 - lw t5, 42(t3) - sh s7, 76(t3) - lb t5, 3(t3) - lbu t5, -231(t3) - lb s10, 59(t3) - sb s7, -186(t3) - sll s7, s10, s10 - sb s7, -44(t3) - srl a0, a1, s10 - sb s7, -13(t3) - sh a7, 88(t3) - c.addi a0, -25 - xor s10, a1, t5 - lbu a1, -23(t3) - c.slli s7, 30 - sub s7, s7, a7 - c.nop - sh s7, 16(t3) - c.andi a1, -19 - sb t5, 1(t3) - c.srli a1, 9 - or t5, a1, a0 - lb a1, 226(t3) #end riscv_hazard_instr_stream_10 - la s4, region_2+4179 #start load_store_instr_stream_0 - la t3, region_2+4157 #start load_store_instr_stream_2 - la t5, region_2+1993 #start load_store_instr_stream_3 - la s0, region_2+3803 #start load_store_instr_stream_4 - la a0, region_2+5855 #start load_store_instr_stream_1 - lh s3, 57(s4) - sh s6, -29(t5) - sb s1, -246(t3) - sb t0, 75(a0) - lb s2, 600(s0) - lh gp, -55(s4) - lb s3, 494(s0) - sb s9, -116(a0) - sb t3, 309(t3) - lh a2, 39(s0) - lb a4, -57(s4) - sh s0, -37(s4) - sw s10, -137(t5) - lbu s10, 28(s4) - sb a2, 210(t5) - lb a6, 302(s0) - lbu s1, -696(t3) - sb s2, -182(t5) - lw t4, 125(a0) - lbu a5, 141(t5) - lh s1, 199(a0) - lh t6, 63(s4) - lb s7, -141(t5) - lb gp, -236(t5) - sb t1, -824(t3) - sb s7, -79(a0) - sb s4, 71(t5) - lhu s3, 767(t3) - lbu a6, -49(a0) - lhu ra, 43(s4) - lbu t6, -94(a0) - sb ra, -3(t5) - sb a7, -30(s4) - sw t4, 57(a0) - lbu s11, 167(t3) - sh s2, 321(t3) #end load_store_instr_stream_2 - lbu gp, -140(a0) #end load_store_instr_stream_1 - sh s10, -63(s4) - lb s3, -278(s0) - lhu s6, -1(t5) #end load_store_instr_stream_3 - lh a3, 435(s0) - lb a3, -944(s0) - lbu s2, 560(s0) #end load_store_instr_stream_4 - lbu t0, -56(s4) #end load_store_instr_stream_0 - la a0, region_1+2305 #start riscv_load_store_rand_instr_stream_10 - lui s6, 564656 - lb zero, 53(a0) - ori a3, t3, -858 - lb a7, -35(a0) - lbu a6, 10(a0) - sb s10, -46(a0) - addi gp, gp, -721 - slli s11, ra, 3 - add a3, s10, t0 - lui s3, 716353 - csrrc s1, 0x340, s5 - lb a3, -22(a0) - sb sp, -12(a0) - srl a1, t0, s0 - lb a7, 38(a0) - nop - slti s5, s2, 623 - sltu s5, s10, t6 - csrrwi tp, 0x340, 20 - auipc zero, 769520 - csrrw s1, 0x340, s2 - slti s0, s3, 550 - sb t0, 62(a0) - lbu ra, -49(a0) - nop - csrrci zero, 0x340, 17 - lb s2, 63(a0) - mulh t4, s0, a2 - lb a3, 36(a0) - or t6, a4, s0 - or a3, tp, s11 - lh gp, -23(a0) - sltiu s1, s9, 414 - c.nop - lb s3, -38(a0) - sb zero, -34(a0) - slt s7, sp, ra - sltiu s1, a4, 737 - lbu a6, -10(a0) - mulhu s1, t1, s1 - csrrw s5, 0x340, t3 - mulh a7, tp, s4 - srai tp, s3, 17 - sb s5, 44(a0) - sltu t6, a7, a7 - lb s7, -41(a0) #end riscv_load_store_rand_instr_stream_10 - addi t3, zero, 10 #init loop 0 counter - remu s1, s7, t6 - addi a3, zero, 10 #init loop 0 limit -main_50_0_t: xor s7, zero, t3 - slt tp, s10, t1 - addi t3, t3, -2 #update loop 0 counter - mulh t6, t4, s2 - bge t3, a3, main_50_0_t #branch for loop 0 - c.xor a2, a5 - la a2, region_4+2940 #start riscv_hazard_instr_stream_3 - sb a1, -10(a2) - c.ebreak;c.nop; - lhu s2, 2(a2) - mulhu a1, s2, t5 - lui s2, 901457 - and t6, t5, a5 - sb a1, 1(a2) - lb zero, 15(a2) - c.andi a5, -31 - sb a1, 11(a2) - sltu a5, t5, a5 - sw zero, 8(a2) - sb t5, 11(a2) - lbu a5, -9(a2) - sb t6, 9(a2) - slti t5, s2, 331 - .4byte 0x00100073 # ebreak - csrrsi a5, 0x340, 20 - c.lw a5, 4(a2) - sb a1, -13(a2) - mul s2, s2, t5 - c.and a5, a1 - lbu s2, 9(a2) - lbu zero, 14(a2) - lhu a1, -2(a2) - sb s2, -5(a2) - sb s2, 16(a2) - lh a5, -14(a2) - sw t5, 8(a2) #end riscv_hazard_instr_stream_3 -main_17: jal gp, 8f -0: c.j 18f -1: jal gp, 14f -2: c.jal 17f -3: c.jal 19f -4: c.j 12f -5: c.jal 4b -6: jal ra, 10f -7: c.jal 15f -8: c.j 1b -9: c.jal 3b -10: jal gp, 2b -11: jal ra, 7b -12: jal ra, 0b -13: c.j 20f -14: c.j 13b -15: jal t1, 9b -16: c.jal 5b -17: c.jal 11b -18: jal ra, 6b -19: c.j 21f -20: c.jal 16b -21: div a7, a3, s3 - la t2, region_4+1075 #start load_store_instr_stream_2 - la gp, region_1+6840 #start load_store_instr_stream_0 - lbu s2, 34(gp) - la s0, region_2+5224 #start load_store_instr_stream_1 - sh s5, 26(s0) - lhu s1, -46(gp) - lbu a0, -51(gp) - lbu s2, -12(t2) - lw t0, -3(t2) - sb s5, -27(s0) - sb s0, 0(t2) - lb s7, -11(t2) - lh t0, 12(s0) - lhu s4, -5(t2) - sb gp, -8(gp) - sb ra, 9(t2) - sb s3, -21(s0) - lbu t6, -7(s0) #end load_store_instr_stream_1 - sb a7, -12(t2) - sh s7, 5(t2) - sb a6, -59(gp) - lb zero, 0(t2) - lhu a6, -60(gp) - lb a7, 41(gp) - sb t2, -7(t2) #end load_store_instr_stream_2 - lbu s5, 33(gp) - lb t3, 29(gp) #end load_store_instr_stream_0 - la s0, region_3+27 #start riscv_hazard_instr_stream_6 - lbu a0, 2(s0) - lhu a4, 5(s0) - sll s6, t1, t1 - lh a3, 9(s0) - sb s6, 10(s0) - sb a3, -8(s0) - sw a4, -15(s0) - lhu a4, -7(s0) - sw a0, 5(s0) - slt a0, a3, a0 - lb t1, 10(s0) - lbu s7, 0(s0) - lhu a0, -1(s0) - lbu a0, 12(s0) - lbu s7, 4(s0) - mulhu a0, s7, a4 - lhu a0, 9(s0) - lbu t1, 4(s0) - and s6, a0, t1 - sb a0, 0(s0) - sltiu s6, s6, 1002 - lbu s7, -11(s0) - sw a4, 9(s0) - c.slli a0, 3 - lbu a3, 2(s0) - c.lui t1, 18 - mulhsu a3, s7, a3 - lhu a4, -7(s0) - lhu a0, -7(s0) - lh s6, -3(s0) - lb a4, -2(s0) - lb a4, -12(s0) - div a0, s6, s7 - sb a0, -8(s0) - sh s6, -13(s0) - lb s6, 10(s0) - sb t1, 6(s0) - div s7, a0, a3 - sb s7, 14(s0) #end riscv_hazard_instr_stream_6 - la s6, region_0+3981 #start load_store_instr_stream_2 - la t3, region_0+805 #start load_store_instr_stream_1 - lh a1, 3(t3) - lbu a5, -84(s6) - la s11, region_0+2587 #start load_store_instr_stream_3 - lbu t1, 2(s11) - lbu a0, 14(t3) - lbu t1, -13(s11) - sb s3, -6(s11) - lh a7, 77(s6) - lbu a5, 46(s6) - la s5, region_0+589 #start load_store_instr_stream_0 - sb s11, 148(t3) - lbu a1, -110(s6) - lh a1, 1(s5) - lbu gp, -127(s6) - lh t0, -137(t3) - lbu s3, -194(t3) - lb a3, 13(s5) - lb a6, 6(s6) - lb s3, 23(t3) - lbu t0, -114(s6) - lw s4, -253(t3) - lb ra, 14(s6) - lbu t4, 8(s5) - lw a7, -9(s6) #end load_store_instr_stream_2 - lbu s0, 202(t3) - lbu tp, -2(s11) - lbu t0, -9(s5) - lb a7, 193(t3) - lbu s1, -164(t3) #end load_store_instr_stream_1 - lbu s0, -15(s5) - lb t1, 8(s11) #end load_store_instr_stream_3 - lbu a0, 4(s5) #end load_store_instr_stream_0 - la a2, region_0+2360 #start load_store_instr_stream_1 - la a5, region_0+1901 #start load_store_instr_stream_2 - lh s1, 6(a2) - lbu gp, -5(a5) - la s2, region_0+3225 #start load_store_instr_stream_3 - la s6, region_0+55 #start load_store_instr_stream_4 - lb t3, -46(s2) - la s11, region_0+121 #start load_store_instr_stream_0 - lbu s0, -13(a5) - lbu a0, -54(s6) - lhu s5, 9(s11) - lbu t6, 6(a2) - lbu gp, -2(a5) - sh a1, -29(s6) - lb s10, -11(s11) - lb t2, -8(s6) - lhu t2, 12(a2) - sh a5, -37(s6) - lh t1, -3(s2) - sw t3, 11(a5) - lw t0, 21(s6) - lb s3, 30(s2) - lb a0, 12(s11) - lb a3, 14(s2) - lbu t5, -16(a5) - lhu gp, -33(s6) - lbu tp, 50(s2) - sb s7, -10(s6) - lbu t5, -11(a5) - lbu s4, -4(a5) - sb zero, -54(s2) - lb t4, 0(a2) - lb s5, -6(s2) - lb a6, 14(s11) - lh s5, 10(a2) #end load_store_instr_stream_1 - sb gp, -3(a5) - lbu s1, 0(s6) - sb t3, -7(s2) #end load_store_instr_stream_3 - sh tp, -3(a5) - sb t6, 1(s11) - sb s2, 50(s6) - sw s8, -1(a5) #end load_store_instr_stream_2 - lh ra, -43(s6) #end load_store_instr_stream_4 - lbu t2, 8(s11) #end load_store_instr_stream_0 -main_21: jal gp, 19f -0: jal ra, 3f -1: c.j 7f -2: jal t1, 1b -3: jal ra, 11f -4: jal t1, 9f -5: c.jal 21f -6: jal s11, 10f -7: c.j 14f -8: jal ra, 4b -9: c.j 23f -10: jal t2, 15f -11: c.jal 2b -12: c.jal 6b -13: jal gp, 18f -14: c.jal 16f -15: c.j 0b -16: c.jal 22f -17: c.j 20f -18: jal s3, 8b -19: c.j 5b -20: jal ra, 12b -21: jal t1, 17b -22: c.jal 13b -23: mulh t5, a6, sp - la s3, region_1+4597 #start load_store_instr_stream_0 - sb s5, -48(s3) - la t4, region_0+816 #start load_store_instr_stream_1 - lb s4, 54(s3) - sb ra, -237(t4) - lhu t3, -31(s3) - sw a2, 56(t4) - lbu a5, -20(s3) - lb s6, 8(s3) - sb tp, 119(t4) - lbu s7, -24(s3) - sh a4, 27(s3) - lhu a5, -174(t4) - lbu t2, -61(s3) - lhu t0, -256(t4) #end load_store_instr_stream_1 - lbu t6, -3(s3) #end load_store_instr_stream_0 - la t6, region_4+3054 #start load_store_instr_stream_0 - la s7, region_1+16141 #start load_store_instr_stream_1 - la tp, region_3+374 #start load_store_instr_stream_2 - lb a0, 62(t6) - lh s5, 614(t6) - lbu a6, -973(t6) - sb s6, 16(tp) - lb s6, -3(s7) - lh ra, 44(tp) - lb s3, 99(t6) - lbu zero, 16(s7) - lhu a5, 20(tp) - sb s7, 4(s7) - sh t5, -32(tp) - lb ra, -153(t6) - lhu a6, 7(s7) - sb t4, -4(s7) - lhu s1, 1(s7) - sb zero, -61(tp) - sb a5, 941(t6) - lbu s6, -24(tp) - lw s11, -1(s7) - lbu s4, 13(tp) - lbu a0, 381(t6) - lb a3, 2(s7) - lb s10, -14(s7) - lbu s5, 34(tp) - lbu t2, 25(tp) #end load_store_instr_stream_2 - lb s5, 10(s7) #end load_store_instr_stream_1 - lb a6, 897(t6) #end load_store_instr_stream_0 -main_23: jal gp, 7f -0: jal ra, 2f -1: jal ra, 28f -2: c.j 23f -3: c.jal 16f -4: c.jal 6f -5: jal t1, 14f -6: jal ra, 22f -7: c.j 27f -8: c.jal 13f -9: c.j 0b -10: c.j 25f -11: jal t1, 8b -12: c.jal 21f -13: c.j 10b -14: jal s11, 1b -15: c.jal 26f -16: jal t1, 9b -17: c.jal 24f -18: jal ra, 11b -19: jal ra, 3b -20: jal t1, 5b -21: jal a0, 20b -22: jal t1, 12b -23: jal ra, 18b -24: jal tp, 4b -25: jal ra, 17b -26: c.jal 19b -27: c.j 15b -28: divu s7, t5, s11 -main_12: jal gp, 9f -0: jal s5, 12f -1: c.j 3f -2: jal ra, 6f -3: c.jal 15f -4: jal s4, 17f -5: jal t1, 21f -6: c.j 4b -7: c.jal 1b -8: jal ra, 11f -9: c.jal 8b -10: jal ra, 2b -11: jal t1, 0b -12: c.jal 16f -13: jal ra, 14f -14: c.j 22f -15: jal tp, 19f -16: c.jal 5b -17: jal ra, 18f -18: jal t1, 20f -19: jal t1, 10b -20: c.jal 13b -21: c.j 7b -22: csrrwi s1, 0x340, 2 - la a7, region_1+6463 #start load_store_instr_stream_1 - la t5, region_2+5260 #start load_store_instr_stream_2 - lbu s3, -3(t5) - sb t6, -49(a7) - sb s3, -44(a7) - sb gp, -28(a7) - la s0, region_4+3392 #start load_store_instr_stream_0 - lbu t6, -7(t5) - lb a5, -15(t5) - lbu a4, 2(a7) - lbu s7, -175(s0) - sw t1, -12(t5) - lb s5, 45(a7) - lbu s4, -11(t5) - lh tp, 15(a7) - sw a7, -35(a7) - lb t0, -245(s0) - lb s3, 11(t5) #end load_store_instr_stream_2 - lbu s1, 168(s0) - lbu a1, 137(s0) - lbu a5, -61(a7) - sh s8, 13(a7) - lb s4, 33(a7) #end load_store_instr_stream_1 - lhu s11, 202(s0) #end load_store_instr_stream_0 - la a0, region_4+469 #start load_store_instr_stream_2 - la t1, region_4+959 #start load_store_instr_stream_1 - la s5, region_4+3010 #start load_store_instr_stream_0 - lb gp, -91(a0) - lb t2, 31(t1) - sb t2, -3(s5) - lb s11, -5(s5) - lbu a5, 56(t1) - sb a5, 5(s5) - sb a1, -9(s5) - sb s0, -134(a0) - lbu s7, 42(t1) - sb tp, -106(a0) - lhu t2, 16(s5) - sw zero, -43(t1) - lb t2, 28(t1) - sb t4, 120(a0) - sh s6, -175(a0) - sw zero, 75(a0) #end load_store_instr_stream_2 - sh a7, -17(t1) - lbu a2, -15(s5) - lw zero, -63(t1) #end load_store_instr_stream_1 - lbu ra, -16(s5) #end load_store_instr_stream_0 - la ra, region_0+1926 #start load_store_instr_stream_3 - la s6, region_0+3511 #start load_store_instr_stream_1 - la a1, region_0+3106 #start load_store_instr_stream_2 - lb a5, 40(s6) - la s11, region_0+153 #start load_store_instr_stream_0 - lbu a3, -21(s6) - sb t2, -18(s6) - sw s5, -27(s6) - sb t5, -49(ra) - sb tp, -50(s11) - lh gp, 5(s11) - lbu t0, -135(ra) - sb a3, -9(a1) - lb t4, -42(s11) - lbu a4, -48(s6) - lbu a0, -9(a1) - lb s0, -88(ra) - lw t5, 138(ra) - lbu t1, -43(s11) - lb tp, 11(a1) - lb a5, -60(s6) - sb a6, 13(a1) - lhu a6, -14(a1) - sb ra, 20(s6) - lbu a3, -31(ra) #end load_store_instr_stream_3 - sb t6, 10(a1) - lb s4, 8(s6) #end load_store_instr_stream_1 - lbu s10, -3(a1) - lh tp, -25(s11) - sb s6, -45(s11) - sb a1, -16(a1) #end load_store_instr_stream_2 - lb t1, 9(s11) #end load_store_instr_stream_0 -main_14: jal gp, 5f -0: c.j 4f -1: c.j 7f -2: jal ra, 16f -3: jal ra, 17f -4: c.j 9f -5: c.jal 6f -6: jal ra, 11f -7: jal ra, 14f -8: c.jal 18f -9: jal ra, 8b -10: jal a0, 2b -11: c.jal 13f -12: jal ra, 15f -13: jal ra, 1b -14: c.j 3b -15: c.jal 0b -16: c.jal 12b -17: c.j 10b -18: sltu s10, s11, a2 - la s10, region_3+12 #start riscv_load_store_rand_instr_stream_1 - ori t2, s7, 971 - c.ebreak;c.nop; - c.andi a3, 9 - sh s4, -8(s10) - .4byte 0x00100073 # ebreak - mul s5, s3, tp - or s4, s8, s4 - csrrw gp, 0x340, s11 - lb a1, 15(s10) - lb t2, 4(s10) - andi s3, tp, -498 - addi t2, t3, -384 - c.add s3, s9 - xor s6, a6, zero - sll s4, s8, a3 - c.nop - slti t3, t4, 476 - sb s8, -4(s10) - sb tp, -6(s10) - rem gp, s9, zero - c.nop - lh s2, 8(s10) - srai a5, zero, 21 - lbu a5, -6(s10) - lui a4, 109413 - lui t5, 40312 - lh s2, -8(s10) - addi a2, s9, -184 - lui zero, 921504 - lh a7, -2(s10) - lbu a5, -6(s10) - lbu t2, 14(s10) - lh a0, -10(s10) - slti s11, s8, 890 - csrrs s4, 0x340, a2 - sw t0, -8(s10) - rem a3, s6, s10 - mulhsu a3, gp, s0 - c.slli s2, 20 - sh a6, -2(s10) - c.li s2, 24 - lb a0, 3(s10) - lb tp, -9(s10) - divu a3, a4, s7 - sb s9, -5(s10) #end riscv_load_store_rand_instr_stream_1 - la s4, region_2+4149 #start riscv_hazard_instr_stream_1 - sb a4, 4(s4) - lbu s2, -8(s4) - c.andi a4, -7 - lb s2, -12(s4) - lb a4, 7(s4) - c.li s2, -27 - sll t6, s2, t5 - lui s2, 391195 - c.addi a4, 15 - sb s2, 5(s4) - lb t5, 2(s4) - srl s2, s2, a5 - c.slli t6, 5 - lbu s2, -7(s4) - csrrsi t5, 0x340, 7 - sh a7, 3(s4) - lb t5, -12(s4) - sltiu a5, s2, -313 - or a7, s2, t6 - lbu a4, -6(s4) - sb s2, -10(s4) - sw a4, 3(s4) - lbu a5, 6(s4) - c.srai a5, 27 - csrrci a4, 0x340, 23 - sb s2, 2(s4) - lbu a5, -3(s4) - sb t5, -16(s4) - mul a4, a7, a5 - lbu s2, -8(s4) - lh a7, -15(s4) - slt s2, s2, t5 - sb a4, -14(s4) - lb t6, 12(s4) - rem s2, a5, s2 - mulhsu a4, a7, t6 - lbu a4, -1(s4) - ori s2, t5, -910 - lb t6, 16(s4) - lbu t5, 16(s4) - sw s2, -9(s4) - c.addi s2, 11 - sw a4, 3(s4) - lbu t5, 0(s4) - c.ebreak;c.nop; - slli a4, a7, 4 - lhu t5, 7(s4) - div t6, s2, s2 - slli a4, t6, 25 - auipc a5, 27481 - srai a7, t5, 16 - nop - mulh a5, a5, t6 - sb a5, 9(s4) - lbu a5, 2(s4) #end riscv_hazard_instr_stream_1 - la ra, region_0+1961 #start riscv_load_store_rand_instr_stream_7 - and t2, a0, s3 - c.slli s11, 27 - sb tp, -52(ra) - sb s1, 39(ra) - c.nop - srli s7, tp, 7 - lh a2, -63(ra) - lb t1, -64(ra) - lb a2, -45(ra) - sb s10, -53(ra) - lh s7, -27(ra) - sb zero, -5(ra) - lb s7, -56(ra) - lbu s6, -38(ra) - or a1, t6, a0 - sra s7, s5, a0 - csrrsi s4, 0x340, 20 - csrrs s5, 0x340, s10 - sub a2, sp, a1 - addi t0, a2, 515 - lbu s2, -7(ra) #end riscv_load_store_rand_instr_stream_7 -main_19: jal gp, 6f -0: c.j 5f -1: jal t0, 10f -2: c.jal 1b -3: c.j 0b -4: jal ra, 8f -5: c.j 11f -6: c.jal 2b -7: jal ra, 9f -8: c.j 12f -9: jal ra, 3b -10: jal s6, 7b -11: c.jal 4b -12: sltiu t3, s1, 580 -main_22: jal gp, 2f -0: jal t1, 3f -1: jal ra, 18f -2: c.jal 17f -3: c.jal 19f -4: c.j 7f -5: c.j 20f -6: jal t2, 15f -7: c.jal 14f -8: jal ra, 12f -9: jal ra, 6b -10: jal ra, 16f -11: jal s3, 5b -12: c.jal 1b -13: c.j 21f -14: jal ra, 0b -15: c.jal 4b -16: jal ra, 9b -17: jal t2, 11b -18: c.jal 13b -19: c.j 8b -20: jal t0, 10b -21: mulhu s11, a7, t4 - la t3, region_2+1119 #start riscv_hazard_instr_stream_4 - mulh a7, t1, t1 - lbu t1, -135(t3) - lbu t1, -24(t3) - sw t1, -23(t3) - lb t1, 181(t3) - lhu a0, 69(t3) - c.li s6, 2 - lbu a2, 2(t3) - lb t1, 247(t3) - or a7, a7, a0 - sb s6, 190(t3) - c.srai a0, 31 - c.xor a2, a2 - auipc a0, 723358 - remu a2, s0, a0 - sh s6, -91(t3) - xor a7, a7, s0 - lbu a2, -92(t3) - c.srai s0, 31 - c.mv s6, t1 - lbu s0, 140(t3) - c.xor a2, s0 - sb s0, -160(t3) - srl a7, t1, a7 - sltu a2, t1, a2 - sh s0, -181(t3) #end riscv_hazard_instr_stream_4 - addi t4, zero, 8 #init loop 0 counter - addi a4, zero, 8 #init loop 0 limit - csrrs a3, 0x340, a2 - c.add s7, t4 -main_54_0_t: slti a2, s9, -609 - addi t4, t4, -5 #update loop 0 counter - sll s2, t1, s7 - bgeu t4, a4, main_54_0_t #branch for loop 0 - srli a3, s0, 0 - la a0, region_2+6978 #start load_store_instr_stream_1 - sb s4, -889(a0) - la s7, region_2+636 #start load_store_instr_stream_2 - la s0, region_2+6608 #start load_store_instr_stream_0 - lh t5, 232(s7) - sb s8, 56(s7) - lbu s4, -21(s0) - lbu t0, -33(s0) - lb t4, -31(s0) - lb s11, -431(a0) - sh t5, -64(s7) - lw a2, -208(s7) - lhu a7, 98(s7) - lbu s1, -15(s0) - lh s6, 206(s7) - lbu ra, 289(a0) - lb gp, -859(a0) - sb t3, 109(s7) - sb t1, 51(s0) - sb s2, 95(a0) - lbu a5, 595(a0) - lbu t1, 39(s0) - sb t5, 178(s7) - sb a4, -984(a0) #end load_store_instr_stream_1 - sb sp, -65(s7) - lh a5, 118(s7) #end load_store_instr_stream_2 - lw s2, -8(s0) #end load_store_instr_stream_0 - la t4, region_3+406 #start load_store_instr_stream_1 - la s3, region_0+2690 #start load_store_instr_stream_0 - lh zero, -32(t4) - la s11, region_2+7566 #start load_store_instr_stream_2 - lb a4, 229(s11) - lbu zero, 25(t4) - lbu gp, -19(t4) - sh a3, 36(s3) - sb s8, 15(t4) - lbu gp, 220(s11) - lb zero, -44(t4) - lhu t2, 186(s11) - lb s0, -616(s3) - lbu a0, -696(s3) - sb a4, 61(t4) - sh t0, 20(s11) - lbu t1, 479(s3) - lbu s7, -35(t4) - lw t5, 62(s3) - sh a4, -58(t4) - sb a7, -681(s3) - lb t2, 13(s11) - lbu t5, 41(s11) #end load_store_instr_stream_2 - lb s4, -149(s3) - sb s0, 39(t4) - sw s1, 482(s3) - sb a1, -698(s3) - lbu t3, -18(t4) #end load_store_instr_stream_1 - sb s6, 192(s3) #end load_store_instr_stream_0 - la a5, region_4+3106 #start riscv_hazard_instr_stream_8 - srai t6, s2, 21 - c.and a4, a4 - nop - sb t4, 3(a5) - lb a4, -8(a5) - remu s2, s2, s3 - sb a7, -5(a5) - csrrw a7, 0x340, a7 - slli s2, t4, 5 - srli a4, s3, 27 - c.add t6, t6 - sh a7, 8(a5) - csrrs a4, 0x340, a7 - remu s2, a7, a4 - sll t4, t6, t4 - lb a4, -3(a5) - srli t4, a4, 16 - andi s2, s3, 464 - sw t4, 2(a5) - slt a7, t4, a7 - sb a7, 15(a5) - lb a4, 13(a5) - lhu a4, 4(a5) - sb a7, -4(a5) - sh a4, 0(a5) - lbu s2, -11(a5) - c.or a4, a4 - lbu t4, -9(a5) - sb s3, -9(a5) - sb t4, 10(a5) - c.li a7, -4 - c.add s3, a4 - xor a7, s2, s2 - lbu a7, -4(a5) - sub s3, a4, t6 - srai s3, a7, 29 - .4byte 0x00100073 # ebreak - csrrsi t4, 0x340, 6 - c.and a4, a4 - sb t4, 9(a5) - srli t6, t6, 13 - mulhu s2, a7, s3 - lb s2, -3(a5) - csrrs a7, 0x340, t4 - c.nop - sb t4, -12(a5) - mulhsu s3, t4, s2 - nop - c.ebreak;c.nop; - lb t6, 1(a5) #end riscv_hazard_instr_stream_8 - la a7, region_1+13938 #start riscv_load_store_rand_instr_stream_4 - divu zero, t6, t1 - lb s11, -7(a7) - auipc t3, 936229 - lb a4, 9(a7) - sb s0, -15(a7) - sll s7, s8, s0 - lbu gp, 7(a7) - .4byte 0x00100073 # ebreak - c.add s4, sp - lbu s10, -3(a7) - add ra, a2, a0 - lb a4, 12(a7) - mulh s10, s11, t4 - c.addi t5, -17 - lb t6, 12(a7) - lhu a2, -12(a7) - lb s10, -3(a7) - lhu a2, 4(a7) - c.srli a1, 22 - xor ra, zero, s6 - lui t6, 753310 - csrrci a1, 0x340, 27 - c.srli a0, 31 - sb s4, -12(a7) - xor s10, s4, t4 - lb a4, 7(a7) #end riscv_load_store_rand_instr_stream_4 - addi t5, zero, -8 #init loop 0 counter - c.or a1, a3 - c.and a0, a3 - nop - addi s6, zero, -7 #init loop 0 limit - xori t0, ra, 468 - remu a3, a5, t3 - remu a6, sp, sp - c.nop - c.ebreak;c.nop; - csrrsi s1, 0x340, 27 -main_53_0_t: c.slli a0, 29 - nop - c.sub a0, a0 - slti s0, s9, -42 - c.and a4, a4 - c.srli a2, 15 - nop - sll s5, a6, s3 - csrrc t2, 0x340, s1 - addi t5, t5, 2 #update loop 0 counter - c.sub a3, a5 - slt a2, t1, s6 - blt t5, s6, main_53_0_t #branch for loop 0 - c.addi a4, -21 - addi t4, zero, 9 #init loop 0 counter - lui s3, 241177 - mulhsu a3, s9, a2 - addi s2, zero, -8 #init loop 0 limit - slti a2, a4, -639 - xori s10, s8, 983 - csrrc t2, 0x340, t1 - c.srli s0, 6 - c.andi s0, -18 -main_55_0_t: c.andi s0, 23 - c.srai a5, 2 - c.lui a2, 25 - or s6, ra, s2 - c.and a5, a4 - auipc s1, 612956 - c.slli gp, 9 - addi t4, t4, -5 #update loop 0 counter - mulhsu zero, s4, s9 - c.and a5, a3 - lui s4, 1036049 - sra zero, s8, a5 - bge t4, s2, main_55_0_t #branch for loop 0 - auipc t0, 812467 - la t4, region_3+501 #start riscv_load_store_rand_instr_stream_11 - c.andi s1, 15 - rem tp, a3, a1 - divu s0, s4, a1 - lbu s11, -178(t4) - c.srai a2, 2 - c.add s4, s8 - addi tp, ra, -153 - sh s5, -219(t4) - lh a3, -61(t4) - csrrw t3, 0x340, s4 - and a6, t6, t4 - csrrc gp, 0x340, s9 - lh a7, -67(t4) - csrrs s11, 0x340, s8 - lhu t3, -477(t4) - lbu a0, -334(t4) - sb s9, -177(t4) - lhu s11, -407(t4) - lhu zero, -181(t4) - sb zero, -346(t4) - lh s1, -103(t4) - sh t6, -161(t4) - c.srai a2, 21 - c.li s7, -14 - sh a4, -59(t4) - sb t2, -297(t4) - lb s1, 10(t4) - lhu a4, -35(t4) - lbu s1, -292(t4) - sh a0, -103(t4) - lb s7, -90(t4) - mulhu tp, sp, s3 - sb s11, -36(t4) - sb s11, -500(t4) - csrrc ra, 0x340, t1 - sb a2, -304(t4) - lb s7, -402(t4) - csrrsi s0, 0x340, 2 - rem s3, s11, s8 - sh a0, -269(t4) - lh t1, -303(t4) - csrrci t1, 0x340, 28 - mul s5, t1, s10 - .4byte 0x00100073 # ebreak - lh t2, -221(t4) - lbu t2, -264(t4) #end riscv_load_store_rand_instr_stream_11 - la a2, region_1+16367 #start load_store_instr_stream_1 - la t5, region_0+206 #start load_store_instr_stream_0 - lbu s11, -224(a2) - sb t0, 6(a2) - lbu s10, -130(a2) - la a3, region_4+58 #start load_store_instr_stream_2 - lb a6, -632(t5) - sb a7, -26(a2) - lw tp, -51(a2) - lhu t1, -16(a3) - sb a2, 206(t5) - lb tp, 21(a3) - sb s2, -81(t5) - sb s0, -118(a2) - la s4, region_2+51 #start load_store_instr_stream_3 - sw tp, 181(s4) - lb s1, -886(t5) - lbu a6, -102(a2) - lb zero, 244(s4) - sb a4, -16(s4) - lb t6, 63(a3) - sb s7, -40(a3) - sh a1, -189(a2) - lb gp, 206(s4) - lbu s1, 27(s4) - sb s10, -248(a2) #end load_store_instr_stream_1 - lhu t4, 123(s4) - sh t3, -40(a3) - lbu a6, 236(s4) #end load_store_instr_stream_3 - sb s1, 515(t5) - sh t3, -2(a3) - sb t1, 60(a3) - lb s10, 15(a3) #end load_store_instr_stream_2 - lbu s6, 687(t5) #end load_store_instr_stream_0 - la a3, region_0+2070 #start riscv_hazard_instr_stream_9 - lbu t6, 1(a3) - srli a7, gp, 20 - lb gp, -7(a3) - lb a5, -1(a3) - lbu a1, -13(a3) - ori a1, gp, 242 - csrrwi a7, 0x340, 24 - mulh a7, a1, gp - csrrw a7, 0x340, s1 - lh a5, 4(a3) - lbu s1, -13(a3) - csrrci s1, 0x340, 15 - lbu a7, -5(a3) - c.mv a7, a5 - lb a7, -4(a3) - lbu a7, -2(a3) - lbu a7, -3(a3) - lbu s1, -10(a3) - lb gp, 12(a3) - lbu a1, 4(a3) - nop - nop - lb s1, 9(a3) - xor s1, a5, gp - mulh a5, a7, a5 - lbu s1, 3(a3) - auipc gp, 211427 - lbu gp, -6(a3) #end riscv_hazard_instr_stream_9 - addi tp, zero, -8 #init loop 1 counter - csrrs ra, 0x340, t2 - csrrsi a2, 0x340, 30 - slli zero, a3, 16 - .4byte 0x00100073 # ebreak - add s6, a2, t2 - c.ebreak;c.nop; - addi t1, zero, 8 #init loop 1 limit - sll s11, a3, a5 -main_49_1_t: csrrsi a1, 0x340, 14 - csrrwi t0, 0x340, 28 - andi s11, tp, 775 - srai s11, a4, 22 - addi tp, tp, 9 #update loop 1 counter - addi s2, zero, -8 #init loop 0 counter - addi a7, zero, -15 #init loop 0 limit - c.mv s3, sp - c.li s5, 5 - csrrw t4, 0x340, t5 - srai a6, a4, 21 - remu zero, s9, a1 -main_49_0_t: csrrci s3, 0x340, 1 - addi s2, s2, -6 #update loop 0 counter - c.mv a2, t0 - sltiu s0, a2, 481 - bge s2, a7, main_49_0_t #branch for loop 0 - rem a2, s11, a5 - bltu tp, t1, main_49_1_t #branch for loop 1 - srai s10, t6, 20 - la s1, region_1+2219 #start load_store_instr_stream_1 - la t2, region_1+10841 #start load_store_instr_stream_2 - lbu a1, 32(t2) - la gp, region_1+15168 #start load_store_instr_stream_0 - lbu ra, 527(gp) - lbu a6, -157(s1) - lbu s2, -937(gp) - lb a3, -54(t2) - lbu a0, -12(s1) - lb s5, -82(s1) - lhu a3, 41(t2) - lb s4, 150(s1) - lb zero, -33(t2) - lh t6, 386(gp) - lbu a3, -342(gp) - lb s2, -41(t2) #end load_store_instr_stream_2 - lb tp, -26(s1) - lb s4, 923(gp) - lbu t4, -120(s1) - lb s2, -70(s1) #end load_store_instr_stream_1 - lb s7, 816(gp) - lbu tp, 15(gp) #end load_store_instr_stream_0 - addi s5, zero, 10 #init loop 1 counter - c.lui s11, 19 - addi a6, zero, 6 #init loop 1 limit - sltu a7, a6, ra - c.srli a1, 30 -main_56_1_t: auipc zero, 30332 - addi s5, s5, -8 #update loop 1 counter - c.nop - addi t2, zero, 4 #init loop 0 counter - or a1, t3, sp - c.li t5, -18 - c.or a4, s0 - addi t6, zero, -16 #init loop 0 limit -main_56_0_t: .4byte 0x00100073 # ebreak - c.ebreak;c.nop; - addi t2, t2, -10 #update loop 0 counter - c.ebreak;c.nop; - c.addi s0, -20 - bge t2, t6, main_56_0_t #branch for loop 0 - lui a4, 321774 - bge s5, a6, main_56_1_t #branch for loop 1 - sltu ra, t4, a6 -main_15: jal gp, 16f -0: jal ra, 20f -1: jal ra, 5f -2: c.j 10f -3: jal ra, 7f -4: c.j 0b -5: jal t4, 2b -6: jal a4, 19f -7: jal t1, 27f -8: jal s1, 12f -9: c.jal 24f -10: c.j 22f -11: c.j 28f -12: jal ra, 25f -13: jal t1, 21f -14: c.j 23f -15: jal s1, 8b -16: c.j 4b -17: jal a0, 26f -18: c.jal 14b -19: c.jal 18b -20: jal t1, 13b -21: jal ra, 9b -22: c.jal 11b -23: c.j 17b -24: jal a2, 6b -25: c.j 3b -26: c.jal 15b -27: c.j 1b -28: srli s10, t5, 3 - la a6, region_1+8955 #start riscv_load_store_rand_instr_stream_5 - lbu s11, -921(a6) - sw a4, -411(a6) - lbu t4, 338(a6) - sb s0, -120(a6) - mulh a2, tp, a4 - lh t0, 75(a6) - sb t6, -16(a6) - lbu zero, 418(a6) - remu t6, s7, t4 - sh t6, 13(a6) - csrrci s11, 0x340, 21 - sb a4, -540(a6) - lh s10, -755(a6) - lbu a0, -260(a6) - sb a4, 278(a6) - sw s8, -619(a6) - slt a2, t0, a6 - csrrsi a2, 0x340, 2 - lbu t0, -468(a6) - sb t2, -351(a6) - sltiu s10, t2, -652 - xor s3, a5, s2 - sb t3, 907(a6) - div a0, s11, a4 - sub a5, a5, s11 - lbu zero, 714(a6) - lbu s7, 186(a6) - or t6, s0, t0 - sb a0, 676(a6) - sb sp, -578(a6) - lbu ra, 39(a6) - lb t3, 578(a6) - lhu tp, 831(a6) - sb a3, -828(a6) - and s0, t0, sp - c.mv s3, t1 - lbu s1, 189(a6) - xori s10, s1, 252 - lbu t2, 522(a6) - sb s10, 1003(a6) #end riscv_load_store_rand_instr_stream_5 - addi a2, zero, -2 #init loop 0 counter - mulhu tp, a4, gp - addi zero, zero, 0 #init loop 0 limit -main_48_0_t: divu a1, s6, t3 - csrrc s2, 0x340, s8 - addi a2, a2, 2 #update loop 0 counter - slti gp, s1, 766 - c.bnez a2, main_48_0_t #branch for loop 0 - sltiu t5, s11, -99 - addi s1, zero, 4 #init loop 0 counter - c.add t5, s4 - or a6, a4, zero - sltiu t5, t6, -837 - or s11, tp, s4 - sll a2, a4, gp - csrrw t6, 0x340, s10 - div a1, s10, a2 - csrrc a3, 0x340, a6 - c.srli a1, 27 - addi s6, zero, 19 #init loop 0 limit - lui s4, 47346 -main_52_0_t: addi t6, s3, -912 - csrrc t3, 0x340, t4 - divu a0, s6, t2 - csrrwi t4, 0x340, 17 - addi s1, s1, 2 #update loop 0 counter - srai s10, s9, 2 - srai s10, ra, 26 - andi zero, ra, 580 - csrrw gp, 0x340, s3 - blt s1, s6, main_52_0_t #branch for loop 0 - c.add a3, a3 - la gp, region_3+189 #start load_store_instr_stream_1 - la s7, region_3+59 #start load_store_instr_stream_3 - la tp, region_3+224 #start load_store_instr_stream_2 - sh t3, -33(s7) - lbu s11, -51(gp) - lb s0, 86(gp) - lb t1, 43(s7) - lbu a7, -118(gp) - la s1, region_3+262 #start load_store_instr_stream_0 - lbu a0, 224(gp) - sb s1, -129(s1) - sb t3, -228(s1) - sh tp, -40(tp) - sb s6, -132(gp) - sb zero, 46(s7) - lb t2, 170(s1) - lb t5, 62(s7) - sb a3, -10(s7) - lh a2, -3(gp) - sh t6, -26(tp) - lbu t3, 200(gp) - lb s0, 25(tp) - sb s4, -225(s1) - lb a5, 59(tp) - sh a3, -45(s7) - sb gp, 58(s7) - sh s8, 54(tp) - sb t4, 48(s7) - sb s8, -36(s7) - lb a2, 320(gp) #end load_store_instr_stream_1 - sw a4, -3(s7) #end load_store_instr_stream_3 - lbu a5, -60(tp) #end load_store_instr_stream_2 - sb tp, -74(s1) #end load_store_instr_stream_0 -main_16: jal gp, 19f -0: jal tp, 1f -1: jal ra, 3f -2: c.jal 11f -3: jal a3, 14f -4: jal t1, 16f -5: c.jal 13f -6: jal a3, 4b -7: c.j 15f -8: c.j 21f -9: c.jal 10f -10: jal t2, 24f -11: c.jal 17f -12: c.j 7b -13: jal ra, 12b -14: jal ra, 2b -15: c.jal 8b -16: c.jal 0b -17: jal t1, 5b -18: jal ra, 23f -19: c.jal 20f -20: jal t1, 22f -21: jal t1, 18b -22: jal t1, 6b -23: c.j 9b -24: ori s4, s8, -101 - la t5, region_0+1619 #start riscv_load_store_rand_instr_stream_3 - slti s3, s1, 66 - ori t4, a0, 898 - lhu a5, 53(t5) - addi s10, a4, -775 - sb a5, -24(t5) - lbu a6, -60(t5) - lbu t3, 19(t5) - sb t3, 51(t5) - csrrsi s0, 0x340, 8 - sll a0, a6, zero - sb s6, 61(t5) - c.li s5, 18 - sb sp, -49(t5) - lbu s10, -14(t5) - lbu s11, -46(t5) - remu t4, sp, gp - sh sp, 31(t5) - lbu a6, -22(t5) - c.sub a2, a4 - sb ra, 8(t5) - lh s11, -43(t5) - lbu s6, -34(t5) - lui gp, 607932 - lbu s2, 45(t5) - mul t6, a3, a6 - rem t4, a4, s10 - lbu a0, 60(t5) - sb t1, 16(t5) - csrrsi t0, 0x340, 20 - rem s2, a6, t1 - lb a4, -52(t5) - csrrc s2, 0x340, a1 - lbu s7, 40(t5) - sh t0, -35(t5) - sh s11, -5(t5) - lbu gp, 32(t5) - csrrwi a3, 0x340, 9 - c.lui ra, 4 - sb s11, -34(t5) - mulh gp, t5, s3 - sra s1, t5, a3 - c.srai a3, 10 - csrrs s2, 0x340, s4 - sw s5, 49(t5) - andi t0, gp, 494 - lb s4, 4(t5) - lbu t0, 54(t5) - c.srai s1, 3 - lbu a7, 38(t5) - sra a1, sp, s8 - lbu s3, -11(t5) - lb a6, -35(t5) #end riscv_load_store_rand_instr_stream_3 - la s11, region_3+190 #start load_store_instr_stream_2 - la s2, region_4+1571 #start load_store_instr_stream_1 - la gp, region_0+3657 #start load_store_instr_stream_4 - sh a4, 62(s11) - lb ra, 6(s2) - la a4, region_1+8267 #start load_store_instr_stream_3 - la tp, region_2+2719 #start load_store_instr_stream_0 - sb s2, 245(gp) - lbu a0, 56(s11) - lb ra, 3(s2) - sb t5, 47(s11) - lw t0, 9(tp) - lb t3, -45(a4) - lhu a3, 7(s2) - lb ra, -63(s11) - lbu a3, -30(a4) - lbu s6, 238(gp) - lb s10, 6(s2) - lhu s0, 215(gp) - sb s2, 8(s2) - lbu s7, -51(gp) - sb t3, 6(tp) - lb s4, 4(s2) - lbu s10, -79(gp) - lb t6, -1(tp) - lb a0, -50(a4) - lbu a1, -3(s11) - lw a3, 6(s11) #end load_store_instr_stream_2 - sb gp, -38(a4) - lb s7, 5(tp) - lbu a3, -8(s2) - lh s5, 215(gp) #end load_store_instr_stream_4 - lbu s5, 26(a4) - lh s3, -1(s2) - lbu s5, 7(tp) - lbu a7, 16(s2) - lb a5, -22(a4) #end load_store_instr_stream_3 - lhu a6, -9(s2) #end load_store_instr_stream_1 - lbu a7, -16(tp) #end load_store_instr_stream_0 -main_20: jal gp, 9f -0: jal ra, 5f -1: jal tp, 0b -2: c.j 8f -3: c.jal 10f -4: c.jal 13f -5: c.j 4b -6: c.j 3b -7: c.j 12f -8: jal t1, 1b -9: c.jal 11f -10: c.j 7b -11: c.jal 6b -12: c.jal 2b -13: c.nop - la t1, region_3+392 #start load_store_instr_stream_4 - la a5, region_3+297 #start load_store_instr_stream_2 - sb s11, -2(a5) - lbu a0, 35(t1) - la s3, region_3+323 #start load_store_instr_stream_3 - la a2, region_3+311 #start load_store_instr_stream_0 - lbu a3, -64(t1) - lb t6, -160(s3) - lbu t4, 12(a5) - lb t4, -8(a5) - lb t2, -17(s3) - lbu t0, -59(t1) - la s4, region_3+164 #start load_store_instr_stream_1 - sh t3, -119(s3) - lbu a0, -14(a5) - lbu t6, -30(a2) - lb s11, -7(s4) - sb s10, 186(s3) - lbu s11, 43(t1) - lbu s11, 0(s4) - lb s11, -3(s4) - lb s6, 12(a5) - lb s11, -202(s3) - sh a2, -61(a2) - lb s2, 30(s3) - sb s1, 13(a5) - lb a0, 21(a2) - lh t2, 43(a2) - lh t3, 3(a5) - lbu a7, -64(s3) - sb t1, -1(s4) - lh zero, -8(s4) - lb s11, -225(s3) - lb t3, 0(a5) #end load_store_instr_stream_2 - lb a7, 126(s3) - lh a1, 22(t1) - lbu tp, -1(s4) #end load_store_instr_stream_1 - sb a6, -13(t1) - sb a2, -32(a2) - lbu s7, 30(t1) - lb t4, -90(s3) #end load_store_instr_stream_3 - lbu a3, 37(a2) - lb a1, 11(t1) #end load_store_instr_stream_4 - lbu s6, 26(a2) #end load_store_instr_stream_0 - la t0, region_3+81 #start riscv_load_store_rand_instr_stream_0 - div t2, s11, t0 - lhu s7, -27(t0) - c.nop - lh s11, -43(t0) - csrrwi s10, 0x340, 10 - csrrwi a7, 0x340, 24 - add a1, t0, a1 - csrrci t4, 0x340, 3 - slli s1, a0, 11 - addi s4, a3, -1 - sb sp, -29(t0) - xor s7, a5, a3 - sb sp, 78(t0) - lbu a1, 222(t0) - slt t1, s5, sp - csrrsi t4, 0x340, 8 - lb tp, 110(t0) - c.xor s0, a5 - c.andi a4, 26 - c.mv t2, a0 - c.srli s1, 24 - c.li s11, 20 - c.or s1, s0 - lbu a5, -46(t0) - nop - and t3, a3, s0 - lbu s1, 128(t0) - rem a6, t0, a5 - and s5, t2, t5 - c.ebreak;c.nop; - sb s5, 148(t0) - csrrwi s10, 0x340, 19 - c.slli s1, 2 - sb gp, 106(t0) #end riscv_load_store_rand_instr_stream_0 - la t5, region_0+2728 #start load_store_instr_stream_3 - la t2, region_2+4997 #start load_store_instr_stream_4 - la s10, region_4+1476 #start load_store_instr_stream_0 - sh a1, -6(t5) - lw s4, 844(s10) - la gp, region_3+192 #start load_store_instr_stream_1 - lb s7, 248(t2) - lb s11, 48(gp) - lb a2, 15(t5) - lbu a7, 23(gp) - lb s7, -2(t2) - la t6, region_1+7463 #start load_store_instr_stream_2 - lh s6, -14(t5) - lbu s6, 7(t5) - sb s10, 5(t5) - sh a3, -160(s10) - lbu s7, 4(t5) - lhu s0, 241(t2) - lh a1, 8(gp) - lhu s2, 16(t5) - sb t2, -49(s10) - lb s7, -18(t6) - lbu a2, -13(t5) - sw s8, 48(gp) - sb s11, 188(t2) - lbu t4, 3(t5) - lb a0, 87(t2) - lbu a3, 907(s10) - lbu a7, 216(t6) - sb t2, -17(gp) - sw s3, -47(t6) - sb a1, -1(t5) #end load_store_instr_stream_3 - lbu a0, -110(t2) - sh a1, 766(s10) - lbu tp, 232(t6) - lh a6, -54(gp) - lbu s11, 42(t2) - lbu a3, -172(t6) #end load_store_instr_stream_2 - sb s1, 59(gp) #end load_store_instr_stream_1 - lh t1, -27(t2) - lh s1, -107(t2) #end load_store_instr_stream_4 - sb a3, -845(s10) #end load_store_instr_stream_0 - add zero, s0, a4 - c.sub s1, s0 - csrrwi s6, 0x340, 25 - lui t1, 843362 - c.nop - csrrw a0, 0x340, s7 - c.slli a5, 10 -main_18: jal gp, 5f -0: c.jal 9f -1: jal ra, 10f -2: jal t0, 11f -3: c.jal 7f -4: jal t5, 0b -5: c.j 8f -6: c.j 4b -7: jal ra, 1b -8: jal s4, 3b -9: jal ra, 2b -10: c.j 6b -11: jal a4, 12f -12: c.ebreak;c.nop; - divu s6, a5, a7 - or a4, sp, sp - csrrci a3, 0x340, 31 - c.addi s3, -9 - and a5, s8, a4 - c.addi s6, 3 - xor s5, s11, a7 - c.ebreak;c.nop; - c.lui t2, 4 - bltu s3, t6, 35f - slt t4, a1, s6 - c.add a7, a0 - c.and a3, a0 - mulhu a3, a0, a4 - auipc s5, 332405 - csrrci s3, 0x340, 7 - c.bnez a2, 38f - .4byte 0x00100073 # ebreak - c.beqz a3, 37f - sra s2, gp, a4 - remu s6, s3, a7 - srl a5, s0, a0 - rem s1, a3, a4 - csrrc a1, 0x340, s6 - mulhu s6, tp, a6 - mulhu t6, s8, a1 - slt s3, t0, s4 - nop -35: csrrc t3, 0x340, s1 - srl a1, a4, sp -37: c.sub a3, s0 -38: add gp, ra, s9 - xor gp, sp, gp - auipc s4, 46061 - c.beqz s1, 56f - andi s5, t2, 738 - c.srai a3, 30 - beq s6, s5, 56f - xori s6, s4, -951 - blt a2, a1, 62f - c.andi a3, 5 - mul t6, s2, t2 - div s7, t2, ra - nop - c.slli s10, 30 - c.add ra, s3 - c.and a2, s0 - c.bnez a0, 73f - csrrw s3, 0x340, s11 -56: .4byte 0x00100073 # ebreak - c.add s4, s11 - csrrwi gp, 0x340, 19 - csrrw s3, 0x340, a0 - csrrw s10, 0x340, s2 - xori t2, s10, 1014 -62: bltu s2, t0, 63f -63: addi s2, sp, 845 - srai a3, a2, 17 - csrrsi s0, 0x340, 1 - c.slli a1, 7 - blt s1, gp, 82f - sltiu t3, sp, -273 - c.srai a5, 25 - sltu a0, a6, t0 - andi gp, t4, -277 - csrrwi t3, 0x340, 21 -73: auipc s7, 143689 - mul a7, a3, t1 - addi s6, t6, -397 - mulhsu a4, a6, a2 - auipc a0, 262041 - rem a0, s0, a4 - c.andi a1, -16 - csrrwi a4, 0x340, 12 - ori s7, t1, -805 -82: or a7, a6, s8 - c.nop - ori a5, t6, -841 - c.and s1, a5 - mul t4, a4, a3 - c.mv ra, a6 - c.and s1, a1 - c.bnez a3, 99f - xor s11, s1, s1 - c.slli ra, 15 - c.or a2, s0 - bge a6, s5, 112f - c.lui s10, 1 - csrrw t6, 0x340, t3 - blt zero, t2, 100f - c.and a1, s0 - div a7, s0, t2 -99: c.slli tp, 19 -100: sub s4, t0, a1 - bltu s8, t5, 114f - c.or a0, a2 - srai s10, zero, 23 - lui zero, 353254 - c.slli a6, 8 - c.and a0, a4 - c.mv ra, a5 - mulhu a0, s9, gp - remu s11, s0, s4 - c.add s6, s9 - nop -112: c.andi a2, -19 - divu s5, a1, t2 -114: c.sub a4, a1 - c.bnez a5, 120f - lui s0, 993948 - bgeu t3, a0, 127f - srli s10, t2, 21 - bge t4, a4, 139f -120: srl a0, t0, tp - blt t1, s5, 137f - slt t3, t6, t1 - c.bnez a4, 133f - sll s4, a2, a6 - csrrw t6, 0x340, a4 - csrrs a4, 0x340, t2 -127: csrrs s3, 0x340, t0 - div a5, a7, t0 - csrrwi s3, 0x340, 10 - slt a1, s1, a6 - bne t3, zero, 139f - sra t4, s8, s3 -133: srli a2, t0, 22 - c.srli s0, 28 - .4byte 0x00100073 # ebreak - andi s3, s1, -38 -137: c.xor a3, s0 - blt t6, t5, 156f -139: srli tp, s10, 7 - andi a5, s4, 517 - c.andi a5, -29 - mul tp, a0, tp - lui s2, 260708 - c.addi s10, 30 - sra a0, s2, t4 - srli gp, s7, 13 - c.bnez a5, 165f - mulh s5, s10, t6 - sltiu a0, s11, 887 - .4byte 0x00100073 # ebreak - c.bnez a2, 160f - c.srai a4, 31 - remu t1, a4, sp - rem t2, s4, a2 - xor t3, s3, tp -156: beq ra, s2, 168f - rem t3, ra, a6 - csrrci s6, 0x340, 18 - c.andi a3, 3 -160: .4byte 0x00100073 # ebreak - nop - csrrwi a4, 0x340, 15 - csrrc a7, 0x340, s9 - addi s2, sp, -594 -165: srai a3, gp, 29 - c.addi t4, 15 - bne ra, ra, 178f -168: c.or s1, a5 - csrrs t5, 0x340, t0 - c.or s1, a5 - and a7, s7, a4 - sltu t2, a5, a0 - csrrsi s7, 0x340, 17 - c.li t0, 23 - c.bnez a5, 183f - bge t3, t6, 189f - c.nop -178: xor a4, a0, t4 - c.xor a4, a2 - bne s10, s5, 189f - add a6, s11, t2 - sub ra, zero, a2 -183: sltu a1, sp, t3 - auipc s4, 852190 - auipc t4, 906415 - sub t3, a3, t5 - mulh a3, t1, s8 - lui a7, 91376 -189: addi zero, a0, 98 - c.beqz a0, 205f - slli a3, zero, 20 - xori s10, sp, 637 - add a0, tp, a5 - sll gp, a1, s11 - add s2, zero, a0 - bltu a7, s1, 199f - c.srai s0, 20 - bne t0, s3, 199f -199: csrrwi a1, 0x340, 29 - c.srai a3, 20 - c.add tp, s11 - add t2, t6, s10 - csrrwi s1, 0x340, 18 - srai t0, t2, 19 -205: csrrs a5, 0x340, s11 - rem a5, zero, s1 - bltu t2, s10, 215f - slt s3, a5, t4 - srli gp, s5, 7 - add gp, sp, tp - csrrsi s2, 0x340, 11 - bltu sp, a1, 228f - sub a1, s11, a5 - and a7, s3, a0 -215: c.srai a1, 27 - c.srli a2, 5 - srli a3, s5, 8 - div t1, t5, a0 - lui s6, 142569 - csrrsi s10, 0x340, 1 - srli t5, t2, 0 - csrrc s11, 0x340, s6 - la t2, region_2+4999 #start load_store_instr_stream_1 - la t5, region_2+3602 #start load_store_instr_stream_4 - la s0, region_2+5185 #start load_store_instr_stream_3 - sb s3, 46(t2) - la ra, region_2+2269 #start load_store_instr_stream_2 - lhu a6, 11(s0) - sb tp, 8(s0) - la a2, region_2+3772 #start load_store_instr_stream_0 - lbu s4, -58(ra) - sw a5, -203(t2) - lhu s10, 25(ra) - sb s9, -184(t2) - lbu a3, -60(ra) - sb a7, 252(t2) - sh s9, -15(s0) - sh s1, 36(t5) - lb s5, 80(t2) - lb t1, -12(s0) - lb s6, -7(ra) - sb a1, -14(ra) - lhu a7, 1(s0) - sb sp, -25(t5) - sh s1, -50(t5) - sb zero, -14(a2) - lb s5, 5(a2) - sb a4, 7(t5) - lbu t6, -6(ra) - lbu a5, -51(ra) - lbu s6, -15(a2) - lbu t4, -7(s0) - lh s1, -1(s0) - lb s6, 17(t5) - sb s4, 15(t5) - lb a0, 46(ra) - sb t5, 2(a2) - sh ra, -63(ra) - lb s4, 115(t2) - lbu t6, -10(s0) #end load_store_instr_stream_3 - lbu gp, 220(t2) - sb sp, 139(t2) - sb s8, -13(t5) #end load_store_instr_stream_4 - lb t3, -7(a2) - sb s3, -49(ra) #end load_store_instr_stream_2 - sw a7, 233(t2) #end load_store_instr_stream_1 - lb a7, 8(a2) #end load_store_instr_stream_0 - c.or a2, s0 - and t4, s5, a4 - c.or a2, s1 - nop - srai tp, a3, 14 -228: sltiu t0, a5, 131 - sra t5, a1, t6 - remu a7, s11, a3 - beq s2, a6, 243f - rem a6, a2, tp - xori t6, t6, -1014 - c.nop - sub t4, s1, a3 - c.bnez a4, 256f - beq t0, s5, 255f - c.nop - c.beqz s0, 254f - slti s11, a3, -493 - blt s0, t1, 250f - .4byte 0x00100073 # ebreak -243: csrrs s5, 0x340, t3 - mul s3, t3, t2 - sltiu s5, s1, -387 - nop - xor a2, s9, a6 - auipc t2, 262443 - remu s2, sp, s4 -250: csrrci t1, 0x340, 18 - bltu s6, t0, 252f -252: div a2, a5, s9 - blt a2, t1, 261f -254: c.lui t3, 11 -255: c.xor a1, s1 -256: mul a1, a5, s8 - csrrs s7, 0x340, a1 - nop - xori tp, s8, -377 - csrrsi t6, 0x340, 19 -261: auipc t1, 883809 - addi t4, t4, 10 - bge t6, s2, 276f - c.or a1, a1 - srai a2, a0, 25 - c.addi s4, 29 - mul t2, s8, s2 - c.mv gp, a2 - srli t4, s6, 18 - csrrci t1, 0x340, 1 - mulhu t5, ra, zero - xor t0, s9, s11 - c.nop - bge s1, a1, 293f - sll ra, tp, ra -276: bne s2, s0, 286f - c.add t0, s11 - nop - mulhsu s3, a5, t6 - csrrs a7, 0x340, t0 - c.andi s1, -15 - csrrsi a2, 0x340, 0 - csrrs t5, 0x340, t6 - csrrci t5, 0x340, 18 - c.xor s1, s0 -286: blt a4, s3, 295f - c.addi a5, -21 - ori tp, ra, -342 - or t4, a2, t0 - csrrwi s7, 0x340, 3 - xori a4, a5, 747 - .4byte 0x00100073 # ebreak -293: csrrsi t6, 0x340, 3 - srai gp, t1, 17 -295: sltu s11, tp, a7 - slt t1, s7, s8 - bgeu gp, a0, 307f - c.add a1, t4 - andi t5, t6, -32 - c.add a5, a0 - c.slli t4, 19 - divu t6, tp, t2 - mulhsu gp, a6, a4 - add s1, s0, a4 - add gp, s8, t2 - remu a7, a6, s5 -307: nop - mul t3, s8, a4 - c.lui s10, 15 - .4byte 0x00100073 # ebreak - rem s11, a4, a1 - c.andi a3, -29 - srli s1, s10, 8 - c.li a1, 7 - mulh t4, a5, s2 - beq a2, a7, 332f - and a3, a2, a3 - c.srai s1, 14 - c.mv a4, s7 - srl a2, t3, sp - xor tp, s3, t0 - csrrwi a4, 0x340, 3 - sll a2, s4, zero - c.ebreak;c.nop; - mulh t6, s1, zero - c.and a5, a2 - c.addi s4, 22 - andi a3, a3, -181 - andi t3, sp, 172 - mul s0, t5, t3 - c.sub a0, s0 -332: .4byte 0x00100073 # ebreak - sltu s4, s10, s10 - div s11, t1, a3 - csrrwi zero, 0x340, 23 - beq s10, t5, 347f - csrrci s1, 0x340, 10 - csrrs zero, 0x340, t5 - c.beqz a1, 349f - c.srli a2, 7 - c.li ra, -20 - csrrc t5, 0x340, t6 - sra a1, gp, t6 - c.bnez a4, 356f - sra s10, a0, s1 - sltu s2, a6, a1 -347: sltiu s4, sp, 51 - rem s3, s8, s7 -349: c.li s7, 4 - c.lui s7, 31 - bltu s5, t3, 366f - c.add a7, t3 - c.nop - csrrw s10, 0x340, s2 - c.li a6, 12 -356: beq t5, s4, 371f - slli s11, sp, 1 - c.slli ra, 16 - csrrwi a1, 0x340, 22 - srai a6, s2, 19 - slli zero, s0, 20 - lui a4, 138441 - blt a2, a6, 368f - c.addi a1, 21 - or t2, a1, s3 -366: c.bnez a4, 367f -367: c.beqz a4, 371f -368: mulhsu a7, sp, t4 - bge a3, t0, 372f - mulh a2, s2, s5 -371: sll t1, a3, s3 -372: xor zero, a0, s1 - remu a6, s7, t2 - csrrci s10, 0x340, 15 - bge a0, s3, 388f - c.addi s3, 31 - .4byte 0x00100073 # ebreak - c.add t5, a2 - .4byte 0x00100073 # ebreak - c.bnez s1, 395f - c.srli s0, 30 - mulhu a4, s2, s2 - rem s4, t3, t0 - c.srai a1, 22 - c.or a1, a4 - c.and s1, s0 - slt t6, s5, s1 -388: bgeu a4, a6, 407f - ori zero, t5, 203 - sltiu t0, a5, -891 - csrrc s7, 0x340, t3 - c.nop - rem t4, s5, s6 - addi a2, t1, 28 -395: slt a4, s7, s1 - bltu s11, s6, 414f - nop - addi t3, a0, 993 - sub a6, s3, a2 - c.srli a4, 24 - csrrs s11, 0x340, s11 - nop - sltiu t0, a2, -506 - xor t6, a1, s0 - ori s11, a5, -995 - mulhsu a6, a2, t5 -407: mulh t6, a5, a3 - sra gp, s3, tp - c.srli s1, 30 - csrrw s7, 0x340, s5 - remu ra, s6, s7 - srl a1, t4, a0 - xor t3, a7, a5 -414: auipc a1, 385598 - c.srai a5, 5 - or s11, a6, s8 - divu ra, s6, a4 - c.nop - mulhsu a7, s7, s9 - c.lui t6, 30 - .4byte 0x00100073 # ebreak - c.add a1, s6 - xori ra, s5, 331 - bge zero, sp, 436f - andi t5, ra, 593 - c.lui s7, 7 - csrrc s3, 0x340, s0 - c.mv a2, gp - or a2, ra, a1 - csrrwi t1, 0x340, 19 - bge s11, gp, 450f - slt a5, ra, s11 - div s4, a2, a4 - bge s9, a4, 449f - c.beqz s1, 444f -436: c.or s1, a1 - c.xor a0, a5 - sltu s3, t2, s0 - divu a4, t5, a0 - xor a1, tp, a4 - addi ra, t4, -152 - c.add s7, a6 - xori t5, gp, -239 -444: c.mv s4, sp - bgeu s7, a1, 450f - mulhsu t6, gp, ra - andi a4, a2, -995 - c.nop -449: add s2, s3, t0 -450: c.bnez a3, 454f - mulhu a0, s9, s1 - addi zero, t6, -880 - mulhsu t6, s11, s11 -454: nop - divu t0, sp, ra - c.lui t4, 16 - slli a6, a6, 0 - divu a0, s11, s1 - c.lui s3, 16 - csrrsi t5, 0x340, 13 - csrrc t2, 0x340, t0 - csrrs a6, 0x340, s6 - csrrci a2, 0x340, 25 - c.srli s1, 19 - ori a2, s1, 76 - xori s11, gp, 717 - srli a7, t2, 2 - slt s5, t3, t3 - xori s6, s4, -648 - c.and a1, a2 - or t3, s7, t5 - mulhsu s3, t3, zero - divu a6, a6, a2 - csrrc a0, 0x340, s7 - srli a0, a4, 2 - csrrwi zero, 0x340, 28 - csrrw ra, 0x340, a1 - sra a2, t4, a1 - mulh t5, s11, t6 - srai ra, t4, 30 - csrrc t2, 0x340, sp - sra a1, tp, zero - blt a0, t0, 496f - beq gp, s7, 494f - lui a5, 532072 - c.nop - bltu s3, t2, 496f - c.mv s10, t0 - srli t6, ra, 25 - blt t0, a3, 498f - c.xor a3, a3 - mulh t5, t0, s0 - c.sub s1, s0 -494: divu ra, s4, s9 - csrrwi t2, 0x340, 31 -496: div a2, ra, zero - slli a6, t3, 20 -498: beq tp, s1, 517f - rem a0, t2, t2 - srli s4, ra, 22 - c.bnez a1, 520f - c.li s6, -17 - ori s3, s11, 881 - mul s6, s5, ra - c.or a5, a0 - xor a5, t5, a2 - bltu a6, t6, 519f - mulh a3, tp, t1 - c.lui a3, 26 - srl t1, t3, a5 - slli s4, s5, 13 - slti t5, t0, 176 - csrrwi ra, 0x340, 5 - auipc t5, 678866 - bge t5, t1, 535f - c.lui s0, 25 -517: addi a0, sp, 774 - c.andi a0, -6 -519: c.addi t6, -5 -520: blt t0, a2, 521f -521: and ra, s8, t1 - mulh a5, a1, a4 - mul t6, a0, gp - c.beqz a3, 527f - sltiu a3, t5, 604 - c.lui tp, 14 -527: sra t0, gp, s10 - c.sub a0, a2 - c.beqz a5, 537f - c.add t6, t1 - c.beqz a5, 543f - c.or a3, s0 - bne gp, a0, 548f - slti s11, s1, -113 -535: bgeu s0, s8, 547f - blt s7, t6, 549f -537: csrrwi a5, 0x340, 26 - c.andi a0, -11 - sltiu a0, sp, -649 - sltu a4, sp, a1 - mul t0, s6, s1 - sll t0, sp, t4 -543: andi s2, a3, -561 - c.srli a0, 23 - csrrsi s4, 0x340, 19 - c.add a2, s8 -547: slt s2, a6, s8 -548: c.li s3, 21 -549: slli s10, a1, 6 - c.srli a2, 16 - or a3, a7, s11 - srli s6, a0, 20 - .4byte 0x00100073 # ebreak - mulh a6, t4, t1 - sub a1, s4, a2 - .4byte 0x00100073 # ebreak - slti s5, a7, -112 - mulhsu s3, t4, t2 - c.and s1, a2 - and a1, a5, zero - add gp, s7, s5 - remu s3, a3, a6 - c.lui s5, 28 - srli a2, a4, 15 - c.and s1, a2 - csrrs a3, 0x340, s0 - addi t1, a7, 708 - sub ra, sp, s9 - divu ra, a7, s9 - rem a2, a2, s7 - mulhu s0, ra, t4 - bgeu a7, tp, 590f - srli a2, s8, 21 - blt s8, s8, 585f - sra s6, t5, s9 - divu a6, s10, a6 - csrrci t6, 0x340, 18 - c.ebreak;c.nop; - addi s5, s0, 449 - c.xor a2, a3 - bgeu gp, gp, 591f - c.nop - c.srai a3, 7 - csrrci s11, 0x340, 9 -585: rem t2, t5, s10 - slt s4, s1, s9 - c.addi a7, -9 - add t4, a1, t1 - slt t2, t4, t4 -590: blt t4, s10, 609f -591: divu s6, a7, s2 - rem s2, s10, s2 - bge s7, a4, 608f - sll a3, sp, tp - c.srai a3, 19 - c.lui a3, 24 - sltiu t1, ra, -395 - c.li a1, 13 - c.lui s6, 10 - mulhu gp, s0, a1 - srai s10, t2, 22 - c.lui s2, 24 - csrrwi s10, 0x340, 5 - srai s6, a2, 17 - .4byte 0x00100073 # ebreak - srli zero, gp, 20 - sltiu t6, sp, 90 -608: slt s5, s7, gp -609: and t4, a1, a1 - csrrw a1, 0x340, t5 - c.slli a4, 25 - c.lui a3, 16 - mulhu ra, t5, a1 - slli a2, a3, 14 - csrrsi ra, 0x340, 5 - c.ebreak;c.nop; - or t5, s4, a0 - remu a5, ra, s0 - srli s7, a4, 29 - blt zero, s11, 635f - andi a1, s7, -290 - c.bnez a3, 640f - bgeu t2, zero, 633f - xori a3, sp, 224 - c.addi a0, -8 - bne s11, s5, 642f - bgeu s8, s2, 643f - srai s7, s3, 11 - mulhu t4, a6, s4 - rem gp, s8, s4 - mul gp, s6, s6 - beq ra, t5, 633f -633: bge s7, ra, 651f - c.or a1, s0 -635: c.srai a2, 17 - csrrw a0, 0x340, s10 - srl s10, t0, a0 - divu s1, t4, gp - srli a6, a5, 14 -640: srai s7, s7, 20 - c.addi t5, 11 -642: addi a4, a0, -172 -643: srli s7, s8, 31 - c.slli ra, 7 - bge s2, tp, 663f - c.srli a1, 12 - c.slli t6, 21 - or gp, s1, t1 - and gp, s6, t4 - mul s4, s5, s2 -651: xor t6, s11, a2 - srai t4, s11, 1 - mulhsu t1, a0, s4 - srl zero, ra, t6 - lui t0, 123367 - bne s2, s1, 666f - sub tp, t1, tp - and t4, t2, t5 - c.xor s0, s1 - c.srai a3, 26 - mul t2, a4, a4 - remu t2, zero, t1 -663: c.andi s1, -13 - csrrw t0, 0x340, s0 - divu a7, a3, a7 -666: sltu a1, s6, s2 - csrrs t2, 0x340, gp - xori a1, tp, -993 - xori t2, t6, 259 - c.and a3, a3 - csrrc zero, 0x340, sp - sub t6, s3, s6 - slli s5, s8, 25 - remu tp, a7, t4 - c.slli s0, 11 - slt gp, s0, tp - slt zero, t3, s8 - slti s11, gp, 292 - c.srai a2, 11 - c.and s1, s0 - csrrwi s5, 0x340, 26 - mulhsu a6, s3, a2 - ori ra, tp, -598 - srli a4, s3, 11 - c.nop - and s6, t6, s8 - sltiu s11, a0, 118 - addi s6, t5, 34 - c.add a6, t5 - c.lui a3, 1 - bne s10, s0, 706f - c.mv gp, s0 - auipc t4, 641196 - xori s3, t0, -1008 - srli s4, s7, 21 - blt s9, a4, 716f - bgeu a4, gp, 713f - mul tp, s4, s7 - sll ra, s3, s10 - blt s0, ra, 715f - blt a1, s5, 702f -702: mulhsu a4, ra, t6 - sra a2, s1, s9 - div a4, sp, s7 - srli t1, s0, 28 -706: c.and a5, a5 - slt s3, t5, t1 - mulhu gp, a1, t4 - andi a3, a5, -206 - c.beqz a3, 719f - sra a5, s11, s7 - or t6, s8, t0 -713: slt gp, s8, a7 - c.bnez a4, 719f -715: c.sub a0, s1 -716: srl a5, a3, a5 - c.beqz s1, 726f - c.bnez s0, 726f -719: xori s10, s8, 1018 - and t0, t5, t5 - sra t4, a5, t1 - addi a4, s5, 317 - c.beqz s1, 724f -724: c.or a3, a3 - c.li s2, -19 -726: beq ra, s7, 736f - csrrs s2, 0x340, s11 - slt s11, t6, a1 - sub tp, a5, t3 - csrrci s7, 0x340, 27 - mulhu tp, a0, t4 - blt s1, sp, 735f - sra s11, a4, s8 - or t0, t4, s7 -735: nop -736: c.and a3, s1 - auipc s11, 745905 - lui a6, 298635 - mulh s11, s10, t1 - remu t3, t2, sp - or gp, gp, s0 - beq a2, a3, 755f - rem s7, a5, s8 - sll t6, s2, gp - slli tp, a3, 28 - c.li t3, -29 - andi t3, s4, 645 - add t2, tp, a0 - bltu sp, s3, 757f - srai s1, t4, 9 - csrrsi t6, 0x340, 17 - csrrs s0, 0x340, sp - c.and s1, s1 - bne s7, gp, 766f -755: mulhsu t5, s2, t2 - remu t2, a5, t1 -757: c.ebreak;c.nop; - beq t1, t4, 777f - srl s5, s0, s0 - remu ra, ra, s11 - c.ebreak;c.nop; - bne a5, a7, 774f - mulh t4, a7, a5 - c.li t6, 29 - sll a5, a1, s11 -766: csrrw a4, 0x340, ra - rem a6, s10, a2 - slti t5, a6, 399 - c.ebreak;c.nop; - c.and a5, a0 - c.srli a5, 15 - slt a1, t6, zero - c.xor a3, a5 -774: c.li s3, -13 - xor s0, a1, s6 - mul a4, s5, t6 -777: auipc s4, 204943 - add ra, t0, a4 - beq tp, a7, 789f - srai s4, a1, 3 - srai t4, a4, 30 - .4byte 0x00100073 # ebreak - c.beqz a4, 799f - c.lui a1, 23 - slt s10, zero, a4 - csrrc t2, 0x340, a3 - or tp, ra, s5 - csrrwi zero, 0x340, 17 -789: c.mv s4, s10 - c.and a4, a1 - xor s1, tp, t6 - .4byte 0x00100073 # ebreak - slti a4, s4, 155 - c.xor a1, s1 - csrrc tp, 0x340, s2 - csrrci t2, 0x340, 7 - xori ra, zero, 552 - c.and s1, a3 -799: ori a6, s4, -735 - csrrw s10, 0x340, t5 - xori t5, zero, 769 - or a6, t2, a6 - c.andi s0, 14 - lui a7, 755028 - c.sub a2, s0 - c.mv s7, s10 - c.sub a5, a2 - rem s1, s3, s2 - auipc s5, 621671 - bne a4, t1, 829f - srai a5, t4, 26 - slt a3, t1, s11 - mul tp, sp, a3 - c.ebreak;c.nop; - sltiu t3, t5, 489 - bgeu s9, s2, 829f - xori t6, ra, 417 - sra t4, a3, a0 - c.or s0, a5 - c.mv s11, a2 - remu s5, a0, t2 - auipc t4, 761075 - remu t1, s4, t3 - sra t2, s9, s7 - csrrs s10, 0x340, s1 - c.srli a2, 14 - beq s5, t0, 838f - bltu s2, sp, 843f -829: c.li s1, 20 - c.nop - c.lui a6, 11 - c.srli a0, 21 - mulh s3, s5, zero - c.addi a0, 21 - c.nop - addi a4, t0, 126 - mulh a6, t0, s6 -838: nop - srli a4, s9, 1 - c.mv s5, t6 - and t2, gp, s11 - or s1, s11, a5 -843: c.li ra, 28 - c.ebreak;c.nop; - csrrci s3, 0x340, 13 - csrrsi a2, 0x340, 9 - csrrc s1, 0x340, s11 - beq s4, s1, 863f - c.lui s11, 30 - csrrw s11, 0x340, t0 - .4byte 0x00100073 # ebreak - nop - divu gp, s1, t0 - add a0, a0, t5 - slli t5, gp, 24 - lui t6, 591528 - and a1, s6, a5 - c.and a4, a4 - or s6, a7, s1 - or t5, t6, a4 - or t3, s11, t0 - c.andi s0, -14 -863: mulhu a5, t4, gp - c.sub a2, a5 - sub t3, a6, a4 - srl t3, s4, zero - sra s11, ra, s9 - beq s4, s11, 887f - srai s2, gp, 13 - c.and s1, s0 - div a7, t5, a6 - c.addi s1, -21 - beq a5, s7, 877f - slt s10, s9, s8 - sub s10, s7, a2 - xori a5, s3, 322 -877: csrrw s11, 0x340, t6 - c.srai s0, 13 - div a6, a1, gp - c.xor a1, a2 - c.nop - c.nop - csrrs t5, 0x340, s3 - and t4, s8, gp - c.lui s0, 10 - c.xor a2, a1 -main_13: jal gp, 8f -0: c.j 13f -1: c.jal 6f -2: c.j 17f -3: jal ra, 4f -4: jal t1, 15f -5: jal t1, 19f -6: c.jal 16f -7: c.j 14f -8: c.jal 2b -9: jal ra, 18f -10: jal gp, 1b -11: c.jal 0b -12: c.j 7b -13: jal ra, 3b -14: jal ra, 5b -15: c.j 12b -16: c.j 11b -17: c.jal 9b -18: jal ra, 10b -19: c.and a1, a3 -887: slt ra, s4, s5 - nop - c.andi a3, -24 - .4byte 0x00100073 # ebreak - ori a3, gp, 485 - lui a0, 214630 - xor a7, a2, s3 - mulhsu a1, s9, t0 - sltiu a4, t1, -653 - .4byte 0x00100073 # ebreak - c.lui a4, 24 - c.nop - ori ra, a4, -703 - slli a4, s3, 1 - beq s10, t3, 913f - sll a7, a0, s5 - xor a3, s8, s6 - c.bnez a0, 919f - bge ra, sp, 918f - div s1, a1, s5 - csrrs a6, 0x340, t5 - csrrs a6, 0x340, t0 - mulhsu a6, a5, t4 - rem a3, t4, a4 - c.lui tp, 28 - srl t2, t2, s4 -913: beq ra, s0, 918f - csrrs s11, 0x340, a0 - srli a3, s2, 24 - rem s1, s9, gp - c.add a5, s5 -918: slli zero, gp, 10 -919: beq sp, s1, 929f - bne s1, a0, 932f - auipc a5, 209844 - slli s2, s7, 24 - slli s5, s1, 8 - c.mv s10, s8 - or s7, s6, t5 - ori s11, s3, 970 - add s2, t3, a2 - csrrw t0, 0x340, sp -929: mulhu t0, s2, a1 - mul t0, t3, s10 - c.lui a1, 15 -932: or s0, a6, ra - mul a3, a0, s1 - div t0, s9, t4 - xori a6, s3, -341 - sra a6, s8, t0 - mulhsu s6, t5, t1 - slt s11, s10, ra - mul a2, a6, ra - csrrsi s5, 0x340, 13 - c.beqz a2, 954f - srai s11, s8, 4 - csrrw tp, 0x340, s4 - mulhu s3, s11, a3 - sll t3, s4, s2 - nop - bgeu s2, zero, 957f - csrrc ra, 0x340, ra - mulhsu a4, gp, t3 - csrrc a7, 0x340, a4 - remu t4, s11, t6 - xori tp, a3, -582 - auipc a2, 486275 -954: auipc a0, 568176 - sltiu s2, s9, 557 - sra t5, s2, t3 -957: slt s3, s5, zero - mulhu s10, t6, tp - slti s5, a3, 644 - srli t5, ra, 16 - sll s0, s6, t6 - c.or s1, a5 - mulhsu a3, s5, s2 - c.nop - c.add a5, tp - blt t5, s0, 984f - c.srai a4, 1 - c.or s1, a0 - lui s5, 731125 - csrrwi a7, 0x340, 2 - csrrc a3, 0x340, a5 - sub s10, a0, t0 - sub t2, s2, s1 - or ra, s0, s0 - divu s1, t3, zero - sltiu gp, s10, 335 - srli a4, t6, 31 - andi s0, a1, -87 - csrrs t2, 0x340, t0 - mulh a0, t2, a7 - ori s3, gp, -987 - divu t5, s6, a1 - sub t4, s2, t4 -984: csrrw s2, 0x340, zero - csrrw s1, 0x340, t6 - sltu a6, s9, s2 - nop - sub t0, s0, t1 - c.li a5, 30 - csrrc a3, 0x340, s5 - c.li s5, -4 - bne t2, t2, 1002f - c.and s0, a3 - auipc s0, 887655 - csrrs s4, 0x340, s1 - sltiu a0, t6, 780 - mulhsu t4, a2, t4 - c.mv s1, t0 - csrrs a2, 0x340, s7 - and a5, t3, tp - sra s10, zero, s4 -1002: c.sub a2, a3 - divu a0, t6, sp - c.mv a1, s0 - c.li a4, -3 - csrrsi t1, 0x340, 0 - remu t3, tp, a5 - ori a0, gp, 15 - divu t1, a4, s7 - slli a3, t0, 17 - csrrwi t6, 0x340, 4 - c.li a7, -5 - c.li a3, -9 - xor t0, s9, t3 - addi s3, s4, -734 - sub t3, t0, gp - ori s10, s3, -46 - or s5, t6, s4 - csrrci t0, 0x340, 1 - csrrwi tp, 0x340, 13 - bgeu t1, a4, 1029f - bne a0, s8, 1034f - sltiu a7, a7, 206 - bne t6, t0, 1028f - sll t2, s9, s7 - c.mv ra, a0 - c.xor a5, s0 -1028: c.add a3, s11 -1029: c.lui t4, 10 - c.andi a5, 3 - and ra, sp, t0 - andi t0, a5, 909 - csrrs t1, 0x340, a0 -1034: c.beqz a5, 1042f - csrrwi s2, 0x340, 20 - c.and s0, s0 - sltiu t4, s2, 446 - div s4, t4, t2 - rem t6, s1, gp - slti s0, sp, -652 - .4byte 0x00100073 # ebreak -1042: sub a7, a0, a5 - slt t1, tp, s9 - div a0, t0, t3 - csrrw a5, 0x340, a4 - xor tp, a2, gp - sub s3, a0, a1 - lui t3, 587122 - srai t5, s10, 23 - c.andi a5, -3 - beq t2, s1, 1067f - c.sub a3, a3 - c.xor s0, a1 - nop - c.addi s3, 23 - sll ra, a6, s2 - add t5, a7, sp - c.sub a4, a3 - bge s11, s1, 1070f - c.li t4, -4 - mul s7, a3, s1 - divu t5, sp, s0 - div s7, zero, t0 - c.mv s4, a0 - mulhu gp, a5, t0 - addi a5, s4, -976 -1067: mulh s11, gp, t3 - c.lui s5, 19 - sltiu gp, a3, 310 -1070: bne t0, a1, 1082f - sltiu s4, t0, 787 - c.addi t5, -14 - bltu tp, t6, 1092f - sll s4, s2, ra - c.li s10, 2 - rem tp, s6, a6 - srli s6, a6, 4 - lui s3, 68082 - blt sp, s7, 1080f -1080: csrrw s2, 0x340, s7 - c.andi a1, -28 -1082: srli s5, sp, 14 - .4byte 0x00100073 # ebreak - .4byte 0x00100073 # ebreak - andi tp, t1, -1001 - c.and s0, a5 - bne a7, sp, 1106f - c.or s1, s0 - slli t0, tp, 8 - auipc s4, 145290 - bge s6, a4, 1110f -1092: div s1, s2, s9 - srl s6, t2, s10 - ori tp, ra, -50 - remu t1, ra, s3 - slli a3, a3, 8 - mulh s11, t0, t6 - c.beqz a1, 1116f - addi ra, ra, 692 - ori tp, tp, -448 - mulhu s4, t4, t5 - csrrwi t6, 0x340, 27 - srli a2, s5, 22 - mulhsu a0, gp, s9 - auipc a7, 97985 -1106: c.lui a0, 2 - nop - andi s3, s3, 811 - mulhsu t3, s6, s1 -1110: blt s7, t1, 1130f - nop - c.xor a2, a0 - xori a3, tp, -149 - c.and s1, a0 - c.andi s1, 31 -1116: sra gp, s7, s1 - c.slli t4, 10 - and gp, s2, ra - divu s4, gp, a0 - c.and s0, a1 - c.ebreak;c.nop; - srli s4, s0, 27 - mulh zero, zero, s1 - divu a0, a3, gp - beq t3, a5, 1140f - rem a5, s5, t0 - mul s11, s2, a4 - c.srli a5, 28 - .4byte 0x00100073 # ebreak -1130: lui zero, 536705 - addi t4, tp, 77 - mulhsu a2, s11, s10 - la s3, sub_1 - csrrsi s10, 0x340, 18 - rem a3, s8, t4 - srl gp, a7, s6 - addi s3, s3, -897 - blt s9, a3, j__main_sub_1_1 #branch to jump instr - srl s10, s11, s7 -j__main_sub_1_1: jalr gp, s3, 897 - nop - c.bnez a0, 1147f - remu a6, a4, s7 - rem s4, s2, a6 - mulh a6, t5, t2 - mul zero, s1, t5 - srai t4, a6, 10 - sll t0, a2, a5 - divu s2, t3, a3 -1140: c.slli s7, 11 - auipc a2, 647299 - bgeu s0, a0, 1151f - divu s0, a0, a5 - c.srli s1, 3 - c.beqz a3, 1148f - csrrw tp, 0x340, t5 -1147: auipc s2, 1001058 -1148: nop - lui zero, 478904 - bge gp, s3, 1151f -1151: c.li t3, 14 - c.xor a3, a2 - sltiu s1, s0, 469 - c.srai a5, 27 - addi s5, s4, -611 - bltu t3, s6, 1165f - c.and s0, a1 - auipc a5, 379980 - sll a6, a1, t4 - c.sub s0, a0 - andi a5, t3, 355 - lui s4, 371847 - mulhsu ra, t6, a6 - bgeu tp, a1, 1180f -1165: csrrci a1, 0x340, 28 - lui gp, 974152 - srai a4, t3, 26 - c.li s10, -24 - c.mv t3, t5 - blt a2, gp, 1185f - csrrwi s10, 0x340, 9 - bge a5, t3, 1184f - c.nop - and s10, tp, t5 - sll s0, a1, s5 - c.or s1, a1 - c.ebreak;c.nop; - srli t0, a6, 25 - divu a1, s0, tp -1180: divu a0, a5, s4 - auipc t6, 204000 - c.lui a4, 2 - .4byte 0x00100073 # ebreak -1184: c.ebreak;c.nop; -1185: div tp, s6, a4 - blt zero, s1, 1195f - add ra, s6, s0 - srli a3, tp, 0 - auipc s11, 594068 - sll s0, t3, t4 - c.bnez a2, 1210f - and t4, t5, t0 - c.addi s7, 25 - ori t5, s2, 876 -1195: xori t0, s3, -918 - c.nop - sll t1, s8, s7 - add t6, t2, s1 - c.sub a0, a4 - slti ra, sp, 354 - srl t4, s0, zero - sra s2, s8, s11 - slt a7, a6, sp - bge t1, a3, 1213f - csrrs s6, 0x340, a7 - sub s6, s2, a7 - csrrw t5, 0x340, a5 - bgeu t0, s6, 1227f - srl ra, t2, zero -1210: csrrw t6, 0x340, s2 - beq t4, s7, 1227f - mulhu a4, t2, sp -1213: c.srai a4, 27 - xori t2, s11, -703 - srl s7, s6, s7 - or t6, tp, s6 - c.beqz s1, 1220f - c.add s2, ra - xori s10, t4, 145 -1220: slti a3, a2, -65 - or t6, a4, t4 - slt zero, a5, s11 - c.lui a6, 29 - c.sub s0, s1 - ori t6, s5, -454 - csrrwi t5, 0x340, 4 -1227: sll a4, t1, s3 - c.beqz a3, 1243f - csrrwi t2, 0x340, 0 - mul s4, t4, t0 - srai a5, t0, 12 - srli s10, zero, 9 - c.andi s1, 12 - csrrc a5, 0x340, s7 - addi s5, s11, -852 - add s7, a6, s10 - c.and a5, a5 - mulh s6, a3, t4 - nop - c.or s0, a1 - slli s7, s8, 12 - beq s11, zero, 1257f -1243: bltu a1, s11, 1253f - c.and a0, s0 - beq t5, t3, 1253f - and a7, s0, s7 - rem s1, s4, s3 - srai gp, a0, 14 - slt gp, gp, a6 - c.sub a1, a5 - add s3, s4, t5 - blt gp, a5, 1256f -1253: c.li a0, -4 - sub t0, s1, t1 - c.slli s6, 22 -1256: csrrc a3, 0x340, s11 -1257: slt s1, a1, s8 - slt s4, a1, ra - c.bnez a5, 1274f - mulhsu a6, s8, a6 - slli t2, t3, 1 - c.bnez a4, 1272f - andi s7, s4, -901 - c.xor a5, a4 - csrrsi t2, 0x340, 1 - mulh s10, t6, s1 - remu a3, t5, s4 - la t6, region_3+101 #start load_store_instr_stream_1 - la a1, region_1+11010 #start load_store_instr_stream_0 - sb a1, 235(t6) - sh s5, 143(t6) - sb t6, 261(t6) - sb s9, 3(a1) - lbu s0, 252(t6) - sb a7, 259(t6) - sb s8, -4(a1) - lb ra, 16(a1) - lh a7, 125(t6) - lb gp, 9(a1) - lb s5, 224(t6) - sb t6, 1(a1) - sb s9, 370(t6) #end load_store_instr_stream_1 - lbu t5, -5(a1) #end load_store_instr_stream_0 - csrrc a6, 0x340, a4 - bne s1, t6, 1270f -1270: c.li s1, -30 - c.beqz a4, 1279f -1272: c.beqz s0, 1283f - slli s10, a2, 2 -1274: bne s5, s9, 1292f - c.or s1, a1 - divu gp, a7, s2 - or t6, a6, s3 - csrrci s10, 0x340, 24 -1279: add s5, t0, a2 - .4byte 0x00100073 # ebreak - csrrc a0, 0x340, gp - divu t3, s11, a0 -1283: c.ebreak;c.nop; - nop - mulhu s4, s10, s8 - xor t6, ra, t4 - c.mv s10, a4 - rem t0, s7, s10 - c.li a0, -13 - srl s11, s1, t6 - bne s10, s2, 1292f -1292: c.ebreak;c.nop; - mulhu ra, s5, s11 - csrrc a3, 0x340, t6 - la t0, region_2+3045 #start riscv_load_store_rand_instr_stream_8 - csrrw t1, 0x340, a0 - sb s3, -48(t0) - sb s7, -11(t0) - c.and a1, a3 - c.sub a5, a3 - sb sp, -36(t0) - lb t4, 60(t0) - slti a0, t3, -511 - xori a6, s4, -22 - sltu zero, s0, s4 - sh a3, -57(t0) - c.slli tp, 25 - sh t4, -59(t0) - sb s8, -26(t0) - lbu t4, 19(t0) - sb s1, 4(t0) - lbu ra, -6(t0) - csrrci tp, 0x340, 1 - lbu a7, 32(t0) - lw a5, 47(t0) - sb a0, -40(t0) - csrrwi zero, 0x340, 25 - sub a3, t1, a1 - slti s10, s10, 301 - sb t3, 36(t0) - lbu a4, 12(t0) - lb s1, -17(t0) - ori s1, a2, -628 - divu zero, t5, s2 - mulh zero, t0, a7 - c.nop - lh a6, 25(t0) - lbu s6, -8(t0) - lb s7, 5(t0) - c.lui a0, 2 - c.li t1, 14 - lb t6, 46(t0) - lbu zero, 46(t0) - lbu t4, 42(t0) - lb a7, 32(t0) #end riscv_load_store_rand_instr_stream_8 - srli a6, s10, 4 - slti t2, s3, -74 - andi zero, t3, -830 - rem t2, t0, a3 - c.mv a0, s10 - c.beqz a3, 1313f - divu t0, a5, t5 - beq t1, s8, 1312f - slli s3, a0, 28 - c.xor a4, a4 - csrrs a1, 0x340, t5 - csrrsi s2, 0x340, 21 - c.slli s5, 25 - c.li tp, -3 - ori s2, s9, -497 - c.nop - mulh s5, a2, s7 -1312: c.srai a4, 30 -1313: c.slli tp, 18 - .4byte 0x00100073 # ebreak - srli t1, s1, 2 - c.or a4, a0 - csrrw a7, 0x340, t1 - beq a5, s6, 1330f - andi s7, s0, -982 - csrrc s11, 0x340, gp - mulhsu s10, a2, t6 - and s7, s4, gp - andi a7, zero, -418 - c.sub a1, a5 - c.slli t3, 9 - mul s0, a5, gp - c.lui tp, 9 - or a7, a2, ra - mulhsu a3, sp, a4 -1330: c.lui s6, 20 - remu a4, gp, t0 - c.addi a4, 21 - c.li s3, -6 - c.beqz a0, 1339f - bge s7, t5, 1347f - xori s7, t1, 475 - slli s1, a2, 18 - c.mv a1, t2 -1339: divu t6, s3, a0 - rem a1, t5, ra - addi t3, a2, -580 - slli s11, t2, 12 - c.srai a5, 31 - xori a0, tp, -633 - remu ra, zero, a3 - mulhsu s6, a7, t4 -1347: c.beqz a5, 1366f - auipc t1, 358321 - beq s4, t1, 1365f - csrrsi s7, 0x340, 14 - csrrc s10, 0x340, s8 - csrrs s11, 0x340, a5 - divu a0, a7, a6 - slti a0, s10, -817 - div t2, gp, s6 - c.addi a2, 9 - c.li tp, -6 - csrrs a1, 0x340, s9 - sub t3, s6, s10 - srli ra, s3, 1 - csrrci t6, 0x340, 24 - divu a3, s3, gp - c.slli s1, 20 - .4byte 0x00100073 # ebreak -1365: xor zero, s0, s0 -1366: slt t6, s7, a4 - c.li t4, 0 - csrrsi s10, 0x340, 22 - .4byte 0x00100073 # ebreak - mulhsu s6, s6, ra - bge a5, a2, 1389f - c.xor s1, s1 - sltiu t0, sp, 991 - bne s7, a6, 1394f - .4byte 0x00100073 # ebreak - c.xor a1, a3 - ori tp, a6, -957 - remu a5, a1, t0 - addi t0, a2, -529 - la t3, region_1+12649 #start riscv_hazard_instr_stream_0 - csrrs ra, 0x340, s3 - lh a2, -15(t3) - lb a2, 18(t3) - sh a0, -11(t3) - c.add ra, a0 - lb a1, 28(t3) - lb a2, -40(t3) - lw a2, -33(t3) - lh s3, 51(t3) - lb a0, -50(t3) - c.andi a1, -8 - lbu a1, -32(t3) - lh a1, 3(t3) - sb a2, 22(t3) - lb t6, -29(t3) - mulh t6, ra, s3 - lb a1, 36(t3) - csrrs a2, 0x340, t6 - sb s3, 46(t3) - sb a1, -2(t3) - c.and a1, a0 - sll a0, ra, a2 - mulh a2, s3, a0 - mul ra, a0, a0 - mulh t6, s3, s3 - lb a2, 44(t3) - sb ra, -16(t3) - sb a2, -26(t3) - lb s3, 43(t3) - mulh a2, ra, a2 - lbu a2, -53(t3) - sb a0, -14(t3) - lb a2, 50(t3) - lb a0, 38(t3) - lb t6, 59(t3) - sb t6, -46(t3) - lw s3, -5(t3) - lh s3, 31(t3) - sh a0, 27(t3) - sh ra, 19(t3) #end riscv_hazard_instr_stream_0 - c.mv ra, s7 - mulhsu s3, t1, gp - slti t3, s10, 883 - and a3, s6, s8 - bltu s2, s11, 1399f - xori gp, s11, 856 - c.srai a3, 25 - .4byte 0x00100073 # ebreak - blt a1, a3, 1401f -1389: rem a4, s2, s1 - addi s10, s0, -955 - auipc s5, 586661 - xori s3, s11, -634 - add a0, t2, gp -1394: bne s6, s5, 1410f - slli s10, s5, 12 - sra s7, t2, s10 - remu s6, t0, t4 - sltu a7, tp, t1 -1399: c.mv s5, a0 - c.sub a2, a1 -1401: csrrsi s7, 0x340, 16 - c.beqz s1, 1410f - c.addi a1, 30 - c.nop - csrrwi s10, 0x340, 0 - c.and a4, a3 - mul t0, a1, t6 - and zero, t3, s5 - rem tp, a0, a0 -1410: c.addi s0, 1 - sltiu s11, a5, 147 - c.srai s0, 31 - csrrwi t3, 0x340, 15 - .4byte 0x00100073 # ebreak - sltu zero, s10, s6 - c.bnez a1, 1426f - c.srli a0, 3 - remu s11, t4, ra - divu t3, s4, s0 - sub a6, t5, tp - slt s2, t2, s1 - sltu s0, t2, a1 - c.slli t1, 2 - auipc t0, 184604 - sltiu s5, s2, 271 -1426: andi t1, t5, -260 - c.bnez a0, 1447f - bgeu a5, a1, 1440f - sll a3, t4, a0 - remu t4, t0, a3 - csrrwi t3, 0x340, 27 - mul t0, t4, tp - c.and a1, s1 - sltiu t4, t3, -941 - c.slli t3, 9 - c.srli s0, 15 - csrrs a0, 0x340, t3 - mul s2, ra, s9 - c.beqz a2, 1449f -1440: c.lui t4, 27 - srai t1, s6, 9 - c.xor s0, a5 - sltu s7, t3, s7 - c.mv t2, s6 - andi s10, t4, 171 - c.beqz a0, 1458f -1447: div t0, t3, t6 - srai a4, s11, 26 -1449: c.mv a5, a1 - bge s3, s1, 1465f - beq t2, s10, 1463f - c.li tp, 17 - mul t3, gp, t0 - sltu t5, a2, a4 - c.bnez a2, 1470f - csrrci t0, 0x340, 2 - rem a4, a0, tp -1458: mulhsu gp, t0, t5 - lui s4, 547352 - slt s1, s9, t3 - slti s7, a5, -630 - xor a1, t5, a3 -1463: divu ra, a6, s4 - nop -1465: bge s7, tp, 1480f - lui s6, 704647 - slli s11, t2, 14 - .4byte 0x00100073 # ebreak - add a0, s0, s1 -1470: csrrwi t1, 0x340, 0 - .4byte 0x00100073 # ebreak - xor t4, s4, t1 - srl tp, s9, tp - divu s7, s10, a4 - nop - c.sub a5, a0 - rem s6, tp, a6 - nop - c.beqz a1, 1497f -1480: slti gp, s7, -717 - div t5, t1, a5 - csrrc t3, 0x340, t3 - sltiu a6, s10, -15 - and gp, t3, s5 - remu s4, t0, a1 - c.add s10, s5 - xori s7, t3, 73 - nop - c.xor a3, a2 - c.andi a5, -22 - and s4, s5, t2 - xor a5, t3, a3 - c.slli s0, 11 - or gp, s1, t5 - mulhu s10, a4, sp - remu a5, tp, tp -1497: and ra, t3, sp - bge s3, zero, 1514f - bne a0, a6, 1510f - mulhu a7, a1, gp - mul a1, ra, a2 - or t1, s9, zero - c.srli a4, 31 - srli s2, a5, 21 - addi t6, a1, 115 - xor s4, s0, zero - c.andi a0, 13 - csrrwi s6, 0x340, 5 - andi t2, t6, -674 -1510: c.beqz a5, 1519f - csrrw tp, 0x340, a6 - and a5, a5, s10 - c.beqz a4, 1526f -1514: mulhsu s5, t4, s0 - c.srli a4, 12 - c.xor a4, s1 - bge a4, a0, 1532f - slti s1, s2, -933 -1519: .4byte 0x00100073 # ebreak - sra t2, t4, a6 - srai t6, t4, 1 - c.add a5, s11 - c.nop - mulhsu s11, a4, a2 - c.sub a3, a5 -1526: csrrsi a4, 0x340, 10 - add gp, s7, t2 - c.slli s4, 7 - c.and a0, s0 - csrrsi s1, 0x340, 17 - csrrs tp, 0x340, s11 -1532: slli zero, a2, 22 - slli s1, t2, 18 - slli s1, a0, 3 - sltiu s4, s1, -673 - mulhsu a4, gp, t2 - bne s4, s10, 1538f -1538: c.and s0, a3 - csrrw a1, 0x340, t6 - remu s4, s11, a4 - div t6, t4, s6 - c.srai s0, 30 - xori s11, s0, -1003 - remu zero, s5, zero - slt t6, a3, t2 - c.andi a0, -18 - csrrs s2, 0x340, s5 - c.andi a5, -18 - sll t5, t2, a5 - xori s0, s9, 215 - csrrwi tp, 0x340, 17 - csrrc s5, 0x340, t5 - or zero, t3, s2 - csrrc tp, 0x340, t4 - csrrc s11, 0x340, s6 - blt ra, a4, 1566f - sra s1, t0, sp - divu t6, t5, s9 - c.bnez a5, 1578f - xori a5, s7, 253 - and s7, a2, s5 - mulh s0, s4, t5 - divu s7, s2, sp - sltu a1, s3, s11 - andi a6, a4, 612 -1566: xor a5, gp, a3 - remu t3, zero, s11 - srli t4, a3, 18 - slli a7, t0, 3 - remu s11, a1, a1 - csrrwi a7, 0x340, 25 - csrrc s2, 0x340, t4 - blt s4, s8, 1581f - c.nop - srli s5, s5, 9 - sltu t0, s8, zero - .4byte 0x00100073 # ebreak -1578: .4byte 0x00100073 # ebreak - sltu s3, t5, ra - csrrsi s11, 0x340, 12 -1581: csrrc a2, 0x340, s5 - divu s2, t5, s6 - c.bnez a3, 1602f - mulhu a5, sp, t3 - csrrsi s2, 0x340, 8 - mulhsu s1, s5, s2 - slli s7, s7, 15 - bltu a4, a3, 1592f - blt t0, t2, 1590f -1590: c.or a3, a3 - sra s3, a4, gp -1592: blt zero, t1, 1610f - csrrs a6, 0x340, a2 - sltiu t6, a1, -851 - bgeu t0, a7, 1600f - srl a0, sp, s3 - bge a4, sp, 1616f - div a6, zero, s0 - mulh a2, s6, s1 -1600: csrrc a5, 0x340, a4 - ori a2, a1, 408 -1602: xori s4, a0, 77 - srl t5, s2, t4 - slt t0, s4, gp - c.andi a4, 0 - c.slli gp, 31 - c.srli a3, 22 - srai t3, t3, 0 - sra t3, s0, t6 -1610: mulhsu s1, gp, t2 - csrrci zero, 0x340, 21 - csrrwi s3, 0x340, 0 - sltu s11, s0, a1 - andi tp, t1, 32 - sltu tp, s3, s5 -1616: csrrci ra, 0x340, 26 - divu s1, a0, a1 - sll s6, s10, sp - c.srai s0, 28 - c.ebreak;c.nop; - add s3, gp, a0 - addi a4, t0, -963 - rem s2, t2, t6 - mulh a6, a1, a3 - xor a4, sp, gp - nop - c.xor a1, a2 - ori s6, a3, 275 - divu s4, s2, t3 - srli a4, a1, 12 - auipc a5, 234635 - nop - c.mv s3, s9 - mulhu s4, t2, t6 - c.ebreak;c.nop; - c.add ra, ra - c.srli a5, 14 - sll s2, t0, t4 - slti a0, s0, -573 - sub t0, a5, s1 - c.andi s1, -12 - add tp, s10, s2 - srl t5, t2, s7 - c.nop - la a1, region_0+775 #start load_store_instr_stream_1 - la t3, region_0+943 #start load_store_instr_stream_2 - la a3, region_0+3180 #start load_store_instr_stream_0 - sb s0, -4(t3) - sb t3, 16(a1) - lb tp, 16(t3) - lh zero, -15(a1) - sh s4, 16(a3) - sh t1, -11(t3) - lh s3, 1(a1) - lh s4, -146(a3) - lb a2, -11(a1) - lbu s10, 11(t3) - sw zero, -200(a3) - sb a3, 15(a1) - lb s5, -22(a3) - lb t5, 79(a3) - lb s0, 13(t3) - sb sp, 103(a3) - lbu s4, 0(a1) #end load_store_instr_stream_1 - sb s7, -9(t3) #end load_store_instr_stream_2 - lbu tp, -163(a3) #end load_store_instr_stream_0 - c.lui s4, 22 - c.bnez a2, 1655f - c.and a2, a4 - ori s4, a5, -651 - c.ebreak;c.nop; - add t2, s3, a3 - divu gp, a7, gp - csrrw a2, 0x340, a5 - c.andi a5, -17 - c.srli a5, 31 -1655: or s4, s4, ra - c.lui a3, 18 - c.addi s4, -16 - bne a6, a2, 1661f - addi s11, s0, 274 - srli a0, t4, 16 -1661: xor s4, t0, tp - mul a3, a4, t1 - nop - or t2, s7, s4 - c.mv t6, t4 - addi a5, s1, 753 - c.slli a4, 6 - nop - csrrsi a0, 0x340, 11 - c.ebreak;c.nop; - c.xor a4, a5 - remu t1, t1, a4 - c.bnez a2, 1686f - csrrc s6, 0x340, t0 - mulh a2, t4, s1 - rem t1, t2, a3 - c.bnez s0, 1692f - c.or a1, s1 - c.beqz a0, 1689f - c.li a6, -11 - csrrsi t6, 0x340, 1 - xori t3, a4, -437 - c.srli a2, 4 - sltu t4, s3, t3 - ori t1, zero, -862 -1686: sll a5, a7, s0 - c.andi a4, 13 - remu t0, a3, s0 -1689: add a7, s1, s6 - bgeu s6, t4, 1699f - add ra, t6, s5 -1692: c.srai a0, 24 - blt t3, ra, 1712f - bne sp, s11, 1703f - mulh s10, a0, a7 - c.bnez a3, 1704f - ori t1, a6, -335 - bne ra, t0, 1710f -1699: c.srli a3, 29 - add a3, s4, a0 - and zero, s3, s2 - c.nop -1703: c.beqz s1, 1704f -1704: c.ebreak;c.nop; - bge s9, s5, 1708f - c.lui a2, 4 - c.xor a3, s1 -1708: beq s1, s5, 1724f - srai s10, s2, 24 -1710: slli s6, s6, 28 - c.or a5, a2 -1712: c.srai a3, 15 - remu a0, t0, t5 - div a7, s5, a6 - c.mv a7, sp - slli s0, a6, 20 - csrrs s1, 0x340, tp - c.ebreak;c.nop; - bne s11, tp, 1735f - slti tp, s11, 151 - csrrci t6, 0x340, 27 - or a6, s0, s9 - sll s4, a4, t0 -1724: c.srai a2, 17 - xori zero, t1, -26 - blt s9, s11, 1739f - srl t5, t3, a7 - c.and a3, a1 - bne a4, a1, 1740f - csrrs a6, 0x340, s4 - .4byte 0x00100073 # ebreak - c.ebreak;c.nop; - csrrwi s4, 0x340, 9 - andi s10, s2, -602 -1735: c.li t5, 20 - c.and a1, a3 - and s11, s5, t0 - c.andi a4, 2 -1739: sltiu a1, s5, -949 -1740: c.xor s0, a3 - srli a1, t6, 1 - beq a7, a0, 1755f - slt zero, s0, s6 - sltu ra, s4, t5 - divu t3, ra, s5 - c.add s3, t5 - bne t5, t0, 1759f - rem zero, a2, gp - c.addi s3, 17 - c.nop - sll s11, zero, t3 - c.li a1, -20 - c.li s1, -15 - c.mv t2, a6 -1755: ori s10, sp, 122 - xor a0, t6, a2 - mulhu s4, a0, t1 - csrrc s5, 0x340, a2 -1759: bltu zero, s2, 1774f - slli s0, t4, 23 - c.bnez a1, 1779f - c.srai a1, 7 - srai s4, a3, 26 - c.nop - xori t2, a3, -785 - c.beqz s1, 1778f - slt s7, s0, t5 - div t0, s4, t2 - rem a2, ra, a1 - c.xor s1, a4 - sra s11, t1, s1 - slli tp, s3, 13 - mulhu s4, t0, a0 -1774: beq s8, s6, 1775f -1775: sll s1, t1, t1 - slli s7, gp, 16 - c.li a1, -28 -1778: c.add s10, tp -1779: c.srai a0, 15 - c.mv s7, t0 - andi a5, a4, 261 - div s6, ra, ra - c.addi t4, -1 - mulhu gp, a0, s2 - add a7, a0, s6 - c.ebreak;c.nop; - bltu a0, a7, 1806f - csrrwi a2, 0x340, 2 - xori a1, s0, 41 - c.xor s0, a4 - c.srli a0, 29 - sltu t3, t1, t3 - c.xor a2, a1 - xori zero, s0, -604 - c.lui s11, 16 - beq s4, a7, 1811f - c.slli s10, 21 - xor s0, s5, s9 - bge a1, a1, 1818f - bge s10, s10, 1820f - csrrs tp, 0x340, t4 - xori t4, t5, 282 - c.ebreak;c.nop; - nop - c.sub a2, s1 -1806: csrrsi ra, 0x340, 16 - csrrwi s5, 0x340, 23 - andi s4, t4, 513 - mul tp, s11, s6 - srai s4, t2, 5 -1811: srl t5, s5, sp - c.or a4, a2 - c.addi gp, 24 - divu t3, zero, a0 - auipc a3, 311590 - c.li a4, 20 - c.mv a4, t2 -1818: bltu t5, zero, 1833f - c.sub a3, s1 -1820: sub s4, a0, zero - xor s10, tp, s0 - bgeu t5, s3, 1826f - srl s4, a4, t1 - mulhsu a0, a6, t3 - csrrci a0, 0x340, 11 -1826: remu tp, a4, s2 - sub a7, s7, s2 - add t5, a4, s5 - xori gp, s10, 944 - sll zero, s0, a3 - c.sub s0, s0 - addi gp, tp, 60 -1833: xori a3, t3, -774 - c.add s10, s0 - xor s6, s6, t6 - bgeu s11, a1, 1846f - sltiu a7, t4, 761 - beq s11, s5, 1856f - csrrc s2, 0x340, s1 - c.li a6, -13 - c.sub a4, s0 - addi a6, s6, -548 - bltu tp, s2, 1853f - ori s3, s9, 54 - c.and s0, a2 -1846: ori t4, zero, -337 - andi s10, a6, 287 - add a1, s2, s2 - c.and s0, a2 - c.sub a2, s0 - csrrc s3, 0x340, t2 - c.and s1, a1 -1853: sltu t5, t5, s7 - srli a7, s0, 26 - sltu zero, s3, s11 -1856: bgeu t1, s5, 1864f - c.xor a5, s0 - bne t3, s8, 1863f - c.beqz s1, 1871f - c.mv a2, a0 - auipc s4, 344639 - srai s2, a6, 8 - and s4, t3, tp - sub t3, t0, tp - srli a0, tp, 19 - la s2, sub_2 - c.andi s0, -6 - addi s2, s2, -983 - sltu t1, t1, a5 - add a0, a6, s3 -j__main_sub_2_2: jalr gp, s2, 983 - addi a0, zero, 5 #init loop 0 counter - slli s11, a3, 25 - srl a6, a5, s4 - rem s3, a5, s2 - addi tp, zero, -9 #init loop 0 limit - rem a1, a0, sp -main_51_0_t: srl gp, s5, t4 - csrrsi a7, 0x340, 6 - xor s0, t5, a4 - srl a7, t6, t3 - mulhsu a7, gp, s0 - andi t3, a2, -487 - srli a6, t3, 26 - srai a5, s11, 9 - srai s7, tp, 27 - add a4, s10, s1 - addi a0, a0, -10 #update loop 0 counter - c.slli a5, 8 - add a1, s4, a1 - srl a4, t6, zero - addi s2, s0, -984 - bge a0, tp, main_51_0_t #branch for loop 0 - mulh s0, t2, gp -1863: c.srai a1, 24 -1864: c.andi a5, -11 - nop - and gp, a5, s11 - csrrs a4, 0x340, s2 - add s1, s4, s1 - sltu t2, t6, s11 - c.add a4, s2 -1871: slti ra, s6, 893 - xor s10, s10, t1 - csrrci t0, 0x340, 29 - div t2, a0, s11 - rem s11, a6, s3 - mulhsu ra, t5, a6 - rem t5, t5, a2 - srai t1, t4, 23 - div t1, t5, a6 - sll tp, tp, t0 - sltiu a4, a3, -930 - lui t5, 696739 - .4byte 0x00100073 # ebreak - c.andi a4, 18 - remu s4, s5, s0 - rem gp, t4, s1 - mulh s0, t3, s1 - csrrc s2, 0x340, t1 - mulhsu a2, tp, s7 - .4byte 0x00100073 # ebreak - sra s5, t2, s5 - csrrsi a3, 0x340, 6 - rem a3, a7, s6 - nop - divu s7, t0, s5 - xor t5, s6, t1 - remu t3, t4, a2 - xor s1, a2, a7 - blt s4, s1, 1912f - c.lui s5, 14 - sub a4, s0, s7 - c.add s4, gp - auipc s6, 370524 - addi t3, a5, -544 - xor a6, s11, t6 - csrrwi s4, 0x340, 6 - add a0, gp, a2 - c.srai a0, 28 - slti s7, s4, 285 - c.srli a4, 21 - c.or a2, a4 -1912: c.andi a2, 2 - c.beqz s0, 1925f - add tp, a6, a6 - c.add a1, t6 - c.lui s1, 17 - xor t0, s8, t2 - sll a0, t1, s7 - mulh a0, sp, zero - lui s5, 139954 - ori zero, s8, -325 - srl s3, s5, t0 - csrrwi t1, 0x340, 23 - nop -1925: blt s5, s11, 1935f - bge a3, t3, 1935f - c.srli s1, 19 - auipc s3, 553367 - slli a1, a3, 5 - csrrc a3, 0x340, s9 - c.srai a2, 10 - c.srai a5, 26 - c.sub a4, s0 - andi a6, t4, -101 -1935: xor s7, s11, a1 - beq t4, a2, 1945f - add s4, t5, a2 - sltu t3, s10, s7 - divu t6, sp, a7 - mulhu s0, a7, a4 - srl s4, s0, s11 - remu s11, a6, s8 - bltu s11, a1, 1962f - sltu s1, s11, a1 -1945: c.bnez a1, 1957f - sltiu t3, t1, -341 - srai a7, a3, 2 - mulhu s4, s0, ra - slti t3, a0, 824 - remu a3, zero, s4 - bltu t1, s8, 1954f - csrrw a4, 0x340, tp - rem gp, s1, t5 -1954: c.srli a3, 13 - sub t4, a6, a7 - sub gp, s7, s9 -1957: andi a7, s9, -720 - c.lui s11, 19 - c.nop - c.srli a1, 6 - lui s7, 292213 -1962: csrrwi s4, 0x340, 3 - mulhsu t3, s6, s3 - nop - slt gp, a1, a1 - or s10, s2, a4 - divu a7, s11, a6 - addi a2, t6, -605 - slli gp, t6, 4 - c.lui t4, 3 - xor a6, gp, s0 - or tp, s11, s5 - ori a2, t2, -418 - or s1, a1, a0 - c.nop - add t4, s3, sp - mulh a6, t1, s6 - c.and a0, a4 - bge a0, a5, 1997f - csrrw s0, 0x340, zero - c.srai s1, 13 - mul s0, a2, a0 - c.and s1, a2 - c.li t4, 24 - blt s8, t1, 1998f - beq s3, a1, 1996f - csrrwi t1, 0x340, 22 - c.slli s3, 19 - mulhsu a2, a3, t6 - sra tp, ra, s4 - csrrci zero, 0x340, 13 - andi s7, t2, 910 - bge s9, s11, 2008f - c.beqz a3, 2013f - c.sub a4, a1 -1996: remu s2, s7, s10 -1997: add t4, a3, t5 -1998: sra s7, s6, sp - sll s11, s1, s10 - c.beqz s1, 2001f -2001: sltu a1, s0, tp - sltu a4, s1, s2 - c.beqz a2, 2007f - srli t3, t2, 14 - c.beqz a1, 2016f - csrrsi t0, 0x340, 12 -2007: divu s11, s6, t6 -2008: c.xor a0, a1 - mulh a2, s10, a0 - bltu a4, a3, 2025f - xor s10, s3, s6 - mulhsu t1, s5, s1 -2013: csrrw gp, 0x340, a4 - bgeu ra, t0, 2033f - blt s6, sp, 2023f -2016: c.ebreak;c.nop; - csrrwi a0, 0x340, 0 - csrrsi a3, 0x340, 2 - mul a6, t1, a2 - c.mv tp, t5 - bgeu a6, zero, 2031f - mulhsu t2, zero, a1 -2023: csrrs a1, 0x340, sp - csrrc zero, 0x340, ra -2025: auipc s0, 914806 - blt a2, a0, 2031f - c.add s5, s5 - mulhsu s4, a6, s7 - c.and s0, a1 - c.nop -2031: div s11, a3, sp - sltiu a6, s9, -804 -2033: c.add a2, sp - remu s0, a3, a5 - xor t6, sp, t3 - slti gp, s9, -65 - mulh a0, s0, s8 - bne s1, s7, 2054f - addi gp, s5, -428 - c.mv s5, sp - c.lui a5, 31 - nop - c.sub a1, a0 - c.and a2, a1 - mulhu s5, a3, gp - c.bnez a1, 2066f - c.srai a4, 25 - c.beqz a5, 2056f - nop - c.bnez s1, 2066f - c.or a5, a4 - rem s11, t0, t6 - blt s9, t6, 2054f -2054: xor s2, t6, sp - divu t6, s4, a2 -2056: c.addi s0, 4 - and a7, s10, t4 - srl t0, t3, t4 - srli a5, s8, 7 - slti a4, s1, -645 - mulhsu s3, a1, t4 - andi a5, t4, 58 - rem s5, a6, tp - mulh gp, a1, t0 - csrrs s7, 0x340, t2 -2066: c.srli a3, 8 - ori a5, s5, -611 - .4byte 0x00100073 # ebreak - sll s6, a0, s4 - c.slli s6, 4 - csrrwi t1, 0x340, 14 - slli a5, gp, 0 - c.srai a5, 11 - sltu t0, t6, a2 - csrrwi gp, 0x340, 20 - srli a4, s6, 11 - nop - bgeu a1, s2, 2093f - bge s11, a7, 2094f - srli ra, zero, 29 - ori gp, a1, 361 - sll s7, t1, a7 - bge tp, zero, 2101f - bltu a4, s9, 2103f - csrrw s7, 0x340, s6 - bge s7, a4, 2096f - mulhu s3, t4, s11 - bne t3, t4, 2096f - sltiu a2, t5, -623 - c.and a5, a5 - c.li s5, -9 - c.mv a1, a3 -2093: c.mv t4, t4 -2094: slt s4, s8, s8 - csrrwi t3, 0x340, 21 -2096: xor t4, s9, a0 - csrrci t3, 0x340, 26 - mulh s2, t6, s6 - c.slli a2, 23 - remu s1, t3, s1 -2101: lui t2, 247790 - c.nop -2103: mulhu s2, a4, s9 - csrrci s5, 0x340, 13 - xor a1, t3, s8 - mulh s0, s9, s0 - c.add a0, t0 - and s2, t5, s8 - addi tp, a1, 959 - c.addi t3, -30 - srli s7, a2, 15 - xor gp, s2, a0 - beq t4, zero, 2132f - c.li t0, 15 - c.mv a7, s7 - bne s5, s7, 2120f - divu s11, sp, t5 - remu s10, a6, a4 - c.mv ra, a4 -2120: rem s7, t6, s3 - csrrsi s3, 0x340, 28 - c.add t3, t1 - c.sub s1, a5 - rem t0, s10, s6 - xori t0, s5, 40 - bgeu s11, a6, 2138f - c.and a3, a0 - rem zero, ra, a1 - csrrci s7, 0x340, 15 - add t0, t6, sp - c.or s0, a2 -2132: c.and a1, s1 - c.addi a7, -16 - blt s4, s5, 2150f - c.sub s1, a2 - c.add s5, s10 - beq t6, t3, 2140f -2138: rem ra, t2, a6 - c.addi a7, -1 -2140: xori t2, t6, 487 - srli s10, a7, 17 - c.ebreak;c.nop; - xori s0, a6, 601 - c.srai a3, 14 - bge s9, tp, 2158f - c.li t5, -24 - bgeu s1, s5, 2148f -2148: ori zero, a5, 427 - sltiu a6, t4, -476 -2150: c.slli a4, 14 - rem t5, gp, a6 - csrrsi s7, 0x340, 16 - rem s11, sp, s2 - c.bnez a1, 2159f - c.srai a4, 9 - c.add s10, a2 - mulhu s11, a2, s11 -2158: xori a0, a3, -1003 -2159: c.li s7, -31 - add s1, a6, s8 - csrrw s4, 0x340, a4 - csrrw s7, 0x340, ra - auipc s0, 953710 - mulhu s3, t1, a4 - bge s2, a7, 2174f - c.li s3, -3 - c.andi a4, 13 - bge t6, s9, 2177f - c.andi a2, 6 - bltu t6, s3, 2189f - bne s3, tp, 2186f - c.add t1, a3 - c.srli a0, 28 -2174: bne s0, a5, 2192f - ori tp, s10, -537 - addi s11, ra, -801 -2177: or tp, s4, t6 - slli a0, tp, 31 - slti zero, a5, -128 - c.nop - add s10, a0, t3 - mulhsu gp, s1, zero - div t1, s1, tp - addi t1, a5, 980 - sltu t0, a2, s6 -2186: c.beqz a2, 2199f - bne s5, a6, 2205f - nop -2189: sltu a1, t6, ra - c.mv s3, a3 - bgeu s8, s10, 2206f -2192: c.mv t6, tp - mulhsu t0, a1, zero - csrrw a2, 0x340, s7 - andi zero, a5, 330 - csrrw a0, 0x340, t5 - bne s5, sp, 2217f - mul s4, a4, t2 -2199: csrrci t4, 0x340, 6 - c.sub s0, s1 - c.andi a3, -12 - blt ra, s5, 2213f - sub zero, a3, s2 - sltu a2, t5, a3 -2205: blt s3, s11, 2220f -2206: add s0, t4, a1 - srl t6, s2, s8 - and a5, s0, s3 - bgeu a2, s6, 2217f - slti t6, s11, 247 - c.ebreak;c.nop; - mulh t2, t2, s8 -2213: c.beqz a4, 2223f - beq t1, ra, 2226f - c.and a2, a1 - c.li s7, 26 -2217: srl s11, sp, gp - div t5, t1, a0 - mulhsu s0, t3, s4 -2220: c.or a3, a5 - mul s11, s4, a6 - addi a5, t0, 511 -2223: csrrsi s2, 0x340, 25 - csrrwi a2, 0x340, 2 - mulhu t6, s1, s4 -2226: add t2, s5, sp - c.sub a0, a3 - lui a0, 774936 - bgeu s3, a7, 2241f - beq t6, s8, 2246f - c.xor a1, s0 - bgeu tp, s11, 2247f - rem t4, t3, s2 - blt s0, a1, 2244f - csrrc s2, 0x340, s0 - slli t6, s0, 17 - c.bnez a0, 2238f -2238: ori a0, a4, 135 - slt t5, s4, t6 - c.bnez a0, 2244f -2241: xor t2, t6, zero - c.slli s5, 24 - c.srai a4, 3 -2244: add s7, s10, s8 - slt s3, a7, a1 -2246: andi a4, a0, 44 -2247: c.srai a1, 7 - sltu t3, s10, gp - c.lui a4, 11 - la s7, region_1+10627 #start riscv_load_store_rand_instr_stream_2 - srli t6, a3, 3 - lui t0, 703817 - lw s0, -59(s7) - slli t5, a2, 16 - lbu s6, 12(s7) - lb s11, 26(s7) - div a4, a5, zero - lbu gp, -22(s7) - addi t4, t1, 732 - lb tp, 36(s7) - srai a1, a6, 19 - c.ebreak;c.nop; - lb t3, 64(s7) - lb ra, 14(s7) - sltiu s2, s5, -828 - slt gp, t5, a0 - srl t2, s1, s10 - lhu t0, 21(s7) - c.lui t0, 30 - addi a2, a4, 1019 - sb s6, -56(s7) - lh s5, -55(s7) - lbu t5, 11(s7) - sub a7, s0, t3 - sb t5, 4(s7) #end riscv_load_store_rand_instr_stream_2 - sltiu t2, a4, -460 - csrrsi s0, 0x340, 19 - sltiu t0, a7, 734 - c.or a5, a0 - c.and a2, a0 - div ra, s11, s2 - slli s4, t4, 15 - mulhsu t2, s8, t3 - c.lui s2, 9 - c.and a0, a5 - auipc s3, 126626 - c.add a1, s11 - or t1, sp, s0 - xori gp, s7, 806 - remu s7, a1, t1 - nop - bne s7, s6, 2281f - csrrs t1, 0x340, s11 - bge a6, s7, 2280f - auipc a3, 182823 - xor s1, ra, s1 - csrrsi a5, 0x340, 4 - c.slli ra, 4 - c.bnez s0, 2278f - csrrwi s5, 0x340, 12 - beq s3, a1, 2276f -2276: divu s6, s9, a7 - blt s4, a4, 2286f -2278: divu s11, sp, s4 - srl a5, s8, gp -2280: sltu a0, a6, s4 -2281: slli gp, t3, 4 - slti a0, zero, 974 - c.addi gp, -20 - c.add gp, s5 - srl a5, t3, s5 -2286: bgeu zero, a3, 2296f - c.srli a3, 20 - srl a5, a4, s3 - sra t1, t5, a0 - csrrw ra, 0x340, a7 - mulhsu a1, s3, t1 - c.ebreak;c.nop; - mul a2, a0, tp - c.beqz a4, 2302f - c.add s5, t4 -2296: slt s2, s11, a3 - c.srai a1, 2 - c.add s3, a6 - srai s7, a1, 13 - sra t1, s6, sp - bgeu t0, a2, 2317f -2302: sra t4, s8, a3 - auipc s10, 329382 - beq s2, sp, 2312f - srli s10, tp, 20 - srai t5, a0, 7 - c.beqz a1, 2317f - add a3, t0, s3 - and t5, a1, s3 - sltu s0, s10, t4 - c.andi a3, 5 -2312: or a6, a3, t3 - c.beqz a4, 2314f -2314: divu s2, t4, a0 - c.nop - bgeu t5, a4, 2327f -2317: c.ebreak;c.nop; - mul gp, a1, t4 - c.srai a5, 12 - srai t2, s11, 11 - sra t0, a3, s4 - addi s7, a0, 544 - srli s7, a1, 15 - andi t5, s7, 554 - sll a2, s1, t3 - bltu a0, t3, 2345f -2327: auipc t2, 119739 - remu s11, s10, a1 - mulhu t4, tp, a7 - csrrsi a6, 0x340, 30 - c.beqz a0, 2350f - csrrs s7, 0x340, s4 - div t3, a7, s10 - c.mv s6, a6 - beq t3, t3, 2350f - andi gp, a5, 7 - divu a6, s4, ra - xori s7, a3, -924 - remu s5, t3, a7 - csrrwi s1, 0x340, 23 - div s1, tp, a0 - c.xor a4, a3 - xori s11, a3, 492 - mul s5, s6, t1 -2345: srai t2, s5, 23 - csrrci a6, 0x340, 30 - c.sub a5, a5 - mul t1, s4, s11 - bgeu s2, s2, 2369f -2350: bgeu s6, a5, 2365f - or gp, s5, a0 - lui a4, 964947 - slli a7, t0, 15 - c.add ra, s9 - sub t6, t6, s2 - c.srli s1, 18 - c.bnez s1, 2370f - c.lui s11, 4 - mulhsu s4, a1, a1 - c.slli s4, 6 - c.bnez a5, 2373f - c.beqz a4, 2380f - sltiu a3, s7, 277 - mulhu s4, t0, a1 -2365: csrrw s10, 0x340, t3 - beq s0, s3, 2381f - c.srli a2, 28 - c.slli s6, 13 -2369: beq a2, tp, 2378f -2370: andi tp, s3, 601 - c.nop - ori a0, t1, 669 -2373: divu t1, zero, s6 - lui s11, 321541 - c.sub s0, a3 - slti a4, a5, -384 - rem s3, a4, gp -2378: c.nop - beq s8, s11, 2395f -2380: csrrsi s5, 0x340, 30 -2381: c.slli t5, 19 - c.beqz a2, 2395f - slt a4, a1, t6 - c.li t6, 24 - csrrc s1, 0x340, sp - srli a2, s7, 20 - xori a1, s10, 221 - srli tp, a0, 21 - nop - rem a5, a6, t4 - csrrs a0, 0x340, t3 - slt gp, a2, t0 - rem s6, s0, a3 - c.nop -2395: sltu s1, t2, a0 - sltu s10, t2, gp - xori a6, s6, -397 - sra a4, s1, t6 - c.srai s1, 21 - auipc s7, 738538 - sub s0, a3, s4 - mulhsu t5, a0, a3 - slt s10, a7, s3 - mulhsu tp, a5, s9 - and a7, s2, a3 - sltiu s5, tp, -702 - sltu t5, tp, s8 - xor t0, a5, a0 - beq a5, tp, 2419f - sra s1, t1, sp - sra s2, s8, t0 - beq t6, a1, 2424f - csrrw s1, 0x340, a0 - or t4, ra, t6 - blt a6, sp, 2418f - slli a6, s7, 11 - srl t4, a6, gp -2418: rem a5, a1, s8 -2419: c.li s5, 14 - mul s3, s0, t2 - csrrw a7, 0x340, s1 - csrrc s0, 0x340, s8 - div a5, a1, tp -2424: add s5, a3, a6 - xor t0, tp, s4 - c.srli a0, 31 - csrrc a2, 0x340, s6 - ori s1, a5, -823 - blt a5, a7, 2447f - sll s7, s3, s3 - sltiu t3, s0, -336 - beq a7, t5, 2451f - c.andi a3, -29 - c.ebreak;c.nop; - ori t5, t6, -348 - mulh s2, s8, a4 - c.andi a3, -13 - remu t4, sp, s10 - c.srli a4, 29 - c.or a2, a3 - divu s0, s3, a5 - rem t1, a2, sp - auipc ra, 246854 - add ra, t6, t5 - or gp, a5, s11 - sltiu a5, a1, -768 -2447: srli t4, t0, 6 - xor s0, s7, s2 - sltu s4, t2, s4 - bne gp, a0, 2461f -2451: sll gp, a7, sp - xor ra, a6, t1 - mulh s7, a1, s4 - c.andi s1, 3 - c.srli a3, 3 - c.lui a7, 6 - addi s7, sp, 688 - c.beqz a0, 2470f - c.bnez a5, 2475f - nop -2461: csrrc a3, 0x340, t1 - mulh s4, s0, s0 - c.sub a1, a0 - c.and a4, a0 - bne a3, ra, 2484f - xor t3, t4, sp - c.and a5, a1 - lui t0, 480417 - c.addi a4, 28 -2470: div a5, s3, a0 - add s4, t6, a1 - c.nop - ori a2, gp, 268 - mulh t5, t2, t6 -2475: csrrc a7, 0x340, s0 - rem a6, sp, a1 - c.and a0, a3 - or t0, a1, tp - csrrc t2, 0x340, s1 - srai s0, s5, 22 - sra a7, t3, a7 - .4byte 0x00100073 # ebreak - slli a3, ra, 13 -2484: rem a0, s1, t2 - slli s2, tp, 22 - c.mv s7, tp - csrrs t2, 0x340, t4 - mulhsu s2, a1, s11 - lui a2, 828503 - c.bnez a1, 2491f -2491: csrrci a7, 0x340, 15 - sltiu s10, sp, 297 - and s4, a6, a1 - csrrci s2, 0x340, 1 - mulhu a3, s11, s5 - and tp, t2, s7 - mulh a4, a6, a3 - sll s3, ra, t1 - csrrw a5, 0x340, t1 - c.addi s6, 29 - c.srai s1, 5 - sltiu gp, s9, 935 - sra a7, s11, a1 - div s1, s2, t0 - div t3, t4, t6 - bltu zero, gp, 2516f - c.add ra, a3 - bltu tp, a1, 2520f - remu t2, s9, a0 - xori tp, s7, 776 - slli a5, s1, 21 - csrrci a7, 0x340, 11 - andi a3, s2, 370 - c.ebreak;c.nop; - auipc s0, 83481 -2516: c.lui s1, 16 - c.li t0, -32 - xori a4, s2, -706 - sll t4, s7, t6 -2520: bgeu s10, tp, 2538f - slt a4, t3, s4 - and t0, gp, s0 - csrrc t0, 0x340, tp - c.beqz s0, 2536f - sltiu a1, t2, -103 - lui t1, 628051 - xor s10, s9, a3 - bne a4, s1, 2543f - xor t0, s2, ra - c.srai a4, 10 - c.bnez a5, 2539f - c.mv s5, a3 - sub s10, t0, a2 - c.beqz a0, 2553f - bne s10, a2, 2548f -2536: c.xor a1, s1 - bltu a7, t5, 2546f -2538: div s3, a0, s6 -2539: remu a3, t2, s11 - c.ebreak;c.nop; - nop - sub t4, a3, t5 -2543: divu s3, a1, s2 - remu ra, a7, t2 - c.ebreak;c.nop; -2546: srl t3, s11, s1 - auipc s4, 81914 -2548: bne a2, a1, 2563f - srai a2, ra, 2 - c.ebreak;c.nop; - la ra, region_2+6957 #start load_store_instr_stream_2 - la s2, region_2+4943 #start load_store_instr_stream_1 - sw t1, 9(s2) - la t0, region_2+384 #start load_store_instr_stream_0 - lb t5, -33(t0) - la gp, region_2+1135 #start load_store_instr_stream_3 - lhu s7, 117(ra) - lb s5, -11(s2) - sh s0, 183(gp) - sb s4, -14(s2) - lbu s7, 10(t0) - sw t5, 85(gp) - sb a3, -202(ra) - sw s8, -81(ra) - sh a3, -30(t0) - lbu a4, -5(s2) - sh t4, -9(s2) - sb a0, -26(t0) - lh a6, -11(s2) - lh a5, 44(t0) - lh s5, -35(ra) - sb t1, 12(s2) - lbu a3, -35(t0) - lw a4, 175(ra) - sb s1, 80(gp) - lbu s7, 23(t0) - lbu a3, -132(ra) - lbu s11, 5(s2) #end load_store_instr_stream_1 - sb s5, -178(ra) - lbu t4, 7(gp) - sb s3, -62(ra) #end load_store_instr_stream_2 - sh s4, -35(gp) #end load_store_instr_stream_3 - sb s5, -24(t0) #end load_store_instr_stream_0 - auipc t6, 24453 - c.add s7, t6 -2553: csrrwi t6, 0x340, 28 - and s6, t4, s2 - lui a3, 632370 - c.xor s1, s0 - c.bnez a1, 2572f - divu s1, s4, t4 - c.and s0, a1 - srai s1, s3, 1 - auipc ra, 60263 - sub t5, s8, s9 -2563: mulhsu a1, s5, zero - slli t5, t3, 30 - csrrwi t4, 0x340, 2 - .4byte 0x00100073 # ebreak - c.xor a4, a2 - div s5, t6, t1 - sll t1, t5, a7 - sub s7, a4, s2 - and t5, s3, s11 -2572: slt t2, s3, t3 - lui s1, 648230 - lui a4, 193664 - c.sub a1, a2 - c.xor a1, s0 - addi tp, s7, 437 - srai t5, sp, 7 - mulh gp, s8, s3 - and ra, a4, a6 - slli t2, zero, 21 - c.andi a2, 24 - bge a4, sp, 2588f - andi a5, a3, 364 - c.mv s5, tp - div s3, s2, a2 - sub zero, a7, s5 -2588: mul s1, t2, gp - c.addi s5, 30 - ori s7, a6, -517 - mul a6, s9, s11 - c.li s6, 7 - div a3, t5, s6 - bne a7, t1, 2604f - sra s10, s8, s0 - slti a7, sp, 617 - csrrwi t2, 0x340, 6 - srai a6, t0, 16 - bgeu t4, gp, 2600f -2600: sltiu a5, s2, -752 - sltiu t3, s7, -227 - csrrsi a5, 0x340, 21 - .4byte 0x00100073 # ebreak -2604: ori s5, t6, 113 - sub s4, a4, a4 - c.andi a3, 5 - c.mv t5, sp - c.lui t5, 3 - slli t4, s2, 21 - c.srai a1, 30 - mul a3, s10, s1 - c.add gp, t3 - lui s3, 641496 - .4byte 0x00100073 # ebreak - bltu s1, t0, 2618f - c.lui s0, 17 - c.lui s4, 30 -2618: xor a0, t5, a2 - divu t0, s8, a2 - sub a5, a5, sp - sub s7, a5, s0 - divu t2, a5, t3 - andi s1, t6, 779 - nop - remu a0, t0, sp - bgeu t6, a5, 2644f - c.and a3, a2 - c.slli a1, 17 - blt a4, a0, 2648f - c.andi a2, -14 - csrrc a4, 0x340, a2 - c.srli a4, 21 - csrrw a0, 0x340, s7 - mul s10, t6, t5 - c.mv s4, s8 - c.xor a1, a5 - addi t2, t4, -285 - and a0, a3, a4 - csrrw s1, 0x340, t4 - sra t5, t3, s2 - xori s5, s11, 883 - la s3, region_2+3509 #start load_store_instr_stream_3 - la a2, region_1+284 #start load_store_instr_stream_2 - la ra, region_4+1462 #start load_store_instr_stream_1 - sb a3, -630(s3) - la a3, region_0+603 #start load_store_instr_stream_0 - sb a4, 132(a3) - sb t6, -6(ra) - lh gp, -253(a3) - lbu s10, 13(ra) - sb a1, 359(s3) - lb t5, 1(a2) - lb t0, -195(a3) - sh sp, 75(s3) - lw s1, -12(a2) - sb s4, 159(a3) - sh ra, -61(a3) - lb s1, -38(s3) - sw t4, 10(ra) - lb t6, -204(a3) - lb s5, 14(ra) - lhu a0, 221(s3) - sb ra, 140(a3) - sb s9, 12(a2) - lbu gp, 3(a2) - lbu a1, -718(s3) - lb a1, -15(ra) - lbu t0, -3(a2) - sb s1, -5(a3) - lb a5, -2(ra) #end load_store_instr_stream_1 - sb s7, -158(s3) - lb s4, -14(a2) - sh s1, -93(a3) - lhu s5, 137(s3) - sh t6, -2(a2) - sb s7, 1015(s3) #end load_store_instr_stream_3 - lh t1, -4(a2) #end load_store_instr_stream_2 - lbu tp, 81(a3) #end load_store_instr_stream_0 - bltu a3, s3, 2652f - c.srai a4, 13 -2644: csrrwi s7, 0x340, 2 - addi s1, a2, 601 - srai s6, a4, 1 - slt t4, s10, s8 -2648: mulhu t6, gp, a1 - mulhsu s0, a0, s7 - c.and s0, s1 - mulhsu s0, a5, ra -2652: c.xor a1, a2 - c.ebreak;c.nop; - c.ebreak;c.nop; - c.lui s0, 2 - remu s11, t2, a5 - c.srli a2, 17 - csrrsi tp, 0x340, 29 - csrrs ra, 0x340, a6 - bgeu a5, t4, 2664f - c.nop - srl zero, a6, s1 - c.bnez a3, 2676f -2664: c.bnez s1, 2672f - c.xor a5, a3 - nop - sub a5, s2, ra - or a2, s6, t2 - remu s10, sp, t2 - c.xor a1, a4 - srl s10, a1, s8 -2672: srai s5, s11, 8 - bgeu s11, t6, 2688f - c.srli s1, 27 - bltu zero, s2, 2691f -2676: c.srli a2, 24 - c.xor a1, a2 - csrrci t4, 0x340, 28 - mul t0, gp, s4 - bgeu gp, s0, 2689f - sub t4, tp, t0 - c.lui s11, 25 - c.slli t2, 1 - c.srli a4, 8 - c.srai a1, 3 - c.addi s2, -22 - srai s6, sp, 20 -2688: c.or a0, a4 -2689: bltu a1, s1, 2709f - c.mv s1, s6 -2691: nop - andi s6, a2, -906 - sltiu s10, a5, 743 - csrrci a5, 0x340, 29 - csrrci s5, 0x340, 1 - and a7, t6, s8 - .4byte 0x00100073 # ebreak - c.beqz s0, 2714f - sra t5, s1, gp - c.andi a5, -24 - c.andi s0, -12 - c.sub a2, a5 - c.and a1, a0 - beq t0, tp, 2712f - c.and a0, a0 - csrrw s6, 0x340, t1 - mulh t0, s4, s0 - bge tp, t2, 2727f -2709: c.ebreak;c.nop; - mulhsu a1, t6, s10 - mulhu a0, s6, s5 -2712: csrrwi s1, 0x340, 19 - c.lui a4, 28 -2714: c.or a5, a3 - srai tp, s11, 3 - c.slli s11, 5 - c.addi a2, 5 - xor a0, s9, a3 - c.srli s0, 20 - csrrs a5, 0x340, s5 - c.mv s11, t3 - csrrsi s4, 0x340, 21 - c.sub s0, a5 - mulh t0, a4, t0 - andi t3, s7, -476 - bgeu tp, zero, 2746f -2727: andi a1, t5, 217 - srl s6, a5, s1 - xori s3, zero, 702 - mulhsu s2, s3, s11 - bgeu a5, s7, 2742f - addi t3, s10, -468 - c.slli a7, 2 - bgeu a2, s6, 2746f - c.sub a1, a4 - bgeu s5, zero, 2744f - and t3, zero, a6 - slti s3, s1, 676 - srl t5, a3, gp - c.bnez a0, 2759f - sub s6, ra, t1 -2742: c.srai a2, 31 - srli t1, sp, 25 -2744: c.add a6, a2 - bgeu a4, s4, 2746f -2746: add s2, s11, s2 - sltu a3, t5, s4 - srl zero, t3, s5 - srai a4, s7, 23 - andi s10, s4, -909 - beq a0, s0, 2756f - slt t5, zero, gp - xori s11, t2, -644 - sltu t4, t6, s0 - andi t3, s4, -70 -2756: lui a2, 742720 - c.addi s0, -26 - c.ebreak;c.nop; -2759: c.addi t5, 3 - bltu s8, a3, 2772f - srai s4, s2, 10 - sltu s1, a5, gp - c.or a3, s1 - beq a1, t2, 2768f - div t3, a0, t0 - sltiu ra, s10, -648 - and a7, t1, tp -2768: mulhu t3, s9, s1 - srli s2, a4, 29 - xor t5, s0, a5 - or s11, s4, t6 -2772: sll a4, a7, a4 - remu s5, gp, a6 - bne s0, s1, 2787f - and t2, a1, t6 - csrrc tp, 0x340, gp - lui t4, 848977 - c.lui s7, 11 - bge s6, s6, 2780f -2780: add a7, s10, a0 - csrrsi t0, 0x340, 21 - c.beqz a4, 2792f - bne s4, a7, 2792f - c.bnez a2, 2797f - bltu gp, t0, 2794f - sltiu s7, t2, 554 -2787: c.addi s0, 5 - xor t2, t5, s11 - slli a2, a2, 2 - sub a4, s7, t1 - mulhu a0, s10, s9 -2792: mul s10, s2, a7 - slli t0, a6, 4 -2794: nop - c.andi a4, -25 - c.and a5, s1 -2797: c.srai a5, 12 - sub s3, s3, s10 - sra t2, s0, t1 - c.addi gp, 2 - mulh a3, s10, t1 - csrrs a2, 0x340, s11 - andi ra, a5, 259 - ori a5, a7, 442 - add t5, gp, t2 - c.srai a3, 26 - blt sp, t2, 2822f - or a2, s11, t4 - addi a5, t0, 710 - mulh t4, a7, s11 - csrrci s4, 0x340, 24 - csrrwi a0, 0x340, 27 - c.slli a3, 21 - andi a5, sp, 906 - srl s7, s10, s10 - c.srai s1, 15 - mulhu a5, a0, s9 - add t2, tp, sp - ori t1, t5, -178 - c.and a2, a1 - c.bnez a2, 2831f -2822: mulhsu s6, a2, s7 - div s11, s11, s10 - csrrci zero, 0x340, 2 - sltu t4, sp, a0 - auipc a5, 636559 - sltiu s10, s5, -258 - sll a0, s1, tp - c.andi a1, 3 - nop -2831: srli t4, s11, 1 - lui a6, 687826 - ori gp, s2, -918 - c.beqz s1, 2850f - csrrs t2, 0x340, a7 - csrrsi s6, 0x340, 1 - slt zero, t3, a1 - add a7, s10, s5 - c.sub a3, s1 - c.srli s1, 5 - srl s2, s5, s3 - beq s11, s3, 2857f - c.or a0, s1 - c.or a3, s0 - c.bnez a2, 2855f - bge a3, a4, 2864f - c.sub a3, a3 - csrrsi a4, 0x340, 12 - c.slli s1, 31 -2850: c.srai a5, 17 - xori s7, ra, -146 - add s10, a2, gp - div s0, zero, t2 - sll s0, zero, s8 -2855: c.ebreak;c.nop; - andi s10, a6, -919 -2857: sltu tp, a7, tp - bgeu a7, tp, 2870f - lui t3, 438906 - srl a0, gp, s3 - srli tp, t2, 28 - c.and a1, a5 - sltiu a6, zero, 982 -2864: andi t2, a1, -635 - csrrc t3, 0x340, sp - xori a2, t3, 388 - csrrci s3, 0x340, 1 - mulh t5, sp, a2 - c.sub s0, a5 -2870: slli t1, t4, 19 - remu t3, sp, a5 - mulh t6, s3, t4 - c.and a5, a3 - ori s2, s5, -622 - slt t0, ra, t1 - la t4, region_3+141 #start riscv_load_store_rand_instr_stream_6 - sb a6, -28(t4) - lbu s6, 212(t4) - or zero, a4, s6 - sb a6, -38(t4) - c.lui s10, 27 - lhu s6, 135(t4) - slt s6, s5, t5 - lbu tp, 6(t4) - csrrc zero, 0x340, a3 - ori a7, s3, 479 - sb a2, 101(t4) - divu s11, sp, s5 - sb t3, -10(t4) - srl t0, gp, s1 - lb s6, -36(t4) - lbu t2, -6(t4) - lb s10, 133(t4) - lbu s1, -115(t4) - c.srli a2, 29 - lbu a6, 22(t4) - csrrwi s11, 0x340, 24 - nop - andi a7, t1, 288 - lbu s7, 19(t4) - c.mv tp, s2 - c.srai s0, 1 - csrrc s3, 0x340, s10 - lhu a1, 91(t4) - mulhsu s0, t5, t6 - sb a7, 252(t4) - lb s1, 26(t4) - andi ra, a0, -605 - c.ebreak;c.nop; - lbu s6, -77(t4) - c.nop - lbu a6, -38(t4) - lw s4, 183(t4) - lbu a0, 180(t4) - c.li s10, 21 - lh s11, -119(t4) - div s3, a6, a6 - c.nop - xori a0, s0, -158 - sh s0, 31(t4) - c.xor a2, a4 - lbu s6, -98(t4) - csrrci s5, 0x340, 18 - ori s3, tp, 882 - lb s6, 174(t4) - ori s0, s3, 1006 - sb s8, 235(t4) - sh a2, -55(t4) - sub s4, t2, t0 - lbu a7, 160(t4) - lui t0, 200020 - lbu a5, 185(t4) - slli gp, s2, 6 - sb t1, 101(t4) #end riscv_load_store_rand_instr_stream_6 - andi t2, s10, 63 - sll a0, a3, s1 - c.and a0, a3 - sltiu s6, a3, 752 - xor t1, a7, s11 - csrrw t0, 0x340, s11 - bltu t6, a4, 2885f - csrrsi a7, 0x340, 3 - c.beqz a4, 2899f -2885: ori tp, a3, -435 - c.xor a5, a1 - c.add a6, s3 - divu s2, s10, s7 - remu t5, ra, sp - csrrsi ra, 0x340, 25 - c.andi a5, 13 - c.nop - slli a2, s8, 29 - c.add a1, s3 - csrrsi ra, 0x340, 22 - c.li a2, 23 - xori t6, t2, -733 - mulhsu a6, gp, s9 -2899: .4byte 0x00100073 # ebreak - c.li s5, -21 - srai a0, s8, 30 - sra a3, s2, t5 - csrrsi gp, 0x340, 7 - sub t1, t1, sp - c.andi a5, -32 - csrrci t0, 0x340, 18 - srli s3, ra, 4 - csrrw t5, 0x340, a3 - sub a1, a5, a3 - beq t4, zero, 2925f - slt t6, s7, t5 - auipc t4, 116265 - mulhu ra, s4, tp - slli t6, s0, 3 - beq a3, s0, 2934f - csrrc a2, 0x340, t2 - beq a4, a0, 2935f - xor t6, a6, a5 - ori s2, t6, 276 - andi a3, a3, 23 - remu t6, s6, s3 - blt a7, a1, 2940f - c.srli s0, 17 - or a0, a4, a5 -2925: mulhsu a3, s3, t0 - srli a4, s5, 12 - slti s7, ra, -534 - c.lui gp, 29 - c.ebreak;c.nop; - auipc s7, 403676 - c.or a1, s0 - beq ra, s5, 2940f - slti s4, a7, 759 -2934: srl t6, a2, zero -2935: sltu t5, s11, t2 - slt gp, s4, s8 - xori s3, gp, -554 - c.beqz a0, 2951f - csrrci zero, 0x340, 6 -2940: csrrwi s5, 0x340, 7 - c.srai a5, 13 - csrrwi t6, 0x340, 13 - c.add t0, s5 - sltu a0, a5, t6 - srl s5, t4, s10 - srli t5, ra, 3 - slti s7, s4, 668 - c.srai s0, 30 - c.andi a5, -23 - bgeu zero, s9, 2954f -2951: c.mv s1, s11 - auipc t4, 653251 - c.xor s1, s0 -2954: and tp, s0, s1 - div t4, s3, s3 - div ra, a1, zero - srl tp, t1, s10 - mulhu t3, s10, a1 - c.add a0, s5 - c.nop - srl a7, a0, a7 - rem s10, a3, s1 - xor zero, s11, a2 - c.addi s1, 27 - slli a7, tp, 8 - c.beqz a1, 2981f - bge a1, a1, 2977f - srai s11, s1, 9 - c.srai s0, 31 - c.bnez s1, 2980f - mulhsu a3, s10, s4 - rem a1, a2, t6 - andi gp, s10, -20 - slt zero, a4, s7 - c.andi a3, -13 - srl a3, gp, t2 -2977: c.beqz a0, 2986f - csrrw s0, 0x340, a2 - lui s7, 632924 -2980: mulhu s6, t1, a6 -2981: nop - or s1, s4, s9 - c.srli a0, 3 - csrrwi t5, 0x340, 31 - remu a4, t0, s9 -2986: c.sub a0, a4 - srai zero, t0, 24 - mulhsu a4, a6, s5 - andi s5, ra, -322 - .4byte 0x00100073 # ebreak - blt s8, s8, 3003f - beq s3, t4, 3011f - csrrwi a6, 0x340, 31 - nop - and s0, sp, t0 - c.mv s5, s10 - mulhu a5, s2, t1 - lui tp, 291569 - c.add s5, s11 - rem tp, a4, a4 - beq s6, s3, 3021f - mulh s10, s0, s7 -3003: auipc a7, 379441 - beq ra, gp, 3016f - bge t3, s0, 3023f - srli a7, tp, 3 - c.beqz s0, 3020f - csrrw s10, 0x340, s7 - nop - sltu t6, t6, tp -3011: slli tp, s5, 9 - csrrw a4, 0x340, a5 - mulhsu s5, t1, s11 - c.ebreak;c.nop; - c.addi s1, -4 -3016: c.andi a5, -2 - auipc gp, 318731 - slt s5, gp, s0 - c.or s0, s0 -3020: c.andi s0, 15 -3021: srli gp, a5, 31 - c.sub a1, a3 -3023: csrrc a2, 0x340, a0 - or s10, s2, s3 - srl s1, ra, a4 - c.andi s0, 26 - c.andi s1, -10 - slti s10, s2, 732 - c.andi a4, 17 - or t3, sp, s9 - bge gp, s0, 3032f -3032: c.slli s6, 10 - sub a0, s10, t4 - rem a1, tp, s4 - slli s7, s4, 9 - addi a1, t1, -43 - c.bnez s0, 3041f - c.xor a1, s0 - sub ra, s5, t0 - csrrc ra, 0x340, t1 -3041: remu t3, t1, t4 -test_done: - li gp, 1 - ecall -sub_2: c.nop - addi sp, sp, -64 - sw gp, 4(sp) - sra s7, a3, t4 - sltu s3, a3, a5 - addi ra, s9, 546 - srli s4, a5, 20 - xor s11, a0, t6 - mulhsu t5, s2, a0 - c.mv t0, s5 - andi tp, t2, 383 - remu t3, sp, s3 - la a2, region_1+14192 #start riscv_load_store_rand_instr_stream_1 - slli a1, t1, 28 - lb zero, 287(a2) - lbu t3, 538(a2) - csrrsi a3, 0x340, 26 - c.srai a0, 13 - c.ebreak;c.nop; - lb s3, -637(a2) - lh a6, -276(a2) - lb zero, -282(a2) - andi s6, a3, 597 - srl ra, a4, ra - sb a6, 49(a2) - srai s2, s6, 3 - c.srai a0, 28 - lbu a4, 135(a2) - sb tp, 678(a2) - srli s3, t4, 6 - sh s3, 300(a2) - c.andi a0, 1 - .4byte 0x00100073 # ebreak - sltu a3, t4, ra - andi t3, gp, 932 - srl s0, tp, t0 - mulh s5, s2, s8 - c.lui s6, 20 - rem s3, a0, s5 - csrrc a0, 0x340, s2 - auipc a6, 947258 - lb t2, -95(a2) - .4byte 0x00100073 # ebreak - srli s4, a6, 22 - slli a7, s11, 30 - slli gp, t6, 0 - lh tp, -852(a2) - c.srli s0, 8 - sw t3, 496(a2) - srai a7, s9, 25 - sb s4, 237(a2) - add a4, s8, s9 - lb s6, -101(a2) #end riscv_load_store_rand_instr_stream_1 - la tp, region_4+259 #start riscv_load_store_rand_instr_stream_0 - csrrs s10, 0x340, s5 - slt a6, gp, a5 - andi zero, ra, -487 - mulhu zero, a5, tp - lw a3, -3(tp) - lhu s10, 11(tp) - c.sub s1, s0 - rem s5, tp, t3 - srli s10, t0, 31 - srl s3, a1, tp - lh a1, -9(tp) - c.lui t5, 17 - c.or a3, s0 - or t1, s11, a0 - sltu s10, tp, s2 - csrrw s7, 0x340, t2 - lb t1, 16(tp) - .4byte 0x00100073 # ebreak - lb s10, -16(tp) - xor s6, s11, t2 - lb a6, -14(tp) - csrrci a3, 0x340, 12 - sub a2, a2, s5 - c.addi a2, -6 - lb a2, 15(tp) - lbu s7, 16(tp) - c.srli a5, 22 - c.addi s1, 12 - lhu s0, -15(tp) - csrrc a6, 0x340, t0 - sra s10, gp, s8 - xori s5, t3, 276 - nop - mulhu t6, s5, a5 - mulh t2, tp, t5 - mulhu s0, a5, s7 - lhu t2, -1(tp) #end riscv_load_store_rand_instr_stream_0 - la t6, region_1+6299 #start riscv_load_store_rand_instr_stream_2 - lw a6, 237(t6) - lb t3, 142(t6) - sll s2, a6, a7 - c.ebreak;c.nop; - sb s10, -202(t6) - sb a0, -222(t6) - lbu tp, 14(t6) - slli a0, t5, 4 - sb gp, 158(t6) - csrrs t2, 0x340, s0 - lbu t4, 41(t6) - lb s4, 8(t6) - sb s8, -184(t6) - c.addi a2, -19 - lbu a7, -212(t6) - sb a1, 89(t6) - sb ra, 156(t6) - lb gp, 133(t6) - lh s3, 111(t6) - lb zero, 37(t6) - lbu s7, 82(t6) - srli s1, a3, 24 - slti zero, ra, 158 - csrrci a0, 0x340, 21 - rem a1, a3, zero - lbu t2, -62(t6) - sb ra, -56(t6) - csrrc zero, 0x340, s10 - lbu gp, 245(t6) - lb a1, 223(t6) - csrrsi t0, 0x340, 19 - sb ra, -148(t6) #end riscv_load_store_rand_instr_stream_2 - la t3, region_0+1963 #start riscv_load_store_rand_instr_stream_3 - lbu a7, 479(t3) - sh a4, -143(t3) - c.add s10, tp - lhu a6, -23(t3) - lbu t5, -860(t3) - lhu s10, -113(t3) - sll a1, s11, a2 - lh s1, -929(t3) - lb a1, 677(t3) - sub a7, t3, t0 - or s7, tp, sp - lb a0, 395(t3) - add t2, s7, sp - sb s11, 679(t3) - srli a3, a1, 2 - sb a2, -220(t3) - c.add a2, a0 - c.or s1, a5 - sub a3, s9, a1 - c.srai a2, 18 - sh t2, -513(t3) - lbu s2, 166(t3) - lbu t4, -16(t3) - lbu t4, -5(t3) - lb a7, -1004(t3) - mulhsu a0, t2, sp - sh s0, 629(t3) - c.sub a0, a3 - c.li s2, 0 - sh s7, -797(t3) - lbu s7, 921(t3) - or t5, t2, a0 - or ra, a0, a6 - lhu a4, 623(t3) - ori a5, a0, -103 - lhu s11, -965(t3) - lbu ra, -484(t3) - rem t2, t5, s11 - lhu s10, -259(t3) - lb s10, -168(t3) - lbu s3, -113(t3) - andi t4, a7, 24 - csrrc a7, 0x340, a7 - sh s2, 923(t3) #end riscv_load_store_rand_instr_stream_3 - la s1, region_3+389 #start load_store_instr_stream_1 - la t3, region_3+436 #start load_store_instr_stream_3 - la t6, region_3+489 #start load_store_instr_stream_0 - sb a3, -194(s1) - lb a0, -10(t3) - lw ra, -53(t6) - la s6, region_3+81 #start load_store_instr_stream_2 - lb s0, -1(t3) - sh a3, -159(s1) - sh a3, 4(t3) - lb a6, 2(s6) - sb a1, -5(t3) - lbu s0, -7(t6) - lhu a3, 7(s6) - sb ra, -2(t3) - lw t4, -37(t6) - lh a2, -59(t6) - lb gp, -3(t3) - sb t0, -61(t6) - lbu s3, 8(s1) - lh a7, 1(t6) - lh a4, 10(t3) - lhu s2, 16(t3) - lb a7, 2(t6) - lb a2, 14(t3) #end load_store_instr_stream_3 - sh a2, -13(s6) - lbu t4, 45(s1) - lbu zero, 5(s6) - lbu s11, -202(s1) - sb t3, -10(s6) - lb s7, -50(t6) - sb s3, -50(s1) #end load_store_instr_stream_1 - lbu t5, -12(s6) #end load_store_instr_stream_2 - lb t5, -28(t6) #end load_store_instr_stream_0 - addi s0, zero, -7 #init loop 1 counter - div t6, s0, s8 - addi s10, zero, 6 #init loop 1 limit - sltiu a4, s6, -802 -sub_2_18_1_t: csrrsi t2, 0x340, 27 - csrrw a2, 0x340, t0 - xor s11, s9, s1 - addi s0, s0, 3 #update loop 1 counter - addi a3, zero, 1 #init loop 0 counter - slti t6, sp, 43 - addi zero, zero, 0 #init loop 0 limit -sub_2_18_0_t: c.or a1, a0 - addi a3, a3, -1 #update loop 0 counter - c.slli s11, 10 - c.bnez a3, sub_2_18_0_t #branch for loop 0 - srl a2, t2, s10 - bltu s0, s10, sub_2_18_1_t #branch for loop 1 - c.andi a2, 31 - la t0, region_0+3987 #start load_store_instr_stream_1 - sb s9, 49(t0) - la gp, region_4+191 #start load_store_instr_stream_2 - sh zero, -93(t0) - lbu a7, 164(gp) - lbu a5, 67(t0) - la t4, region_2+4717 #start load_store_instr_stream_0 - lw s11, -169(t4) - sb a3, 188(gp) - sb s2, -201(t0) - sb t6, 224(t4) - lh s0, 61(t0) - lb a2, -7(t0) - sb s8, 247(t4) - sw a1, 161(gp) - lh s3, -41(t0) - sb a7, -53(gp) - lw zero, -21(t4) - lbu ra, -188(t4) - lbu s4, -111(t0) - lb a7, 231(gp) - lbu a7, -102(t4) - sb a0, -142(gp) - lb s11, 75(t0) #end load_store_instr_stream_1 - lbu s6, -146(t4) - sb a6, 54(gp) #end load_store_instr_stream_2 - lbu a6, -254(t4) - sh s0, 237(t4) - lbu zero, 24(t4) #end load_store_instr_stream_0 -sub_2_5: jal gp, 1f -0: jal t1, 4f -1: c.jal 16f -2: jal t0, 25f -3: c.j 13f -4: c.j 9f -5: jal ra, 8f -6: jal ra, 17f -7: c.j 24f -8: c.jal 2b -9: c.jal 7b -10: jal t1, 11f -11: c.j 23f -12: jal t0, 19f -13: c.j 22f -14: c.jal 15f -15: c.j 21f -16: c.jal 20f -17: jal ra, 5b -18: c.j 14b -19: c.jal 0b -20: jal ra, 12b -21: c.j 3b -22: jal tp, 10b -23: c.j 6b -24: c.j 18b -25: rem s3, gp, s11 -sub_2_7: jal gp, 10f -0: jal a4, 20f -1: jal t1, 18f -2: c.jal 0b -3: c.j 24f -4: c.jal 13f -5: c.j 2b -6: c.j 27f -7: jal s11, 9f -8: jal a1, 25f -9: c.j 29f -10: jal ra, 26f -11: c.jal 8b -12: c.jal 19f -13: jal ra, 17f -14: jal t1, 16f -15: c.j 1b -16: c.j 23f -17: jal ra, 14b -18: c.jal 11b -19: c.jal 5b -20: c.j 15b -21: c.j 28f -22: c.jal 6b -23: c.jal 22b -24: jal t1, 7b -25: jal a4, 3b -26: jal s2, 4b -27: c.j 21b -28: c.jal 12b -29: sub s10, s2, gp - la s3, region_4+53 #start load_store_instr_stream_1 - la s7, region_0+1799 #start load_store_instr_stream_0 - lb s4, 8(s3) - sb a4, -242(s7) - lb ra, -9(s3) - sw a1, -207(s7) - lhu tp, -15(s3) - sb a6, -9(s3) - lbu ra, -16(s3) - sb s9, -9(s3) - lb gp, -75(s7) - lbu s5, 68(s7) - lb tp, 229(s7) - lbu t1, -12(s3) #end load_store_instr_stream_1 - lbu gp, 139(s7) #end load_store_instr_stream_0 - la a5, region_1+13109 #start riscv_hazard_instr_stream_0 - sb ra, 424(a5) - lbu t6, 534(a5) - lw a2, 619(a5) - sh ra, -351(a5) - sb t5, 400(a5) - sb t5, 344(a5) - lbu t5, 697(a5) - sh gp, -705(a5) - lhu ra, 141(a5) - lw ra, 659(a5) - sb t6, 882(a5) - sb gp, -48(a5) - c.lui t5, 18 - lhu t5, -729(a5) - slti ra, ra, 969 - sb t6, 358(a5) - add t5, t2, gp - sb a2, 268(a5) - sra ra, ra, t5 - lbu ra, 118(a5) - sb gp, 586(a5) - lb a2, 753(a5) - mul t5, t5, ra - mulhsu gp, ra, gp - lb ra, 642(a5) - sh t6, 753(a5) - sb t2, 181(a5) - sh t6, 985(a5) - sb t5, 418(a5) - add t2, t2, t5 - sb gp, 839(a5) - nop - lb ra, -148(a5) - sll ra, t5, t6 - lb t6, 800(a5) - mulh t6, ra, ra - lh a2, -171(a5) - auipc t5, 886068 - c.xor a2, a2 - sb t5, -34(a5) #end riscv_hazard_instr_stream_0 - la t3, region_3+496 #start load_store_instr_stream_2 - la a4, region_4+209 #start load_store_instr_stream_4 - la gp, region_0+2167 #start load_store_instr_stream_3 - la s2, region_1+12425 #start load_store_instr_stream_1 - lb s6, -8(a4) - la s1, region_2+5828 #start load_store_instr_stream_0 - lbu a6, -28(s2) - lbu a5, 537(s1) - sw t5, 31(a4) - sb ra, -52(s2) - lbu a0, -357(t3) - sb s6, -370(gp) - lbu s10, 667(s1) - sh s1, -29(a4) - lbu t6, -928(gp) - sb tp, -300(t3) - sh s10, 942(s1) - lbu s10, -19(s2) - lb s5, -887(s1) - lhu s5, -7(s2) - sb zero, -20(s2) - sw zero, -17(a4) - lb s4, 415(gp) - lb t5, -51(s2) - lb t4, -733(gp) - lw a7, 116(s1) - sb s1, -93(t3) - lb s11, -24(a4) #end load_store_instr_stream_4 - sh ra, -225(gp) - lw zero, -33(s2) - sh t2, -18(t3) - lb s11, 964(s1) - lbu a6, -589(s1) - sb s10, 438(gp) - lbu a3, 39(s2) - lbu t1, -247(t3) - lb a3, 250(gp) #end load_store_instr_stream_3 - lbu t6, -46(s2) #end load_store_instr_stream_1 - sb t6, -183(t3) #end load_store_instr_stream_2 - sb s10, 92(s1) #end load_store_instr_stream_0 - addi a6, zero, 6 #init loop 1 counter - addi t2, zero, 5 #init loop 1 limit -sub_2_17_1_t: sll t0, s6, t4 - addi a6, a6, -6 #update loop 1 counter - addi s0, zero, -5 #init loop 0 counter - addi zero, zero, 0 #init loop 0 limit -sub_2_17_0_t: sltiu a2, s5, 859 - addi s0, s0, 5 #update loop 0 counter - c.beqz s0, sub_2_17_0_t #branch for loop 0 - bge a6, t2, sub_2_17_1_t #branch for loop 1 - c.ebreak;c.nop; - la a2, region_3+323 #start load_store_instr_stream_2 - la a5, region_3+368 #start load_store_instr_stream_0 - la a1, region_3+119 #start load_store_instr_stream_1 - lbu s6, -76(a2) - lh t1, 117(a1) - lb a7, -58(a5) - sb s1, 376(a1) - lw s5, 61(a2) - lb t3, -166(a2) - sb tp, 256(a1) - lbu t2, 166(a1) - sb sp, -34(a5) - lbu s4, -140(a2) - lhu t1, 52(a5) - lbu s2, -76(a2) - sh a7, 249(a1) - sb a0, -33(a2) - lb t3, 1(a5) - sb s6, 18(a2) - lb a3, -124(a2) - sb s0, -49(a5) - lhu a6, 60(a5) - lbu t4, 268(a1) - lhu s6, 11(a1) - lbu s11, 50(a1) - lbu tp, -11(a2) #end load_store_instr_stream_2 - lhu t6, -10(a5) - sb s11, -27(a5) - lb t0, 277(a1) - lh s4, -48(a5) - lbu t4, -59(a1) #end load_store_instr_stream_1 - lb t4, -9(a5) #end load_store_instr_stream_0 - la t6, region_3+240 #start riscv_hazard_instr_stream_2 - sll s10, s4, s10 - slli t5, s10, 25 - lbu s1, -12(t6) - csrrci s10, 0x340, 28 - c.sub s1, a5 - lbu s1, 11(t6) - mulhsu s1, t5, a5 - srli a5, s10, 12 - lui a5, 940248 - csrrw a5, 0x340, a7 - c.mv s1, s4 - lbu s10, 11(t6) - ori s4, a7, 21 - c.nop - sh s4, 2(t6) - lbu s10, -7(t6) - lbu t5, 7(t6) - c.addi s4, -20 - lb a7, 12(t6) - lw s1, -16(t6) - slt s1, a7, t5 - lb a7, -7(t6) - lbu s10, -11(t6) - nop - c.srai a5, 10 - xor t5, t5, s1 - lbu s4, 5(t6) - lh s4, -12(t6) - lbu t5, -13(t6) - ori a7, a5, 258 - lb s4, 13(t6) - c.nop - c.lui s4, 27 - sh s10, -10(t6) - lh a5, 2(t6) - sb a5, 0(t6) - lhu s10, -16(t6) - auipc s10, 274007 - lh a7, -6(t6) - lb s10, 11(t6) #end riscv_hazard_instr_stream_2 - addi t4, zero, -4 #init loop 0 counter - c.nop - c.andi a1, -6 - addi ra, zero, 10 #init loop 0 limit - and t5, zero, s5 -sub_2_16_0_t: c.or a0, a0 - andi s7, tp, -754 - addi t4, t4, 9 #update loop 0 counter - nop - c.ebreak;c.nop; - or s3, a7, a1 - c.xor a5, a2 - c.andi a2, -21 - sra s4, s10, a6 - bltu t4, ra, sub_2_16_0_t #branch for loop 0 - c.andi a0, 21 - la t2, region_4+3323 #start load_store_instr_stream_2 - la s2, region_4+1207 #start load_store_instr_stream_0 - la s5, region_4+3448 #start load_store_instr_stream_3 - lbu s7, -28(t2) - lb t4, 398(s5) - lb t6, 457(s5) - sb t4, -1016(s2) - sh gp, 13(t2) - lb s3, 36(t2) - lb s0, -48(t2) - lbu t3, -994(s2) - sh s11, -501(s2) - lb s7, 8(t2) - lh ra, 612(s5) - la s6, region_4+2431 #start load_store_instr_stream_1 - sh t3, -440(s5) - lb a6, 222(s6) - sb t4, -339(s5) - lb zero, -40(t2) - lbu a1, -901(s5) - sb a7, -96(s6) - lbu s10, -12(s5) - lbu a2, 530(s2) - lb a1, -36(s6) - lb t6, -97(s6) - lbu s1, -14(t2) - sb a1, -42(s6) - lbu t6, -78(s6) - sb ra, -1019(s5) #end load_store_instr_stream_3 - lbu a7, -195(s6) - lbu t1, 10(t2) #end load_store_instr_stream_2 - lbu a6, -69(s6) #end load_store_instr_stream_1 - sb s11, 176(s2) #end load_store_instr_stream_0 - la s10, region_1+1100 #start riscv_hazard_instr_stream_1 - c.andi s1, -2 - c.slli s2, 13 - mulh s11, s1, s11 - lb a5, -227(s10) - lhu s1, -92(s10) - sb s2, -141(s10) - sb s11, -114(s10) - sltiu a5, s1, -261 - sh s4, -108(s10) - auipc s0, 691150 - lbu s11, 120(s10) - lbu s2, -169(s10) - nop - remu s1, s2, a5 - c.mv s11, s1 - or s4, s0, s2 - srai s2, s0, 7 - sh s0, 34(s10) - lb s1, -105(s10) - c.or s0, s1 - sb a5, 195(s10) - mulhsu s1, s1, a5 - lh s0, -190(s10) - srli s0, s1, 30 - nop - lbu s4, 11(s10) - sb s4, -19(s10) - sw s0, 124(s10) - mulh s2, s0, a5 - sh s11, -4(s10) - sll s1, a5, s2 - lb s2, -78(s10) - c.li s11, -1 - ori s11, s1, 313 - c.li a5, 24 - lbu s4, 71(s10) - csrrw s11, 0x340, s11 - sw s4, -116(s10) - lbu s1, 185(s10) - sw s11, -72(s10) - lbu s0, 163(s10) - srai s4, s0, 9 - slt s4, a5, s11 - lbu s1, -101(s10) - csrrci s2, 0x340, 2 - lb s1, 7(s10) #end riscv_hazard_instr_stream_1 - bne sp, sp, 12f - xor s0, a1, a1 - mul ra, a6, s11 - and a2, t0, s6 - xor s5, t4, zero - and a5, t0, a2 - addi a5, s7, 552 - c.srai a2, 16 - c.srli s0, 13 - or t0, s5, a7 - c.bnez a0, 23f - sltu s7, t3, s10 -12: csrrs t6, 0x340, gp - or gp, s0, s4 - sltiu s1, t6, 127 - divu a4, t0, t3 - csrrw s3, 0x340, s7 - nop - c.add t2, s11 - bltu s3, ra, 30f - c.srli s1, 20 - andi a2, gp, 188 - c.lui s7, 26 -23: sra gp, s4, s9 - c.and a3, a2 - bltu s10, ra, 32f - c.beqz a3, 31f - srl a7, a1, a7 - nop - mulh s3, a2, a0 -30: ori ra, s5, 261 -31: csrrs s11, 0x340, a5 -32: csrrc s11, 0x340, a7 - bne t1, s4, 36f - mulhu a7, s2, t3 - blt a0, t6, 43f -36: lui gp, 440233 - divu ra, t0, s0 - csrrw a1, 0x340, zero - c.srli s0, 28 - c.lui a1, 1 - csrrc t5, 0x340, s8 - lui a7, 1026660 -43: csrrsi s2, 0x340, 28 - addi s1, s11, -483 - c.and a3, a1 - .4byte 0x00100073 # ebreak - ori zero, a7, 387 - bne s6, t0, 66f - srl a6, s5, gp - csrrs t1, 0x340, s11 - add a6, zero, s3 - ori a3, s1, 77 - and a2, zero, a1 - mulhu a3, a0, t0 -sub_2_6: jal gp, 5f -0: c.j 3f -1: jal t0, 16f -2: jal s4, 15f -3: c.jal 12f -4: c.j 6f -5: jal s4, 8f -6: c.jal 14f -7: jal t1, 0b -8: c.j 4b -9: c.j 10f -10: c.j 11f -11: jal gp, 17f -12: jal s6, 1b -13: c.j 7b -14: c.jal 13b -15: c.j 9b -16: c.jal 2b -17: c.xor s0, a3 - c.or a2, a2 - mulhsu s2, ra, t3 - sltiu s5, a1, 240 - c.bnez s1, 66f - srli s3, s10, 26 - c.slli tp, 15 - nop - srli s5, gp, 30 - auipc t1, 441617 - c.add t4, s9 - csrrci s3, 0x340, 25 -66: srl s3, a4, a4 - c.bnez a2, 75f - c.srai s1, 17 - c.slli s3, 2 - or t2, ra, a5 - slti s4, a1, -826 - la t1, region_4+1973 #start load_store_instr_stream_2 - la s4, region_1+12100 #start load_store_instr_stream_1 - lbu a7, 903(t1) - sb t4, -380(t1) - la t2, region_3+143 #start load_store_instr_stream_0 - lbu a4, -82(s4) - sb s6, -79(s4) - lb t4, 226(t2) - lhu gp, -166(s4) - lb t0, 90(s4) - lbu a5, 17(s4) - sh a6, 263(t2) - lbu s2, 220(t1) - lb a2, 35(t2) - lb s1, -114(s4) #end load_store_instr_stream_1 - lb a1, 31(t1) - lhu t5, 293(t1) - sb t1, 90(t2) - lbu gp, 360(t1) #end load_store_instr_stream_2 - sb s3, 298(t2) #end load_store_instr_stream_0 - csrrs s7, 0x340, t1 - beq a2, s0, 88f - c.beqz a1, 84f -75: c.bnez a4, 76f -76: c.andi a0, -18 - sub a6, a7, a2 - c.or a1, s1 - sltiu s11, a4, -551 - c.li s5, -12 - srli a7, a0, 27 - c.and s1, s1 - sltiu a0, s7, -553 -84: rem a6, ra, a7 - c.mv s10, s0 - mulhsu s7, s8, s9 - csrrw a5, 0x340, sp -88: lui s7, 413888 - c.ebreak;c.nop; - c.bnez s1, 95f - mul s1, t3, s1 - c.srli a2, 28 - c.beqz a1, 111f - beq s11, s1, 107f -95: beq sp, tp, 99f - sltu s1, s1, s2 - .4byte 0x00100073 # ebreak - srli a3, t6, 5 -99: c.slli s11, 15 - addi t3, a7, 235 - bne s5, a0, 116f - bgeu s0, t0, 110f - mul s7, tp, sp - beq s4, s6, 105f -105: c.srli a3, 17 - bge a1, a5, 107f -107: mul gp, t2, t6 - c.beqz s1, 114f - c.addi a6, 21 -110: bne gp, a5, 113f -111: xori gp, s0, 339 - xori s0, s9, -600 -113: csrrwi gp, 0x340, 9 -114: srai t1, s5, 11 - bne a4, a4, 118f -116: c.add s5, tp - sub ra, t5, s7 -118: sub s4, s0, ra - srai s0, s4, 31 - mul gp, zero, s9 - c.bnez s1, 130f - csrrwi a1, 0x340, 22 - mulhsu gp, ra, s10 - remu a2, t0, a1 - or s5, a1, s6 - andi s0, s1, 354 - sltu a1, a5, t0 - c.ebreak;c.nop; - sltiu t2, s4, -209 -130: slti t6, a5, 968 - .4byte 0x00100073 # ebreak - c.mv t2, a2 - or s10, t0, a4 - sra s11, t6, t6 - slli s4, s6, 1 - csrrwi a6, 0x340, 2 - sll t2, t2, sp - sra s2, s6, t4 - rem s10, t5, a4 - bgeu t0, t3, 146f - slli t3, t2, 3 - lui t4, 1014003 - c.slli s2, 5 - c.bnez a2, 156f - csrrci a4, 0x340, 16 -146: bltu ra, tp, 148f - csrrsi s2, 0x340, 25 -148: auipc s3, 934217 - slti t2, s1, 681 - blt a2, gp, 160f - beq a3, s6, 164f - csrrci gp, 0x340, 14 - srli s6, a5, 4 - srai a4, t6, 13 - sltiu s5, a0, 441 -156: xori zero, a4, 47 - sub a7, t1, a5 - sra tp, s3, tp - c.mv a4, a1 -160: c.bnez a0, 175f - div t3, s6, t5 - c.slli t0, 29 - sltu ra, s8, s9 -164: mulh s3, s2, s0 - addi s11, zero, -459 - sltu a2, tp, t5 - add s5, a0, s4 - mul t3, s11, t3 - nop - c.ebreak;c.nop; - c.bnez a2, 177f - c.mv s10, a1 - xori s5, a0, 239 - div s1, s2, s2 -175: ori s5, t3, -977 - mul s3, s9, s7 -177: csrrc s1, 0x340, ra - c.nop - or s2, t5, s10 - c.xor a2, s0 - or zero, a3, s2 - bne t5, s10, 192f - mulh tp, s5, a1 - c.slli a3, 21 - slli t5, t5, 3 - rem t1, a4, a6 - srl a2, a4, sp - and a3, s4, t2 - bne s8, t1, 197f - blt a0, a0, 196f - c.sub a3, a3 -192: slti s5, s1, 959 - c.or a0, a3 - mul s3, a1, s9 - lui s4, 573303 -196: auipc gp, 12781 -197: div t5, tp, a3 - auipc s10, 892344 - c.xor a4, a3 - c.srai a5, 5 - sll t2, t0, a7 - slli t0, t2, 16 - c.xor a3, a0 - sltiu zero, s2, 59 - c.sub s0, a4 - csrrsi gp, 0x340, 0 - srl t6, a2, a3 - beq s9, gp, 217f - c.and a4, s0 - csrrw s6, 0x340, s6 - sltu s6, s1, a4 - xori t3, s0, 309 - andi s1, t5, -708 - c.add gp, t5 - c.srli a1, 22 - mul tp, s4, a4 -217: csrrw a6, 0x340, s7 - c.andi s1, -7 - divu t4, t4, s0 - xor a0, a3, t6 - slti a6, s10, 367 - divu s1, zero, a4 - c.mv t0, t5 - remu zero, s11, zero - c.sub a5, a5 - csrrc s0, 0x340, s0 - c.sub s1, s0 - c.sub s0, a0 - c.sub a3, s0 - c.slli t3, 26 - c.andi a0, 12 - slli t6, s3, 12 - add t2, a1, t0 - srl t3, a0, s4 - c.and a4, a0 - c.or a2, a2 - .4byte 0x00100073 # ebreak - csrrsi t6, 0x340, 28 - rem gp, s10, gp - csrrs s3, 0x340, t5 - c.lui a7, 14 - c.addi a0, -30 - c.xor a4, a5 - csrrci t6, 0x340, 31 - c.mv a5, s10 - ori a0, s5, -945 - c.lui tp, 6 - c.beqz s0, 256f - bgeu s3, s3, 259f - c.or a4, a0 - addi s7, t1, 328 - csrrc t3, 0x340, s7 - add s11, tp, a0 - slli a0, a2, 24 - c.bnez a1, 267f -256: c.lui s11, 31 - c.lui s6, 20 - c.slli t2, 22 -259: addi t4, t0, -18 - csrrci t4, 0x340, 4 - srai t1, t3, 7 - mulhsu s10, s2, s0 - c.bnez a1, 264f -264: c.mv s10, ra - c.xor s0, a2 - c.mv t0, a3 -267: c.li s4, -26 - .4byte 0x00100073 # ebreak - mulhsu a5, s8, t1 - or zero, s5, s5 - mulhu a0, t6, s11 - srai s2, s11, 3 - ori s5, s11, -156 - or a4, s5, t2 - sltiu a1, tp, 631 - c.and s0, s0 - c.beqz a4, 278f -278: remu t6, gp, s7 - sltu s7, a1, t2 - c.bnez a4, 283f - remu s2, a2, s2 - sra a4, s5, a2 -283: mul s10, a2, a6 - c.or s1, a4 - la t1, region_2+1093 #start load_store_instr_stream_1 - la s6, region_2+2134 #start load_store_instr_stream_2 - la s3, region_2+1247 #start load_store_instr_stream_3 - la s7, region_2+7123 #start load_store_instr_stream_4 - lw s5, -39(s7) - lb t2, 31(s7) - la tp, region_2+2241 #start load_store_instr_stream_0 - lb s1, 15(s7) - lb a5, 22(t1) - lb t3, 17(s6) - lb t3, -45(s6) - lb a7, -23(s7) - lb s10, 32(t1) - lbu t5, 63(t1) - lbu a0, -759(tp) - lhu s2, -13(s3) - lw a1, 23(t1) - sb a5, 41(s6) - lb t5, -24(tp) - lbu t0, -32(s6) - lb t0, -45(s7) - lbu s0, -26(t1) - lbu ra, 983(tp) - sb t3, -52(s6) - lb t2, -62(t1) - lb a3, -816(tp) - lb s2, 522(tp) - lbu a7, 10(s7) - lb a1, 8(s3) - lbu t5, 671(tp) - sb a6, 4(s3) - sb tp, -10(s3) - lbu s1, 7(s7) - lb t4, -29(t1) - lbu t0, 14(s3) - lb t3, 44(tp) - sh a4, -11(s7) - lb ra, 6(s3) - sb s9, 10(t1) - sb s9, 9(s3) #end load_store_instr_stream_3 - sb a0, -62(s6) - lhu a3, -51(t1) - lbu t0, 54(s7) - lw t4, -3(s7) #end load_store_instr_stream_4 - lb a2, -667(tp) - lb s0, 10(t1) #end load_store_instr_stream_1 - lb a0, -39(s6) #end load_store_instr_stream_2 - lbu s5, -659(tp) #end load_store_instr_stream_0 - c.srli s1, 24 - csrrs tp, 0x340, a2 - slt a3, ra, t1 - bne a4, s5, 299f - slli ra, t0, 21 - srai t4, s9, 7 - c.nop - c.lui t0, 11 - csrrc ra, 0x340, s9 - csrrs t1, 0x340, t6 - sub s7, s6, a7 - xor t2, t6, zero - c.slli t3, 13 - c.or s0, a1 -299: mulhsu s10, a7, s2 - bne a5, t5, 305f - c.mv a7, t5 - sltu zero, zero, t2 - xor s11, t3, s0 - c.slli s11, 7 -305: c.beqz a5, 323f - c.srai s0, 5 - csrrsi a1, 0x340, 27 - csrrci a1, 0x340, 15 - slli s0, a5, 26 - c.ebreak;c.nop; - bne t1, s4, 314f - nop - c.slli t2, 24 -314: c.ebreak;c.nop; - bltu s6, t2, 319f - c.slli a3, 23 - mulh s1, s5, a1 - or s4, t4, s3 -319: sltiu a1, s10, -317 - srli s6, t4, 17 - sub t0, a1, zero - sll a7, t1, t1 -323: srl s2, t6, s9 - mulhsu s2, s10, t2 - csrrci t0, 0x340, 5 - .4byte 0x00100073 # ebreak - slt s0, s10, a4 - rem s3, ra, t5 - xori s3, tp, -315 - mulhsu t4, zero, s3 - divu a1, gp, t3 - csrrs a4, 0x340, s2 - divu a7, s5, a7 - c.nop - or s6, t2, s8 - c.or a5, a4 - c.mv a0, t3 - c.slli t3, 22 - and a1, t3, s9 - c.slli s4, 31 - add s11, s10, a0 - xori a2, a2, 21 - nop - csrrci s1, 0x340, 18 - csrrc tp, 0x340, t5 - c.beqz a1, 359f - sll a3, s7, a1 - c.andi a4, 16 - xori zero, a2, 403 - c.sub a2, a1 - c.nop - csrrc s4, 0x340, s7 - xor a0, a4, t0 - or ra, a3, t2 - beq t0, s1, 363f - auipc s2, 1006943 - srai a0, s7, 20 - c.beqz a0, 363f -359: lui a7, 428888 - bltu t4, t2, 361f -361: csrrci a4, 0x340, 5 - srai t2, sp, 4 -363: c.sub a5, s1 - beq s3, a6, 377f - sltiu a7, a2, 196 - addi s10, t4, -309 - c.andi a1, -12 - c.mv s4, t1 - csrrw s6, 0x340, s10 - divu s7, t5, t4 - xor s7, a6, s5 - slt t5, t6, t3 - c.lui a2, 31 - srl a3, a5, tp - mulh a1, a2, t3 - add a7, t1, s0 -377: c.and a4, a4 - c.ebreak;c.nop; - sll t6, s7, a2 - sll a0, t0, a0 - andi s4, a5, -69 - and s4, s7, s7 - auipc t0, 667201 - c.srai a0, 9 - bge s7, s11, 398f - or s1, t3, t3 - c.andi a2, 25 - csrrsi s1, 0x340, 7 - sub s1, s1, t3 - c.beqz s0, 405f - blt t0, s3, 409f - beq s3, a5, 395f - beq ra, t0, 395f - or a7, s2, a2 -395: mulhu t4, s3, sp - or a3, a7, tp - slt s1, tp, sp -398: mul s0, t4, s1 - sra a3, s3, s11 - c.sub a0, a5 - bne a6, s5, 413f - sltiu a0, a1, -160 - csrrw s0, 0x340, a1 - beq a3, a0, 412f -405: csrrci s6, 0x340, 28 - bltu zero, s0, 413f - c.beqz a3, 410f - sub a5, s10, t0 -409: c.ebreak;c.nop; -410: c.add a7, s0 - blt s11, s10, 423f -412: ori a1, s3, -483 -413: beq a4, t6, 426f - auipc t2, 644136 - mulh s0, s4, s9 - slt ra, s1, s5 - div s0, a0, s7 - bgeu a3, s10, 436f - c.li s6, -29 - .4byte 0x00100073 # ebreak - c.and s0, s1 - c.sub s1, a4 -423: srl t0, s11, sp - xori a4, ra, 599 - .4byte 0x00100073 # ebreak -426: mulhu s1, s4, t0 - csrrc a7, 0x340, t4 - mulhu tp, s11, s3 - sll s4, s7, t0 - bgeu t0, a3, 435f - mulhsu s2, t4, ra - lui zero, 567133 - bgeu a5, tp, 436f - srli a6, a2, 7 -435: add s10, s10, ra -436: csrrwi s1, 0x340, 9 - sra gp, t4, s1 - c.sub a3, a1 - c.sub a2, a5 - c.add s6, a2 - c.add s0, s5 - csrrwi s4, 0x340, 0 - csrrs s7, 0x340, s4 - csrrw t3, 0x340, zero - c.and a5, s0 - blt s1, a6, 461f - xor t6, a2, a0 - and a1, sp, t2 - srai gp, a7, 6 - sra ra, t2, s11 - andi gp, s3, 883 - ori t2, a7, -74 - sltu s2, s6, s4 - slli t2, s7, 0 - beq s8, t5, 461f - bgeu zero, a6, 461f - mul s10, zero, s6 - c.li a3, -27 - c.srai a0, 14 - bge t6, a1, 464f -461: c.andi s1, 0 - c.ebreak;c.nop; - c.srai a2, 14 -464: srli t4, s9, 16 - csrrsi t2, 0x340, 8 - rem a6, t2, sp - slli s3, gp, 18 - blt t1, a0, 480f - sra t5, tp, t3 - slt s0, zero, a0 - bne a6, s0, 479f - c.beqz a1, 473f -473: c.bnez s1, 483f - add gp, s0, s6 - csrrwi ra, 0x340, 1 - csrrw s0, 0x340, s8 - sltu a4, ra, s9 - sra a1, ra, s1 -479: and s10, a7, s6 -480: mulhu t0, a5, s2 - c.mv t3, a5 - remu ra, gp, s2 -483: c.beqz a5, 489f - xor ra, s6, ra - slli a7, t2, 28 - bge s1, gp, 496f - or a5, zero, s7 - sltu s0, s4, gp -489: auipc t3, 19451 - divu a6, a3, a3 - c.bnez s1, 499f - slt t4, a3, a1 - csrrw t0, 0x340, a7 - auipc s7, 122954 - bne a1, s1, 502f -496: c.add t5, s8 - bltu s1, s10, 498f -498: mulhu a1, a6, t6 -499: srli a0, t1, 17 - c.addi t2, 20 - mul s7, t0, s5 -502: c.ebreak;c.nop; - srai t1, t4, 24 - csrrw a3, 0x340, s3 - bne ra, s0, 508f - c.sub s0, a0 - c.li t3, 27 -508: slt tp, a6, t0 - c.li t1, 17 - srl s2, t4, s7 - c.mv a3, a3 - xori tp, s11, 585 - c.nop - srl t4, s6, a2 - c.beqz a2, 517f - bgeu s4, a0, 534f -517: add t2, t0, s3 - c.slli t3, 6 - slli s0, s11, 17 - bge a2, s9, 521f -521: sltiu s4, a1, -756 - lui s3, 616822 - addi a5, tp, -479 - divu zero, t0, a3 - mulh t3, t5, s2 - xori a3, t5, -721 - add t3, t6, s9 - mulhsu s10, a5, a6 - csrrsi t1, 0x340, 16 - mulh s4, s9, s10 - slli a5, a0, 27 - c.srai a4, 1 - csrrwi s6, 0x340, 13 -534: c.or a5, a5 - andi t2, tp, 337 - c.and a3, a5 - sra a1, s8, s7 - xori tp, tp, 371 - andi s4, s8, 843 - c.andi a3, 11 - auipc s2, 586091 - sltiu s1, s5, 411 - beq tp, gp, 558f - mul s5, t0, s0 - remu s10, s10, s10 - remu s4, s9, ra - blt s1, s5, 560f - mul ra, t5, gp - bne a5, s4, 560f - divu a5, a0, s11 - csrrw a0, 0x340, s9 - sltu t4, s4, ra - sll a0, a7, sp - bge s11, zero, 567f - srl tp, zero, t3 - mulhsu gp, t6, a0 - c.srai a0, 21 -558: slt t5, s1, a5 - xor s6, t0, s1 -560: remu t2, a1, a3 - ori t2, zero, 154 - xor s6, zero, zero - mul s4, s11, s2 - c.li a3, 12 - rem gp, a4, s10 - c.add a5, t1 -567: sra t6, s9, t1 - srl a7, s3, s4 - c.mv s4, s11 - or t0, s11, ra - c.li t2, -21 - mul zero, a7, s0 - bge a2, s9, 581f - c.sub a0, s0 - mulhsu s6, ra, s11 - bgeu tp, zero, 585f - slli tp, a4, 18 - mulhu t2, a2, s6 - xori t4, s11, -398 - mulhu t6, a2, tp -581: c.bnez a0, 589f - mulh s3, a4, s3 - add t2, s1, s1 - sub s4, zero, a7 -585: sll a2, a5, a0 - c.ebreak;c.nop; - mul s4, gp, a6 - bne t0, t6, 603f -589: xori s6, s1, -447 - sra s7, s9, s8 - csrrs a1, 0x340, a6 - and s7, s2, s0 - c.srai a5, 19 - c.addi tp, -8 - csrrwi t1, 0x340, 16 - csrrwi zero, 0x340, 2 - c.addi s3, -2 - lui t4, 827079 - add ra, s10, a7 - and t1, sp, s5 - add a5, t1, s5 - auipc t3, 694951 -603: sub a6, s8, t2 - add s0, s5, sp - c.and a2, a5 - slt a0, t1, sp - sltiu s3, s0, -96 - c.nop - csrrci t1, 0x340, 8 - c.slli s2, 11 - .4byte 0x00100073 # ebreak - c.xor a3, a4 - blt a3, s4, 614f -614: c.addi tp, 1 - xori a3, a6, 187 - ori t2, s4, 787 - ori t0, s9, -648 - sltiu a4, tp, 944 - sltiu s3, s5, 855 - csrrs t5, 0x340, t4 - c.andi s1, -27 - csrrwi a0, 0x340, 25 - c.or s1, a5 - mul a4, s2, s4 - beq t0, t5, 635f - c.addi a1, -32 - c.and a0, a1 - c.li a5, -4 - slt s3, a1, s10 - srl tp, s4, s9 - c.xor s1, a2 - c.beqz a2, 645f - bge s2, s1, 643f - sra a2, s4, s2 -635: and a7, tp, a7 - blt s7, t3, 648f - and s10, t4, s6 - bgeu s11, s0, 646f - c.ebreak;c.nop; - c.slli t0, 1 - bge t1, t5, 643f - addi s5, t5, -240 -643: c.nop - mulhu t4, s4, t1 -645: c.ebreak;c.nop; -646: add a0, s2, t1 - slti s6, t4, 594 -648: mulh a3, s0, s9 - c.and a1, a3 - csrrc t0, 0x340, tp - c.mv t6, t1 - bltu s4, t3, 655f - or s7, ra, a3 - slt a6, t5, s4 -655: xori s5, s6, 803 - c.mv a5, gp - mulh gp, sp, t2 - div s3, s4, s10 - and t1, s6, a2 - c.srli a3, 29 - rem s1, gp, t0 - c.srai a0, 6 - beq t2, tp, 666f - c.lui s3, 2 - sra s11, a2, t3 -666: c.andi a1, -11 - c.sub a3, a2 - slli a5, s8, 11 - remu zero, a4, t2 - blt a1, s6, 681f - c.li a3, 19 - c.srli a5, 13 - mulhu a0, s11, a2 - slt s2, s5, s6 - auipc a2, 275418 - c.lui t4, 29 - andi t0, s2, 492 - rem s3, a6, a7 - c.srli a2, 25 - divu t1, t4, t0 -681: bge zero, t2, 689f - bne t1, s11, 687f - srl a5, t2, s5 - beq s6, t3, 699f - mulhu s4, s6, a5 - c.srai a4, 9 -687: c.slli s3, 14 - c.srai a4, 2 -689: c.beqz s0, 694f - c.mv t4, s3 - rem a3, s8, tp - sltiu a7, s3, -412 - mulhsu s1, a7, t1 -694: bge t0, a4, 701f - c.nop - c.srli a0, 1 - c.andi a4, 18 - divu t3, sp, s2 -699: c.beqz a0, 708f - c.bnez a3, 718f -701: divu a0, s2, t2 - addi t5, ra, 683 - c.srli s1, 23 - c.slli s6, 22 - sub a1, sp, s9 - bgeu a6, a6, 719f - beq s7, t1, 708f -708: csrrci s5, 0x340, 13 - addi a4, zero, 924 - nop - csrrw s5, 0x340, t2 - slti zero, t0, 296 - csrrsi t4, 0x340, 24 - srl s2, s2, sp - mulhsu s0, zero, t2 - csrrci s3, 0x340, 23 - addi gp, ra, -581 -718: sll a7, s8, s8 -719: nop - csrrwi t5, 0x340, 9 - sra gp, a3, a2 - c.andi a1, 9 - srl s3, t0, s1 - csrrs tp, 0x340, a0 - blt tp, sp, 743f - c.beqz a2, 734f - bgeu tp, t0, 739f - c.srai a4, 15 - slli t0, a2, 8 - c.mv s3, s2 - ori zero, a2, 54 - csrrs zero, 0x340, s0 - or t5, a3, s7 -734: mulh s3, s3, a0 - andi s5, t5, -428 - sub a1, t3, s5 - c.srai a4, 30 - mulhu s0, s2, ra -739: c.add a2, s3 - add t1, t2, s3 - srl s2, t6, a3 - or s5, s10, tp -743: mulh s4, a4, a3 - c.ebreak;c.nop; - bge s2, a5, 746f -746: lui s2, 181520 - addi gp, zero, 508 - c.add s3, t1 - csrrsi gp, 0x340, 11 - csrrc tp, 0x340, s9 - csrrci a2, 0x340, 19 - addi a7, ra, -783 - bge s9, a5, 756f - csrrwi a4, 0x340, 11 - .4byte 0x00100073 # ebreak -756: csrrci tp, 0x340, 11 - c.mv gp, ra - sltiu s1, s8, 333 - csrrsi s3, 0x340, 23 - c.and s0, s1 - csrrwi s1, 0x340, 19 - c.sub a4, a2 - rem zero, t1, s1 - .4byte 0x00100073 # ebreak - srl s7, s3, s9 - csrrc s2, 0x340, s7 - lui s5, 827953 - bne a3, t0, 772f - blt gp, s7, 775f - sra a2, a6, tp - srli s2, t5, 14 -772: auipc a7, 720648 -sub_2_4: jal gp, 6f -0: jal ra, 4f -1: jal ra, 13f -2: jal a1, 15f -3: jal t1, 11f -4: jal t1, 12f -5: jal ra, 17f -6: c.jal 2b -7: c.j 0b -8: c.j 3b -9: jal t1, 16f -10: c.jal 9b -11: c.j 7b -12: c.jal 5b -13: jal ra, 14f -14: c.jal 10b -15: jal t1, 8b -16: jal ra, 18f -17: c.jal 1b -18: slt s6, s7, zero - csrrci t4, 0x340, 3 - csrrwi s3, 0x340, 5 -775: csrrwi tp, 0x340, 18 - nop - csrrw a2, 0x340, s11 - c.add tp, sp - ori tp, s9, -935 - srl s0, sp, ra - nop - bne ra, s4, 788f - mul t1, zero, a1 - csrrc a2, 0x340, s3 - c.li s11, 28 - c.nop - lui s0, 483671 -788: lui t0, 610414 - c.lui s7, 24 - bgeu s3, a1, 798f - andi s11, t5, -507 - srli s6, gp, 13 - add s2, t4, s8 - ori a6, s8, 459 - xori s3, t5, 113 - auipc s3, 70999 - bge s11, t2, 810f -798: csrrsi tp, 0x340, 19 - mulhsu a5, sp, s11 - c.sub s0, a5 - c.mv gp, a4 - sltu s10, s3, t5 - srli t1, a3, 1 - csrrsi t5, 0x340, 29 - c.beqz s0, 807f - addi a2, t4, -636 -807: bgeu a6, zero, 808f -808: sltu t3, s3, s1 - c.srli a4, 27 -810: c.mv t5, a5 - c.lui a0, 18 - c.addi ra, 17 - c.slli tp, 18 - c.sub s0, a1 - auipc gp, 431627 - c.sub a5, s1 - c.bnez a1, 830f - slt s3, s5, t4 - sltu a4, s0, sp - csrrw t5, 0x340, s9 - blt a6, a2, 833f - c.xor a0, a0 - srl a0, s3, t2 - sll a1, t4, s11 - nop - mulhsu s3, s3, s9 - and s4, a5, tp - .4byte 0x00100073 # ebreak - andi t6, t3, 475 -830: mulhu s1, a1, t2 - xori a5, sp, 121 - srai zero, t3, 27 -833: c.srai a3, 11 - c.nop - c.beqz a4, 841f - sll s2, s9, a7 - csrrs t0, 0x340, a6 - slt t6, a5, s9 - andi s1, t1, 897 - c.srai a3, 24 -841: csrrci s7, 0x340, 15 - c.ebreak;c.nop; - blt a6, s11, 848f - csrrci t4, 0x340, 2 - c.mv s0, s2 - csrrc ra, 0x340, t6 - rem a2, a7, s3 -848: add t0, sp, ra - blt zero, s1, 850f -850: blt t6, t1, 858f - slt s1, a6, t0 - c.xor a3, a4 - mul tp, t5, t5 - slti a2, t0, 300 - .4byte 0x00100073 # ebreak - c.or a4, s1 - slli t3, sp, 1 -858: beq t0, s0, 873f - csrrsi a2, 0x340, 24 - mulh zero, s8, sp - mulhsu a2, s10, a7 - andi a2, s8, -120 - csrrsi s6, 0x340, 19 - csrrci gp, 0x340, 30 - sltiu s4, s9, 649 - csrrsi t2, 0x340, 2 - mulhsu a0, a4, t0 - csrrwi s10, 0x340, 23 - blt s4, s9, 887f - c.lui a6, 23 - csrrci a3, 0x340, 5 - la s6, region_4+410 #start riscv_hazard_instr_stream_3 - sltiu t4, ra, 814 - lb t1, 2(s6) - lh a3, -6(s6) - and a0, t1, t4 - sb a0, -9(s6) - auipc t4, 150124 - lbu t1, 1(s6) - mul a3, tp, ra - sb a0, -11(s6) - mulh tp, t1, a0 - c.mv a3, tp - sb tp, 6(s6) - .4byte 0x00100073 # ebreak - lb t1, 9(s6) - lw t1, -14(s6) - lb t4, -8(s6) - mulhsu t4, t1, tp - slti ra, a3, -254 - c.srai a3, 8 - lbu a3, -10(s6) - lbu t1, 13(s6) - slli tp, t1, 18 - mulh a0, tp, tp - lbu tp, -11(s6) #end riscv_hazard_instr_stream_3 - c.nop -873: slti s5, t5, -673 - mulhsu s5, t1, t2 - rem s11, gp, zero - c.srai a2, 10 - c.addi s2, 8 - sltu a3, a7, s1 - divu a6, a1, a6 - srai s4, tp, 19 - c.srai a4, 18 - auipc t1, 10958 - c.slli s0, 25 - ori a1, s8, 253 - c.andi a1, 13 - c.srli a3, 1 -887: mulhu a1, s6, a1 - beq t6, a3, 901f - add s0, s4, s11 - slti zero, t2, -554 - csrrs s10, 0x340, a4 - c.bnez a2, 900f - beq t6, a1, 903f - csrrsi s11, 0x340, 29 - bltu sp, s3, 908f - auipc s0, 491417 - c.addi s4, -21 - c.srli a3, 31 - sra zero, t3, t3 -900: bne s11, zero, 911f -901: mul s2, s4, a6 - nop -903: add t1, s11, a1 - bgeu t1, t5, j_sub_2_sub_3_3 #branch to jump instr - slt t2, t3, s3 - c.srai a4, 27 - lui t5, 437879 - sll s0, t5, s11 - mulh s10, a5, a0 - mulhu s7, t6, zero - or a2, t0, s11 - lui a7, 125317 - c.mv s1, s2 - csrrwi t2, 0x340, 18 -j_sub_2_sub_3_3: jal gp, sub_3 - lui a2, 15334 - c.andi s1, -27 - sltu a6, s5, s0 - c.and a5, a3 -908: csrrsi a6, 0x340, 0 - csrrci ra, 0x340, 10 - c.xor s1, a4 -911: c.mv t6, t1 - c.slli t5, 7 - divu s1, t3, a0 - andi a2, s8, 93 - slti a3, t3, -579 - c.xor a0, s1 - mulhu t3, s7, t2 - nop - andi t3, t6, -50 - mulhsu s1, s2, s11 - or t3, s4, a7 - csrrw t1, 0x340, s0 - csrrs s3, 0x340, a0 - auipc s6, 243556 - csrrc zero, 0x340, a1 - auipc t6, 1034381 - andi t4, zero, 542 - nop - nop - mulhu a4, sp, t5 - c.srai a5, 15 - c.li a2, -23 - ori a0, a7, -972 - c.sub a3, a2 - c.ebreak;c.nop; - sll gp, a1, t5 - slt a5, s5, s5 - c.lui a5, 5 - bge t5, ra, 954f - c.nop - csrrw t4, 0x340, s2 - slti t1, gp, 253 - c.add t4, s9 - c.andi a3, -13 - and a3, t4, s7 - nop - remu t6, a6, tp - c.and s1, a4 - or s3, a2, a6 - sltiu s6, s4, 678 - srl a3, gp, s3 - beq s5, ra, 955f - xori s0, s6, 1010 -954: csrrci s6, 0x340, 29 -955: blt s11, t3, 960f - auipc zero, 31326 - .4byte 0x00100073 # ebreak - c.lui s2, 21 - and s6, s0, sp -960: mulhu s4, s7, a0 - sll t3, s7, s2 - c.lui s2, 29 - c.bnez a3, 971f - lui s2, 455953 - mulhsu a2, s10, t1 - slti t2, t2, -413 - slti t0, t5, -698 - csrrw s10, 0x340, s10 - csrrsi s0, 0x340, 3 - csrrsi s11, 0x340, 24 -971: div t4, s4, s11 - c.beqz a3, 975f - xor t6, t4, s10 - srl a7, t2, tp -975: c.mv t2, tp - c.addi t0, 1 - blt t6, s1, 981f - remu t4, s0, t4 - c.beqz s1, 988f - remu a4, s3, t4 -981: bge s9, a0, 993f - csrrci a3, 0x340, 1 - c.nop - xor s6, s3, s3 - c.beqz a5, 988f - mul a4, s11, a7 - remu s4, t5, s0 -988: sltu s7, t1, t1 - div tp, a7, tp - mul zero, a0, a5 - sltu t0, s0, s10 - xori t4, s4, 494 -993: csrrc tp, 0x340, sp - rem s1, gp, gp - c.slli t5, 27 - csrrsi t3, 0x340, 21 - or a7, zero, a0 - add s7, s10, a5 - mulhsu zero, a0, a2 - lui s6, 442848 - c.srai a2, 1 - mulhu s2, s8, s7 - xor s4, a2, t3 - sll a3, ra, s11 - blt s6, t5, 1023f - c.mv s2, a4 - nop - srl t5, s4, a6 - auipc s6, 658570 - c.mv a5, s1 - c.li a1, 12 - c.sub a4, a2 - csrrci tp, 0x340, 30 - div t3, a4, s0 - blt s6, t5, 1021f - csrrw t1, 0x340, s10 - xor tp, s8, s11 - ori gp, tp, 162 - c.addi s0, 11 - c.addi s10, -30 -1021: csrrw a6, 0x340, t0 - nop -1023: slt a3, a3, s7 - csrrc a6, 0x340, a0 - c.and a4, a4 - csrrw a1, 0x340, tp - csrrw s3, 0x340, t0 - sltiu a1, s9, -194 - bltu a7, a5, 1039f - or a6, t3, a6 - csrrsi t2, 0x340, 19 - sltu a4, s7, s5 - div t1, tp, a4 - mulhu a1, s4, t0 - c.addi gp, 16 - c.sub s0, a0 - c.slli ra, 5 - mul s3, a5, tp -1039: srli a1, tp, 9 - srai s10, t3, 5 - lui a6, 498037 - slli s2, s2, 7 - lui tp, 44685 - lui a4, 526875 - c.bnez a5, 1052f - nop - c.bnez a5, 1048f -1048: srai t6, t2, 20 - c.or a5, a4 - srl a7, a3, s8 - bgeu sp, s10, 1059f -1052: sra t4, s1, s8 - lui a2, 862581 - and t3, s6, s6 - c.sub a3, a1 - bge a0, a6, 1061f - slt ra, s8, s4 - xori zero, ra, -396 -1059: bgeu s4, gp, 1074f - c.lui a1, 16 -1061: c.xor a2, s1 - c.mv s10, s2 - csrrsi t0, 0x340, 4 - add s10, a7, s2 - bne s9, t3, 1075f - c.ebreak;c.nop; - sra a3, s8, a6 - sll t4, s3, s9 - sltu t1, a4, zero - sub s4, t6, tp - slli gp, sp, 17 - .4byte 0x00100073 # ebreak - c.and s1, a3 -1074: c.xor a3, s1 -1075: c.andi a4, -11 - sub t3, a3, s6 - c.slli s7, 8 - c.li gp, -3 - bgeu t4, s5, 1089f - c.srli a0, 21 - csrrci t6, 0x340, 14 - xor a6, sp, s8 - c.nop - c.ebreak;c.nop; - c.srli a1, 13 - srl t0, a5, s7 - srai a0, s4, 2 - c.addi tp, -15 -1089: sltiu a7, s5, 576 - c.li s7, 23 - bge t6, s4, 1103f - slli ra, a5, 25 - c.nop - c.sub a2, s0 - mul a3, s5, s4 - c.nop - auipc a0, 548174 - c.bnez a1, 1116f - nop - srai t6, zero, 20 - c.li ra, 20 - add s4, gp, sp -1103: divu s0, s11, s7 - csrrs s0, 0x340, s5 - sltu s4, gp, a2 - c.slli s2, 8 - slti s7, s6, -821 - slt a1, t6, s5 - c.srai a2, 21 - c.sub s0, s0 - sltu ra, a6, t4 - bltu tp, s6, 1113f -1113: sra a5, a3, s7 - sra s2, t6, zero - mulhsu a1, a3, sp -1116: mul s5, a2, t2 - slt a2, t5, s7 - c.lui t0, 22 - srli a7, t3, 15 - c.beqz a1, 1127f - xori a0, t3, 700 - csrrwi ra, 0x340, 16 - div t4, s5, ra - csrrc a0, 0x340, ra - srl ra, a3, t1 - blt s0, zero, 1128f -1127: divu s11, sp, s5 -1128: c.ebreak;c.nop; - srai a2, a0, 23 - c.andi s0, 6 - c.nop - csrrsi s7, 0x340, 30 - add t3, s0, s5 - lui s2, 288309 - and s5, s11, t6 - c.sub a5, s0 - c.li s5, 30 - addi a4, s7, -667 - csrrs s1, 0x340, zero - lui s0, 807741 - c.sub a0, s0 - sub zero, tp, s9 - bgeu s3, a4, 1151f - slt s3, t5, t6 - csrrs s5, 0x340, s4 - csrrwi zero, 0x340, 30 - csrrw a5, 0x340, a4 - csrrs t4, 0x340, s8 - xori s11, tp, -204 - c.bnez a4, 1168f -1151: slt t2, a6, a5 - bgeu a5, t6, 1165f - bne a0, gp, 1158f - sra s5, a7, tp - c.srai s1, 13 - csrrw t4, 0x340, s5 - lui s0, 869827 -1158: c.srai s0, 1 - nop - auipc a6, 59221 - csrrwi s5, 0x340, 29 - rem ra, gp, s3 - divu ra, a6, s6 - srl t3, a4, a6 -1165: xori s6, s0, 207 - csrrc s1, 0x340, t5 - lui s3, 637642 -1168: or t6, s6, a3 - divu s1, s4, s10 - c.ebreak;c.nop; - c.srai a1, 28 - csrrs s4, 0x340, gp - c.or a0, s1 - csrrw s4, 0x340, zero - bgeu ra, t4, 1179f - xor gp, s11, t4 - slti s7, t0, 919 - div t6, sp, s3 -1179: add s11, t3, s11 - div s5, s2, t5 - and t5, zero, s7 - c.lui a4, 23 - srai s11, s1, 1 - beq t5, s3, 1199f - ori s1, s9, 84 - slt s5, a3, s0 - .4byte 0x00100073 # ebreak - xori s3, a2, -549 - c.li t4, -12 - c.slli s7, 23 - c.li tp, -11 - c.srli a0, 13 - add gp, a3, s2 - c.bnez a4, 1205f - csrrs ra, 0x340, t3 - .4byte 0x00100073 # ebreak - ori a6, gp, -433 - srli a2, t6, 0 -1199: c.sub a3, a4 - srai s5, t3, 29 - bgeu t4, a4, 1207f - sltu s11, t6, s7 - c.add t4, t6 - c.mv a1, t1 -1205: c.srli a0, 18 - rem ra, s9, s6 -1207: srai a3, a0, 4 - c.xor a3, a3 - bge ra, zero, 1212f - xor s3, s10, ra - beq s9, ra, 1222f -1212: c.mv t3, t6 - csrrwi s1, 0x340, 24 - sra s5, s8, s11 - bgeu a3, a2, 1222f - c.or a1, s1 - c.mv s0, t1 - lui a0, 417957 - remu s5, zero, zero - mulh t3, a4, tp - sll a4, ra, t4 -1222: add a6, s10, t2 - lw gp, 4(sp) - addi sp, sp, 64 - c.srai a0, 24 - .4byte 0x00100073 # ebreak - .4byte 0x00100073 # ebreak - c.li a0, 20 - mulhsu a0, s2, s6 - rem s7, s3, a7 - c.sub s1, a4 -1960: c.jr x3 -sub_4: blt a5, ra, sub_4_stack_p - sra s4, a1, s9 - c.mv t2, gp - c.slli t4, 2 - c.addi t6, 27 -sub_4_stack_p: addi sp, sp, -36 - slli t6, t0, 8 - c.srai a4, 8 - sw gp, 4(sp) - c.addi s2, 16 - slli s2, s8, 23 - .4byte 0x00100073 # ebreak - la t1, region_1+11208 #start load_store_instr_stream_2 - sb tp, -3(t1) - la a2, region_4+2726 #start load_store_instr_stream_1 - la ra, region_0+880 #start load_store_instr_stream_3 - lh a7, -14(t1) - lbu gp, -1(t1) - lh t2, 6(ra) - lh gp, -12(ra) - sb s7, 3(ra) - la tp, region_2+2416 #start load_store_instr_stream_0 - lbu s10, -167(a2) - lh t0, 10(ra) - lhu a5, -2(ra) - sb s9, -50(tp) - sb gp, 90(a2) - lb a6, 10(t1) - lhu a0, 8(t1) - lb s10, -53(tp) - lb t4, -16(ra) - lb s5, -48(a2) - lb a0, -153(a2) - sb a1, 9(ra) - lbu zero, -15(tp) - lhu s0, -52(tp) - sw a7, 8(ra) - lhu s10, 178(a2) - lb s3, -7(t1) - sb a6, -8(a2) - sb a5, 33(tp) - lhu t4, 8(a2) - lbu t4, 172(a2) - lb a4, -9(t1) - sb t1, 17(a2) #end load_store_instr_stream_1 - sh s8, -12(t1) #end load_store_instr_stream_2 - lbu s2, 9(ra) #end load_store_instr_stream_3 - lbu t3, 59(tp) #end load_store_instr_stream_0 - la a0, region_3+196 #start load_store_instr_stream_1 - lbu t4, -61(a0) - la s6, region_3+220 #start load_store_instr_stream_0 - lb t5, -41(a0) - lbu s3, 11(s6) - lbu s5, -31(a0) - lhu a5, -22(a0) - lbu a6, -46(a0) - sb s10, 37(s6) - lh t2, -6(s6) - lh a6, -34(a0) - sb a0, -62(s6) - lbu t3, -3(s6) - lbu gp, 14(a0) - lb t2, 14(s6) - lbu s7, 39(a0) - sh a4, 54(s6) - lbu s3, 31(a0) - sb a3, -5(a0) #end load_store_instr_stream_1 - lb a4, 13(s6) #end load_store_instr_stream_0 - la s2, region_3+201 #start riscv_hazard_instr_stream_1 - lbu a6, 34(s2) - xor t6, s1, t6 - lb s0, -28(s2) - csrrwi t6, 0x340, 18 - divu t6, s7, s1 - lhu s1, -89(s2) - andi s0, s7, 949 - lb t3, 202(s2) - c.add t3, t3 - xori s0, t6, 409 - lb s7, -154(s2) - sh t6, 25(s2) - sb a6, -50(s2) - ori t3, s1, -580 - mul s7, a6, s1 - div t3, s0, s1 - sb s0, -135(s2) - mulh a6, s0, a6 - srl s1, s1, s1 - lh a6, 3(s2) - lb s1, 60(s2) - lbu s0, 254(s2) - addi s1, s0, 376 - slti a6, t3, -527 - lb t6, 23(s2) - sb s7, -37(s2) - lb t3, 58(s2) - sw s0, -73(s2) - slt s1, s7, t3 - lb t3, 87(s2) - lhu s0, -65(s2) - xori s1, s7, -666 - sb t6, -96(s2) - lhu t6, 43(s2) - lhu a6, -139(s2) #end riscv_hazard_instr_stream_1 -sub_4_4: jal gp, 15f -0: c.j 11f -1: c.j 8f -2: c.jal 17f -3: jal t1, 1b -4: jal ra, 6f -5: c.jal 13f -6: c.jal 0b -7: c.j 10f -8: c.jal 4b -9: c.j 12f -10: c.j 5b -11: jal a7, 2b -12: jal ra, 7b -13: c.jal 14f -14: c.j 16f -15: jal ra, 9b -16: jal t1, 3b -17: sra t3, s3, t5 - la t1, region_0+1185 #start riscv_load_store_rand_instr_stream_0 - sw t1, 47(t1) - srl s1, t1, s1 - sh t2, 11(t1) - sb s4, -6(t1) - srli s0, s9, 12 - rem t2, s9, a4 - sb s6, -3(t1) - lbu t4, -24(t1) - c.ebreak;c.nop; - remu a7, t0, a1 - andi s4, t5, 980 - sb a3, 60(t1) - c.andi a1, 11 - c.add tp, a4 - xori s5, s9, -183 - c.sub s1, a3 - c.xor s0, a4 - lb s4, 30(t1) - mul s3, t6, t4 - lb s3, 12(t1) - c.srai a3, 19 - csrrsi s4, 0x340, 3 - sb t4, 47(t1) - lhu t6, -41(t1) - mulhsu s1, a2, t1 - rem t4, t6, s11 - c.mv s6, s6 - lbu s5, 44(t1) - c.srli a5, 2 - c.slli s10, 17 - c.or a0, a1 - mulhsu s6, t4, s7 - lbu s10, 24(t1) - divu s3, s9, s2 - mulhsu s4, a3, s2 - lb tp, -42(t1) - csrrw a2, 0x340, t6 - lb t2, 33(t1) - c.srai s0, 11 - and t0, sp, s7 - xori s5, t0, -674 - ori a7, s4, 927 - lbu s3, 24(t1) #end riscv_load_store_rand_instr_stream_0 - la t1, region_2+5172 #start load_store_instr_stream_2 - la a5, region_2+4643 #start load_store_instr_stream_0 - sb a7, 897(t1) - la a4, region_2+3101 #start load_store_instr_stream_1 - lb t6, 34(t1) - sh a0, -53(a5) - lw a2, -844(t1) - sh s11, 1(a4) - lbu ra, -2(a4) - sh a6, -7(a4) - lbu gp, -682(t1) - sb s11, 1022(a5) - sh a4, -224(t1) - sw gp, 11(a4) - lw s2, -684(t1) - lb s2, -534(a5) - lbu zero, 6(a4) - lbu s4, 530(a5) - lbu s1, -14(a4) - sb s8, -737(a5) - lb ra, -2(a4) - lb a7, -873(t1) #end load_store_instr_stream_2 - sb a4, 9(a4) #end load_store_instr_stream_1 - lbu zero, 662(a5) #end load_store_instr_stream_0 -sub_4_3: jal gp, 21f -0: c.jal 18f -1: jal ra, 24f -2: c.jal 17f -3: jal t1, 5f -4: c.j 22f -5: c.jal 13f -6: jal t1, 1b -7: c.jal 15f -8: jal ra, 9f -9: c.jal 20f -10: c.jal 14f -11: c.j 6b -12: jal ra, 7b -13: jal ra, 12b -14: jal ra, 8b -15: jal t5, 25f -16: c.j 23f -17: c.j 26f -18: c.jal 4b -19: c.jal 10b -20: c.j 27f -21: jal gp, 2b -22: c.jal 16b -23: c.j 3b -24: c.j 19b -25: jal ra, 11b -26: jal ra, 0b -27: div s6, s11, t3 - la t3, region_2+2652 #start riscv_hazard_instr_stream_2 - or a6, a1, s0 - add a4, a4, a1 - lb a4, -33(t3) - c.mv s0, s0 - c.and a0, s0 - lb t4, -39(t3) - sltu t4, a1, t4 - lui a1, 804247 - srli a6, a4, 5 - xor a4, a4, a4 - rem t4, a1, t4 - lh s0, 48(t3) - sltiu s0, a1, 482 - div a1, a6, a1 - ori a4, s0, 504 - lb s0, -21(t3) - sra a4, a0, t4 - lbu s0, -8(t3) - lhu a0, -52(t3) - lbu a1, 54(t3) - sb a1, 22(t3) - sb a6, -37(t3) - div s0, a4, t4 - sb a1, -47(t3) - lhu t4, 42(t3) - sw a6, 20(t3) - lh a1, 18(t3) - sb s0, -51(t3) - sw a1, 60(t3) - c.xor a1, a4 - lb t4, 43(t3) - lhu s0, -18(t3) - c.nop - or a4, a1, a0 - addi a0, t4, 932 - add a0, a0, a6 - lui a4, 1034402 - lbu t4, 32(t3) - sb t4, -21(t3) - sb a0, -60(t3) - sw a6, 48(t3) - lb s0, 43(t3) - andi s0, t4, -1006 - c.srai a0, 16 - csrrc s0, 0x340, a0 - sltu s0, s0, a4 - csrrwi a1, 0x340, 8 - sb t4, 45(t3) - sb a1, 47(t3) #end riscv_hazard_instr_stream_2 -sub_4_5: jal gp, 21f -0: jal ra, 12f -1: c.jal 18f -2: c.j 9f -3: jal ra, 15f -4: c.jal 7f -5: jal gp, 4b -6: c.j 2b -7: c.j 0b -8: jal ra, 20f -9: c.jal 1b -10: c.jal 14f -11: jal ra, 5b -12: jal ra, 22f -13: c.j 8b -14: c.j 6b -15: c.j 10b -16: jal ra, 3b -17: jal ra, 19f -18: c.j 11b -19: c.jal 16b -20: jal t1, 17b -21: jal ra, 13b -22: srli t4, zero, 19 - la a0, region_4+1705 #start load_store_instr_stream_1 - la s11, region_0+2345 #start load_store_instr_stream_2 - la s10, region_1+6317 #start load_store_instr_stream_0 - sb s2, -6(a0) - sb a6, 137(s10) - lhu tp, -7(a0) - lb t0, -14(a0) - lbu tp, 127(s11) - lb t4, 12(a0) - sb a2, 16(s10) - lbu s7, -9(a0) - lb s6, -191(s10) - lw s0, -733(s11) - lb a1, 548(s11) - sb s10, 10(a0) - sh s4, -365(s11) - sb a1, -298(s11) - lb a5, 10(a0) - lhu s2, 239(s10) - lbu a5, -4(a0) #end load_store_instr_stream_1 - lh a5, 507(s11) #end load_store_instr_stream_2 - lb s3, 58(s10) #end load_store_instr_stream_0 - la a1, region_2+58 #start riscv_hazard_instr_stream_0 - .4byte 0x00100073 # ebreak - sh t3, 158(a1) - c.sub s0, s0 - lbu s0, -25(a1) - c.andi s0, -8 - lh ra, 176(a1) - c.nop - lbu a2, 58(a1) - lh a2, 234(a1) - mulh s0, zero, ra - c.or s0, s0 - c.mv ra, a2 - sb a6, 127(a1) - sh a6, 236(a1) - xor a6, zero, ra - sb s0, 248(a1) - mulhsu a2, a6, s0 - lbu ra, -41(a1) - div a2, s0, t3 - and t3, a2, zero - lw a2, 34(a1) - rem s0, zero, s0 - lbu t3, 223(a1) - sb s0, 83(a1) - lbu a2, 15(a1) - lh ra, 140(a1) - lbu t3, 206(a1) - sb t3, 135(a1) - csrrc zero, 0x340, t3 - sub s0, a2, t3 - srli t3, a2, 18 - mulh t3, a2, a6 - div a6, a6, s0 - c.mv s0, t3 - lb s0, 65(a1) - csrrwi t3, 0x340, 4 - srli a2, ra, 26 - lb a6, -39(a1) #end riscv_hazard_instr_stream_0 - la s3, region_4+2995 #start load_store_instr_stream_4 - la a5, region_4+1263 #start load_store_instr_stream_0 - la s10, region_4+2405 #start load_store_instr_stream_1 - lh a7, 803(s3) - lh s2, -747(s3) - la s6, region_4+1141 #start load_store_instr_stream_2 - la t0, region_4+304 #start load_store_instr_stream_3 - sb s4, -121(t0) - lb s5, -1(a5) - lh ra, -31(s10) - lb s11, 8(s6) - lw a3, -49(s10) - sb a1, -8(a5) - sb s11, 37(t0) - lb s4, 6(s6) - lbu gp, 10(s6) - lb a7, -24(s10) - lbu a7, 2(a5) - sb s4, -848(s3) - lb tp, -96(t0) - lhu a1, 3(a5) - lbu gp, 7(a5) - sb tp, -24(s10) - sb a6, 580(s3) - lbu s2, 255(t0) - sh s6, -5(a5) - sb s0, -51(s10) - lb ra, -15(s6) - lbu s4, 205(t0) #end load_store_instr_stream_3 - sb tp, 9(s6) - lb s5, -41(s10) - lbu ra, 6(s6) - sb t2, 37(s10) - lb t2, -36(s10) - sb a3, 0(s6) - lb a0, 4(a5) - sh zero, 9(s6) - sb s0, -21(s10) - lhu a0, 971(s3) #end load_store_instr_stream_4 - lbu a0, 5(s6) - lhu s4, 3(a5) - lhu ra, 1(s6) #end load_store_instr_stream_2 - lhu s2, 35(s10) #end load_store_instr_stream_1 - lhu a3, 5(a5) #end load_store_instr_stream_0 - la s5, region_4+1660 #start riscv_load_store_rand_instr_stream_2 - mulhsu t6, zero, s4 - divu zero, s10, ra - c.srai a2, 22 - sra s0, s2, t1 - mulhsu s2, s7, s10 - lb a2, -138(s5) - .4byte 0x00100073 # ebreak - mulhu t6, s0, s4 - sw s4, -72(s5) - c.ebreak;c.nop; - mulhsu t0, a7, s0 - c.addi s10, -7 - c.nop - sub t2, a4, a6 - add t2, t5, tp - sb s5, 89(s5) - lbu t6, -3(s5) - sll t6, s4, s10 - c.xor a5, s1 - mulhsu s1, s5, s5 - c.xor a1, a2 - lb t0, -240(s5) - c.or a4, a0 - lb s0, -150(s5) - c.or s0, a4 - c.mv t4, s6 - sb s0, -225(s5) - sb t4, 202(s5) - lui t3, 861101 - auipc ra, 547871 - remu t1, s2, s11 - srl a1, s10, s6 - mulhu t4, s9, t0 - c.and a2, a3 - c.add a2, a3 - sra t2, s10, s10 - sb s11, 131(s5) - srl t5, a1, a0 - lhu t1, 214(s5) #end riscv_load_store_rand_instr_stream_2 - bge t4, t3, 15f - lui s10, 404034 - sra t0, s7, t5 - c.sub a1, a2 - xori s5, t2, -801 - c.andi s0, -25 - sltu s5, t3, a5 - sra s11, s6, s2 - or s7, s6, t2 - c.srli a4, 12 - rem gp, a6, s10 - remu a4, a2, tp - bne s0, s0, 32f - bgeu sp, a5, 31f - c.li a4, 7 -15: c.or a0, a2 - mulhsu a4, zero, tp - mul a6, a6, s8 - slt t2, a7, a0 - c.srli a2, 27 - csrrsi a4, 0x340, 10 - csrrwi t1, 0x340, 26 - csrrwi t3, 0x340, 13 - c.addi s5, -20 - slti s6, a0, 847 - addi a1, t2, 347 - sltu t3, s10, t4 - add s3, t2, t5 - c.addi tp, 26 - mulhu a6, s10, t2 - c.slli a5, 13 -31: bltu t1, s10, 51f -32: csrrc gp, 0x340, s2 - .4byte 0x00100073 # ebreak - mul t0, a2, t4 - csrrs t6, 0x340, t2 - sltiu tp, s10, -456 - or s11, a4, zero - srl s1, a2, tp - andi s4, t2, 812 - bge s6, zero, 60f - bne t3, t2, 57f - csrrw a7, 0x340, a4 - c.addi gp, -16 - mul s1, s5, tp - slli t6, sp, 23 - bltu t3, t2, 61f - c.or a0, a1 - xori t3, s7, -636 - c.nop - or s7, a2, s5 -51: slt t1, s2, s5 - c.srai a0, 14 - csrrw t3, 0x340, tp - add s7, t4, sp - xori s5, a2, -440 - mulhsu t4, a1, s1 -57: c.addi s2, -28 - lui s1, 11189 - c.nop -60: addi t5, a2, 559 -61: srl a5, s9, a7 - add t6, s6, s8 - c.add t1, s5 - c.xor a4, a4 - xor s0, s10, s1 - xori a1, a2, -28 - slt s3, t6, a1 - ori t2, a7, 602 - c.mv t4, s9 - sltu a6, s7, a0 - divu a4, s10, s2 - csrrci s0, 0x340, 7 - remu t4, s1, a7 - ori t3, t3, -878 - ori s5, s5, 883 - remu a6, a4, a0 - slli a7, a6, 21 - xor s7, sp, a7 - add s3, tp, s5 - c.nop - bge a6, gp, 100f - andi t0, a5, -376 - and a4, gp, ra - bgeu s9, a1, 95f - c.li s3, -32 - c.lui s5, 10 - c.srli s0, 2 - bne zero, t1, 105f - divu a2, a2, s0 - bgeu s8, t4, 103f - srli t6, t0, 30 - c.slli tp, 25 - slt a1, a2, t0 - rem s2, a5, t4 -95: bge s11, s6, 113f - csrrsi a3, 0x340, 21 - c.bnez a5, 117f - c.beqz s1, 112f - lui zero, 24942 -100: ori t2, ra, 367 - addi s7, a6, 76 - blt s2, s9, 110f -103: c.add s11, t1 - csrrsi t4, 0x340, 12 -105: beq s9, a4, 117f - csrrc t2, 0x340, a0 - nop - c.srli a3, 7 - srl t4, s6, t1 -110: csrrw s1, 0x340, s1 - csrrwi s0, 0x340, 30 -112: srl a4, t2, t0 -113: c.lui s1, 17 - xori t1, t4, -42 - c.andi a1, 13 - c.andi a1, -11 -117: bltu s0, t1, 135f - sll s5, a1, t6 - nop - csrrw zero, 0x340, t3 - mulhu s2, t0, s6 - addi a3, s3, 92 - bgeu s11, s5, 128f - addi s2, a3, -484 - c.xor a3, s1 - sra a3, a0, a1 - c.andi s0, -10 -128: c.bnez a2, 132f - c.or a5, a0 - xori a2, a2, -34 - csrrs s3, 0x340, t0 -132: c.andi a0, -30 - c.nop - sll s10, t2, s0 -135: mulhu s0, t1, s2 - blt sp, t4, 155f - beq a1, a6, 150f - sra s5, t3, s6 - .4byte 0x00100073 # ebreak - mulhu a6, a6, t0 - slti zero, s4, 402 - or a0, s8, s5 - csrrci t4, 0x340, 10 - divu a5, s9, a3 - c.beqz a2, 161f - csrrc s11, 0x340, s1 - csrrsi a2, 0x340, 27 - blt s4, s10, 161f - c.slli a6, 8 -150: csrrwi s2, 0x340, 5 - nop - remu a6, s4, s3 - add t1, s0, s4 - c.li a1, -12 -155: bne s10, t5, 166f - andi s5, a1, -852 - c.sub a3, a5 - c.li s6, -5 - mulhsu s3, t6, gp - c.srai a1, 10 -161: c.mv a0, gp - csrrwi t4, 0x340, 7 - .4byte 0x00100073 # ebreak - c.ebreak;c.nop; - c.srai a3, 28 -166: divu ra, t2, s2 - mulh s1, s8, a4 - csrrwi a3, 0x340, 3 - c.srli s1, 18 - srl s2, a5, a0 - mulhu s11, t5, s7 - c.li t2, 5 - slti a5, a5, 625 - srai s11, sp, 1 - or s0, sp, s10 - c.beqz a5, 193f - sub zero, a7, s10 - div s5, s8, a4 - c.sub s1, a5 - sltiu t3, ra, -912 - c.srli s1, 31 - div zero, t2, t4 - csrrci s11, 0x340, 25 - or s11, t0, gp - mul s6, a4, s11 - srl a0, zero, a4 - mul s2, a5, a5 - c.and a3, a2 - .4byte 0x00100073 # ebreak - divu a3, s11, s7 - sub a3, a1, t0 - mulhsu gp, t3, s11 -193: c.slli a1, 16 - sltu t5, s5, t5 - mulhsu s10, t0, a7 - c.add ra, a6 - xori s1, gp, 334 - csrrci s2, 0x340, 28 - c.bnez s1, 218f - c.li s5, -27 - mulh a1, ra, s10 - andi gp, a0, -282 - c.xor a5, a0 - srl t5, s10, zero - c.andi a0, 7 - srli t6, t4, 13 - slti s2, sp, -549 - blt s4, s5, 224f - ori s1, s10, 615 - csrrs a7, 0x340, t6 - rem t5, sp, t3 - bne a3, s11, 214f - andi tp, s10, -410 -214: divu a6, s1, a5 - nop - c.or a3, a3 - rem a0, s8, a7 -218: c.add s2, t6 - mulhu s4, s5, t2 - sltu s1, s5, s2 - ori tp, gp, 0 - andi s5, a7, 315 - addi ra, t6, 61 -224: and t1, a4, t6 - csrrc s2, 0x340, t3 - or tp, s2, ra - c.add s10, a7 - mulhsu a1, s9, t4 - sra t5, s4, a7 - c.slli a0, 24 - xor s3, a5, s0 - ori a4, a1, 235 - mulh t0, s1, a1 - c.li a7, 8 - mulhu s5, t0, a1 - xori a0, sp, -950 - csrrw a4, 0x340, a6 - auipc a3, 825923 - slti t0, sp, -855 - c.li s2, 22 - andi s0, a3, -756 - or s3, a7, a4 - addi t4, a5, -738 - bltu s11, a6, 259f - sll s0, a3, s3 - sltu s0, a6, a7 - srl t0, s7, t0 - mulhu a0, t4, s9 - c.add tp, s9 - c.mv t5, t0 - csrrwi s3, 0x340, 9 - xor t4, a6, s3 - or a5, s0, tp - bgeu t2, a6, 260f - andi a0, s6, 503 - add s7, tp, a3 - c.srli a0, 25 - csrrw s7, 0x340, a1 -259: nop -260: nop - c.or a2, a5 - nop - add a1, ra, a6 - c.and a3, a4 - sra ra, t5, s10 - c.beqz s0, 286f - mulhsu t1, t4, ra - c.bnez s0, 282f - c.ebreak;c.nop; - sra s0, a2, ra - c.add a7, a0 - blt s7, zero, 287f - or a4, zero, s3 - add s7, a3, a7 - c.beqz a1, 280f - ori a2, a5, 241 - c.srai s1, 15 - mulhsu t2, a1, s5 - or t5, s11, s7 -280: .4byte 0x00100073 # ebreak - remu t1, zero, a7 -282: divu t4, a6, a6 - c.slli a7, 30 - srl s1, s1, s7 - c.sub s1, a1 -286: nop -287: c.slli s4, 8 - andi a5, a4, -662 - lui s1, 343712 - c.and a0, a0 - c.or s1, a0 - rem s5, t1, t4 - c.srli a3, 18 - c.slli tp, 29 - c.srai a3, 14 - csrrci s5, 0x340, 27 - sub t0, s4, a2 - mul a1, t5, t3 - c.srai a2, 6 - csrrwi gp, 0x340, 20 - div a0, a6, t2 - c.li ra, 25 - c.srli s0, 27 - srl a3, sp, a1 - c.xor s0, a3 - bne a7, tp, 319f - c.bnez a1, 323f - rem s0, s2, s10 - nop - csrrci s4, 0x340, 19 - blt a1, t2, 331f - sub s11, t6, t3 - or s2, s0, s7 - csrrw a4, 0x340, t4 - add a3, a4, sp - c.ebreak;c.nop; - mulhu t2, t1, s11 - and a4, a2, gp -319: slti t6, s3, 796 - div a3, s11, s4 - bgeu gp, s10, 339f - addi t5, a4, 765 -323: div s0, s7, a0 - c.or a4, a2 - c.slli s5, 20 - .4byte 0x00100073 # ebreak - c.ebreak;c.nop; - c.li a1, -7 - csrrci a2, 0x340, 14 - auipc gp, 444824 -331: bgeu sp, a4, 339f - c.xor a5, a2 - c.bnez a0, 344f - c.nop - div gp, s6, t5 - slt a0, s5, tp - mulhu a6, a3, zero - mulhsu a1, s0, s1 -339: c.xor a3, a1 - rem t1, t6, s6 - mulhu t5, t4, sp - csrrci t6, 0x340, 2 - bge a2, s1, 360f -344: sub a1, s1, s5 - auipc a3, 623228 - c.mv t4, s6 - div t4, a7, s8 - c.add a0, s1 - c.srli s1, 22 - beq tp, s9, 366f - csrrci ra, 0x340, 4 - srli s3, t2, 30 - c.srli s0, 23 - c.sub s0, a0 - csrrs a0, 0x340, t1 - csrrc ra, 0x340, t2 - mulhu a0, s11, sp - div a4, s10, tp - lui a0, 208933 -360: mulhu a3, t4, a1 - srl s11, s7, sp - sltiu s0, s0, 866 - c.ebreak;c.nop; - csrrc s10, 0x340, a4 - add t1, s4, a4 -366: auipc tp, 940702 - sltu a6, s4, s9 - divu t4, gp, s4 - sra a2, t4, a6 - srl a2, s11, a1 - auipc s3, 873548 - mul a1, a0, sp - c.mv a5, s5 - srli a7, s3, 10 - csrrw s2, 0x340, t0 - mulh t6, a5, tp - mul t3, s2, tp - nop - c.bnez a0, 399f - c.li s11, 25 - c.nop - mul a0, s3, a7 - csrrw t0, 0x340, a4 - bne t0, a5, 399f - .4byte 0x00100073 # ebreak - csrrwi zero, 0x340, 23 - srai s10, s8, 10 - mulh zero, s6, s3 - csrrs a3, 0x340, s4 - sltiu t6, a6, -263 - slli t6, s0, 12 - srli s10, a3, 19 - slti a0, s11, -223 - slt s7, a2, a3 - c.addi t3, -4 - c.add a0, t4 - rem s2, s11, s9 - remu a6, tp, s3 -399: c.srli s0, 1 - c.and a4, s1 - remu t6, a2, s1 - addi a5, zero, 10 #init loop 0 counter - c.srai a2, 28 - .4byte 0x00100073 # ebreak - auipc a6, 733674 - srai t6, zero, 15 - c.andi a2, 30 - ori a0, t5, -861 - or s10, s8, a4 - sltiu a2, t1, 298 - c.add t2, s2 - sra t6, a5, a7 - addi zero, zero, 0 #init loop 0 limit - c.andi s1, -22 - mul a7, s1, gp -sub_4_12_0_t: xori t5, t2, -987 - addi a5, a5, -1 #update loop 0 counter - csrrc s10, 0x340, t0 - c.or s0, s1 - rem s5, a6, t0 - c.andi s1, 2 - c.mv s0, s5 - c.beqz a5, sub_4_12_0_t #branch for loop 0 - c.xor s0, a4 - or t0, s10, tp - bne s4, s8, 416f - c.ebreak;c.nop; - xori a1, a0, 756 - beq s0, s3, 424f - csrrsi s4, 0x340, 10 - c.xor a2, a5 - rem s7, t5, s1 - rem s5, s8, s6 - and a3, a0, s1 - srli s4, s3, 20 - rem s2, a6, a4 - add a1, s7, t4 - bltu s3, s1, 417f -416: divu t6, s6, t1 -417: .4byte 0x00100073 # ebreak - srli t1, s6, 20 - lui t0, 907459 - c.or a4, a4 - div a5, t5, a5 - addi t5, t1, 903 - c.li a0, 7 -424: csrrc a1, 0x340, s1 - beq zero, s6, 431f - divu gp, s6, s11 - bgeu s11, a1, 446f - rem tp, t4, s11 - ori t4, a0, -87 - bne t0, a6, 445f -431: c.lui t5, 8 - mul s10, a6, tp - slli s5, s3, 5 - blt zero, s6, 446f - srli a3, s0, 18 - srli ra, s5, 27 - sra s2, t5, s6 - sra t3, s11, gp - srli zero, s11, 2 - csrrsi s11, 0x340, 15 - c.bnez a2, 461f - blt a5, s11, 460f - add s6, s7, s4 - xori gp, s6, 59 -445: addi t1, ra, 12 -446: auipc s6, 739814 - .4byte 0x00100073 # ebreak - div a7, a2, t5 - beq s9, s9, 453f - div t0, s0, s6 - xori a6, s2, -424 - xor a0, zero, t4 -453: mulhsu t1, s2, a1 - or t2, zero, ra - mulh s3, t2, s6 - xori t1, s10, -364 - sra zero, s6, s5 - c.nop - sltiu s6, s4, 199 -460: c.sub a4, a5 -461: c.sub a3, a2 - divu t5, s8, a2 - c.or a3, a1 - rem t6, t0, zero - mulh s11, s6, a6 - c.or a3, s1 - xori a5, ra, 521 - csrrci tp, 0x340, 23 - c.andi s1, -8 - csrrs a2, 0x340, t2 - .4byte 0x00100073 # ebreak - or s5, a0, a6 - sltu a1, t1, s9 - sra t1, s5, s7 - lui a3, 390550 - bge t5, s6, 492f - c.slli t6, 10 - csrrwi zero, 0x340, 19 - slli s3, t3, 0 - c.slli a0, 6 - srli s0, t6, 8 - c.slli t0, 18 - mulhu s7, s11, s3 - and a3, t5, s5 - mulhu t2, a3, t5 - beq s2, gp, 499f - slti a7, s8, 862 - c.bnez a0, 507f - mulhu a0, t6, a4 - c.andi s0, 29 - c.xor a2, s1 -492: xor a4, s0, s1 - sltu a5, sp, sp - ori s6, s4, -49 - csrrci a2, 0x340, 4 - rem s10, s10, a2 - mul s1, a3, t0 - c.andi a3, -17 -499: .4byte 0x00100073 # ebreak - remu s7, s10, s6 - auipc zero, 722577 - rem ra, s1, t3 - c.beqz s1, 522f - add t3, s4, a1 - .4byte 0x00100073 # ebreak - c.srli a0, 24 -507: nop - c.bnez s1, 519f - bge t2, s2, 526f - c.ebreak;c.nop; - c.lui t5, 20 - c.addi s2, -2 - remu a3, tp, s10 - divu s7, tp, t1 - mulh gp, t0, a0 - andi s0, s9, 232 - nop - div a0, s7, s8 -519: slli zero, a6, 15 - sra zero, s8, s0 - nop -522: csrrc a6, 0x340, s1 - srai s3, s6, 10 - c.sub a2, s0 - xori s7, s11, -440 -526: c.beqz a1, 541f - sra a6, a5, a1 - remu s4, zero, t0 - c.add a7, t2 - c.or a2, a5 - xor s7, s6, t3 - c.ebreak;c.nop; - bne tp, a6, 547f - beq s6, s0, 552f - srl t5, a0, a0 - rem a6, a7, a4 - remu s0, s4, s1 - mul s2, t1, t4 - c.add ra, tp - c.sub a5, a1 -541: xori s0, s4, -88 - rem s11, a4, t1 - c.and s0, a3 - c.xor s0, s0 - c.sub a2, a1 - bgeu s4, s9, 559f -547: nop - add a0, s5, a5 - srli s3, ra, 17 - csrrsi a0, 0x340, 11 - c.ebreak;c.nop; -552: c.or a4, a1 - csrrc s2, 0x340, ra - c.and a0, s1 - bge a2, a1, 561f - bne t2, t4, 574f - csrrc t5, 0x340, a2 - xori ra, a5, -203 -559: c.ebreak;c.nop; - csrrs s3, 0x340, s1 -561: c.or a0, a0 - c.beqz a1, 578f - blt a7, zero, 565f - lui t6, 298128 -565: c.sub a2, a5 - csrrsi t6, 0x340, 2 - csrrw s2, 0x340, ra - and s2, s11, sp - csrrwi a6, 0x340, 22 - addi s2, t3, -752 - bge a1, s11, 575f - sltu s4, s9, a4 - addi ra, tp, -771 -574: csrrci a4, 0x340, 30 -575: sub t0, t5, a4 - sll s0, a5, s8 - divu s3, s8, s8 -578: mulhu s11, a6, s9 - and tp, a6, t2 - c.bnez a3, 599f - slti s1, a3, 568 - c.and a0, a3 - srl zero, a1, s11 - slti s3, t4, -462 - slti t4, s7, -453 - c.lui s4, 3 - c.srli a0, 30 - csrrc t4, 0x340, t1 - c.nop - xor t6, sp, s11 - .4byte 0x00100073 # ebreak - bgeu sp, s2, 607f - c.bnez a3, 604f - ori s10, t3, -201 - sltiu a0, a3, -764 - c.sub a2, a0 - c.bnez s0, 615f - csrrs t1, 0x340, s4 - la a4, region_3+451 #start load_store_instr_stream_2 - la t6, region_4+1416 #start load_store_instr_stream_1 - lb t1, -1007(t6) - la s1, region_0+609 #start load_store_instr_stream_0 - la a5, region_1+5369 #start load_store_instr_stream_3 - la a7, region_2+2614 #start load_store_instr_stream_4 - sb a2, 10(a4) - sh s4, -539(s1) - sb a6, -66(s1) - lbu t0, 897(t6) - sh s8, 3(a4) - lbu s7, 266(s1) - lbu s10, -1(a4) - lhu a1, 829(s1) - lb t0, -8(a7) - lbu t3, 19(a4) - lbu zero, 130(a5) - sb a1, 291(t6) - sh ra, 557(a5) - lbu a3, 529(s1) - sb t0, 638(t6) - sb s3, 210(s1) - sw a6, -416(t6) - lb a6, 669(t6) - lbu t5, -55(s1) - sw sp, 25(a4) - sb t1, 0(a7) - sb a7, -758(a5) - lb ra, 999(t6) - sh s10, 649(a5) - lh a0, 23(a4) - lb s5, -15(a7) - sb a2, -520(a5) - lb t0, 60(a4) - lb a3, 5(a7) - lb s10, 832(a5) #end load_store_instr_stream_3 - lb ra, 12(a4) - lb s3, -7(a7) #end load_store_instr_stream_4 - lb s7, -44(a4) #end load_store_instr_stream_2 - lb s5, 647(t6) - lh t3, -990(t6) #end load_store_instr_stream_1 - lhu s11, -121(s1) #end load_store_instr_stream_0 -599: mulhu s4, s2, t2 - c.and a2, s0 - xor a5, zero, tp - xori s1, s3, 350 - add t0, s8, a3 -604: add s1, t6, sp - divu a6, s7, s8 - srai a3, a5, 24 -607: xor s4, sp, a5 - .4byte 0x00100073 # ebreak - srai t0, t6, 3 - c.srli a0, 30 - auipc a3, 472884 - mulh t0, t5, s6 - divu t2, a1, sp - c.nop -615: sltiu a3, s4, -795 - xori a6, ra, 786 - nop - bgeu a6, t6, 631f - blt zero, s1, 636f - c.nop - c.beqz s0, 633f - slt t3, a3, s11 - c.xor a1, a3 - divu a4, s11, a3 - lui s3, 532002 - beq zero, tp, 634f - div a5, t4, t3 - ori s6, t2, 860 - srai a2, s6, 27 - csrrci a0, 0x340, 28 -631: remu s5, gp, t0 - nop -633: c.srai a0, 7 -634: sltiu a3, s4, -777 - xori s7, t4, -181 -636: srl tp, a7, s4 - add a1, t3, s10 - c.andi a4, -15 - xor s5, a4, s10 - csrrsi s10, 0x340, 8 - slli t5, s7, 24 - auipc s7, 203673 - divu s4, t4, t0 - andi s2, a3, -628 - bge s6, s4, 662f - c.li s11, -4 - sub ra, zero, s11 - c.beqz a4, 668f - div t1, s1, a3 - c.sub a5, a1 - bge a3, t2, 670f - bge a3, s6, 672f - beq s4, t0, 658f - beq s0, s8, 674f - lui a3, 402310 - div t1, s0, a5 - slti s4, s1, 931 -658: .4byte 0x00100073 # ebreak - csrrsi ra, 0x340, 19 - srli tp, a7, 20 - sll a3, s8, a1 -662: srli s0, s1, 18 - c.bnez s0, 678f - c.add a3, s7 - sra s10, t4, gp - c.srai a4, 30 - c.slli s4, 26 -668: c.and a5, a0 - srli t2, a6, 30 -670: csrrsi s10, 0x340, 0 - c.xor a4, a2 -672: sltiu a3, s6, -802 - xor a5, t5, ra -674: c.srai a2, 22 - csrrci t3, 0x340, 11 - rem zero, t0, t3 - add a2, s8, t5 -678: c.xor s0, s0 - sltiu s6, s3, -674 - andi s4, a6, -591 - addi a6, t6, -254 - c.bnez a3, 693f - add a6, a6, t5 - csrrci a0, 0x340, 29 - c.ebreak;c.nop; - .4byte 0x00100073 # ebreak - c.srli s1, 17 - sra t3, t1, s4 - xor s0, s4, t3 - c.xor a3, a3 - c.beqz a0, 707f - c.mv t0, a1 -693: div s3, s2, a6 - ori a6, s10, -862 - slt t4, t0, s9 - nop - c.mv gp, s1 - sltu s1, t1, a0 - bltu t2, s8, 715f - bltu s5, t2, 720f - csrrsi t4, 0x340, 15 - mulhu t2, a3, t5 - slli a2, sp, 31 - xor s3, t1, t1 - bgeu t1, s10, 724f - csrrsi s6, 0x340, 20 -707: andi t6, a4, 807 - xor a1, ra, t3 - addi a6, zero, 2 #init loop 0 counter - c.nop - c.addi s10, -8 - c.sub a3, a2 - addi t0, zero, -9 #init loop 0 limit - c.mv s6, t0 - mulhu s4, sp, s5 - csrrs t2, 0x340, s6 - c.add a2, s2 - csrrsi zero, 0x340, 3 - sltu s3, a4, s8 - c.addi a3, -14 - csrrw ra, 0x340, a2 - remu a0, t5, t6 - and t2, t0, s10 - sub s6, t5, s8 - csrrc a4, 0x340, t2 - c.li s0, 20 - c.li s6, -20 - csrrc a7, 0x340, t3 -sub_4_13_0_t: c.lui ra, 28 - addi a6, a6, -1 #update loop 0 counter - divu a3, s7, a0 - and a4, t4, s5 - sub s11, s10, s1 - rem zero, s1, a1 - srai gp, gp, 14 - beq a6, t0, sub_4_13_0_t #branch for loop 0 - and s3, t0, s3 - sll a1, t2, a5 - csrrs a0, 0x340, sp - slli s3, a7, 21 - srai a7, t3, 31 - c.nop - sub s6, a4, s7 -715: c.add a5, a6 - c.xor a1, a4 - remu t6, s9, s6 - lui tp, 221489 - lui s0, 464350 -720: xori a5, s8, -879 - sll s3, a1, zero - c.and a2, a0 - slt a4, a5, t4 -724: csrrci t0, 0x340, 25 - srl a0, t0, s2 - bne s5, s2, 739f - slti tp, a5, -643 - c.and a4, a5 - c.and a1, a0 - ori a0, ra, -609 - blt t0, s5, 742f - bne s4, s1, 751f - div s3, zero, a3 - nop - xori a5, t6, 12 - andi zero, zero, 578 - c.bnez a4, 755f - c.add s2, t5 -739: .4byte 0x00100073 # ebreak - xori zero, s6, 829 - beq t6, s3, 758f -742: or t1, a3, a3 - bge s5, s1, 758f - lui t3, 694317 - c.andi a0, -7 - lui s1, 712598 - or s2, s3, t3 - csrrwi a4, 0x340, 4 - srli s2, a7, 11 - srl s5, t0, t4 -751: c.lui t1, 29 - c.ebreak;c.nop; - div a7, t2, a3 - ori t5, s2, -231 -755: rem t2, a5, t6 - c.mv s5, s6 - c.beqz s0, 768f -758: rem s0, a2, t5 - divu s7, ra, t6 - nop - c.nop - c.addi s6, 10 - auipc s2, 878289 - c.andi a3, -8 - csrrw gp, 0x340, t5 - andi tp, t6, 588 - c.add a2, sp -768: csrrc s11, 0x340, s2 - slt t2, a4, a7 - c.mv t5, s0 - c.sub a3, a1 - bge t2, t1, 787f - addi t3, t1, -51 - slti a0, s0, 905 - mulhsu a7, t1, t0 - c.li a3, -22 - csrrsi a6, 0x340, 30 - c.slli s11, 31 - csrrwi s6, 0x340, 9 - .4byte 0x00100073 # ebreak - c.nop - div tp, s5, s9 - csrrsi a2, 0x340, 1 - slli a4, sp, 14 - sltu a5, a3, ra - or s2, t3, s11 -787: bge t1, s0, 792f - slt s7, t4, a7 - csrrci tp, 0x340, 0 - mul t4, a7, s11 - c.srli a4, 18 -792: csrrw s1, 0x340, a6 - xor s6, a6, t0 - c.or a5, a5 - sll t6, a7, a7 - c.andi a5, -11 - c.srai a3, 20 - csrrwi a6, 0x340, 1 - c.li a4, -20 - csrrw s1, 0x340, a2 - ori s10, s6, 870 - divu s6, s0, t5 - c.addi a5, -15 - beq s5, s2, 820f - mulhu t2, a0, tp - sub s6, t5, s3 - mul t2, a6, t5 - remu s4, a6, s5 - beq a6, a3, 828f - mulhu gp, t6, s0 - div s5, t2, t3 - bne s6, t5, 814f - and a4, a3, t2 -814: slli s1, s7, 5 - mul a7, s3, s11 - add a2, s0, ra - c.nop - sll tp, a0, s10 - c.beqz s0, 839f -820: mulhsu a1, s4, sp - sra t2, s8, a5 - addi s5, t5, -435 - c.or a4, a2 - remu a6, a0, s11 - add t2, s5, t1 - bgeu a2, s9, 832f - c.and a1, s1 -828: sra a5, a0, a2 - sltiu t4, s2, 94 - csrrci s6, 0x340, 23 - lui s4, 300824 -832: bltu a0, ra, 840f - sltiu a2, s1, -268 - sub a3, s5, a1 - csrrwi s6, 0x340, 6 - and a7, a7, s9 - bltu a3, t4, 850f - c.nop -839: bgeu a5, s4, 859f -840: c.andi a4, -24 - c.beqz s1, 856f - mulh t5, tp, s8 - c.xor a3, a5 - srai a0, s7, 14 - bne t1, a0, 849f - nop - xor t3, s3, a0 - .4byte 0x00100073 # ebreak -849: divu t1, s5, zero -850: c.li s10, 22 - srli s3, t1, 28 - ori s1, a2, 549 - .4byte 0x00100073 # ebreak - or t1, s10, a0 - mul s1, s5, s4 -856: bge gp, s7, 874f - c.add t2, t2 - csrrsi s4, 0x340, 3 -859: sltiu a3, sp, 382 - .4byte 0x00100073 # ebreak - c.srai s1, 2 - c.li s4, 16 - auipc t5, 199554 - c.addi t2, 17 - addi s6, t6, -11 - rem a4, s1, s7 - lui a0, 621383 - andi a7, s2, 215 - c.li s1, 21 - xor s2, s10, t5 - c.andi s1, -13 - csrrs a0, 0x340, s10 - slti a6, t2, 33 -874: andi a2, s2, 185 - xori s11, t4, 334 - c.add s0, a6 - csrrwi t1, 0x340, 16 - remu tp, s4, t4 - slli s7, t5, 22 - c.andi s0, -21 - .4byte 0x00100073 # ebreak - slli t0, s0, 12 - and s7, a0, sp - nop - srli a2, t3, 12 - csrrc s3, 0x340, a2 - c.or a0, s0 - srl s3, s6, a7 - bne s1, zero, 909f - sltiu s0, a3, 139 - c.slli t3, 8 - mulhsu s3, s1, s9 - la a0, region_4+1257 #start riscv_load_store_rand_instr_stream_1 - sh s0, -1(a0) - c.srai a1, 13 - sw a6, 11(a0) - mulhsu s4, a2, s8 - sb a6, -7(a0) - lb s5, -8(a0) - sh tp, 1(a0) - mulh s3, s7, t1 - sub s4, sp, a0 - lb s5, 16(a0) - lb s1, 8(a0) - c.srai a3, 14 - remu t2, tp, s10 - sltu ra, s3, a4 - lbu a2, -6(a0) - and t2, t0, gp - c.nop - sw ra, 15(a0) - mulhsu s2, sp, s1 - sw a5, 11(a0) - lbu zero, 14(a0) - slli a5, t1, 24 - csrrwi t2, 0x340, 4 - sh a0, 7(a0) - slti t0, a4, 922 - lb t2, 4(a0) - sh ra, 9(a0) - lhu s5, 5(a0) - rem ra, sp, a2 - lbu s6, -15(a0) - lbu s2, -10(a0) - sll s4, a0, s11 - lhu t6, -13(a0) - lui s1, 453200 - lb s1, -11(a0) - c.srai a5, 26 - c.and a1, a4 - c.lui s5, 2 - sb s9, -12(a0) - c.srli a2, 7 - srl zero, s3, s5 - lb t1, -6(a0) - c.mv s10, s10 - lb t0, 12(a0) - divu a6, a7, zero - csrrwi s5, 0x340, 18 - lh t3, -13(a0) #end riscv_load_store_rand_instr_stream_1 - csrrw t3, 0x340, ra - xori t0, a7, -264 - sll s3, s8, a7 - mulhsu a3, a6, a6 - srli t1, t3, 15 - csrrc s6, 0x340, a0 - sltu a4, t4, s10 - srai s7, s11, 19 - csrrwi gp, 0x340, 24 - rem t4, a6, zero - c.and a4, a3 - c.ebreak;c.nop; - sub a5, a4, s9 - csrrw a6, 0x340, s1 - add a6, s11, t4 - add gp, s3, s7 -909: c.srli a1, 10 - bgeu a1, s4, 926f - bge t6, s11, 928f - rem s11, a2, a2 - xor t5, a0, s2 - c.beqz s1, 926f - c.srli a1, 2 - mulh a4, ra, s9 - mulh a3, a5, t5 - c.ebreak;c.nop; - csrrw s3, 0x340, s3 - divu s3, t6, ra - c.or a0, a0 - mul tp, tp, s6 - c.andi s1, 17 - c.xor a1, a0 - csrrwi s11, 0x340, 25 -926: divu s3, t3, a3 - beq t5, t4, 938f -928: xor s11, s5, t4 - c.lui s0, 8 - sll t2, s10, t3 - csrrs a0, 0x340, t6 - slt t3, a3, s11 - csrrwi t1, 0x340, 20 - lui ra, 505293 - csrrwi zero, 0x340, 29 - sltu t6, t4, gp - div s5, zero, tp -938: slti s5, s8, 621 - lw gp, 4(sp) - and a4, s8, a2 - addi sp, sp, 36 - ori s2, t4, 171 - srl s7, s7, a4 - c.or a2, a2 - nop - c.mv s4, a1 - c.or a4, a5 - c.ebreak;c.nop; -1530: c.jr x3 -sub_5: srai t5, a2, 8 - c.sub a5, a2 - c.and a0, s0 - nop - addi sp, sp, -16 - c.mv a3, s9 - sll t6, s7, a2 - mul a6, t1, a7 - sw gp, 4(sp) - c.slli s2, 4 - la s11, region_0+3728 #start riscv_hazard_instr_stream_1 - sb t1, -5(s11) - lbu t1, -8(s11) - sb t1, 9(s11) - lb a5, 15(s11) - sb t1, -13(s11) - lbu t1, 9(s11) - lbu t3, -5(s11) - csrrwi s5, 0x340, 30 - sb s5, -15(s11) - lb t1, -15(s11) - lh t1, -14(s11) - xori t3, t1, 259 - lb t3, -13(s11) - sh t3, 6(s11) - lbu a2, -1(s11) - sh a1, -8(s11) - csrrw a1, 0x340, a2 - lb a2, -1(s11) - lbu a2, -15(s11) - sh t1, -16(s11) - lbu a5, -6(s11) - c.srai a2, 10 - sb t1, 11(s11) - sra a5, s5, t3 - sra s5, t1, s5 - lb a1, -15(s11) - or a2, t3, a1 - lhu t3, 6(s11) - lhu t1, -6(s11) - c.slli a5, 18 - lh s5, 8(s11) - c.lui s5, 20 - lh a5, 0(s11) - c.mv s5, t3 - lbu a2, -1(s11) - lb t1, 11(s11) #end riscv_hazard_instr_stream_1 - la t2, region_4+4005 #start load_store_instr_stream_3 - la s10, region_2+5 #start load_store_instr_stream_0 - lh a6, -1(s10) - sb gp, 1(s10) - la s6, region_3+50 #start load_store_instr_stream_1 - sb a4, 5(s6) - lbu a6, -7(t2) - lbu s2, 37(t2) - la t5, region_1+9371 #start load_store_instr_stream_2 - lh t6, 25(t2) - sh s2, -87(t5) - sw gp, 13(t5) - lhu a4, 13(s10) - lb t0, 13(s6) - sb a4, -16(s6) - sb a5, 16(s10) - sh s10, 23(t2) - lw s2, -159(t5) - lb gp, -16(s6) - sb s2, 11(s10) - lb t3, 51(t5) - sb s11, 2(s10) - lh gp, -1(s10) - lbu a3, 10(t2) - lbu s5, 4(s10) - sh s2, -67(t5) - sh sp, 0(s6) - lhu zero, 5(s10) - lbu zero, 25(t2) - lhu t1, -15(t2) - lb a0, -35(t2) - sh t2, 31(t5) - lb s1, 14(t2) - lbu t3, 85(t5) - sw tp, -6(s6) #end load_store_instr_stream_1 - lbu s7, 103(t5) #end load_store_instr_stream_2 - lh a6, 17(t2) #end load_store_instr_stream_3 - lbu zero, -2(s10) #end load_store_instr_stream_0 - la tp, region_4+254 #start riscv_load_store_rand_instr_stream_1 - lb ra, 481(tp) - lbu a4, -711(tp) - sb s10, -157(tp) - sb a6, 183(tp) - lui a0, 328074 - sh t1, 552(tp) - lbu s10, -69(tp) - remu a3, t2, t6 - csrrwi t1, 0x340, 25 - and t5, s6, a0 - sll gp, ra, a5 - csrrs s4, 0x340, s11 - lb t3, 349(tp) - lh a1, 628(tp) - c.slli s11, 4 - c.ebreak;c.nop; - sh tp, -462(tp) - rem s2, t6, t4 - srai a1, a2, 0 - lbu a2, -741(tp) - lb a6, 809(tp) - sra t4, a0, tp - sh s4, -206(tp) - sh a3, -288(tp) - lhu s2, -74(tp) - lbu s3, 187(tp) - sh ra, 242(tp) - lbu a4, 894(tp) - csrrs s7, 0x340, t3 - c.nop - sb s2, 176(tp) - rem t5, zero, a6 - c.ebreak;c.nop; - addi a3, a0, 1005 - sh s0, 476(tp) - sub a5, zero, a5 - lbu a1, -17(tp) - sb t1, -135(tp) #end riscv_load_store_rand_instr_stream_1 -sub_5_2: jal gp, 8f -0: c.jal 15f -1: c.j 3f -2: jal t0, 14f -3: jal ra, 4f -4: jal ra, 0b -5: jal s2, 11f -6: c.j 5b -7: c.j 9f -8: c.j 18f -9: jal t1, 16f -10: jal t1, 19f -11: c.jal 1b -12: c.j 13f -13: c.j 7b -14: c.jal 6b -15: jal t1, 12b -16: jal ra, 17f -17: c.jal 21f -18: c.j 20f -19: c.j 2b -20: c.jal 10b -21: mul a0, s8, tp - la ra, region_3+293 #start load_store_instr_stream_0 - la a5, region_3+501 #start load_store_instr_stream_3 - la t6, region_3+368 #start load_store_instr_stream_2 - la t0, region_3+130 #start load_store_instr_stream_1 - sb t5, 40(ra) - lbu s1, -55(a5) - lb zero, -59(ra) - sh t3, 21(ra) - lh a6, 54(t6) - lbu a4, 16(ra) - sb a0, 7(t6) - sb s6, -60(ra) - lbu t5, -3(t0) - sb a3, -35(t6) - sh a1, -28(t6) - sw s5, -10(t0) - sb a4, -184(a5) - sb s9, 49(t6) - lbu zero, 56(ra) - lb gp, -137(a5) - sb s10, -42(ra) - sb zero, -5(t0) - sb gp, -112(a5) - sb tp, -248(a5) - lbu s11, -13(t0) - lb t3, -48(ra) - lhu s4, -12(t6) - lbu tp, -16(t0) - sh a7, 12(t6) - lhu a4, -215(a5) #end load_store_instr_stream_3 - lbu s3, 5(t0) - lhu gp, 2(t0) #end load_store_instr_stream_1 - sb s3, 59(t6) #end load_store_instr_stream_2 - lbu a0, -14(ra) #end load_store_instr_stream_0 - la t6, region_3+228 #start riscv_load_store_rand_instr_stream_0 - lhu a5, 146(t6) - lh tp, 22(t6) - c.ebreak;c.nop; - c.li a0, -13 - lbu a1, 245(t6) - lhu s6, -108(t6) - sb s9, -184(t6) - rem a2, s6, s9 - lb s0, 75(t6) - csrrw t4, 0x340, ra - ori s10, a6, -267 - c.add a3, s2 - mulhu a5, gp, s6 - srai zero, a4, 14 - lb a1, -79(t6) - srli zero, s2, 22 - lb s11, 114(t6) - sltu a1, s3, t1 - sra gp, s0, t5 - .4byte 0x00100073 # ebreak - xori t4, s9, 34 - nop - lb s0, -67(t6) - lhu s11, -92(t6) - sb t2, -39(t6) - sub ra, a3, a2 - xor zero, t5, s0 - mul gp, t0, s6 - lb t4, -77(t6) - srli a1, a3, 20 - lbu a4, 237(t6) - c.nop - lbu s7, 69(t6) - c.srai a5, 14 - sw a3, -216(t6) - divu a2, s1, ra - rem tp, t1, a7 - lbu a3, 143(t6) - lbu s11, 173(t6) - mulh a7, t5, s5 - lh s0, 8(t6) - sh sp, 230(t6) - c.lui s1, 28 - sb s4, 248(t6) - and zero, t5, zero - ori t5, t2, 227 - lbu a1, -132(t6) - lbu a1, 42(t6) - sb a5, -88(t6) - sw t5, -108(t6) - lb a1, -39(t6) #end riscv_load_store_rand_instr_stream_0 - la t4, region_2+6486 #start load_store_instr_stream_1 - la s1, region_0+3012 #start load_store_instr_stream_0 - lb a5, 15(t4) - la s6, region_4+1799 #start load_store_instr_stream_3 - la ra, region_3+336 #start load_store_instr_stream_2 - lb s2, 207(s1) - sb a7, -7(s6) - lhu a7, 0(t4) - sb a1, 8(t4) - lbu a1, -77(ra) - lbu zero, 645(s1) - lw t6, -228(ra) - sb a3, 455(s1) - lb a6, -10(s6) - lb a2, -95(ra) - lbu s4, -969(s1) - sb t4, 139(ra) - sb s6, -63(ra) - lh a1, -57(s6) - lhu s5, 2(t4) - sb s1, 4(t4) - sb a5, -36(s6) - sb s11, 29(s6) - lbu a6, -43(ra) - lb gp, -10(s6) - lh a7, -890(s1) - lbu s4, -125(s1) - sw t6, -23(s6) - lhu a0, 4(t4) - sb a0, 91(ra) - lhu s10, -68(ra) - sb s0, 801(s1) - lb a1, -46(s6) #end load_store_instr_stream_3 - sw a6, 14(t4) #end load_store_instr_stream_1 - sb t0, -197(ra) - sb a2, 875(s1) - lb a4, -141(ra) #end load_store_instr_stream_2 - lb s0, 319(s1) - sb s7, 43(s1) #end load_store_instr_stream_0 -sub_5_3: jal gp, 12f -0: jal tp, 5f -1: jal ra, 3f -2: c.jal 9f -3: c.j 13f -4: jal ra, 6f -5: jal tp, 1b -6: jal t1, 0b -7: c.jal 2b -8: jal ra, 10f -9: jal t1, 11f -10: c.j 7b -11: c.j 4b -12: jal ra, 8b -13: divu s3, t0, s3 - la t1, region_0+2530 #start riscv_hazard_instr_stream_0 - sb a6, -1(t1) - c.srli a2, 11 - lw t6, 38(t1) - and a4, t6, a1 - lb s11, 63(t1) - lbu a4, 64(t1) - csrrw a2, 0x340, s11 - sw a1, -18(t1) - sb t6, -19(t1) - sub a1, a2, t6 - sb s11, 39(t1) - lui a4, 799675 - csrrc a6, 0x340, s11 - lb t6, -1(t1) - sw a2, 42(t1) - lh a2, 32(t1) - nop - srli t6, s11, 24 - c.andi a1, 13 - c.sub a2, a4 - lh s11, -10(t1) - lb a1, 61(t1) - c.addi a6, -9 - ori s11, a6, -573 - sltiu a1, a4, -146 - sw a1, -18(t1) - lbu a6, -33(t1) - sh a1, 4(t1) - csrrw a6, 0x340, a1 - sb a2, 5(t1) - c.nop - sb a1, -31(t1) - lhu a1, 2(t1) #end riscv_hazard_instr_stream_0 - ori tp, a7, -906 - mulh a1, a5, a3 - c.li t0, 6 - sub a2, t0, s0 - divu a0, gp, ra - c.xor a4, s1 - bge gp, s8, 8f - auipc t4, 402073 -8: c.sub s1, s1 - csrrsi s11, 0x340, 8 - sltiu s10, ra, 811 - div tp, s7, s10 - bne s9, a1, 29f - bne s9, a3, 33f - mulhsu a3, s3, s11 - c.and a3, a0 - c.and s1, a0 - csrrci s0, 0x340, 6 - bgeu zero, t3, 37f - bgeu gp, s1, 27f - nop - xor a3, a1, t1 - sra a3, a1, a5 - c.addi a0, -32 - sll a4, a6, t2 - csrrwi a3, 0x340, 1 - rem s3, t0, t2 -27: beq a3, gp, 41f - bne a7, zero, 35f -29: bne s10, a1, 48f - lui t0, 209065 - slt t1, t3, s2 - mul s0, t5, s5 -33: bge s4, s11, 46f - andi s4, a1, -855 -35: srli t0, s11, 2 - beq s9, a6, 56f -37: bgeu a1, s7, 47f - c.lui t2, 30 - slli a6, s6, 28 - c.and a0, a2 -41: slti s1, t5, 145 - or s5, sp, t5 - add s11, a4, t4 - c.sub a4, s1 - addi t1, t3, 180 -46: andi a3, t6, -597 -47: c.srli s1, 22 -48: .4byte 0x00100073 # ebreak - beq a2, a0, 69f - c.nop - c.nop - c.add s2, t1 - beq s0, s5, 72f - c.mv a3, s1 - c.bnez a2, 58f -56: .4byte 0x00100073 # ebreak - csrrw t2, 0x340, s10 -58: blt s1, ra, 73f - srl t6, t2, zero - srli a7, a3, 31 - .4byte 0x00100073 # ebreak - c.mv s2, s8 - rem t2, s1, s5 - srl tp, sp, a4 - andi s2, s10, 267 - c.andi a4, -30 - andi s1, a4, 272 - add tp, a4, t1 -69: auipc t1, 537810 - c.add a3, a6 - addi a0, ra, -794 -72: mulhsu t6, a6, s7 -73: c.andi s0, 24 - c.and s1, a1 - mulhu t2, s10, s2 - c.srai a0, 17 - c.xor s0, s1 - c.add s11, a7 - c.bnez s1, 85f - or a3, a1, a4 - xori a3, a4, -907 - c.add t6, t5 - remu s6, s3, a7 - c.slli s10, 16 -85: ori s10, s11, 796 - c.or a4, a2 - csrrci t3, 0x340, 7 - andi s2, ra, -907 - c.or a2, s0 - c.li a0, -32 - c.nop - c.slli ra, 29 - slt s5, t5, gp - c.srai s0, 12 - xori t5, t0, -1012 - slli s6, a1, 28 - ori t5, s3, 977 - mulhu t5, s7, s3 - csrrs ra, 0x340, sp - nop - c.andi s0, 31 - bge s3, s8, 112f - c.nop - slli t0, a0, 26 - sltu s11, s0, a4 - c.mv s1, ra - remu a5, s3, s11 - sltu a3, s2, ra - mulh a3, s7, s7 - sub s5, s4, t2 - c.nop -112: c.bnez a3, 124f - c.srai a5, 13 - sll zero, s8, t6 - xor s6, t1, a0 - .4byte 0x00100073 # ebreak - nop - bne t3, tp, 131f - c.bnez s1, 137f - divu zero, t0, s0 - srli a3, t5, 5 - csrrwi s5, 0x340, 15 - csrrw s11, 0x340, s2 -124: c.xor s1, s0 - csrrs s6, 0x340, a6 - nop - c.bnez s1, 141f - mul s5, s1, t5 - or s5, t5, s9 - srl zero, a2, tp -131: srli gp, s3, 16 - lui s0, 272294 - mulhsu a0, a3, t0 - bltu s2, s8, 144f - csrrci s5, 0x340, 23 - srli s0, s2, 22 -137: sltu t2, a0, a5 - mulhsu a3, t0, sp - c.srai a3, 16 - c.and s1, s0 -141: auipc s2, 616637 - add ra, s6, t0 - csrrs t3, 0x340, s10 -144: slt s2, ra, a0 - c.lui s1, 24 - andi s1, a4, 769 - c.addi a5, 29 - srli s5, a7, 11 - srl t3, ra, t2 - c.xor a3, s0 - mulh t4, a0, s1 - mulh t5, s2, a0 - c.addi s11, -29 - nop - csrrsi s7, 0x340, 25 - csrrsi s0, 0x340, 12 - c.addi s4, 2 - c.slli s6, 27 - c.andi a0, 25 - sltiu ra, t5, -1 - addi t2, a0, -371 - c.mv s3, a0 - mulhsu a6, s7, s10 - andi s1, a6, -23 - addi t4, s8, 496 - mulhu ra, a4, s3 - sltiu t1, gp, 498 - nop - csrrwi zero, 0x340, 1 - xori t3, s10, -160 - c.or s0, a0 - div t0, a2, sp - andi s5, s10, 1018 - rem t5, t0, tp - sra a1, t0, t1 - divu s10, s1, t5 - sltiu s4, a2, 173 - c.nop - c.and a4, a4 - c.li t6, -21 - lui s4, 819528 - nop - nop - and s7, s11, a5 - and t5, a5, s5 - c.beqz a2, 197f - sll s0, ra, a3 - andi t2, sp, 656 - csrrs s6, 0x340, gp - c.bnez a0, 208f - csrrw tp, 0x340, s0 - c.lui t3, 13 - lui a6, 873107 - c.ebreak;c.nop; - c.bnez a1, 203f - xor a1, gp, a2 -197: c.li s3, -1 - remu s10, t2, zero - srli t1, a3, 11 - lui t4, 656843 - bge sp, s9, 218f - andi t0, a5, 212 -203: c.addi t1, 12 - c.and a4, a0 - beq t6, s7, 209f - c.addi t3, -29 - xor gp, sp, a1 -208: c.sub a2, a4 -209: slt t4, a1, s2 - ori a7, s5, 974 - addi a2, s1, 178 - c.nop - beq s6, a1, 224f - .4byte 0x00100073 # ebreak - csrrw a6, 0x340, s2 - slli s6, s8, 3 - sra s2, s10, s10 -218: nop - c.andi s0, 13 - addi a3, zero, -7 #init loop 0 counter - sub t3, zero, a3 - sra t1, a3, s10 - sub zero, a1, zero - sll a0, a5, t0 - andi s6, t5, 590 - csrrs s5, 0x340, s0 - csrrw a2, 0x340, sp - srl s11, s10, t6 - rem zero, s4, zero - addi t0, s7, -461 - c.slli a6, 31 - rem s6, tp, t5 - sltiu a4, s4, 332 - addi tp, zero, -10 #init loop 0 limit - remu a4, a6, a0 - sra s6, a2, s10 -sub_5_8_0_t: divu zero, tp, s4 - .4byte 0x00100073 # ebreak - c.sub a1, a1 - csrrsi zero, 0x340, 18 - addi a3, a3, -6 #update loop 0 counter - srli s2, t4, 21 - ori t5, s2, -720 - c.xor a2, a3 - bge a3, tp, sub_5_8_0_t #branch for loop 0 - c.mv s5, t4 - csrrwi tp, 0x340, 25 - mulhsu a4, s0, a4 - c.li s5, 0 - addi t0, a0, -641 -224: remu tp, a4, s1 - mul zero, s5, s4 - bltu t2, s8, 242f - c.addi t0, -32 - c.lui s6, 29 - sltu s10, s3, t0 - or s0, a4, t0 - .4byte 0x00100073 # ebreak - sra s3, a4, tp - csrrc t6, 0x340, tp - csrrsi t3, 0x340, 25 - slt ra, a7, t0 - slli ra, sp, 12 - csrrs s6, 0x340, a7 - andi t0, t6, 448 - xor s0, t4, s6 - blt t1, zero, 256f - c.or a0, a3 -242: c.nop - auipc t2, 1045254 - c.lui a0, 6 - div s2, a5, s10 - xor a2, s5, zero - xor s7, s1, zero - slti a1, t2, -942 - slt t5, t0, t1 - bne s2, t5, 270f - xor tp, a2, t1 - sra gp, t3, s9 - srli zero, s7, 20 - auipc s10, 801478 - c.andi a2, 5 -256: xori s4, a1, 979 - andi s5, a0, -713 - csrrci gp, 0x340, 12 - sltiu t5, sp, 41 - csrrsi ra, 0x340, 2 - c.andi a4, 27 - c.bnez a4, 281f - sra a4, gp, t5 - c.srai a4, 10 - xori t4, t5, -491 - c.srai a5, 1 - c.and a2, s0 - c.xor a4, a4 - mulhu ra, t5, s6 -270: lui s2, 588349 - c.beqz s0, 282f - beq a1, a7, 285f - bge a6, a6, 292f - bltu tp, a7, 282f - c.and s0, s0 - bne a7, s8, 289f - ori t0, t5, 230 - and t3, t6, a7 - divu a0, s6, s3 - mul a6, t4, s4 -281: c.bnez a4, 284f -282: bltu s2, t4, 301f - srli tp, a1, 17 -284: divu ra, sp, t2 -285: mulhu s1, s3, a4 - csrrw s2, 0x340, a3 - sll s7, ra, s4 - c.srai a5, 14 -289: .4byte 0x00100073 # ebreak - sltiu a4, tp, 67 - c.li s0, -18 -292: c.lui s4, 2 - c.xor a0, a4 - andi t6, ra, -114 - csrrci a7, 0x340, 4 - c.addi t4, 27 - bne s0, s5, 315f - srai t3, s9, 7 - sra s0, s6, zero - c.xor a3, a3 -301: bge s7, a1, 318f - bgeu t2, s8, 308f - c.or a3, a3 - c.add s6, s9 - c.addi s11, -4 - slli s11, tp, 29 - lui a6, 433343 -308: sll s1, s5, t2 - bgeu s4, s7, 319f - bge s11, a6, 322f - c.or s0, a2 - mulhsu t6, a6, a2 - xor s10, s4, t6 - c.addi t3, 15 -315: lui a3, 598733 - add s6, a7, a5 - c.srai a5, 9 -318: or gp, ra, t3 -319: c.beqz a2, 330f - addi s1, a6, 821 - div s10, a1, tp -322: c.or a2, a2 - or a7, a6, t6 - c.nop - c.slli t3, 6 - bgeu s8, a2, 342f - sra tp, a6, s5 - addi ra, t0, 636 - bge t6, t1, 337f -330: c.xor a4, a5 - c.add s1, t4 - srl s4, a2, a7 - csrrc a2, 0x340, s9 - c.or a2, a3 - c.srli a3, 31 - csrrc a5, 0x340, s6 -337: sra s5, t3, s11 - sltiu a2, t0, -920 - sub s5, ra, s1 - add t0, a7, t0 - mulhu gp, a5, s7 -342: remu gp, tp, t3 - nop - c.ebreak;c.nop; - bltu gp, a4, 361f - slti a3, t4, 956 - c.ebreak;c.nop; - remu s4, s1, s7 - c.sub a3, a3 - c.or a5, s1 - srli s10, zero, 10 - mul s0, a1, s4 - srl a2, s6, s4 - xori s6, s3, -970 - andi s11, a6, -1023 - bgeu s4, t6, 370f - sll a3, t2, ra - c.add gp, s0 - c.beqz s0, 374f - la s2, region_2+171 #start load_store_instr_stream_3 - la a7, region_2+7396 #start load_store_instr_stream_2 - sb ra, -256(s2) - la t5, region_2+4838 #start load_store_instr_stream_1 - la s4, region_2+7226 #start load_store_instr_stream_0 - sb gp, -168(s2) - lh a5, 16(s4) - sb t2, 362(a7) - sh gp, -2(t5) - lhu a6, 662(a7) - lb ra, 416(s2) - sb t4, -9(s4) - sb s9, 434(a7) - lw tp, 480(a7) - lbu a5, -3(t5) - sb a5, -193(s2) - lb s3, -9(s4) - lhu tp, 0(t5) - lb s10, 279(s2) - sw t2, -6(s4) - lb s10, -114(a7) - sw t0, 693(s2) - lb t4, 983(a7) - lbu t3, 11(t5) - lb t2, 656(s2) - lb a2, 5(s4) - lb s10, 11(s4) - lbu a5, 58(a7) - sh s2, -57(s2) - lw s6, 560(a7) #end load_store_instr_stream_2 - sh a3, 781(s2) #end load_store_instr_stream_3 - lbu a5, -9(t5) #end load_store_instr_stream_1 - lbu t2, 5(s4) #end load_store_instr_stream_0 - sra s1, sp, a5 -361: csrrc s10, 0x340, sp - c.bnez a1, 376f - srli s10, zero, 24 - c.srli a3, 28 - c.nop - divu s10, s1, s8 - auipc s5, 810864 - c.nop - c.srli a5, 9 -370: sub s10, s1, a0 - c.beqz a1, 391f - bge s8, gp, 374f - blt t2, t3, 383f -374: slt a6, s5, t4 - c.nop -376: addi a0, zero, -541 - xor a1, a0, s4 - rem s11, a4, zero - c.slli s6, 29 - bne s8, sp, 384f - srai tp, s7, 8 - remu tp, a6, a5 -383: or s7, t2, t6 -384: .4byte 0x00100073 # ebreak - srli s4, a5, 13 - c.or s0, a5 - ori t2, s11, 116 - mulhu a5, t3, t2 - sra gp, a6, tp - bne sp, s4, 407f -391: mul s6, t1, tp - sltiu s1, gp, -910 - c.lui a3, 8 - mulh a2, s5, zero - mulh t0, a0, zero - c.or a1, a2 - sub s6, t2, a6 - c.ebreak;c.nop; - c.nop - c.srli a0, 28 - bge zero, ra, 421f - lui a1, 125172 - csrrs ra, 0x340, a5 - c.sub a2, a2 - xor t2, s8, sp - c.xor a3, a3 -407: auipc tp, 103940 - sltu s3, a6, a7 - mul a2, a3, t4 - auipc a2, 948988 - c.srli a3, 21 - c.srai a3, 30 - c.nop - srli gp, a1, 14 - bne ra, a4, 433f - c.and a3, a3 - c.or a3, a5 - c.slli s7, 30 - slli t6, a2, 19 - srai s3, t0, 21 -421: c.and a0, a2 - csrrs t1, 0x340, a7 - bgeu s0, a2, 430f - nop - blt t6, t1, 435f - andi t3, a1, -429 - c.beqz a3, 443f - csrrc t1, 0x340, gp - c.or a3, a2 -430: c.or a4, s0 - c.srai a5, 29 - c.slli s6, 10 -433: slt t5, t4, s4 - rem t0, s3, sp -435: bne s2, a7, 454f - csrrs zero, 0x340, a3 - mulhsu s7, s3, sp - add t4, t3, s6 - sll s11, tp, s8 - div s1, s0, s3 - csrrc t5, 0x340, tp - c.sub a2, a5 -443: csrrc s3, 0x340, s0 - c.and a1, a4 - div t6, a1, a4 - c.sub a4, s0 - csrrs s7, 0x340, t2 - slt s2, s4, sp - sltiu a5, s9, 622 - beq a6, t5, 470f - c.addi s3, 28 - mulhsu a7, s0, t5 - c.srai a3, 8 -454: add t1, t0, s7 - c.beqz a5, 468f - bge t0, a0, 473f - c.andi a1, 6 - and a3, s7, t6 - add t3, tp, s8 - slli s2, s6, 21 - nop - ori s3, a5, 839 - or a6, a6, gp - lui s5, 922184 - srl t6, s1, s5 - sll gp, a1, t5 - mulhu s3, t3, t4 -468: andi t3, s11, 726 - and zero, t1, a0 -470: csrrc a0, 0x340, gp - c.andi a1, 4 - rem s11, zero, sp -473: csrrw zero, 0x340, a6 - c.srli s0, 11 - csrrci s0, 0x340, 15 - c.addi t3, 12 - csrrc a2, 0x340, a2 - mulhsu ra, a2, a5 - c.bnez a0, 496f - or a3, a1, gp - ori t6, s5, -1020 - c.srai s1, 31 - sll t0, t2, t0 - c.add s2, s7 - sll t1, s3, s11 - slli t3, s8, 26 - sll a1, s1, a0 - c.addi a1, -13 - add a5, s8, t1 - mulhu a7, s9, s4 - addi s10, s8, -377 - sra a6, s2, a4 - addi t2, s4, -69 - addi s1, s4, -161 - slt a3, s11, a4 -496: .4byte 0x00100073 # ebreak - slti tp, a5, 254 - and t4, s2, a6 - c.nop - beq sp, a7, 508f - mulh zero, gp, sp - sub a1, t1, s1 - c.add gp, t1 - sll s3, t2, t5 - mulhu zero, s6, zero - add s6, a3, s11 - c.srai a3, 6 -508: ori zero, t1, -402 - csrrs s6, 0x340, a3 - mulhu t2, s9, s8 - lui a1, 877662 - ori t6, a0, 903 - c.sub s1, a1 - csrrwi s3, 0x340, 27 - c.beqz s1, 521f - ori a4, s2, 457 - c.srai s1, 20 - add s1, s8, s11 - c.beqz a5, 532f - c.ebreak;c.nop; -521: xori s10, a1, -711 - c.beqz s1, 530f - and t3, a6, t0 - lui zero, 578180 - c.beqz a0, 536f - c.sub s0, a5 - slli t1, s11, 10 - or s0, t6, s9 - c.beqz s0, 539f -530: and a6, a7, a0 - slt s1, ra, a2 -532: sltiu t0, s1, 819 - c.li t2, 17 - c.ebreak;c.nop; - c.xor a5, a5 -536: srli zero, gp, 20 - srai a2, a1, 15 - xor s0, zero, s9 -539: sltiu s7, s5, -857 - csrrc t2, 0x340, sp - csrrs t1, 0x340, t4 - c.mv s6, t3 - c.li t6, 29 - slli s0, s0, 4 - slt s5, a5, a6 - or a7, s0, a0 - mulhu ra, t2, s11 - mulhu s4, s2, t3 - c.mv tp, a1 - div a6, a1, s8 - beq s7, sp, 561f - lui a4, 978872 - sra a0, a4, tp - c.beqz a3, 573f - c.or a1, s1 - c.lui s0, 2 - c.and a3, a2 - srl s1, gp, gp - c.beqz a3, 566f - sltu t1, s7, s2 -561: c.bnez a4, 581f - c.sub a5, a1 - mulhu t2, ra, s0 - or t4, a7, s10 - c.nop -566: div t3, s7, t6 - mulhu a7, s4, a3 - or a7, a5, s7 - c.slli t0, 25 - c.sub a4, a4 - c.bnez a0, 589f - bne s4, t4, 574f -573: bge ra, a0, 576f -574: c.beqz a5, 592f - mulhsu zero, s3, t4 -576: bltu a3, a1, 592f - div t6, s0, s8 - mulhsu a2, t3, s11 - c.andi a4, -17 - mulhu a2, tp, s7 -581: slti t2, s0, -975 - blt s5, s8, 586f - div a1, a3, a4 - add a6, a3, zero - nop -586: c.sub a4, s0 - or a5, s0, a4 - lui gp, 600974 -589: slti s5, a2, -441 - bgeu gp, gp, 592f - c.or a1, a4 -592: mulhu s4, a6, a2 - sltiu s1, s11, -210 - lw gp, 4(sp) - .4byte 0x00100073 # ebreak - add t2, t0, a7 - add t0, s4, a4 - remu t3, sp, a0 - slli a5, s8, 3 - addi sp, sp, 16 - c.mv s10, s2 - mulhsu a3, a1, a4 - divu ra, a3, s3 -985: c.jr x3 -sub_1: lui s2, 809301 - sub ra, t3, t6 - divu tp, s3, s10 - addi sp, sp, -36 - sw gp, 4(sp) - c.ebreak;c.nop; - c.srli s0, 5 - slti t1, s3, -611 - mul a5, a7, t5 - la s11, region_3+142 #start riscv_hazard_instr_stream_5 - lbu t3, -15(s11) - lb a7, 13(s11) - sltiu s4, a4, 385 - c.slli tp, 18 - sb s4, 13(s11) - csrrci a7, 0x340, 14 - lbu tp, 3(s11) - sb tp, -7(s11) - sb t3, 13(s11) - sb t3, 5(s11) - lbu a7, 1(s11) - sb s4, 15(s11) - c.sub a4, a4 - lb t3, 13(s11) - sb a4, 5(s11) - lhu tp, -10(s11) - sb t3, -15(s11) - lbu tp, 3(s11) - sb a4, 4(s11) - sb t3, 2(s11) - lbu t6, 12(s11) - lh a4, -2(s11) - csrrsi t3, 0x340, 2 - c.ebreak;c.nop; - sb a4, -2(s11) - sb t6, 0(s11) - lbu tp, 15(s11) - lb t3, -4(s11) - c.and a4, a4 - lui t6, 630497 - lhu t3, 16(s11) - lhu a4, -4(s11) - c.srai a4, 15 - lb tp, -9(s11) - lw a7, -14(s11) - sb s4, -8(s11) - lbu a7, 16(s11) - sltiu t3, t3, 169 - lhu t6, 0(s11) #end riscv_hazard_instr_stream_5 - la a1, region_4+3339 #start riscv_hazard_instr_stream_11 - sb t2, -12(a1) - lbu a2, -1(a1) - lh a4, -1(a1) - c.srli a4, 14 - sh s1, 11(a1) - add a4, s1, a4 - srl t2, a2, s1 - sb t2, 9(a1) - c.xor a2, a2 - lb t2, 15(a1) - lbu t2, 16(a1) - slt t2, s11, a2 - lh t2, -15(a1) - mulhu a4, a6, s1 - lbu a6, 14(a1) - sb a2, -14(a1) - lbu t2, -8(a1) - srli t2, a4, 25 - lhu s1, -5(a1) - sb a2, 2(a1) - sh s11, -13(a1) - sra a6, t2, a2 - lb s11, -2(a1) - srli a6, a4, 24 - sb s1, -16(a1) - c.ebreak;c.nop; - c.slli t2, 29 - sb s1, 12(a1) - sb a2, -12(a1) - lbu a6, -16(a1) - lb s1, -5(a1) - c.nop - remu a6, a4, s1 - lb t2, -13(a1) - lbu s11, 16(a1) - lbu a4, -11(a1) - lbu s1, 11(a1) - sh t2, 3(a1) - lb s1, -4(a1) - lb a6, 16(a1) - sb s11, 10(a1) - lui a6, 699600 - xori t2, t2, 261 - lbu s11, 0(a1) #end riscv_hazard_instr_stream_11 - la a5, region_4+3428 #start load_store_instr_stream_2 - la s0, region_1+3960 #start load_store_instr_stream_1 - lhu a6, 10(a5) - lb s7, 15(a5) - lbu tp, 5(s0) - sw s11, -16(a5) - lbu s2, -7(s0) - la s10, region_0+1867 #start load_store_instr_stream_0 - sb s6, 8(s0) - lb a3, 38(s10) - sb t0, 2(a5) - sb s2, -13(a5) - lb s1, -5(s0) - lb s1, -7(s0) - lbu t5, 30(s10) - sb t4, 9(a5) - sh a4, 14(s0) - lb t0, -12(s0) - sb a2, -11(a5) - lhu zero, 8(s0) #end load_store_instr_stream_1 - lb a0, 16(a5) - sb a5, 64(s10) - lw t5, 45(s10) - sb s8, 1(a5) #end load_store_instr_stream_2 - sb s9, -14(s10) #end load_store_instr_stream_0 - la a0, region_3+85 #start load_store_instr_stream_0 - la t2, region_4+2037 #start load_store_instr_stream_2 - lhu s5, 11(a0) - la t4, region_2+4117 #start load_store_instr_stream_3 - la a3, region_1+2137 #start load_store_instr_stream_4 - la s0, region_0+2644 #start load_store_instr_stream_1 - lbu t6, 6(a3) - lbu s6, -2(t2) - lhu s3, 1(t4) - lb s10, 93(s0) - lb s5, -2(t2) - sb gp, -6(a3) - sh t1, 13(t4) - sb a5, -14(a0) - sh a5, 814(s0) - lbu zero, 13(t4) - sh t4, -35(a0) - lh a1, 272(s0) - sw a3, -840(s0) - lw t3, -53(a3) - sb t2, 28(a0) - lb s4, -28(a3) - lb s4, -12(t4) - lb t6, 8(t2) - sb a6, -55(t2) - lbu gp, 957(s0) - sh s5, -49(a3) - sh a5, -51(t2) - lbu a5, 13(a3) - sb ra, 56(a0) - sb a6, -50(t2) - lbu a2, 0(t4) #end load_store_instr_stream_3 - lbu t6, -34(t2) - lbu a5, 845(s0) - sb s7, -8(a3) - sb a1, 27(a3) - lbu t0, -8(t2) - lbu s6, 8(a0) - sh a4, 194(s0) #end load_store_instr_stream_1 - sb gp, -8(a0) - lb t1, 19(a0) - lb t1, -29(t2) #end load_store_instr_stream_2 - lhu a5, -3(a3) #end load_store_instr_stream_4 - lw t6, -1(a0) #end load_store_instr_stream_0 - la s11, region_1+1943 #start riscv_hazard_instr_stream_9 - c.nop - .4byte 0x00100073 # ebreak - lbu s7, 16(s11) - lh t1, 3(s11) - sw t1, -3(s11) - lh t4, 11(s11) - sra t1, t1, t1 - mul t4, s0, s1 - sltu s0, s7, s0 - divu tp, t4, s7 - c.or s1, s1 - lh s7, 15(s11) - divu s1, s7, tp - lb t4, -4(s11) - lbu t4, -6(s11) - sb t4, 4(s11) - mul t4, t4, tp - lb tp, -5(s11) - mulhu t4, s1, s1 - lb s7, 0(s11) - mulhsu s7, s7, s7 - mulhsu t4, t4, t1 - mulh tp, t1, s0 - sh tp, -13(s11) - div s0, t4, t4 - sb s7, 16(s11) - sh s7, 5(s11) - lh t1, -13(s11) - lhu s1, 11(s11) - lbu t1, -10(s11) - lbu s1, -4(s11) - lb tp, 9(s11) - c.lui s1, 10 - add t1, s0, s7 - sub s7, s1, t4 - lb t1, -2(s11) - sb t4, 10(s11) - lb s7, 8(s11) - c.sub s0, s1 - mulhu s1, s7, s7 - sb tp, -2(s11) - lb t1, -3(s11) - lbu s7, 12(s11) - sb t4, 5(s11) - sb tp, 15(s11) - mulhsu s1, s0, tp - csrrc s1, 0x340, s7 - lbu tp, -10(s11) #end riscv_hazard_instr_stream_9 -sub_1_17: jal gp, 6f -0: c.j 13f -1: jal ra, 8f -2: jal ra, 11f -3: c.j 15f -4: jal t1, 2b -5: c.jal 10f -6: jal s4, 22f -7: c.j 5b -8: jal ra, 12f -9: c.j 18f -10: c.jal 14f -11: c.jal 7b -12: jal tp, 17f -13: c.jal 1b -14: jal s4, 28f -15: jal s11, 25f -16: c.jal 30f -17: jal ra, 29f -18: c.j 26f -19: jal a0, 0b -20: c.j 3b -21: jal ra, 19b -22: c.j 27f -23: jal a5, 20b -24: jal ra, 9b -25: c.j 24b -26: jal ra, 21b -27: jal ra, 4b -28: jal a2, 23b -29: c.j 16b -30: remu t6, a3, t0 - la t5, region_0+1764 #start load_store_instr_stream_1 - la s4, region_4+2629 #start load_store_instr_stream_2 - la s2, region_2+5644 #start load_store_instr_stream_0 - lhu a5, -696(t5) - lb zero, -557(s2) - la a2, region_1+16332 #start load_store_instr_stream_3 - lb s7, -9(a2) - sh a0, -168(s2) - lbu s10, -195(t5) - lh t6, 12(a2) - lb a3, 22(s4) - lbu ra, 271(t5) - lbu zero, -5(s4) - lhu ra, -10(a2) - lhu s1, -320(s2) - lh s5, 14(a2) - lbu ra, 53(s4) - sw a1, 19(s4) - lhu a6, -626(t5) - lbu s5, 60(s4) #end load_store_instr_stream_2 - lb a6, 190(s2) - lb a6, -475(t5) - lbu s0, 255(s2) - lb t2, -12(a2) - lbu t1, -13(a2) - lbu a5, -869(t5) #end load_store_instr_stream_1 - lb a6, -6(a2) #end load_store_instr_stream_3 - sh a3, -428(s2) #end load_store_instr_stream_0 - la t0, region_1+1233 #start riscv_load_store_rand_instr_stream_8 - .4byte 0x00100073 # ebreak - lb s11, 174(t0) - lbu s0, 85(t0) - sub t6, a4, s11 - lb gp, 41(t0) - lb a0, -43(t0) - lbu zero, 82(t0) - lb s5, 135(t0) - or t1, t3, s0 - lb t4, 241(t0) - sb s9, 132(t0) - lbu gp, 16(t0) - c.nop - lbu t2, 34(t0) - mulhsu t2, s8, t2 - lb a1, -224(t0) - lhu a0, 81(t0) - sb a0, -219(t0) - lbu a2, 20(t0) - csrrsi ra, 0x340, 28 - lw t3, 215(t0) - c.addi a6, -8 - c.srai a3, 29 - divu t5, s5, a1 - lb a2, -200(t0) - lb s2, 156(t0) - lb s5, 74(t0) - csrrsi s3, 0x340, 12 - lb a2, 140(t0) - add a2, t0, ra - lb a5, 32(t0) - xor a1, s6, t3 - csrrci s3, 0x340, 8 - lb a4, -114(t0) - c.nop - lh s10, -39(t0) - csrrs s3, 0x340, s9 - csrrw tp, 0x340, a1 - slti s7, s2, -284 - lbu a1, -192(t0) - lb s10, -252(t0) - sb ra, 168(t0) - .4byte 0x00100073 # ebreak - srl s1, tp, s7 - lbu s0, -228(t0) - c.li a7, -21 - lbu s0, 120(t0) - sb ra, -92(t0) #end riscv_load_store_rand_instr_stream_8 - addi s0, zero, -3 #init loop 1 counter - addi s11, zero, 14 #init loop 1 limit -sub_1_65_1_t: sltiu t4, t6, -852 - addi s0, s0, 6 #update loop 1 counter - c.lui s3, 21 - addi a3, zero, 9 #init loop 0 counter - addi s2, zero, 4 #init loop 0 limit - mulh t3, a7, s7 -sub_1_65_0_t: csrrsi s6, 0x340, 18 - addi a3, a3, -1 #update loop 0 counter - nop - bgeu a3, s2, sub_1_65_0_t #branch for loop 0 - bltu s0, s11, sub_1_65_1_t #branch for loop 1 - mulh t0, gp, a1 - la t3, region_1+3038 #start load_store_instr_stream_1 - sb s6, -29(t3) - la a2, region_2+6888 #start load_store_instr_stream_2 - lbu s1, -13(a2) - la a1, region_0+3420 #start load_store_instr_stream_0 - lbu s5, -15(a2) - lhu ra, -28(t3) - lb t2, 3(a2) - sh ra, 14(a2) - sb a5, -133(a1) - sh a5, -100(a1) - lbu tp, -8(a2) - lhu s4, -8(t3) - lb s11, 235(a1) - sb a2, -65(t3) - sh a6, -16(a2) - lh a5, -4(a1) - lb s4, -10(a2) #end load_store_instr_stream_2 - sb a6, -6(t3) - sb a1, 139(a1) - lh a3, -60(t3) - lhu s11, -182(t3) - lbu a3, 145(a1) - sh s10, 202(a1) - sh s10, 242(a1) - lbu a6, -167(a1) - sb s3, 57(t3) #end load_store_instr_stream_1 - sb t5, 180(a1) #end load_store_instr_stream_0 - la a6, region_2+6753 #start load_store_instr_stream_1 - la s0, region_2+5757 #start load_store_instr_stream_2 - lbu t0, 10(a6) - la s1, region_2+5604 #start load_store_instr_stream_0 - lh t4, -15(a6) - lh a2, -251(s0) - sb ra, -4(a6) - lb s5, 133(s1) - lbu ra, -381(s1) - lhu s7, 1(a6) - sb s1, 126(s0) - lbu t1, -686(s0) - lb s10, -74(s0) - lbu s3, -779(s1) - lb t5, -9(a6) - sw a1, 416(s1) - lh t5, -5(a6) #end load_store_instr_stream_1 - sb t0, 920(s1) - lbu t4, -858(s0) - sb a3, 199(s1) - lw t5, -44(s1) - sw t3, 540(s1) - lbu ra, -938(s0) #end load_store_instr_stream_2 - lbu a5, -258(s1) #end load_store_instr_stream_0 - la a1, region_4+845 #start riscv_load_store_rand_instr_stream_0 - c.add a4, t3 - c.li s4, 24 - lhu a3, 43(a1) - csrrw zero, 0x340, a6 - csrrs s2, 0x340, a4 - c.srli a0, 3 - csrrsi s11, 0x340, 17 - c.addi s6, -20 - lh t6, -45(a1) - xori t5, a1, 318 - slli s0, t0, 22 - mulhu tp, s10, t3 - lui tp, 922128 - lbu s1, 45(a1) - sh t1, -35(a1) - csrrs a0, 0x340, a3 - c.addi s5, -30 - sb s10, 43(a1) - c.andi a4, -21 - lh a0, -43(a1) - xori tp, a7, 9 - slti t3, t2, 760 - addi s1, tp, -462 - mulhu zero, s3, s9 - remu s11, s9, t5 - csrrwi tp, 0x340, 16 - c.or a5, a1 - csrrc s4, 0x340, t6 - auipc t5, 862105 - and a0, ra, zero - .4byte 0x00100073 # ebreak - lh s1, -15(a1) - sb a1, 20(a1) - lb a7, -20(a1) - mulhsu a7, zero, s7 - divu s5, s2, s9 - or s10, t4, a6 - c.addi a7, -1 - srli s3, t5, 25 - lb t2, 61(a1) #end riscv_load_store_rand_instr_stream_0 -sub_1_22: jal gp, 1f -0: c.j 26f -1: c.jal 21f -2: c.jal 27f -3: c.j 23f -4: jal ra, 12f -5: c.j 29f -6: jal ra, 7f -7: jal t1, 19f -8: c.j 24f -9: c.jal 15f -10: jal a4, 17f -11: jal ra, 8b -12: jal ra, 25f -13: c.j 2b -14: jal t3, 13b -15: c.j 4b -16: c.j 22f -17: jal tp, 9b -18: c.jal 0b -19: c.j 18b -20: jal t6, 5b -21: jal t1, 10b -22: jal t0, 11b -23: jal ra, 16b -24: jal ra, 28f -25: c.j 14b -26: c.jal 20b -27: jal s2, 3b -28: c.jal 6b -29: c.srai a4, 29 - la s5, region_2+1454 #start load_store_instr_stream_3 - la t0, region_2+860 #start load_store_instr_stream_0 - sb t1, 15(s5) - la a0, region_2+7805 #start load_store_instr_stream_1 - sb ra, -13(s5) - la s0, region_2+4887 #start load_store_instr_stream_2 - lbu s7, 5(s5) - lb t6, 481(s0) - lbu a3, 3(t0) - sb s7, -16(a0) - lb s10, 6(a0) - sb s1, -9(s5) - sh a7, -6(s5) - lbu t3, 584(s0) - lbu a6, -13(a0) - lhu t4, 12(s5) - lhu t1, 63(a0) - lhu t2, -14(s5) - lb gp, -808(s0) - lhu gp, 419(s0) - sh a1, -6(t0) - lh a1, 29(a0) - lhu t5, 319(s0) - sb s5, -1012(s0) - sb s0, 6(t0) - lh tp, -10(s5) - sb a0, -494(s0) - lb s11, 442(s0) - lbu t6, -10(t0) - lbu a3, -10(s5) - lbu ra, -3(t0) - lbu t4, 48(a0) #end load_store_instr_stream_1 - lb gp, 852(s0) - lbu a1, 819(s0) #end load_store_instr_stream_2 - sb t1, 11(s5) #end load_store_instr_stream_3 - sb ra, 3(t0) #end load_store_instr_stream_0 - la gp, region_1+11720 #start load_store_instr_stream_1 - sb s10, 759(gp) - la s4, region_1+7872 #start load_store_instr_stream_4 - la s11, region_1+2767 #start load_store_instr_stream_0 - sb t4, 295(s4) - sb t1, 640(s4) - lhu s10, -776(gp) - lb zero, -411(gp) - la s1, region_1+6895 #start load_store_instr_stream_2 - la a4, region_1+10970 #start load_store_instr_stream_3 - lbu a6, 338(s4) - lhu ra, 13(s1) - lbu s0, -787(gp) - sb gp, 3(s1) - lb s7, -2(s1) - lb t3, 378(s4) - lh s3, 1(s1) - lb s5, 41(s4) - sb tp, 231(s11) - lb s7, -66(s11) - lbu t5, 763(s4) - lbu ra, -15(s1) - lbu t0, 219(a4) - lhu a3, -40(a4) - lbu s10, -127(gp) - lb a6, 806(gp) - lb zero, 0(s11) - sh s2, 336(gp) #end load_store_instr_stream_1 - lhu a3, -26(a4) - sb t6, -689(s4) - lb ra, -12(s1) - sb gp, 72(s11) - lhu t3, 44(a4) - lh s10, 15(s1) - lh t6, -60(a4) #end load_store_instr_stream_3 - lbu a6, -2(s1) #end load_store_instr_stream_2 - lb s5, 809(s4) #end load_store_instr_stream_4 - sb s2, -126(s11) #end load_store_instr_stream_0 - la tp, region_1+9603 #start riscv_hazard_instr_stream_10 - sh ra, 13(tp) - c.mv a6, t6 - auipc t5, 770602 - sb a1, 8(tp) - xor a6, a6, a1 - addi ra, a6, -881 - lbu ra, 13(tp) - lb t5, -5(tp) - or a1, a6, a1 - c.nop - sb ra, -8(tp) - ori a6, a2, 259 - lbu a1, 7(tp) - csrrwi a2, 0x340, 5 - slt a1, ra, ra - lbu a6, 14(tp) - srl t5, a6, a6 - lui t5, 526491 - sw t5, 5(tp) - mul a6, a1, a6 - sb a1, 7(tp) - sb a2, -8(tp) - srl a1, ra, t6 - divu a1, a1, a6 - lw a6, -11(tp) - slti t5, ra, 737 - c.slli ra, 10 - lb t5, -15(tp) - sb a1, -16(tp) - lb t5, -6(tp) - c.mv t6, a1 - lb a2, 2(tp) - lb ra, -1(tp) - xori t6, t6, -346 - csrrc t6, 0x340, a1 - srl ra, a2, ra - c.xor a1, a1 - lbu t6, 0(tp) - lbu a6, -13(tp) - xori a2, a1, 635 - sb a6, -14(tp) - lhu t6, -1(tp) - lh a1, -9(tp) - lb ra, -4(tp) - sb t5, -4(tp) - lbu a2, 8(tp) - mulhsu a2, a6, ra - and a1, a6, ra - lbu a6, -8(tp) - mulhsu t5, a1, a1 - csrrsi ra, 0x340, 29 - lhu a6, 3(tp) - sb ra, -12(tp) - sh ra, 15(tp) - mulhu t5, t5, a2 - lb a1, 10(tp) - nop - lb t5, -12(tp) #end riscv_hazard_instr_stream_10 - la gp, region_1+7888 #start load_store_instr_stream_0 - la a7, region_3+217 #start load_store_instr_stream_1 - lbu a0, 15(gp) - sb a5, -19(gp) - lb s11, 17(a7) - lbu zero, 201(gp) - lb s1, 26(a7) - sb s1, -91(gp) - sb t2, -5(gp) - lbu t3, -36(a7) - lbu s2, -11(a7) - lb t0, 49(a7) - lhu t2, 230(gp) - lbu a3, 121(gp) - lbu a6, 48(a7) - lh a6, 21(a7) - lbu tp, 181(gp) - lb ra, -30(a7) - lbu a3, -50(a7) #end load_store_instr_stream_1 - lbu t2, 197(gp) #end load_store_instr_stream_0 - la t3, region_2+1770 #start riscv_hazard_instr_stream_6 - c.add s0, s2 - mul zero, zero, s0 - lbu s10, -44(t3) - div a5, a5, a5 - lbu s10, 49(t3) - c.andi s0, -25 - nop - add s2, s10, s10 - lb s2, 33(t3) - sb a5, -2(t3) - sb a0, 9(t3) - lb a5, 12(t3) - sb s10, -9(t3) - lbu a0, -33(t3) - lui s2, 562367 - c.add s2, s0 - sb a5, -44(t3) - sb zero, -45(t3) - c.ebreak;c.nop; - lb s0, -14(t3) - lb a5, -43(t3) - c.and a0, a0 - c.srai a0, 7 - or s10, zero, a5 - c.andi a5, 16 - lb a0, -45(t3) - c.srai a0, 1 - andi a5, a5, 635 - lb a5, -13(t3) - c.sub s0, s0 - or a0, s0, zero - sb s10, 62(t3) - srl s10, s0, a5 - csrrwi s10, 0x340, 24 - and s10, s2, s0 - sh a5, -48(t3) - csrrs s0, 0x340, a5 - sb s10, 39(t3) - lbu s10, -61(t3) - c.nop - c.xor a5, a0 - lhu zero, -14(t3) - lbu a0, -15(t3) - lb s0, 41(t3) - lbu s10, -57(t3) #end riscv_hazard_instr_stream_6 - la t5, region_0+3923 #start load_store_instr_stream_3 - la tp, region_1+849 #start load_store_instr_stream_2 - la s11, region_2+2032 #start load_store_instr_stream_1 - sb a0, 799(s11) - la s2, region_4+2381 #start load_store_instr_stream_0 - lh gp, -552(s11) - lbu a6, 8(tp) - sb s8, -859(s11) - lh s6, -3(s2) - lh t3, -13(tp) - sb a4, 0(tp) - lb a7, -218(t5) - lbu s6, 6(tp) - lbu t1, -62(t5) - lbu t0, 52(t5) - sb s7, 676(s11) - lh a4, 5(tp) - lbu s0, -15(s2) - lh a7, -1(s2) - lbu s1, -125(t5) - lb t4, -14(tp) #end load_store_instr_stream_2 - lh a5, 286(s11) - sw s4, -9(s2) - lbu zero, -239(s11) - sw t4, -99(t5) - lhu s6, 204(s11) - lw zero, -75(t5) #end load_store_instr_stream_3 - lbu t0, 260(s11) #end load_store_instr_stream_1 - sb a3, -16(s2) #end load_store_instr_stream_0 - addi a2, zero, -3 #init loop 1 counter - csrrc t3, 0x340, s4 - addi zero, zero, 0 #init loop 1 limit - nop -sub_1_63_1_t: sltu a5, s0, a5 - csrrwi ra, 0x340, 24 - add a5, s3, s10 - c.srai a3, 11 - slli s3, tp, 8 - .4byte 0x00100073 # ebreak - sll a5, s9, t2 - addi a2, a2, 3 #update loop 1 counter - rem s7, ra, s6 - sub t5, a3, s9 - addi a4, zero, -7 #init loop 0 counter - addi t0, zero, -15 #init loop 0 limit -sub_1_63_0_t: add a7, s3, s9 - andi a3, s0, 248 - c.addi s10, -17 - ori s1, t4, 997 - addi a4, a4, -4 #update loop 0 counter - sra s2, t3, a0 - divu tp, a7, s3 - addi s10, s5, -343 - beq a4, t0, sub_1_63_0_t #branch for loop 0 - c.beqz a2, sub_1_63_1_t #branch for loop 1 - xor t4, tp, a4 -sub_1_19: jal gp, 9f -0: c.jal 1f -1: c.j 3f -2: jal tp, 4f -3: jal ra, 12f -4: jal ra, 10f -5: c.jal 13f -6: jal ra, 8f -7: jal s10, 14f -8: jal t1, 16f -9: jal s6, 0b -10: c.jal 7b -11: c.j 5b -12: c.j 2b -13: jal t3, 6b -14: jal gp, 15f -15: c.jal 11b -16: csrrsi t0, 0x340, 26 - la t6, region_1+15071 #start riscv_load_store_rand_instr_stream_6 - srl zero, sp, s3 - c.mv s4, s8 - lb s1, -14(t6) - lb a6, -12(t6) - c.or a0, a5 - lbu t2, -8(t6) - csrrci t3, 0x340, 17 - sb a2, 6(t6) - rem zero, s3, tp - remu zero, a3, s8 - lui s7, 491023 - sw t0, -15(t6) - csrrc s4, 0x340, s11 - csrrs s3, 0x340, a2 - c.nop - lb s10, -10(t6) - lb t5, 14(t6) - c.andi s0, -30 - lb s7, 6(t6) - c.addi a4, -31 - lbu a3, -10(t6) - sb a3, -2(t6) - lb s5, 5(t6) - lb t5, -10(t6) - nop - c.nop - csrrwi s5, 0x340, 4 - and t5, t4, a4 - add s10, t0, t2 - lb a1, 16(t6) - sltiu s0, t6, 900 - slti a3, t2, -450 - c.xor a0, a5 - slli tp, t5, 21 - mulh s10, s11, t4 - div a4, a3, a2 - c.mv ra, t2 - sh ra, 3(t6) - sb gp, -10(t6) #end riscv_load_store_rand_instr_stream_6 - la s5, region_2+6577 #start riscv_hazard_instr_stream_3 - mulhsu a7, gp, s4 - sll a3, a5, s2 - lh s4, -223(s5) - c.mv a7, a7 - lw s4, 187(s5) - c.srli a3, 31 - sb s2, -71(s5) - sh a3, -49(s5) - addi s2, s2, 1002 - c.add a3, a3 - lbu gp, 176(s5) - ori a5, a7, 795 - lw a5, -125(s5) - ori a7, a5, 361 - or gp, a5, s2 - slti a7, s2, -250 - lbu gp, 154(s5) - lbu s4, 72(s5) - addi s4, gp, -228 - lbu a7, 167(s5) - sub gp, s2, gp - csrrw gp, 0x340, s2 - c.add a3, a3 - add s2, a7, s2 - csrrwi a5, 0x340, 14 - .4byte 0x00100073 # ebreak - lbu s2, -26(s5) - sb a5, -24(s5) - sh a7, -79(s5) - c.li a3, -11 - lbu a5, 192(s5) - sh a7, 107(s5) - nop - mulhu gp, s4, a7 - sh gp, 29(s5) - csrrc s2, 0x340, s4 - sw s2, 227(s5) - c.addi a5, 20 - csrrc a5, 0x340, gp - lbu s2, -20(s5) #end riscv_hazard_instr_stream_3 - la s5, region_3+397 #start riscv_load_store_rand_instr_stream_7 - sltiu s0, s4, 422 - c.add s10, s6 - lbu s11, 57(s5) - srli s2, s4, 18 - nop - lbu a5, -101(s5) - lh s7, -43(s5) - lh t3, -5(s5) - sb t2, -318(s5) - lw s0, -137(s5) - sra s7, t0, s10 - csrrs s10, 0x340, a7 - nop - sb tp, -356(s5) - lhu s4, 3(s5) - sb s3, -163(s5) - sw a1, -97(s5) - sw ra, 59(s5) - lbu t6, -290(s5) - sltiu t4, t3, 212 - lui t3, 532802 - and t0, sp, s10 - lhu zero, -187(s5) - sh tp, -207(s5) - sltiu ra, gp, 181 - lb gp, -52(s5) - lbu t0, -355(s5) - lh s2, -381(s5) - sb a2, -342(s5) - lb gp, -6(s5) - div a0, t2, s4 - add s4, a3, t2 - lh t3, -291(s5) - sb s1, -372(s5) - lhu s3, -283(s5) - sh t2, 81(s5) - lbu t6, -12(s5) - sh s6, -331(s5) - lb t3, -219(s5) - lb a4, -240(s5) #end riscv_load_store_rand_instr_stream_7 - addi ra, zero, 7 #init loop 0 counter - c.ebreak;c.nop; - c.slli a1, 25 - addi a7, zero, 2 #init loop 0 limit -sub_1_56_0_t: mulhu a2, a6, a3 - sub t6, a6, a7 - c.srai s0, 18 - addi ra, ra, -1 #update loop 0 counter - c.li t2, 11 - c.srli s1, 6 - bgeu ra, a7, sub_1_56_0_t #branch for loop 0 - ori a0, t1, 325 - la s5, region_2+2314 #start riscv_load_store_rand_instr_stream_11 - remu t2, a6, s7 - sb a4, -59(s5) - lbu a7, -16(s5) - lh t0, -52(s5) - lui a0, 1017564 - srli s4, s9, 21 - sh t6, -36(s5) - andi gp, t6, 152 - c.nop - slti a6, a0, 384 - mul a6, t1, t1 - csrrc gp, 0x340, gp - srl a5, s4, ra - xor t1, t3, s4 - auipc s2, 1014333 - sb t3, 16(s5) - sb a1, -39(s5) - lbu s11, 12(s5) - or a4, a7, sp - srl a7, t2, s3 - sb t3, 49(s5) - lb a7, 58(s5) - lb a3, 15(s5) - lui t4, 144595 - srai tp, s5, 25 - lhu s1, 38(s5) - lhu s4, -34(s5) - lb t1, 34(s5) - lhu s11, 46(s5) - c.srai s1, 1 - lb a0, -40(s5) - sh t0, -32(s5) - sb s0, 50(s5) - c.xor a3, s0 - c.nop - sb sp, 52(s5) - c.slli tp, 14 - lhu t5, 22(s5) - sb s8, 5(s5) #end riscv_load_store_rand_instr_stream_11 - la t1, region_2+7749 #start load_store_instr_stream_1 - la a4, region_2+641 #start load_store_instr_stream_0 - lb s7, 6(a4) - lbu a0, 13(a4) - lhu t6, -15(a4) - lh s11, -11(t1) - lb s11, -56(t1) - lb tp, 16(a4) - lh s0, -13(a4) - sh ra, -13(t1) - lbu t5, 3(a4) - sh tp, 55(t1) - lb a0, 1(a4) - lhu t0, 3(t1) #end load_store_instr_stream_1 - lbu a2, -12(a4) - sb ra, 8(a4) #end load_store_instr_stream_0 - la s11, region_3+495 #start load_store_instr_stream_3 - la s3, region_3+395 #start load_store_instr_stream_1 - la a1, region_3+162 #start load_store_instr_stream_4 - lbu a0, -62(s11) - sb t6, -11(a1) - sb s10, -36(s11) - lb s7, -54(s11) - la t1, region_3+16 #start load_store_instr_stream_0 - sb s10, -52(s11) - la t2, region_3+96 #start load_store_instr_stream_2 - sb t3, -7(a1) - lb gp, -24(t2) - sh a2, 113(s3) - lb gp, 71(t1) - lw a3, -63(s11) - lb a7, -255(s3) - lb a6, -316(s3) - lbu a5, 12(t2) - lhu tp, 148(t1) - sb s4, -18(s11) - sh a7, 6(a1) - sb s0, -105(s3) - sb s3, -11(a1) - lb t3, 13(a1) - lh s10, -15(s3) - sh s8, -46(t2) - lb a6, 127(t1) - lbu s6, 31(t2) - sb ra, 102(s3) - lbu a6, -19(t2) #end load_store_instr_stream_2 - sh t0, -53(s3) #end load_store_instr_stream_1 - lbu a2, 13(a1) - lw zero, 2(a1) - lb a3, -58(s11) #end load_store_instr_stream_3 - sw s6, 14(a1) #end load_store_instr_stream_4 - sb a4, -13(t1) - lhu t4, 128(t1) #end load_store_instr_stream_0 -sub_1_21: jal gp, 13f -0: c.jal 5f -1: jal ra, 24f -2: jal ra, 12f -3: c.j 17f -4: jal ra, 1b -5: jal t1, 3b -6: jal t1, 19f -7: c.j 4b -8: c.jal 15f -9: c.j 10f -10: c.jal 0b -11: jal ra, 16f -12: c.jal 26f -13: jal t1, 21f -14: jal ra, 2b -15: c.j 9b -16: c.jal 14b -17: jal t6, 18f -18: jal ra, 6b -19: c.j 25f -20: c.j 22f -21: jal ra, 20b -22: c.jal 23f -23: jal a2, 7b -24: c.jal 8b -25: c.jal 11b -26: mulhu a6, ra, sp -sub_1_20: jal gp, 16f -0: jal ra, 6f -1: jal ra, 17f -2: c.j 14f -3: c.jal 11f -4: c.jal 21f -5: jal t3, 8f -6: c.j 1b -7: jal ra, 10f -8: jal a1, 3b -9: c.j 23f -10: c.jal 9b -11: c.j 22f -12: c.j 13f -13: c.j 18f -14: c.jal 4b -15: c.jal 5b -16: jal t6, 19f -17: c.jal 28f -18: jal ra, 24f -19: c.jal 26f -20: jal ra, 7b -21: c.j 12b -22: c.j 25f -23: jal t1, 0b -24: jal a2, 27f -25: c.j 2b -26: jal t1, 15b -27: c.j 20b -28: andi t0, s3, 825 - addi a2, zero, 6 #init loop 1 counter - addi zero, zero, 0 #init loop 1 limit - sltiu s4, s2, -272 - andi s2, t3, -781 -sub_1_58_1_t: c.slli t6, 9 - ori t5, t1, 994 - addi a2, a2, -3 #update loop 1 counter - c.slli s3, 7 - add a1, t3, t5 - addi a0, zero, 5 #init loop 0 counter - srli s11, t4, 26 - addi t0, zero, 15 #init loop 0 limit -sub_1_58_0_t: divu s11, s6, s4 - c.or s1, a1 - addi a0, a0, 1 #update loop 0 counter - bltu a0, t0, sub_1_58_0_t #branch for loop 0 - remu s2, s11, s5 - sltiu s5, s1, 368 - c.bnez a2, sub_1_58_1_t #branch for loop 1 - mulhsu t5, a4, zero -sub_1_18: jal gp, 13f -0: c.j 2f -1: c.j 14f -2: jal t1, 5f -3: c.j 17f -4: c.j 11f -5: jal ra, 10f -6: jal t1, 9f -7: c.jal 15f -8: jal t1, 12f -9: jal ra, 16f -10: jal t0, 7b -11: c.j 1b -12: c.j 3b -13: c.jal 0b -14: c.jal 6b -15: c.jal 4b -16: jal s6, 8b -17: srai s3, s2, 11 - la s6, region_4+390 #start load_store_instr_stream_1 - sb t1, 821(s6) - la a6, region_1+11209 #start load_store_instr_stream_2 - la s5, region_0+1111 #start load_store_instr_stream_3 - lb t1, -24(a6) - lh s7, 972(s6) - sb t0, -22(s5) - sb tp, 242(s5) - lbu t4, -178(s5) - la a1, region_2+5854 #start load_store_instr_stream_0 - sh s11, 141(s5) - lbu t3, -24(a6) - lb t0, 303(s6) - lbu s1, 847(a1) - sh s4, -538(s6) - lb ra, 89(s5) - sb ra, 56(a6) - lb t0, -241(s5) - lhu a3, -926(a1) - sb s9, -118(a1) - lh a7, 930(s6) - sb s6, 63(s5) - sh t2, -58(a1) - sb a4, -224(s6) #end load_store_instr_stream_1 - sb zero, -211(a1) - lh s10, -1(a6) - lb s0, -203(s5) - sb ra, 343(a1) - lbu s0, 18(s5) - sh sp, -21(a6) #end load_store_instr_stream_2 - sw s7, 69(s5) #end load_store_instr_stream_3 - lh s3, -10(a1) #end load_store_instr_stream_0 - la t4, region_2+1405 #start riscv_hazard_instr_stream_2 - sb a2, 2(t4) - srli s6, ra, 13 - sb t2, -15(t4) - addi t2, a2, 664 - csrrs a3, 0x340, a2 - mul gp, gp, gp - sb ra, 13(t4) - sb t2, 10(t4) - mulhsu s6, t2, ra - sb gp, -4(t4) - ori a3, ra, -289 - srli s6, gp, 31 - c.or a3, a2 - c.sub a3, a3 - mulh ra, ra, gp - lbu s6, 16(t4) - sh a3, -7(t4) - lbu ra, 0(t4) - lbu t2, 5(t4) - lh ra, -3(t4) - lb t2, 0(t4) - sh a3, -11(t4) - addi a3, t2, -728 - sb s6, 6(t4) - mulh t2, ra, a2 - c.srli a2, 16 - sltiu t2, a3, 725 - c.srli a2, 12 - lbu gp, -14(t4) - c.nop - xori gp, gp, -539 - lbu ra, 15(t4) - slti t2, a3, -210 - sb a2, -12(t4) - lui t2, 1010440 - c.lui s6, 8 - sb t2, 14(t4) #end riscv_hazard_instr_stream_2 -sub_1_27: jal gp, 9f -0: jal t1, 6f -1: jal t1, 7f -2: c.j 4f -3: c.jal 2b -4: jal ra, 13f -5: c.j 12f -6: c.jal 10f -7: c.jal 3b -8: jal t1, 1b -9: c.jal 8b -10: jal t5, 5b -11: jal s3, 0b -12: c.jal 14f -13: c.j 11b -14: mulh s11, a0, s10 - la s7, region_2+4022 #start riscv_hazard_instr_stream_0 - c.srli a0, 22 - rem a4, tp, a4 - mulh a4, s10, t5 - lui a0, 403989 - mulh a0, t5, a6 - mulhsu s10, a4, t5 - sh tp, 12(s7) - auipc tp, 6010 - c.or a4, a0 - c.li s10, -31 - srai t5, a0, 29 - divu a0, tp, s10 - sb t5, -4(s7) - csrrs a4, 0x340, tp - rem a6, tp, a0 - sb s10, -3(s7) - lbu t5, -11(s7) - lui a0, 550487 - slli s10, a6, 14 - lbu a0, -3(s7) - sltiu tp, a0, -900 - lbu a6, 14(s7) - c.ebreak;c.nop; - slt t5, a6, t5 - srl a4, a4, tp - csrrsi t5, 0x340, 28 - divu a6, a0, s10 - mulhu a0, a4, t5 - add a4, t5, a0 - lbu a0, 11(s7) - sb a6, 3(s7) - c.slli tp, 10 - sltu a0, a6, t5 - sb s10, 4(s7) - sb t5, 13(s7) - c.nop - mul a4, t5, s10 - slti a4, a0, 836 - sltu tp, s10, tp - .4byte 0x00100073 # ebreak - sh s10, 6(s7) #end riscv_hazard_instr_stream_0 - la a3, region_2+5062 #start load_store_instr_stream_1 - la a0, region_4+2126 #start load_store_instr_stream_0 - lhu s6, -100(a3) - la s10, region_0+3396 #start load_store_instr_stream_2 - sh s10, 488(a0) - lb gp, 11(s10) - lh a5, -180(a3) - lh a1, -288(a0) - lb s2, -6(s10) - sb s1, -690(a0) - lb a4, 15(s10) - lbu zero, 155(a3) - sb a0, -203(a0) - lbu a7, -5(s10) - lw a7, 8(s10) - lhu s11, 380(a0) - lbu s1, -4(a3) - lbu s5, 190(a3) - lbu t1, -577(a0) - sb t2, -13(s10) #end load_store_instr_stream_2 - lh s1, 104(a3) - lbu tp, -231(a3) - lbu a7, 699(a0) - sh s8, 60(a3) - lbu zero, 296(a0) - lb s0, 92(a3) #end load_store_instr_stream_1 - lbu s1, -775(a0) #end load_store_instr_stream_0 - addi a6, zero, 8 #init loop 0 counter - div s7, s0, t2 - c.lui gp, 26 - addi t0, zero, -12 #init loop 0 limit - c.ebreak;c.nop; - csrrc s11, 0x340, s10 -sub_1_57_0_t: auipc tp, 914809 - addi a6, a6, -10 #update loop 0 counter - c.addi a0, -24 - beq a6, t0, sub_1_57_0_t #branch for loop 0 - sll s0, s0, a2 - la s0, region_3+266 #start riscv_load_store_rand_instr_stream_4 - sb s6, 125(s0) - sb t1, -171(s0) - lui s3, 83688 - c.mv t5, a6 - lh s11, -16(s0) - sra ra, t6, s10 - sh ra, -136(s0) - lbu a0, 29(s0) - lb t0, -132(s0) - rem ra, a1, t1 - c.or a1, a2 - sh t4, -100(s0) - lh a6, -80(s0) - sub gp, tp, a1 - c.and a0, a4 - lb a2, -246(s0) - c.mv ra, t4 - sltu t0, a7, s3 - lbu t0, -212(s0) - lb ra, -205(s0) - lbu ra, 127(s0) - lb zero, 222(s0) - sb t3, -213(s0) - sra a5, t3, t3 - sb a6, -169(s0) - c.ebreak;c.nop; - lbu t1, 62(s0) - sh sp, 126(s0) - sra t2, zero, ra - sb s11, -154(s0) - c.and a0, a2 - sb t5, 34(s0) - lbu s7, -96(s0) - sltiu a2, t4, -159 - .4byte 0x00100073 # ebreak - csrrw a0, 0x340, t3 - c.srli a2, 18 - sltiu t6, a2, -478 - auipc s4, 941036 - sb t0, 229(s0) - c.sub a1, s0 - sh s7, 60(s0) - or s10, sp, sp - c.and a3, a0 - lui s4, 880231 - lbu ra, 91(s0) #end riscv_load_store_rand_instr_stream_4 - la s5, region_3+499 #start load_store_instr_stream_0 - sb gp, -43(s5) - la a5, region_3+373 #start load_store_instr_stream_1 - sb s0, 10(s5) - lb s7, -16(a5) - lbu ra, -14(a5) - lh s0, -51(s5) - lbu t1, -40(a5) - sb t1, 8(s5) - lbu gp, 0(s5) - sw zero, 3(a5) - sb s6, -32(s5) - lbu s2, 16(a5) - lbu t6, -30(s5) - lb s10, -54(s5) - sb sp, 32(a5) - sh a2, -29(s5) - sb a3, -45(a5) - lbu a2, -41(a5) #end load_store_instr_stream_1 - lbu s4, -33(s5) #end load_store_instr_stream_0 - la t6, region_4+3031 #start riscv_load_store_rand_instr_stream_1 - c.ebreak;c.nop; - srai s5, s8, 18 - c.add t0, t4 - remu s1, t5, s4 - lbu a1, 14(t6) - sltu gp, a4, a2 - csrrsi t0, 0x340, 20 - c.srai a0, 1 - csrrw s6, 0x340, t1 - sltiu s11, s2, 207 - sltu s4, s9, s3 - sb t6, 4(t6) - remu s2, s10, s0 - lb a1, 0(t6) - lbu s0, 3(t6) - c.li a7, 18 - c.add t5, t6 - lbu s0, 9(t6) - xori s0, zero, -496 - c.and a2, a2 - sltu s10, t1, gp - csrrci s4, 0x340, 15 - lbu a6, -10(t6) - lhu a5, -5(t6) - c.or s1, a5 - srli t4, t1, 13 - sb s2, -15(t6) - sh t6, 5(t6) - divu a0, t2, s5 - sb a4, 6(t6) - ori a0, t4, 539 - sb gp, -10(t6) - c.mv a1, t1 - lb s2, 0(t6) - sb s6, -10(t6) #end riscv_load_store_rand_instr_stream_1 - addi s5, zero, 3 #init loop 0 counter - addi tp, zero, -14 #init loop 0 limit - xor a2, t3, s0 - c.andi a0, -17 - and t0, t5, a7 - mulhu a5, t0, s7 -sub_1_60_0_t: divu s1, a4, a6 - csrrsi s1, 0x340, 7 - csrrc a1, 0x340, a1 - ori s11, ra, -91 - lui t4, 929648 - addi s5, s5, -1 #update loop 0 counter - c.srai a0, 21 - c.addi a4, -20 - c.srai a1, 4 - bne s5, tp, sub_1_60_0_t #branch for loop 0 - mulhsu t0, zero, a1 - la s11, region_4+1594 #start riscv_hazard_instr_stream_13 - lb t4, -11(s11) - sb t4, 8(s11) - sll a4, t4, a2 - lbu a4, 4(s11) - lb a4, 8(s11) - lb s4, 11(s11) - csrrci a2, 0x340, 28 - c.slli a6, 20 - lb a4, -8(s11) - lbu a4, -7(s11) - andi a6, a4, -633 - lbu t4, 10(s11) - lbu s4, 15(s11) - c.srli s1, 14 - c.sub a4, a2 - c.slli s1, 4 - slt t4, a4, t4 - srai a2, a4, 9 - lbu a4, 16(s11) - lbu a4, 4(s11) - csrrc a4, 0x340, s4 - lbu s1, 12(s11) - sb a2, -9(s11) - lb t4, 3(s11) - c.xor a2, a2 - add t4, s4, a4 - lbu s1, 4(s11) - xor t4, t4, t4 - sb a4, -15(s11) - xori a6, s4, 192 - lb a4, 7(s11) - csrrci a2, 0x340, 29 - sb s1, -11(s11) - c.sub a2, a2 - srl t4, s1, s1 - sb a2, 16(s11) - sh a6, -4(s11) - sub s1, a4, s4 - mulhsu a6, a2, s4 - lbu a2, 2(s11) - lbu a6, -4(s11) - mul t4, a6, s4 - sra a4, s1, a6 - lb a4, 1(s11) - lbu a6, 5(s11) - c.srai a4, 3 - csrrci a4, 0x340, 24 - div t4, a6, a4 - lbu a2, -9(s11) - lb a6, -15(s11) - lb t4, -1(s11) - lbu a6, -9(s11) #end riscv_hazard_instr_stream_13 - la t4, region_2+2029 #start riscv_load_store_rand_instr_stream_5 - c.and s0, s1 - c.or a1, a4 - c.li t0, 9 - .4byte 0x00100073 # ebreak - lbu s5, 14(t4) - sb s11, -8(t4) - sll tp, a5, s3 - lb t5, -6(t4) - sh t2, -15(t4) - csrrci s0, 0x340, 13 - c.mv a1, s10 - mulh zero, gp, t2 - sltu a1, ra, a6 - lbu t2, -14(t4) - lb s2, 15(t4) - c.and s0, a1 - addi t0, a6, -704 - sb a2, -12(t4) - lbu t3, -15(t4) - lb a0, -7(t4) - sb a0, 10(t4) - c.srai a4, 8 - xor tp, s5, t1 - div zero, a5, s2 - sra t5, a1, s8 - .4byte 0x00100073 # ebreak - lb tp, 6(t4) - nop - lw t1, 11(t4) #end riscv_load_store_rand_instr_stream_5 - la s2, region_4+1009 #start riscv_load_store_rand_instr_stream_13 - lh a6, -35(s2) - sh a3, -169(s2) - slt tp, a4, a1 - lbu t5, -114(s2) - c.ebreak;c.nop; - c.and a4, a4 - c.andi s1, -23 - sb s3, -79(s2) - lbu a4, 67(s2) - csrrci tp, 0x340, 30 - c.srai s1, 18 - nop - div a5, s10, t1 - lb a6, 68(s2) - sb sp, -236(s2) - andi a1, t1, -14 - c.and s0, a2 - c.and s0, a1 - c.mv s11, a2 - slt ra, s8, s7 - lui t5, 204334 - auipc a6, 679306 - sw tp, 83(s2) - lhu a3, 225(s2) - slt t2, t5, t1 - lbu s6, 64(s2) - lb a7, -156(s2) - sh s3, -23(s2) #end riscv_load_store_rand_instr_stream_13 - la gp, region_3+229 #start riscv_hazard_instr_stream_12 - sltiu a1, zero, -52 - mulhu zero, zero, a1 - lbu a4, 9(gp) - sb a1, -10(gp) - sltiu a1, a4, -193 - sb s6, 2(gp) - mulhu a4, zero, zero - lhu t3, 13(gp) - mulh a1, t0, s6 - lbu zero, 16(gp) - c.srai a4, 30 - slti zero, s6, -646 - lb s6, 16(gp) - lb a1, -6(gp) - lb a1, 7(gp) - mulhsu t3, zero, t3 - rem zero, t0, t0 - sh a1, 1(gp) - slti a4, a4, -977 - sh t0, -1(gp) - lh zero, 13(gp) - lbu t3, -2(gp) - csrrs zero, 0x340, zero - .4byte 0x00100073 # ebreak - sll a4, zero, t3 - sb t0, -14(gp) - csrrs a4, 0x340, s6 - lh a4, 9(gp) - csrrci t3, 0x340, 11 - sb t3, 16(gp) - c.or a4, a1 - sll t0, t0, t3 - lbu t0, -10(gp) #end riscv_hazard_instr_stream_12 - la s0, region_2+4373 #start load_store_instr_stream_1 - la a7, region_1+8046 #start load_store_instr_stream_0 - lbu s3, 4(s0) - sb s7, -14(s0) - lb a2, -14(s0) - sb s3, 807(a7) - sb t0, -14(s0) - lbu t0, -491(a7) - sh t1, -11(s0) - sb s9, 1003(a7) - lb s7, 14(s0) - lb t3, 169(a7) - lb t4, -13(s0) #end load_store_instr_stream_1 - lhu t6, 748(a7) - sb t1, -759(a7) - sw s10, -362(a7) #end load_store_instr_stream_0 -sub_1_25: jal gp, 3f -0: jal t1, 7f -1: c.jal 4f -2: jal ra, 9f -3: jal t1, 12f -4: jal a7, 11f -5: jal ra, 0b -6: jal t1, 1b -7: jal tp, 13f -8: jal ra, 10f -9: jal ra, 5b -10: c.jal 2b -11: c.jal 14f -12: jal a2, 8b -13: c.jal 6b -14: sll a3, s8, s7 -sub_1_26: jal gp, 13f -0: c.jal 25f -1: c.j 0b -2: jal t3, 12f -3: c.j 7f -4: jal tp, 16f -5: c.j 26f -6: jal ra, 2b -7: c.j 28f -8: jal ra, 18f -9: c.j 24f -10: jal t0, 23f -11: jal a0, 5b -12: c.j 20f -13: jal ra, 15f -14: c.jal 1b -15: c.jal 10b -16: c.jal 11b -17: c.jal 29f -18: c.j 6b -19: c.jal 4b -20: jal tp, 22f -21: c.jal 14b -22: jal ra, 3b -23: jal ra, 17b -24: c.j 19b -25: jal gp, 9b -26: jal t1, 8b -27: c.jal 30f -28: jal ra, 27b -29: jal t1, 21b -30: c.li tp, 19 - la s1, region_0+1432 #start load_store_instr_stream_3 - la a2, region_0+75 #start load_store_instr_stream_1 - sb s4, -18(a2) - la t3, region_0+4064 #start load_store_instr_stream_4 - sb zero, 32(a2) - la s2, region_0+2944 #start load_store_instr_stream_0 - la t0, region_0+3745 #start load_store_instr_stream_2 - lbu a3, -43(t3) - lb ra, 13(t0) - lhu s4, -29(a2) - lbu t2, -25(a2) - lb s7, -981(s1) - lh s6, 19(a2) - sh tp, -58(t3) - lbu t1, -44(a2) - sb sp, -27(t3) - lh s5, -50(t3) - lb zero, 13(t0) - sw s1, -5(t0) - lw s7, 372(s1) - lbu a3, 769(s2) - lbu ra, -31(t3) - lb t6, -37(a2) - lb s6, -49(t3) - lb s3, -12(t0) - sw t4, -35(a2) #end load_store_instr_stream_1 - sh s1, -826(s1) - lh s3, -1(t0) - lb a3, -53(t3) #end load_store_instr_stream_4 - lb s5, -815(s2) - lbu s6, -12(t0) - sw t2, -604(s2) - sb t2, -227(s1) - lb s0, -848(s2) - lhu zero, 9(t0) #end load_store_instr_stream_2 - lbu s6, 71(s1) #end load_store_instr_stream_3 - sb gp, 115(s2) - lb ra, 25(s2) #end load_store_instr_stream_0 -sub_1_15: jal gp, 1f -0: jal ra, 3f -1: c.jal 7f -2: c.j 12f -3: c.j 5f -4: jal ra, 2b -5: c.j 8f -6: jal ra, 9f -7: jal t1, 0b -8: c.j 11f -9: jal t0, 4b -10: c.jal 6b -11: jal ra, 10b -12: rem gp, tp, s11 - la s0, region_2+7136 #start load_store_instr_stream_1 - la t2, region_2+820 #start load_store_instr_stream_2 - la t3, region_2+2452 #start load_store_instr_stream_3 - la s10, region_2+4840 #start load_store_instr_stream_0 - lbu t1, 13(s10) - sb t1, 229(t2) - lbu s1, -6(t3) - sb a2, -7(s0) - sb a2, 3(s0) - lbu s6, 59(t2) - sb s2, -13(s10) - sb s0, 219(t2) - lb s3, 10(t3) - lb s1, 19(s0) - sb s3, 45(t2) - sb ra, -9(t3) - lb s2, -63(s0) - lb t4, 2(s10) - sb t5, 7(s10) - sb a4, 196(t2) - sw s6, 120(t2) - lbu t4, 7(s10) - sb t4, -13(t3) - lb a4, -3(t3) - lbu t6, 7(s10) - lbu gp, -30(s0) #end load_store_instr_stream_1 - lbu s11, 13(t3) - lbu tp, 7(t3) #end load_store_instr_stream_3 - lb gp, -15(t2) #end load_store_instr_stream_2 - sb a1, -16(s10) #end load_store_instr_stream_0 - la a2, region_3+385 #start riscv_load_store_rand_instr_stream_9 - lhu s2, -235(a2) - sb s2, 97(a2) - lb tp, 12(a2) - lbu s0, -178(a2) - add a4, s10, a0 - c.li s7, -17 - sw s10, -17(a2) - lh t0, -1(a2) - lb a0, -128(a2) - lbu s10, -238(a2) - csrrsi t6, 0x340, 3 - srai t6, t6, 14 - auipc a4, 319034 - sb a1, -37(a2) - and t3, t4, a7 - lh t3, -55(a2) - csrrsi a3, 0x340, 17 - lb t6, -104(a2) - mulhu s3, ra, a5 - c.add s2, s11 - lb tp, 57(a2) - c.nop - andi t3, s4, -962 - rem a7, a2, a2 - or s6, a1, ra - lb a6, 30(a2) - sb s10, -107(a2) - add s0, t4, s5 - mulhu s4, s3, s6 - lb zero, -164(a2) - sb zero, -105(a2) - sh s2, -39(a2) - lb tp, 58(a2) - sll s7, a0, t0 - sb t4, -213(a2) - lh t4, -63(a2) - c.sub a4, a1 - lh t1, -125(a2) - c.lui a6, 17 - lb a0, -116(a2) - lw s7, -97(a2) #end riscv_load_store_rand_instr_stream_9 - la a4, region_0+1688 #start riscv_hazard_instr_stream_8 - lhu t5, 10(a4) - c.and a3, a3 - lbu t1, 1(a4) - mulhsu t1, a5, t1 - mul a3, t5, a5 - lw s1, 16(a4) - lw a5, 12(a4) - auipc a1, 159560 - csrrs a1, 0x340, a1 - c.add t5, a1 - lbu t1, 16(a4) - c.andi a3, -32 - sw t5, 16(a4) - .4byte 0x00100073 # ebreak - c.xor s1, a5 - ori a3, t5, 431 - sh a5, 16(a4) - sw a3, 8(a4) - lhu a5, -4(a4) - lbu s1, 14(a4) #end riscv_hazard_instr_stream_8 - la a4, region_0+1030 #start riscv_load_store_rand_instr_stream_12 - sb s10, 183(a4) - csrrci tp, 0x340, 23 - c.nop - sb a5, -56(a4) - c.or a2, a5 - lbu a2, 919(a4) - lhu s0, 140(a4) - sb t2, 727(a4) - sb s2, -147(a4) - c.sub s0, s1 - or a2, s10, s2 - lbu s10, -565(a4) - sb s3, -485(a4) - xori t4, a6, -72 - csrrwi gp, 0x340, 27 - lh s7, 608(a4) - lh t4, -284(a4) - add a7, gp, s11 - srli s7, s2, 16 - c.mv t5, a0 - c.srai a5, 10 - nop - lh zero, -990(a4) - sb t2, 945(a4) - sh a0, -214(a4) - sb s11, 596(a4) - csrrsi zero, 0x340, 7 - c.slli t1, 29 - srai s11, s3, 21 - sh zero, 526(a4) - sltu zero, tp, a6 - lb s7, -466(a4) - sb s8, -663(a4) - lb s3, -337(a4) - mulh t6, a2, a1 - sll s6, tp, t2 - sll s4, s8, s11 - c.and a0, s0 - mulh ra, gp, sp - csrrc t6, 0x340, s0 - c.xor a0, a5 - lb gp, -40(a4) - lb a6, -973(a4) - lw s11, -138(a4) - lb ra, -494(a4) - csrrwi a2, 0x340, 22 - lw t0, 562(a4) - srli s6, a6, 9 - lw t2, -570(a4) #end riscv_load_store_rand_instr_stream_12 - addi a5, zero, 9 #init loop 0 counter - c.and a3, a0 - slli t1, a2, 0 - srai t3, s8, 12 - csrrci s4, 0x340, 24 - mulhu t5, s5, s6 - addi zero, zero, 0 #init loop 0 limit - mulh t0, s8, s1 - add t6, t2, a3 - c.srai s1, 30 -sub_1_59_0_t: divu a3, gp, s11 - mul s5, s8, t4 - c.nop - sltu a3, s10, t5 - c.srai a2, 19 - c.xor s0, a3 - mulhsu t1, gp, a1 - mulhu t0, a5, zero - andi t4, s11, -446 - remu s4, a6, a2 - addi a5, a5, -3 #update loop 0 counter - c.beqz a5, sub_1_59_0_t #branch for loop 0 - csrrw s7, 0x340, a3 - la s3, region_2+3133 #start riscv_hazard_instr_stream_7 - mulh t2, s6, a7 - lb a7, 684(s3) - csrrsi s6, 0x340, 19 - sb s6, -327(s3) - lbu s1, 562(s3) - andi s1, a7, 871 - c.srli s1, 15 - lh s1, -523(s3) - sub s6, t2, s1 - lb s6, -411(s3) - lui t2, 197641 - srl a0, s6, a0 - xor a0, s1, t6 - slli a0, s1, 23 - csrrw t6, 0x340, t2 - lbu a0, -481(s3) - csrrsi t2, 0x340, 31 - sb s6, 763(s3) - sb t2, 948(s3) - sltu s1, s6, t2 - slti a7, a7, -269 - sh a0, 213(s3) - sh s1, 369(s3) - lui a7, 536346 - lbu a0, 392(s3) - lh t6, -887(s3) #end riscv_hazard_instr_stream_7 -sub_1_24: jal gp, 9f -0: c.j 12f -1: jal gp, 5f -2: jal ra, 19f -3: jal ra, 17f -4: jal s10, 2b -5: c.j 16f -6: c.j 11f -7: c.j 21f -8: jal ra, 14f -9: jal a0, 1b -10: jal ra, 3b -11: c.jal 10b -12: jal ra, 7b -13: jal t3, 20f -14: jal ra, 4b -15: jal s2, 6b -16: c.j 15b -17: c.j 0b -18: jal ra, 22f -19: c.jal 18b -20: jal ra, 8b -21: jal t1, 13b -22: sub a2, a2, a0 - la a6, region_2+6974 #start riscv_load_store_rand_instr_stream_3 - sb t1, 435(a6) - and t2, t3, s8 - nop - mulh a0, t0, s0 - lb s5, 755(a6) - c.and a2, a3 - c.and a3, a0 - sb gp, -658(a6) - .4byte 0x00100073 # ebreak - lh t5, 886(a6) - divu s4, s7, t2 - nop - lbu tp, 505(a6) - sb s3, 274(a6) - mul s10, s5, s10 - sw s6, 154(a6) - c.andi a1, 19 - csrrsi t6, 0x340, 6 - csrrsi t2, 0x340, 6 - add t6, sp, a3 - slt s1, s1, a1 - andi gp, a1, -222 - csrrc a4, 0x340, s9 - sb a0, 779(a6) - lh zero, 844(a6) - lb s10, 475(a6) - csrrw s4, 0x340, t3 - csrrc a5, 0x340, zero - sb a1, -933(a6) - lb ra, -851(a6) #end riscv_load_store_rand_instr_stream_3 - la s10, region_1+9455 #start load_store_instr_stream_2 - la t1, region_1+13526 #start load_store_instr_stream_3 - la a1, region_1+15929 #start load_store_instr_stream_0 - sb s9, 171(t1) - la s4, region_1+997 #start load_store_instr_stream_1 - lbu t6, -214(s4) - lb t4, -10(a1) - lb a5, -114(s4) - lw t3, -101(s4) - lbu t4, 6(a1) - sb a2, 234(s4) - lb s7, -169(s10) - lh t2, 185(s10) - lh t4, -3(a1) - sh s9, -175(s4) - sb gp, 35(t1) - lbu s7, 158(s4) - lbu s0, -14(a1) - lbu s11, -221(t1) - sb a6, -175(s4) - lbu s5, 122(s10) - sb a3, -242(t1) - lbu s11, -246(s10) - lbu s3, -138(s4) #end load_store_instr_stream_1 - lb t4, 55(t1) #end load_store_instr_stream_3 - lb s7, 82(s10) #end load_store_instr_stream_2 - lb a2, 13(a1) #end load_store_instr_stream_0 - la a3, region_4+391 #start riscv_hazard_instr_stream_1 - remu s7, s1, s0 - lb a1, 12(a3) - csrrw tp, 0x340, s0 - c.xor s1, a1 - c.lui tp, 24 - lb tp, -6(a3) - lb s7, 14(a3) - c.add s0, s7 - sh s7, -13(a3) - lb a1, 2(a3) - div tp, s7, s0 - addi tp, s1, 425 - lb a1, 11(a3) - lbu s7, -14(a3) - mul s1, s1, s1 - lb s7, -2(a3) - lb s0, -8(a3) - c.addi s0, -32 - sb a1, -6(a3) - lb s1, 15(a3) - lb s0, 2(a3) - c.srli s0, 16 - csrrwi tp, 0x340, 4 - lh s7, 3(a3) - sub s1, gp, gp - slli tp, s1, 31 - mul s0, a1, s0 - lb s7, -6(a3) - csrrc tp, 0x340, a1 - lh a1, 9(a3) - lb s0, 4(a3) #end riscv_hazard_instr_stream_1 - addi a5, zero, 6 #init loop 1 counter - addi zero, zero, 0 #init loop 1 limit -sub_1_61_1_t: c.addi a3, -21 - c.sub s1, a5 - addi a5, a5, -1 #update loop 1 counter - c.sub s0, a1 - addi s3, zero, 10 #init loop 0 counter - c.slli t1, 12 - addi s7, zero, 6 #init loop 0 limit -sub_1_61_0_t: c.addi s10, -14 - addi s3, s3, -1 #update loop 0 counter - srai ra, t4, 31 - bgeu s3, s7, sub_1_61_0_t #branch for loop 0 - c.beqz a5, sub_1_61_1_t #branch for loop 1 - mulhu s10, t0, a0 - la s1, region_4+506 #start load_store_instr_stream_0 - lhu t1, -104(s1) - lb a6, 216(s1) - lbu a1, 100(s1) - sb sp, 141(s1) - la t4, region_4+1971 #start load_store_instr_stream_1 - lbu a2, 38(s1) - sb t0, -599(t4) - lhu ra, -459(t4) - sh a4, -222(s1) - lb t0, 118(t4) - lbu s5, 167(s1) - lbu a0, -62(t4) - sb a6, -121(s1) - sb s0, 13(s1) - sb a7, 396(t4) #end load_store_instr_stream_1 - lbu tp, -214(s1) #end load_store_instr_stream_0 - addi ra, zero, 3 #init loop 0 counter - addi s5, zero, -16 #init loop 0 limit - .4byte 0x00100073 # ebreak -sub_1_62_0_t: csrrwi zero, 0x340, 13 - addi ra, ra, -1 #update loop 0 counter - bne ra, s5, sub_1_62_0_t #branch for loop 0 - remu t2, t4, t3 - la gp, region_2+3557 #start load_store_instr_stream_2 - la s11, region_0+1323 #start load_store_instr_stream_1 - lb s7, -486(s11) - la s3, region_1+1164 #start load_store_instr_stream_3 - la tp, region_4+925 #start load_store_instr_stream_0 - lh s1, 13(gp) - lbu s10, 714(s11) - lhu s7, 995(s11) - lbu s6, 2(gp) - lbu s7, 1013(s11) - lb a5, 0(gp) - sb t5, 10(tp) - lhu s2, -15(gp) - lb zero, -141(s11) - lhu a0, 25(tp) - sb s5, 4(gp) - lb a6, 39(s3) - sb ra, -39(tp) - lh s0, -1015(s11) - lw s1, 3(gp) #end load_store_instr_stream_2 - sb s9, 49(s3) - lb t3, 833(s11) - sb a5, 22(s3) - sb a7, 823(s11) - lb s10, -6(tp) - sw s3, 793(s11) #end load_store_instr_stream_1 - lbu a6, -12(tp) - sh s8, -40(s3) - lb s2, 55(s3) #end load_store_instr_stream_3 - lb a3, 46(tp) #end load_store_instr_stream_0 - la tp, region_0+330 #start riscv_load_store_rand_instr_stream_2 - addi s1, a7, -57 - lb t5, 201(tp) - sll s7, a5, a6 - mulhsu s0, zero, s11 - remu s11, sp, zero - lb t0, 113(tp) - lb s3, 67(tp) - c.ebreak;c.nop; - lb a4, -17(tp) - sub a4, a2, s1 - lhu s2, -4(tp) - lhu t3, 164(tp) - ori a0, a5, -632 - slli a4, s2, 19 - c.andi a3, -26 - mulhsu t5, tp, s5 - lui a3, 306607 - lhu a1, -130(tp) - c.add s6, s10 - lbu a4, -82(tp) - lb gp, -34(tp) - mulhsu t6, a5, s9 - lbu t4, 226(tp) - and zero, s7, t4 - lb s4, -88(tp) - lb t0, -245(tp) - add a0, t1, t1 - sb s4, 176(tp) - c.andi a3, 26 - lb s2, 143(tp) - addi s2, t6, -385 - lbu s11, 61(tp) - sltu a1, s8, s11 - nop - sb s6, -76(tp) - lhu t2, 200(tp) - lbu gp, -208(tp) - c.or s1, a1 - sb ra, -55(tp) - sb t0, -168(tp) - addi t2, a3, 436 - sltiu s2, s10, -680 - lb a7, -162(tp) - c.srli a1, 23 - sb s6, -140(tp) - lhu t4, -226(tp) #end riscv_load_store_rand_instr_stream_2 -sub_1_23: jal gp, 1f -0: c.jal 25f -1: c.j 12f -2: jal t1, 22f -3: jal t1, 20f -4: c.j 13f -5: jal s11, 26f -6: c.jal 4b -7: c.j 11f -8: c.j 2b -9: jal a0, 10f -10: jal t1, 28f -11: jal ra, 3b -12: c.j 27f -13: c.j 16f -14: jal t1, 5b -15: c.j 17f -16: jal t1, 23f -17: c.jal 0b -18: c.j 15b -19: jal a3, 8b -20: c.jal 21f -21: c.jal 24f -22: c.jal 14b -23: c.j 18b -24: c.jal 6b -25: c.jal 19b -26: jal gp, 9b -27: c.j 7b -28: c.lui t3, 4 - la s11, region_1+9223 #start load_store_instr_stream_4 - la t5, region_3+63 #start load_store_instr_stream_3 - la t6, region_0+2721 #start load_store_instr_stream_1 - la a5, region_4+1049 #start load_store_instr_stream_0 - lh zero, 495(t6) - la gp, region_2+685 #start load_store_instr_stream_2 - sb a3, -196(a5) - lb a3, 210(gp) - sb tp, -838(t6) - sb s6, 48(s11) - sh t3, -15(s11) - sb a5, 20(gp) - lb s1, -164(gp) - lhu a7, 7(t5) - lb a2, 95(a5) - lh a7, 51(s11) - lhu s5, -179(a5) - lb ra, 28(s11) - lh t2, 397(t6) - lh s10, 11(a5) - lhu ra, -3(s11) - sw s11, -31(s11) - lbu s10, -56(t5) - sb a0, 141(gp) - lbu t4, -32(t5) - lhu s6, 17(a5) - sb sp, -62(t5) - sb s4, 570(t6) - sh t5, 49(s11) - sb t1, -126(a5) - lw s4, 227(a5) - lbu s10, -42(t5) - lb t1, 30(s11) #end load_store_instr_stream_4 - lhu zero, -29(t5) - lbu s2, 232(gp) - lh zero, 975(t6) - sb t4, -226(t6) #end load_store_instr_stream_1 - lbu t3, 16(gp) #end load_store_instr_stream_2 - lbu s1, 60(a5) - lb s10, -30(t5) - lb s7, -16(t5) #end load_store_instr_stream_3 - lbu a1, 161(a5) #end load_store_instr_stream_0 - addi a2, zero, -6 #init loop 1 counter - addi s5, t1, -209 - addi zero, zero, 0 #init loop 1 limit - div a3, t4, a0 - xori s5, t3, -925 - sra t3, s3, t6 - c.or s0, a5 - auipc s0, 549420 - rem a5, s4, a4 -sub_1_66_1_t: slt a7, s11, a4 - lui a0, 791510 - auipc t0, 438576 - addi a2, a2, 3 #update loop 1 counter - csrrw s10, 0x340, t3 - addi a6, zero, -4 #init loop 0 counter - add a7, s4, t5 - c.andi a4, -28 - c.lui a3, 15 - rem t3, s2, t2 - csrrsi s1, 0x340, 0 - addi t4, zero, -1 #init loop 0 limit - c.xor a1, a0 -sub_1_66_0_t: c.mv s5, s5 - mul s10, s3, s8 - xor tp, t4, s1 - csrrci gp, 0x340, 4 - addi a6, a6, 2 #update loop 0 counter - srl t0, zero, s8 - blt a6, t4, sub_1_66_0_t #branch for loop 0 - csrrs s3, 0x340, s4 - sra a0, s9, a1 - c.bnez a2, sub_1_66_1_t #branch for loop 1 - auipc s3, 927834 - la a0, region_3+112 #start riscv_hazard_instr_stream_4 - xori a2, t0, -355 - ori a3, t4, -159 - lb a2, 5(a0) - lbu a5, 130(a0) - div a5, a2, t0 - c.nop - sh a2, 360(a0) - ori a2, t4, -337 - and t0, a3, t4 - lbu t2, 171(a0) - lbu t4, 293(a0) - c.srai a3, 10 - xor t2, a5, t4 - sb t4, 64(a0) - nop - lw a5, 280(a0) - .4byte 0x00100073 # ebreak - or t2, t0, a2 - mul t0, t2, t4 - sltu a2, a5, a5 - srli t2, t4, 14 - sh t0, 150(a0) - c.lw a2, 8(a0) - xor a2, a3, t2 - sb t4, 217(a0) - lb t2, -9(a0) - div t0, t0, t4 - sra a5, a2, t0 - lh a2, -24(a0) - lbu t4, 201(a0) - lbu t4, 109(a0) - lbu a5, 360(a0) - lb t4, 166(a0) - add t0, t4, t4 - lb t0, 234(a0) - lb a3, -85(a0) - sub a5, a5, t2 - lb a3, 77(a0) - csrrwi t2, 0x340, 9 - c.ebreak;c.nop; - add a3, a3, a2 - c.sw a3, 8(a0) - c.srli a3, 16 - sll a5, a3, t2 - c.sub a3, a3 - lb a3, 240(a0) - sll t2, t0, t0 - divu a2, t2, t4 - sb a3, -30(a0) - c.sub a2, a3 - csrrci t0, 0x340, 16 - auipc a5, 382164 - lb a5, 150(a0) #end riscv_hazard_instr_stream_4 - la t0, region_2+5991 #start load_store_instr_stream_1 - lb ra, -366(t0) - lb s5, -957(t0) - la t6, region_2+2050 #start load_store_instr_stream_2 - la s11, region_2+6387 #start load_store_instr_stream_0 - la gp, region_2+1942 #start load_store_instr_stream_4 - la s2, region_2+2099 #start load_store_instr_stream_3 - sh ra, -2(gp) - sh t6, -484(t6) - lhu a0, 47(s11) - sb a3, 285(t0) - lbu a6, -413(s2) - lbu s7, 1(gp) - lbu s3, 25(s11) - lbu a6, -32(s11) - lb s4, -933(t0) - lb s7, 124(s2) - sh s10, -245(s2) - lbu t2, 987(t6) - lhu s4, -913(s2) - lbu a6, -9(gp) - sb a4, -336(s2) - lb a3, -20(s11) - lhu s10, -8(gp) - lb s5, 3(gp) - sb s1, -50(s11) - lbu s6, 176(t6) - lh a5, -6(gp) - lhu a1, 39(s11) - lb a5, -16(gp) - lbu t4, 497(s2) - lb s1, -918(t6) - lb ra, 851(t6) - lb a3, 396(s2) - lw a4, 857(s2) #end load_store_instr_stream_3 - lbu a1, 3(gp) #end load_store_instr_stream_4 - sb a1, -464(t0) #end load_store_instr_stream_1 - lbu t5, -203(t6) #end load_store_instr_stream_2 - lhu t5, -19(s11) #end load_store_instr_stream_0 - la t6, region_2+4459 #start load_store_instr_stream_2 - la a2, region_2+2203 #start load_store_instr_stream_1 - la a4, region_2+4803 #start load_store_instr_stream_0 - lh s1, -811(a2) - lb t4, -42(t6) - sb a1, -15(t6) - lbu t1, 6(t6) - lhu s10, 135(a2) - sw ra, 777(a4) - lb tp, 10(t6) - sw a6, 445(a2) - lbu a3, 32(t6) - lb t2, 186(a4) - lb t5, -28(t6) #end load_store_instr_stream_2 - sb t4, 400(a4) - sb s0, -281(a4) - lhu t5, -887(a2) - sh s6, -585(a2) #end load_store_instr_stream_1 - lbu s4, 983(a4) - lw a0, 557(a4) #end load_store_instr_stream_0 - la a0, region_2+3710 #start load_store_instr_stream_0 - la ra, region_1+5059 #start load_store_instr_stream_2 - sh t1, -8(a0) - la t3, region_4+3445 #start load_store_instr_stream_3 - lhu tp, -11(ra) - lhu t6, 5(ra) - lb s5, 649(t3) - sb s7, 15(a0) - sb s4, 6(ra) - lhu t1, 429(t3) - lh s2, 265(t3) - lh zero, 5(ra) - la a5, region_0+3177 #start load_store_instr_stream_1 - sh s9, -599(t3) - lbu s1, -7(ra) - lbu s10, 593(t3) - lh t4, 5(a5) - lbu a6, 8(a5) - lbu a1, 23(a0) - lbu s1, -8(a5) - sb sp, 60(a0) - lbu t1, -12(a5) - sb s1, 245(t3) - lb a2, 8(a5) - sh t6, -5(ra) - sb s10, 10(a5) - lb a6, 923(t3) - sb tp, -16(a5) #end load_store_instr_stream_1 - lh s2, 393(t3) - lb s2, 1(a0) - lb s6, -6(ra) - lhu s2, -18(a0) - sh sp, -845(t3) - lhu s0, -12(a0) - sb a6, -14(ra) #end load_store_instr_stream_2 - sb a6, 648(t3) #end load_store_instr_stream_3 - lbu s3, -35(a0) #end load_store_instr_stream_0 - addi t6, zero, 9 #init loop 1 counter - addi s3, zero, -1 #init loop 1 limit -sub_1_64_1_t: mulh t0, t5, a6 - addi t6, t6, -2 #update loop 1 counter - addi ra, zero, -10 #init loop 0 counter - sub t3, s8, t3 - addi s6, zero, -9 #init loop 0 limit -sub_1_64_0_t: sltu t4, tp, s8 - addi ra, ra, 3 #update loop 0 counter - blt ra, s6, sub_1_64_0_t #branch for loop 0 - bne t6, s3, sub_1_64_1_t #branch for loop 1 - csrrw t1, 0x340, gp -sub_1_16: jal gp, 3f -0: c.jal 6f -1: c.jal 5f -2: c.jal 4f -3: c.jal 12f -4: c.jal 8f -5: jal ra, 0b -6: jal ra, 7f -7: jal ra, 11f -8: jal tp, 1b -9: c.jal 10f -10: c.j 13f -11: jal ra, 9b -12: c.j 2b -13: slti t0, s1, 1013 - blt s7, t2, 8f - sltu a3, ra, t5 - c.slli t3, 13 - sll s1, tp, t1 - bltu t3, a3, 16f - srli t4, t3, 11 - sub s1, s2, t4 - andi gp, s8, 638 -8: c.ebreak;c.nop; - bge s4, s4, 17f - ori a2, s2, 922 - csrrsi s11, 0x340, 31 - and a5, s9, s11 - sll t5, s0, sp - sub t1, t3, s1 - beq a7, a5, 29f -16: c.andi a4, -30 -17: rem a7, zero, ra - sltu s4, s3, s3 - slli zero, t0, 31 - mulh a6, a1, s4 - blt a5, t0, 40f - div a6, a3, s5 - bne s5, t6, 39f - and t4, s8, ra - and s3, s0, t0 - c.xor a0, a1 - mulhu a6, a4, t0 - csrrsi s2, 0x340, 9 -29: c.lui tp, 19 - nop - c.bnez s1, 43f - csrrsi t0, 0x340, 21 - remu s1, a2, s5 - c.nop - csrrci s7, 0x340, 5 - c.lui gp, 4 - c.li gp, -16 - nop -39: mul t4, s11, t4 -40: rem s3, ra, a4 - slli s2, a0, 10 - srl s0, t5, s5 -43: blt s4, t0, 45f - c.xor a4, a2 -45: c.xor s1, s0 - srli a1, s9, 22 - c.nop - sltu t4, ra, t5 - bltu t2, s11, 57f - slti t0, s9, -708 - bltu zero, gp, 69f - sll a7, s8, gp - blt a5, tp, 57f - or s10, a5, t1 - srai a7, s3, 10 - c.mv a3, a3 -57: c.li t3, 19 - bge t2, ra, 74f - addi t3, ra, 27 - nop - slti t1, s8, 976 - rem a7, a3, t2 - csrrc t0, 0x340, ra - lui t2, 456716 - mul t5, a5, a7 - auipc s3, 611063 - .4byte 0x00100073 # ebreak - csrrci a4, 0x340, 24 -69: rem ra, s8, s8 - c.beqz a4, 76f - c.ebreak;c.nop; - slt a3, s9, s3 - csrrci a5, 0x340, 20 -74: nop - xor t5, gp, a5 -76: mul t1, a2, s6 - csrrci s11, 0x340, 13 - bne s5, s8, 97f - add t1, s10, zero - c.xor a1, a5 - c.li s6, 21 - bltu s4, t6, 88f - mulh a7, s2, zero - xor zero, t4, a5 - bgeu t4, t4, 87f - csrrc a7, 0x340, t1 -87: add t5, t0, s8 -88: c.srli s0, 8 - c.xor s1, a1 - csrrwi t0, 0x340, 26 - xor tp, a7, t6 - xori t0, t1, -859 - c.ebreak;c.nop; - mulhu t6, a5, s7 - addi t3, t0, -307 - c.mv a3, s0 -97: c.sub a5, a1 - c.bnez a5, 103f - and a4, t6, ra - bne s6, s8, 102f - csrrwi s6, 0x340, 20 -102: c.srai a4, 5 -103: csrrci t4, 0x340, 7 - bltu tp, s8, 108f - or t6, a5, t1 - or t6, ra, t1 - bge tp, a0, 120f -108: mulhsu s4, a6, s4 - csrrci t0, 0x340, 18 - bgeu sp, a6, 124f - auipc s6, 515478 - sra a6, a2, s10 - addi a0, a4, -181 - srai t0, a0, 9 - bge a4, s2, 125f - bge sp, a0, 136f - c.ebreak;c.nop; - xori gp, a1, 612 - bge t0, s4, 138f -120: ori a7, t0, 930 - mulhu t6, t0, t6 - and ra, t3, a6 - csrrsi zero, 0x340, 18 -124: rem gp, s11, s1 -125: remu s1, a2, a2 - mulhu a7, a0, s9 - c.xor a3, s0 - c.andi s1, 19 - csrrsi a6, 0x340, 11 - or gp, s0, a2 - c.ebreak;c.nop; - mul t0, a3, a3 - lui s6, 43309 - c.nop - csrrw s7, 0x340, s6 -136: csrrc s11, 0x340, s4 - auipc t5, 562037 -138: div s4, s7, a0 - mulhsu a5, s6, s0 - remu s2, a2, t5 - c.and a3, a3 - c.lui t4, 28 - c.xor s1, a0 - and s4, a0, zero - c.andi a4, -13 - blt s3, s2, 151f - rem zero, a0, t3 - slli a4, t1, 24 - c.xor a2, s1 - xor s2, zero, a0 -151: sll a2, t5, t2 - srli s11, t1, 26 - csrrw gp, 0x340, s4 - c.addi s11, -7 - csrrci tp, 0x340, 1 - c.andi a5, -8 - c.lui a6, 5 - csrrci s5, 0x340, 23 - .4byte 0x00100073 # ebreak - div s10, a6, s11 - csrrci t5, 0x340, 28 - mul t4, s0, a2 - or a6, a3, s11 - csrrc s0, 0x340, s0 - c.li t4, 24 - c.srli a2, 30 - divu t6, t5, s1 - bltu zero, a7, 180f - ori s10, s1, -603 - c.and a3, a4 - csrrs s1, 0x340, s3 - sub a1, a6, s11 - c.add s5, t6 - lui a1, 576890 - xor a0, a5, s8 - c.beqz a4, 196f - c.nop - rem s4, a7, s11 - c.li t3, -12 -180: div s11, a5, t0 - c.srli a5, 28 - c.addi gp, 24 - csrrci s5, 0x340, 6 - c.andi a1, 7 - c.ebreak;c.nop; - sltu a6, a7, s11 - srl t2, t6, t2 - csrrwi s6, 0x340, 8 - csrrsi a1, 0x340, 17 - slti a2, s4, -730 - bge a7, a0, 199f - c.ebreak;c.nop; - csrrw a1, 0x340, a4 - and s3, a4, t1 - andi a2, t3, 465 -196: c.beqz a0, 204f - sltiu s7, a7, -710 - remu s11, a3, s9 -199: c.bnez a1, 207f - mul a5, s8, s8 - slti a2, a0, 585 - nop - c.xor s0, a2 -204: addi t4, s1, -260 - c.sub s0, a4 - xori a1, a0, 956 -207: csrrwi a0, 0x340, 18 - srli a2, a3, 29 - ori s5, s11, -305 - slti a4, s0, -311 - csrrci a0, 0x340, 28 - sltiu s7, a3, -437 - mulhu a7, s3, zero - c.bnez a4, 226f - addi t6, a0, 550 - add s10, s4, a3 - sll s0, a5, a2 - slli s10, s1, 21 - andi t0, t0, -315 - c.sub a0, s0 - mul gp, s1, t6 - rem a3, sp, s2 - beq s7, s7, 242f - c.li s10, 28 - c.addi a2, 18 -226: beq s2, a0, 228f - c.and a5, a0 -228: and t1, a2, sp - slti tp, t3, -411 - slli t1, t3, 21 - c.bnez s0, 233f - c.srli a0, 10 -233: c.ebreak;c.nop; - bge s2, sp, 239f - c.add a4, t6 - bne t1, s8, 241f - csrrw t4, 0x340, ra - c.lui a3, 8 -239: c.addi t2, -27 - c.addi t4, 12 -241: bgeu s2, s4, 259f -242: slti s5, s8, 939 - c.lui t0, 31 - c.slli s6, 2 - div tp, s4, s1 - sltu t6, s0, s8 - lui s6, 454137 - bltu s3, t5, 262f - andi zero, ra, -682 - auipc a4, 267417 - c.and s1, a3 - bgeu t6, t2, 254f - c.addi s11, 6 -254: c.add gp, t1 - c.and a4, s1 - c.addi ra, -28 - c.nop - divu t0, s3, zero -259: mulhsu a0, t2, t5 - c.lui t3, 17 - blt t6, tp, 281f -262: remu a5, s1, sp - .4byte 0x00100073 # ebreak - c.bnez s1, 284f - sll s6, a3, a5 - csrrc t2, 0x340, a6 - c.li a7, -3 - xori ra, t5, 94 - srl s4, s0, a4 - slti a0, s9, 86 - blt a4, ra, 285f - srl a0, a6, s4 - sltu s2, s9, s5 - bge s0, s4, 293f - slti a0, s10, -727 - beq a0, tp, 284f - csrrwi ra, 0x340, 8 - c.xor a5, a2 - csrrci a6, 0x340, 29 - mulhu s10, a1, s5 -281: c.beqz s1, 285f - c.and a0, s0 - mul s0, s1, s10 -284: srli a7, s7, 8 -285: c.li a4, -16 - csrrci s0, 0x340, 11 - slt gp, a0, a4 - sltu t1, a0, tp - c.and s1, a1 - div a0, a6, t6 - and t1, t1, a1 - c.srli a5, 6 -293: lui a4, 839995 - and s2, a3, s11 - sra s1, t5, ra - csrrwi t2, 0x340, 28 - sll a1, s4, s6 - and a7, a7, s5 - mul a4, s9, s1 - mulhu s0, s3, a6 - csrrs s4, 0x340, s10 - nop - bltu a6, ra, 322f - .4byte 0x00100073 # ebreak - c.andi a3, -11 - slt t2, a0, zero - c.xor a2, a2 - and a1, s10, sp - c.ebreak;c.nop; - addi t5, t5, -663 - srli s1, s4, 4 - slti s4, s10, 225 - csrrs a3, 0x340, t5 - xori a7, t3, 901 - c.add t3, a2 - srl zero, s8, a6 - rem s5, a0, s5 - lui zero, 649289 - c.andi a4, 13 - c.mv t6, s0 - c.srli a0, 29 -322: csrrwi t1, 0x340, 4 - c.or a5, a0 - c.slli tp, 5 - nop - sltu ra, s11, s5 - bgeu a7, a5, 343f - c.li s6, -15 - mulh s7, ra, a1 - mulhu s0, ra, t1 - xor t3, a4, a6 - srli s11, t4, 26 - mul s0, t3, tp - sll tp, t2, t3 - rem s10, a6, a6 - c.and a5, s1 - csrrc zero, 0x340, gp - bltu a7, a4, 350f - sltiu a5, gp, -248 - csrrs s0, 0x340, s5 - or t0, a1, t1 - lui a2, 1031426 -343: addi a7, s11, 535 - c.bnez s1, 352f - c.ebreak;c.nop; - c.add tp, s9 - c.xor a5, a0 - c.addi s0, 23 - mul t0, t3, zero -350: add s7, ra, s6 - c.andi a3, 16 -352: c.or a4, a2 - c.sub a2, a5 - sub a0, s6, a1 - c.lui t1, 13 - csrrs a2, 0x340, s3 - csrrc a0, 0x340, gp - addi s1, s5, 341 - slti s7, a7, -172 - xori s0, t0, -572 - c.bnez a4, 374f - bgeu s5, sp, 366f - mulhsu s7, s1, a5 - c.nop - nop -366: csrrw zero, 0x340, zero - c.sub a3, a4 - c.andi a1, 9 - c.srai a4, 29 - csrrw ra, 0x340, a0 - addi t0, t0, -382 - bgeu t4, tp, 378f - divu s7, s3, s0 -374: c.slli s11, 19 - srli s1, t2, 15 - nop - mul s7, t2, t0 -378: bne sp, sp, 386f - slt tp, t2, tp - xori zero, a0, -649 - divu a2, s9, s11 - c.add t2, t3 - beq gp, s11, 391f - mul t5, sp, s6 - sub a5, s1, a0 -386: addi s6, t1, -920 - csrrsi a3, 0x340, 7 - csrrwi a3, 0x340, 12 - nop - c.nop -391: c.or a3, a4 - xor t2, a2, t3 - and a7, a4, a5 - blt a3, a3, 406f - srl a3, s6, s1 - divu a7, t3, t0 - blt t0, zero, 407f - xori gp, zero, 135 - slti t0, s4, -440 - sltu s7, sp, s3 - c.srli s0, 19 - xori s2, a1, 156 - ori s3, a3, -269 - c.beqz a4, 410f - nop -406: c.slli a2, 5 -407: c.srai a5, 14 - csrrsi t0, 0x340, 16 - c.nop -410: srl ra, s8, t1 - c.andi a0, -31 - sll t5, s8, zero - c.and a5, a4 - slti t4, t6, -78 - c.and a4, a4 - c.add t2, t4 - sll s2, a6, t3 - and a1, a6, t5 - lui a4, 475989 - addi s2, sp, -583 - bge s1, s1, 429f - addi s2, a6, 104 - sra s4, s10, s2 - mul t5, s2, s1 - xor ra, s4, a1 - sltiu t4, zero, 297 - csrrci zero, 0x340, 22 - c.srai a4, 12 -429: bgeu a7, a5, 437f - c.xor a2, s0 - xori t1, s5, -529 - rem a2, a0, s3 - c.ebreak;c.nop; - sra a0, a4, gp - and a3, ra, a4 - csrrwi s10, 0x340, 12 -437: sltu a5, sp, a0 - srl a3, s6, a1 - bgeu tp, t5, 455f - c.addi t0, -19 - sltiu t3, a7, -333 - nop - mulhsu t1, s5, a5 - sltiu a5, s2, -431 - or s11, a4, s3 - sltu s1, s4, s2 - mulhsu a6, s3, t2 - and t4, s5, a5 - div s2, a2, a4 - c.andi a1, -26 - divu t4, a5, s1 - nop - bge s2, a2, 472f - csrrs t0, 0x340, s8 -455: c.andi s1, 23 - c.srli a4, 29 - andi t1, a2, -269 - blt a3, s4, 466f - sltu a5, s11, s6 - c.mv s3, sp - c.addi gp, -14 - divu a6, t3, s3 - remu gp, gp, sp - divu ra, t3, ra - c.or a3, a3 -466: srai s3, a7, 5 - bne t2, zero, 477f - c.bnez a0, 474f - xor t5, sp, t0 - sra a6, s8, gp - csrrc s2, 0x340, s7 -472: mulh s3, t4, a6 - xor t5, a1, s6 -474: divu s1, a0, s8 - c.nop - add a3, gp, a6 -477: sub s1, s5, zero - slli ra, s8, 21 - lui s11, 274496 - srl s10, t1, s6 - addi s5, s7, -431 - blt a5, tp, 488f - c.andi a4, 24 - srli a0, tp, 20 - slli a0, s0, 19 - csrrs a7, 0x340, s3 - csrrwi t4, 0x340, 17 -488: blt ra, tp, 500f - or s1, zero, s0 - c.add t3, a3 - beq a0, t1, 509f - mulh gp, a1, tp - sltu t6, t4, t6 - div a3, s10, s2 - csrrc s7, 0x340, a2 - sub s11, a5, gp - mul a5, s7, s1 - divu gp, t6, s1 - mulhu s7, t4, a7 -500: sra a1, s8, t3 - add t2, s4, s9 - srli a0, s6, 14 - xor t3, s9, gp - .4byte 0x00100073 # ebreak - mulhsu s3, s3, a5 - divu t4, t2, a7 - srl t6, a0, t5 - csrrs t0, 0x340, t3 -509: srli a3, s11, 19 - rem a1, s3, a0 - rem s10, sp, s5 - and s1, s0, a3 - beq s11, s3, 521f - c.or a1, a3 - bge a7, s0, 535f - slli s3, s11, 31 - c.add s5, a6 - addi t0, s10, 919 - sltu a0, s10, a6 - c.mv t3, tp -521: c.srli a5, 12 - mulh t3, s9, ra - sra t3, s10, tp - mulhu t4, t1, t6 - csrrsi s10, 0x340, 31 - bge s8, a1, 542f - c.and a1, a5 - remu t5, a7, s2 - mul t5, s10, t5 - .4byte 0x00100073 # ebreak - blt s1, t4, 536f - or s7, s0, ra - mulh ra, a1, ra - bgeu t1, a4, 542f -535: rem a4, s10, sp -536: addi a0, a1, -768 - andi a7, s10, -1004 - c.andi a4, -32 - srli s2, tp, 10 - csrrc a5, 0x340, s11 - div t2, t0, s0 -542: xori a3, s2, 166 - mulhu a7, t2, s0 - remu a4, gp, a0 - c.sub a2, s0 - c.bnez s1, 560f - c.srai a5, 25 - rem gp, s9, t0 - andi t6, t2, -852 - mulhu a7, t6, a5 - c.slli a3, 15 - sra s7, sp, s8 - c.beqz s0, 555f - csrrci s0, 0x340, 19 -555: add a2, a5, t4 - c.add a4, a3 - sub ra, s5, s1 - sub s10, s6, t1 - slt s11, sp, t3 -560: slli t0, s0, 26 - mulhu a6, zero, a6 - sra s3, s3, a6 - sltiu s3, s5, -284 - blt a4, s5, 584f - slli t1, s9, 12 - c.nop - blt a7, tp, 575f - c.lui t0, 31 - csrrci a2, 0x340, 2 - bltu t2, t1, 574f - c.li ra, -31 - c.add t4, t0 - c.nop -574: slti t0, a1, 319 -575: bge gp, a1, 577f - srli s0, s7, 31 -577: c.and a4, a4 - c.nop - sll gp, t1, a5 - csrrsi s7, 0x340, 7 - rem a0, a2, gp - c.xor s0, s1 - csrrwi s4, 0x340, 10 -584: mul ra, s7, a3 - c.lui s5, 29 - bgeu t1, s2, 605f - and a3, s6, s4 - remu a3, t5, s2 - csrrw a2, 0x340, s4 - csrrs s5, 0x340, gp - slti a2, a3, 418 - lui a5, 894303 - mul a4, s9, s10 - nop - c.bnez s0, 603f - c.addi a0, 7 - csrrci a7, 0x340, 18 - xor s6, s0, s7 - c.lui s3, 8 - mulh s4, s4, t1 - c.or a4, a0 - c.addi a5, -31 -603: csrrwi s2, 0x340, 11 - addi a5, t4, 866 -605: c.bnez a1, 613f - c.beqz a4, 622f - c.and s1, a3 - c.slli s4, 13 - c.bnez a2, 623f - c.srai s0, 28 - c.mv a3, s10 - sltiu a5, ra, 503 -613: c.addi s4, -5 - c.xor a1, a5 - c.addi t0, 26 - mulhu zero, s6, t2 - c.bnez a3, 636f - c.srai a5, 27 - c.add a2, s7 - andi s2, a0, -279 - or a2, t3, s2 -622: c.addi a7, -24 -623: add a4, a5, a6 - c.nop - and tp, t3, s8 - csrrsi s6, 0x340, 23 - c.slli a0, 3 - sub s7, a5, a3 - sltu s4, s2, s3 - c.lui a0, 19 - remu s3, a5, a4 - mulh s11, s9, s10 - c.sub a0, s1 - c.beqz s0, 638f - sra t1, t6, a0 -636: c.nop - sltiu ra, s3, -325 -638: bne s8, t4, 651f - remu ra, t1, sp - bgeu ra, t0, 652f - c.srai s1, 3 - sub a0, a6, s10 - slti a1, s4, -518 - lui t6, 28343 - csrrw s1, 0x340, s4 - slt tp, a6, ra - lui a1, 636970 - csrrci a6, 0x340, 30 - or s4, s8, zero - c.srli a2, 15 -651: srli a0, a7, 23 -652: mulh a4, ra, s10 - srli s5, a1, 25 - nop - sltiu t3, t0, 316 - c.add t1, s11 - andi a0, s3, -470 - c.addi gp, -19 - div a1, s8, t5 - slti a7, t1, -751 - remu a3, s9, a7 - csrrw gp, 0x340, s10 - .4byte 0x00100073 # ebreak - c.srli a0, 3 - bge s11, ra, 677f - .4byte 0x00100073 # ebreak - slti s7, s10, -900 - lui s7, 226741 - srli a2, a1, 9 - slli a4, t4, 30 - c.add s0, s8 - csrrsi t1, 0x340, 2 - csrrc tp, 0x340, a0 - srl a2, sp, tp - bgeu a0, a0, 680f - csrrw a0, 0x340, sp -677: srli s11, a7, 24 - csrrc a6, 0x340, s10 - and s1, s2, s8 -680: mulh t0, s8, zero - bne t3, t5, 683f - mulh a5, a1, t1 -683: c.mv gp, s8 - c.addi t2, -7 - csrrs zero, 0x340, a3 - c.or s1, a0 - xori a6, s7, 829 - c.addi ra, -30 - sub a7, ra, ra - c.or a3, a2 - xor s1, s0, s3 - sra s5, a3, t5 - csrrw t4, 0x340, t1 - c.srli a0, 18 - csrrwi s2, 0x340, 6 - c.mv s5, t1 - div zero, s0, a4 - xor gp, a2, s7 - div s1, tp, a0 - c.addi s0, -11 - c.srli a1, 28 - lui t1, 840602 - c.nop - and t1, zero, a5 - bltu s6, t1, 718f - c.nop - sltu s11, sp, s8 - mulh s5, s10, s3 - lui s1, 966335 - or a6, t4, ra - lui s5, 344608 - srl a1, ra, s11 - add s11, tp, s2 - c.nop - c.add t1, sp - sra a2, s1, ra - c.add s10, s7 -718: mulhu s0, gp, s8 - sub s5, s11, s9 - add s11, a2, s10 - sltu a4, s11, a3 - c.add s6, s6 - slt s2, a2, a5 - slli t3, s4, 28 - bltu a2, zero, 731f - mulhsu s1, s11, s8 - csrrwi ra, 0x340, 29 - div a6, s0, s0 - add t2, s9, s6 - srli gp, s2, 14 -731: c.addi t1, -32 - csrrci s4, 0x340, 3 - c.addi a1, -16 - div s11, s11, s7 - divu s6, s4, a7 - bne t4, zero, 744f - or a0, s1, t2 - beq zero, a3, 742f - xori s4, a0, -455 - bge a6, s10, 742f - mulh s3, s10, a5 -742: bne a7, s0, 754f - div gp, sp, t5 -744: lui t4, 345562 - sub t6, s4, s4 - .4byte 0x00100073 # ebreak - andi a2, ra, 761 - ori s1, s4, -111 - addi a1, s11, -285 - srl s4, s2, a4 - .4byte 0x00100073 # ebreak - sltiu a6, t0, -35 - bltu t6, a0, 767f -754: sra t0, s1, t4 - c.ebreak;c.nop; - lui s6, 137751 - c.li s2, 14 - c.bnez a3, 778f - remu a7, s11, s10 - divu s5, a2, s11 - and a0, tp, tp - srai zero, s10, 21 - remu a6, a3, s3 - divu s2, t0, s10 - remu s11, t4, s10 - c.mv t0, tp -767: or a4, s4, s7 - sra s2, a3, a2 - mul s5, s3, a0 - addi t5, s1, 895 - lui t0, 506598 - c.and a5, a2 - c.nop - csrrw s7, 0x340, t6 - c.xor a0, s1 - srl a4, t3, t6 - bgeu s5, a7, 791f -778: c.xor a4, a0 - bltu t5, ra, 784f - slt s7, s4, s8 - sltu t2, s0, t5 - c.xor a0, a2 - .4byte 0x00100073 # ebreak -784: xor t4, a1, sp - c.mv a2, a6 - srli s10, a2, 26 - blt t4, tp, 795f - csrrsi tp, 0x340, 27 - beq s10, s6, 808f - ori s4, s1, 970 -791: nop - c.addi ra, 15 - csrrc s5, 0x340, gp - remu s2, t3, gp -795: srl tp, s1, a7 - c.srli a5, 5 - c.lui a3, 19 - srai s10, s8, 24 - slti s11, a3, 774 - csrrwi s2, 0x340, 29 - srai tp, a3, 0 - c.andi a1, 10 - c.li a2, -14 - slli s1, s4, 30 - csrrw s4, 0x340, s6 - sra s6, t3, a4 - c.slli t5, 3 -808: sra a6, s9, s0 - mulhsu a6, a6, s11 - c.srli a1, 29 - srl s0, s1, a6 - c.srli a3, 15 - srai ra, t3, 10 - xori s10, a1, -829 - csrrc a7, 0x340, a7 - remu s3, s6, ra - csrrs t4, 0x340, s1 - srl gp, s3, s0 - div zero, s5, a3 - auipc s11, 425057 - bltu s10, s4, 839f - addi s11, a3, -843 - sltu zero, s7, t1 - csrrsi a4, 0x340, 0 - c.srai a3, 9 - mulhsu s1, a5, t6 - nop - c.add s10, s4 - c.nop - c.andi a1, 18 - bne s3, zero, 851f - divu s6, s6, t2 - csrrci s11, 0x340, 20 - srli s10, a1, 25 - slti t6, t1, 76 - c.add a5, a7 - mulhu s5, a7, s5 - csrrw t3, 0x340, s11 -839: auipc tp, 241521 - srli t0, ra, 31 - xor ra, a1, a0 - srai s6, s4, 6 - lui s2, 714116 - c.sub s0, a4 - slli t0, s3, 14 - slt a2, t6, t2 - or a5, s7, t6 - mulh a3, t4, s9 - c.or s1, s0 - c.srli a2, 2 -851: c.nop - csrrci s6, 0x340, 2 - c.add s2, s1 - c.slli ra, 17 - bge a7, t5, 860f - c.bnez a3, 860f - c.sub a4, a5 - sll t6, t3, t1 - csrrc s0, 0x340, zero -860: div t3, tp, s10 - sltu a6, sp, a7 - andi a4, a4, -360 - c.slli s10, 18 - lui s11, 780535 - nop - srli t6, gp, 9 - slt t6, t2, a6 - c.or a1, a0 - nop - c.xor s0, a2 - c.ebreak;c.nop; - c.and a5, a3 - and t0, s7, s11 - sltu s5, a2, s6 - c.beqz a3, 881f - srl a2, s5, t5 - mulhu tp, a5, a1 - c.nop - mulhu t5, s2, sp - c.or a1, s0 -881: add s5, sp, s2 - srl s6, a2, s11 - c.and a4, a5 - c.nop - add zero, t6, a0 - srl a5, t3, a5 - sltu ra, sp, s11 - csrrw s7, 0x340, a3 - .4byte 0x00100073 # ebreak - mulhu s1, s1, t0 - and t3, s8, t3 - sltu t0, t6, ra - auipc a1, 938603 - add s4, s2, s0 - c.mv s2, a2 - blt a5, a2, 904f - csrrs a0, 0x340, gp - ori s2, t3, -620 - andi t6, s3, -571 - div a1, ra, a5 - c.and a2, a4 - c.beqz s0, 912f - sltiu t3, a7, -243 -904: ori ra, a4, 147 - slti a1, s6, 1008 - c.srai s1, 13 - mul a5, s2, zero - auipc s1, 42370 - slti a4, s2, -825 - mulhu a7, t0, s5 - c.lui tp, 5 -912: csrrc s3, 0x340, t4 - xor a0, t6, a7 - c.slli s10, 2 - xor zero, s1, a2 - srli zero, s7, 8 - slti t6, tp, 1021 - remu t4, a3, zero - mulhu a3, s5, s3 - xori s7, t4, 680 - slli s5, s1, 1 - csrrc a1, 0x340, s9 - csrrc t5, 0x340, a0 - csrrw a1, 0x340, a6 - mulhsu gp, s7, t6 - c.lui t4, 29 - slli ra, s3, 6 - c.addi a2, -3 - csrrwi a2, 0x340, 3 - c.and a4, a5 - csrrc a6, 0x340, s10 - csrrci a2, 0x340, 26 - srai ra, t2, 23 - nop - .4byte 0x00100073 # ebreak - blt a5, a0, 938f - div t6, s4, s3 -938: slt s3, s10, t5 - csrrci t0, 0x340, 28 - sltiu s4, s7, 274 - c.bnez a1, 943f - c.mv a5, t1 -943: slti s11, zero, 911 - mulh t5, s3, a4 - c.or a5, a4 - sltiu a1, a4, -684 - div s7, t0, s2 - divu a6, t5, t2 - beq s9, s9, 968f - sltu a1, t4, a4 - csrrci s10, 0x340, 20 - c.bnez a1, 964f - div t6, s8, a5 - srli a1, a1, 15 - mulhu s1, s11, a6 - c.srli a4, 17 - c.srli a0, 13 - andi a7, s10, 715 - sltu a2, a0, sp - csrrw a0, 0x340, t2 - sltiu a7, t0, -609 - c.beqz s0, 978f - c.lui s6, 3 -964: c.ebreak;c.nop; - c.srai a0, 18 - csrrc s7, 0x340, t3 - csrrc tp, 0x340, t4 -968: bne t0, a6, 984f - mulhu a1, t1, a2 - c.li s4, -26 - ori s1, t1, 444 - srl gp, t1, a0 - srl ra, s6, sp - auipc t2, 414418 - c.li a4, 29 - c.nop - div a1, t3, s0 -978: sltu t1, t4, ra - or gp, t3, t2 - c.nop - addi t3, tp, 881 - xori s7, a3, -199 - c.li a5, 23 -984: c.bnez a1, 1003f - sll s7, s2, a0 - c.sub a3, a4 - div a0, a6, zero - add s10, a4, t4 - csrrc a3, 0x340, s10 - add gp, s5, sp - or gp, s5, a7 - c.or a3, a4 - c.or s1, a2 - beq t2, s3, 1002f - slli t2, s0, 23 - srli s0, gp, 9 - mul a6, sp, a4 - mul s7, sp, s5 - ori a6, a3, -975 - c.add s1, a4 - srl s0, t3, t4 -1002: bge zero, t3, 1014f -1003: sll t5, zero, ra - div s6, a5, s0 - c.sub a4, a5 - c.addi t2, -15 - andi s6, a3, 418 - csrrci t5, 0x340, 18 - bgeu s9, t3, 1017f - rem a5, tp, s11 - mulhsu t6, s0, a5 - .4byte 0x00100073 # ebreak - andi t5, t6, 694 -1014: csrrci s7, 0x340, 0 - c.andi a1, -2 - c.lui s4, 21 -1017: c.sub a4, s0 - auipc tp, 807402 - csrrwi s0, 0x340, 0 - sra s6, a4, t2 - beq t0, t4, 1029f - c.bnez a2, 1042f - xori s11, s7, 542 - c.nop - divu a0, sp, s2 - c.srai a0, 18 - divu a7, s0, s7 - c.beqz a3, 1044f -1029: c.ebreak;c.nop; - and tp, t5, s6 - c.slli a5, 9 - sub s5, t0, a7 - blt a2, a1, 1037f - c.mv s5, s3 - auipc a0, 161399 - slt t6, s4, s8 -1037: mulhsu tp, s7, a4 - mulhu a1, s1, a6 - csrrc ra, 0x340, t0 - srli t1, tp, 18 - csrrci a3, 0x340, 16 -1042: sra a4, a1, s4 - c.srai a4, 11 -1044: slti s3, gp, -185 - slti s6, t5, 980 - c.srai a5, 13 - csrrsi s0, 0x340, 13 - mulhu a2, tp, a0 - srli t2, a5, 28 - sub ra, a5, a0 - or s3, tp, a7 - slli t0, a0, 30 - csrrci a6, 0x340, 11 - csrrci s6, 0x340, 2 - sltu t2, s1, t1 - rem s3, t6, a2 - mulh gp, s6, a2 - c.addi t5, -25 - rem t1, t5, s7 - beq gp, t1, 1062f - mulh a3, t6, s1 -1062: ori t1, t6, 717 - c.or s0, a0 - mulhsu a1, s6, t5 - csrrs t1, 0x340, a1 - mulhu t4, s6, s3 - div t3, a2, t4 - csrrwi t0, 0x340, 28 - mulhu a6, t3, t5 - mul t6, s3, sp - rem a1, gp, a4 - c.slli s11, 1 - andi s4, tp, -801 - c.nop - csrrs a4, 0x340, s4 - divu s5, a2, s9 - blt s2, t0, 1085f - c.mv gp, a6 - .4byte 0x00100073 # ebreak - c.and a3, a3 - remu s4, s10, a7 - xori ra, s10, -967 - bge a7, t4, 1091f - bne s11, a5, 1103f -1085: lui a5, 886186 - xori a6, s4, 988 - mulh s3, t4, s1 - c.mv tp, a2 - c.srli a0, 23 - slti a6, s3, -1008 -1091: c.addi ra, -3 - slti t1, zero, 928 - mulhu zero, a5, s0 - bne t0, s10, 1113f - rem s1, a7, sp - csrrs a6, 0x340, t4 - srai s11, t2, 1 - csrrw t2, 0x340, s1 - and t6, a4, a0 - c.srli a3, 21 - sra gp, s6, sp - csrrwi a1, 0x340, 9 -1103: csrrsi t6, 0x340, 23 - rem s6, s4, t3 - remu s10, t5, s9 - auipc t1, 775217 - remu s6, s6, a7 - lui t3, 727793 - c.andi a2, -21 - srai s1, t4, 10 - rem a5, a7, s11 - xor t2, a4, a0 -1113: lui a4, 606219 - c.srai a3, 14 - sltu s6, s7, s9 - c.add s3, s10 - c.srai a1, 24 - bne s4, zero, 1137f - sra s0, s11, a1 - csrrci s5, 0x340, 26 - csrrsi a2, 0x340, 26 - add a6, s10, a7 - c.andi a1, -23 - srl s11, s8, a1 - bge s0, a0, 1133f - c.lui s3, 3 - slti gp, zero, 49 - mulh t0, s11, a6 - csrrci gp, 0x340, 21 - c.addi t4, -6 - c.addi a0, 31 - add a7, s9, s4 -1133: c.xor a5, a4 - c.andi a5, -12 - csrrwi s7, 0x340, 19 - mulhsu s4, t5, a7 -1137: xori ra, t1, -222 - sub s11, s3, s2 - bge a6, a4, 1149f - bgeu a2, s4, 1145f - c.addi t4, 28 - andi zero, s3, -111 - .4byte 0x00100073 # ebreak - c.sub a0, s1 -1145: c.srli a4, 24 - csrrs s10, 0x340, t2 - c.slli t1, 16 - csrrc a4, 0x340, t2 -1149: xor t0, gp, a6 - beq s1, t4, 1152f - srai s2, a7, 25 -1152: bge s6, s0, 1160f - slli s7, zero, 10 - slti t6, a5, -372 - bltu t5, a7, 1157f - addi s6, t2, 990 -1157: or s5, a1, t2 - sll s11, a1, a4 - blt sp, t5, 1173f -1160: sll t1, tp, s8 - sra s5, a5, s7 - c.ebreak;c.nop; - sub zero, a5, gp - c.nop - c.beqz a3, 1178f - bgeu a3, zero, 1180f - csrrwi t5, 0x340, 0 - c.addi a2, -18 - csrrs a3, 0x340, s11 - slti s6, s10, 815 - ori gp, t1, -901 - sll a6, s11, a3 -1173: mulhu s10, s6, a7 - nop - csrrwi a2, 0x340, 18 - c.or a5, a3 - c.slli a2, 7 -1178: c.mv a2, t6 - lui t4, 530983 -1180: bne s11, s9, 1188f - blt a7, a5, 1193f - c.li a0, -12 - c.mv s6, t3 - sra a5, t3, s1 - csrrci s10, 0x340, 4 - mulh t6, t3, s2 - srl t2, s8, s10 -1188: mulhu ra, s10, s1 - csrrci a2, 0x340, 31 - sub s6, s2, a5 - c.srli a5, 26 - ori a5, s3, 422 -1193: c.bnez a5, 1201f - slti tp, a0, -207 - blt s6, ra, 1213f - sra s0, gp, s4 - lui s11, 750459 - csrrsi t0, 0x340, 11 - mulhu a6, s4, t5 - addi t5, s11, 987 -1201: nop - or s10, t2, s4 - sra t6, a7, t5 - csrrc s6, 0x340, a6 - c.srai a5, 27 - auipc s11, 995329 - bgeu t1, tp, 1219f - lui a3, 823780 - c.add a5, s4 - or a5, a7, s7 - mulh s3, s0, a1 - xori s11, t1, -864 -1213: bge t4, t6, 1219f - divu a3, a0, a5 - sltiu a0, t6, 822 - addi a4, a2, 947 - c.lui s10, 27 - c.srai a2, 11 -1219: csrrc a5, 0x340, s8 - auipc s3, 447586 - csrrw s4, 0x340, s11 - ori a5, s3, 892 - sll s3, s1, s1 - srli t1, sp, 29 - srli t1, t4, 5 - lui t3, 1009668 - lui a6, 756267 - csrrc t1, 0x340, s1 - remu s2, zero, ra - bne s9, s6, 1250f - csrrsi zero, 0x340, 25 - bgeu a6, a4, 1248f - auipc t0, 721912 - srl s10, s11, gp - c.srai a0, 17 - c.bnez a0, 1241f - xori ra, a7, 331 - csrrci gp, 0x340, 5 - xor zero, t6, zero - srli a0, s0, 18 -1241: mul s2, t2, s4 - c.addi s0, -26 - rem ra, s10, a0 - xor zero, zero, a6 - mulhu ra, tp, tp - slli s7, a0, 0 - slli s5, t2, 9 -1248: blt a0, t5, 1260f - c.li a1, 13 -1250: csrrw t2, 0x340, a6 - addi a1, t0, 457 - csrrwi t4, 0x340, 18 - rem a3, s7, t3 - remu s2, s5, s1 - auipc a7, 118419 - beq sp, t3, 1260f - mulh a3, s1, s0 - c.andi s1, 4 - c.srai a0, 22 -1260: c.ebreak;c.nop; - c.li gp, 22 - slt s11, t0, t1 - c.beqz s0, 1269f - srli tp, a3, 28 - slli ra, a0, 27 - c.lui t1, 16 - or s2, t2, s3 - slt a6, s5, a2 -1269: c.xor a2, a4 - c.mv s5, t1 - bne s7, ra, 1276f - c.li a5, 1 - nop - and s2, t2, a4 - sll tp, tp, tp -1276: blt sp, t4, 1288f - .4byte 0x00100073 # ebreak - andi a2, s0, -702 - remu a1, s4, t0 - slt s6, a2, a4 - csrrs a7, 0x340, t6 - nop - lui s10, 528456 - andi t4, a6, -671 - bne s11, s3, 1305f - rem a2, s4, a0 - sltiu s2, s10, 924 -1288: c.bnez a1, 1294f - c.lui s4, 24 - c.ebreak;c.nop; - c.or s0, a0 - csrrci gp, 0x340, 2 - c.mv s5, t3 - la a0, region_3+42 #start load_store_instr_stream_3 - la t3, region_0+852 #start load_store_instr_stream_4 - la s3, region_1+15818 #start load_store_instr_stream_1 - la s11, region_2+2019 #start load_store_instr_stream_2 - sb t0, -95(t3) - lb a2, -60(s11) - la a1, region_4+3209 #start load_store_instr_stream_0 - lhu a5, 180(t3) - sb t4, 69(s3) - lb a5, 105(s3) - sb t3, -250(t3) - sb tp, 28(s11) - lbu s0, 49(a0) - lb s1, -374(a1) - lw t1, -244(t3) - sb t2, -20(s11) - sb a6, -186(t3) - lb s0, -3(a0) - lbu s2, -19(a0) - lb s5, -241(s3) - lw a2, -52(t3) - lhu s4, 13(s11) - lb t6, -220(t3) - sb a1, 12(a0) - lb a3, -63(t3) #end load_store_instr_stream_4 - lbu a6, 216(a1) - lb a3, 44(s11) - lbu a7, -466(a1) - lb s2, -116(s3) - lbu s1, 99(s3) #end load_store_instr_stream_1 - lbu t5, 566(a1) - sb s0, -64(s11) #end load_store_instr_stream_2 - lbu a2, -27(a0) #end load_store_instr_stream_3 - lb a5, 484(a1) #end load_store_instr_stream_0 -1294: c.lui s2, 4 - c.or a3, a5 - c.li t3, -25 - sub s5, s6, a1 - slti s0, s9, 368 - and s2, a1, s8 - csrrwi a2, 0x340, 10 - slli s3, s7, 2 - sll a6, a1, a4 - c.and s1, a2 - c.add a0, a2 -1305: sll s7, gp, s3 - c.sub s0, a4 - rem a0, s10, s8 - c.addi a5, -26 - bne s1, a6, 1317f - srai a0, t3, 4 - csrrw s3, 0x340, tp - lui t0, 980678 - c.mv t3, a6 - sll s7, s2, gp - xor s11, s5, s7 - c.mv s3, s1 -1317: slli s7, s8, 2 - sll t5, s10, sp - mulh t5, a5, t0 - sltu s5, s7, tp - or t5, sp, ra - div s7, t2, a2 - slti a3, a2, -5 - sltu gp, t4, s7 - c.nop - and tp, s3, s2 - c.or a3, a5 - xori s3, t3, -706 - c.lui t4, 14 - c.andi a0, 31 - srai s7, s9, 23 - sltu gp, s8, s1 - c.slli a4, 29 - srli s0, s10, 20 - sub t1, a6, s5 - c.xor s1, s0 - add s10, sp, s8 - bne a3, t5, 1351f - .4byte 0x00100073 # ebreak - andi t0, zero, 311 - andi s3, t5, -178 - nop - c.add a4, sp - c.srai a4, 28 - nop - csrrwi a6, 0x340, 25 - mulhu t2, a7, a1 - addi t0, s9, -858 - sltu t5, zero, t6 - .4byte 0x00100073 # ebreak -1351: lui zero, 974384 - c.srai s1, 7 - c.srli a0, 4 - srai s10, s7, 17 - slti s2, s6, 215 - slli a4, s2, 17 - c.slli s5, 27 - bne s1, s8, 1362f - andi tp, sp, 903 - csrrwi gp, 0x340, 6 - csrrs t6, 0x340, t6 -1362: csrrc s1, 0x340, s9 - divu t6, gp, gp - div gp, gp, a6 - csrrw s2, 0x340, a3 - slti t4, s8, -234 - xori t4, t1, -13 - blt t3, a5, 1374f - slli a6, a3, 18 - nop - auipc s7, 731053 - csrrsi tp, 0x340, 31 - csrrw t4, 0x340, a2 -1374: xori zero, s6, -323 - slli a1, s11, 23 - beq a5, t5, 1392f - beq s8, t4, 1385f - lui t2, 1028653 - srli t1, a0, 23 - srli a2, s10, 0 - addi t1, a3, -844 - c.addi tp, -30 - bgeu s11, gp, 1393f - and t6, t3, s0 -1385: mulh t0, s9, s0 - csrrci t4, 0x340, 23 - mulh s3, a1, t5 - c.add s10, s5 - csrrc ra, 0x340, s11 - srai zero, t6, 20 - auipc a7, 972982 -1392: ori a6, s0, 478 -1393: auipc a0, 1018773 - remu zero, s4, s10 - rem a2, s11, a5 - srai a3, s6, 7 - c.addi t6, -19 - mul t2, a0, t4 - srli t3, a4, 15 - bltu s7, s1, 1408f - beq s2, zero, 1406f - c.mv s6, a7 - c.nop - blt gp, a1, 1412f - .4byte 0x00100073 # ebreak -1406: c.li a5, 4 - c.slli s6, 14 -1408: blt sp, t1, 1422f - bltu a7, a5, 1421f - c.ebreak;c.nop; - sll t0, s6, s6 -1412: c.sub a1, s0 - mulhu s5, gp, a6 - c.nop - bltu s10, s3, 1417f - beq gp, zero, 1436f -1417: c.mv s7, a1 - csrrwi s6, 0x340, 20 - c.nop - xor a1, a3, gp -1421: c.and a2, a0 -1422: c.xor a5, s1 - srli a4, s7, 11 - add s4, a3, a4 - srl a6, s9, s10 - and tp, s4, t6 - blt s7, tp, 1446f - sll a1, t5, a2 - .4byte 0x00100073 # ebreak - and a2, s9, s9 - xori s10, ra, 666 - c.xor s1, a4 - c.addi s5, 1 - slt s0, t6, tp - addi gp, zero, -508 -1436: divu a0, a0, a3 - srai a6, a7, 5 - csrrs a2, 0x340, a2 - slti a4, a1, -739 - c.beqz a0, 1444f - div a1, a3, t6 - mulhu ra, tp, s6 - addi s2, t0, -849 -1444: remu s7, a3, a0 - .4byte 0x00100073 # ebreak -1446: slt t3, t3, s8 - slti a4, a5, -577 - csrrci gp, 0x340, 23 - remu t3, a1, a6 - c.or a1, a1 - c.beqz a3, 1453f - addi t1, gp, -554 -1453: c.and a2, a0 - sltu t6, gp, sp - c.sub a2, a0 - csrrw a3, 0x340, s4 - c.addi s7, 13 - slli s1, a1, 21 - mulhsu zero, t5, t0 - ori a5, s10, -463 - bltu a7, a5, 1479f - c.li t5, 3 - sll s10, a5, s1 - c.and a2, a5 - c.xor a2, s1 - bne s3, a0, 1468f - and a7, t4, zero -1468: c.add s11, a4 - sll gp, s5, t1 - csrrci a0, 0x340, 16 - c.li s4, 25 - sltiu a3, s6, 417 - c.mv s11, s8 - c.bnez a2, 1486f - sub t2, ra, a3 - csrrci zero, 0x340, 25 - srai a5, s6, 7 - sll s3, s6, s8 -1479: beq t0, s8, 1495f - nop - sub s10, a7, s1 - bgeu tp, s1, 1490f - addi a7, t0, -771 - beq tp, t1, 1498f - sll s5, s3, t0 -1486: xori s0, a6, -354 - c.nop - csrrwi gp, 0x340, 8 - slli s2, a4, 9 -1490: c.xor s1, s0 - bge s6, s6, 1499f - c.bnez a5, 1511f - c.addi ra, -9 - bne a0, sp, 1513f -1495: or s3, s4, a2 - c.sub a3, a3 - slt a6, s4, a0 -1498: sll a7, a0, a1 -1499: bge s2, t2, 1507f - csrrw s6, 0x340, s10 - lui t6, 306045 - c.beqz a4, 1510f - rem a5, a5, s9 - and a5, s4, s0 - c.srai a1, 2 - mulhu a6, a0, gp -1507: srl t0, s4, s3 - andi t2, a0, -416 - sltiu gp, gp, -670 -1510: c.li s2, -8 -1511: .4byte 0x00100073 # ebreak - bltu t4, a2, 1518f -1513: c.addi s5, -31 - blt a3, t1, 1518f - c.li ra, -23 - bne t2, t0, 1528f - csrrw zero, 0x340, a1 -1518: c.ebreak;c.nop; - slti a7, zero, 317 - c.lui s3, 31 - c.li s4, -27 - slt s5, t6, s4 - csrrsi t1, 0x340, 5 - and t2, a2, tp - addi tp, a5, 836 - beq t0, s7, 1538f - andi gp, ra, -398 -1528: c.slli t4, 2 - slt t2, t0, s3 - c.beqz a3, 1548f - bge t6, s9, 1539f - slli t6, t2, 7 - c.and a3, a5 - csrrwi t3, 0x340, 10 - csrrc t2, 0x340, s10 - srl s7, s2, s7 - c.li a2, -30 -1538: csrrs ra, 0x340, gp -1539: mul s6, gp, t3 - c.bnez a4, 1559f - c.ebreak;c.nop; - div s6, s11, s5 - c.or a3, a4 - c.lui t0, 7 - c.beqz s1, 1549f - c.mv a2, s2 - sll t0, ra, a5 -1548: auipc t0, 477002 -1549: c.add t1, s2 - c.li a5, 21 - srai s6, a1, 25 - beq t0, s2, 1554f - sll s2, t3, a0 -1554: csrrsi t5, 0x340, 11 - csrrwi t6, 0x340, 9 - slti t4, t3, -881 - div tp, s7, s6 - c.srai a4, 18 -1559: mulhu s5, a1, a0 - sltu a6, s3, a2 - lui ra, 139249 - csrrsi s5, 0x340, 10 - .4byte 0x00100073 # ebreak - c.and a5, a2 - .4byte 0x00100073 # ebreak - srli a5, ra, 2 - sub t3, s10, t4 - c.slli a7, 23 - c.li a0, 5 - rem s7, s8, t1 - csrrwi s1, 0x340, 0 - slli s0, s4, 18 - blt t6, t0, 1583f - la s4, region_1+15360 #start load_store_instr_stream_2 - la t6, region_1+2522 #start load_store_instr_stream_1 - la a1, region_1+10669 #start load_store_instr_stream_0 - lh s10, -62(s4) - lw s3, -56(s4) - lb s1, -13(a1) - lb s6, 18(s4) - lw a0, -938(t6) - lbu a5, -165(t6) - sb t3, 23(s4) - lbu a7, -57(a1) - lw t5, -862(t6) - lb a5, -577(t6) - lhu tp, -49(a1) - sb a0, -877(t6) - sh zero, 14(s4) #end load_store_instr_stream_2 - sb a2, 639(t6) - lbu t2, 41(t6) - lhu a5, 27(a1) - sb a5, -158(t6) - lbu ra, 836(t6) - sb a6, -25(t6) #end load_store_instr_stream_1 - lbu s1, 22(a1) #end load_store_instr_stream_0 - csrrci s7, 0x340, 10 - addi t0, t2, 539 - mul s5, s3, t3 - c.andi a1, 19 - c.xor s1, s0 - srli a2, s0, 1 - csrrc t5, 0x340, t5 - csrrc a5, 0x340, a4 - .4byte 0x00100073 # ebreak -1583: addi s7, s3, 29 - csrrw s0, 0x340, t3 - nop - auipc a0, 935182 - csrrc a7, 0x340, s2 - bne t0, s6, 1596f - divu gp, s11, zero - c.addi a3, -30 - srl t5, s0, s5 - mulhsu s11, t4, ra - nop - sll a5, s9, s9 - c.lui s5, 16 -1596: c.li s10, 10 - c.mv tp, s3 - sll s11, s9, s0 - mulhu t0, sp, t6 - addi t0, t5, 481 - sltiu s6, a5, 639 - or s10, s8, t2 - c.bnez a1, 1617f - csrrsi a6, 0x340, 29 - c.bnez s1, 1613f - srai a0, tp, 21 - mulhu s7, s6, s0 - srl t2, t1, s2 - remu ra, s1, s11 - csrrci t0, 0x340, 20 - srl s10, t4, s8 - c.sub a3, a5 -1613: c.mv t5, t0 - c.andi s1, 21 - slt s1, t5, a2 - c.li s6, 28 -1617: xori t2, a4, -699 - srl a7, a3, tp - csrrwi t1, 0x340, 20 - sll a3, s8, zero - mulh s11, zero, t2 - mulhu t3, s7, s1 - bge s4, a6, 1625f - slt s4, a2, t2 -1625: or a5, t0, s6 - c.bnez a0, 1632f - c.nop - c.mv a4, s9 - slli s4, s9, 3 - sub a7, s6, ra - bgeu s8, a7, 1647f -1632: c.slli a2, 27 - andi s0, s10, 24 - csrrc a3, 0x340, s6 - div a7, t0, t4 - rem zero, s8, s2 - mulhu ra, gp, a6 - bne a2, a4, 1652f - xor t6, t5, s11 - csrrwi s1, 0x340, 28 - c.li a2, -6 - csrrw s5, 0x340, s7 - c.beqz a0, 1648f - andi s1, s6, 471 - srli t5, t3, 0 - xor a1, s5, tp -1647: sltu s7, s3, s1 -1648: c.lui a3, 10 - c.ebreak;c.nop; - addi a2, gp, -368 - divu gp, s7, s8 -1652: slti t4, s2, 950 - auipc s7, 809965 - div a0, a5, t1 - c.xor s1, s1 - bne t5, s11, 1669f - blt gp, s0, 1677f - c.andi s1, 19 - c.xor a3, a0 - c.xor a3, a2 - blt t3, a6, 1680f - remu a2, s1, s3 - c.li t4, 1 - mulh a5, t4, t4 - remu s5, s0, zero - csrrwi s1, 0x340, 12 - slti gp, a5, 972 - csrrsi t5, 0x340, 2 -1669: slti a0, a4, 704 - bgeu tp, tp, 1682f - divu s7, s10, s10 - sra t5, t5, t1 - csrrs s4, 0x340, a6 - slti a2, a6, -219 - nop - c.bnez a4, 1695f -1677: c.lui s11, 4 - sltu s6, s8, s11 - rem s6, t5, zero -1680: c.bnez s0, 1688f - csrrsi s10, 0x340, 30 -1682: c.slli ra, 30 - c.or s0, a4 - mulhu s0, a2, s6 - srl t4, gp, s0 - csrrs s10, 0x340, s11 - csrrs tp, 0x340, s7 -1688: slti t4, t4, 643 - divu a2, s2, a7 - c.lui gp, 27 - andi s5, a7, -464 - sltu t4, a0, zero - mul t4, t2, s2 - div s7, a4, a1 -1695: xor t6, s2, a2 - c.and a5, a1 - and t5, a2, t1 - csrrwi s3, 0x340, 27 - c.andi a1, -24 - mulhu a2, t0, t3 - mulhsu t4, a6, tp - xori s7, a5, -30 - bltu s9, s5, 1705f - rem s1, s2, gp -1705: bltu sp, gp, 1721f - addi t1, s9, -14 - mulh s11, a3, a1 - mul s11, s4, ra - csrrci s11, 0x340, 2 - divu zero, s11, t1 - c.nop - .4byte 0x00100073 # ebreak - addi a7, t1, 857 - c.bnez a1, 1719f - c.lui a5, 12 - c.add a2, t6 - mulh a3, a6, t1 - ori a6, a0, 655 -1719: c.bnez a5, 1739f - c.bnez a3, 1734f -1721: c.lui a6, 27 - slti a6, t0, -580 - sra t2, s3, s2 - rem a2, zero, tp - mulhu t5, a0, t5 - slli s0, gp, 13 - c.nop - mulhsu gp, sp, a0 - sll s0, s10, t3 - nop - ori a3, s9, -748 - csrrsi s11, 0x340, 24 - mulh t6, s4, s9 -1734: nop - and gp, a1, s1 - slti s2, s10, -351 - c.nop - c.addi t3, -9 -1739: c.bnez a1, 1743f - csrrw t5, 0x340, s0 - bne zero, sp, 1745f - csrrsi t0, 0x340, 3 -1743: c.addi t3, 26 - sub s1, s2, t2 -1745: c.nop - csrrwi t6, 0x340, 19 - csrrsi a0, 0x340, 21 - sra a3, s2, s7 - mul a1, t1, s3 - c.ebreak;c.nop; - sub s0, a7, a3 - div a3, s10, s0 - beq s11, s2, 1772f - blt s1, s3, 1760f - nop - mul a7, s9, s0 - and s2, s0, a7 - srl s3, sp, t3 - c.sub a3, a5 -1760: andi gp, gp, -557 - .4byte 0x00100073 # ebreak - c.or s1, a0 - slli t4, t3, 27 - sltiu s4, s4, -147 - srl a3, t4, s10 - c.slli s5, 19 - slti s3, s0, -546 - c.lui s2, 17 - nop - csrrsi a7, 0x340, 16 - c.andi a2, 15 -1772: slti s5, s7, 713 - xori s11, s7, -31 - blt t4, s4, 1782f - lui gp, 721957 - bltu a6, a2, 1784f - c.xor a0, a0 - c.nop - andi s6, s0, 319 - csrrci s11, 0x340, 20 - c.andi a0, 12 -1782: c.and s0, a2 - c.andi s1, -3 -1784: nop - beq t3, s10, 1798f - mulhu s10, t4, t5 - beq s11, a1, 1789f - bltu ra, gp, 1804f -1789: bgeu a3, a3, 1801f - srai t1, t1, 31 - auipc a7, 639153 - mulhsu t5, s0, a4 - remu s5, t2, t1 - c.beqz a0, 1813f - srai ra, a0, 10 - csrrc tp, 0x340, tp - xor s7, t4, s9 -1798: srli t5, t4, 6 - csrrc zero, 0x340, a2 - csrrw a6, 0x340, a6 -1801: csrrci a0, 0x340, 17 - sra a6, a7, s3 - auipc s7, 847017 -1804: rem a6, s4, t3 - srli s2, a2, 5 - nop - remu a2, s4, s11 - addi s1, s7, 899 - slt t2, s2, a2 - remu t6, s2, a2 - mul a0, s9, t1 - mul zero, t6, s6 -1813: sub t4, s4, t4 - div a3, s4, gp - sll s1, t0, zero - c.addi s11, 2 - slt a6, s11, t0 - c.add a0, t1 - csrrsi t3, 0x340, 31 - c.add s3, s11 - c.bnez a1, 1837f - csrrci t2, 0x340, 9 - c.xor a0, s1 - blt a0, a4, 1838f - c.xor a2, a0 - c.bnez s0, 1846f - rem s2, s9, t3 - slli s11, t2, 29 - c.lui s6, 7 - sub t1, a2, gp - andi t0, a1, 860 - bge s11, s6, 1850f - xor s11, a1, a5 - or s5, t4, t4 - mulh a5, a0, t4 - c.beqz a5, 1844f -1837: c.or a4, a1 -1838: c.addi tp, 12 - c.sub a4, s0 - bne t6, a4, 1860f - .4byte 0x00100073 # ebreak - c.beqz a1, 1850f - csrrsi s0, 0x340, 28 -1844: csrrs s2, 0x340, s3 - c.mv a2, a1 -1846: sltu t3, s2, s0 - xor s1, s7, t6 - srli gp, t5, 16 - slti t5, a5, 553 -1850: mulh a3, t5, t5 - csrrwi gp, 0x340, 30 - csrrc s1, 0x340, t4 - srli a6, s4, 10 - blt s7, t2, 1859f - csrrsi s11, 0x340, 29 - mulh s10, s11, s7 - c.mv s11, s0 - c.addi a4, -26 -1859: c.srai s0, 12 -1860: c.mv s4, s11 - lui a0, 955192 - bge s2, s0, 1868f - csrrsi a0, 0x340, 28 - csrrwi s11, 0x340, 11 - sll a1, t4, s7 - csrrc t3, 0x340, a5 - c.srli a2, 8 -1868: c.xor a3, a4 - add s7, a6, a7 - add a5, a3, a1 - srai ra, s5, 13 - beq a3, ra, 1884f - csrrsi a5, 0x340, 6 - c.or a3, a4 - sra a1, s10, s9 - xori zero, s1, 792 - sub zero, a5, s11 - bgeu s7, a2, 1886f - remu s1, ra, a5 - bge gp, t5, 1890f - bgeu t2, s4, 1893f - c.addi t3, -26 - and t2, s10, a6 -1884: sub t3, t5, gp - andi a3, s9, -726 -1886: .4byte 0x00100073 # ebreak - c.sub a1, a2 - slt a4, a6, a3 - c.andi s0, -1 -1890: nop - sra a1, s1, t2 - c.andi a3, -4 -1893: srli s4, t2, 17 - srli t5, a6, 4 - div a2, a2, ra - sltu s1, s10, s8 - divu a7, t6, s11 - slli t0, a5, 24 - csrrci t4, 0x340, 10 - div s2, s6, gp - xori a7, a2, 96 - csrrci tp, 0x340, 16 - nop - c.and a4, a4 - and s3, s4, gp - sub tp, s2, a0 - sltu s0, s4, s11 - csrrs s10, 0x340, a1 - sll t6, a1, s11 - c.li a5, -14 - nop - rem s2, a2, zero - c.bnez a1, 1918f - csrrc zero, 0x340, a2 - csrrc t0, 0x340, s11 - slli gp, s9, 29 - csrrs t6, 0x340, s5 -1918: mul s1, sp, t5 - andi s5, s10, -959 - addi a7, s9, -658 - csrrs t5, 0x340, a4 - c.xor a2, a2 - xori t1, s11, 153 - sra t1, s2, ra - csrrsi s7, 0x340, 7 - csrrs a1, 0x340, s11 - c.ebreak;c.nop; - csrrw t5, 0x340, a2 - csrrwi s5, 0x340, 13 - nop - mulh t3, t0, s8 - sra ra, s9, t6 - c.bnez a4, 1935f - blt tp, a3, 1936f -1935: c.ebreak;c.nop; -1936: c.or a2, a5 - mulhu t0, s5, zero - mulh s4, a6, s4 - auipc a6, 35214 - c.or a3, s0 - nop - and a5, t0, a7 - slli a5, t2, 7 - sra a1, a0, tp - srl a6, t0, a4 - bgeu a4, t1, 1954f - c.addi s3, -19 - c.nop - c.srai a2, 2 - mul s4, t2, t3 - sltu t4, t3, tp - c.and a1, a2 - c.srli a1, 1 -1954: c.slli s4, 17 - csrrci s3, 0x340, 1 - slti s7, t6, 462 - csrrci s11, 0x340, 2 - csrrsi t6, 0x340, 16 - csrrsi s3, 0x340, 29 - divu s11, a6, a6 - csrrw s7, 0x340, s10 - rem a2, s10, t6 - sltiu tp, t1, 561 - c.addi tp, 16 - sra a5, t5, s1 - xor a3, s0, s4 - .4byte 0x00100073 # ebreak - mul s6, a7, a0 - c.lui t6, 3 - c.srli a4, 17 - and tp, a3, t3 - c.addi s1, 30 - csrrc a2, 0x340, a5 - srl a3, s4, a5 - sltu s2, s1, t0 - c.srai a2, 13 - mul s6, s2, t0 - c.andi s0, -19 - sltiu a7, s9, -884 - sll t5, a3, s7 - c.srai a3, 26 - andi a6, tp, 798 - c.addi s1, -16 - csrrs a7, 0x340, t6 - c.bnez s1, 2004f - c.andi s1, 6 - sltiu t5, a2, 786 - auipc s1, 869020 - rem s11, t6, a7 - bne s5, t5, 2010f - c.add s6, a4 - c.mv s7, s11 - mulh a3, tp, a7 - c.or a1, s0 - mulhu t4, s3, zero - mul s11, s6, s0 - csrrwi a1, 0x340, 8 - c.srai s1, 28 - andi t0, t4, -893 - c.ebreak;c.nop; - ori gp, s4, -570 - bge a3, a5, 2008f - mulhsu s3, a7, t1 -2004: c.srai a5, 3 - c.add s6, a1 - bne t6, s11, 2008f - xor a3, t1, sp -2008: rem s6, sp, a3 - div s1, s6, a0 -2010: c.andi s1, -16 - c.and a1, a3 - c.andi a1, -31 - c.andi a4, 0 - c.add s4, t5 - ori a3, s1, 96 - beq a2, t4, 2021f - slti a4, t1, 528 - and t0, a2, t5 - c.srli s1, 26 - c.srli a2, 27 -2021: srli t1, s6, 20 - c.srli a5, 23 - mulhsu a7, sp, t5 - mulhu t3, a6, t0 - xor a6, t6, ra - bgeu s5, t4, 2046f - c.bnez a3, 2039f - c.nop - bne s1, ra, 2043f - and s2, tp, s1 - csrrs s1, 0x340, gp - sltiu a4, a5, -365 - c.beqz a1, 2052f - c.sub a3, a1 - csrrw t5, 0x340, t5 - c.lui s11, 5 - remu s2, s3, t5 - bltu a0, a2, 2054f -2039: slli a4, ra, 30 - .4byte 0x00100073 # ebreak - c.mv s1, s10 - mul t1, a7, s1 -2043: bne s5, s10, 2045f - c.beqz a0, 2048f -2045: bltu zero, s2, 2053f -2046: c.srli s1, 7 - c.slli a1, 6 -2048: nop - andi t0, s3, -421 - c.srai a0, 6 - addi a0, s8, 471 -2052: xor s4, sp, ra -2053: ori s3, s4, -11 -2054: csrrwi s11, 0x340, 5 - c.sub s0, s0 - c.mv t6, s4 - sll t1, a1, ra - csrrc s10, 0x340, zero - srai ra, t5, 7 - sltiu s4, t6, 430 - bge t6, s8, 2063f - csrrwi a0, 0x340, 1 -2063: csrrs t0, 0x340, t3 - csrrw s6, 0x340, s3 - lui s0, 31833 - nop - c.andi a3, 10 - srl t2, s10, s4 - div a7, tp, s8 - c.nop - c.nop - csrrsi ra, 0x340, 23 - mulh a6, s10, t4 - sll t1, gp, a1 - addi t3, t1, -725 - xori s5, s1, -324 - and t5, a5, s3 - sra t6, s7, s10 - xori a2, a7, 511 - bge zero, s9, 2085f - c.beqz a2, 2099f - mulhu a4, a2, s0 - bgeu s8, s1, 2102f - divu a4, s3, t6 -2085: sltu s1, t3, a7 - addi s0, a4, 451 - beq tp, gp, 2101f - mulh zero, t6, s5 - c.andi a1, -4 - slt s7, a1, a2 - nop - c.xor a3, a2 - sltu s4, a1, s10 - divu a2, tp, t3 - c.srli a1, 27 - c.beqz a4, 2102f - sltiu a5, s8, -170 - remu a6, gp, t3 -2099: or ra, sp, tp - slti a4, s7, 752 -2101: rem s2, t5, s4 -2102: blt sp, t6, 2110f - slti s10, gp, 336 - and ra, t5, s9 - c.slli a1, 10 - srai t3, t4, 13 - bltu t1, s9, 2126f - c.nop - srl s6, s6, t3 -2110: mulhsu s4, a0, t4 - bge a5, a4, 2115f - c.andi s0, 15 - blt s8, t4, 2121f - srai s11, sp, 25 -2115: and s7, s5, a0 - beq s4, t2, 2124f - csrrsi s10, 0x340, 18 - csrrc s7, 0x340, t2 - c.srli a2, 4 - c.sub a3, s1 -2121: rem s11, t3, s1 - c.ebreak;c.nop; - bltu t4, t5, 2135f -2124: lui s2, 462320 - c.beqz a3, 2138f -2126: c.mv a6, t3 - csrrw t5, 0x340, t3 - remu s10, s8, t1 - lui t0, 558719 - slli t0, ra, 2 - csrrci a1, 0x340, 24 - c.nop - c.nop - xori t2, t6, 908 -2135: ori a0, s8, 141 - c.or a3, a1 - mulhsu t5, a1, a0 -2138: slli s3, gp, 26 - lui s6, 467426 - sltu a3, a3, t0 - or a3, a1, a7 - c.ebreak;c.nop; - beq t0, sp, 2155f - c.srli a2, 17 - sll a5, s4, a3 - c.addi t4, -10 - slt zero, t0, s1 - c.sub a2, a4 - c.addi s5, -9 - .4byte 0x00100073 # ebreak - c.mv t6, t2 - slt t5, a6, a1 - lui t4, 468730 - .4byte 0x00100073 # ebreak -2155: addi t2, s6, -904 - xori a5, ra, 993 - bge s7, ra, 2165f - c.and s1, s0 - c.and a5, s0 - sra a4, a7, zero - c.ebreak;c.nop; - nop - csrrwi s10, 0x340, 20 - sltu s6, a0, a4 -2165: sltu t4, a7, s7 - bne a6, a5, 2182f - c.srli a4, 9 - addi s1, t3, 914 - c.lui s1, 10 - rem t3, t1, s7 - slti s1, s6, 897 - c.sub a1, a5 - blt s9, s4, 2183f - srl t1, t0, s1 - c.andi s1, -29 - .4byte 0x00100073 # ebreak - c.and a4, a4 - sra s0, a7, t3 - blt gp, s4, 2187f - sltu s4, s5, s10 - slt s1, s11, gp -2182: mulhsu t0, t0, a7 -2183: andi t0, s3, 780 - mulhu s0, a2, a4 - divu a0, s3, s10 - c.addi a4, 4 -2187: beq a5, s11, 2195f - c.slli a3, 3 - c.slli s0, 15 - mulhu tp, s1, gp - c.ebreak;c.nop; - bge s10, a1, 2212f - c.slli s0, 11 - c.addi s4, 19 -2195: c.xor a1, a4 - div s11, zero, t5 - bge zero, t5, 2205f - c.and a2, a3 - c.lui a5, 4 - c.srli a1, 14 - remu a0, gp, ra - c.lui a1, 11 - divu a1, a5, zero - xor s1, a6, s0 -2205: div ra, s11, a0 - c.xor a0, a5 - lui a0, 935979 - sll zero, a5, s4 - blt s3, a5, 2222f - csrrs zero, 0x340, t1 - bne a6, a7, 2219f -2212: mulhu s4, gp, s0 - or a4, sp, t1 - lui a0, 76271 - slt s5, s0, s4 - srli t6, a3, 5 - slt s10, a7, t0 - c.nop -2219: bne a3, ra, 2231f - c.or a1, a5 - c.beqz a4, 2233f -2222: mul s3, s0, s5 - c.add s1, a6 - csrrc a4, 0x340, tp - c.and a4, a4 - c.lui gp, 30 - c.li t0, -5 - mulhu t4, s2, sp - auipc s2, 202567 - blt s1, t0, 2246f -2231: c.add t3, a7 - csrrci a3, 0x340, 10 -2233: csrrw a7, 0x340, s10 - bge s0, t1, 2236f - c.lui t5, 21 -2236: xori a3, a4, -698 - bltu t4, s9, 2249f - sltu s7, a1, zero - xor gp, zero, t6 - c.lui a1, 21 - slti a1, s5, -914 - divu s11, a4, s0 - c.slli a5, 21 - c.mv s4, a1 - c.xor a1, s0 -2246: and gp, s5, s0 - mul s6, s0, s7 - c.ebreak;c.nop; -2249: srli s3, s3, 16 - slti a5, t1, 661 - remu s6, s9, zero - bgeu s7, s9, 2254f - c.nop -2254: add a0, s4, s7 - sltiu t6, sp, 678 - mulhu a4, ra, a7 - c.mv s7, t3 - auipc ra, 363600 - xori s6, t1, 927 - csrrwi s10, 0x340, 28 - c.ebreak;c.nop; - sra a3, t0, a7 - slti ra, a3, -665 - andi t4, ra, 206 - csrrw t1, 0x340, s7 - bgeu s7, a2, 2282f - bge s4, a3, 2286f - mulhu t3, s8, a7 - csrrs t5, 0x340, s7 - auipc s1, 106261 - csrrc s0, 0x340, t3 - slli a7, s10, 28 - beq a0, t4, 2279f - c.addi a6, -24 - slli t3, s1, 20 - addi s2, zero, 520 - c.xor s0, a3 - c.beqz a5, 2298f -2279: auipc s1, 334252 - c.lui a0, 15 - c.sub a0, s1 -2282: c.nop - c.srai a0, 5 - bne t2, t6, 2294f - csrrw a6, 0x340, a6 -2286: c.sub a5, a3 - c.bnez s1, 2306f - and a7, t5, t3 - c.addi s11, -12 - remu ra, s4, a3 - sra t2, t3, t6 - sll gp, gp, s11 - add a0, t5, tp -2294: c.lui a0, 12 - mul t0, s8, s0 - divu s3, ra, a4 - nop -2298: beq a2, ra, 2300f - add t6, t2, a3 -2300: addi s0, s4, 827 - c.mv t3, sp - c.ebreak;c.nop; - c.li s4, -12 - rem tp, t3, a7 - nop -2306: sra s0, s9, s7 - c.ebreak;c.nop; - .4byte 0x00100073 # ebreak - c.bnez a3, 2323f - andi a4, s5, -367 - c.lui s6, 1 - remu s11, s2, s9 - c.xor a5, s1 - mulhu t6, s1, s11 - and a5, a1, a1 - remu s2, sp, s1 - ori t6, t5, -581 - divu s11, s4, s3 - c.lui gp, 22 - xor a7, s2, s8 - c.lui a0, 22 - xori t3, s6, -764 -2323: c.or a3, s0 - c.li a7, -2 - addi a1, t3, 560 - andi t6, zero, -145 - slt t0, ra, tp - csrrci t1, 0x340, 0 - divu s4, t4, t6 - .4byte 0x00100073 # ebreak - ori t6, zero, -248 - andi t1, t5, -661 - div t3, a2, t0 - xor a1, a5, a7 - c.beqz s1, 2349f - addi s4, ra, -369 - div ra, s2, s10 - c.srli a2, 10 - slti s1, s2, 1009 - sltiu ra, s1, 414 - or t0, a1, a0 - c.xor a2, a0 - bne a1, a2, 2361f - srai s6, tp, 28 - sll s7, s7, t5 - div a0, ra, a2 - csrrsi t6, 0x340, 18 - c.srli a1, 31 -2349: c.mv t1, gp - bltu zero, zero, 2369f - div tp, s4, t1 - srli s7, sp, 22 - c.ebreak;c.nop; - c.nop - divu zero, t6, t2 - sltu a3, a5, a6 - c.srai a5, 24 - .4byte 0x00100073 # ebreak - nop - c.sub a3, a1 -2361: mul t3, a3, sp - mulhu t0, ra, s7 - c.lui a2, 20 - c.lui gp, 28 - c.slli s1, 9 - c.xor a1, a5 - c.srli a3, 22 - c.add a6, s2 -2369: nop - csrrci t1, 0x340, 29 - csrrci s1, 0x340, 20 - c.slli t0, 3 - sra tp, s8, a3 - c.srai s0, 2 - andi s11, s0, 680 - nop - .4byte 0x00100073 # ebreak - c.srai a0, 2 - sll a4, s6, zero - and t6, a1, s1 - mul a5, a0, s4 - auipc t0, 986667 - c.add s5, t1 - csrrsi ra, 0x340, 23 - addi ra, s3, 421 - c.srli a0, 14 - add a0, s5, ra - and a0, tp, s10 - blt s6, t2, 2395f - c.li a3, 18 - c.srli a4, 9 - slli s2, s3, 1 - rem s10, s7, sp - srl s0, a3, s0 -2395: srl s11, a5, s11 - remu s10, t5, t3 - divu a6, s11, t1 - remu a0, s7, s0 - bge t0, s7, 2403f - andi a6, zero, 24 - ori s0, a7, -648 - mul s5, a2, s3 -2403: add s0, s4, t5 - c.lui t5, 24 - sll s11, t1, a0 - xor a6, t4, ra - mul t6, t2, s7 - ori s11, t3, 481 - srli a0, t2, 3 - c.lui s3, 23 - ori t6, a5, -830 - c.addi s11, 14 - mulhu s3, a7, gp - c.xor a4, a2 - c.beqz a4, 2420f - csrrw t0, 0x340, tp - bge s3, s9, 2425f - c.srai a3, 10 - c.bnez s0, 2424f -2420: c.sub a5, a0 - slti t4, s6, 125 - mul ra, s10, t3 - remu s4, s9, a7 -2424: auipc s11, 661482 -2425: add s6, s5, s0 - divu s11, s7, t0 - sll a0, a7, tp - sll s4, a4, s10 - c.srli a0, 1 - rem a3, s6, s1 - sub a6, t0, s6 - csrrci s7, 0x340, 3 - and a6, a5, a2 - addi t6, a0, -463 - bge t0, a3, 2439f - slli s11, s9, 13 - srai s3, a7, 26 - c.addi a1, 18 -2439: nop - xor a2, zero, a0 - csrrw a0, 0x340, a1 - c.xor a1, s0 - slt s11, s1, s1 - c.addi a2, -24 - c.srli a4, 17 - rem s1, s6, t6 - and a6, s3, tp - slt t2, a5, s8 - sub s11, s10, zero - srl s10, t1, t0 - auipc a3, 772615 - c.addi t4, -7 - sltu s1, s1, s4 - bne zero, a0, 2462f - lui a2, 99638 - xor a3, ra, s10 - bgeu s9, a0, 2465f - rem t5, t5, ra - xori zero, s8, 61 - andi gp, t4, -488 - addi s5, a0, 71 -2462: slt s0, s10, t4 - csrrsi s11, 0x340, 5 - c.nop -2465: csrrs s1, 0x340, a3 - divu t1, a5, t5 - c.andi a0, -3 - and a5, s2, a7 - c.addi s0, -30 - bgeu a1, a4, 2472f - beq a2, s1, 2487f -2472: srli a2, s0, 26 - sltu s0, t4, a5 - c.nop - c.sub s1, a4 - mulhsu a6, t1, s2 - div a3, a0, tp - c.beqz a2, 2483f - c.nop - sub a3, t5, s1 - c.bnez a2, 2500f - auipc a2, 480393 -2483: c.ebreak;c.nop; - xori t5, s8, -83 - c.srli a3, 3 - beq sp, s5, 2506f -2487: slli s2, t2, 12 - add t1, a1, a7 - slt t0, s5, a5 - blt s9, a1, 2510f - rem s10, s2, s0 - slli a1, t4, 26 - c.srli a4, 12 - sra a6, t2, s0 - c.bnez a3, 2499f - bne ra, ra, 2508f - ori s4, s4, -309 - divu t0, a7, s1 -2499: or s1, a1, gp -2500: c.srai a2, 3 - and s2, tp, t4 - beq s10, t6, 2504f - csrrsi a2, 0x340, 21 -2504: rem t2, t6, t5 - c.and a4, a5 -2506: sltu a0, s10, s5 - ori s0, a7, -222 -2508: addi a3, a5, -822 - bge s2, a3, 2521f -2510: c.andi a1, 12 - srai gp, a7, 26 - c.ebreak;c.nop; - ori s3, zero, -527 - c.bnez a2, 2522f - or zero, a2, gp - c.xor a1, a2 - xor s4, s7, tp - csrrw s4, 0x340, s1 - ori s11, a3, 34 - bltu s3, t2, 2528f -2521: and a2, gp, tp -2522: srl zero, a0, s8 - or t2, s1, s10 - csrrc tp, 0x340, a1 - c.ebreak;c.nop; - sll s4, s7, t3 - bgeu s9, s1, 2545f -2528: c.add a2, s10 - add t6, a1, ra - c.nop - csrrs zero, 0x340, s3 - csrrw t3, 0x340, ra - csrrc s5, 0x340, t6 - slti zero, sp, -563 - csrrci s5, 0x340, 19 - mulhu a4, gp, t1 - c.lui t5, 7 - c.andi s1, 30 - sltu t1, ra, sp - c.bnez s0, 2559f - c.beqz a0, 2555f - slti s6, a0, 632 - rem s10, s7, a3 - or s5, s4, t0 -2545: sltiu a0, s1, -407 - csrrs t0, 0x340, s2 - bgeu zero, s11, 2555f - c.ebreak;c.nop; - addi s11, s4, 139 - c.lui a4, 31 - c.sub s1, a3 - and t1, tp, a5 - csrrci t6, 0x340, 6 - c.or a0, a4 -2555: c.xor a0, a3 - add a7, s2, a4 - divu a3, s7, t0 - auipc a6, 399601 -2559: mulhsu s0, tp, a0 - csrrc t2, 0x340, s10 - srli t3, t2, 9 - nop - csrrsi a2, 0x340, 0 - slti s11, sp, 280 - csrrwi t6, 0x340, 31 - c.add t1, s10 - ori s1, t0, -576 - mulh a6, a2, a5 - c.lui a5, 23 - c.bnez a0, 2572f - c.beqz a1, 2587f -2572: srai s6, a0, 24 - bltu ra, s1, 2585f - sll s5, ra, s10 - mul t4, t2, ra - beq t0, s9, 2582f - c.slli tp, 2 - beq s11, s8, 2592f - srl s2, s1, a1 - blt s2, t0, 2590f - c.nop -2582: sub t3, a4, t3 - ori gp, s4, 445 - slti t2, s2, -748 -2585: srl a4, a7, gp - c.srli a0, 29 -2587: lui zero, 835328 - sltu a4, s5, a0 - csrrc a1, 0x340, s8 -2590: addi s10, a2, 682 - c.bnez a1, 2610f -2592: sra s0, s4, t5 - sll a5, zero, s2 - c.xor a5, a4 - c.sub a3, a4 - and gp, s2, s11 - c.andi a1, 6 - srl a1, a3, a3 - divu a3, a4, s4 - xor a5, s0, s8 - c.and s0, a1 - c.srli a1, 24 - c.srli a2, 29 - remu s11, s10, t1 - add s10, t1, s4 - c.bnez a3, 2619f - mul a6, s2, t6 - c.andi a4, 6 - add t3, t0, a1 -2610: blt a1, a0, 2618f - c.mv a2, t3 - csrrwi a0, 0x340, 23 - c.add s5, t6 - csrrc t4, 0x340, a5 - sltiu a7, a2, 711 - xor t1, t6, t1 - auipc t4, 1038754 -2618: rem s0, tp, a1 -2619: csrrsi t2, 0x340, 31 - auipc t0, 184266 - sll a7, t6, s7 - srli a1, a4, 27 - csrrci t0, 0x340, 31 - bltu t3, t2, 2630f - c.sub s1, a5 - csrrsi t0, 0x340, 8 - mulhsu a3, ra, s11 - srli a3, t0, 5 - auipc s6, 157168 -2630: mulhsu t4, s8, t1 - c.addi a2, -13 - bgeu t3, gp, 2637f - slt ra, t4, s10 - srli t5, t4, 16 - mulhu a6, a0, a2 - div s3, a1, a1 -2637: mulhu a6, s2, sp - srli s3, s7, 15 - ori t1, a2, -579 - sll s10, a5, t1 - c.srli a4, 22 - c.mv t1, t0 - ori s10, a2, -390 - sub s6, s10, t3 - c.nop - blt t2, s3, 2654f - c.srai a4, 13 - c.sub s1, s0 - sltu s1, ra, t0 - addi t2, a6, 40 - xori s10, sp, -888 - csrrsi t0, 0x340, 8 - div s1, t5, s0 -2654: add s11, t2, zero - c.bnez a2, 2663f - c.or a4, s1 - lui t0, 234487 - rem t3, a2, s9 - or tp, a1, tp - bltu a4, ra, 2664f - c.ebreak;c.nop; - csrrs s1, 0x340, s0 -2663: c.sub a5, a4 -2664: sra a1, s5, a6 - c.or s1, s0 - slti t2, t1, -76 - c.sub s1, a1 - csrrsi t1, 0x340, 25 - bge ra, zero, 2675f - xor s4, a7, s10 - sltu zero, a2, t0 - slli a5, s10, 26 - xor tp, a1, t3 - and s10, s1, t6 -2675: csrrwi a2, 0x340, 7 - csrrc s6, 0x340, s0 - c.nop - blt t1, s4, 2696f - sltiu s10, s11, -744 - c.bnez a5, 2694f - andi t6, s9, -844 - lui ra, 952731 - ori t3, a4, -74 - c.or s0, a0 - mul tp, s1, s7 - csrrw s5, 0x340, t2 - csrrwi a6, 0x340, 17 - c.add t5, s6 - and a7, s10, s9 - csrrw a1, 0x340, t4 - c.and s0, a1 - mulh a0, t5, s10 - bge a3, a0, 2705f -2694: c.srai s1, 4 - c.li s11, -26 -2696: c.slli t4, 2 - csrrs a1, 0x340, s8 - csrrc tp, 0x340, zero - c.beqz a3, 2718f - bltu a7, a0, 2708f - addi a3, sp, -443 - sll t1, t1, a7 - beq t5, t3, 2705f - mulhsu s2, a0, a7 -2705: c.bnez a4, 2725f - auipc s2, 443629 - remu s0, tp, t4 -2708: csrrci s4, 0x340, 17 - bne s1, s1, 2717f - xori a3, a6, 765 - c.sub s0, a1 - c.mv t4, s0 - c.slli t4, 5 - c.li s4, -15 - c.bnez a3, 2731f - add a5, s8, s2 -2717: c.lui a5, 1 -2718: csrrci s7, 0x340, 17 - slt t0, a1, gp - nop - mulhsu t2, s4, a0 - c.beqz a5, 2741f - c.beqz s0, 2736f - div s3, tp, t3 -2725: c.slli t5, 16 - mulhu s0, t5, s5 - csrrs zero, 0x340, zero - slt t6, zero, s11 - c.addi a7, -22 - lui s7, 830727 -2731: xor a4, s8, a0 - csrrwi zero, 0x340, 24 - c.beqz a2, 2735f - andi a6, ra, -527 -2735: c.andi a4, -27 -2736: sltiu a6, t2, 247 - srai s4, a6, 24 - sub a6, a4, a2 - auipc a6, 896866 - nop -2741: bgeu a2, t0, 2747f - srli s2, zero, 28 - c.addi s11, 14 - csrrw a6, 0x340, t1 - sltiu t2, t3, 3 - mulh s6, sp, t0 -2747: blt s7, t2, 2751f - c.and a5, a4 - c.addi ra, -25 - bge s5, t0, 2758f -2751: or s10, sp, zero - mulh tp, sp, a4 - remu zero, a7, t0 - csrrs s2, 0x340, s7 - blt tp, tp, 2763f - c.srai a4, 28 - c.mv gp, gp -2758: and a1, zero, a3 - csrrsi a7, 0x340, 17 - slli a6, a3, 12 - c.xor s0, s1 - slli s3, a7, 21 -2763: and s0, s2, t0 - mulh s0, t1, t0 - ori a0, s0, -35 - lui s10, 197564 - bne s2, s3, 2777f - mulh s7, s11, t3 - c.li a1, 0 - mulh s11, sp, s8 - c.lui t3, 3 - csrrci t2, 0x340, 1 - c.ebreak;c.nop; - auipc s0, 224093 - xor s10, s8, gp - c.andi a2, -15 -2777: c.sub a4, a2 - and s2, s2, zero - rem zero, s3, t0 - slli a4, s10, 11 - .4byte 0x00100073 # ebreak - csrrc s1, 0x340, t2 - beq t6, s3, 2788f - add s1, t0, a5 - c.li gp, -4 - c.bnez a1, 2794f - div s5, a7, t6 -2788: c.addi a7, 16 - nop - c.lui a1, 1 - c.add s7, t3 - mulhsu s5, s10, a5 - xor t6, s8, gp -2794: c.beqz a1, 2808f - mul s1, a7, s1 - csrrs zero, 0x340, a6 - bltu t6, t6, 2813f - div tp, s11, a1 - xori a5, s8, 508 - bne t2, s9, 2805f - csrrs s2, 0x340, a5 - c.add s7, a7 - c.bnez a1, 2805f - xori t3, t4, -967 -2805: c.andi a2, -19 - c.bnez a3, 2814f - csrrwi a4, 0x340, 6 -2808: csrrs ra, 0x340, a4 - c.srai a1, 11 - bge s10, a7, 2814f - c.lui t6, 28 - auipc s6, 321236 -2813: mulh s4, t1, s4 -2814: c.or a4, a5 - beq gp, t3, 2834f - ori t0, sp, 796 - c.ebreak;c.nop; - beq a7, s10, 2830f - xor t4, a5, a2 - andi s10, t2, 503 - c.add t4, s5 - c.beqz s0, 2842f - sub a2, s1, sp - div s2, t3, s5 - csrrwi a7, 0x340, 25 - div a4, a4, s7 - c.addi t6, -11 - c.or a5, a5 - bgeu a3, a7, 2841f -2830: c.add s1, t2 - c.srai a3, 31 - c.srai a3, 11 - slli tp, s5, 14 -2834: bge a0, a0, 2850f - c.add s3, t1 - csrrc a1, 0x340, s8 - srai a1, a0, 6 - c.li a0, 26 - slli s1, a2, 4 - div s10, a4, a0 -2841: div t3, a0, t6 -2842: blt t3, ra, 2861f - slt a1, t1, s5 - c.xor a1, a5 - csrrsi s2, 0x340, 6 - sltiu a1, t4, -73 - csrrc a6, 0x340, s1 - c.and a1, s1 - c.add s3, a5 -2850: remu a6, t2, s0 - remu t2, a7, t0 - csrrs s3, 0x340, t4 - bgeu s9, s2, 2866f - mul a0, s4, zero - beq a7, s9, 2861f - blt s0, a6, 2862f - xor t5, s4, zero - c.or s0, a2 - c.srai s0, 18 - blt s4, t2, 2879f -2861: srai s2, s5, 31 -2862: csrrwi ra, 0x340, 6 - c.andi a3, 0 - c.srai a4, 6 - csrrc s5, 0x340, t0 -2866: andi s5, s6, 292 - c.slli s5, 31 - c.nop - addi a4, s6, 6 - auipc s11, 179354 - mulhu s5, t2, s3 - c.srai a1, 27 - or s1, s4, t3 - ori s2, t3, -314 - or s6, s11, s2 - c.lui s2, 11 - c.bnez a3, 2885f - srli s11, a6, 4 -2879: c.sub a3, a3 - beq tp, s4, 2884f - c.xor a3, a1 - sll t3, a2, s4 - slt s2, s6, a3 -2884: xor t6, a5, t5 -2885: addi t1, sp, 393 - bne t4, s11, 2894f - c.ebreak;c.nop; - addi t6, t1, -133 - c.slli s2, 3 - csrrs a6, 0x340, t2 - mulhu s6, s3, a0 - divu s1, zero, tp - .4byte 0x00100073 # ebreak -2894: c.andi a5, -5 - c.xor a5, a1 - c.addi a0, -28 - c.srli a4, 20 - csrrc a6, 0x340, tp - mulh t5, s3, t4 - bne a3, t1, 2902f - c.addi ra, -20 -2902: c.andi a5, 25 - c.and a4, a1 - c.and s0, a3 - bne s10, t5, 2921f - c.nop - csrrci t1, 0x340, 23 - andi s2, s8, -825 - .4byte 0x00100073 # ebreak - mul a4, sp, s2 - c.addi t2, -29 - csrrwi a2, 0x340, 14 - srli t5, a2, 17 - auipc a1, 144172 - csrrsi t1, 0x340, 1 - divu a5, s10, a7 - c.add s11, sp - mul s4, t6, a7 - mulhsu a7, s2, s1 - sra t5, a0, sp -2921: csrrci a7, 0x340, 10 - c.ebreak;c.nop; - sltu a0, ra, tp - slti s10, a6, 778 - div zero, s3, s6 - csrrsi s5, 0x340, 10 - .4byte 0x00100073 # ebreak - or s3, t2, tp - add zero, s6, a4 - bne sp, s8, 2949f - and tp, gp, zero - c.addi a0, 25 - add s11, a7, s8 - blt t0, a6, 2952f - srl zero, zero, ra - csrrci s6, 0x340, 17 - or a0, a5, s4 - bge a5, s7, 2958f - auipc s1, 245603 - mulh t2, a0, s5 - or s6, a7, s9 - sltu s5, t1, a5 - csrrci s3, 0x340, 7 - divu zero, a2, s3 - c.slli s4, 16 - auipc t1, 464925 - bgeu s0, t3, 2952f - sub a4, t5, a0 -2949: csrrci s11, 0x340, 27 - lui a2, 513029 - csrrwi gp, 0x340, 25 -2952: addi s2, t3, -598 - sra s1, s7, a5 - slt s10, a3, s11 - mulh a3, a2, s5 - sltiu a0, a2, -194 - c.lui s10, 3 -2958: csrrwi s7, 0x340, 17 - and t3, t3, s2 - c.srli s0, 28 - csrrs t2, 0x340, s7 - mulh s2, t0, s9 - bgeu t6, a7, 2967f - and gp, s11, a6 - c.and a0, s1 - c.add t4, a7 -2967: andi t1, s10, -987 - and zero, t5, s0 - bltu s4, s6, 2979f - csrrci zero, 0x340, 4 - and s2, t2, t4 - c.bnez a1, 2984f - divu s7, t2, t6 - sra gp, s3, tp - csrrci t6, 0x340, 4 - c.andi a2, -17 - xor s1, s11, t5 - ori t0, s2, -150 -2979: lui s0, 809598 - c.ebreak;c.nop; - bne tp, a1, 2989f - srai a0, s1, 8 - or a4, s4, s7 -2984: divu a6, a5, s5 - blt t5, t3, 2993f - mulh t6, s3, t4 - csrrs t5, 0x340, a2 - c.add s3, a5 -2989: slti s10, s9, -528 - or s4, s10, ra - lui a3, 883260 - divu s0, s8, a5 -2993: slli t6, t6, 10 - ori a4, a5, 568 - csrrsi a5, 0x340, 12 - div a2, a6, s6 - c.andi s1, -32 - c.xor a4, a4 - rem s3, tp, ra - sltiu s4, t0, 95 - mulhsu a6, s1, ra - csrrci a3, 0x340, 15 - csrrsi t3, 0x340, 17 - addi tp, s10, 621 - remu s10, a7, a4 - c.addi s1, 9 - remu a1, t6, a0 - .4byte 0x00100073 # ebreak - c.lui a2, 10 - slli a3, s6, 7 - bge s8, s2, 3013f - remu s5, a5, s5 -3013: mulh a5, a6, t1 - c.srai a3, 25 - c.ebreak;c.nop; - divu s6, a3, s0 - sltu a1, a7, s3 - bgeu s11, tp, 3032f - srl a1, a7, a1 - csrrc a3, 0x340, a3 - csrrw s4, 0x340, t0 - csrrci tp, 0x340, 20 - mul a1, a5, s10 - c.and s0, s1 - mulhsu gp, s9, ra - c.nop - auipc a7, 642773 - lui t0, 217485 - slti a2, sp, 641 - la a0, region_2+1502 #start load_store_instr_stream_1 - la s3, region_3+0 #start load_store_instr_stream_0 - sb a2, 11(a0) - lb s5, 36(a0) - lb t5, 35(s3) - sb t0, 12(a0) - lb s4, -21(a0) - lbu a5, 40(a0) - sb s1, 38(s3) - sw s4, 22(a0) - lb t3, -4(a0) - lbu a7, 51(a0) - lb gp, -36(a0) - lh s2, 54(s3) - lb gp, 49(s3) - lb s2, -47(a0) #end load_store_instr_stream_1 - lbu t4, 25(s3) #end load_store_instr_stream_0 - sltiu s4, t1, 137 - bltu a0, s2, 3043f -3032: remu t1, t6, t2 - .4byte 0x00100073 # ebreak - c.li t5, 29 - lui s2, 182964 - mul t5, s7, a3 - andi tp, a1, 754 - srli t3, t3, 31 - mul s1, s4, a2 - mul s11, a0, zero - csrrw a0, 0x340, s8 - bge a6, s4, 3056f -3043: c.lui a4, 17 - rem s11, s0, a2 - div s1, sp, a6 -sub_1_14: jal gp, 3f -0: c.jal 17f -1: jal ra, 10f -2: c.j 13f -3: jal ra, 0b -4: c.jal 1b -5: c.jal 15f -6: c.j 11f -7: c.j 9f -8: c.j 12f -9: c.jal 2b -10: jal ra, 16f -11: c.j 4b -12: c.jal 14f -13: c.j 5b -14: jal ra, 6b -15: jal s11, 18f -16: jal ra, 7b -17: jal ra, 8b -18: c.add s10, a3 - c.srai s0, 5 - c.or a4, s1 - c.nop - csrrw ra, 0x340, s7 - sra t1, a0, s4 - csrrsi s5, 0x340, 0 - sra s2, t1, zero - mulhu a2, zero, s7 - beq s1, t1, 3074f - divu t3, t4, s5 -3056: .4byte 0x00100073 # ebreak - sub t1, t1, t5 - srli s0, a4, 11 - bgeu a5, a5, 3064f - mulhu s0, zero, a6 - divu s11, a6, a7 - addi a3, s1, -743 - c.and a2, a0 -3064: c.beqz a5, 3066f - c.beqz s0, 3077f -3066: c.xor a3, a5 - blt gp, gp, 3075f - mul t4, t5, ra - c.xor s0, a5 - xor gp, t2, s10 - c.slli s5, 2 - c.or a2, s0 - andi a7, s3, 467 -3074: srli s7, a3, 26 -3075: blt sp, zero, 3083f - mul a3, s7, s0 -3077: csrrwi a5, 0x340, 5 - sub s11, t2, t4 - c.beqz a0, 3087f - csrrci s5, 0x340, 29 - csrrci a3, 0x340, 16 - c.mv a0, a2 -3083: c.nop - c.xor a3, a4 - add s7, a7, t1 - c.or a2, s0 -3087: mulhu t4, a4, t6 - divu s3, gp, s11 - addi gp, s7, 470 - c.sub a3, a2 - sltu s4, s6, s1 - mulhu s7, s10, s4 - c.lui a4, 10 - c.beqz a4, 3113f - sltiu s4, s9, 572 - slli a7, a2, 21 - slt a2, a2, gp - c.bnez a5, 3106f - or s6, s6, a6 - div ra, a4, a7 - nop - mulh s2, a6, a0 - divu a2, s9, s9 - la t2, region_2+1640 #start load_store_instr_stream_2 - la t0, region_2+61 #start load_store_instr_stream_1 - la a5, region_2+4330 #start load_store_instr_stream_0 - lbu gp, 29(a5) - lb a6, -11(t0) - sw t5, -124(t2) - sh t6, -1(t0) - sb s5, 10(t0) - lbu a1, 16(t0) - sh s5, 242(t2) - sb s10, -7(t0) - lw t6, 2(a5) - lb s7, 154(t2) - lb zero, 91(t2) - sb a0, -13(t0) - lhu t1, -9(t0) - lb a2, 9(t0) - lh a7, 38(a5) - lb a0, 83(t2) - sb sp, -1(a5) - lw tp, -228(t2) - sb t4, -231(t2) - sb gp, -37(a5) - lhu ra, 200(t2) - sb s4, -203(t2) - lhu s3, 15(t0) - sb t3, -15(t0) #end load_store_instr_stream_1 - lbu s4, -248(t2) #end load_store_instr_stream_2 - lbu s6, -48(a5) #end load_store_instr_stream_0 - c.nop - srli ra, a2, 11 -3106: c.andi a4, 5 - csrrci a3, 0x340, 0 - bne a4, a7, 3110f - slli t3, a0, 10 -3110: auipc tp, 941196 - srli t4, a5, 6 - slli t4, s5, 10 -3113: csrrci s2, 0x340, 16 - sll a3, s6, gp - andi a2, a2, -839 - csrrc a5, 0x340, s11 - la a2, region_0+1585 #start riscv_load_store_rand_instr_stream_10 - sb s3, -2(a2) - lb s11, -4(a2) - csrrw a0, 0x340, s1 - sw sp, 3(a2) - c.ebreak;c.nop; - lb s7, 4(a2) - c.and s1, a4 - lui s4, 380563 - mulhu a3, s11, a1 - sb t3, -16(a2) - div t6, s7, s0 - rem a6, zero, a2 - lbu t1, -4(a2) - lui s0, 344389 - sb ra, -2(a2) - c.add s5, s9 - c.slli t5, 27 - csrrci a4, 0x340, 16 - sb t2, 16(a2) - lb t1, -16(a2) - sw s3, 3(a2) - sh t2, 5(a2) - sw t1, 3(a2) - sltiu a3, s9, -273 - c.lui t1, 8 - lb s2, 16(a2) #end riscv_load_store_rand_instr_stream_10 - blt s0, a3, 3125f - csrrc t1, 0x340, s10 - srli a1, s3, 27 - div a0, s9, t1 - sll s0, s7, a6 - c.li a0, -19 - bne a4, s2, 3139f - .4byte 0x00100073 # ebreak -3125: bge t6, t6, 3135f - .4byte 0x00100073 # ebreak - sltiu s0, s8, 5 - slti a6, t5, -940 - mulhsu t6, ra, t6 - or s1, t4, s1 - or t0, t0, s4 - srai a2, a5, 10 - bne s8, t6, 3147f - bne s11, t4, 3153f -3135: mul t0, a3, tp - sll t1, t2, s11 - c.ebreak;c.nop; - rem s4, tp, a2 -3139: and a6, t2, s0 - lui t4, 74847 - xori gp, t2, 512 - c.srai a5, 21 - c.andi s1, 0 - mulhu t1, t4, s4 - csrrc a7, 0x340, tp - bge s10, s6, 3162f -3147: xor t2, s10, a2 - auipc t6, 891276 - addi s10, sp, 184 - srli gp, s9, 23 - c.and a3, a0 - slli s1, s2, 15 -3153: bne s5, ra, 3166f - csrrwi a0, 0x340, 22 - add t1, t5, s2 - csrrs t6, 0x340, tp - ori s5, sp, 408 - c.add t0, t4 - beq s6, a2, 3177f - divu s3, s8, t4 - beq a0, s7, 3167f -3162: xor a4, t6, a0 - addi s11, s0, 536 - srai a3, t4, 7 - mulh a6, t2, s3 -3166: bgeu tp, s7, 3172f -3167: c.li t1, 2 - sltu a2, a3, s5 - divu s4, a7, ra - c.and s1, a5 - mulh a7, s11, a5 -3172: csrrs s11, 0x340, s7 - c.add s3, s9 - mulhu a0, a6, t5 - div a2, s3, s6 - slli s2, a3, 11 -3177: c.andi a5, 16 - srli t5, tp, 20 - c.slli a2, 23 - beq t6, zero, 3184f - .4byte 0x00100073 # ebreak - srai s4, s6, 23 - c.srli s0, 31 -3184: andi s6, a7, 720 - ori a7, tp, -365 - c.andi a5, 3 - slt t2, a7, gp - or s0, t2, t3 - c.lui s11, 2 - c.li s0, 31 - sra gp, a2, sp - and s6, gp, a4 - beq t6, a4, 3213f - xori s1, s2, 815 - nop - auipc a2, 966775 - and t5, a7, s2 - c.addi t0, -8 - srl s7, s2, a4 - csrrs a1, 0x340, t2 - xor tp, t1, s10 - c.xor a5, a0 - add s7, s4, s6 - and a0, a0, s4 - mulhu s0, gp, t1 - c.srli a5, 4 - .4byte 0x00100073 # ebreak - div a2, s8, t1 - c.and a5, a3 - csrrs s3, 0x340, t0 - bgeu s6, s3, 3215f - bne s0, zero, 3214f -3213: mulhu s6, s7, t4 -3214: sra a0, sp, a6 -3215: c.beqz s0, 3234f - c.bnez s0, 3236f - auipc s2, 788099 - srli t1, a1, 4 - mulhu a7, a7, gp - blt a5, s6, 3222f - slti s3, a7, 148 -3222: lui s2, 121160 - c.li a4, -21 - c.add a1, t5 - bltu a5, s7, 3237f - c.sub a3, a3 - c.slli a0, 19 - or s3, s8, a7 - xori a5, zero, 843 - xor a1, t5, gp - c.ebreak;c.nop; - c.xor a5, a5 - sltiu s10, t0, 997 -3234: divu s6, t0, t6 - beq s1, a5, 3243f -3236: rem s6, s3, s5 -3237: sra t2, s0, a2 - auipc ra, 696490 - remu s2, gp, s6 - add s3, a5, tp - srai zero, gp, 14 - c.mv a3, a2 -3243: .4byte 0x00100073 # ebreak - csrrw t3, 0x340, s0 - c.lui a1, 8 - bge s3, a7, 3258f - mulh s10, a5, s3 - slti gp, s0, 301 - c.or a5, a5 - csrrw ra, 0x340, gp - lui t2, 146886 - divu a6, s10, t4 - slli a6, a3, 28 - mulhsu t2, t0, s8 - ori t5, tp, 673 - c.slli ra, 17 - csrrci a7, 0x340, 19 -3258: add s1, tp, s0 - div a3, s9, a0 - mul a2, t4, s10 - add a3, tp, s6 - csrrc s7, 0x340, a7 - c.srli a2, 8 - lui s3, 452631 - c.addi t3, 28 - sll a7, s4, tp - csrrc s7, 0x340, tp - csrrs zero, 0x340, t3 - srai tp, s6, 22 - c.srli a0, 26 - mulhsu s0, a2, s6 - and t4, a4, a7 - slli a4, s8, 2 - c.and a4, a3 - lui zero, 839047 - sra tp, zero, tp - sub s1, a1, gp - mul t6, t1, s8 - sltiu s7, s0, 1002 - c.addi t6, 19 - andi s5, a0, 891 - mulhu a3, a5, s8 - csrrci t5, 0x340, 12 - xor t0, s6, s7 - bne s9, t5, 3293f - bne s3, t1, 3300f - c.andi s0, 5 - csrrci s6, 0x340, 26 - c.addi a6, 23 - c.mv t2, t6 - addi a7, s4, 287 - srl s10, t4, t1 -3293: c.xor s1, a4 - mul a4, t5, t2 - bltu s9, s10, 3307f - rem s6, t4, s6 - or zero, a7, tp - divu s4, zero, a0 - c.slli ra, 12 -3300: csrrc a0, 0x340, s8 - div s4, s2, sp - csrrsi a0, 0x340, 31 - div a1, ra, a6 - rem t2, a2, t5 - bne s9, tp, 3310f - srli t1, t1, 0 -3307: csrrw s0, 0x340, s5 - blt s6, s0, 3313f - srl s7, s6, a0 -3310: c.mv ra, s4 - csrrc ra, 0x340, t3 - c.beqz a0, 3320f -3313: c.or s1, s0 - mulhu tp, a2, t2 - c.nop - xori s7, s4, 556 - mulh gp, ra, tp - c.addi ra, 9 - divu a0, t1, s8 -3320: c.li t4, 7 - mul s0, s2, s6 - c.srai a0, 8 - sra a7, gp, zero - mulhu a1, s8, s4 - csrrw a2, 0x340, s5 - xor t4, s9, t2 - blt t5, s10, 3333f - c.xor a2, a4 - csrrs a0, 0x340, s6 - c.ebreak;c.nop; - csrrsi t2, 0x340, 12 - bgeu a1, s7, 3348f -3333: div t3, s0, s7 - csrrs t5, 0x340, s3 - divu a6, a0, s5 - c.nop - c.addi s5, 3 - nop - mul a1, a4, t0 - bgeu a3, s5, 3352f - c.bnez a4, 3343f - mulhsu a3, s7, s3 -3343: c.andi s0, -1 - beq s3, s6, 3362f - c.nop - c.xor a3, a4 - or s10, zero, t0 -3348: xori s2, a2, -1017 - div a2, a7, a0 - bge s4, s10, 3358f - sub zero, t1, a6 -3352: c.andi a0, 25 - c.lui gp, 5 - csrrci a3, 0x340, 23 - mulh t1, s8, a0 - mulhu s6, sp, s7 - slti tp, s2, 2 -3358: csrrci a1, 0x340, 8 - or s4, gp, t1 - srai s11, t0, 12 - csrrci s1, 0x340, 2 -3362: c.add a3, t1 - ori t3, a0, 991 - mulhsu s0, s9, s6 - or a7, ra, a2 - add a4, a5, t1 - bgeu s3, s11, 3375f - mulh s2, t6, a6 - c.lui s3, 14 - srl a6, t1, s2 - c.beqz s1, 3390f - c.ebreak;c.nop; - c.or a4, s0 - c.ebreak;c.nop; -3375: mulh s1, s5, s8 - auipc gp, 76569 - sra s0, a7, t3 - c.or a1, a2 - slli s2, t2, 3 - xori s0, s6, 787 - c.srai s0, 17 - blt a6, t4, 3394f - c.add a5, t1 - mulh a5, t5, s8 - c.and a2, s1 - sltu a7, a3, a2 - beq t6, s6, 3407f - csrrwi t2, 0x340, 8 - slli t4, a4, 23 -3390: mulhsu s4, a6, zero - c.mv a4, gp - bgeu t5, s10, 3406f - c.addi s0, -18 -3394: sltiu s2, s11, 215 - andi s11, a5, -869 - mul s7, s5, t2 - csrrci t0, 0x340, 8 - c.addi s1, 28 - add t1, s3, a7 - csrrc a2, 0x340, a0 - ori a4, s2, -684 - and a4, a2, s5 - c.li s5, 3 - csrrci tp, 0x340, 6 - c.addi a1, -22 -3406: c.bnez a4, 3418f -3407: c.sub s1, a0 - or gp, s8, s11 - slli s11, s9, 29 - mulhsu s7, zero, t1 - c.add a0, t6 - c.lui t2, 16 - mulhu t4, s11, s4 - and t5, a1, sp - srai a0, a7, 7 - nop - c.or s0, a4 -3418: csrrwi a6, 0x340, 23 - rem s7, ra, t2 - bne a4, t6, 3439f - csrrw a2, 0x340, s3 - c.bnez s1, 3428f - or t1, a0, s10 - srli t0, a7, 5 - slli a0, a5, 4 - c.andi a1, -22 - mul ra, sp, s7 -3428: bltu a5, s9, 3448f - divu a7, t0, t5 - c.srli a1, 18 - sltu t5, zero, a7 - csrrwi s5, 0x340, 17 - sltiu a7, t0, -38 - c.mv s5, ra - c.bnez a0, 3443f - bgeu a7, s5, 3441f - csrrsi s10, 0x340, 24 - c.xor a1, s0 -3439: mulhu s3, gp, s11 - and a4, a6, a0 -3441: slt s5, ra, zero - sub ra, s6, s10 -3443: beq gp, s5, 3447f - c.bnez a0, 3463f - bge s10, s7, 3453f - csrrwi s7, 0x340, 4 -3447: or a1, t0, gp -3448: bge a1, a7, 3450f - c.bnez a2, 3451f -3450: lui ra, 1044439 -3451: sltiu t1, a7, 135 - addi s3, s2, -296 -3453: srai t0, s11, 25 - csrrci a4, 0x340, 11 - c.nop - c.or a2, a4 - c.mv s11, s0 - sra a5, a3, t5 - ori ra, s4, 623 - bltu a7, a1, 3470f - xori s5, s4, 294 - slti tp, s11, -839 -3463: c.and a1, a0 - slli s5, s0, 31 - slli a1, a3, 10 - mul a1, sp, s6 - sub a2, t1, s4 - mulhu s6, zero, s1 - srl s10, s11, t6 -3470: c.li a5, -19 - sub s0, t3, zero - c.mv t4, s2 - beq s0, tp, 3478f - mulhu a1, t2, a1 - xor s11, t4, s6 - bge ra, s9, 3484f - csrrwi a5, 0x340, 7 -3478: mulh t5, a3, a3 - sltiu s11, ra, 489 - mul ra, a4, t2 - c.addi s5, -5 - mul t3, t0, t2 - mulhu t5, s9, a4 -3484: csrrc t6, 0x340, t4 - mulhu zero, a7, zero - auipc a2, 143503 - csrrs a5, 0x340, a5 - sll s11, a5, s11 - csrrci zero, 0x340, 8 - c.or s1, a2 - c.ebreak;c.nop; - csrrci s1, 0x340, 23 - c.li t2, 7 - andi a0, a3, -634 - sra a1, a2, s0 - beq s5, t1, 3500f - c.srli a4, 16 - nop - mulhu t4, tp, t6 -3500: c.li s3, 25 - bltu t0, t1, 3517f - srai t4, sp, 7 - sll t3, t1, t3 - mulhu s4, t4, s1 - addi s1, s10, 968 - srai s10, s4, 2 - c.slli a2, 12 - xori t1, t2, -765 - c.bnez a1, 3523f - c.xor s0, a2 - bltu t5, s8, 3524f - slli t1, s11, 30 - and s0, s2, sp - c.srli a0, 10 - c.beqz a5, 3523f - c.slli s7, 30 -3517: mulhu s7, gp, zero - xori s7, zero, 373 - c.sub a0, a0 - xor tp, t6, a4 - bltu a2, zero, 3526f - andi a3, a1, -18 -3523: blt t6, t5, 3533f -3524: c.srai a3, 24 - csrrwi tp, 0x340, 2 -3526: remu s4, sp, t2 - sra s5, t6, t4 - bltu a7, s7, 3544f - sltu t1, s11, a2 - srai s4, s8, 16 - c.mv a0, a5 - c.add t3, t0 -3533: add t6, s5, t6 - slt a7, ra, zero - c.or a4, a5 - sltiu gp, s4, 80 - mulhu a1, s5, s0 - mul s6, s1, a4 - mulh s7, gp, a2 - sll s1, s1, t5 - c.or a2, a1 - sltiu s7, t4, -436 - xor s0, s3, t3 -3544: ori zero, zero, -6 - sll s3, a0, tp - c.andi a3, 16 - c.sub a4, a0 - div s0, t4, gp - mul s0, s9, t3 - remu a4, a6, a4 - beq a7, t0, 3553f - c.sub a5, s1 -3553: srli a7, s4, 3 - ori t6, a0, -488 - csrrwi t6, 0x340, 15 - c.srai s1, 6 - bltu sp, t5, 3561f - mul s6, a3, a6 - c.beqz a4, 3567f - nop -3561: sub ra, a3, a5 - ori a6, a6, -505 - slti s5, s10, 554 - slli s11, t4, 21 - .4byte 0x00100073 # ebreak - div zero, t5, a1 -3567: slli ra, gp, 12 - c.andi a2, 25 - c.bnez a0, 3588f - divu s3, s7, zero - c.mv s5, t4 - ori s2, s9, 105 - c.srai a2, 27 - rem s7, s2, a0 - bltu ra, s9, 3577f - beq s4, t3, 3590f -3577: c.bnez a1, 3589f - c.and a1, a0 - csrrc a0, 0x340, t0 - mulh a7, s6, s6 - bgeu s0, ra, 3594f - mulhsu a7, a1, t2 - mulhsu a6, zero, s11 - c.slli a1, 8 - add t3, a4, a7 - c.lui a0, 31 - sll t4, a5, sp -3588: c.li s7, 28 -3589: bne sp, s7, 3595f -3590: auipc t1, 230378 - nop - mulhsu s1, s6, t2 - blt s5, a3, 3607f -3594: csrrwi s5, 0x340, 13 -3595: c.andi a3, -16 - slt s5, zero, s0 - sltiu t6, a3, 121 - sltu s6, a0, t2 - divu s2, s2, t4 - .4byte 0x00100073 # ebreak - bgeu s10, s1, 3603f - ori t4, s8, 303 -3603: sltiu a5, t4, 213 - sltu a2, t3, a4 - c.add tp, s10 - c.mv tp, a6 -3607: or a1, t1, s10 - mulh s7, s2, s0 - add t1, a1, s1 - c.or a0, a4 - bne a4, s10, 3619f - csrrs a1, 0x340, a2 - bgeu s8, a0, 3621f - c.li t5, 3 - c.addi t4, -5 - sltiu ra, a7, -209 - sub a6, s5, a1 - c.sub a2, a1 -3619: srli s7, sp, 18 - xori t6, s7, -317 -3621: ori gp, s2, 291 - c.andi a1, 31 - and t1, s8, s1 - c.addi s11, -2 - csrrsi tp, 0x340, 2 - blt a0, ra, 3638f - c.nop - csrrs s11, 0x340, s5 - div ra, s8, s11 - srli a2, s10, 31 - csrrs s10, 0x340, a1 - c.ebreak;c.nop; - add t5, t1, s4 - c.addi s0, -16 - csrrsi zero, 0x340, 11 - andi a5, a3, -669 - div a3, t5, t3 -3638: remu t3, s2, s5 - c.ebreak;c.nop; - xori s0, gp, 850 - sll t2, zero, t2 - csrrsi a4, 0x340, 0 - c.nop - mulh t2, s3, s3 - bltu zero, s7, 3664f - mulh s6, t4, a0 - sltu t3, a4, sp - c.or s1, a5 - bgeu ra, t2, 3654f - c.and s0, a5 - c.ebreak;c.nop; - remu a6, s7, s1 - remu s1, sp, s4 -3654: slt s11, sp, gp - c.or a1, a4 - c.addi a7, 31 - lui s5, 673487 - mulhsu gp, t6, tp - c.slli tp, 30 - mulhsu t2, ra, gp - mulhsu s2, zero, s7 - add t0, t1, a4 - xor s6, a3, s9 -3664: or zero, a4, t3 - bne sp, sp, 3685f - csrrs t0, 0x340, s1 - c.slli s6, 31 - csrrwi ra, 0x340, 8 - csrrc a4, 0x340, a3 - and tp, a1, s11 - c.addi t2, 30 - auipc t6, 542984 - rem a3, a4, t3 - bltu s7, t1, 3682f - csrrc a0, 0x340, t6 - sra s1, sp, s9 - add s3, s4, s6 - lui t0, 62162 - c.andi a2, 9 - c.xor a4, a3 - mulh a3, s7, sp -3682: .4byte 0x00100073 # ebreak - c.andi s1, -29 - csrrsi s1, 0x340, 16 -3685: csrrsi s4, 0x340, 29 - slti t6, a3, -480 - bltu zero, a7, 3707f - c.lui t2, 13 - nop - div s6, s4, s1 - c.xor a4, a1 - add a0, t4, s3 - bge s11, a2, 3701f - bgeu s1, s10, 3700f - c.or a4, s0 - csrrwi s1, 0x340, 8 - c.ebreak;c.nop; - bge s8, a2, 3714f - c.slli s6, 24 -3700: blt t0, a1, 3712f -3701: mulhu s5, t6, s5 - srli t1, t6, 18 - csrrsi a0, 0x340, 21 - slt a7, s7, t5 - andi a2, t2, 89 - sll t1, zero, s0 -3707: srai t3, ra, 10 - nop - c.lui t0, 16 - slt s0, ra, a4 - bltu s0, t2, 3715f -3712: csrrw a3, 0x340, zero - slt s11, a3, t2 -3714: remu a1, s4, s0 -3715: c.or a2, a4 - c.beqz a3, 3734f - and t0, s8, zero - and a6, a2, s8 - c.addi a1, 14 - c.slli a5, 30 - addi s0, a4, -555 - c.nop - mulhu s0, a4, s10 - beq s0, s0, 3732f - div a4, a1, s1 - csrrsi gp, 0x340, 10 - mulhsu a1, s6, s0 - c.lui t1, 16 - c.and a1, s0 - c.addi t2, 29 - mulhsu t1, ra, t1 -3732: c.srli a0, 27 - c.xor a2, a5 -3734: div s3, s10, a0 - c.xor a0, s0 - bgeu t6, a5, 3740f - beq t4, t2, 3740f - c.slli s1, 24 - c.ebreak;c.nop; -3740: xor t5, tp, s8 - c.add s2, a6 - sra s2, a3, t5 - lw gp, 4(sp) - andi a6, t4, -220 - csrrc s4, 0x340, ra - addi sp, sp, 36 - lui t4, 773714 - c.srli a1, 18 - slli a4, t0, 23 - srl tp, a5, ra - ori a2, t5, -627 -6211: c.jr x3 -sub_3: c.andi a5, 30 - csrrsi a0, 0x340, 2 - c.beqz a2, sub_3_stack_p -sub_3_stack_p: addi sp, sp, -40 - xor s7, t2, t5 - sw gp, 4(sp) - and a3, a7, a2 - srai t5, a3, 30 - c.add a0, t0 - c.slli s7, 6 - addi s1, s7, -423 - la a7, sub_4 - c.lui a1, 7 - c.and a0, s1 - add a5, a4, s2 - addi a7, a7, 254 - sub t3, s9, s10 - lui t2, 763957 - csrrwi s5, 0x340, 28 - sltiu a5, a4, -177 -j_sub_3_sub_4_6: jalr gp, a7, -254 - la s2, region_1+886 #start riscv_load_store_rand_instr_stream_0 - lbu t6, -45(s2) - div s7, s1, ra - mulhsu s4, a7, s8 - sltiu gp, zero, -704 - sw s4, -26(s2) - lb s10, -63(s2) - mulhsu a2, t1, t1 - lbu a0, 32(s2) - sll ra, tp, s8 - c.mv t0, ra - lbu t0, 57(s2) - mul t2, s6, t0 - csrrwi a6, 0x340, 6 - lbu t2, 31(s2) - c.slli a0, 16 - lhu t2, 44(s2) - add s0, ra, a4 - lbu tp, 11(s2) - c.and a4, a1 - sb a5, 25(s2) - lbu t2, 12(s2) - xor a3, s8, s9 - lbu s3, 12(s2) #end riscv_load_store_rand_instr_stream_0 -sub_3_1: jal gp, 10f -0: c.jal 18f -1: c.j 5f -2: c.jal 6f -3: c.j 20f -4: jal tp, 25f -5: c.jal 0b -6: jal ra, 13f -7: jal ra, 27f -8: jal t4, 12f -9: c.jal 1b -10: c.jal 2b -11: c.jal 16f -12: c.j 14f -13: jal s5, 26f -14: c.j 7b -15: c.jal 8b -16: jal t1, 24f -17: c.j 19f -18: c.j 23f -19: jal s0, 21f -20: c.jal 17b -21: c.j 4b -22: jal ra, 9b -23: c.jal 3b -24: c.jal 22b -25: c.jal 15b -26: c.jal 11b -27: sll s1, a0, gp - la t2, region_4+3322 #start load_store_instr_stream_1 - la tp, region_4+3186 #start load_store_instr_stream_0 - sb s4, -131(tp) - lhu a7, 32(tp) - sb s8, -45(tp) - lbu t0, -26(t2) - lb t5, -102(tp) - sb t5, 14(tp) - lb t4, 196(tp) - lbu s3, 27(t2) - lhu gp, -206(tp) - lhu a0, -36(t2) - sb s0, -43(t2) - lh s6, -20(tp) - lhu t3, -214(tp) - lbu a5, 29(t2) #end load_store_instr_stream_1 - lb s0, -130(tp) #end load_store_instr_stream_0 - addi s1, zero, 10 #init loop 0 counter - c.srai a3, 26 - add tp, s6, s2 - addi zero, zero, 0 #init loop 0 limit -sub_3_4_0_t: sra t4, tp, t2 - srai a3, ra, 20 - mulhu t5, s11, t0 - c.ebreak;c.nop; - addi s1, s1, -5 #update loop 0 counter - c.or a2, a1 - c.addi s11, 19 - csrrci t2, 0x340, 25 - sra a6, a7, s11 - c.bnez s1, sub_3_4_0_t #branch for loop 0 - sltu t0, t1, s2 - la a1, region_3+87 #start load_store_instr_stream_0 - la t4, region_2+1844 #start load_store_instr_stream_1 - lbu t2, 11(a1) - lbu zero, 50(t4) - lhu s0, 5(a1) - lb t6, 3(t4) - lbu ra, -1(a1) - lbu s5, -44(t4) - lw s6, 12(t4) - lbu s5, -63(t4) - sb a1, -23(t4) - lh s7, -7(a1) - sh tp, -18(t4) #end load_store_instr_stream_1 - lbu s11, 9(a1) #end load_store_instr_stream_0 - mulh t4, a3, t3 - srai gp, tp, 3 - c.slli t6, 6 - div a1, t6, a7 - bge a0, t0, 18f - srl s11, s1, s1 - or a7, t4, s0 - c.addi a6, -19 - sltu a2, ra, a6 - bne t4, ra, 24f - srli a7, a0, 30 - bltu sp, a2, 23f - mulhsu s6, a1, a7 - c.xor a1, s1 - mulhu a5, ra, s3 - c.srai s1, 13 - c.nop - .4byte 0x00100073 # ebreak -18: csrrw s7, 0x340, sp - mulh s10, tp, s4 - mulhu t2, a7, a6 - c.mv t5, a7 - c.beqz a1, 28f -23: c.xor a3, a1 -24: mul t0, a6, a4 - srli tp, s6, 12 - c.srli a3, 23 - srli a0, s5, 23 -28: .4byte 0x00100073 # ebreak - c.ebreak;c.nop; - c.andi a2, -5 - add a6, t3, a6 - remu t1, zero, a5 - c.andi a1, 21 - sra s11, a1, s4 - divu t2, sp, a3 - bne gp, a0, 41f - mul s3, gp, s3 - c.or a0, a3 - csrrci s7, 0x340, 3 - add a0, s3, a7 -41: c.xor a4, a0 - blt s1, a6, 57f - rem a4, t3, s1 - srai s10, s5, 27 - or s4, s1, t4 - c.bnez a4, 55f - mulhu t1, s7, gp - slt gp, t4, s3 - divu s1, s8, t6 - andi a3, t3, -829 - mulhsu zero, s9, a7 - bne t3, ra, 65f - xor s7, t4, sp - c.and a0, a2 -55: c.lui a7, 25 - mulhu a5, zero, ra -57: or gp, s10, t2 - c.slli a6, 13 - sll s7, ra, t1 - c.ebreak;c.nop; - slli a1, tp, 5 - bgeu a7, s6, 72f - c.xor s1, a4 - sltu s11, s2, s7 -65: c.mv ra, s5 - bltu a7, a7, 83f - csrrs t4, 0x340, a4 - lui s3, 844062 - nop - srai s4, tp, 13 - slti s0, t2, 651 -72: or t5, s8, s5 - mul tp, s2, s3 - sltiu zero, gp, -563 - remu a0, t2, gp - divu a2, a3, a4 - c.add s5, s0 - c.nop - divu a4, gp, s4 - ori s10, ra, 30 - csrrsi t3, 0x340, 24 - slt t0, ra, sp -83: c.bnez a3, 92f - csrrwi t5, 0x340, 5 - csrrs t6, 0x340, t4 - c.addi t6, 24 - auipc a4, 203769 - c.srli a5, 29 - add s7, s3, s8 - c.sub s0, a1 - sltu s11, t6, gp -92: c.andi a5, 23 - andi a1, s6, 579 - c.slli a3, 8 - c.and a0, a5 - bge s11, zero, 97f -97: or s0, t0, tp - mulh a5, a6, s9 - .4byte 0x00100073 # ebreak - xori s7, s4, -426 - beq zero, s5, 121f - slti t1, t3, 806 - mul s2, t3, a1 - c.andi a5, 0 - la a1, sub_5 - andi a0, zero, -109 - sll t1, a0, s8 - addi a1, a1, -290 - add a4, s4, a5 - c.andi a2, -6 -j_sub_3_sub_5_5: jalr gp, a1, 290 - srli s5, t1, 30 - csrrs ra, 0x340, s10 - c.or a5, s1 - or t1, t5, t4 - auipc a3, 687135 - xori tp, a7, -654 - bne s3, s11, 119f - csrrsi s0, 0x340, 4 - lui t6, 770690 - auipc tp, 463171 - mulhsu a4, a4, s2 - c.xor a2, a1 - srli t1, t4, 29 - mulhu s6, a1, a4 - divu a3, s11, a4 - mulh s5, a3, a0 - or ra, t3, s8 -119: auipc t3, 140397 - c.or a3, s0 -121: sll s5, a3, a0 - bgeu gp, s0, 135f - xor s2, s8, t6 - slt t1, s9, t4 - and a7, s5, s1 - bne sp, t3, 133f - xor s7, t4, ra - mul s7, t6, s11 - c.slli ra, 1 - and a0, s8, s5 - c.slli t0, 22 - c.ebreak;c.nop; -133: bge gp, a7, 147f - sltu s0, gp, a3 -135: nop - c.slli a5, 15 - mulhu s10, t6, s0 - bltu zero, t3, 147f - xori s11, tp, 2 - csrrc a3, 0x340, a5 - c.nop - c.bnez a1, 144f - c.or a4, s1 -144: xori a3, t6, 544 - bge a6, s11, 162f - bltu s3, t0, 166f -147: or t6, s11, s0 - c.srai a3, 16 - c.nop - c.beqz a4, 160f - c.mv a0, s8 - andi s4, s10, -253 - srai s10, t5, 26 - or t1, s2, t2 - c.lui a3, 6 - c.mv s1, s5 - la s4, region_4+1991 #start riscv_hazard_instr_stream_0 - lbu t1, 184(s4) - lb t5, 134(s4) - lbu a7, 192(s4) - lb t1, -76(s4) - lhu t6, 89(s4) - lb a7, 44(s4) - lbu a1, -75(s4) - lb t1, -98(s4) - lb a1, -206(s4) - c.srai s0, 2 - lb a1, -7(s4) - divu a7, a1, a1 - lbu a1, -6(s4) - lw a7, 125(s4) - lb a1, -162(s4) - lbu a7, -42(s4) - andi t6, s0, 512 - c.lui a7, 6 - sb a7, 138(s4) - nop - lbu s0, 3(s4) - and t1, a7, t6 - lbu a7, -248(s4) - mulh t5, t1, t5 - sb a7, 248(s4) - or a1, t5, t5 - sw a7, -139(s4) - lw a7, 25(s4) - lbu a7, 200(s4) - lb t5, 176(s4) - lbu a7, -133(s4) - lb t1, 120(s4) - lbu a7, 68(s4) - sb a1, 82(s4) - c.add t1, a1 - lbu t1, 196(s4) - c.nop - sltu a1, a7, a7 - sra t5, s0, s0 - lbu t6, 38(s4) - lb t5, -164(s4) #end riscv_hazard_instr_stream_0 - c.slli a0, 13 - csrrwi s3, 0x340, 27 - mulh a7, s9, t0 -160: mulh s4, s0, t6 - c.ebreak;c.nop; -162: csrrw s11, 0x340, t2 - c.li s11, -11 - c.and a5, a5 - xori a6, a1, 166 -166: andi t5, zero, 395 - divu a4, t2, t1 - add s3, t4, a0 - and s1, s9, a5 - c.nop - mulhsu a5, s3, s9 - sra t4, a0, s2 - or a5, a2, gp - c.addi s4, -24 - c.srli a4, 23 - slti t3, t3, 302 - bltu a3, s1, 178f -178: c.and a0, a2 - sra t4, a7, ra - csrrw t3, 0x340, s7 - add s1, s5, a1 - beq s8, t4, 190f - c.sub a2, s1 - blt s10, a2, 201f - sltiu a2, s0, 903 - c.bnez a5, 195f - c.slli a0, 23 - c.srli a1, 31 - c.xor a1, a1 -190: xor a3, t3, a1 - div tp, tp, t5 - sub s5, s5, a0 - csrrwi a6, 0x340, 20 - c.nop -195: c.sub a0, a4 - or s1, t0, s2 - slli t2, tp, 2 - c.srli a2, 3 - csrrs s10, 0x340, a1 - mulhsu a7, t6, ra -201: mulhu s6, s7, t1 - c.or a1, s0 - csrrci t6, 0x340, 19 - divu s2, t1, s9 - c.lui a2, 22 - or t0, s10, s0 - lui s10, 496633 - c.andi a0, -1 - mulhsu s7, a7, s7 - mulh a6, s11, ra - rem s2, gp, a3 - c.li a6, -23 - sub a3, t0, s7 - c.or a4, a0 - c.li gp, 2 - csrrsi t3, 0x340, 18 - c.andi a1, -18 - div a5, s3, s5 - c.addi a4, 13 - mulhu s4, s10, s11 - c.ebreak;c.nop; - c.or a4, a0 - bge a2, zero, 231f - mulhu a3, a4, a7 - c.li a6, 24 - remu s0, zero, s4 - bltu a2, a6, 230f - slt s2, a2, t0 - c.ebreak;c.nop; -230: mul t0, t2, a3 -231: add zero, s0, s2 - c.slli a2, 1 - mul a2, t6, sp - nop - blt t0, a6, 242f - nop - c.addi s1, -22 - .4byte 0x00100073 # ebreak - csrrw t1, 0x340, s11 - sra s3, a5, t4 - c.mv s3, tp -242: divu a6, s9, t2 - srai ra, a3, 18 - csrrs zero, 0x340, sp - sltu a5, t0, s7 - c.or s0, s0 - bltu a2, s9, 254f - csrrs a2, 0x340, gp - c.li t0, 10 - addi s11, s2, -6 - slli t6, t1, 18 - or a5, s2, a1 - c.srli a2, 30 -254: c.slli a6, 25 - mulh a5, a5, t6 - remu s4, a2, s0 - c.add a0, sp - slli a3, t3, 16 - bge s9, a7, 261f - mulhu a2, a4, a2 -261: sltu t5, s6, s1 - addi s2, ra, 358 - c.xor s0, s1 - xor s10, t0, t6 - mul t4, a4, s7 - ori t4, s7, 776 - c.add a4, s1 - mulh s11, a7, a0 - slti s6, s1, -222 - mulhu zero, t4, t5 - slt s2, a7, a6 - slti tp, s2, 479 - c.sub a0, a5 - sll s0, s5, t6 - andi s5, s8, 295 - or t6, t3, a4 - remu t2, gp, s0 - bne s0, t5, 286f - ori a2, s1, -249 - slt a7, a7, t5 - csrrw s3, 0x340, s9 - blt s7, t5, 294f - c.xor a0, a0 - c.andi a5, -5 - sub t2, s2, s0 -286: c.bnez a3, 295f - csrrwi ra, 0x340, 20 - c.addi gp, 21 - c.slli t0, 12 - mulh s10, a3, s8 - mulhu s7, t5, t1 - mulhsu s3, t2, a3 - c.lui a3, 9 -294: c.add s11, a4 -295: addi t4, a7, -494 - csrrc t6, 0x340, a7 - csrrci t5, 0x340, 28 - auipc t5, 800478 - mulhu s7, s5, gp - blt t3, s2, 320f - mulhsu ra, a5, s8 - c.li gp, -3 - addi s5, s3, 354 - la s11, sub_4 - addi s11, s11, 414 - bltu tp, a1, j_sub_3_sub_4_4 #branch to jump instr - divu s3, a4, t6 - c.addi t2, -6 - c.mv t3, s11 - slli s7, a4, 0 -j_sub_3_sub_4_4: jalr gp, s11, -414 - add a7, a6, zero - c.ebreak;c.nop; - c.and a3, s0 - .4byte 0x00100073 # ebreak - sll t1, t3, t2 - xori a5, a7, 216 - xori gp, sp, 150 - c.sub a1, a2 - mulh s0, t1, s6 - bne t4, a6, 330f - c.mv a4, sp - remu s2, s8, s0 - csrrw s11, 0x340, a6 - mulh zero, s9, s3 - addi t3, zero, 96 - bltu zero, s0, 323f - addi s6, t4, 608 - blt a4, t2, 333f - xor a7, t0, t1 -320: srai t1, a1, 31 - remu s4, s5, a7 - mulhsu t5, t4, a5 -323: c.or a3, a3 - bltu s10, t5, 341f - c.bnez a0, 334f - rem ra, s7, tp - c.beqz a2, 341f - c.nop - c.sub a5, a0 -330: c.srai a5, 13 - c.nop - csrrci a4, 0x340, 24 -333: slli t5, a6, 7 -334: nop - c.and a1, a4 - c.lui s6, 28 - mulh a2, a7, a6 - nop - .4byte 0x00100073 # ebreak - bltu t3, t4, 346f -341: c.ebreak;c.nop; - csrrsi zero, 0x340, 17 - lui a3, 648945 - c.lui t0, 26 - c.srli a3, 4 -346: bltu s11, s2, 363f - sltu a3, s9, sp - c.add a6, t1 - addi s0, a4, -489 - c.andi a2, 0 - mulhsu a2, s5, sp - bgeu s3, gp, 359f - xor s0, t0, t0 - remu t4, t5, s5 - remu t2, t2, s2 - c.add a2, a3 - lui s0, 907554 - add a5, s5, s5 -359: xor tp, t1, s4 - divu t0, t3, a0 - c.or s0, a2 - c.or a1, a0 -363: c.beqz a0, 368f - srai s7, a7, 13 - csrrwi s11, 0x340, 24 - c.bnez a5, 381f - divu a7, t6, t0 -368: csrrs ra, 0x340, tp - csrrwi a4, 0x340, 31 - c.srli a3, 31 - nop - bltu t0, zero, 380f - c.and a0, s1 - mulhsu t3, t4, a7 - c.xor a4, s0 - c.srai a5, 31 - c.add t1, s0 - mulhsu gp, t3, a2 - srai s10, s9, 27 -380: sub t2, a5, s10 -381: bltu t2, a0, 395f - bgeu a1, ra, 391f - c.bnez a5, 384f -384: mul t1, s0, a3 - c.ebreak;c.nop; - nop - csrrsi t0, 0x340, 13 - sub a6, a6, a3 - srai t4, s8, 14 - c.bnez s1, 403f -391: csrrc s1, 0x340, s11 - c.srai a5, 30 - csrrs a4, 0x340, s1 - c.lui t3, 9 -395: c.nop - sub a0, s5, s10 - or t3, gp, a0 - c.sub a5, a1 - .4byte 0x00100073 # ebreak - bge a2, a7, 413f - c.bnez a2, 404f - auipc s5, 901029 -403: xori a3, t6, -778 -404: csrrw a6, 0x340, s5 - sra zero, a5, t3 - slli s1, t0, 21 - mulhu s3, t2, a1 - add s4, s1, a3 - or t4, a6, a0 - csrrc s2, 0x340, s8 - mulhu a6, s9, s8 - c.li a0, 10 -413: c.li t4, 12 - rem a2, t2, s6 - slli s1, a4, 17 - sltiu t2, s4, 432 - mulh t4, a6, a7 - sub s4, ra, a6 - or s10, a7, a3 - c.addi a7, 11 - and s0, t5, t4 - c.beqz s0, 433f - .4byte 0x00100073 # ebreak - blt a1, t1, 425f -425: remu a6, t0, a5 - mulhu tp, a5, s8 - csrrwi t3, 0x340, 7 - c.sub a3, a1 - c.or a2, a1 - or a5, s2, s3 - .4byte 0x00100073 # ebreak - sll ra, tp, a7 -433: xori t3, t0, -5 - sub s6, t5, a0 - and s1, s10, s9 - c.and a5, a4 - csrrw t4, 0x340, s5 - nop - c.beqz a5, 449f - c.li t2, 15 - auipc s1, 489914 - csrrc t2, 0x340, a5 - add s10, tp, s1 - csrrci a3, 0x340, 26 - c.slli s11, 31 - slti t0, s1, 956 - c.mv a0, a2 - lui t1, 966445 -449: xori t3, zero, 466 - xor a6, s0, a6 - c.and a1, a3 - csrrci s7, 0x340, 1 - c.andi a4, -27 - srl gp, sp, s7 - div s4, t3, a1 - sub t6, a7, s3 - c.add s2, s0 - sub t5, zero, t2 - sra t0, s1, a0 - xori a6, sp, 887 - csrrw ra, 0x340, t0 - srai a5, a4, 10 - lui a0, 409468 - c.li s0, 6 - lw gp, 4(sp) - addi sp, sp, 40 - andi t1, tp, 957 - rem a7, s5, t3 - xori s2, ra, 102 - c.slli a5, 22 -654: c.jr x3 -write_tohost: - sw gp, tohost, t5 - -_exit: - li a0, CV_VP_STATUS_FLAGS_BASE + 4 - li a1, 0 - sw a1, 0(a0) - j write_tohost - -init_machine_mode: - li x4, 0x101800 - csrw 0x300, x4 # MSTATUS - li x4, 0x0 - csrw 0x304, x4 # MIE - mret -.data -.pushsection .tohost,"aw",@progbits; -.align 6; .global tohost; tohost: .dword 0; -.align 6; .global fromhost; fromhost: .dword 0; -.popsection; -.pushsection .region_0,"aw",@progbits; -region_0: -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.popsection; -.pushsection .region_1,"aw",@progbits; -region_1: -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 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0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 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0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.popsection; -.pushsection .region_2,"aw",@progbits; -region_2: -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 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0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 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0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 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0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.popsection; -.pushsection .region_3,"aw",@progbits; -region_3: -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.popsection; -.pushsection .region_4,"aw",@progbits; -region_4: -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.word 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f -.word 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f -.word 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f -.word 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f -.word 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f -.word 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf -.word 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf -.word 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff -.popsection; -.align 4; -.pushsection .user_stack,"aw",@progbits; -.align 12 -_user_stack_start: -.rept 4999 -.4byte 0x0 -.endr -_user_stack_end: -.4byte 0x0 -.popsection; -_kernel_instr_start: .align 12 -.text -.align 12 -mtvec_handler: - csrrw x2, 0x340, x2 - add x2, x24, zero - 1: addi x2, x2, -124 - sw x1, 4(x2) - sw x2, 8(x2) - sw x3, 12(x2) - sw x4, 16(x2) - sw x5, 20(x2) - sw x6, 24(x2) - sw x7, 28(x2) - sw x8, 32(x2) - sw x9, 36(x2) - sw x10, 40(x2) - sw x11, 44(x2) - sw x12, 48(x2) - sw x13, 52(x2) - sw x14, 56(x2) - sw x15, 60(x2) - sw x16, 64(x2) - sw x17, 68(x2) - sw x18, 72(x2) - sw x19, 76(x2) - sw x20, 80(x2) - sw x21, 84(x2) - sw x22, 88(x2) - sw x23, 92(x2) - sw x24, 96(x2) - sw x25, 100(x2) - sw x26, 104(x2) - sw x27, 108(x2) - sw x28, 112(x2) - sw x29, 116(x2) - sw x30, 120(x2) - sw x31, 124(x2) - csrr x4, 0x342 # MCAUSE - srli x4, x4, 31 - bne x4, x0, mmode_intr_handler - -mmode_exception_handler: - csrr x4, 0x341 # MEPC - csrr x4, 0x342 # MCAUSE - li x7, 0x3 # BREAKPOINT - beq x4, x7, ebreak_handler - li x7, 0x8 # ECALL_UMODE - beq x4, x7, ecall_handler - li x7, 0x9 # ECALL_SMODE - beq x4, x7, ecall_handler - li x7, 0xb # ECALL_MMODE - beq x4, x7, ecall_handler - li x7, 0x1 - beq x4, x7, instr_fault_handler - li x7, 0x5 - beq x4, x7, load_fault_handler - li x7, 0x7 - beq x4, x7, store_fault_handler - li x7, 0xc - beq x4, x7, pt_fault_handler - li x7, 0xd - beq x4, x7, pt_fault_handler - li x7, 0xf - beq x4, x7, pt_fault_handler - li x7, 0x2 # ILLEGAL_INSTRUCTION - beq x4, x7, illegal_instr_handler - csrr x7, 0x343 # MTVAL - 1: jal x1, test_done - -ebreak_handler: - csrr x4, mepc - addi x4, x4, 4 - csrw mepc, x4 - lw x1, 4(x2) - lw x2, 8(x2) - lw x3, 12(x2) - lw x4, 16(x2) - lw x5, 20(x2) - lw x6, 24(x2) - lw x7, 28(x2) - lw x8, 32(x2) - lw x9, 36(x2) - lw x10, 40(x2) - lw x11, 44(x2) - lw x12, 48(x2) - lw x13, 52(x2) - lw x14, 56(x2) - lw x15, 60(x2) - lw x16, 64(x2) - lw x17, 68(x2) - lw x18, 72(x2) - lw x19, 76(x2) - lw x20, 80(x2) - lw x21, 84(x2) - lw x22, 88(x2) - lw x23, 92(x2) - lw x24, 96(x2) - lw x25, 100(x2) - lw x26, 104(x2) - lw x27, 108(x2) - lw x28, 112(x2) - lw x29, 116(x2) - lw x30, 120(x2) - lw x31, 124(x2) - addi x2, x2, 124 - add x24, x2, zero - csrrw x2, 0x340, x2 - mret - -ecall_handler: - la x4, _start - sw x0, 0(x4) - sw x1, 4(x4) - sw x2, 8(x4) - sw x3, 12(x4) - sw x4, 16(x4) - sw x5, 20(x4) - sw x6, 24(x4) - sw x7, 28(x4) - sw x8, 32(x4) - sw x9, 36(x4) - sw x10, 40(x4) - sw x11, 44(x4) - sw x12, 48(x4) - sw x13, 52(x4) - sw x14, 56(x4) - sw x15, 60(x4) - sw x16, 64(x4) - sw x17, 68(x4) - sw x18, 72(x4) - sw x19, 76(x4) - sw x20, 80(x4) - sw x21, 84(x4) - sw x22, 88(x4) - sw x23, 92(x4) - sw x24, 96(x4) - sw x25, 100(x4) - sw x26, 104(x4) - sw x27, 108(x4) - sw x28, 112(x4) - sw x29, 116(x4) - sw x30, 120(x4) - sw x31, 124(x4) - j write_tohost -illegal_instr_handler: - csrr x4, mepc - addi x4, x4, 4 - csrw mepc, x4 - lw x1, 4(x2) - lw x2, 8(x2) - lw x3, 12(x2) - lw x4, 16(x2) - lw x5, 20(x2) - lw x6, 24(x2) - lw x7, 28(x2) - lw x8, 32(x2) - lw x9, 36(x2) - lw x10, 40(x2) - lw x11, 44(x2) - lw x12, 48(x2) - lw x13, 52(x2) - lw x14, 56(x2) - lw x15, 60(x2) - lw x16, 64(x2) - lw x17, 68(x2) - lw x18, 72(x2) - lw x19, 76(x2) - lw x20, 80(x2) - lw x21, 84(x2) - lw x22, 88(x2) - lw x23, 92(x2) - lw x24, 96(x2) - lw x25, 100(x2) - lw x26, 104(x2) - lw x27, 108(x2) - lw x28, 112(x2) - lw x29, 116(x2) - lw x30, 120(x2) - lw x31, 124(x2) - addi x2, x2, 124 - add x24, x2, zero - csrrw x2, 0x340, x2 - mret - -instr_fault_handler: - lw x1, 4(x2) - lw x2, 8(x2) - lw x3, 12(x2) - lw x4, 16(x2) - lw x5, 20(x2) - lw x6, 24(x2) - lw x7, 28(x2) - lw x8, 32(x2) - lw x9, 36(x2) - lw x10, 40(x2) - lw x11, 44(x2) - lw x12, 48(x2) - lw x13, 52(x2) - lw x14, 56(x2) - lw x15, 60(x2) - lw x16, 64(x2) - lw x17, 68(x2) - lw x18, 72(x2) - lw x19, 76(x2) - lw x20, 80(x2) - lw x21, 84(x2) - lw x22, 88(x2) - lw x23, 92(x2) - lw x24, 96(x2) - lw x25, 100(x2) - lw x26, 104(x2) - lw x27, 108(x2) - lw x28, 112(x2) - lw x29, 116(x2) - lw x30, 120(x2) - lw x31, 124(x2) - addi x2, x2, 124 - add x24, x2, zero - csrrw x2, 0x340, x2 - mret - -load_fault_handler: - lw x1, 4(x2) - lw x2, 8(x2) - lw x3, 12(x2) - lw x4, 16(x2) - lw x5, 20(x2) - lw x6, 24(x2) - lw x7, 28(x2) - lw x8, 32(x2) - lw x9, 36(x2) - lw x10, 40(x2) - lw x11, 44(x2) - lw x12, 48(x2) - lw x13, 52(x2) - lw x14, 56(x2) - lw x15, 60(x2) - lw x16, 64(x2) - lw x17, 68(x2) - lw x18, 72(x2) - lw x19, 76(x2) - lw x20, 80(x2) - lw x21, 84(x2) - lw x22, 88(x2) - lw x23, 92(x2) - lw x24, 96(x2) - lw x25, 100(x2) - lw x26, 104(x2) - lw x27, 108(x2) - lw x28, 112(x2) - lw x29, 116(x2) - lw x30, 120(x2) - lw x31, 124(x2) - addi x2, x2, 124 - add x24, x2, zero - csrrw x2, 0x340, x2 - mret - -store_fault_handler: - lw x1, 4(x2) - lw x2, 8(x2) - lw x3, 12(x2) - lw x4, 16(x2) - lw x5, 20(x2) - lw x6, 24(x2) - lw x7, 28(x2) - lw x8, 32(x2) - lw x9, 36(x2) - lw x10, 40(x2) - lw x11, 44(x2) - lw x12, 48(x2) - lw x13, 52(x2) - lw x14, 56(x2) - lw x15, 60(x2) - lw x16, 64(x2) - lw x17, 68(x2) - lw x18, 72(x2) - lw x19, 76(x2) - lw x20, 80(x2) - lw x21, 84(x2) - lw x22, 88(x2) - lw x23, 92(x2) - lw x24, 96(x2) - lw x25, 100(x2) - lw x26, 104(x2) - lw x27, 108(x2) - lw x28, 112(x2) - lw x29, 116(x2) - lw x30, 120(x2) - lw x31, 124(x2) - addi x2, x2, 124 - add x24, x2, zero - csrrw x2, 0x340, x2 - mret - -pt_fault_handler: - nop - -.align 12 -mmode_intr_handler: - csrr x4, 0x300 # MSTATUS; - csrr x4, 0x304 # MIE; - csrr x4, 0x344 # MIP; - csrrc x4, 0x344, x4 # MIP; - lw x1, 4(x2) - lw x2, 8(x2) - lw x3, 12(x2) - lw x4, 16(x2) - lw x5, 20(x2) - lw x6, 24(x2) - lw x7, 28(x2) - lw x8, 32(x2) - lw x9, 36(x2) - lw x10, 40(x2) - lw x11, 44(x2) - lw x12, 48(x2) - lw x13, 52(x2) - lw x14, 56(x2) - lw x15, 60(x2) - lw x16, 64(x2) - lw x17, 68(x2) - lw x18, 72(x2) - lw x19, 76(x2) - lw x20, 80(x2) - lw x21, 84(x2) - lw x22, 88(x2) - lw x23, 92(x2) - lw x24, 96(x2) - lw x25, 100(x2) - lw x26, 104(x2) - lw x27, 108(x2) - lw x28, 112(x2) - lw x29, 116(x2) - lw x30, 120(x2) - lw x31, 124(x2) - addi x2, x2, 124 - add x24, x2, zero - csrrw x2, 0x340, x2 - mret; - -_kernel_instr_end: nop -.pushsection .kernel_stack,"aw",@progbits; -.align 12 -_kernel_stack_start: -.rept 3999 -.4byte 0x0 -.endr -_kernel_stack_end: -.4byte 0x0 -.popsection; diff --git a/cv32e40x/tests/programs/custom/riscv_ebreak_test_0/test.yaml b/cv32e40x/tests/programs/custom/riscv_ebreak_test_0/test.yaml deleted file mode 100644 index e0332befd2..0000000000 --- a/cv32e40x/tests/programs/custom/riscv_ebreak_test_0/test.yaml +++ /dev/null @@ -1,4 +0,0 @@ -name: riscv_ebreak_test_0 -uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c -description: > - Static EBREAK test generated from riscv-dv \ No newline at end of file diff --git a/cv32e40x/tests/programs/embench/README.md b/cv32e40x/tests/programs/embench/README.md deleted file mode 100644 index 0f51965ca7..0000000000 --- a/cv32e40x/tests/programs/embench/README.md +++ /dev/null @@ -1,4 +0,0 @@ -EMBench generated tests -================================== - -This directory is populated with generated tests when running EMBench speed benchmark diff --git a/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_base_test.sv b/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_base_test.sv deleted file mode 100644 index fc9244135c..0000000000 --- a/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_base_test.sv +++ /dev/null @@ -1,484 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technologies -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - - -`ifndef __UVMT_CV32E40X_BASE_TEST_SV__ -`define __UVMT_CV32E40X_BASE_TEST_SV__ - - -/** - * Abstract component from which all other CV32E40X test cases must - * ultimately extend. - * Subclasses must provide stimulus via the virtual sequencer by implementing - * UVM runtime phases. - */ -class uvmt_cv32e40x_base_test_c extends uvm_test; - - // Objects - rand uvmt_cv32e40x_test_cfg_c test_cfg ; - rand uvme_cv32e40x_cfg_c env_cfg ; - rand uvme_cv32e40x_cntxt_c env_cntxt; - uvml_logs_rs_text_c rs ; - uvml_logs_reg_logger_cbs_c reg_cbs ; - - // Components - uvme_cv32e40x_env_c env ; - uvme_cv32e40x_vsqr_c vsequencer; - - // Handles testbench interfaces - virtual uvmt_cv32e40x_vp_status_if vp_status_vif; // virtual peripheral status - - // Default sequences - rand uvme_cv32e40x_reset_vseq_c reset_vseq; - - - `uvm_component_utils_begin(uvmt_cv32e40x_base_test_c) - `uvm_field_object(test_cfg , UVM_DEFAULT) - `uvm_field_object(env_cfg , UVM_DEFAULT) - `uvm_field_object(env_cntxt, UVM_DEFAULT) - `uvm_component_utils_end - - - constraint env_cfg_cons { - env_cfg.enabled == 1; - env_cfg.is_active == UVM_ACTIVE; - env_cfg.trn_log_enabled == 1; - } - - constraint heartbreat_mon_default_cons { - soft test_cfg.heartbeat_mon_enabled == 1; - } - - constraint test_type_default_cons { - soft test_cfg.tpt == NO_TEST_PROGRAM; - } - - // Additional, temporary constraints to get around known design bugs/constraints - `include "uvmt_cv32e40x_base_test_workarounds.sv" - - - /** - * 1. Replaces default report server with rs. - * 2. Creates reset_vseq. - */ - extern function new(string name="uvmt_cv32e40x_base_test", uvm_component parent=null); - - /** - * 1. Builds test_cfg & env_cfg via create_cfg() - * 2. Randomizes entire test class via randomize_test() - * 3. Passes env_cfg to env via uvm_config_db via assign_cfg() - * 4. Builds env_cntxt via create_cntxt() - * 5. Passes env_cntxt to env using UVM Configuration Database via assign_cntxt() - * 6. Builds env via create_env() - * 7. Builds the rest of the components/objects via create_components() - */ - extern virtual function void build_phase(uvm_phase phase); - - /** - * 1. Assigns environment's virtual sequencer handle to vsequencer. - * 2. Add register callback (reg_cbs) to all registers & fields. - */ - extern virtual function void connect_phase(uvm_phase phase); - - /** - * Print final test configuration - */ - extern virtual function void end_of_elaboration_phase(uvm_phase phase); - - /** - * 1. Triggers the start of clock generation via start_clk() - * 2. Starts the watchdog timeout via watchdog_timeout() - */ - extern virtual task run_phase(uvm_phase phase); - - /** - * Runs reset_vseq. - */ - extern virtual task reset_phase(uvm_phase phase); - - /** - * In a typical UVM env, this task writes contents of RAL to the DUT. - * Here, test_cfg is used to determine if the test program is loaded into - * the TB's instruction memory. - */ - extern virtual task configure_phase(uvm_phase phase); - - /** - * Prints out start of phase banners. - */ - extern virtual function void phase_started(uvm_phase phase); - - /** - * Indicates to the test bench (uvmt_cv32e40x_tb) that the test has completed. - * This is done by checking the properties of the phase argument. - */ - extern virtual function void phase_ended(uvm_phase phase); - - /** - * post_randomize hook to complete configuration of test/environment config object - */ - extern function void post_randomize(); - - /** - * Retrieves virtual interfaces from UVM configuration database. - */ - extern function void retrieve_vifs(); - - /** - * Creates test_cfg and env_cfg. Assigns ral handle to env_cfg's. - */ - extern virtual function void create_cfg(); - - /** - * 1. Calls test_cfg's process_cli_args() - * 2. Calls randomize on 'this' and fatals out if it fails. - */ - extern virtual function void randomize_test(); - - /** - * Configures uvml_default_hrtbt_monitor. - */ - extern function void cfg_hrtbt_monitor(); - - /** - * Assigns environment configuration (env_cfg) handle to environment (env) - * using UVM Configuration Database. - */ - extern virtual function void assign_cfg(); - - /** - * Creates env_cntxt. - */ - extern virtual function void create_cntxt(); - - /** - * Assigns environment context (env_cntxt) handle to environment (env) using - * UVM Configuration Database. - */ - extern virtual function void assign_cntxt(); - - /** - * Sample the core (DUT) parameters - */ - extern virtual function void sample_core_parameters(); - - /** - * Creates env. - */ - extern virtual function void create_env(); - - /** - * Creates additional (non-environment) components (and objects). - */ - extern virtual function void create_components(); - - /** - * Prints overlined and underlined text in uppercase. - */ - extern function void print_banner(string text); - - /** - * Fatals out after watchdog_timeout has elapsed. - */ - extern virtual task watchdog_timer(); - -endclass : uvmt_cv32e40x_base_test_c - - -function uvmt_cv32e40x_base_test_c::new(string name="uvmt_cv32e40x_base_test", uvm_component parent=null); - - super.new(name, parent); - - // Replaces default report server - // Gives you short-and-sweet looger messages like this: - // UVM_INFO @ 9.750 ns : uvmt_cv32e40x_dut_wrap.sv(79) reporter [DUT_WRAP] load_instr_mem asserted! - rs = new("rs"); - - - // Terminate simulation after a "reasonable" number of errors - uvm_report_server::set_server(rs); - reset_vseq = uvme_cv32e40x_reset_vseq_c::type_id::create("reset_vseq"); -endfunction : new - - -function void uvmt_cv32e40x_base_test_c::build_phase(uvm_phase phase); - - super.build_phase(phase); - - rs.set_max_quit_count(.count(5), .overridable(1)); - - create_cfg (); - cfg_hrtbt_monitor(); - assign_cfg (); - create_cntxt (); - assign_cntxt (); - retrieve_vifs (); - sample_core_parameters(); - randomize_test (); - create_env (); - create_components(); - -endfunction : build_phase - - -function void uvmt_cv32e40x_base_test_c::connect_phase(uvm_phase phase); - - super.connect_phase(phase); - - vsequencer = env.vsequencer; - uvm_reg_cb::add(null, reg_cbs); - -endfunction : connect_phase - -function void uvmt_cv32e40x_base_test_c::end_of_elaboration_phase(uvm_phase phase); - - super.end_of_elaboration_phase(phase); - - `uvm_info("BASE TEST", $sformatf("Top-level environment configuration:\n%s", env_cfg.sprint()), UVM_NONE) - `uvm_info("BASE TEST", $sformatf("Testcase configuration:\n%s", test_cfg.sprint()), UVM_NONE) - -endfunction : end_of_elaboration_phase - - -task uvmt_cv32e40x_base_test_c::run_phase(uvm_phase phase); - - super.run_phase(phase); - - watchdog_timer(); - -endtask : run_phase - - -task uvmt_cv32e40x_base_test_c::reset_phase(uvm_phase phase); - - super.reset_phase(phase); - - phase.raise_objection(this); - - env_cntxt.core_cntrl_cntxt.core_cntrl_vif.load_instr_mem = 1'bX; // Using 'X to signal uvmt_cv32e40x_dut_wrap.sv to wait... - - `uvm_info("BASE TEST", $sformatf("Starting reset virtual sequence:\n%s", reset_vseq.sprint()), UVM_NONE) - reset_vseq.start(vsequencer); - `uvm_info("BASE TEST", $sformatf("Finished reset virtual sequence:\n%s", reset_vseq.sprint()), UVM_NONE) - - phase.drop_objection(this); - -endtask : reset_phase - - -task uvmt_cv32e40x_base_test_c::configure_phase(uvm_phase phase); - - // Control the loading of the pre-compiled firmware - // Actual loading done in uvmt_cv32e40x_dut_wrap.sv to avoid XMRs across packages. - if (test_cfg.tpt == NO_TEST_PROGRAM) begin - env_cntxt.core_cntrl_cntxt.core_cntrl_vif.load_instr_mem = 1'b0; - `uvm_info("BASE TEST", "clear load_instr_mem", UVM_NONE) - end - else begin - env_cntxt.core_cntrl_cntxt.core_cntrl_vif.load_instr_mem = 1'b1; - `uvm_info("BASE TEST", "set load_instr_mem", UVM_NONE) - end - - //TODO: is this OK?!? - super.configure_phase(phase); - `uvm_info("BASE TEST", "configure_phase() complete", UVM_HIGH) - -endtask : configure_phase - - -function void uvmt_cv32e40x_base_test_c::phase_started(uvm_phase phase); - - string phase_name = phase.get_name(); - - super.phase_started(phase); - - print_banner($sformatf("start of %s phase", phase_name)); - -endfunction : phase_started - - -function void uvmt_cv32e40x_base_test_c::phase_ended(uvm_phase phase); - - // Local vars for test status outputs from Virtual Peripheral in uvmt_cv32e40x_tb.dut_wrap.mem_i - bit tp; - bit tf; - bit evalid; - bit [31:0] evalue; - - super.phase_ended(phase); - - if (phase.is(uvm_final_phase::get())) begin - // Set sim_finished (otherwise tb will flag that sim was aborted) - uvm_config_db#(bit)::set(null, "", "sim_finished", 1); - - // - // Get test status outputs - if(!(uvm_config_db#(bit )::get(null, "*", "tp", tp ))) `uvm_error("END_OF_TEST", "Cannot get tp from config_db.") - if(!(uvm_config_db#(bit )::get(null, "*", "tf", tf ))) `uvm_error("END_OF_TEST", "Cannot get tf from config_db.") - if(!(uvm_config_db#(bit )::get(null, "*", "evalid", evalid))) `uvm_error("END_OF_TEST", "Cannot get valid from config_db.") - if(!(uvm_config_db#(bit[31:0])::get(null, "*", "evalue", evalue))) `uvm_error("END_OF_TEST", "Cannot get evalue from config_db.") - - // Use the DUT Wrapper Virtual Peripheral's status outputs to update report server status. - if (tf) `uvm_error ("END_OF_TEST", "DUT WRAPPER virtual peripheral flagged test failure.") - - // Check exit code if a valid exit code was written to Virtual Peripheral - if (evalid) begin - if (evalue != 0) begin - `uvm_error("END_OF_TEST", $sformatf("DUT WRAPPER virtual peripheral signaled exit_value=%0h.", evalue)) - end - else begin - `uvm_info("END_OF_TEST", $sformatf("DUT WRAPPER virtual peripheral signaled exit_value=%0h.", evalue), UVM_NONE) - end - end - - // Catch hanging tests. If no exit code nor test pass/test fail status was ever written to Virtual Peripheral - // then mark test as failed - if (!tp && !evalid && !tf) `uvm_error("END_OF_TEST", "DUT WRAPPER virtual peripheral failed to flag test passed and failed to signal exit value.") - - print_banner("test finished"); - end - -endfunction : phase_ended - -function void uvmt_cv32e40x_base_test_c::post_randomize(); - - -endfunction : post_randomize - - -function void uvmt_cv32e40x_base_test_c::retrieve_vifs(); - - if (!uvm_config_db#(virtual uvmt_cv32e40x_vp_status_if)::get(this, "", "vp_status_vif", vp_status_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find vp_status_vif handle of type %s in uvm_config_db", $typename(vp_status_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found vp_status_vif handle of type %s in uvm_config_db", $typename(vp_status_vif)), UVM_DEBUG) - end - - if (!uvm_config_db#(virtual uvme_cv32e40x_core_cntrl_if)::get(this, "", "core_cntrl_vif", env_cntxt.core_cntrl_cntxt.core_cntrl_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find core_cntrl_vif handle of type %s in uvm_config_db", $typename(env_cntxt.core_cntrl_cntxt.core_cntrl_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found core_cntrl_vif handle of type %s in uvm_config_db", $typename(env_cntxt.core_cntrl_cntxt.core_cntrl_vif)), UVM_DEBUG) - end - -endfunction : retrieve_vifs - - -function void uvmt_cv32e40x_base_test_c::create_cfg(); - - test_cfg = uvmt_cv32e40x_test_cfg_c::type_id::create("test_cfg"); - env_cfg = uvme_cv32e40x_cfg_c ::type_id::create("env_cfg" ); - -endfunction : create_cfg - - -function void uvmt_cv32e40x_base_test_c::randomize_test(); - - test_cfg.process_cli_args(); - `uvm_info("TEST", "randomize test", UVM_LOW); - if (!this.randomize()) begin - `uvm_fatal("BASE TEST", "Failed to randomize test"); - end - -endfunction : randomize_test - - -function void uvmt_cv32e40x_base_test_c::cfg_hrtbt_monitor(); - - uvml_default_hrtbt.enabled = test_cfg.heartbeat_mon_enabled; - //`uvml_hrtbt_set_cfg(startup_timeout , test_cfg.startup_timeout) - uvml_default_hrtbt.startup_timeout = test_cfg.startup_timeout; // TODO DOP: Fix heartbeat macros - //`uvml_hrtbt_set_cfg(heartbeat_period, test_cfg.heartbeat_period) - uvml_default_hrtbt.startup_timeout = test_cfg.heartbeat_period; // TODO DOP: Fix heartbeat macros - -endfunction : cfg_hrtbt_monitor - - -function void uvmt_cv32e40x_base_test_c::assign_cfg(); - - uvm_config_db#(uvme_cv32e40x_cfg_c)::set(this, "env", "cfg", env_cfg); - -endfunction : assign_cfg - - -function void uvmt_cv32e40x_base_test_c::create_cntxt(); - - env_cntxt = uvme_cv32e40x_cntxt_c::type_id::create("env_cntxt"); - -endfunction : create_cntxt - - -function void uvmt_cv32e40x_base_test_c::assign_cntxt(); - - uvm_config_db#(uvme_cv32e40x_cntxt_c)::set(this, "env", "cntxt", env_cntxt); - -endfunction : assign_cntxt - - -function void uvmt_cv32e40x_base_test_c::sample_core_parameters(); - - env_cfg.sample_parameters(env_cntxt.core_cntrl_cntxt); - -endfunction : sample_core_parameters - - -function void uvmt_cv32e40x_base_test_c::create_env(); - - env = uvme_cv32e40x_env_c::type_id::create("env", this); - -endfunction : create_env - - -function void uvmt_cv32e40x_base_test_c::create_components(); - - reg_cbs = uvml_logs_reg_logger_cbs_c::type_id::create("reg_cbs"); - -endfunction : create_components - - -function void uvmt_cv32e40x_base_test_c::print_banner(string text); - - if (test_cfg != null) begin - if (test_cfg.print_uvm_runflow_banner) begin - $display(""); - $display("*******************************************************************************"); - $display(text.toupper()); - $display("*******************************************************************************"); - end - else begin - `uvm_info("BASE_TEST", "Printing of UVM run-flow banner disabled", UVM_HIGH) - end - end - -endfunction : print_banner - - -task uvmt_cv32e40x_base_test_c::watchdog_timer(); - - fork - begin - #(test_cfg.watchdog_timeout * 1ns); - `uvm_fatal("TIMEOUT", $sformatf("Global timeout after %0dns. Heartbeat list:\n%s", test_cfg.watchdog_timeout, uvml_default_hrtbt.print_comp_names())) - end - join_none - -endtask : watchdog_timer - - -`endif // __UVMT_CV32E40X_BASE_TEST_SV__ diff --git a/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_base_test_workarounds.sv b/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_base_test_workarounds.sv deleted file mode 100644 index 176c4736d9..0000000000 --- a/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_base_test_workarounds.sv +++ /dev/null @@ -1,11 +0,0 @@ -// COPYRIGHT HEADER - - -`ifndef __UVMT_CV32E40X_BASE_TEST_WORKAROUNDS_SV__ -`define __UVMT_CV32E40X_BASE_TEST_WORKAROUNDS_SV__ - - -// This file should be empty by the end of the project - - -`endif // __UVMT_CV32E40X_BASE_TEST_WORKAROUNDS_SV__ diff --git a/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_test_cfg.sv b/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_test_cfg.sv deleted file mode 100644 index e2c235caf3..0000000000 --- a/cv32e40x/tests/uvmt/base-tests/uvmt_cv32e40x_test_cfg.sv +++ /dev/null @@ -1,147 +0,0 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -`ifndef __UVMT_CV32E40X_TEST_CFG_SV__ -`define __UVMT_CV32E40X_TEST_CFG_SV__ - - -/** - * Configuration object for testcases - */ -class uvmt_cv32e40x_test_cfg_c extends uvm_object; - - - // Knobs for environment control - rand bit heartbeat_mon_enabled; - rand int unsigned startup_timeout ; // Specified in nanoseconds (ns) - rand int unsigned heartbeat_period; // Specified in nanoseconds (ns) - rand int unsigned watchdog_timeout; // Specified in nanoseconds (ns) - - // Knobs for test-program control - rand test_program_type tpt; - - // Command line arguments for controlling RAL - // (note: its not clear if this ENV will use the RAL) - string cli_block_name_str = "BLKNM"; - bit cli_block_name_override = 0; - //uvm_reg_block cli_selected_block; - - // Command line arguments for FIRMWARE (Test Program) selection - // +firmware= - string cli_firmware_select_str = "firmware"; - bit cli_firmware_select_override = 0; - string cli_firmware_name_str = ""; - - // Command line arguments to control whether the UVM run-flow banner is - // written to stdout. (A bit overkill for on/off control.) - // +print_uvm_runflow_banner=1 - string cli_uvm_banner_select_str = "print_uvm_runflow_banner"; - bit cli_uvm_banner_select_override = 0; - string cli_uvm_banner_name_str = ""; - - // Run-time control - bit run_riscv_gcc_toolchain = 0; - bit print_uvm_runflow_banner = 0; - - `uvm_object_utils_begin(uvmt_cv32e40x_test_cfg_c) - `uvm_field_int(heartbeat_mon_enabled, UVM_DEFAULT) - `uvm_field_int(startup_timeout, UVM_DEFAULT | UVM_DEC) - `uvm_field_int(heartbeat_period, UVM_DEFAULT | UVM_DEC) - `uvm_field_int(watchdog_timeout, UVM_DEFAULT | UVM_DEC) - - `uvm_field_enum(test_program_type, tpt, UVM_DEFAULT) - - //`uvm_field_object(cli_selected_block, UVM_DEFAULT) - `uvm_field_int(run_riscv_gcc_toolchain, UVM_DEFAULT) - `uvm_field_int(print_uvm_runflow_banner, UVM_DEFAULT) - `uvm_object_utils_end - - - constraint timeouts_default_cons { - soft startup_timeout == 100_000_000; // Set to be huge for now so that sim can finish - soft heartbeat_period == 200_000; // 2 us // TODO Set default Heartbeat Monitor period for uvmt_cv32e40x_base_test_c - soft watchdog_timeout == 100_000_000; // 10 ms // TODO Set default Watchdog timeout period for uvmt_cv32e40x_base_test_c - } - - //constraint test_type_default_cons { - // soft tpt == NONE; - //} - - /** - * Default constructor. - */ - extern function new(string name="uvmt_cv32e40x_test_cfg"); - - /** - * TODO Describe uvmt_cv32e40x_test_cfg_c::process_cli_args() - */ - extern function void process_cli_args(); - -endclass : uvmt_cv32e40x_test_cfg_c - - -function uvmt_cv32e40x_test_cfg_c::new(string name="uvmt_cv32e40x_test_cfg"); - - super.new(name); - - if ($value$plusargs("timeout=%d", watchdog_timeout)) begin - watchdog_timeout.rand_mode(0); - end - -endfunction : new - - -function void uvmt_cv32e40x_test_cfg_c::process_cli_args(); - - string cli_block_name_parsed_str = ""; - - // RAL control - cli_block_name_override = 0; //default - if (uvm_cmdline_proc.get_arg_value({"+", cli_block_name_str, "="}, cli_block_name_parsed_str)) begin - if (cli_block_name_parsed_str != "") begin - cli_block_name_override = 1; - //cli_selected_block = ral.get_block_by_name(cli_block_name_parsed_str); - `uvm_info("TEST_CFG", $sformatf("process_cli_args() RAL block_name=%s", cli_block_name_str), UVM_LOW) - end - end - - // Test program (firmware) selection - cli_firmware_select_override = 0; // default - if (uvm_cmdline_proc.get_arg_value({"+", cli_firmware_select_str, "="}, cli_firmware_name_str)) begin - if (cli_firmware_name_str != "") begin - cli_firmware_select_override = 1; - run_riscv_gcc_toolchain = 1; - `uvm_info("TEST_CFG", $sformatf("process_cli_args() firmware=%s", cli_firmware_name_str), UVM_LOW) - end - end - - // Turn on printing of UVM run-flow banner (any arg will work) - // void'($value$plusargs("print_uvm_runflow_banner=%0d", print_uvm_runflow_banner)); - cli_uvm_banner_select_override = 0; // default - if (uvm_cmdline_proc.get_arg_value({"+", cli_uvm_banner_select_str, "="}, cli_uvm_banner_name_str)) begin - if (cli_firmware_name_str != "") begin - cli_uvm_banner_select_override = 1; - print_uvm_runflow_banner = 1; - `uvm_info("TEST_CFG", $sformatf("process_cli_args() cli_uvm_banner_select_str=%s", cli_uvm_banner_name_str), UVM_LOW) - end - end - - `uvm_info("TEST_CFG", "process_cli_args() complete", UVM_HIGH) - -endfunction : process_cli_args - - -`endif // __UVMT_CV32E40X_TEST_CFG_SV__ diff --git a/cv32e40x/tests/uvmt/bin/README.md b/cv32e40x/tests/uvmt/bin/README.md deleted file mode 100644 index a62812f4ec..0000000000 --- a/cv32e40x/tests/uvmt/bin/README.md +++ /dev/null @@ -1 +0,0 @@ -Place scripts related to CV32E40X tests here. diff --git a/cv32e40x/tests/uvmt/bin/test_template/README.md b/cv32e40x/tests/uvmt/bin/test_template/README.md deleted file mode 100644 index 5932fc19d8..0000000000 --- a/cv32e40x/tests/uvmt/bin/test_template/README.md +++ /dev/null @@ -1,21 +0,0 @@ -# Purpose -This script creates a new UVM test for CV32. - - - -# Usage -`% new_test.sh ` - -Ex: `new_test.sh sanity` - - -## Note -This script must be run from this directory. - - - -# Outputs -The script outputs a single file, `uvmt_cv32__test.sv`. The example command in 'Usage' would create `uvmt_cv32_sanity_test.sv` in this directory. -The resultant file will have a number of `TODO` (with examples) in comments, to be completed by the user. - - diff --git a/cv32e40x/tests/uvmt/bin/test_template/new_test.sh b/cv32e40x/tests/uvmt/bin/test_template/new_test.sh deleted file mode 100644 index 81e681ab4c..0000000000 --- a/cv32e40x/tests/uvmt/bin/test_template/new_test.sh +++ /dev/null @@ -1,37 +0,0 @@ -#!/bin/bash -############################################################################### -# Copyright 2020 OpenHW Group -# Copyright 2020 Datum Technology Corporation -# -# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://solderpad.org/licenses/ -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -############################################################################### - - -######### -# ABOUT # -######### -# Simple script to take test_templates.sv and do a simple string substitution for the test name. - - -############# -# ARGUMENTS # -############# -test_name=$1 -test_name_uppercase=${test_name^^} - - -############### -# ENTRY POINT # -############### -cat test_template.sv | sed -E "s/[$][{]name_uppercase[}]/$test_name_uppercase/g" | sed -E "s/[$][{]name[}]/$test_name/g" > uvmt_cv32_${test_name}_test.sv - diff --git a/cv32e40x/tests/uvmt/bin/test_template/test_template.sv b/cv32e40x/tests/uvmt/bin/test_template/test_template.sv deleted file mode 100644 index bba0201230..0000000000 --- a/cv32e40x/tests/uvmt/bin/test_template/test_template.sv +++ /dev/null @@ -1,104 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - -`ifndef __UVMT_CV32_${name_uppercase}_TEST_SV__ -`define __UVMT_CV32_${name_uppercase}_TEST_SV__ - - -/** - * TODO Describe uvmt_cv32_${name}_test_c - */ -class uvmt_cv32_${name}_test_c extends uvmt_cv32_base_test_c; - - // TODO Add virtual sequence(s) to uvmt_cv32_${name}_test_c - // Ex: rand uvme_cv32_my_vseq_c my_vseq; - - - `uvm_component_utils(uvmt_cv32_${name}_test_c) - - - constraint ${name}_cons { - // TODO Add constraints to uvmt_cv32_${name}_test_c - // Ex: env_cfg.abc == 100; - // my_vseq.xyz == 5; - // watchdog_timeout == 200_000_000; // 200 ms - } - - - /** - * Contructor function, performs factory overrides and creates all objects. - * TODO Describe uvmt_cv32_${name}_test_c::new() - */ - extern function new(string name="uvmt_cv32_${name}_test", uvm_component parent=null); - - /** - * Executes test stimulus. - * TODO Describe uvmt_cv32_${name}_test_c::main_phase() - */ - extern virtual task main_phase(uvm_phase phase); - - /** - * Performs test self-check to ensure stimulus, scoreboarding and checking - * actually took place. - * TODO Describe uvmt_cv32_${name}_test_c::check_phase() - */ - extern virtual function void check_phase(uvm_phase phase); - -endclass : uvmt_cv32_${name}_test_c - - -function uvmt_cv32_${name}_test_c::new(string name="uvmt_cv32_${name}_test", uvm_component parent=null); - - super.new(name, parent); - - // TODO Add factory overrides to uvmt_cv32_${name}_test_c - // Ex: my_override_class_c::type_id:set_type_override(my_overriden_class_c.get_type()); - - // TODO Create uvmt_cv32_${name}_test_c test objects - // Ex: my_vseq = uvme_cv32_my_vseq_c::type_id::create("my_vseq"); - -endfunction : new - - -task uvmt_cv32_${name}_test_c::main_phase(uvm_phase phase); - - super.main_phase(phase); - - phase.raise_objection(this); - // TODO Add stimulus to uvmt_cv32_${name}_test_c - // Ex: `uvm_info("TEST", $sformatf("Starting my_vseq virtual sequence:\n%s", my_vseq.sprint()), UVM_NONE) - // my_vseq.start(vsequencer); - // `uvm_info("TEST", "Finished my_vseq virtual sequence", UVM_NONE) - phase.drop_objection(this); - -endtask : run_phase - - -function void uvmt_cv32_${name}_test_c::check_phase(uvm_phase phase); - - super.check_phase(phase); - - // TODO Implement uvmt_cv32_${name}_test_c::check_phase() - // Ex: if (env_cntxt.abc > some_threshold) begin - // `uvm_error("TEST", "Hmmm, didn't expect that...") - // end - -endfunction : check_phase - - -`endif // __UVMT_CV32_${name_uppercase}_SV__ diff --git a/cv32e40x/tests/uvmt/compliance-tests/README.md b/cv32e40x/tests/uvmt/compliance-tests/README.md deleted file mode 100644 index 61bb542311..0000000000 --- a/cv32e40x/tests/uvmt/compliance-tests/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# Running compliance tests in the UVM environment -Testcase `uvmt_cv32_firmware_test.sv` is implemented to run the RISC-V and OpenHW Compliance testcases. diff --git a/cv32e40x/tests/uvmt/compliance-tests/uvmt_cv32e40x_firmware_test.sv b/cv32e40x/tests/uvmt/compliance-tests/uvmt_cv32e40x_firmware_test.sv deleted file mode 100644 index 5e638c898b..0000000000 --- a/cv32e40x/tests/uvmt/compliance-tests/uvmt_cv32e40x_firmware_test.sv +++ /dev/null @@ -1,203 +0,0 @@ -// -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// - - - -`ifndef __UVMT_CV32E40X_FIRMWARE_TEST_SV__ -`define __UVMT_CV32E40X_FIRMWARE_TEST_SV__ - - -/** - * CV32E40X "firmware" test. - * This class relies on a pre-existing "firmware" file written in C and/or - * RISC-V assembly code. This class will invoke the riscv-gcc-toolchain to - * translate the firmware into a "hexfile" that is read into the CV32E40X - * instruction memory in the testbench module. - * - * This class doesn't care what the firmware does, it mearly compiles it. - * - */ -class uvmt_cv32e40x_firmware_test_c extends uvmt_cv32e40x_base_test_c; - - //constraint env_cfg_cons { - // env_cfg.enabled == 1; - // env_cfg.is_active == UVM_ACTIVE; - // env_cfg.trn_log_enabled == 1; - //} - - constraint test_type_cons { - test_cfg.tpt == PREEXISTING_SELFCHECKING; - } - - - `uvm_component_utils(uvmt_cv32e40x_firmware_test_c) - - /** - */ - extern function new(string name="uvmt_cv32e40x_firmware_test", uvm_component parent=null); - - /** - * Runs reset_vseq. - */ - extern virtual task reset_phase(uvm_phase phase); - - /** - * Loads the test program (the "firmware") into memory. - */ - extern virtual task configure_phase(uvm_phase phase); - - /** - * Enable program execution, wait for completion. - */ - extern virtual task run_phase(uvm_phase phase); - - /** - * Start random debug sequencer - */ - extern virtual task random_debug(); - - extern virtual task reset_debug(); - - extern virtual task bootset_debug(); - /** - * Start the interrupt sequencer to apply random interrupts during test - */ - extern virtual task irq_noise(); - -endclass : uvmt_cv32e40x_firmware_test_c - - -function uvmt_cv32e40x_firmware_test_c::new(string name="uvmt_cv32e40x_firmware_test", uvm_component parent=null); - - super.new(name, parent); - `uvm_info("TEST", "This is the FIRMWARE TEST", UVM_NONE) - -endfunction : new - - -task uvmt_cv32e40x_firmware_test_c::reset_phase(uvm_phase phase); - super.reset_phase(phase); - -endtask : reset_phase - - -task uvmt_cv32e40x_firmware_test_c::configure_phase(uvm_phase phase); - - super.configure_phase(phase); - -endtask : configure_phase - - -task uvmt_cv32e40x_firmware_test_c::run_phase(uvm_phase phase); - - // start_clk() and watchdog_timer() are called in the base_test - super.run_phase(phase); - - if ($test$plusargs("gen_random_debug")) begin - fork - random_debug(); - join_none - end - - if ($test$plusargs("gen_irq_noise")) begin - fork - irq_noise(); - join_none - end - - if ($test$plusargs("reset_debug")) begin - fork - reset_debug(); - join_none - end - if ($test$plusargs("debug_boot_set")) begin - fork - bootset_debug(); - join_none - end - - phase.raise_objection(this); - @(posedge env_cntxt.clknrst_cntxt.vif.reset_n); - repeat (33) @(posedge env_cntxt.clknrst_cntxt.vif.clk); - `uvm_info("TEST", "Started RUN", UVM_NONE) - // The firmware is expected to write exit status and pass/fail indication to the Virtual Peripheral - wait ( - (vp_status_vif.exit_valid == 1'b1) || - (vp_status_vif.tests_failed == 1'b1) || - (vp_status_vif.tests_passed == 1'b1) - ); - repeat (100) @(posedge env_cntxt.clknrst_cntxt.vif.clk); - //TODO: exit_value will not be valid - need to add a latch in the vp_status_vif - `uvm_info("TEST", $sformatf("Finished RUN: exit status is %0h", vp_status_vif.exit_value), UVM_NONE) - phase.drop_objection(this); - -endtask : run_phase - -task uvmt_cv32e40x_firmware_test_c::reset_debug(); - uvme_cv32e40x_random_debug_reset_c debug_vseq; - debug_vseq = uvme_cv32e40x_random_debug_reset_c::type_id::create("random_debug_reset_vseqr"); - `uvm_info("TEST", "Applying debug_req_i at reset", UVM_NONE); - @(negedge env_cntxt.clknrst_cntxt.vif.reset_n); - - void'(debug_vseq.randomize()); - debug_vseq.start(vsequencer); - -endtask - -task uvmt_cv32e40x_firmware_test_c::bootset_debug(); - uvme_cv32e40x_random_debug_bootset_c debug_vseq; - debug_vseq = uvme_cv32e40x_random_debug_bootset_c::type_id::create("random_debug_bootset_vseqr"); - `uvm_info("TEST", "Applying single cycle debug_req after reset", UVM_NONE); - @(negedge env_cntxt.clknrst_cntxt.vif.reset_n); - - // Delay debug_req_i by up to 35 cycles.Should hit BOOT_SET - repeat($urandom_range(35,1)) @(posedge env_cntxt.clknrst_cntxt.vif.clk); - - void'(debug_vseq.randomize()); - debug_vseq.start(vsequencer); - -endtask - -task uvmt_cv32e40x_firmware_test_c::random_debug(); - `uvm_info("TEST", "Starting random debug in thread UVM test", UVM_NONE); - - while (1) begin - uvme_cv32e40x_random_debug_c debug_vseq; - repeat (100) @(env_cntxt.debug_cntxt.vif.mon_cb); - debug_vseq = uvme_cv32e40x_random_debug_c::type_id::create("random_debug_vseqr"); - void'(debug_vseq.randomize()); - debug_vseq.start(vsequencer); - break; - end -endtask : random_debug - -task uvmt_cv32e40x_firmware_test_c::irq_noise(); - `uvm_info("TEST", "Starting IRQ Noise thread in UVM test", UVM_NONE); - while (1) begin - uvme_cv32e40x_interrupt_noise_c interrupt_noise_vseq; - - interrupt_noise_vseq = uvme_cv32e40x_interrupt_noise_c::type_id::create("interrupt_noise_vseqr"); - assert(interrupt_noise_vseq.randomize() with { - reserved_irq_mask == 32'h0; - }); - interrupt_noise_vseq.start(vsequencer); - break; - end -endtask : irq_noise - -`endif // __UVMT_CV32E40X_FIRMWARE_TEST_SV__ diff --git a/cv32e40x/tests/uvmt/test-programs/crt0.S b/cv32e40x/tests/uvmt/test-programs/crt0.S deleted file mode 100644 index 9f8f9cec99..0000000000 --- a/cv32e40x/tests/uvmt/test-programs/crt0.S +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright (c) 2017 SiFive Inc. All rights reserved. - * Copyright (c) 2019 ETH Zürich and University of Bologna - * This copyrighted material is made available to anyone wishing to use, - * modify, copy, or redistribute it subject to the terms and conditions - * of the FreeBSD License. This program is distributed in the hope that - * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, - * including the implied warranties of MERCHANTABILITY or FITNESS FOR - * A PARTICULAR PURPOSE. A copy of this license is available at - * http://www.opensource.org/licenses. - */ - -/* Entry point for bare metal programs */ -.section .text.start -.global _start -.type _start, @function - -_start: -/* initialize global pointer */ -.option push -.option norelax -1: auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) -.option pop - -/* initialize stack pointer */ - la sp, _sp - -/* set vector table address */ - la a0, __vector_start - csrw mtvec, a0 - -/* clear the bss segment */ - la a0, __bss_start - la a2, __bss_end - sub a2, a2, a0 - li a1, 0 - call memset - -/* new-style constructors and destructors */ - la a0, __libc_fini_array - call atexit - call __libc_init_array - -/* call main */ - lw a0, 0(sp) /* a0 = argc */ - addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ - li a2, 0 /* a2 = envp = NULL */ - call main - tail exit - -.size _start, .-_start - -.global _init -.type _init, @function -.global _fini -.type _fini, @function -_init: -_fini: - /* These don't have to do anything since we use init_array/fini_array. Prevent - missing symbol error */ - ret -.size _init, .-_init -.size _fini, .-_fini diff --git a/cv32e40x/tests/uvmt/test-programs/hello_world.c b/cv32e40x/tests/uvmt/test-programs/hello_world.c deleted file mode 100644 index ae786783f3..0000000000 --- a/cv32e40x/tests/uvmt/test-programs/hello_world.c +++ /dev/null @@ -1,117 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Sanity test for the CV32E40X core. Reads the MISA and MVENDORID CSRs and -** prints some useful (?) messages to -** stdout. Will fail if MISA is not sane. -** -******************************************************************************* -*/ - -#include -#include - -int main(int argc, char *argv[]) -{ - unsigned int mvendorid_rval, misa_rval, mxl; - int reserved, tentative, nonstd, user, super; - - mxl = 0; reserved = 0; tentative = 0; nonstd = 0; user = 0; super = 0; - - /* inline assembly: read mvendorid and misa */ - asm volatile("ecall"); - __asm__ volatile("csrr %0, 0xF11" : "=r"(mvendorid_rval)); - __asm__ volatile("csrr %0, 0x301" : "=r"(misa_rval)); - - /* Check MISA CSR: if its zero, it might not be implemented at all */ - if (misa_rval == 0x0) { - printf("\tERROR: CSR MISA returned zero!\n\n"); - return EXIT_FAILURE; - } - - /* Print a banner to stdout and interpret MISA CSR */ - printf("\nThis is the OpenHW Group CV32E40X RISC-V processor core\n"); - printf("running an example \"custom\" test-program.\n"); - printf("Please consult the CORE-V Verification Strategy for more information\n"); - printf("on the distinction between a UVM testcase and a core test-program.\n"); - printf("\tmvendorid = 0x%0x\n", mvendorid_rval); - printf("\tmisa = 0x%0x\n", misa_rval); - mxl = ((misa_rval & 0xC0000000) >> 30); // MXL == MISA[31:30] - switch (mxl) { - case 0: printf("\tERROR: MXL cannot be zero!\n"); - return EXIT_FAILURE; - break; - case 1: printf("\tXLEN is 32-bits\n"); - break; - case 2: printf("\tXLEN is 64-bits\n"); - break; - case 3: printf("\tXLEN is 128-bits\n"); - break; - default: printf("\tERROR: mxl (%0d) not in 0..3, your code is broken!\n", mxl); - return EXIT_FAILURE; - } - - printf("\tSupported Instructions: "); - if ((misa_rval >> 25) & 0x00000001) ++reserved; - if ((misa_rval >> 24) & 0x00000001) ++reserved; - if ((misa_rval >> 23) & 0x00000001) ++nonstd; - if ((misa_rval >> 22) & 0x00000001) ++reserved; - if ((misa_rval >> 21) & 0x00000001) ++tentative; - if ((misa_rval >> 20) & 0x00000001) ++user; - if ((misa_rval >> 19) & 0x00000001) ++tentative; - if ((misa_rval >> 18) & 0x00000001) ++super; - if ((misa_rval >> 17) & 0x00000001) ++reserved; - if ((misa_rval >> 16) & 0x00000001) printf("Q"); - if ((misa_rval >> 15) & 0x00000001) ++tentative; - if ((misa_rval >> 14) & 0x00000001) ++reserved; - if ((misa_rval >> 13) & 0x00000001) printf("N"); - if ((misa_rval >> 12) & 0x00000001) printf("M"); - if ((misa_rval >> 11) & 0x00000001) ++tentative; - if ((misa_rval >> 10) & 0x00000001) ++reserved; - if ((misa_rval >> 9) & 0x00000001) printf("J"); - if ((misa_rval >> 8) & 0x00000001) printf("I"); - if ((misa_rval >> 7) & 0x00000001) printf("H"); - if ((misa_rval >> 6) & 0x00000001) printf("G"); - if ((misa_rval >> 5) & 0x00000001) printf("F"); - if ((misa_rval >> 4) & 0x00000001) printf("E"); - if ((misa_rval >> 3) & 0x00000001) printf("D"); - if ((misa_rval >> 2) & 0x00000001) printf("C"); - if ((misa_rval >> 1) & 0x00000001) printf("B"); - if ((misa_rval ) & 0x00000001) printf("A"); - printf("\n"); - if (super) { - printf("\tThis machine supports SUPERVISOR mode.\n"); - } - if (user) { - printf("\tThis machine supports USER mode.\n"); - } - if (nonstd) { - printf("\tThis machine supports non-standard instructions.\n"); - } - if (tentative) { - printf("\tWARNING: %0d tentative instruction extensions are defined!\n", tentative); - } - if (reserved) { - printf("\tERROR: %0d reserved instruction extensions are defined!\n\n", reserved); - return EXIT_FAILURE; - } - else { - printf("\n"); - return EXIT_SUCCESS; - } -} diff --git a/cv32e40x/tests/uvmt/test-programs/link.ld b/cv32e40x/tests/uvmt/test-programs/link.ld deleted file mode 100644 index e1f454b7a1..0000000000 --- a/cv32e40x/tests/uvmt/test-programs/link.ld +++ /dev/null @@ -1,380 +0,0 @@ -/* Script for -z combreloc: combine and sort reloc sections */ -/* Copyright (C) 2014-2018 Free Software Foundation, Inc. - Copyright (C) 2019 ETH Zürich and University of Bologna - Copying and distribution of this script, with or without modification, - are permitted in any medium without royalty provided the copyright - notice and this notice are preserved. */ - -/* This linker script is derived from the default linker script of the RISC-V - gcc compiler. We have made a few changes to make it suitable for linking bare - metal programs. These are mostly removing dynamic linking related sections and - putting sections into our memory regions. */ - -OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", - "elf32-littleriscv") -OUTPUT_ARCH(riscv) -ENTRY(_start) - -MEMORY -{ - /* Our testbench is a bit weird in that we initialize the RAM (thus - allowing initialized sections to be placed there). Infact we dump all - sections to ram. */ - - ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 -} - -SECTIONS -{ - /* we want a fixed entry point */ - PROVIDE(__boot_address = 0x80); - - /* stack and heap related settings */ - __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; - PROVIDE(__stack_size = __stack_size); - __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; - - - /* Read-only sections, merged into text segment: */ - PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS; - - - /* We don't do any dynamic linking so we remove everything related to it */ -/* - .interp : { *(.interp) } - .note.gnu.build-id : { *(.note.gnu.build-id) } - .hash : { *(.hash) } - .gnu.hash : { *(.gnu.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - PROVIDE_HIDDEN (__rela_iplt_start = .); - *(.rela.iplt) - PROVIDE_HIDDEN (__rela_iplt_end = .); - } - .rela.plt : - { - *(.rela.plt) - } -*/ - - /* interrupt vectors */ - .vectors (ORIGIN(ram)): - { - PROVIDE(__vector_start = .); - KEEP(*(.vectors)); - } >ram - - /* crt0 init code */ - .init (__boot_address): - { - KEEP (*(SORT_NONE(.init))) - KEEP (*(.text.start)) - } >ram - - - /* More dynamic linking sections */ -/* - .plt : { *(.plt) } - .iplt : { *(.iplt) } -*/ - - - /* the bulk of the program: main, libc, functions etc. */ - .text : - { - *(.text.unlikely .text.*_unlikely .text.unlikely.*) - *(.text.exit .text.exit.*) - *(.text.startup .text.startup.*) - *(.text.hot .text.hot.*) - *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - } >ram - - - /* not used by RISC-V*/ - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >ram - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - - /* read-only sections */ - .rodata : - { - *(.rodata .rodata.* .gnu.linkonce.r.*) - } >ram - .rodata1 : - { - *(.rodata1) - } >ram - - - /* second level sbss and sdata, I don't think we need this */ - /* .sdata2 : {*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)} */ - /* .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } */ - - - /* gcc language agnostic exception related sections (try-catch-finally) */ - .eh_frame_hdr : - { - *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) - } >ram - .eh_frame : ONLY_IF_RO - { - KEEP (*(.eh_frame)) *(.eh_frame.*) - } >ram - .gcc_except_table : ONLY_IF_RO - { - *(.gcc_except_table .gcc_except_table.*) - } >ram - .gnu_extab : ONLY_IF_RO - { - *(.gnu_extab*) - } >ram - /* These sections are generated by the Sun/Oracle C++ compiler. */ - /* - .exception_ranges : ONLY_IF_RO { *(.exception_ranges - .exception_ranges*) } - */ - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); - - - /* Exception handling */ - .eh_frame : ONLY_IF_RW - { - KEEP (*(.eh_frame)) *(.eh_frame.*) - } >ram - .gnu_extab : ONLY_IF_RW - { - *(.gnu_extab) - } >ram - .gcc_except_table : ONLY_IF_RW - { - *(.gcc_except_table .gcc_except_table.*) - } >ram - .exception_ranges : ONLY_IF_RW - { - *(.exception_ranges .exception_ranges*) - } >ram - - - /* Thread Local Storage sections */ - .tdata : - { - PROVIDE_HIDDEN (__tdata_start = .); - *(.tdata .tdata.* .gnu.linkonce.td.*) - } >ram - .tbss : - { - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - } >ram - - - /* initialization and termination routines */ - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >ram - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >ram - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >ram - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >ram - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >ram - - /* .jcr : { KEEP (*(.jcr)) } */ - /* .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } */ - /* .dynamic : { *(.dynamic) } */ - . = DATA_SEGMENT_RELRO_END (0, .); - - - /* data sections for initalized data */ - .data : - { - __DATA_BEGIN__ = .; - *(.data .data.* .gnu.linkonce.d.*) - SORT(CONSTRUCTORS) - } >ram - .data1 : - { - *(.data1) - } > ram - - /* no dynamic linking, no object tables required */ - /* .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } */ - - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : - { - __SDATA_BEGIN__ = .; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } >ram - _edata = .; PROVIDE (edata = .); - . = .; - - - /* zero initialized sections */ - __bss_start = .; - .sbss : - { - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } >ram - .bss : - { - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - /* Align here to ensure that the .bss section occupies space up to - _end. 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This reduces code size. */ - __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, - MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); - _end = .; PROVIDE (end = .); - . = DATA_SEGMENT_END (.); - - - /* heap: we should consider putting this to the bottom of the address space */ - .heap : - { - PROVIDE(__heap_start = .); - . = __heap_size; - PROVIDE(__heap_end = .); - } >ram - - - /* stack: we should consider putting this further to the top of the address - space */ - .stack : ALIGN(16) /* this is a requirement of the ABI(?) */ - { - PROVIDE(__stack_start = .); - . = __stack_size; - PROVIDE(_sp = .); - PROVIDE(__stack_end = .); - } >ram - - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - /* DWARF Extension. */ - .debug_macro 0 : { *(.debug_macro) } - .debug_addr 0 : { *(.debug_addr) } - .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } -} diff --git a/cv32e40x/tests/uvmt/test-programs/smoke.c b/cv32e40x/tests/uvmt/test-programs/smoke.c deleted file mode 100644 index 8cee636553..0000000000 --- a/cv32e40x/tests/uvmt/test-programs/smoke.c +++ /dev/null @@ -1,32 +0,0 @@ -/* -** -** Copyright 2020 OpenHW Group -** -** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -** you may not use this file except in compliance with the License. -** You may obtain a copy of the License at -** -** https://solderpad.org/licenses/ -** -** Unless required by applicable law or agreed to in writing, software -** distributed under the License is distributed on an "AS IS" BASIS, -** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -** See the License for the specific language governing permissions and -** limitations under the License. -** -******************************************************************************* -** -** Smoke test for the CV32E40X core. Prints and quits -** -******************************************************************************* -*/ - -#include -#include - -int main(int argc, char *argv[]) -{ - /* Print a banner to stdout and die */ - printf("\nThis is the OpenHW Group CV32E40X RISC-V processor core.\n\n"); - return EXIT_SUCCESS; -} diff --git a/cv32e40x/tests/uvmt/test-programs/vectors.S b/cv32e40x/tests/uvmt/test-programs/vectors.S deleted file mode 100644 index 8a177a6918..0000000000 --- a/cv32e40x/tests/uvmt/test-programs/vectors.S +++ /dev/null @@ -1,120 +0,0 @@ -/* -* Copyright 2019 ETH Zürich and University of Bologna -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -.section .vectors, "ax" -.option norvc -vector_table: - j sw_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j __no_irq_handler - j verification_irq_handler - -/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the -new vector table (which is at mtvec) */ -/* .section .legacy_irq, "ax" */ -/* j vector_table */ -/* j __no_irq_handler */ -/* j __no_irq_handler */ -/* j __no_irq_handler */ - -.section .text.vecs -/* exception handling */ -__no_irq_handler: - la a0, no_exception_handler_msg - jal ra, puts - j __no_irq_handler - - -sw_irq_handler: - csrr t0, mcause - slli t0, t0, 1 /* shift off the high bit */ - srli t0, t0, 1 - li t1, 2 - beq t0, t1, handle_illegal_insn - li t1, 11 - beq t0, t1, handle_ecall - li t1, 3 - beq t0, t1, handle_ebreak - j handle_unknown - -handle_ecall: - la a0, ecall_msg - jal ra, puts - j end_handler - -handle_ebreak: - la a0, ebreak_msg - jal ra, puts - j end_handler - -handle_illegal_insn: - la a0, illegal_insn_msg - jal ra, puts - j end_handler - -handle_unknown: - la a0, unknown_msg - jal ra, puts - j end_handler - -end_handler: - csrr a0, mepc - addi a0, a0, 4 - csrw mepc, a0 - mret -/* this interrupt can be generated for verification purposes, random or when the PC is equal to a given value*/ -verification_irq_handler: - mret - -.section .rodata -illegal_insn_msg: - .string "illegal instruction exception handler entered\n" -ecall_msg: - .string "ecall exception handler entered\n" -ebreak_msg: - .string "ebreak exception handler entered\n" -unknown_msg: - .string "unknown exception handler entered\n" -no_exception_handler_msg: - .string "no exception handler installed\n" diff --git a/cv32e40x/tests/uvmt/vseq/uvmt_cv32e40x_vseq_lib.sv b/cv32e40x/tests/uvmt/vseq/uvmt_cv32e40x_vseq_lib.sv deleted file mode 100644 index 1f6519cf95..0000000000 --- a/cv32e40x/tests/uvmt/vseq/uvmt_cv32e40x_vseq_lib.sv +++ /dev/null @@ -1,39 +0,0 @@ -// COPYRIGHT HEADER - - -`ifndef __UVMT_CV32E40X_VSEQ_LIB_SV__ -`define __UVMT_CV32E40X_VSEQ_LIB_SV__ - - -/** - * Object holding virtual sequence library for CV32E40X test cases. - */ -class uvmt_cv32e40x_vseq_lib_c extends uvm_sequence_library#( - .REQ(uvm_sequence_item), - .RSP(uvm_sequence_item) -); - - `uvm_object_utils (uvmt_cv32e40x_vseq_lib_c) - `uvm_sequence_library_utils(uvmt_cv32e40x_vseq_lib_c) - - - /** - * Initializes sequence library. - */ - extern function new(string name="uvmt_cv32e40x_vseq_lib"); - -endclass : uvmt_cv32e40x_vseq_lib_c - - -function uvmt_cv32e40x_vseq_lib_c::new(string name="uvmt_cv32e40x_vseq_lib"); - - super.new(name); - init_sequence_library(); - - // TODO Add sequences to uvmt_cv32e40x_vseq_lib_c - // Ex: add_sequence(uvmt_cv32e40x_abc_vseq_c::get_type()); - -endfunction : new - - -`endif // __UVMT_CV32E40X_VSEQ_LIB_SV__ diff --git a/cv32e40x/vendor_lib/.gitignore b/cv32e40x/vendor_lib/.gitignore deleted file mode 100644 index 173bb8ff15..0000000000 --- a/cv32e40x/vendor_lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -embench/ - diff --git a/cv32e40x/vendor_lib/README.md b/cv32e40x/vendor_lib/README.md deleted file mode 100644 index 797a3e18e2..0000000000 --- a/cv32e40x/vendor_lib/README.md +++ /dev/null @@ -1,12 +0,0 @@ -## VENDOR_LIB: Library of third-party verification components - -This is where you will find "vendor" Verification Components used the CORE-V verification environments. - -# imperas -Source files used to support the Imperas Instruction Set Simulator. - -# google -Verification components from Google. Note that the bulk of the code is cloned -to directories below this directory by the scriptware and/or Makefiles that -compile the verification environment and launch simulations. - diff --git a/cv32e40x/vendor_lib/google/.gitignore b/cv32e40x/vendor_lib/google/.gitignore deleted file mode 100644 index 604e292c53..0000000000 --- a/cv32e40x/vendor_lib/google/.gitignore +++ /dev/null @@ -1 +0,0 @@ -riscv-dv diff --git a/cv32e40x/vendor_lib/google/GoogleCheats.md b/cv32e40x/vendor_lib/google/GoogleCheats.md deleted file mode 100644 index 209b3e4a16..0000000000 --- a/cv32e40x/vendor_lib/google/GoogleCheats.md +++ /dev/null @@ -1,37 +0,0 @@ -## RISCV-DV Cheat Sheet - -### tests - -``` -riscv_arithmetic_basic_test -riscv_rand_instr_test -riscv_jump_stress_test -riscv_loop_test -riscv_rand_jump_test -riscv_mmu_stress_test -riscv_no_fence_test -riscv_illegal_instr_test -riscv_ebreak_test -riscv_ebreak_debug_mode_test -riscv_full_interrupt_test -riscv_csr_test -riscv_unaligned_load_store_test -``` - -### Useful (?) examples - -``` -$ rm -rf out_2020-07-03 metrics* dsim.env -$ python3 ./run.py -si dsim --target rv32imc --steps gen --test riscv_arithmetic_basic_test -$ python3 ./run.py -si dsim --target rv32imc --steps gen --test riscv_rand_instr_test -$ python3 ./run.py -si dsim --target rv32imc --steps gen -v --test riscv_rand_instr_test -$ python3 ./run.py -si dsim --target rv32imc --steps gen -v --test riscv_jump_stress_test -``` - -### CSR Testing - -Unlike all the other tests, which are produced by a SystemVerilog/UVM program, the CSR test is generated -by a Python3 script using a YAML file to specify the CSRs. To run it: -``` -$ python3 ./riscv-dv/scripts/gen_csr_test.py --csr_file corev-dv/cv32e40x_csr_template.yaml --out ./corev-dv -``` diff --git a/cv32e40x/vendor_lib/google/README.md b/cv32e40x/vendor_lib/google/README.md deleted file mode 100644 index 412b4967e5..0000000000 --- a/cv32e40x/vendor_lib/google/README.md +++ /dev/null @@ -1,14 +0,0 @@ -### Google -Verification components from Google and CORE-V specific extensions and updates to same. - -**riscv-dv**: location where the Google RISC-V Instruction Stream Generator is cloned to. - -In order to use riscv-dv the following shell ENV variables must be set (values are examples only): -``` -export DSIM="/tools/Metrics/dsim/20190802.10.1/bin/dsim" -export DSIM_LIB_PATH="/tools/Metrics/dsim/20190802.10.1/uvm-1.2/src/dpi" -export RISCV_GCC="/opt/riscv/bin/riscv32-unknown-elf-gcc" -export RISCV_OBJCOPY="/opt/riscv/bin/riscv32-unknown-elf-objcopy" -export SPIKE_PATH="/opt/riscv-64/bin/spike" -export RISCV_DV_ROOT="/data/mike/GitHubRepos/openhwgroup/core-v-verif/isg_tests/vendor_lib/google/riscv-dv" -``` diff --git a/cv32e40x/vendor_lib/imperas/riscv_CV32E40X_OVPsim/sv/riscv_CV32E40P.h b/cv32e40x/vendor_lib/imperas/riscv_CV32E40X_OVPsim/sv/riscv_CV32E40P.h deleted file mode 100644 index 2cc29d4074..0000000000 --- a/cv32e40x/vendor_lib/imperas/riscv_CV32E40X_OVPsim/sv/riscv_CV32E40P.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * - * Copyright (c) 2005-2021 Imperas Software Ltd., www.imperas.com - * - * The contents of this file are provided under the Software License - * Agreement that you accepted before downloading this file. - * - * This source forms part of the Software and can be used for educational, - * training, and demonstration purposes but cannot be used for derivative - * works except in cases where the derivative works require OVP technology - * to run. - * - * For open source models released under licenses that you can use for - * derivative works, please visit www.OVPworld.org or www.imperas.com - * for the location of the open source models. - * - */ - -typedef struct { - Uns64 retPC; - Uns64 excPC; - Uns64 nextPC; - - Uns64 order; - Uns64 trap; - - // Signals to SV - Uns64 irq_ack_o; - Uns64 irq_id_o; - Uns64 DM; -} RMDataT; - -typedef struct { - // Signals from SV - Uns64 reset; - Uns64 deferint; - Uns64 irq_i; - Uns64 haltreq; - Uns64 resethaltreq; - Uns64 terminate; - - // E40X - Uns64 LoadBusFaultNMI; - Uns64 StoreBusFaultNMI; - Uns64 InstructionBusFault; - - Uns64 cycles; -} SVDataT; diff --git a/cv32e40x/vendor_lib/imperas/riscv_CV32E40X_OVPsim/sv/riscv_datatype.h b/cv32e40x/vendor_lib/imperas/riscv_CV32E40X_OVPsim/sv/riscv_datatype.h deleted file mode 100644 index 32ca185673..0000000000 --- a/cv32e40x/vendor_lib/imperas/riscv_CV32E40X_OVPsim/sv/riscv_datatype.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * - * Copyright (c) 2005-2021 Imperas Software Ltd., www.imperas.com - * - * The contents of this file are provided under the Software License - * Agreement that you accepted before downloading this file. - * - * This source forms part of the Software and can be used for educational, - * training, and demonstration purposes but cannot be used for derivative - * works except in cases where the derivative works require OVP technology - * to run. - * - * For open source models released under licenses that you can use for - * derivative works, please visit www.OVPworld.org or www.imperas.com - * for the location of the open source models. - * - */ - -typedef struct { - Uns64 retPC; - Uns64 excPC; - Uns64 nextPC; - - //Uns64 x[32]; - //Uns64 f[32]; - //Uns64 csr[4096]; - - Uns64 order; - Uns64 trap; - - // Signals to SV - Uns64 irq_ack_o; - Uns64 irq_id_o; - Uns64 DM; -} RMDataT; - -typedef struct { - // Signals from SV - Uns64 reset; - Uns64 deferint; - Uns64 irq_i; - Uns64 haltreq; - Uns64 resethaltreq; - Uns64 terminate; - - Uns64 cycles; -} SVDataT; diff --git a/cv32e40x/vendor_lib/riscv/.gitignore b/cv32e40x/vendor_lib/riscv/.gitignore deleted file mode 100644 index 0657f61a5e..0000000000 --- a/cv32e40x/vendor_lib/riscv/.gitignore +++ /dev/null @@ -1 +0,0 @@ -riscv-compliance diff --git a/cv32e40x/vendor_lib/riscv/README.md b/cv32e40x/vendor_lib/riscv/README.md deleted file mode 100644 index 748a14bd7a..0000000000 --- a/cv32e40x/vendor_lib/riscv/README.md +++ /dev/null @@ -1,4 +0,0 @@ -### RISCV -RISC-V Compliance Test-suite. - -The Makefiles (e.g. ../../cv32/sim/uvmt_cv32/Makefile) are expected to support targets to clone a specific hash/tag of the RISC-V Compliance Test-suite here. diff --git a/cv32e40x/vendor_lib/verilab/README.md b/cv32e40x/vendor_lib/verilab/README.md deleted file mode 100644 index 21a9560151..0000000000 --- a/cv32e40x/vendor_lib/verilab/README.md +++ /dev/null @@ -1,33 +0,0 @@ -# Verilab SVLIB Vendor Library - -The Verilab SVLIB http://www.verilab.com/resources/svlib/ is a SystemVerilog package that provides a host of convenient utilities for -testbench functionality that is not provided by UVM nor SystemVerilog itself conveniently. These utilities include: - -- Advanced string handling -- Regular expression parsing -- File pathname manipulation -- Environment variable queries -- Time functions - -## Documentation - -For more details on using the SVLIB, please refer to their documentation PDF. This PDF can be found either on the Verilab website -or by cloning the Bitbucket SVLIB repository into vendor_lib (`make clone_svlib`) and finding the documenation under `svlib/doc` - -## CORE-V_VERIF Compilation - -The SVLIB will now be cloned and compiled into every core-v-verif simulation. The source code is cloned from a checked-in hash -in Common.mk for the CV_CORE being simulated. The Makefiles will compile this package into the simulation database automatically. -From any class or module simply address or import the svlib_pkg to access the SVLIB itself. - -## Shared Library - -SVLIB is partially implemented in C accessed via the DPI in SystemVerilog. A checked-in shared object (compile to Linux 64-bit) will enable -out-of-the-box operation for most users. However if one needs to recompile the SVLIB DPI this can be accomplished via the `svlib` make target. -Note that each CV_CORE has a separate SVLIB directory. Refer to `mk/Common.mk` for more details on the actual compilation and creation of the -shared library and the variables provided to customize. - - -``` -% make svlib CV_CORE=cv32e40x -``` diff --git a/cv32e40x/vendor_lib/verilab/svlib_dpi.so b/cv32e40x/vendor_lib/verilab/svlib_dpi.so deleted file mode 100755 index c88d8ce14b..0000000000 Binary files a/cv32e40x/vendor_lib/verilab/svlib_dpi.so and /dev/null differ diff --git a/cv32e40x/vendor_lib/verilab/svlib_pkg.flist b/cv32e40x/vendor_lib/verilab/svlib_pkg.flist deleted file mode 100644 index 3ca5d49de3..0000000000 --- a/cv32e40x/vendor_lib/verilab/svlib_pkg.flist +++ /dev/null @@ -1,17 +0,0 @@ -// Copyright 2021 OpenHW Group -// Copyright 2021 Silicon Labs -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance -// with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at -// https://solderpad.org/licenses/SHL-2.1/ -// Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on -// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -// Directories -+incdir+${DV_SVLIB_PATH}/svlib/svlib/src - -// Files -${DV_SVLIB_PATH}/svlib/svlib/src/svlib_pkg.sv diff --git a/docs/CodingStyleGuidelines.md b/docs/CodingStyleGuidelines.md index be185ae8af..6e2f1a0543 100644 --- a/docs/CodingStyleGuidelines.md +++ b/docs/CodingStyleGuidelines.md @@ -98,10 +98,10 @@ Files should contain the following, in order: | Location | Item Type | Item Name | File Name | | -------------------- | ------------------- | ------------------- | ---------------------- | | `verif/vkits/` | Package | `_pkg` | `_pkg.sv` | -| `verif/vkits/` | Interface | `_intf` | `_intf.sv` | +| `verif/vkits/` | Interface | `_if` | `_if.sv` | | `verif/vkits/` | Class | `_c` | `__c` | | `verif/vkits/` | Flist File | N/A | `.flist` | -| `verif/` | Top-level Testbench | `_tb_top` | `_tb_top.sv` | +| `verif/` | Top-level Testbench | `_tb` | `_tb.sv` | | `verif/` | Class | `_c` | `.sv` | | `verif/` | Flist File | N/A | `.flist` | | `verif//tests` | Base Test | `base_test_c` | `base_test.sv` | @@ -140,9 +140,9 @@ foo_drv.sv: | `_c` | Classes | `_t` | Typedefs, Misc. Types | | `_e` | Enumerated Types | `_s` | Structs | | `_pkg` | Packages | `_cb` | Clocking Blocks | -| `_intf` | Interface Types | `_mp` | Modports | -| `_i` | Interface Instances | `_cnstr` | Constraints | -| `_vi` | Virtual Interface Instances | `_cg` | Covergroups | +| `_if_t` | Interface Types | `_mp` | Modports | +| `_if` | Interface Instances | `_cnstr` | Constraints | +| `_vif` | Virtual Interface Instances | `_cg` | Covergroups | | | | | | The purpose of these suffixes is: @@ -300,7 +300,7 @@ verif/vkits/foo/ mentor.flist foo_agent.sv foo_drv.sv - foo_intf.sv + foo_if.sv foo_item.sv foo_macros.sv foo_mon.sv @@ -420,9 +420,9 @@ See the SystemVerilog standard 1800-2012, section 6.18, for more information on Interfaces cannot be defined inside of a package, so they are compiled separately. -2.5.1. The name of the interface shall be `__intf`, where `` is the kit prefix. +2.5.1. The name of the interface shall be `__if`, where `` is the kit prefix. -2.5.2. *Recommended*: The name of the file containing the interface definition should be `__intf.sv`. +2.5.2. *Recommended*: The name of the file containing the interface definition should be `__if.sv`. 2.5.3. *Recommended*: `_` is unnecessary if there is only one interface defined in the verification kit. This alternative also applies to 2.6.1. (See File Naming.) @@ -457,7 +457,7 @@ The simulation requirement is only necessary when different simulators are used, ```sh verif/vkits/foo/vcs.flist: +incdir+../../verif/vkits/foo -../../verif/vkits/foo/foo_intf.sv +../../verif/vkits/foo/foo_if.sv ../../verif/vkits/foo/foo_pkg.sv ``` @@ -689,16 +689,16 @@ In this module, the DUT is instantiated (or, a wrapper module that instantiates 4.4.1. *Recommended*: The `tb_top` module shall instantiate all interfaces that connect to the DUT and provide virtual interfaces that point to these interfaces to the verification environment via the UVM resource database. -4.4.2. *Recommended*: Use the macro `` `cmn_set_intf `` to push virtual interface handles into the resource database. +4.4.2. *Recommended*: Use the macro `` `cmn_set_if `` to push virtual interface handles into the resource database. ```v module tb_top; - foo_intf foo_i; + foo_if_t foo_if; - blk_wrapper dut_wrapper(.foo_intf (foo_i)); + blk_wrapper dut_wrapper(.foo_if_t (foo_if)); function void pre_run_test(); - `cmn_set_intf(virtual foo_intf, "foo_pkg::intf", "foo_vi", foo_i); + `cmn_set_if(virtual foo_if_t, "foo_pkg::if", "foo_vif", foo_if); endfunction : pre_run_test initial begin @@ -709,13 +709,13 @@ endmodule : tb_top ``` -In this example, `foo_pkg::intf` is the scope, and `foo_vi` is the name, under which the virtual interface is stored in the UVM resource database. +In this example, `foo_pkg::if` is the scope, and `foo_vif` is the name, under which the virtual interface is stored in the UVM resource database. Within the module `tb_top`, the structure of the UVM component hierarchy is not necessarily known, which is why the UVM configuration database is not used. Instead, virtual interfaces are put into the UVM resource database, essentially making them globally visible to all UVM components. -In the example above, the scope name ("`foo_pkg::intf`") is a name that is required by the foo verification kit. (The `FOO` vkit is hardcoded to look for its interfaces using that scope name.) Note that the scope name starts with `_pkg`, as required. +In the example above, the scope name ("`foo_pkg::if`") is a name that is required by the foo verification kit. (The `FOO` vkit is hardcoded to look for its interfaces using that scope name.) Note that the scope name starts with `_pkg`, as required. -The name ("`foo_vi`" in the example) is a name that is provided by the `tb_top`. The `base_test_c` has knowledge of these names, since it is part of the same testbench as `tb_top`. +The name ("`foo_vif`" in the example) is a name that is provided by the `tb_top`. The `base_test_c` has knowledge of these names, since it is part of the same testbench as `tb_top`. The `base_test_c` knows the UVM component hierarchy, so it can provide the interface names to the appropriate UVM components through the UVM configuration database: @@ -726,7 +726,7 @@ class base_test_c; function void build_phase(uvm_phase phase); super.build_phase(phase); foo_env = foo_pkg::env_c::type_id::create("foo_env", this); - uvm_config_db#(string)::set(this, "foo_env", "intf_name", "foo_vi"); + uvm_config_db#(string)::set(this, "foo_env", "if_name", "foo_vif"); … ``` @@ -736,28 +736,28 @@ The above method for passing virtual interfaces to the verification environment 4.4.3. Components only get handles to virtual interfaces from the UVM resource database. -4.4.4. The component defines a string configuration field that is used to look up the virtual interface (`intf_name`, by custom). +4.4.4. The component defines a string configuration field that is used to look up the virtual interface (`if_name`, by custom). 4.4.5. The vkit defines a scope name under which all virtual interfaces for all instances of the verification kit are stored. -4.4.6. *Recommended*: Use the macro `` `cmn_get_intf `` to pull virtual interface handles from the resource database. +4.4.6. *Recommended*: Use the macro `` `cmn_get_if `` to pull virtual interface handles from the resource database. 4.4.7. *Recommended*: Components should use the `` `uvm_component_utils `` macros to declare configurable variables which perform database lookups during the build phase. Such variables should have the `UVM_COMPONENT` flag attached. -Extending the example from above, the `foo_pkg::env_c` class has a configuration field called "`intf_name`". Wherever a FOO class needs to get the virtual interface to a `foo_intf`, it knows to look in the UVM resource database under the scope `foo_pkg::intf`, and the name specified by the `intf_name` field. If the interface was not registered or was registered with a different name, a fatal error prints out and reports that `` is not found in the database. +Extending the example from above, the `foo_pkg::env_c` class has a configuration field called "`if_name`". Wherever a FOO class needs to get the virtual interface to a `foo_if_t`, it knows to look in the UVM resource database under the scope `foo_pkg::if`, and the name specified by the `if_name` field. If the interface was not registered or was registered with a different name, a fatal error prints out and reports that `` is not found in the database. ```v class env_c; `uvm_component_utils_begin(env_c) - `uvm_field_string(intf_name, UVM_COMPONENT) + `uvm_field_string(if_name, UVM_COMPONENT) //... - string intf_name = ""; - virtual foo_intf foo_vi; + string if_name = ""; + virtual foo_if_t foo_vif; //TODO: vi= viritual interface, should this be if_vi? function void build_phase(uvm_phase phase); super.build_phase(phase); - `cmn_get_intf(virtual foo_intf, "foo_pkg::intf", intf_name, foo_vi) + `cmn_get_if(virtual foo_if_t, "foo_pkg::if", if_name, foo_vif) //... ``` diff --git a/docs/VerifPlans/ISA/RV32/Simulation/RV32B_Extension_Instructions.xlsx b/docs/VerifPlans/ISA/RV32/Simulation/RV32B_Extension_Instructions.xlsx index 1a06880f8a..a06190b9c1 100755 Binary files a/docs/VerifPlans/ISA/RV32/Simulation/RV32B_Extension_Instructions.xlsx and b/docs/VerifPlans/ISA/RV32/Simulation/RV32B_Extension_Instructions.xlsx differ diff --git a/lib/corev-dv/corev_asm_program_gen.sv b/lib/corev-dv/corev_asm_program_gen.sv index 67a089064f..26103e961f 100644 --- a/lib/corev-dv/corev_asm_program_gen.sv +++ b/lib/corev-dv/corev_asm_program_gen.sv @@ -36,9 +36,23 @@ class corev_asm_program_gen extends riscv_asm_program_gen; instr_stream.push_back(".section .text.start"); instr_stream.push_back(""); - instr_stream.push_back(".section .mtvec_bootstrap, \"ax\""); - instr_stream.push_back(".globl _mtvec_bootstrap"); - instr_stream.push_back(" j mtvec_handler"); + if (cfg.mtvec_mode == DIRECT) begin + instr_stream.push_back(".section .mtvec_bootstrap, \"ax\""); + instr_stream.push_back(".globl _mtvec_bootstrap"); + instr_stream.push_back(" j mtvec_handler"); + instr_stream.push_back(".section .nmi_bootstrap, \"ax\""); + instr_stream.push_back(".globl _nmi_bootstrap"); + instr_stream.push_back(" j nmi_handler"); + end else if (cfg.mtvec_mode == CLIC) begin + instr_stream.push_back(".section .mtvec_bootstrap, \"ax\""); + instr_stream.push_back(".globl _mtvec_bootstrap"); + instr_stream.push_back(" j mtvec_handler"); + end else begin + instr_stream.push_back(".globl vectored_mode"); + instr_stream.push_back(".section .mtvec_handler, \"ax\""); + instr_stream.push_back(".globl mtvec_handler"); + instr_stream.push_back(".type mtvec_handler, @function"); + end instr_stream.push_back(""); instr_stream.push_back(".globl _start"); diff --git a/lib/corev-dv/corev_instr_base_test.sv b/lib/corev-dv/corev_instr_base_test.sv index 58395c2f75..9884f70cf2 100644 --- a/lib/corev-dv/corev_instr_base_test.sv +++ b/lib/corev-dv/corev_instr_base_test.sv @@ -44,7 +44,7 @@ class corev_instr_base_test extends riscv_instr_base_test; virtual function void build_phase(uvm_phase phase); super.build_phase(phase); - endfunction + endfunction task run_phase(uvm_phase phase); int fd; @@ -52,6 +52,7 @@ class corev_instr_base_test extends riscv_instr_base_test; string test_name; randomize_cfg(); riscv_instr::create_instr_list(cfg); + riscv_csr_instr::create_csr_filter(cfg); asm_gen = corev_asm_program_gen::type_id::create("asm_gen", , `gfn); asm_gen.cfg = cfg; asm_gen.get_directed_instr_stream(); diff --git a/lib/corev-dv/instr_lib/corev_interrupt_csr_instr_stream.sv b/lib/corev-dv/instr_lib/corev_interrupt_csr_instr_stream.sv index 297a5e6f22..5eb4d40d89 100644 --- a/lib/corev-dv/instr_lib/corev_interrupt_csr_instr_stream.sv +++ b/lib/corev-dv/instr_lib/corev_interrupt_csr_instr_stream.sv @@ -26,7 +26,7 @@ class corev_interrupt_csr_instr_stream extends riscv_load_store_rand_instr_stream; - typedef enum { + typedef enum { RANDOM_MIE, RANDOM_MSTATUS_MIE } interrupt_csr_action_enum; @@ -53,7 +53,7 @@ class corev_interrupt_csr_instr_stream extends riscv_load_store_rand_instr_strea `ifndef _VCP constraint default_wgt_c { soft wgt_random_mie == 1; - soft wgt_random_mstatus_mie == 3; + soft wgt_random_mstatus_mie == 3; } `endif @@ -79,10 +79,10 @@ class corev_interrupt_csr_instr_stream extends riscv_load_store_rand_instr_strea riscv_instr inserted_instr_list[$]; riscv_pseudo_instr li_instr; - riscv_instr csr_instr; + riscv_csr_instr csr_instr; // Instruction 0: Generate a li with a randomized mask - li_instr = riscv_pseudo_instr::type_id::create("LI"); + li_instr = riscv_pseudo_instr::type_id::create("LI"); `DV_CHECK_RANDOMIZE_WITH_FATAL(li_instr, pseudo_instr_name == LI; !(rd inside {reserved_rd, cfg.reserved_regs}); @@ -93,12 +93,12 @@ class corev_interrupt_csr_instr_stream extends riscv_load_store_rand_instr_strea li_instr.comment = $sformatf("corev-dv: Set MIE to 0x%08x", rand_mie_setting); li_instr.update_imm_str(); inserted_instr_list.push_back(li_instr); - + // Instruction 1: Generate a write, set or clear to MIE - csr_instr = riscv_instr::get_rand_instr(.include_instr(allowed_mie_instr)); - csr_instr.csr_c.constraint_mode(0); + csr_instr = riscv_csr_instr'(riscv_instr::get_rand_instr(.include_instr(allowed_mie_instr))); + csr_instr.csr_addr_c.constraint_mode(0); `DV_CHECK_RANDOMIZE_WITH_FATAL(csr_instr, - csr == MIE; + csr == MIE; !(rd inside {reserved_rd, cfg.reserved_regs}); rs1 == li_instr.rd; , "Cannot randomize MIE CSR instruction" @@ -110,11 +110,11 @@ class corev_interrupt_csr_instr_stream extends riscv_load_store_rand_instr_strea endfunction : generate_mie_write function void generate_mstatus_mie_write(); - riscv_instr csr_instr; + riscv_csr_instr csr_instr; - // Randomly set or clear bit 3 (MIE) in MSTATUS - csr_instr = riscv_instr::get_rand_instr(.include_instr({CSRRSI, CSRRCI})); - csr_instr.csr_c.constraint_mode(0); + // Randomly set or clear bit 3 (MIE) in MSTATUS + csr_instr = riscv_csr_instr'(riscv_instr::get_rand_instr(.include_instr({CSRRSI, CSRRCI}))); + csr_instr.csr_addr_c.constraint_mode(0); `DV_CHECK_RANDOMIZE_WITH_FATAL(csr_instr, csr == MSTATUS; !(rd inside {reserved_rd, cfg.reserved_regs}); @@ -127,4 +127,4 @@ class corev_interrupt_csr_instr_stream extends riscv_load_store_rand_instr_strea endclass : corev_interrupt_csr_instr_stream - \ No newline at end of file + diff --git a/lib/isa_decoder/isa_constants.sv b/lib/isa_decoder/isa_constants.sv new file mode 100644 index 0000000000..6a4e7ad8c4 --- /dev/null +++ b/lib/isa_decoder/isa_constants.sv @@ -0,0 +1,26 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// ------------------------------------------------------------------- +// This file holds constants related to the ISA decoder +// ------------------------------------------------------------------- + +`ifndef __ISA_CONSTANTS__ +`define __ISA_CONSTANTS__ + + + parameter CLIC_ID_WIDTH = 5; + + +`endif // __ISA_CONSTANTS__ diff --git a/lib/isa_decoder/isa_decoder.sv b/lib/isa_decoder/isa_decoder.sv new file mode 100644 index 0000000000..9bd20e596c --- /dev/null +++ b/lib/isa_decoder/isa_decoder.sv @@ -0,0 +1,1510 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// ------------------------------------------------------------------- +// This file holds the ISA decoder, and its subfunctions +// ------------------------------------------------------------------- + +`ifndef __ISA_DECODER__ +`define __ISA_DECODER__ + + + // --------------------------------------------------------------------------- + // Stack_adj for zcmp instructions + // --------------------------------------------------------------------------- + function int get_stack_adj( rlist_t rlist, logic[5:4] spimm); + int stack_adj_base; + int stack_adj; + + case(rlist) inside + [4:7]: stack_adj_base = 16; + [8:11]: stack_adj_base = 32; + [12:14]: stack_adj_base = 48; + 15: stack_adj_base = 64; + default: stack_adj_base = 0; + endcase + + stack_adj = stack_adj_base + spimm*16; + return stack_adj; + endfunction + + + // --------------------------------------------------------------------------- + // Non-trivial immediate decoder + // --------------------------------------------------------------------------- + function logic [20:1] get_sort_j_imm(instr_t instr); + get_sort_j_imm = { + instr.uncompressed.format.j.imm[31], + instr.uncompressed.format.j.imm[21:12], + instr.uncompressed.format.j.imm[22], + instr.uncompressed.format.j.imm[30:23] + }; + endfunction : get_sort_j_imm + + function logic [11:0] get_sort_s_imm(instr_t instr); + get_sort_s_imm = { + instr.uncompressed.format.s.imm_h, + instr.uncompressed.format.s.imm_l + }; + endfunction : get_sort_s_imm + + function logic [12:1] get_sort_b_imm(instr_t instr); + get_sort_b_imm = { + instr.uncompressed.format.b.imm_h[31], + instr.uncompressed.format.b.imm_l[7], + instr.uncompressed.format.b.imm_h[30:25], + instr.uncompressed.format.b.imm_l[11:8] + }; + endfunction : get_sort_b_imm + + function logic [5:0] get_sort_ci_imm_lwsp(instr_t instr); + get_sort_ci_imm_lwsp = { + instr.compressed.format.ci.imm_6_2[3:2], + instr.compressed.format.ci.imm_12, + instr.compressed.format.ci.imm_6_2[6:4] + }; + endfunction : get_sort_ci_imm_lwsp + + function logic [5:0] get_sort_ci_imm_addi16sp(instr_t instr); + get_sort_ci_imm_addi16sp = { + instr.compressed.format.ci.imm_12, + instr.compressed.format.ci.imm_6_2[4:3], + instr.compressed.format.ci.imm_6_2[5], + instr.compressed.format.ci.imm_6_2[2], + instr.compressed.format.ci.imm_6_2[6] + }; + endfunction : get_sort_ci_imm_addi16sp + + function logic [8:0] get_sort_cb_imm_not_sequential(instr_t instr); + get_sort_cb_imm_not_sequential = { + instr.compressed.format.cb.offset_12_10[12], + instr.compressed.format.cb.offset_6_2[6:5], + instr.compressed.format.cb.offset_6_2[2], + instr.compressed.format.cb.offset_12_10[11:10], + instr.compressed.format.cb.offset_6_2[4:3] + }; + endfunction : get_sort_cb_imm_not_sequential + + function logic [5:0] get_sort_cj_imm(instr_t instr); + get_sort_cj_imm = { + instr.compressed.format.cj.imm[12], + instr.compressed.format.cj.imm[8], + instr.compressed.format.cj.imm[10:9], + instr.compressed.format.cj.imm[6], + instr.compressed.format.cj.imm[7], + instr.compressed.format.cj.imm[2], + instr.compressed.format.cj.imm[11], + instr.compressed.format.cj.imm[5:3] + }; + endfunction : get_sort_cj_imm + + function logic [4:0] get_sort_cl_imm(instr_t instr); + get_sort_cl_imm = { + instr.compressed.format.cl.imm_6_5[5], + instr.compressed.format.cl.imm_12_10, + instr.compressed.format.cl.imm_6_5[6] + }; + endfunction : get_sort_cl_imm + + function logic [4:0] get_sort_cs_imm(instr_t instr); + get_sort_cs_imm = { + instr.compressed.format.cs.imm_6_5[5], + instr.compressed.format.cs.imm_12_10, + instr.compressed.format.cs.imm_6_5[6] + }; + endfunction : get_sort_cs_imm + + function logic [7:0] get_sort_ciw_imm(instr_t instr); + get_sort_ciw_imm = { + instr.compressed.format.ciw.imm[10:7], + instr.compressed.format.ciw.imm[12:11], + instr.compressed.format.ciw.imm[6], + instr.compressed.format.ciw.imm[5] + }; + endfunction : get_sort_ciw_imm + + function gpr_t get_gpr_from_gpr_rvc(gpr_rvc_t gpr); + gpr_t uncompressed_gpr; + casex (gpr.gpr) + C_X8: uncompressed_gpr.gpr = X8; + C_X9: uncompressed_gpr.gpr = X9; + C_X10: uncompressed_gpr.gpr = X10; + C_X11: uncompressed_gpr.gpr = X11; + C_X12: uncompressed_gpr.gpr = X12; + C_X13: uncompressed_gpr.gpr = X13; + C_X14: uncompressed_gpr.gpr = X14; + C_X15: uncompressed_gpr.gpr = X15; + default: uncompressed_gpr.gpr = X0; // Function used wrong if we ever end up here + endcase + + return uncompressed_gpr; + endfunction : get_gpr_from_gpr_rvc + + // --------------------------------------------------------------------------- + // Find the value of immediate + // --------------------------------------------------------------------------- + function int get_imm_value_i(logic[11:0] imm); + if(imm[11] == 1) begin + get_imm_value_i = {20'hfffff, imm}; + end else begin + get_imm_value_i = {20'b0, imm}; + end + endfunction : get_imm_value_i + + function int get_imm_value_j(logic[20:1] imm); + if(imm[20] == 1) begin + get_imm_value_j = {11'h7ff, imm, 1'b0}; + end else begin + get_imm_value_j = {11'b0, imm, 1'b0}; + end + endfunction : get_imm_value_j + + function int get_imm_value_b(logic[12:1] imm); + if(imm[12] == 1) begin + get_imm_value_b = {19'h7ffff, imm, 1'b0}; + end else begin + get_imm_value_b = {19'b0, imm, 1'b0}; + end + endfunction : get_imm_value_b + + function int get_imm_value_ci(logic[5:0] imm); + if(imm[5] == 1) begin + get_imm_value_ci = {26'h3ffffff, imm}; + end else begin + get_imm_value_ci = {26'b0, imm}; + end + endfunction : get_imm_value_ci + + function int get_imm_value_ci_lui(logic[17:12] imm); + if(imm[17] == 1) begin + get_imm_value_ci_lui = {14'h3fff, imm, 12'b0}; + end else begin + get_imm_value_ci_lui = {14'b0, imm, 12'b0}; + end + endfunction : get_imm_value_ci_lui + + function int get_imm_value_ci_addi16sp(logic[9:4] imm); + if(imm[9] == 1) begin + get_imm_value_ci_addi16sp = {22'h3fffff, imm, 4'b0}; + end else begin + get_imm_value_ci_addi16sp = {22'b0, imm, 4'b0}; + end + endfunction : get_imm_value_ci_addi16sp + + function int get_imm_value_cb(logic[8:1] imm); + if(imm[8] == 1) begin + get_imm_value_cb = {23'h7fffff, imm, 1'b0}; + end else begin + get_imm_value_cb = {22'b0, imm, 1'b0}; + end + endfunction : get_imm_value_cb + + function int get_imm_value_cj(logic[11:1] imm); + if(imm[11] == 1) begin + get_imm_value_cj = {20'hfffff, imm, 1'b0}; + end else begin + get_imm_value_cj = {20'b0, imm, 1'b0}; + end + endfunction : get_imm_value_cj + + + // Get the correspopnding name of the hint instruction + function hint_name_e get_hint_name(instr_name_e name); + hint_name_e hint_name; + + casex(name) + SLTI, SLTIU, ANDI, ORI, XORI, SLLI, SRLI, SRAI: hint_name = REG_IMM_I_H; + + ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU: hint_name = REG_REG_R_H; + + C_LUI, C_SLLI: hint_name = CONST_GEN_CI_H; + + C_MV, C_ADD: hint_name = REG_REG_CR_H; + + LUI, AUIPC:hint_name = REG_IMM_U_H; + + ADDI: hint_name = ADDI_H; + + FENCE: hint_name = FENCE_H; + + C_NOP: hint_name = C_NOP_H; + + C_ADDI: hint_name = C_ADDI_H; + + C_LI: hint_name = C_LI_H; + + default : hint_name = UNKNOWN_HINT; + endcase + + return hint_name; + endfunction + + // Find out if the instruction is a HINT. + function logic check_if_hint(instr_name_e name, instr_format_e format, instr_t instr); + logic hint; + + casex (get_hint_name(name)) + ADDI_H: hint = (instr.uncompressed.format.i.rd == X0 && (instr.uncompressed.format.i.rs1 != X0 || instr.uncompressed.format.i.imm != 12'b0)); + + FENCE_H: hint = ((instr.uncompressed.format.i.imm.funct7[27:25] == 3'b0 && instr.uncompressed.format.i.imm.shamt[24] == 1'b0) || instr.uncompressed.format.i.imm.shamt[23:20] == 4'b0); + + REG_IMM_I_H: hint = (instr.uncompressed.format.i.rd == X0); + + REG_IMM_U_H: hint = (instr.uncompressed.format.u.rd == X0); + + REG_REG_R_H: hint = (instr.uncompressed.format.r.rd == X0); + + C_NOP_H: hint = ((instr.compressed.format.ci.imm_12 != 1'b0 || instr.compressed.format.ci.imm_6_2 != 5'b0)); + + C_ADDI_H: hint = ((instr.compressed.format.ci.imm_12 == 1'b0 && instr.compressed.format.ci.imm_6_2 == 5'b0) && instr.compressed.format.ci.rd_rs1 != X0); + + C_LI_H: hint = (instr.compressed.format.ci.rd_rs1 == X0); + + CONST_GEN_CI_H: hint = (instr.compressed.format.ci.rd_rs1 == X0 && (instr.compressed.format.ci.imm_12 != 1'b0 || instr.compressed.format.ci.imm_6_2 != 5'b0)); + + REG_REG_CR_H: hint = (instr.compressed.format.cr.rd_rs1 == X0 && instr.compressed.format.cr.rs2 != X0); + + default : hint = 0; + endcase + + return hint; + endfunction + + + function logic[11:0] read_s_imm(logic[31:0] instr); + automatic logic [11:0] imm; + imm = {instr[31:25], instr[11:7]}; + return imm; + endfunction : read_s_imm + + + // --------------------------------------------------------------------------- + // build_asm intends to implement a decoder for the Risc-V ISA + // (Currently only RV32I, Zicsr plus a few select other instructions are + // supported) + // + // The ouput format intends to decode the instruction in a human readable + // manner, and aims to populate a structure that can be easily parsed to + // generate proper risc-v assembly code. + // --------------------------------------------------------------------------- + + function automatic asm_t build_asm(instr_name_e name, instr_format_e format, instr_t instr); + asm_t asm = { '0 }; + asm.instr = name; + asm.format = format; + + if(check_if_hint(name, format, instr)) begin + asm.is_hint = 1; + end + + casex (format) + I_TYPE: begin + if (asm.instr inside { FENCE_I, ECALL, EBREAK, MRET, DRET, WFI, WFE }) begin + asm.rd.valid = 0; + asm.rs1.valid = 0; + asm.rs2.valid = 0; + asm.imm.valid = 0; + end else if (asm.instr inside { FENCE }) begin + asm.imm.imm_raw = instr.uncompressed.format.i.imm; + asm.imm.imm_raw_sorted = instr.uncompressed.format.i.imm; + asm.imm.imm_type = IMM; + asm.imm.width = 12; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_i(instr.uncompressed.format.i.imm); + asm.imm.valid = 1; + end else if (asm.instr inside { CSRRW, CSRRS, CSRRC }) begin + asm.rd.gpr = instr.uncompressed.format.i.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.i.rs1.gpr; + asm.csr.address = instr.uncompressed.format.i.imm; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.csr.valid = 1; + end else if (asm.instr inside { CSRRWI, CSRRSI, CSRRCI }) begin + asm.rd.gpr = instr.uncompressed.format.i.rd.gpr; + asm.imm.imm_raw = instr.uncompressed.format.i.rs1; + asm.imm.imm_raw_sorted = instr.uncompressed.format.i.rs1; + asm.imm.imm_type = UIMM; + asm.imm.width = 5; + asm.imm.imm_value = instr.uncompressed.format.i.rs1; + asm.csr.address = instr.uncompressed.format.i.imm; + asm.rd.valid = 1; + asm.imm.valid = 1; + asm.csr.valid = 1; + end else if (asm.instr inside { RORI, BEXTI, BCLRI, BINVI, BSETI, SLLI, SRLI, SRAI }) begin + asm.rd.gpr = instr.uncompressed.format.i.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.i.rs1.gpr; + asm.imm.imm_raw = instr.uncompressed.format.i.imm.shamt; + asm.imm.imm_raw_sorted = instr.uncompressed.format.i.imm.shamt; + asm.imm.imm_type = SHAMT; + asm.imm.width = 5; + asm.imm.imm_value = instr.uncompressed.format.i.imm.shamt; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.imm.valid = 1; + end else begin + asm.rd.gpr = instr.uncompressed.format.i.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.i.rs1.gpr; + asm.imm.imm_raw = instr.uncompressed.format.i.imm; + asm.imm.imm_raw_sorted = instr.uncompressed.format.i.imm; + asm.imm.imm_type = IMM; + asm.imm.width = 12; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_i(instr.uncompressed.format.i.imm); + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.imm.valid = 1; + end + end + J_TYPE: begin + asm.rd.gpr = instr.uncompressed.format.j.rd.gpr; + asm.imm.imm_raw = instr.uncompressed.format.j.imm; + asm.imm.imm_raw_sorted = get_sort_j_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 20; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_j(get_sort_j_imm(instr)); + asm.rd.valid = 1; + asm.imm.valid = 1; + end + S_TYPE: begin + asm.rs1.gpr = instr.uncompressed.format.s.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.s.rs2.gpr; + asm.imm.imm_raw = get_sort_s_imm(instr); + asm.imm.imm_raw_sorted = get_sort_s_imm(instr); + asm.imm.imm_type = IMM; + asm.imm.width = 12; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_i(get_sort_s_imm(instr)); + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.imm.valid = 1; + end + R_TYPE: begin + if ( asm.instr inside { LR_W, SC_W, AMOSWAP_W, AMOADD_W, AMOXOR_W, AMOAND_W, AMOOR_W, AMOMIN_W, AMOMAX_W, AMOMINU_W, AMOMAXU_W } ) begin + asm.rd.gpr = instr.uncompressed.format.r.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.r.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.r.rs2.gpr; + asm.atomic.aq = instr.uncompressed.format.r.funct7[26]; + asm.atomic.rl = instr.uncompressed.format.r.funct7[25]; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.atomic.valid = 1; + end else begin + asm.rd.gpr = instr.uncompressed.format.r.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.r.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.r.rs2.gpr; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + end + end + R4_TYPE: begin + asm.rd.gpr = instr.uncompressed.format.r4.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.r4.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.r4.rs2.gpr; + asm.rs3.gpr = instr.uncompressed.format.r4.rs3.gpr; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.rs3.valid = 1; + end + B_TYPE: begin + asm.rs1.gpr = instr.uncompressed.format.b.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.b.rs2.gpr; + asm.imm.imm_raw = {instr.uncompressed.format.b.imm_h, instr.uncompressed.format.b.imm_l}; + asm.imm.imm_raw_sorted = get_sort_b_imm(instr); + asm.imm.imm_type = IMM; + asm.imm.width = 12; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_b(get_sort_b_imm(instr)); + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.imm.valid = 1; + end + U_TYPE: begin + asm.rd.gpr = instr.uncompressed.format.u.rd.gpr; + asm.imm.imm_raw = instr.uncompressed.format.u.imm; + asm.imm.imm_raw_sorted = instr.uncompressed.format.u.imm; + asm.imm.imm_type = IMM; + asm.imm.width = 20; + asm.imm.imm_value = { instr.uncompressed.format.u.imm, 12'b0000_0000_0000 }; + asm.rd.valid = 1; + asm.imm.valid = 1; + end + // Compressed + CR_TYPE: begin + if (name inside { C_EBREAK }) begin + asm.rd.valid = 0; + asm.rs1.valid = 0; + asm.rs2.valid = 0; + asm.rs3.valid = 0; + asm.imm.valid = 0; + end else if (name inside { C_MV }) begin + asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; + asm.rd.valid = 1; + asm.rs2.valid = 1; + asm.rs1.valid = 1; + end else if (name inside { C_ADD }) begin + asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + end else if (name inside { C_JR, C_JALR }) begin + asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + end + end + CI_TYPE: begin + if (name inside { C_NOP, C_ADDI }) begin + asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.rs1.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_raw_sorted = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_type = IMM; + asm.imm.width = 6; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_ci({ instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }); + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.imm.valid = 1; + end else if (name == C_LI) begin + asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_raw_sorted = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_type = IMM; + asm.imm.width = 6; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_ci({ instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }); + asm.rd.valid = 1; + asm.imm.valid = 1; + end else if (name == C_LUI) begin + asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_raw_sorted = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_type = NZIMM; + asm.imm.width = 6; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_ci_lui({ instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }); + asm.rd.valid = 1; + asm.imm.valid = 1; + end else if (name inside { C_LWSP }) begin + asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_raw_sorted = get_sort_ci_imm_lwsp(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 6; + asm.imm.imm_value = {24'b0, get_sort_ci_imm_lwsp(instr), 2'b0}; + asm.rd.valid = 1; + asm.imm.valid = 1; + end else if (name inside { C_ADDI16SP }) begin + asm.rs1.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_raw_sorted = get_sort_ci_imm_addi16sp(instr); + asm.imm.imm_type = NZIMM; + asm.imm.width = 6; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_ci_addi16sp(get_sort_ci_imm_addi16sp(instr)); + asm.rs1.valid = 1; + asm.rd.valid = 1; + asm.imm.valid = 1; + end else if (name inside { C_SLLI }) begin + asm.rs1.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_raw_sorted = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.imm.imm_type = SHAMT; + asm.imm.width = 6; + asm.imm.imm_value = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; + asm.rs1.valid = 1; + asm.rd.valid = 1; + asm.imm.valid = 1; + end + end + CSS_TYPE: begin + asm.rs2.gpr = instr.compressed.format.css.rs2.gpr; + asm.imm.imm_raw = instr.compressed.format.css.imm; + asm.imm.imm_raw_sorted = { instr.compressed.format.css.imm[9:7], instr.compressed.format.css.imm[12:10] }; + asm.imm.imm_type = OFFSET; + asm.imm.width = 6; + asm.imm.imm_value = { 24'b0, instr.compressed.format.css.imm[9:7], instr.compressed.format.css.imm[12:10], 2'b0 }; + asm.rs2.valid = 1; + asm.imm.valid = 1; + end + CIW_TYPE: begin + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ciw.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.ciw.rd.gpr; + asm.imm.imm_raw = instr.compressed.format.ciw.imm; + asm.imm.imm_raw_sorted = get_sort_ciw_imm(instr); + asm.imm.imm_type = NZUIMM; + asm.imm.width = 8; + asm.imm.imm_value = { 22'b0, get_sort_ciw_imm(instr), 2'b0 }; + asm.imm.valid = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + end + CL_TYPE: begin + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cl.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.cl.rd.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cl.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cl.rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.cl.imm_12_10, instr.compressed.format.cl.imm_6_5 }; + asm.imm.imm_raw_sorted = get_sort_cl_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 5; + asm.imm.imm_value = { 25'b0, get_sort_cl_imm(instr), 2'b0 }; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end + CS_TYPE: begin + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cs.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.cs.rs2.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cs.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cs.rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.cs.imm_12_10, instr.compressed.format.cs.imm_6_5 }; + asm.imm.imm_raw_sorted = get_sort_cs_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 5; + asm.imm.imm_value = { 25'b0, get_sort_cs_imm(instr), 2'b0 }; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end + CA_TYPE: begin + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ca.rd_rs1.gpr); + asm.rd.gpr_rvc = instr.compressed.format.ca.rd_rs1.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ca.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.ca.rd_rs1.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ca.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.ca.rs2.gpr; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + end + CB_TYPE: begin + if (name inside { C_SRLI, C_SRAI }) begin + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rd.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; + asm.imm.imm_raw_sorted = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; + asm.imm.imm_type = SHAMT; + asm.imm.width = 6; + asm.imm.imm_value = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end else if (name inside { C_BEQZ, C_BNEZ }) begin + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.cb.offset_12_10, instr.compressed.format.cb.offset_6_2 }; + asm.imm.imm_raw_sorted = get_sort_cb_imm_not_sequential(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 8; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_cb(get_sort_cb_imm_not_sequential(instr)); + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end + end + CJ_TYPE: begin + asm.imm.imm_raw = instr.compressed.format.cj.imm; + asm.imm.imm_raw_sorted = get_sort_cj_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 11; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_cj(get_sort_cj_imm(instr)); + asm.imm.valid = 1; + end + CLB_TYPE: begin + asm.imm.imm_raw = instr.compressed.format.clb.uimm; + asm.imm.imm_raw_sorted = { instr.compressed.format.clb.uimm[5], instr.compressed.format.clb.uimm[6] }; + asm.imm.imm_type = UIMM; + asm.imm.width = 2; + asm.imm.imm_value = { instr.compressed.format.clb.uimm[5], instr.compressed.format.clb.uimm[6] }; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clb.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.clb.rs1.gpr; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clb.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.clb.rd.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end + CSB_TYPE: begin + asm.imm.imm_raw = instr.compressed.format.csb.uimm; + asm.imm.imm_raw_sorted = { instr.compressed.format.csb.uimm[5], instr.compressed.format.csb.uimm[6] }; + asm.imm.imm_type = UIMM; + asm.imm.width = 2; + asm.imm.imm_value = { instr.compressed.format.csb.uimm[5], instr.compressed.format.csb.uimm[6] }; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csb.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.csb.rs1.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csb.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.csb.rs2.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end + CLH_TYPE: begin + asm.imm.imm_raw = instr.compressed.format.clh.uimm; + asm.imm.imm_raw_sorted = instr.compressed.format.clh.uimm; + asm.imm.imm_type = UIMM; + asm.imm.width = 1; + asm.imm.imm_value = { 30'b0, instr.compressed.format.clh.uimm }; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clh.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.clh.rs1.gpr; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clh.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.clh.rd.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end + CSH_TYPE: begin + asm.imm.imm_raw = instr.compressed.format.csh.uimm; + asm.imm.imm_raw_sorted = instr.compressed.format.csh.uimm; + asm.imm.imm_type = UIMM; + asm.imm.width = 1; + asm.imm.imm_value = {30'b0, instr.compressed.format.csh.uimm, 1'b0}; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csh.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.csh.rs1.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csh.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.csh.rs2.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end + CU_TYPE: begin + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cu.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cu.rd_rs1.gpr; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cu.rd_rs1.gpr); + asm.rd.gpr_rvc = instr.compressed.format.cu.rd_rs1.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + end + CMMV_TYPE: begin + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cmmv.r1s.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cmmv.r1s.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cmmv.r2s.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.cmmv.r2s.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + end + CMJT_TYPE: begin + asm.imm.imm_raw = instr.compressed.format.cmjt.index; + asm.imm.imm_raw_sorted = instr.compressed.format.cmjt.index; + asm.imm.imm_type = INDEX; + asm.imm.width = 1; + asm.imm.imm_value = instr.compressed.format.cmjt.index; + asm.imm.valid = 1; + end + CMPP_TYPE: begin + asm.imm.imm_raw = instr.compressed.format.cmpp.spimm; + asm.imm.imm_raw_sorted = instr.compressed.format.cmpp.spimm; + asm.imm.imm_type = SPIMM; + asm.imm.width = 1; + asm.rlist.rlist = instr.compressed.format.cmpp.urlist; + asm.stack_adj.stack_adj = get_stack_adj(instr.compressed.format.cmpp.urlist, instr.compressed.format.cmpp.spimm); + asm.imm.valid = 1; + asm.rs1.gpr = instr.compressed.format.csh.rs1.gpr; + asm.rs2.gpr = instr.compressed.format.csh.rs2.gpr; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.rlist.valid = 1; + asm.stack_adj.valid = 1; + end + + default : ; + endcase + + return asm; + endfunction : build_asm + + // --------------------------------------------------------------------------- + // Main decoder logic, identifies type and instruction name, + // add instructions here as needed. + // --------------------------------------------------------------------------- + function automatic asm_t decode_instr(instr_t instr); + asm_t asm = { '0 }; + case (1) + + ( (instr.uncompressed.opcode == MISC_MEM) + && (instr.uncompressed.format.i.funct3 == 3'b0)) : + asm = build_asm(FENCE, I_TYPE, instr); + + ( (instr.uncompressed.opcode == MISC_MEM) + && (instr.uncompressed.format.i.funct3 == 3'b001)) : + asm = build_asm(FENCE_I, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.imm == 12'b0000_0000_0000)) : + asm = build_asm(ECALL, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.imm == 12'b0000_0000_0001)) : + asm = build_asm(EBREAK, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.rd == 5'b0_0000) + && (instr.uncompressed.format.i.funct3 == 3'b000) + && (instr.uncompressed.format.i.rs1 == 5'b0_0000) + && (instr.uncompressed.format.i.imm == 12'b0011_0000_0010)) : + asm = build_asm(MRET, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.imm == 12'b0111_1011_0010)) : + asm = build_asm(DRET, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.rd == 5'b0_0000) + && (instr.uncompressed.format.i.funct3 == 3'b000) + && (instr.uncompressed.format.i.rs1 == 5'b0_0000) + && (instr.uncompressed.format.i.imm == 12'b0001_0000_0101)) : + asm = build_asm(WFI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.rd == 5'b0_0000) + && (instr.uncompressed.format.i.funct3 == 3'b000) + && (instr.uncompressed.format.i.rs1 == 5'b0_0000) + && (instr.uncompressed.format.i.imm == 12'b1000_1100_0000)) : + asm = build_asm(WFE, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_CSRRW)) : + asm = build_asm(CSRRW, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_CSRRS)) : + asm = build_asm(CSRRS, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_CSRRC)) : + asm = build_asm(CSRRC, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_CSRRWI)) : + asm = build_asm(CSRRWI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_CSRRSI)) : + asm = build_asm(CSRRSI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == SYSTEM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_CSRRCI)) : + asm = build_asm(CSRRCI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == STORE) + && (instr.uncompressed.format.s.funct3 == FUNCT3_SB)) : + asm = build_asm(SB, S_TYPE, instr); + + ( (instr.uncompressed.opcode == STORE) + && (instr.uncompressed.format.s.funct3 == FUNCT3_SH)) : + asm = build_asm(SH, S_TYPE, instr); + + ( (instr.uncompressed.opcode == STORE) + && (instr.uncompressed.format.s.funct3 == FUNCT3_SW)) : + asm = build_asm(SW, S_TYPE, instr); + + ( (instr.uncompressed.opcode == LOAD) + && (instr.uncompressed.format.i.funct3 == FUNCT3_LB)) : + asm = build_asm(LB, I_TYPE, instr); + + ( (instr.uncompressed.opcode == LOAD) + && (instr.uncompressed.format.i.funct3 == FUNCT3_LH)) : + asm = build_asm(LH, I_TYPE, instr); + + ( (instr.uncompressed.opcode == LOAD) + && (instr.uncompressed.format.i.funct3 == FUNCT3_LW)) : + asm = build_asm(LW, I_TYPE, instr); + + ( (instr.uncompressed.opcode == LOAD) + && (instr.uncompressed.format.i.funct3 == FUNCT3_LBU)) : + asm = build_asm(LBU, I_TYPE, instr); + + ( (instr.uncompressed.opcode == LOAD) + && (instr.uncompressed.format.i.funct3 == FUNCT3_LHU)) : + asm = build_asm(LHU, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ADDI)) : + asm = build_asm(ADDI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_SLTI)) : + asm = build_asm(SLTI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_SLTIU)) : + asm = build_asm(SLTIU, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_XORI)) : + asm = build_asm(XORI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ORI)) : + asm = build_asm(ORI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ANDI)) : + asm = build_asm(ANDI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_SLLI) + && (instr.uncompressed.format.i.imm.funct7 == 7'b0000000)) : + asm = build_asm(SLLI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_SRLI_SRAI) + && (instr.uncompressed.format.i.imm.funct7 == 7'b0000000)) : + asm = build_asm(SRLI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_SRLI_SRAI) + && (instr.uncompressed.format.i.imm.funct7 == 7'b0100000)) : + asm = build_asm(SRAI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_ADD_SUB) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(ADD, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_ADD_SUB) + && (instr.uncompressed.format.r.funct7 == 7'b0100000)) : + asm = build_asm(SUB, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SLL) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(SLL, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SLT) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(SLT, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SLTU) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(SLTU, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_XOR) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(XOR, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SRL_SRA) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(SRL, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SRL_SRA) + && (instr.uncompressed.format.r.funct7 == 7'b0100000)) : + asm = build_asm(SRA, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_OR) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(OR, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_AND) + && (instr.uncompressed.format.r.funct7 == 7'b0000000)) : + asm = build_asm(AND, R_TYPE, instr); + + ( (instr.uncompressed.opcode == LUI_OP) ) : + asm = build_asm(LUI, U_TYPE, instr); + + ( (instr.uncompressed.opcode == AUIPC_OP) ) : + asm = build_asm(AUIPC, U_TYPE, instr); + + ( (instr.uncompressed.opcode == JALR_OP) ) : + asm = build_asm(JALR, I_TYPE, instr); + + ( (instr.uncompressed.opcode == JAL_OP) ) : + asm = build_asm(JAL, J_TYPE, instr); + + ( (instr.uncompressed.opcode == BRANCH) + && (instr.uncompressed.format.b.funct3 == FUNCT3_BEQ)) : + asm = build_asm(BEQ, B_TYPE, instr); + + ( (instr.uncompressed.opcode == BRANCH) + && (instr.uncompressed.format.b.funct3 == FUNCT3_BNE)) : + asm = build_asm(BNE, B_TYPE, instr); + + ( (instr.uncompressed.opcode == BRANCH) + && (instr.uncompressed.format.b.funct3 == FUNCT3_BLT)) : + asm = build_asm(BLT, B_TYPE, instr); + + ( (instr.uncompressed.opcode == BRANCH) + && (instr.uncompressed.format.b.funct3 == FUNCT3_BGE)) : + asm = build_asm(BGE, B_TYPE, instr); + + ( (instr.uncompressed.opcode == BRANCH) + && (instr.uncompressed.format.b.funct3 == FUNCT3_BLTU)) : + asm = build_asm(BLTU, B_TYPE, instr); + + ( (instr.uncompressed.opcode == BRANCH) + && (instr.uncompressed.format.b.funct3 == FUNCT3_BGEU)) : + asm = build_asm(BGEU, B_TYPE, instr); + + //A + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.rs2 == X0) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_LR_W)) : + asm = build_asm(LR_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_SC_W)) : + asm = build_asm(SC_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOSWAP_W)) : + asm = build_asm(AMOSWAP_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOADD_W)) : + asm = build_asm(AMOADD_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOXOR_W)) : + asm = build_asm(AMOXOR_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOAND_W)) : + asm = build_asm(AMOAND_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOOR_W)) : + asm = build_asm(AMOOR_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOMIN_W)) : + asm = build_asm(AMOMIN_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOMAX_W)) : + asm = build_asm(AMOMAX_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOMINU_W)) : + asm = build_asm(AMOMINU_W, R_TYPE, instr); + + ( (instr.uncompressed.opcode == AMO) + && (instr.uncompressed.format.r.funct3 == FUNCT3_A_W) + && (instr.uncompressed.format.r.funct7[31:27] == FUNCT5_AMOMAXU_W)) : + asm = build_asm(AMOMAXU_W, R_TYPE, instr); + + //Zba + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SH1ADD) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBA)) : + asm = build_asm(SH1ADD, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SH2ADD) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBA)) : + asm = build_asm(SH2ADD, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_SH3ADD) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBA)) : + asm = build_asm(SH3ADD, R_TYPE, instr); + + //Zbb + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MIN) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_MIN_MAX)) : + asm = build_asm(MIN, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MINU) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_MIN_MAX)) : + asm = build_asm(MINU, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MAX) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_MIN_MAX)) : + asm = build_asm(MAX, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MAXU) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_MIN_MAX)) : + asm = build_asm(MAXU, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_C) + && (instr.uncompressed.format.i.imm == 12'b0110_0000_0010)) : + asm = build_asm(CPOP, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_C) + && (instr.uncompressed.format.i.imm == 12'b0110_0000_0001)) : + asm = build_asm(CTZ, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ORC_B) + && (instr.uncompressed.format.i.imm == 12'b0010_1000_0111)) : + asm = build_asm(ORC_B, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_ORN) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_LOGICAL)) : + asm = build_asm(ORN, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_C) + && (instr.uncompressed.format.i.imm == 12'b0110_0000_0000)) : + asm = build_asm(CLZ, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_ANDN) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_LOGICAL)) : + asm = build_asm(ANDN, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_ROL) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_ROTATE)) : + asm = build_asm(ROL, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_ROR_RORI) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_ROTATE)) : + asm = build_asm(ROR, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ROR_RORI) + && (instr.uncompressed.format.i.imm.funct7 == FUNCT7_ZBB_ROTATE )) : + asm = build_asm(RORI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_XNOR) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBB_LOGICAL)) : + asm = build_asm(XNOR, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_REV8) + && (instr.uncompressed.format.i.imm == 12'b0110_1001_1000)) : + asm = build_asm(REV8, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_SEXT) + && (instr.uncompressed.format.i.imm == 12'b0110_0000_0100)) : + asm = build_asm(SEXT_B, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_SEXT) + && (instr.uncompressed.format.i.imm == 12'b0110_0000_0101)) : + asm = build_asm(SEXT_H, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ZEXT_H) + && (instr.uncompressed.format.i.imm == 12'b0000_1000_0000)) : + asm = build_asm(ZEXT_H, I_TYPE, instr); + + //Zbc + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_CLMUL) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBC)) : + asm = build_asm(CLMUL, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_CLMULH) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBC)) : + asm = build_asm(CLMULH, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_CLMULR) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBC)) : + asm = build_asm(CLMULR, R_TYPE, instr); + + //Zbs + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_BEXT_BEXTI) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBS_BCLR_BEXT)) : + asm = build_asm(BEXT, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_BEXT_BEXTI) + && (instr.uncompressed.format.i.imm.funct7 == FUNCT7_ZBS_BCLR_BEXT)) : + asm = build_asm(BEXTI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_B_BI) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBS_BCLR_BEXT)) : + asm = build_asm(BCLR, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_B_BI) + && (instr.uncompressed.format.i.imm.funct7 == FUNCT7_ZBS_BCLR_BEXT)) : + asm = build_asm(BCLRI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_B_BI) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBS_BINV)) : + asm = build_asm(BINV, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_B_BI) + && (instr.uncompressed.format.i.imm.funct7 == FUNCT7_ZBS_BINV)) : + asm = build_asm(BINVI, I_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_B_BI) + && (instr.uncompressed.format.r.funct7 == FUNCT7_ZBS_BSET)) : + asm = build_asm(BSET, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP_IMM) + && (instr.uncompressed.format.i.funct3 == FUNCT3_B_BI) + && (instr.uncompressed.format.i.imm.funct7 == FUNCT7_ZBS_BSET)) : + asm = build_asm(BSETI, I_TYPE, instr); + + //M + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MUL) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(MUL, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MULH) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(MULH, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MULHSU) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(MULHSU, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_MULHU) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(MULHU, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_DIV) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(DIV, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_DIVU) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(DIVU, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_REM) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(REM, R_TYPE, instr); + + ( (instr.uncompressed.opcode == OP) + && (instr.uncompressed.format.r.funct3 == FUNCT3_REMU) + && (instr.uncompressed.format.r.funct7 == FUNCT7_M)) : + asm = build_asm(REMU, R_TYPE, instr); + + // Compressed + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.ci.rd_rs1.gpr == X0) + && (instr.compressed.format.ci.imm_12 == 1'b0) + && (instr.compressed.format.ci.imm_6_2 == 5'b0) + && (instr.compressed.format.ci.funct3 == 3'b0)) : + asm = build_asm(ILLEGAL_INSTR, CI_TYPE, instr); + + // Zca + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cr.rd_rs1.gpr == X0) + && (instr.compressed.format.cr.rs2.gpr == X0) + && (instr.compressed.format.cr.funct4 == 4'b1001)) : + asm = build_asm(C_EBREAK, CR_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cr.rs2.gpr != X0) + && (instr.compressed.format.cr.funct4 == 4'b1000)) : + asm = build_asm(C_MV, CR_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cr.rs2.gpr != X0) + && (instr.compressed.format.cr.funct4 == 4'b1001)) : + asm = build_asm(C_ADD, CR_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cr.rd_rs1.gpr != X0) + && (instr.compressed.format.cr.rs2.gpr == X0) + && (instr.compressed.format.cr.funct4 == 4'b1000)) : + asm = build_asm(C_JR, CR_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cr.rd_rs1.gpr != X0) + && (instr.compressed.format.cr.rs2.gpr == X0) + && (instr.compressed.format.cr.funct4 == 4'b1001)) : + asm = build_asm(C_JALR, CR_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.ci.rd_rs1.gpr != X0) + && (instr.compressed.format.ci.funct3 == FUNCT3_C_LWSP)) : + asm = build_asm(C_LWSP, CI_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ci.funct3 == FUNCT3_C_LI_LW)) : + asm = build_asm(C_LI, CI_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ci.rd_rs1.gpr != X2) + && (instr.compressed.format.ci.funct3 == FUNCT3_C_LUI)) : + asm = build_asm(C_LUI, CI_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ci.rd_rs1.gpr != X0) + && (instr.compressed.format.ci.funct3 == FUNCT3_C_ADDI_NOP)) : + asm = build_asm(C_ADDI, CI_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ci.rd_rs1.gpr == X2) + && (instr.compressed.format.ci.funct3 == FUNCT3_C_ADDI16SP)) : + asm = build_asm(C_ADDI16SP, CI_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.ci.funct3 == FUNCT3_C_SLLI)) : + asm = build_asm(C_SLLI, CI_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ci.rd_rs1.gpr == X0) + && (instr.compressed.format.ci.funct3 == FUNCT3_C_ADDI_NOP)) : + asm = build_asm(C_NOP, CI_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ca.funct2 == 2'b00) + && (instr.compressed.format.ca.funct6 == 6'b100011)) : + asm = build_asm(C_SUB, CA_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ca.funct2 == 2'b01) + && (instr.compressed.format.ca.funct6 == 6'b100011)) : + asm = build_asm(C_XOR, CA_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ca.funct2 == 2'b10) + && (instr.compressed.format.ca.funct6 == 6'b100011)) : + asm = build_asm(C_OR, CA_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ca.funct2 == 2'b11) + && (instr.compressed.format.ca.funct6 == 6'b100011)) : + asm = build_asm(C_AND, CA_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cb.offset_12_10[12] == 1'b0) + && (instr.compressed.format.cb.offset_12_10[11:10] == 2'b00) + && (instr.compressed.format.cb.funct3 == FUNCT3_C_SRLI_SRAI)) : + asm = build_asm(C_SRLI, CB_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cb.offset_12_10[12] == 1'b0) + && (instr.compressed.format.cb.offset_12_10[11:10] == 2'b01) + && (instr.compressed.format.cb.funct3 == FUNCT3_C_SRLI_SRAI)) : + asm = build_asm(C_SRAI, CB_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cb.funct3 == FUNCT3_C_BEQZ)) : + asm = build_asm(C_BEQZ, CB_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cb.funct3 == FUNCT3_C_BNEZ)) : + asm = build_asm(C_BNEZ, CB_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cb.offset_12_10[11:10] == 2'b10) + && (instr.compressed.format.cb.funct3 == FUNCT3_C_ANDI)) : + asm = build_asm(C_ANDI, CB_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.css.funct3 == FUNCT3_C_SWSP)) : + asm = build_asm(C_SWSP, CSS_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.ciw.imm != X0) + && (instr.compressed.format.ciw.funct3 == FUNCT3_C_ADDI4SPN)) : + asm = build_asm(C_ADDI4SPN, CIW_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.cl.funct3 == FUNCT3_C_LI_LW)) : + asm = build_asm(C_LW, CL_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.cs.funct3 == FUNCT3_C_SW)) : + asm = build_asm(C_SW, CS_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cj.funct3 == FUNCT3_C_J)) : + asm = build_asm(C_J, CJ_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cj.funct3 == FUNCT3_C_JAL)) : + asm = build_asm(C_JAL, CJ_TYPE, instr); + + //Zcb + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_ZEXT_B) + && (instr.compressed.format.cu.funct6 == 6'b100111)) : + asm = build_asm(C_ZEXT_B, CU_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_SEXT_B) + && (instr.compressed.format.cu.funct6 == 6'b100111)) : + asm = build_asm(C_SEXT_B, CU_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_ZEXT_H) + && (instr.compressed.format.cu.funct6 == 6'b100111)) : + asm = build_asm(C_ZEXT_H, CU_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_SEXT_H) + && (instr.compressed.format.cu.funct6 == 6'b100111)) : + asm = build_asm(C_SEXT_H, CU_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_NOT) + && (instr.compressed.format.cu.funct6 == 6'b100111)) : + asm = build_asm(C_NOT, CU_TYPE, instr); + + ( (instr.compressed.opcode == C1) + && (instr.compressed.format.ca.funct2 == 2'b10) + && (instr.compressed.format.ca.funct6 == 6'b100111)) : + asm = build_asm(C_MUL, CA_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.clb.funct6 == 6'b100000)) : + asm = build_asm(C_LBU, CLB_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.clh.funct1 == 1'b0) + && (instr.compressed.format.clh.funct6 == 6'b100001)) : + asm = build_asm(C_LHU, CLH_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.clh.funct1 == 1'b1) + && (instr.compressed.format.clh.funct6 == 6'b100001)) : + asm = build_asm(C_LH, CLH_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.csb.funct6 == 6'b100010)) : + asm = build_asm(C_SB, CSB_TYPE, instr); + + ( (instr.compressed.opcode == C0) + && (instr.compressed.format.csh.funct1 == 1'b0) + && (instr.compressed.format.csh.funct6 == 6'b100011)) : + asm = build_asm(C_SH, CSH_TYPE, instr); + + + //Zcmp + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmpp.funct2 == 2'b00) + && (instr.compressed.format.cmpp.funct6 == 6'b101110)) : + asm = build_asm(CM_PUSH, CMPP_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmpp.funct2 == 2'b10) + && (instr.compressed.format.cmpp.funct6 == 6'b101110)) : + asm = build_asm(CM_POP, CMPP_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmpp.funct2 == 2'b00) + && (instr.compressed.format.cmpp.funct6 == 6'b101111)) : + asm = build_asm(CM_POPRETZ, CMPP_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmpp.funct2 == 2'b10) + && (instr.compressed.format.cmpp.funct6 == 6'b101111)) : + asm = build_asm(CM_POPRET, CMPP_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmmv.funct2 == 2'b11) + && (instr.compressed.format.cmmv.funct6 == 6'b101011)) : + asm = build_asm(CM_MVA01S, CMMV_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmmv.funct2 == 2'b01) + && (instr.compressed.format.cmmv.funct6 == 6'b101011)) : + asm = build_asm(CM_MVSA01, CMMV_TYPE, instr); + + //Zcmt + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmjt.index < 32) + && (instr.compressed.format.cmjt.funct6 == 6'b101000)) : + asm = build_asm(CM_JT, CMJT_TYPE, instr); + + ( (instr.compressed.opcode == C2) + && (instr.compressed.format.cmjt.index >= 32) + && (instr.compressed.format.cmjt.funct6 == 6'b101000)) : + asm = build_asm(CM_JALT, CMJT_TYPE, instr); + + default: asm = build_asm(UNKNOWN_INSTR, UNKNOWN_FORMAT, instr_t'(32'h0)); + endcase + + return asm; + + endfunction : decode_instr + + // --------------------------------------------------------------------------- + // Identify if a given instruction matches an expected instruction name + // --------------------------------------------------------------------------- + function match_instr(instr_t instr, instr_name_e instr_type); + match_instr = (decode_instr(instr).instr == instr_type); + endfunction : match_instr + + +//endpackage + +`endif // __ISA_DECODER__ + diff --git a/lib/isa_decoder/isa_decoder_pkg.flist b/lib/isa_decoder/isa_decoder_pkg.flist new file mode 100644 index 0000000000..0e7d1c79c0 --- /dev/null +++ b/lib/isa_decoder/isa_decoder_pkg.flist @@ -0,0 +1,21 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +// Directories ++incdir+${DV_ISA_DECODER_PATH} + +// Files +${DV_ISA_DECODER_PATH}/isa_decoder_pkg.sv diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_tdefs.sv b/lib/isa_decoder/isa_decoder_pkg.sv similarity index 67% rename from cv32e40x/env/uvme/uvme_cv32e40x_tdefs.sv rename to lib/isa_decoder/isa_decoder_pkg.sv index 450b8272b7..935b7294f0 100644 --- a/cv32e40x/env/uvme/uvme_cv32e40x_tdefs.sv +++ b/lib/isa_decoder/isa_decoder_pkg.sv @@ -1,5 +1,4 @@ -// Copyright 2020 OpenHW Group -// Copyright 2020 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -14,17 +13,17 @@ // limitations under the License. // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// +`ifndef __ISA_DECODER_PKG__ +`define __ISA_DECODER_PKG__ -`ifndef __UVME_CV32E40X_TDEFS_SV__ -`define __UVME_CV32E40X_TDEFS_SV__ +package isa_decoder_pkg; + `include "isa_constants.sv" + `include "isa_typedefs_csr.sv" + `include "isa_typedefs.sv" + `include "isa_decoder.sv" +endpackage -typedef enum { - FETCH_CONSTANT, - FETCH_INITIAL_DELAY_CONSTANT, - FETCH_RANDOM_TOGGLE -} fetch_toggle_t; +`endif // __ISA_DECODER_PKG__ -`endif // __UVME_CV32E40X_TDEFS_SV__ diff --git a/lib/isa_decoder/isa_typedefs.sv b/lib/isa_decoder/isa_typedefs.sv new file mode 100644 index 0000000000..374985c103 --- /dev/null +++ b/lib/isa_decoder/isa_typedefs.sv @@ -0,0 +1,957 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// ------------------------------------------------------------------- +// This file holds typedefs related to the ISA decoder +// ------------------------------------------------------------------- + +`ifndef __ISA_TYPEDEFS__ +`define __ISA_TYPEDEFS__ + + + // --------------------------------------------------------------------------- + // Instruction names, add instructions as needed + // --------------------------------------------------------------------------- + typedef enum { + // Unknown for instructions that cannot be decoded + UNKNOWN_INSTR = 0, + FENCE, + FENCE_I, + MRET, + DRET, + ECALL, + EBREAK, + WFI, + WFE, + CSRRW, + CSRRS, + CSRRC, + CSRRWI, + CSRRSI, + CSRRCI, + // RV32I + LUI, + AUIPC, + JAL, + JALR, + BEQ, + BNE, + BLT, + BGE, + BLTU, + BGEU, + SB, + SH, + SW, + LB, + LH, + LW, + LBU, + LHU, + ADDI, + SLTI, + SLTIU, + XORI, + ORI, + ANDI, + SLLI, + SRLI, + SRAI, + ADD, + SUB, + SLL, + SLT, + SLTU, + XOR, + SRL, + SRA, + OR, + AND, + //A + LR_W, + SC_W, + AMOSWAP_W, + AMOADD_W, + AMOXOR_W, + AMOAND_W, + AMOOR_W, + AMOMIN_W, + AMOMAX_W, + AMOMINU_W, + AMOMAXU_W, + //Zba + SH1ADD, + SH2ADD, + SH3ADD, + //Zbb + MIN, + MINU, + MAX, + MAXU, + CPOP, + CTZ, + ORC_B, + ORN, + CLZ, + ANDN, + ROL, + ROR, + RORI, + XNOR, + REV8, + SEXT_B, + SEXT_H, + ZEXT_H, + //Zbc + CLMUL, + CLMULH, + CLMULR, + //Zbs + BCLR, + BCLRI, + BEXT, + BEXTI, + BINV, + BINVI, + BSET, + BSETI, + //M + MUL, + MULH, + MULHSU, + MULHU, + DIV, + DIVU, + REM, + REMU, + // Compressed + ILLEGAL_INSTR, + //Zca + C_LWSP, + C_SWSP, + C_LW, + C_SW, + C_EBREAK, + C_MV, + C_ADD, + C_LI, + C_LUI, + C_JR, + C_JALR, + C_J, + C_JAL, + C_ANDI, + C_AND, + C_OR, + C_XOR, + C_SUB, + C_NOP, + C_ADDI4SPN, + C_ADDI16SP, + C_ADDI, + C_SLLI, + C_SRLI, + C_SRAI, + C_BEQZ, + C_BNEZ, + //Zcb + C_LBU, + C_LHU, + C_LH, + C_SB, + C_SH, + C_ZEXT_B, + C_SEXT_B, + C_ZEXT_H, + C_SEXT_H, + C_NOT, + C_MUL, + //Zcmp + CM_PUSH, + CM_POP, + CM_POPRET, + CM_POPRETZ, + CM_MVA01S, + CM_MVSA01, + //Zcmt + CM_JT, + CM_JALT, + //Hints + HINT_C_LI, + HINT_C_LUI, + HINT_C_NOP, + HINT_C_ADDI, + HINT_C_MV, + HINT_C_ADD, + // Pseudo name, class of instructions + STORE_INSTR, + LOAD_INSTR + + } instr_name_e; + + // --------------------------------------------------------------------------- + // GPR Registers + // --------------------------------------------------------------------------- + typedef enum logic [4:0] { + X0 = 5'd0, + X1 = 5'd1, + X2 = 5'd2, + X3 = 5'd3, + X4 = 5'd4, + X5 = 5'd5, + X6 = 5'd6, + X7 = 5'd7, + X8 = 5'd8, + X9 = 5'd9, + X10 = 5'd10, + X11 = 5'd11, + X12 = 5'd12, + X13 = 5'd13, + X14 = 5'd14, + X15 = 5'd15, + X16 = 5'd16, + X17 = 5'd17, + X18 = 5'd18, + X19 = 5'd19, + X20 = 5'd20, + X21 = 5'd21, + X22 = 5'd22, + X23 = 5'd23, + X24 = 5'd24, + X25 = 5'd25, + X26 = 5'd26, + X27 = 5'd27, + X28 = 5'd28, + X29 = 5'd29, + X30 = 5'd30, + X31 = 5'd31 + } gpr_name_e; + + typedef enum logic [4:0] { + ZERO = 5'd0, + RA = 5'd1, + SP = 5'd2, + GP = 5'd3, + TP = 5'd4, + T0 = 5'd5, + T1 = 5'd6, + T2 = 5'd7, + S0 = 5'd8, + S1 = 5'd9, + A0 = 5'd10, + A1 = 5'd11, + A2 = 5'd12, + A3 = 5'd13, + A4 = 5'd14, + A5 = 5'd15, + A6 = 5'd16, + A7 = 5'd17, + S2 = 5'd18, + S3 = 5'd19, + S4 = 5'd20, + S5 = 5'd21, + S6 = 5'd22, + S7 = 5'd23, + S8 = 5'd24, + S9 = 5'd25, + S10 = 5'd26, + S11 = 5'd27, + T3 = 5'd28, + T4 = 5'd29, + T5 = 5'd30, + T6 = 5'd31 + } gpr_abi_name_e; + + typedef enum logic [2:0] { + C_X8 = 3'b000, + C_X9 = 3'b001, + C_X10 = 3'b010, + C_X11 = 3'b011, + C_X12 = 3'b100, + C_X13 = 3'b101, + C_X14 = 3'b110, + C_X15 = 3'b111 + } gpr_rvc_name_e; + + typedef enum logic [2:0] { + C_S0 = 3'b000, + C_S1 = 3'b001, + C_A0 = 3'b010, + C_A1 = 3'b011, + C_A2 = 3'b100, + C_A3 = 3'b101, + C_A4 = 3'b110, + C_A5 = 3'b111 + } gpr_rvc_abi_name_e; + + typedef union packed { + bit [2:0] raw; + gpr_rvc_name_e gpr; + gpr_rvc_abi_name_e gpr_abi; + } gpr_rvc_t; + + typedef union packed { + bit [4:0] raw; + gpr_name_e gpr; + gpr_abi_name_e gpr_abi; + } gpr_t; + + // --------------------------------------------------------------------------- + // Rlist for zcmp instructions + // --------------------------------------------------------------------------- + typedef enum logic [3:0] { + X1__ = 4'd4, + X1__X8 = 4'd5, + X1__X8_X9 = 4'd6, + X1__X8_X9__X18 = 4'd7, + X1__X8_X9__X18_X19 = 4'd8, + X1__X8_X9__X18_X20 = 4'd9, + X1__X8_X9__X18_X21 = 4'd10, + X1__X8_X9__X18_X22 = 4'd11, + X1__X8_X9__X18_X23 = 4'd12, + X1__X8_X9__X18_X24 = 4'd13, + X1__X8_X9__X18_X25 = 4'd14, + X1__X8_X9__X18_X27 = 4'd15 + } rlist_name_e; + + typedef enum logic [3:0] { + RA__ = 4'd4, + RA__S0 = 4'd5, + RA__S0_S1 = 4'd6, + RA__S0_S2 = 4'd7, + RA__S0_S3 = 4'd8, + RA__S0_S4 = 4'd9, + RA__S0_S5 = 4'd10, + RA__S0_S6 = 4'd11, + RA__S0_S7 = 4'd12, + RA__S0_S8 = 4'd13, + RA__S0_S9 = 4'd14, + RA__S0_S11 = 4'd15 + } rlist_abi_name_e; + + typedef union packed { + bit [3:0] raw; + rlist_name_e rlist; + rlist_abi_name_e rlist_abi; + } rlist_t; + + // ------------------------------------------------------------------- + // Function types + // ------------------------------------------------------------------- + + // Major opcodes + typedef enum logic [6:0] { + LOAD = 7'b000_0011, LOAD_FP = 7'b000_0111, CUS_0 = 7'b000_1011, MISC_MEM = 7'b000_1111, OP_IMM = 7'b001_0011, AUIPC_OP = 7'b001_0111,OP_IMM_32 = 7'b001_1011, + STORE = 7'b010_0011, STORE_FP = 7'b010_0111, CUS_1 = 7'b010_1011, AMO = 7'b010_1111, OP = 7'b011_0011, LUI_OP = 7'b011_0111,OP_32 = 7'b011_1011, + MADD = 7'b100_0011, MSUB = 7'b100_0111, NMSUB = 7'b100_1011, NMADD = 7'b100_1111, OP_FP = 7'b101_0011, RES_1 = 7'b101_0111,CUS_2 = 7'b101_1011, + BRANCH = 7'b110_0011, JALR_OP = 7'b110_0111, RES_0 = 7'b110_1011, JAL_OP = 7'b110_1111, SYSTEM = 7'b111_0011, RES_2 = 7'b111_0111,CUS_3 = 7'b111_1011 + } major_opcode_e; + + + // TODO opcode map for rv32c - problem here is that it is multi-field dependent. + typedef enum logic [1:0] { + C0 = 2'b00, C1 = 2'b01, C2 = 2'b10, C3 = 2'b11 /* C3 does not exist, is uncompressed */ + } compressed_major_opcode_e; + + + // Minor opcodes + typedef enum logic [2:0] { + FUNCT3_CSRRW = 3'b001, + FUNCT3_CSRRS = 3'b010, + FUNCT3_CSRRC = 3'b011, + FUNCT3_CSRRWI = 3'b101, + FUNCT3_CSRRSI = 3'b110, + FUNCT3_CSRRCI = 3'b111 + } csr_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_LB = 3'b000, + FUNCT3_LH = 3'b001, + FUNCT3_LW = 3'b010, + FUNCT3_LBU = 3'b100, + FUNCT3_LHU = 3'b101 + } load_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_SB = 3'b000, + FUNCT3_SH = 3'b001, + FUNCT3_SW = 3'b010 + } store_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_BEQ = 3'b000, + FUNCT3_BNE = 3'b001, + FUNCT3_BLT = 3'b100, + FUNCT3_BGE = 3'b101, + FUNCT3_BLTU = 3'b110, + FUNCT3_BGEU = 3'b111 + } branch_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_ADDI = 3'b000, + FUNCT3_SLTI = 3'b010, + FUNCT3_SLTIU = 3'b011, + FUNCT3_XORI = 3'b100, + FUNCT3_ORI = 3'b110, + FUNCT3_ANDI = 3'b111, + FUNCT3_SLLI = 3'b001, + FUNCT3_SRLI_SRAI = 3'b101 + } op_imm_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_ADD_SUB = 3'b000, + FUNCT3_SLL = 3'b001, + FUNCT3_SLT = 3'b010, + FUNCT3_SLTU = 3'b011, + FUNCT3_XOR = 3'b100, + FUNCT3_SRL_SRA = 3'b101, + FUNCT3_OR = 3'b110, + FUNCT3_AND = 3'b111 + } op_minor_opcode_e; + + // Minor opcodes for Zba + typedef enum logic [2:0] { + FUNCT3_SH2ADD = 3'b100, + FUNCT3_SH3ADD = 3'b110, + FUNCT3_SH1ADD = 3'b010 + } zba_minor_opcode_e; + + // Minor opcodes for Zbb + // Minor opcodes for min and max instructions + typedef enum logic [2:0] { + FUNCT3_MIN = 3'b100, + FUNCT3_MINU = 3'b101, + FUNCT3_MAX = 3'b110, + FUNCT3_MAXU = 3'b111 + } zbb_min_max_minor_opcode_e; + + // Minor opcodes for logical operators and sign extend (FUNCT3_SEXT) + typedef enum logic [2:0] { + FUNCT3_XNOR = 3'b100, + FUNCT3_ORC_B = 3'b101, + FUNCT3_ORN = 3'b110, + FUNCT3_ANDN = 3'b111, + FUNCT3_SEXT = 3'b001 + } zbb_logical_minor_opcode_e; + + // Minor opcodes for rotate instructions + typedef enum logic [2:0] { + FUNCT3_ROR_RORI = 3'b101, + FUNCT3_ROL = 3'b001 + } zbb_rotate_minor_opcode_e; + + // Minor opcodes for byte reverse register (FUNCT3_REV8), count instructions (FUNCT3_C) + // and zero extend halfword instruction (FUNCT3_ZEXTH). + // FUNCT3_C is correct for all count isntructions. + typedef enum logic [2:0] { + FUNCT3_REV8 = 3'b101, + FUNCT3_C = 3'b001, + FUNCT3_ZEXT_H = 3'b100 + } zbb_rev8_c_zexth_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_C_SRLI_SRAI = 3'b100, + FUNCT3_C_SLLI = 3'b000, + FUNCT3_C_SW = 3'b110 + } compressed_shift_store_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_C_BEQZ = 3'b110, + FUNCT3_C_BNEZ = 3'b111, + FUNCT3_C_J = 3'b101, + FUNCT3_C_JAL = 3'b001 + } compressed_branch_jump_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_C_LI_LW = 3'b010, + FUNCT3_C_LUI = 3'b011 + } compressed_load_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_C_LWSP = 3'b010, + FUNCT3_C_SWSP = 3'b110, + FUNCT3_C_ADDI4SPN = 3'b000, + FUNCT3_C_ADDI16SP = 3'b011 + } compressed_sp_minor_opcode_e; + + typedef enum logic [2:0] { + FUNCT3_C_ANDI = 3'b100, + FUNCT3_C_ADDI_NOP = 3'b000 + } compressed_minor_opcode_e; + + // Minor opcodes for Zbc + typedef enum logic [2:0] { + FUNCT3_CLMUL = 3'b001, + FUNCT3_CLMULR = 3'b010, + FUNCT3_CLMULH = 3'b011 + } zbc_minor_opcode_e; + + // Minor opcodes for Zbs + // FUNCT3_B_BI corresponds to all single-Bit instructions other than BEXT and BEXTI. + typedef enum logic [2:0] { + FUNCT3_BEXT_BEXTI = 3'b101, + FUNCT3_B_BI = 3'b001 + } zbs_single_bit_minor_opcode_e; + + // Minor opcodes for multiplication and division, "M". + typedef enum logic [2:0] { + FUNCT3_MUL = 3'b000, + FUNCT3_MULH = 3'b001, + FUNCT3_MULHSU = 3'b010, + FUNCT3_MULHU = 3'b011, + FUNCT3_DIV = 3'b100, + FUNCT3_DIVU = 3'b101, + FUNCT3_REM = 3'b110, + FUNCT3_REMU = 3'b111 + } m_minor_opcode_e; + + // Minor opcode for atomic instructions, "A". + typedef enum logic [2:0] { + FUNCT3_A_W = 3'b010, + FUNCT3_A_D = 3'b011 + } a_minor_opcode_e; + + typedef enum logic [4:0] { + FUNCT5_C_SEXT_B = 5'b11001, + FUNCT5_C_ZEXT_B = 5'b11000, + FUNCT5_C_ZEXT_H = 5'b11010, + FUNCT5_C_SEXT_H = 5'b11011, + FUNCT5_C_NOT = 5'b11101 + } funct5_compressed_e; + + typedef enum logic [4:0] { + FUNCT5_LR_W = 5'b00010, + FUNCT5_SC_W = 5'b00011, + FUNCT5_AMOSWAP_W = 5'b00001, + FUNCT5_AMOADD_W = 5'b00000, + FUNCT5_AMOXOR_W = 5'b00100, + FUNCT5_AMOAND_W = 5'b01100, + FUNCT5_AMOOR_W = 5'b01000, + FUNCT5_AMOMIN_W = 5'b10000, + FUNCT5_AMOMAX_W = 5'b10100, + FUNCT5_AMOMINU_W = 5'b11000, + FUNCT5_AMOMAXU_W = 5'b11100 + } funct5_atomic_e; + + + // Funct7 + typedef enum logic [6:0] { + FUNCT7_ZBB_MIN_MAX = 7'b000_0101, + FUNCT7_ZBB_LOGICAL = 7'b010_0000, + FUNCT7_ZBB_ROTATE = 7'b011_0000, + FUNCT7_ZBS_BCLR_BEXT = 7'b010_0100, + FUNCT7_ZBS_BINV = 7'b011_0100, + FUNCT7_ZBS_BSET = 7'b001_0100 + } zbb_zbs_funct7_e; + + typedef enum logic [6:0] { + FUNCT7_ZBA = 7'b001_0000, + FUNCT7_ZBC = 7'b000_0101, + FUNCT7_M = 7'b000_0001 + } zba_zbc_m_funct7_e; + + // U type + typedef struct packed { + logic [31:12] imm; + gpr_t rd; + } u_type_t; + + // J type + typedef struct packed { + logic [31:12] imm; + gpr_t rd; + } j_type_t; + + typedef struct packed { + logic [31:25] funct7; + gpr_t rs2; + } r_funct12_t; + + // R type + typedef struct packed { + logic [31:25] funct7; + gpr_t rs2; + gpr_t rs1; + logic [14:12] funct3; + gpr_t rd; + } r_type_t; + + // R4 type + typedef struct packed { + gpr_t rs3; + logic [26:25] funct2; + gpr_t rs2; + gpr_t rs1; + logic [14:12] funct3; + gpr_t rd; + } r4_type_t; + + typedef struct packed { + logic [31:25] funct7; + logic [24:20] shamt; + } i_imm_t; + + // I type + typedef struct packed { + i_imm_t imm; + gpr_t rs1; + logic [14:12] funct3; + gpr_t rd; + } i_type_t; + + // I type (Load) + typedef struct packed { + i_imm_t imm; + gpr_t rs1; + load_minor_opcode_e funct3; + gpr_t rd; + } i_type_load_t; + + // B type + typedef struct packed { + logic [31:25] imm_h; + gpr_t rs2; + gpr_t rs1; + logic [14:12] funct3; + logic [11:7] imm_l; + } b_type_t; + + // S type + typedef struct packed { + logic [31:25] imm_h; + gpr_t rs2; + gpr_t rs1; + store_minor_opcode_e funct3; + logic [11:7] imm_l; + } s_type_t; + + // Generic + typedef struct packed { + union packed { + logic [31:7] raw; + i_type_t i; + i_type_load_t i_load; + j_type_t j; + s_type_t s; + r_type_t r; + r4_type_t r4; + b_type_t b; + u_type_t u; + } format; // Would like to use type, but type is reserved keyword in sv + major_opcode_e opcode; + } uncompressed_instr_t; + + typedef struct packed { + logic[15:12] funct4; + gpr_t rd_rs1; + gpr_t rs2; + } cr_type_t; + + typedef struct packed { + logic[15:13] funct3; + logic[12:12] imm_12; + gpr_t rd_rs1; + logic[6:2] imm_6_2; + } ci_type_t; + + typedef struct packed { + logic[15:13] funct3; + logic[12:7] imm; + gpr_t rs2; + } css_type_t; + + typedef struct packed { + logic[15:13] funct3; + logic[12:5] imm; + gpr_rvc_t rd; + } ciw_type_t; + + typedef struct packed { + logic[15:13] funct3; + logic[12:10] imm_12_10; + gpr_rvc_t rs1; + logic[6:5] imm_6_5; + gpr_rvc_t rd; + } cl_type_t; + + typedef struct packed { + logic[15:13] funct3; + logic[12:10] imm_12_10; + gpr_rvc_t rs1; + logic[6:5] imm_6_5; + gpr_rvc_t rs2; + } cs_type_t; + + typedef struct packed { + logic[15:10] funct6; + gpr_rvc_t rd_rs1; + logic[6:5] funct2; + gpr_rvc_t rs2; + } ca_type_t; + + typedef struct packed { + logic[15:13] funct3; + logic[12:10] offset_12_10; + gpr_rvc_t rd_rs1; + logic[6:2] offset_6_2; + } cb_type_t; + + typedef struct packed { + logic[15:13] funct3; + logic[12:2] imm; + } cj_type_t; + + typedef struct packed { + logic[15:10] funct6; + gpr_rvc_t rs1; + logic[6:5] uimm; + gpr_rvc_t rd; + } clb_type_t; + + typedef struct packed { + logic[15:10] funct6; + gpr_rvc_t rs1; + logic[6:5] uimm; + gpr_rvc_t rs2; + } csb_type_t; + + typedef struct packed { + logic[15:10] funct6; + gpr_rvc_t rs1; + logic funct1; + logic uimm; + gpr_rvc_t rd; + } clh_type_t; + + typedef struct packed { + logic[15:10] funct6; + gpr_rvc_t rs1; + logic funct1; + logic uimm; + gpr_rvc_t rs2; + } csh_type_t; + + typedef struct packed { + logic[15:10] funct6; + gpr_rvc_t rd_rs1; + logic[6:2] funct5; + } cu_type_t; + + typedef struct packed { + logic[15:10] funct6; + gpr_rvc_t r1s; + logic[6:5] funct2; + gpr_rvc_t r2s; + } cmmv_type_t; + + typedef struct packed { + logic[15:10] funct6; + logic[9:2] index; + } cmjt_type_t; + + typedef struct packed { + logic[15:10] funct6; + logic[9:8] funct2; + rlist_t urlist; + logic[5:4] spimm; + } cmpp_type_t; + + // Compressed instruction types + typedef struct packed { + logic [31:16] reserved_31_16; + union packed { + logic [15:2] raw; + cr_type_t cr; + ci_type_t ci; + css_type_t css; + ciw_type_t ciw; + cl_type_t cl; + cs_type_t cs; + ca_type_t ca; + cb_type_t cb; + cj_type_t cj; + clb_type_t clb; + csb_type_t csb; + clh_type_t clh; + csh_type_t csh; + cu_type_t cu; + cmmv_type_t cmmv; + cmjt_type_t cmjt; + cmpp_type_t cmpp; + } format; + compressed_major_opcode_e opcode; + } compressed_instr_t; + + typedef union packed { + compressed_instr_t compressed; + uncompressed_instr_t uncompressed; + } instr_t; + + // --------------------------------------------------------------------------- + // Datatypes used for disassembled instructions, fields that are not + // applicable to all instructions are qualified with a valid bit in the + // respective structure. + // --------------------------------------------------------------------------- + + + // --------------------------------------------------------------------------- + // gpr structure, can represent raw value, enumerated non-abi machine register + // and enumerated abi register names + // --------------------------------------------------------------------------- + typedef struct packed { + gpr_t gpr; + gpr_rvc_t gpr_rvc; + bit valid; + bit valid_gpr_rvc; + } reg_operand_t; + + // --------------------------------------------------------------------------- + // Datatype to represent disassemblede immediate + // + // TODO: defer until needed + // * Add non-interpreted sorted bitfields for immediates + // * Add width-fields and associated logic for setting immediate + // and non-interpreted immediate bitfield widths + // * Add type/sign-extension fields and associated logic + // --------------------------------------------------------------------------- + + //Immediate types + typedef enum { + IMM, + NZIMM, + NZUIMM, + OFFSET, + I_IMM, + U_IMM, + SHAMT, + UIMM, + SPIMM, + INDEX + } imm_e; + + typedef struct packed { + int imm_value; + bit[31:0] imm_raw; // The immediate in the order it is presented in the instruction without shifting. + bit[31:0] imm_raw_sorted; // The immediate sorted in the correct order. No shifitng. + imm_e imm_type; // States the type of the immediate + int width; // Number of bits in immediate + bit sign_ext; // Indicates whether the immediate is sign-extended or not. + bit valid; + } imm_operand_t; + + typedef struct packed { + union packed { + csr_name_e name; + } address; + bit valid; + } csr_operand_t; + // --------------------------------------------------------------------------- + // Currently not used, can be used as an intermediate representation for + // an register + offset field in assembly + // --------------------------------------------------------------------------- + typedef struct packed { + int offset; + gpr_t gpr; + bit valid; + } mem_operand_t; + + // rlist operand for Zcmp instructions + typedef struct packed { + rlist_t rlist; + bit valid; + } rlist_operand_t; + + // stack_adj operand for Zcmp instructions + typedef struct packed { + int stack_adj; + bit valid; + } stack_adj_operand_t; + + // Atomic operand to specify additional memory ordering constraints for atomic instructions + typedef struct packed { + bit aq; + bit rl; + bit valid; + } atomic_operand_t; + // --------------------------------------------------------------------------- + // Instruction formats + // --------------------------------------------------------------------------- + typedef enum logic[7:0] { + // Others + UNKNOWN_FORMAT = 0, + I_TYPE, + J_TYPE, + S_TYPE, + R_TYPE, + R4_TYPE, + B_TYPE, + U_TYPE, + // Compressed formats + CR_TYPE, + CI_TYPE, + CSS_TYPE, + CIW_TYPE, + CL_TYPE, + CS_TYPE, + CA_TYPE, + CB_TYPE, + CJ_TYPE, + CLB_TYPE, + CSB_TYPE, + CLH_TYPE, + CSH_TYPE, + CU_TYPE, + CMMV_TYPE, + CMJT_TYPE, + CMPP_TYPE + } instr_format_e; + + // --------------------------------------------------------------------------- + // Main _decoded_ and _disassembled_ data structure + // --------------------------------------------------------------------------- + typedef struct packed { + instr_name_e instr; // Instruction name + instr_format_e format; // Instruction format type + reg_operand_t rd; // Destination register, qualified by rd.valid + reg_operand_t rs1; // source register 1, qualified by rs1.valid + reg_operand_t rs2; // -- 2, -- 2 + reg_operand_t rs3; // -- 3, -- 3 + imm_operand_t imm; // Immediate, qualified by imm.valid + csr_operand_t csr; // CSR register address, qualified by csr.valid + logic is_hint; // Indicates whether the current instruction is a HINT. + rlist_operand_t rlist; // structure to handle rlist fields for Zcmp-instructions + stack_adj_operand_t stack_adj; // structure to handle stack_adj fields for Zcmp-instructions + atomic_operand_t atomic; + } asm_t; + + // --------------------------------------------------------------------------- + // HINT + // --------------------------------------------------------------------------- + typedef enum logic[7:0] { + ADDI_H, + FENCE_H, + C_NOP_H, + C_ADDI_H, + C_LI_H, + REG_IMM_I_H, + REG_IMM_U_H, + REG_REG_R_H, + REG_REG_CR_H, + CONST_GEN_CI_H, + // Others + UNKNOWN_HINT + } hint_name_e; + + +`endif // __ISA_TYPEDEFS__ diff --git a/lib/isa_decoder/isa_typedefs_csr.sv b/lib/isa_decoder/isa_typedefs_csr.sv new file mode 100644 index 0000000000..99d7d09339 --- /dev/null +++ b/lib/isa_decoder/isa_typedefs_csr.sv @@ -0,0 +1,159 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// ------------------------------------------------------------------- +// This file holds typedefs related to the CSRs in the ISA decoder. +// ------------------------------------------------------------------- + +`ifndef __ISA_TYPEDEFS_CSR__ +`define __ISA_TYPEDEFS_CSR__ + + // ------------------------------------------------------------------- + // CSR Addresses + // ------------------------------------------------------------------- + + + + // TODO: expand + typedef enum logic [31:20] { + MSTATUS = 12'h300, + MISA = 12'h301, + MIE = 12'h304, + MTVEC = 12'h305, + MTVT = 12'h307, + MSTATUSH = 12'h310, + MCOUNTINHIBIT = 12'h320, + MHPMEVENT3 = 12'h323, + MHPMEVENT31 = 12'h33F, + MSCRATCH = 12'h340, + MEPC = 12'h341, + MCAUSE = 12'h342, + MTVAL = 12'h343, + MIP = 12'h344, + MNXTI = 12'h345, + MINTSTATUS = 12'h346, + MINTTHRESH = 12'h347, + MSCRATCHCSW = 12'h348, + MSCRATCHCSWL = 12'h349, + MCLICBASE = 12'h34A, + TSELECT = 12'h7A0, + TDATA1 = 12'h7A1, + TDATA2 = 12'h7A2, + TDATA3 = 12'h7A3, + TINFO = 12'h7A4, + TCONTROL = 12'h7A5, + DCSR = 12'h7B0, + DPC = 12'h7B1, + DSCRATCH0 = 12'h7B2, + DSCRATCH1 = 12'h7B3, + CPUCTRL = 12'hBF0, + SECURESEED0 = 12'hBF9, + SECURESEED1 = 12'hBFA, + SECURESEED2 = 12'hBFC + } csr_name_e; + + // ------------------------------------------------------------------- + // CSR Types - TODO replace with include when autogen in place + // ------------------------------------------------------------------- + typedef struct packed { + logic [31:24] mil; + logic [23:16] reserved; + logic [15:8] sil; + logic [7:0] uil; + } mintstatus_t; + + typedef struct packed { + logic [31:8] reserved_0; + logic [7:0] th; + } mintthresh_t; + + typedef struct packed { + logic [31:31] sd; + logic [30:23] reserved_3; + logic [22:22] tsr; + logic [21:21] tw; + logic [20:20] tvm; + logic [19:19] mxr; + logic [18:18] sum; + logic [17:17] mprv; + logic [16:15] xs; + logic [14:13] fs; + logic [12:11] mpp; + logic [10:9] vs; + logic [8:8] spp; + logic [7:7] mpie; + logic [6:6] ube; + logic [5:5] spie; + logic [4:4] reserved_2; + logic [3:3] mie; + logic [2:2] reserved_1; + logic [1:1] sie; + logic [0:0] reserved_0; + } mstatus_t; + + // TODO non-clic union + typedef struct packed { + logic [31:7] base_31_7; + logic [6:2] base_6_2; + logic [1:0] mode; + } mtvec_clic_t; + + // TODO CLIC_ID_WIDTH readable? + localparam N_MTVT = 2+CLIC_ID_WIDTH > 6 ? 2+CLIC_ID_WIDTH : 6; + + typedef struct packed { + logic [31:N_MTVT] base_31_n; + logic [N_MTVT-1:6] base_n_6; + logic [5:0] reserved; + } mtvt_t; + + typedef struct packed { + logic [31:1] m_exception_pc; + logic [0:0] reserved; + } mepc_t; + + // TODO exccode_t core specific? + typedef struct packed { + logic [31:31] interrupt; + logic [30:30] minhv; + logic [29:28] mpp; + logic [27:27] mpie; + logic [26:24] reserved_1; + logic [23:16] mpil; + logic [15:12] reserved_0; + logic [11:0] exccode; // TODO typedef - core specific how to handle properly? + } mcause_t; + + typedef struct packed { + logic [31:28] debugver; + logic [27:18] reserved_27_18; + logic [17:17] ebreakvs; + logic [16:16] ebreakvu; + logic [15:15] ebreakm; + logic [14:14] reserved_14; + logic [13:13] ebreaks; + logic [12:12] ebreaku; + logic [11:11] stepie; + logic [10:10] stopcount; + logic [9:9] stoptime; + logic [8:6] cause; + logic [5:5] v; + logic [4:4] mprven; + logic [3:3] nmip; + logic [2:2] step; + logic [1:0] prv; + } dcsr_t; + + +`endif // __ISA_TYPEDEFS_CSR__ diff --git a/lib/mem_region_gen/pma_adapted_mem_region_gen.sv b/lib/mem_region_gen/pma_adapted_mem_region_gen.sv index 99f5eab5eb..b12b8773b2 100644 --- a/lib/mem_region_gen/pma_adapted_mem_region_gen.sv +++ b/lib/mem_region_gen/pma_adapted_mem_region_gen.sv @@ -21,7 +21,7 @@ class pma_adapted_memory_regions_c; typedef enum { S_INIT, S_CHK_DONE, S_DONE, S_POP, S_CLASSIFY, S_CLASSIFY_DONE, S_INSERT, S_SPLIT_REGION, S_ADJUST_LOWER_BOUND, S_ADJUST_UPPER_BOUND, S_PUSH } fsm_state_e; typedef struct { - pma_region_t cfg; + pma_cfg_t cfg; int prio; region_status_e flag; } classified_region_t; @@ -65,12 +65,12 @@ class pma_adapted_memory_regions_c; /* * Function: new * - * Inputs: pma_region_t pma_region[] - true pma configuration of the core + * Inputs: pma_cfg_t pma_region[] - true pma configuration of the core * * Init function ,adds initial regions to the stack, classifies them as UNCHECKED * and initializes FSM */ - function new(pma_region_t pma_region[]); + function new(pma_cfg_t pma_region[]); for (int i = pma_region.size() - 1; i >= 0; i--) begin // Skip zero-length regions if (pma_region[i].word_addr_low < pma_region[i].word_addr_high) begin @@ -160,12 +160,12 @@ class pma_adapted_memory_regions_c; /* * Function: add_region * - * Inputs: pma_region_t pma_region - Region to compute real bounds and insert into modified pma config stack + * Inputs: pma_cfg_t pma_region - Region to compute real bounds and insert into modified pma config stack * int pma_prio - Priority of sampled PMA region (index in original array) * region_status_e stack_flag - Region status flag * */ - protected virtual function void add_region(pma_region_t pma_region, int pma_prio, region_status_e stack_flag); + protected virtual function void add_region(pma_cfg_t pma_region, int pma_prio, region_status_e stack_flag); pma_region.word_addr_high -= 1; stack.push_back('{cfg: pma_region, flag: stack_flag, prio: pma_prio}); endfunction : add_region @@ -434,7 +434,7 @@ class pma_adapted_memory_regions_c; // In lieu of creating a typed queue to restrict size of process_stack, do a check on max size here to ensure the queue // does not grow beyond expected bounds if (process_stack.size() > MAX_PROCESS_STACK_SIZE) begin - `uvm_fatal("PMAPROCSTACK", $sformatf("process_stack size of %0d is greater than maximum allowed: %0s", process_stack.size(), MAX_PROCESS_STACK_SIZE)); + display_fatal($sformatf("process_stack size of %0d is greater than maximum allowed: %0s", process_stack.size(), MAX_PROCESS_STACK_SIZE)); end fsm_state_transitions; diff --git a/lib/support/support_constants.sv b/lib/support/support_constants.sv new file mode 100644 index 0000000000..1df9f880bd --- /dev/null +++ b/lib/support/support_constants.sv @@ -0,0 +1,26 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// ------------------------------------------------------------------- +// This file holds constants for the support logic +// ------------------------------------------------------------------- + +`ifndef __SUPPORT_CONSTANTS__ +`define __SUPPORT_CONSTANTS__ + + + parameter DEFAULT_XLEN = 32; + + +`endif // __SUPPORT_CONSTANTS__ diff --git a/lib/support/support_pkg.flist b/lib/support/support_pkg.flist new file mode 100644 index 0000000000..1a74e4090b --- /dev/null +++ b/lib/support/support_pkg.flist @@ -0,0 +1,21 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +// Directories ++incdir+${DV_SUPPORT_PATH} + +// Files +${DV_SUPPORT_PATH}/support_pkg.sv diff --git a/lib/support/support_pkg.sv b/lib/support/support_pkg.sv new file mode 100644 index 0000000000..5edcb02792 --- /dev/null +++ b/lib/support/support_pkg.sv @@ -0,0 +1,28 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +`ifndef __SUPPORT_PKG__ +`define __SUPPORT_PKG__ + + +package support_pkg; + import isa_decoder_pkg::*; + `include "support_constants.sv" + `include "support_utility.sv" +endpackage + +`endif // __SUPPORT_PKG__ + diff --git a/lib/support/support_utility.sv b/lib/support/support_utility.sv new file mode 100644 index 0000000000..8504795a0a --- /dev/null +++ b/lib/support/support_utility.sv @@ -0,0 +1,68 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// ------------------------------------------------------------------- +// This file holds utilities (functions and signals) for the support logic +// ------------------------------------------------------------------- + +`ifndef __SUPPORT_UTILITY__ +`define __SUPPORT_UTILITY__ + + + // ------------------------------------------------------------------- + // Functions + // ------------------------------------------------------------------- + + function automatic logic is_csr_read_spec_f(asm_t asm); + if (asm.instr inside { CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI }) begin + case (asm.instr) + CSRRW, CSRRWI : is_csr_read_spec_f = asm.rd.gpr ? 1'b1 : 1'b0; + CSRRS, CSRRC : is_csr_read_spec_f = 1'b1; + CSRRSI, CSRRCI: is_csr_read_spec_f = 1'b1; + // Should never be here + default : is_csr_read_spec_f = 1'b0; + endcase + end else begin + is_csr_read_spec_f = 1'b0; + end + endfunction : is_csr_read_spec_f + + function logic is_csr_write_spec_f(asm_t asm); + if (asm.instr inside { CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI }) begin + case (asm.instr) + CSRRW, CSRRWI : is_csr_write_spec_f = 1'b1; + CSRRS, CSRRC : is_csr_write_spec_f = asm.rs1.gpr ? 1'b1 : 1'b0; + CSRRSI, CSRRCI: is_csr_write_spec_f = asm.imm.imm_value ? 1'b1 : 1'b0; + // Should never be here + default : is_csr_write_spec_f = 1'b0; + endcase + end else begin + is_csr_write_spec_f = 1'b0; + end + endfunction : is_csr_write_spec_f + + // Short functions for recognising special functions + + function automatic logic[31:0] get_jvt_addr_f( + logic [DEFAULT_XLEN-1:0] instr, + logic [31:0] jvt + ); + logic [ 9:2] field_index = instr[9:2]; + logic [31:6] field_base = jvt[31:6]; + + return ({field_base, 6'd 0} + (field_index << 2)); + endfunction : get_jvt_addr_f + + +`endif // __SUPPORT_UTILITY__ diff --git a/lib/uvm_agents/uvma_clic/cov/uvma_clic_cov_model.sv b/lib/uvm_agents/uvma_clic/cov/uvma_clic_cov_model.sv new file mode 100644 index 0000000000..43c853e695 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/cov/uvma_clic_cov_model.sv @@ -0,0 +1,178 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CLIC_COV_MODEL_SV__ +`define __UVMA_CLIC_COV_MODEL_SV__ + + +/** + * Component encapsulating Interrupt functional coverage model. + */ +class uvma_clic_cov_model_c#(CLIC_ID_WIDTH) extends uvm_component; + + // Objects + uvma_clic_cfg_c cfg; + uvma_clic_cntxt_c#(CLIC_ID_WIDTH) cntxt; + uvma_clic_mon_trn_c#(CLIC_ID_WIDTH) mon_trn; + uvma_clic_seq_item_c seq_item; + + // TLM + uvm_tlm_analysis_fifo#(uvma_clic_mon_trn_c#(CLIC_ID_WIDTH) ) mon_trn_fifo; + uvm_tlm_analysis_fifo#(uvma_clic_seq_item_c) seq_item_fifo; + + + `uvm_component_utils_begin(uvma_clic_cov_model_c#(CLIC_ID_WIDTH)) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_cov_model", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null. + * 2. Builds fifos. + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Forks all sampling loops + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * TODO Describe sample_cfg + */ + extern virtual function void sample_cfg(); + + /** + * TODO Describe sample_cntxt + */ + extern virtual function void sample_cntxt(); + + /** + * TODO Describe sample_mon_trn + */ + extern virtual function void sample_mon_trn(); + + /** + * TODO Describe sample_seq_item + */ + extern virtual function void sample_seq_item(); + +endclass : uvma_clic_cov_model_c + + +`pragma protect begin + + +function uvma_clic_cov_model_c::new(string name="uvma_clic_cov_model", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_clic_cov_model_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_clic_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_clic_cntxt_c#(CLIC_ID_WIDTH))::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + mon_trn_fifo = new("mon_trn_fifo" , this); + seq_item_fifo = new("seq_item_fifo", this); + +endfunction : build_phase + + +task uvma_clic_cov_model_c::run_phase(uvm_phase phase); + super.run_phase(phase); + + if (cfg.enabled && cfg.cov_model_enabled) begin + fork + // Configuration + forever begin + cntxt.sample_cfg_e.wait_trigger(); + sample_cfg(); + end + + // Context + forever begin + cntxt.sample_cntxt_e.wait_trigger(); + sample_cntxt(); + end + + // Monitor transactions + forever begin + mon_trn_fifo.get(mon_trn); + sample_mon_trn(); + end + + // Sequence items + forever begin + seq_item_fifo.get(seq_item); + sample_seq_item(); + end + join_none + end + +endtask : run_phase + + +function void uvma_clic_cov_model_c::sample_cfg(); + + // TODO Implement uvma_clic_cov_model_c::sample_cfg(); + +endfunction : sample_cfg + + +function void uvma_clic_cov_model_c::sample_cntxt(); + + // TODO Implement uvma_clic_cov_model_c::sample_cntxt(); + +endfunction : sample_cntxt + + +function void uvma_clic_cov_model_c::sample_mon_trn(); + + // TODO Implement uvma_clic_cov_model_c::sample_mon_trn(); + +endfunction : sample_mon_trn + + +function void uvma_clic_cov_model_c::sample_seq_item(); + + // TODO Implement uvma_clic_cov_model_c::sample_seq_item(); + +endfunction : sample_seq_item + + +`pragma protect end + + +`endif // __UVMA_CLIC_COV_MODEL_SV__ diff --git a/lib/uvm_agents/uvma_clic/seq/uvma_clic_base_seq.sv b/lib/uvm_agents/uvma_clic/seq/uvma_clic_base_seq.sv new file mode 100644 index 0000000000..1c79a04ace --- /dev/null +++ b/lib/uvm_agents/uvma_clic/seq/uvma_clic_base_seq.sv @@ -0,0 +1,56 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CLIC_BASE_SEQ_SV__ +`define __UVMA_CLIC_BASE_SEQ_SV__ + + +/** + * Abstract object from which all other Interrupt agent sequences must extend. + * Subclasses must be run on Interrupt sequencer (uvma_clic_sqr_c) instance. + */ +class uvma_clic_base_seq_c#(CLIC_ID_WIDTH) extends uvm_sequence#( + .REQ(uvma_clic_seq_item_c), + .RSP(uvma_clic_seq_item_c) +); + + `uvm_object_utils(uvma_clic_base_seq_c) + `uvm_declare_p_sequencer(uvma_clic_sqr_c#(CLIC_ID_WIDTH)) + + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_base_seq"); + +endclass : uvma_clic_base_seq_c + + +`pragma protect begin + + +function uvma_clic_base_seq_c::new(string name="uvma_clic_base_seq"); + + super.new(name); + +endfunction : new + + +`pragma protect end + + +`endif // __UVMA_CLIC_BASE_SEQ_SV__ diff --git a/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_item.sv b/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_item.sv new file mode 100644 index 0000000000..772d33af12 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_item.sv @@ -0,0 +1,117 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CLIC_SEQ_ITEM_SV__ +`define __UVMA_CLIC_SEQ_ITEM_SV__ + + +/** + * Object created by Interrupt agent sequences extending uvma_clic_seq_base_c. + */ +class uvma_clic_seq_item_c extends uvml_trn_seq_item_c; + + rand uvma_clic_seq_item_action_enum action; + rand int unsigned index; + rand bit [8:0] level; + rand bit [1:0] privilege_mode; + rand bit sel_hardware_vectoring; + + rand int unsigned skew; // Skew (in cycles) before applying individual interrupt actions per interrupt + rand int unsigned repeat_count; // Number of times to apply action to interrupt + + rand int unsigned no_skew_wgt; + rand int unsigned skew_wgt; + + + // TODO FIXME update actually used signals + `uvm_object_utils_begin(uvma_clic_seq_item_c) + `uvm_field_enum(uvma_clic_seq_item_action_enum, action, UVM_DEFAULT) + `uvm_field_int(index, UVM_DEFAULT) + `uvm_field_int(level, UVM_DEFAULT) + `uvm_field_int(privilege_mode, UVM_DEFAULT) + `uvm_field_int(sel_hardware_vectoring, UVM_DEFAULT) + `uvm_field_int(skew, UVM_DEFAULT) + `uvm_field_int(no_skew_wgt, UVM_DEFAULT) + `uvm_field_int(skew_wgt, UVM_DEFAULT) + `uvm_field_int(repeat_count, UVM_DEFAULT) + `uvm_object_utils_end + + //constraint irq_index_c { + // irq_index inside {[0:4095]}; + //} + + // FIXME TODO move to core specific cfg + constraint irq_privilege_mode_c { + privilege_mode == 2'b11; + } + constraint irq_privilege_level_c { + level inside {[0:255]}; + } + constraint irq_index_c { + index inside {[0:1023]}; + } + + constraint valid_repeat_count_c { + repeat_count != 0; + } + + constraint default_repeat_count_c { + soft repeat_count == 1; + } + + constraint valid_skew_wgt { + no_skew_wgt + skew_wgt != 0; + skew_wgt == 1; + no_skew_wgt == 0; + } + + constraint default_skew_wgt_c { + no_skew_wgt inside {[0:5]}; + skew_wgt inside {[0:3]}; + } + + constraint skew_wgt_order_c { + solve skew_wgt before skew; + solve no_skew_wgt before skew; + } + + constraint default_skew_c { + skew dist { 0 :/ no_skew_wgt, + [1:32] :/ skew_wgt}; + } + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_seq_item"); + +endclass : uvma_clic_seq_item_c + +`pragma protect begin + + +function uvma_clic_seq_item_c::new(string name="uvma_clic_seq_item"); + + super.new(name); + +endfunction : new + + +`pragma protect end + + +`endif // __UVMA_CLIC_SEQ_ITEM_SV__ diff --git a/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_item_logger.sv b/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_item_logger.sv new file mode 100644 index 0000000000..5add5644e7 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_item_logger.sv @@ -0,0 +1,113 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CLIC_SEQ_ITEM_LOGGER_SV__ +`define __UVMA_CLIC_SEQ_ITEM_LOGGER_SV__ + + +/** + * Component writing Interrupt sequence items interrupt data to disk as plain text. + */ +class uvma_clic_seq_item_logger_c#(CLIC_ID_WIDTH) extends uvml_logs_seq_item_logger_c#( + .T_TRN (uvma_clic_seq_item_c), + .T_CFG (uvma_clic_cfg_c ), + .T_CNTXT(uvma_clic_cntxt_c#(CLIC_ID_WIDTH)) +); + + `uvm_component_utils(uvma_clic_seq_item_logger_c#(CLIC_ID_WIDTH)) + + + /** + * Default constructor. + */ + function new(string name="uvma_clic_seq_item_logger", uvm_component parent=null); + + super.new(name, parent); + + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_clic_seq_item_c t); + + // TODO Implement uvma_clic_seq_item_logger_c::write() + // Ex: fwrite($sformatf(" %t | %08h | %02b | %04d | %02h |", $realtime(), t.a, t.b, t.c, t.d)); + + endfunction : write + + /** + * Writes log header to disk. + */ + virtual function void print_header(); + + // TODO Implement uvma_clic_seq_item_logger_c::print_header() + // Ex: fwrite("----------------------------------------------"); + // fwrite(" TIME | FIELD A | FIELD B | FIELD C | FIELD D "); + // fwrite("----------------------------------------------"); + + endfunction : print_header + +endclass : uvma_clic_seq_item_logger_c + + +/** + * Component writing INTERRUPT monitor transactions interrupt data to disk as JavaScript Object Notation (JSON). + */ +class uvma_clic_seq_item_logger_json_c#(CLIC_ID_WIDTH) extends uvma_clic_seq_item_logger_c#(CLIC_ID_WIDTH); + + `uvm_component_utils(uvma_clic_seq_item_logger_json_c) + + + /** + * Set file extension to '.json'. + */ + function new(string name="uvma_clic_seq_item_logger_json", uvm_component parent=null); + + super.new(name, parent); + fextension = "json"; + + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_clic_seq_item_c t); + + // TODO Implement uvma_clic_seq_item_logger_json_c::write() + // Ex: fwrite({"{", + // $sformatf("\"time\":\"%0t\",", $realtime()), + // $sformatf("\"a\":%h," , t.a ), + // $sformatf("\"b\":%b," , t.b ), + // $sformatf("\"c\":%d," , t.c ), + // $sformatf("\"d\":%h," , t.c ), + // "},"}); + + endfunction : write + + /** + * Empty function. + */ + virtual function void print_header(); + + // Do nothing: JSON files do not use headers. + + endfunction : print_header + +endclass : uvma_clic_seq_item_logger_json_c + +`endif // __UVMA_CLIC_SEQ_ITEM_LOGGER_SV__ diff --git a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vseq_lib.sv b/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_lib.sv similarity index 50% rename from cv32e40x/env/uvme/vseq/uvme_cv32e40x_vseq_lib.sv rename to lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_lib.sv index e2a83cbfa6..03cd8e5a1b 100644 --- a/cv32e40x/env/uvme/vseq/uvme_cv32e40x_vseq_lib.sv +++ b/lib/uvm_agents/uvma_clic/seq/uvma_clic_seq_lib.sv @@ -1,5 +1,6 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -14,39 +15,40 @@ // limitations under the License. -`ifndef __UVME_CV32E40X_VSEQ_LIB_SV__ -`define __UVME_CV32E40X_VSEQ_LIB_SV__ +`ifndef __UVMA_CLIC_SEQ_LIB_SV__ +`define __UVMA_CLIC_SEQ_LIB_SV__ /** - * Virtual sequence library for CV32E40X environment. + * Object holding sequence library for Interrupt agent. */ -class uvme_cv32e40x_vseq_lib_c extends uvm_sequence_library#( - .REQ(uvm_sequence_item), - .RSP(uvm_sequence_item) +class uvma_clic_seq_lib_c extends uvm_sequence_library#( + .REQ(uvma_clic_seq_item_c), + .RSP(uvma_clic_seq_item_c) ); - `uvm_object_utils (uvme_cv32e40x_vseq_lib_c) - `uvm_sequence_library_utils(uvme_cv32e40x_vseq_lib_c) + `uvm_object_utils (uvma_clic_seq_lib_c) + `uvm_sequence_library_utils(uvma_clic_seq_lib_c) /** - * Initializes sequence library. + * Initializes sequence library */ - extern function new(string name="uvme_cv32e40x_vseq_lib"); + extern function new(string name="uvma_clic_seq_lib"); -endclass : uvme_cv32e40x_vseq_lib_c +endclass : uvma_clic_seq_lib_c -function uvme_cv32e40x_vseq_lib_c::new(string name="uvme_cv32e40x_vseq_lib"); +function uvma_clic_seq_lib_c::new(string name="uvma_clic_seq_lib"); super.new(name); init_sequence_library(); - // TODO Add sequences to uvme_cv32e40x_vseq_lib_c - // Ex: add_sequence(uvme_cv32e40x_abc_vseq_c::get_type()); + // TODO Add sequences to uvma_clic_seq_lib_c + // Ex: add_sequence(uvma_clic_abc_seq_c::get_type()); endfunction : new -`endif // __UVME_CV32E40X_VSEQ_LIB_SV__ +`endif // __UVMA_CLIC_SEQ_LIB_SV__ + diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_agent.sv b/lib/uvm_agents/uvma_clic/uvma_clic_agent.sv new file mode 100644 index 0000000000..2fdc03a808 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_agent.sv @@ -0,0 +1,234 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_CLIC_AGENT_SV__ +`define __UVMA_CLIC_AGENT_SV__ + +/** + * Top-level component that encapsulates, builds and connects all others. + * Capable of driving/monitoring Clock & Reset interface. + */ +class uvma_clic_agent_c#(CLIC_ID_WIDTH) extends uvm_agent; + + // Objects + uvma_clic_cfg_c cfg; + uvma_clic_cntxt_c#(CLIC_ID_WIDTH) cntxt; + + // Components + uvma_clic_drv_c#(CLIC_ID_WIDTH) driver; + uvma_clic_mon_c#(CLIC_ID_WIDTH) monitor; + uvma_clic_sqr_c#(CLIC_ID_WIDTH) sequencer; + uvma_clic_cov_model_c#(CLIC_ID_WIDTH) cov_model; + uvma_clic_seq_item_logger_c#(CLIC_ID_WIDTH) seq_item_logger; + uvma_clic_mon_trn_logger_c#(CLIC_ID_WIDTH) mon_trn_logger; + + // TLM + uvm_analysis_port#(uvma_clic_seq_item_c) drv_ap; + uvm_analysis_port#(uvma_clic_mon_trn_c#(CLIC_ID_WIDTH)) mon_ap; + + + `uvm_component_utils_begin(uvma_clic_agent_c#(CLIC_ID_WIDTH)) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_agent", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null + * 2. Builds all components + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * 1. Links agent's analysis ports to sub-components' + * 2. Connects coverage models and loggers + */ + extern virtual function void connect_phase(uvm_phase phase); + + /** + * Uses uvm_config_db to retrieve cfg and hand out to sub-components. + */ + extern function void get_and_set_cfg(); + + /** + * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. + */ + extern function void get_and_set_cntxt(); + + /** + * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this + * agent. + */ + extern function void retrieve_vif(); + + /** + * Creates sub-components. + */ + extern function void create_components(); + + /** + * Connects sequencer and driver's TLM port(s). + */ + extern function void connect_sequencer_and_driver(); + + /** + * Connects agent's TLM ports to driver's and monitor's. + */ + extern function void connect_analysis_ports(); + + /** + * Connects coverage model to monitor and driver's analysis ports. + */ + extern function void connect_cov_model(); + + /** + * Connects transaction loggers to monitor and driver's analysis ports. + */ + extern function void connect_trn_loggers(); + +endclass : uvma_clic_agent_c + + +function uvma_clic_agent_c::new(string name="uvma_clic_agent", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_clic_agent_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + get_and_set_cfg (); + get_and_set_cntxt(); + retrieve_vif (); + create_components(); + +endfunction : build_phase + + +function void uvma_clic_agent_c::connect_phase(uvm_phase phase); + + super.connect_phase(phase); + + connect_sequencer_and_driver(); + connect_analysis_ports(); + + if (cfg.cov_model_enabled) begin + connect_cov_model(); + end + if (cfg.trn_log_enabled) begin + connect_trn_loggers(); + end + +endfunction: connect_phase + + +function void uvma_clic_agent_c::get_and_set_cfg(); + + void'(uvm_config_db#(uvma_clic_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + else begin + `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) + uvm_config_db#(uvma_clic_cfg_c)::set(this, "*", "cfg", cfg); + end + +endfunction : get_and_set_cfg + + +function void uvma_clic_agent_c::get_and_set_cntxt(); + + void'(uvm_config_db#(uvma_clic_cntxt_c#(CLIC_ID_WIDTH))::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) + cntxt = uvma_clic_cntxt_c#(CLIC_ID_WIDTH)::type_id::create("cntxt"); + end + uvm_config_db#(uvma_clic_cntxt_c#(CLIC_ID_WIDTH))::set(this, "*", "cntxt", cntxt); + +endfunction : get_and_set_cntxt + + +function void uvma_clic_agent_c::retrieve_vif(); + + if (!uvm_config_db#(virtual uvma_clic_if_t#(CLIC_ID_WIDTH))::get(this, "", "vif", cntxt.vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", $typename(cntxt.vif)), UVM_DEBUG) + end + +endfunction : retrieve_vif + + +function void uvma_clic_agent_c::create_components(); + + monitor = uvma_clic_mon_c#(CLIC_ID_WIDTH)::type_id::create("monitor", this); + cov_model = uvma_clic_cov_model_c#(CLIC_ID_WIDTH)::type_id::create("cov_model", this); + mon_trn_logger = uvma_clic_mon_trn_logger_c#(CLIC_ID_WIDTH)::type_id::create("mon_trn_logger", this); + + if (cfg.is_active == UVM_ACTIVE) begin + sequencer = uvma_clic_sqr_c#(CLIC_ID_WIDTH)::type_id::create("sequencer", this); + driver = uvma_clic_drv_c#(CLIC_ID_WIDTH)::type_id::create("driver", this); + seq_item_logger = uvma_clic_seq_item_logger_c#(CLIC_ID_WIDTH)::type_id::create("seq_item_logger", this); + end + +endfunction : create_components + + +function void uvma_clic_agent_c::connect_sequencer_and_driver(); + + //sequencer.set_arbitration(cfg.sqr_arb_mode); + driver.seq_item_port.connect(sequencer.seq_item_export); + +endfunction : connect_sequencer_and_driver + + +function void uvma_clic_agent_c::connect_analysis_ports(); + + drv_ap = driver .ap; + mon_ap = monitor.ap; + +endfunction : connect_analysis_ports + + +function void uvma_clic_agent_c::connect_cov_model(); + + mon_ap.connect(cov_model.mon_trn_fifo.analysis_export); + drv_ap.connect(cov_model.seq_item_fifo.analysis_export); + +endfunction : connect_cov_model + + +function void uvma_clic_agent_c::connect_trn_loggers(); + + mon_ap.connect(mon_trn_logger.analysis_export); + drv_ap.connect(seq_item_logger.analysis_export); + +endfunction : connect_trn_loggers + + +`endif // __UVMA_CLIC_AGENT_SV__ diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_cfg.sv b/lib/uvm_agents/uvma_clic/uvma_clic_cfg.sv new file mode 100644 index 0000000000..389222ae66 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_cfg.sv @@ -0,0 +1,82 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_CLIC_CFG_SV__ +`define __UVMA_CLIC_CFG_SV__ + + +/** + * Object encapsulating all parameters for creating, connecting and running all + * Clock & Reset agent (uvma_clic_agent_c) components. + */ +class uvma_clic_cfg_c extends uvm_object; + + // Common options + rand bit enabled; + rand uvm_active_passive_enum is_active; + rand bit is_mmode_irq_only; + + rand bit cov_model_enabled; + rand bit trn_log_enabled; + + // Implementation options + rand bit[31:0] valid_irq_mask; ///< State variable: the valid clics for the core under test + rand bit[31:0] enabled_irq_mask; ///< The mask of clics that can be driven + rand bit clear_irq_on_ack; + + `uvm_object_utils_begin(uvma_clic_cfg_c) + `uvm_field_int ( enabled , UVM_DEFAULT) + `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT) + `uvm_field_int ( is_mmode_irq_only , UVM_DEFAULT) + `uvm_field_int ( cov_model_enabled , UVM_DEFAULT) + `uvm_field_int ( trn_log_enabled , UVM_DEFAULT) + `uvm_field_int ( clear_irq_on_ack , UVM_DEFAULT) + `uvm_field_int ( enabled_irq_mask , UVM_DEFAULT) + `uvm_object_utils_end + + + constraint defaults_cons { + soft enabled == 1; + soft is_active == UVM_PASSIVE; + soft is_mmode_irq_only == 0; + soft cov_model_enabled == 0; + soft trn_log_enabled == 1; + soft clear_irq_on_ack == 1; + soft enabled_irq_mask == 32'hffff_ffff; + } + + constraint valid_irq { + // Should always have at least one valid clic enabled + (enabled_irq_mask & valid_irq_mask) != 0; + } + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_cfg"); + +endclass : uvma_clic_cfg_c + +function uvma_clic_cfg_c::new(string name="uvma_clic_cfg"); + + super.new(name); + +endfunction : new + +`endif // __UVMA_CLIC_CFG_SV__ diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_cntxt.sv b/lib/uvm_agents/uvma_clic/uvma_clic_cntxt.sv new file mode 100644 index 0000000000..1b03b921e0 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_cntxt.sv @@ -0,0 +1,75 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CLIC_CNTXT_SV__ +`define __UVMA_CLIC_CNTXT_SV__ + + +/** + * Object encapsulating all state variables for all Interrupt agent + * (uvma_clic_agent_c) components. + */ +class uvma_clic_cntxt_c#(CLIC_ID_WIDTH) extends uvm_object; + + // Handle to agent interface + virtual uvma_clic_if_t#(CLIC_ID_WIDTH) vif; + + // Events + uvm_event sample_cfg_e; + uvm_event sample_cntxt_e; + + `uvm_object_utils_begin(uvma_clic_cntxt_c#(CLIC_ID_WIDTH)) + `uvm_field_event(sample_cfg_e , UVM_DEFAULT) + `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) + `uvm_object_utils_end + + /** + * Builds events. + */ + extern function new(string name="uvma_clic_cntxt"); + + /** + * TODO Describe uvma_clic_cntxt_c::reset() + */ + extern function void reset(); + +endclass : uvma_clic_cntxt_c + + +`pragma protect begin + + +function uvma_clic_cntxt_c::new(string name="uvma_clic_cntxt"); + + super.new(name); + + sample_cfg_e = new("sample_cfg_e" ); + sample_cntxt_e = new("sample_cntxt_e"); + +endfunction : new + +function void uvma_clic_cntxt_c::reset(); + + // TODO Implement uvma_clic_cntxt_c::reset() + +endfunction : reset + + +`pragma protect end + + +`endif // __UVMA_CLIC_CNTXT_SV__ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_macros.sv b/lib/uvm_agents/uvma_clic/uvma_clic_constants.sv similarity index 74% rename from cv32e40x/env/uvme/uvme_cv32e40x_macros.sv rename to lib/uvm_agents/uvma_clic/uvma_clic_constants.sv index 2c24cf292e..133cf983b9 100644 --- a/cv32e40x/env/uvme/uvme_cv32e40x_macros.sv +++ b/lib/uvm_agents/uvma_clic/uvma_clic_constants.sv @@ -1,5 +1,6 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -14,12 +15,11 @@ // limitations under the License. -`ifndef __UVME_CV32E40X_MACROS_SV__ -`define __UVME_CV32E40X_MACROS_SV__ +`ifndef __UVMA_CLIC_CONSTANTS_SV__ +`define __UVMA_CLIC_CONSTANTS_SV__ -`define per_instance_fcov `ifndef DSIM option.per_instance = 1; `endif -`define UVME_CV32E40X_MEM_SIZE 22 -`endif // __UVME_CV32E40X_MACROS_SV__ + +`endif // __UVMA_CLIC_CONSTANTS_SV__ diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_drv.sv b/lib/uvm_agents/uvma_clic/uvma_clic_drv.sv new file mode 100644 index 0000000000..899ee3ea94 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_drv.sv @@ -0,0 +1,242 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +`ifndef __UVMA_CLIC_DRV_SV__ +`define __UVMA_CLIC_DRV_SV__ + +/** + * Component driving a Clock & Reset virtual interface (uvma_clic_if_t). + */ +class uvma_clic_drv_c#(CLIC_ID_WIDTH) extends uvm_driver#( + .REQ(uvma_clic_seq_item_c), + .RSP(uvma_clic_seq_item_c) +); + + // Objects + uvma_clic_cfg_c cfg; + uvma_clic_cntxt_c#(CLIC_ID_WIDTH) cntxt; + + semaphore assert_until_ack_sem[4096]; + + // TLM + uvm_analysis_port#(uvma_clic_seq_item_c) ap; + + `uvm_component_utils_begin(uvma_clic_drv_c#(CLIC_ID_WIDTH)) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_drv", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null. + * 2. Builds ap. + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Obtains the reqs from the sequence item port and calls drv_req() + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Thread that clears acknowledged interrupts that were randomly asserted + */ + extern task irq_ack_clear(); + + /** + * Drives the virtual interface's (cntxt.vif) signals using req's contents. + */ + extern task drv_req(uvma_clic_seq_item_c req); + + /** + * Forked thread to handle interrupts + */ + extern task assert_irq_until_ack(uvma_clic_seq_item_c req); + + /** + * Assert an interrupt signal + */ + extern task assert_irq(uvma_clic_seq_item_c req); + + /** + * Deassert an interrupt signal + */ + extern task deassert_irq(uvma_clic_seq_item_c req); + +endclass : uvma_clic_drv_c + +function uvma_clic_drv_c::new(string name="uvma_clic_drv", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_clic_drv_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_clic_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + uvm_config_db#(uvma_clic_cfg_c)::set(this, "*", "cfg", cfg); + + void'(uvm_config_db#(uvma_clic_cntxt_c#(CLIC_ID_WIDTH))::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + uvm_config_db#(uvma_clic_cntxt_c#(CLIC_ID_WIDTH))::set(this, "*", "cntxt", cntxt); + + ap = new("ap", this); + + foreach (assert_until_ack_sem[i]) begin + assert_until_ack_sem[i] = new(1); + end +endfunction : build_phase + + +task uvma_clic_drv_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + // Enable the driver in the interface + cntxt.vif.is_active = cfg.enabled; + cntxt.vif.is_mmode_irq_only = cfg.is_mmode_irq_only; + + // Fork thread to deassert randomly asserted clics when acknowledged + if (cfg.clear_irq_on_ack) begin + fork + irq_ack_clear(); + join_none + end + + forever begin + seq_item_port.get_next_item(req); + `uvml_hrtbt() + drv_req(req); + ap.write(req); + seq_item_port.item_done(); + end + +endtask : run_phase + +task uvma_clic_drv_c::drv_req(uvma_clic_seq_item_c req); + `uvm_info("CLICDRV", $sformatf("Driving:\n%s", req.sprint()), UVM_HIGH); + case (req.action) + UVMA_CLIC_SEQ_ITEM_ACTION_ASSERT_UNTIL_ACK: begin + assert_irq_until_ack(req); + end + UVMA_CLIC_SEQ_ITEM_ACTION_ASSERT: begin + assert_irq(req); + end + UVMA_CLIC_SEQ_ITEM_ACTION_DEASSERT: begin + deassert_irq(req); + end + endcase + +endtask : drv_req + +task uvma_clic_drv_c::assert_irq_until_ack(uvma_clic_seq_item_c req); + // If a thread is already running on this irq, then exit + if (!assert_until_ack_sem[req.index].try_get(1)) + return; + + repeat (req.skew) @(cntxt.vif.drv_cb); + + for (int loop = 0; loop < req.repeat_count; loop++) begin + repeat (req.skew) @(cntxt.vif.drv_cb); + cntxt.vif.drv_cb.clic_irq_drv <= 1'b1; + cntxt.vif.drv_cb.clic_irq_id_drv <= req.index; + cntxt.vif.drv_cb.clic_irq_shv_drv <= req.sel_hardware_vectoring; + cntxt.vif.drv_cb.clic_irq_priv_drv <= req.privilege_mode; + cntxt.vif.drv_cb.clic_irq_level_drv <= req.level; + + while (1) begin + @(cntxt.vif.mon_cb); + if (cntxt.vif.mon_cb.irq_ack) begin + break; + end + end + end + + `uvm_info("CLICDRV", $sformatf("assert_irq_until_ack: Deasserting irq: %0d", req.index), UVM_DEBUG); + cntxt.vif.drv_cb.clic_irq_drv <= 1'b0; + cntxt.vif.drv_cb.clic_irq_id_drv <= req.index; + cntxt.vif.drv_cb.clic_irq_shv_drv <= req.sel_hardware_vectoring; + cntxt.vif.drv_cb.clic_irq_priv_drv <= req.privilege_mode; + cntxt.vif.drv_cb.clic_irq_level_drv <= req.level; + assert_until_ack_sem[req.index].put(1); +endtask : assert_irq_until_ack + +task uvma_clic_drv_c::assert_irq(uvma_clic_seq_item_c req); + if (assert_until_ack_sem[req.index].try_get(1)) begin + repeat (req.skew) @(cntxt.vif.drv_cb); + cntxt.vif.drv_cb.clic_irq_drv <= 1'b1; + cntxt.vif.drv_cb.clic_irq_id_drv <= req.index; + cntxt.vif.drv_cb.clic_irq_shv_drv <= req.sel_hardware_vectoring; + cntxt.vif.drv_cb.clic_irq_priv_drv <= req.privilege_mode; + cntxt.vif.drv_cb.clic_irq_level_drv <= req.level; + assert_until_ack_sem[req.index].put(1); + return; + end +endtask : assert_irq + +task uvma_clic_drv_c::deassert_irq(uvma_clic_seq_item_c req); + if (assert_until_ack_sem[req.index].try_get(1)) begin + repeat (req.skew) @(cntxt.vif.drv_cb); + cntxt.vif.drv_cb.clic_irq_drv <= 1'b0; + cntxt.vif.drv_cb.clic_irq_id_drv <= req.index; + cntxt.vif.drv_cb.clic_irq_shv_drv <= req.sel_hardware_vectoring; + cntxt.vif.drv_cb.clic_irq_priv_drv <= req.privilege_mode; + cntxt.vif.drv_cb.clic_irq_level_drv <= req.level; + assert_until_ack_sem[req.index].put(1); + return; + end +endtask : deassert_irq + +task uvma_clic_drv_c::irq_ack_clear(); + while(1) begin + @(cntxt.vif.mon_cb); + if (cntxt.vif.mon_cb.irq_ack && cfg.enabled) begin + // Try to get the semaphore for the irq_id, + // If we can't get it, then this irq is managed by assert_irq_until_ack and we will ignore this ack + // Otherwise deassert the interrupt + int unsigned irq_id; + + irq_id = cntxt.vif.mon_cb.clic_irq_id_drv; + + `uvm_info("IRQDRV", $sformatf("irq_ack_clear: ack for IRQ: %0d", irq_id), UVM_DEBUG); + if (assert_until_ack_sem[irq_id].try_get(1)) begin + `uvm_info("IRQDRV", $sformatf("irq_ack_clear: Clearing IRQ: %0d", irq_id), UVM_DEBUG); + cntxt.vif.drv_cb.clic_irq_drv <= 1'b0; + cntxt.vif.drv_cb.clic_irq_id_drv <= 11'b0; + cntxt.vif.drv_cb.clic_irq_shv_drv <= 1'b0; + cntxt.vif.drv_cb.clic_irq_priv_drv <= 2'b00; + cntxt.vif.drv_cb.clic_irq_level_drv <= 8'b0; + assert_until_ack_sem[irq_id].put(1); + end + end + end +endtask + +`endif // __UVMA_CLIC_DRV_SV__ diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_if.sv b/lib/uvm_agents/uvma_clic/uvma_clic_if.sv new file mode 100644 index 0000000000..42e7d1338c --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_if.sv @@ -0,0 +1,129 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CLIC_IF_SV__ +`define __UVMA_CLIC_IF_SV__ + + +/** + * Encapsulates all signals and clocking of Interrupt interface. Used by + * monitor and driver. + */ +interface uvma_clic_if_t#(CLIC_ID_WIDTH = 5); + + // --------------------------------------------------------------------------- + // Interface wires + // --------------------------------------------------------------------------- + wire clk; + wire reset_n; + + wire clic_irq; + wire [CLIC_ID_WIDTH-1:0] clic_irq_id; + wire [7:0] clic_irq_level; + wire [1:0] clic_irq_priv; + wire clic_irq_shv; + wire irq_ack; + wire [31:0] irq; + wire [4:0] irq_id; + + // // Used to time true clic entry with tracer instruction retirement + wire deferint; + wire ovp_cpu_state_stepi; + + // ------------------------------------------------------------------- + // Testbench control + // --------------------------------------------------------------------------- + // ------------------------------------------------------------------- + bit is_active; // Set to active drive the clic lines + bit is_mmode_irq_only; + bit [31:0] irq_drv; // TB clic driver + + bit clic_irq_drv; + bit [CLIC_ID_WIDTH-1:0] clic_irq_id_drv; + bit [1:0] clic_irq_priv_drv; + bit [7:0] clic_irq_level_drv; + bit clic_irq_shv_drv; + + bit [1:0] clic_irq_priv_masked; + + // typedef to be able to parameterize clic_irq_id_drv assignments + // without warnings + typedef bit [$bits(clic_irq_id_drv) - 1:0] clic_irq_id_t; + + // ------------------------------------------------------------------- + // Begin module code + // ------------------------------------------------------------------- + + // Mux in driver to irq lines + //always_comb begin + // clic_irq = is_active ? clic_irq_drv : 1'b0; + //end + assign clic_irq = is_active ? clic_irq_drv : 1'b0; + assign clic_irq_id = is_active ? clic_irq_id_drv : clic_irq_id_t'('b0); + assign clic_irq_level = is_active ? clic_irq_level_drv : 2'b0; + assign clic_irq_priv = is_active ? clic_irq_priv_masked : 2'b11; + assign clic_irq_shv = is_active ? clic_irq_shv_drv : 1'b0; + + assign clic_irq_priv_masked = is_mmode_irq_only ? 2'b11 : clic_irq_priv_drv; + + `ifndef FORMAL // suppress warning, initial is not supported in formal + initial begin + is_active = 1'b0; + clic_irq_drv = '0; + end + `endif + + /** + * Used by target DUT. + */ + clocking dut_cb @(posedge clk or reset_n); + endclocking : dut_cb + + /** + * Used by uvma_clic_drv_c. + */ + clocking drv_cb @(posedge clk or reset_n); + input #1step irq_ack; + output irq_drv, + clic_irq_drv, + clic_irq_id_drv, + clic_irq_level_drv, + clic_irq_priv_drv, + clic_irq_shv_drv; + endclocking : drv_cb + + /** + * Used by uvma_clic_mon_c. + */ + clocking mon_cb @(posedge clk or reset_n); + input #1step irq_ack, + irq_drv, + clic_irq_drv, + clic_irq_id_drv, + clic_irq_level_drv, + clic_irq_priv_drv, + clic_irq_shv_drv; + endclocking : mon_cb + + modport dut_mp (clocking dut_cb); + modport active_mp (clocking drv_cb); + modport passive_mp(clocking mon_cb); + +endinterface : uvma_clic_if_t + + +`endif // __UVMA_CLIC_IF_SV__ diff --git a/cv32e40x/env/uvme/uvme_cv32e40x_pkg.flist b/lib/uvm_agents/uvma_clic/uvma_clic_macros.sv similarity index 81% rename from cv32e40x/env/uvme/uvme_cv32e40x_pkg.flist rename to lib/uvm_agents/uvma_clic/uvma_clic_macros.sv index cfea6f5807..0a0d0676d6 100644 --- a/cv32e40x/env/uvme/uvme_cv32e40x_pkg.flist +++ b/lib/uvm_agents/uvma_clic/uvma_clic_macros.sv @@ -1,5 +1,6 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -14,10 +15,11 @@ // limitations under the License. -// Directories -+incdir+${DV_UVME_PATH} -+incdir+${DV_UVME_PATH}/cov -+incdir+${DV_UVME_PATH}/vseq +`ifndef __UVMA_CLIC_MACROS_SV__ +`define __UVMA_CLIC_MACROS_SV__ -// Files -${DV_UVME_PATH}/uvme_cv32e40x_pkg.sv + + + + +`endif // __UVMA_CLIC_MACROS_SV__ diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_mon.sv b/lib/uvm_agents/uvma_clic/uvma_clic_mon.sv new file mode 100644 index 0000000000..0c29a71e3a --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_mon.sv @@ -0,0 +1,160 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_CLIC_MON_SV__ +`define __UVMA_CLIC_MON_SV__ + + +/** + * Component sampling transactions from a Clock & Reset virtual interface + * (uvma_clic_if_t). + */ +class uvma_clic_mon_c#(CLIC_ID_WIDTH) extends uvm_monitor; + + // Objects + uvma_clic_cfg_c cfg; + uvma_clic_cntxt_c#(CLIC_ID_WIDTH) cntxt; + + // TLM + // This analysis port will fire when the irq_ack_o is seen (core acknowledges the clic) + uvm_analysis_port#(uvma_clic_mon_trn_c#(CLIC_ID_WIDTH)) ap; + + // This analysis port will fire when the first instruction in the ISR is retired (i.e. the MTVEC location) + uvm_analysis_port#(uvma_clic_mon_trn_c#(CLIC_ID_WIDTH)) ap_iss; + + `uvm_component_utils_begin(uvma_clic_mon_c#(CLIC_ID_WIDTH)) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_mon", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null. + * 2. Builds ap. + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Oversees monitoring via monitor_clk() and monitor_reset() tasks in parallel + * forks. + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Publish a monitor transactin when clic is taken. + */ + extern virtual task monitor_irq(); + + /** + * Publish a monitor transaction when clic is taken (delayed until the first instruction of the ISR is retired) + */ + extern virtual task monitor_irq_iss(); + +endclass : uvma_clic_mon_c + +function uvma_clic_mon_c::new(string name="uvma_clic_mon", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_clic_mon_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_clic_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_clic_cntxt_c#(CLIC_ID_WIDTH))::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + ap = new("ap", this); + ap_iss = new("ap_iss", this); + +endfunction : build_phase + +task uvma_clic_mon_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + if (cfg.enabled) begin + while (1) begin + wait (cntxt.vif.reset_n === 1'b0); + wait (cntxt.vif.reset_n === 1'b1); + + fork begin + // To maintain random thread stability launch iss thread always, but it will exit immediately if no iss configured + fork + monitor_irq(); + monitor_irq_iss(); + join_none + + wait (cntxt.vif.reset_n === 1'b0); + + disable fork; + end + join + end + end +endtask : run_phase + +task uvma_clic_mon_c::monitor_irq(); + while(1) begin + @(cntxt.vif.mon_cb); + + if (cntxt.vif.mon_cb.irq_ack) begin + uvma_clic_mon_trn_c#(CLIC_ID_WIDTH) mon_trn = uvma_clic_mon_trn_c#(CLIC_ID_WIDTH)::type_id::create("mon_irq_trn"); + mon_trn.action = UVMA_CLIC_MON_ACTION_IRQ; + mon_trn.id = cntxt.vif.mon_cb.clic_irq_id_drv; + ap.write(mon_trn); + end + end +endtask : monitor_irq + +task uvma_clic_mon_c::monitor_irq_iss(); + if ($test$plusargs("USE_ISS")) begin + while(1) begin + @(cntxt.vif.mon_cb); + + if (cntxt.vif.mon_cb.irq_ack) begin + uvma_clic_mon_trn_c#(CLIC_ID_WIDTH) mon_trn = uvma_clic_mon_trn_c#(CLIC_ID_WIDTH)::type_id::create("mon_irq_trn"); + mon_trn.action = UVMA_CLIC_MON_ACTION_IRQ; + mon_trn.id = cntxt.vif.mon_cb.clic_irq_id_drv; + + // Wait for the ISS to enter + wait (cntxt.vif.deferint == 1'b0); + wait (cntxt.vif.ovp_cpu_state_stepi == 1'b1); + + ap_iss.write(mon_trn); + end + end + end +endtask : monitor_irq_iss + + +`endif // __UVMA_CLIC_MON_SV__ diff --git a/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_cntxt.sv b/lib/uvm_agents/uvma_clic/uvma_clic_mon_trn.sv similarity index 52% rename from cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_cntxt.sv rename to lib/uvm_agents/uvma_clic/uvma_clic_mon_trn.sv index 016f2568ac..aa5505916d 100644 --- a/cv32e40x/env/uvme/uvma_cv32e40x_core_cntrl_cntxt.sv +++ b/lib/uvm_agents/uvma_clic/uvma_clic_mon_trn.sv @@ -1,6 +1,6 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -15,37 +15,43 @@ // limitations under the License. -`ifndef __UVMA_CV32E40X_CORE_CNTRL_CNTXT_SV__ -`define __UVMA_CV32E40X_CORE_CNTRL_CNTXT_SV__ +`ifndef __UVMA_CLIC_MON_TRN_SV__ +`define __UVMA_CLIC_MON_TRN_SV__ /** - * Object encapsulating all state variables for all Rvvi agent - * (uvma_core_cntrl_agent_c) components. + * Object rebuilt from the Interrupt monitor Analog of uvma_clic_seq_item_c. */ - class uvma_cv32e40x_core_cntrl_cntxt_c extends uvma_core_cntrl_cntxt_c; +class uvma_clic_mon_trn_c#(CLIC_ID_WIDTH) extends uvml_trn_mon_trn_c; - virtual uvme_cv32e40x_core_cntrl_if core_cntrl_vif; + uvma_clic_mon_action_enum action; - `uvm_object_utils_begin(uvma_cv32e40x_core_cntrl_cntxt_c) + int unsigned id; + + `uvm_object_utils_begin(uvma_clic_mon_trn_c#(CLIC_ID_WIDTH)) + `uvm_field_enum(uvma_clic_mon_action_enum, action, UVM_DEFAULT) + `uvm_field_int(id, UVM_DEFAULT) `uvm_object_utils_end /** - * Builds events. + * Default constructor. */ - extern function new(string name="uvma_cv32e40x_core_cntrl_cntxt"); + extern function new(string name="uvma_clic_mon_trn"); + +endclass : uvma_clic_mon_trn_c -endclass : uvma_cv32e40x_core_cntrl_cntxt_c `pragma protect begin -function uvma_cv32e40x_core_cntrl_cntxt_c::new(string name="uvma_cv32e40x_core_cntrl_cntxt"); + +function uvma_clic_mon_trn_c::new(string name="uvma_clic_mon_trn"); super.new(name); endfunction : new + `pragma protect end -`endif // __UVMA_CV32E40X_CORE_CNTRL_CNTXT_SV__ +`endif // __UVMA_CLIC_MON_TRN_SV__ diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_mon_trn_logger.sv b/lib/uvm_agents/uvma_clic/uvma_clic_mon_trn_logger.sv new file mode 100644 index 0000000000..9e81efdbe8 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_mon_trn_logger.sv @@ -0,0 +1,114 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CLIC_MON_TRN_LOGGER_SV__ +`define __UVMA_CLIC_MON_TRN_LOGGER_SV__ + + +/** + * Component writing Interrupt monitor transactions clic data to disk as plain text. + */ +class uvma_clic_mon_trn_logger_c#(CLIC_ID_WIDTH) extends uvml_logs_mon_trn_logger_c#( + .T_TRN (uvma_clic_mon_trn_c#(CLIC_ID_WIDTH)), + .T_CFG (uvma_clic_cfg_c ), + .T_CNTXT(uvma_clic_cntxt_c#(CLIC_ID_WIDTH) ) +); + + `uvm_component_utils(uvma_clic_mon_trn_logger_c#(CLIC_ID_WIDTH)) + + + /** + * Default constructor. + */ + function new(string name="uvma_clic_mon_trn_logger", uvm_component parent=null); + + super.new(name, parent); + + endfunction : new + + /** + * Writes contents of t to disk + */ + virtual function void write(uvma_clic_mon_trn_c#(CLIC_ID_WIDTH) t); + + // TODO Implement uvma_clic_mon_trn_logger_c::write() + // Ex: fwrite($sformatf(" %t | %08h | %02b | %04d | %02h |", $realtime(), t.a, t.b, t.c, t.d)); + + endfunction : write + + /** + * Writes log header to disk + */ + virtual function void print_header(); + + // TODO Implement uvma_clic_mon_trn_logger_c::print_header() + // Ex: fwrite("----------------------------------------------"); + // fwrite(" TIME | FIELD A | FIELD B | FIELD C | FIELD D "); + // fwrite("----------------------------------------------"); + + endfunction : print_header + +endclass : uvma_clic_mon_trn_logger_c + + +/** + * Component writing CLIC monitor transactions clic data to disk as JavaScript Object Notation (JSON). + */ +class uvma_clic_mon_trn_logger_json_c#(CLIC_ID_WIDTH) extends uvma_clic_mon_trn_logger_c#(CLIC_ID_WIDTH); + + `uvm_component_utils(uvma_clic_mon_trn_logger_json_c#(CLIC_ID_WIDTH)) + + + /** + * Set file extension to '.json'. + */ + function new(string name="uvma_clic_mon_trn_logger_json", uvm_component parent=null); + + super.new(name, parent); + fextension = "json"; + + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_clic_mon_trn_c#(CLIC_ID_WIDTH) t); + + // TODO Implement uvma_clic_mon_trn_logger_json_c::write() + // Ex: fwrite({"{", + // $sformatf("\"time\":\"%0t\",", $realtime()), + // $sformatf("\"a\":%h," , t.a ), + // $sformatf("\"b\":%b," , t.b ), + // $sformatf("\"c\":%d," , t.c ), + // $sformatf("\"d\":%h," , t.c ), + // "},"}); + + endfunction : write + + /** + * Empty function. + */ + virtual function void print_header(); + + // Do nothing: JSON files do not use headers. + + endfunction : print_header + +endclass : uvma_clic_mon_trn_logger_json_c + + +`endif // __UVMA_CLIC_MON_TRN_LOGGER_SV__ diff --git a/cv32e40x/tb/uvmt/imperas_iss.flist b/lib/uvm_agents/uvma_clic/uvma_clic_pkg.flist similarity index 69% rename from cv32e40x/tb/uvmt/imperas_iss.flist rename to lib/uvm_agents/uvma_clic/uvma_clic_pkg.flist index 90dfc60f13..b0ec7ee39e 100644 --- a/cv32e40x/tb/uvmt/imperas_iss.flist +++ b/lib/uvm_agents/uvma_clic/uvma_clic_pkg.flist @@ -1,28 +1,26 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// Copyright 2022 Silicon Labs, Inc. +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// -// CV32 test bench files -${TBSRC_HOME}/uvmt/uvmt_cv32e40x_iss_wrap.sv -// Vendor Libraries -+incdir+${DV_OVPM_DESIGN} -${DV_OVPM_DESIGN}/typedefs.sv -${DV_OVPM_DESIGN}/monitor.sv -${DV_OVPM_DESIGN}/ram.sv +// Directories ++incdir+${DV_UVMA_CLIC_PATH} ++incdir+${DV_UVMA_CLIC_PATH}/cov ++incdir+${DV_UVMA_CLIC_PATH}/seq -+incdir+${DV_OVPM_MODEL}/sv -${DV_OVPM_MODEL}/sv/imperas_CV32.sv +// Files +${DV_UVMA_CLIC_PATH}/uvma_clic_pkg.sv diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_pkg.sv b/lib/uvm_agents/uvma_clic/uvma_clic_pkg.sv new file mode 100644 index 0000000000..d8fdeaceea --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_pkg.sv @@ -0,0 +1,71 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_CLIC_PKG_SV__ +`define __UVMA_CLIC_PKG_SV__ + + +// Pre-processor macros +`include "uvm_macros.svh" +`include "uvml_hrtbt_macros.sv" +`include "uvma_clic_macros.sv" + +// Interface(s) / Module(s) / Checker(s) +`include "uvma_clic_if.sv" + +/** + * Encapsulates all the types needed for an UVM agent capable of driving and/or + * monitoring Clock & Reset. + */ +package uvma_clic_pkg; + + import uvm_pkg ::*; + import uvml_hrtbt_pkg::*; + import uvml_trn_pkg ::*; + import uvml_logs_pkg ::*; + + // Constants / Structs / Enums + `include "uvma_clic_constants.sv" + `include "uvma_clic_tdefs.sv" + + // Objects + `include "uvma_clic_cfg.sv" + `include "uvma_clic_cntxt.sv" + + // High-level transactions + `include "uvma_clic_mon_trn.sv" + `include "uvma_clic_mon_trn_logger.sv" + `include "uvma_clic_seq_item.sv" + `include "uvma_clic_seq_item_logger.sv" + + // Agent components + `include "uvma_clic_cov_model.sv" + `include "uvma_clic_drv.sv" + `include "uvma_clic_mon.sv" + `include "uvma_clic_sqr.sv" + `include "uvma_clic_agent.sv" + + // Sequences + `include "uvma_clic_base_seq.sv" + `include "uvma_clic_seq_lib.sv" + +endpackage : uvma_clic_pkg + + +`endif // __UVMA_CLIC_PKG_SV__ diff --git a/lib/uvm_agents/uvma_clic/uvma_clic_sqr.sv b/lib/uvm_agents/uvma_clic/uvma_clic_sqr.sv new file mode 100644 index 0000000000..8be42dd4b1 --- /dev/null +++ b/lib/uvm_agents/uvma_clic/uvma_clic_sqr.sv @@ -0,0 +1,81 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_CLIC_SQR_SV__ +`define __UVMA_CLIC_SQR_SV__ + + +/** + * Component running Clock & Reset sequences extending uvma_clic_seq_base_c. + * Provides sequence items for uvma_clic_drv_c. + */ +class uvma_clic_sqr_c#(CLIC_ID_WIDTH) extends uvm_sequencer#( + .REQ(uvma_clic_seq_item_c), + .RSP(uvma_clic_seq_item_c) +); + + // Objects + uvma_clic_cfg_c cfg; + uvma_clic_cntxt_c#(CLIC_ID_WIDTH) cntxt; + + + `uvm_component_utils_begin(uvma_clic_sqr_c#(CLIC_ID_WIDTH)) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_clic_sqr", uvm_component parent=null); + + /** + * Ensures cfg & cntxt handles are not null + */ + extern virtual function void build_phase(uvm_phase phase); + +endclass : uvma_clic_sqr_c + + +function uvma_clic_sqr_c::new(string name="uvma_clic_sqr", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_clic_sqr_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_clic_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_clic_cntxt_c#(CLIC_ID_WIDTH))::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + +endfunction : build_phase + + +`endif // __UVMA_CLIC_SQR_SV__ diff --git a/cv32e40s/tb/uvmt/imperas_iss.flist b/lib/uvm_agents/uvma_clic/uvma_clic_tdefs.sv similarity index 62% rename from cv32e40s/tb/uvmt/imperas_iss.flist rename to lib/uvm_agents/uvma_clic/uvma_clic_tdefs.sv index 926cad37d7..6da31ea99f 100644 --- a/cv32e40s/tb/uvmt/imperas_iss.flist +++ b/lib/uvm_agents/uvma_clic/uvma_clic_tdefs.sv @@ -1,6 +1,6 @@ -// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation +// Copyright 2022 Silicon Labs, Inc. // // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,16 +13,19 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// -// CV32 test bench files -${TBSRC_HOME}/uvmt/uvmt_cv32e40s_iss_wrap.sv -// Vendor Libraries -+incdir+${DV_OVPM_DESIGN} -${DV_OVPM_DESIGN}/typedefs.sv -${DV_OVPM_DESIGN}/monitor.sv -${DV_OVPM_DESIGN}/ram.sv +`ifndef __UVMA_CLIC_TDEFS_SV__ +`define __UVMA_CLIC_TDEFS_SV__ + +typedef enum { + UVMA_CLIC_SEQ_ITEM_ACTION_ASSERT_UNTIL_ACK, + UVMA_CLIC_SEQ_ITEM_ACTION_ASSERT, + UVMA_CLIC_SEQ_ITEM_ACTION_DEASSERT +} uvma_clic_seq_item_action_enum; + +typedef enum { + UVMA_CLIC_MON_ACTION_IRQ +} uvma_clic_mon_action_enum; -+incdir+${DV_OVPM_MODEL}/sv -${DV_OVPM_MODEL}/sv/imperas_CV32.sv +`endif // __UVMA_CLIC_TDEFS_SV__ diff --git a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_agent.sv b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_agent.sv index 46dfc1b752..e979a2a65b 100644 --- a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_agent.sv +++ b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_agent.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_CLKNRST_AGENT_SV__ @@ -25,11 +25,11 @@ * Capable of driving/monitoring Clock & Reset interface. */ class uvma_clknrst_agent_c extends uvm_agent; - + // Objects uvma_clknrst_cfg_c cfg; uvma_clknrst_cntxt_c cntxt; - + // Components uvma_clknrst_drv_c driver; uvma_clknrst_mon_c monitor; @@ -37,117 +37,117 @@ class uvma_clknrst_agent_c extends uvm_agent; uvma_clknrst_cov_model_c cov_model; uvma_clknrst_seq_item_logger_c seq_item_logger; uvma_clknrst_mon_trn_logger_c mon_trn_logger; - + // TLM uvm_analysis_port#(uvma_clknrst_seq_item_c) drv_ap; uvm_analysis_port#(uvma_clknrst_mon_trn_c ) mon_ap; - - + + `uvm_component_utils_begin(uvma_clknrst_agent_c) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - - + + /** * Default constructor. */ extern function new(string name="uvma_clknrst_agent", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null * 2. Builds all components */ extern virtual function void build_phase(uvm_phase phase); - + /** * 1. Links agent's analysis ports to sub-components' * 2. Connects coverage models and loggers */ extern virtual function void connect_phase(uvm_phase phase); - + /** * Uses uvm_config_db to retrieve cfg and hand out to sub-components. */ extern function void get_and_set_cfg(); - + /** * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. */ extern function void get_and_set_cntxt(); - + /** * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this * agent. */ extern function void retrieve_vif(); - + /** * Creates sub-components. */ extern function void create_components(); - + /** * Connects sequencer and driver's TLM port(s). */ extern function void connect_sequencer_and_driver(); - + /** * Connects agent's TLM ports to driver's and monitor's. */ extern function void connect_analysis_ports(); - + /** * Connects coverage model to monitor and driver's analysis ports. */ extern function void connect_cov_model(); - + /** * Connects transaction loggers to monitor and driver's analysis ports. */ extern function void connect_trn_loggers(); - + endclass : uvma_clknrst_agent_c function uvma_clknrst_agent_c::new(string name="uvma_clknrst_agent", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_clknrst_agent_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + get_and_set_cfg (); get_and_set_cntxt(); retrieve_vif (); create_components(); - + endfunction : build_phase function void uvma_clknrst_agent_c::connect_phase(uvm_phase phase); - + super.connect_phase(phase); - + connect_sequencer_and_driver(); connect_analysis_ports(); - + if (cfg.cov_model_enabled) begin connect_cov_model(); end if (cfg.trn_log_enabled) begin connect_trn_loggers(); end - + endfunction: connect_phase function void uvma_clknrst_agent_c::get_and_set_cfg(); - + void'(uvm_config_db#(uvma_clknrst_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") @@ -156,75 +156,75 @@ function void uvma_clknrst_agent_c::get_and_set_cfg(); `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) uvm_config_db#(uvma_clknrst_cfg_c)::set(this, "*", "cfg", cfg); end - + endfunction : get_and_set_cfg function void uvma_clknrst_agent_c::get_and_set_cntxt(); - + void'(uvm_config_db#(uvma_clknrst_cntxt_c)::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) cntxt = uvma_clknrst_cntxt_c::type_id::create("cntxt"); end uvm_config_db#(uvma_clknrst_cntxt_c)::set(this, "*", "cntxt", cntxt); - + endfunction : get_and_set_cntxt function void uvma_clknrst_agent_c::retrieve_vif(); - - if (!uvm_config_db#(virtual uvma_clknrst_if)::get(this, "", "vif", cntxt.vif)) begin + + if (!uvm_config_db#(virtual uvma_clknrst_if_t)::get(this, "", "vif", cntxt.vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.vif))) end else begin `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", $typename(cntxt.vif)), UVM_DEBUG) end - + endfunction : retrieve_vif function void uvma_clknrst_agent_c::create_components(); - + monitor = uvma_clknrst_mon_c ::type_id::create("monitor" , this); sequencer = uvma_clknrst_sqr_c ::type_id::create("sequencer" , this); driver = uvma_clknrst_drv_c ::type_id::create("driver" , this); cov_model = uvma_clknrst_cov_model_c ::type_id::create("cov_model" , this); mon_trn_logger = uvma_clknrst_mon_trn_logger_c ::type_id::create("mon_trn_logger" , this); seq_item_logger = uvma_clknrst_seq_item_logger_c::type_id::create("seq_item_logger", this); - + endfunction : create_components function void uvma_clknrst_agent_c::connect_sequencer_and_driver(); - + //sequencer.set_arbitration(cfg.sqr_arb_mode); driver.seq_item_port.connect(sequencer.seq_item_export); - + endfunction : connect_sequencer_and_driver function void uvma_clknrst_agent_c::connect_analysis_ports(); - + drv_ap = driver .ap; mon_ap = monitor.ap; - + endfunction : connect_analysis_ports function void uvma_clknrst_agent_c::connect_cov_model(); - + mon_ap.connect(cov_model.mon_trn_fifo .analysis_export); drv_ap.connect(cov_model.seq_item_fifo.analysis_export); - + endfunction : connect_cov_model function void uvma_clknrst_agent_c::connect_trn_loggers(); - + mon_ap.connect(mon_trn_logger .analysis_export); drv_ap.connect(seq_item_logger.analysis_export); - + endfunction : connect_trn_loggers diff --git a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_cntxt.sv b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_cntxt.sv index 43e1d219b2..00b078240c 100644 --- a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_cntxt.sv +++ b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_cntxt.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_CLKNRST_CNTXT_SV__ @@ -25,77 +25,77 @@ * (uvma_clknrst_agent_c) components. */ class uvma_clknrst_cntxt_c extends uvm_object; - + // Handle to agent interface - virtual uvma_clknrst_if vif; - + virtual uvma_clknrst_if_t vif; + // Clock Monitoring bit mon_clk_lock ; ///< Indicates that we have achieved clock lock realtime mon_clk_period ; ///< Sampled clock period logic mon_clk_last_val ; ///< Last clock value sampled realtime mon_clk_last_edge ; ///< Timestamp of last clock edge int unsigned mon_clk_cycle_count; ///< Number of good clock cycles - + // Reset Monitoring logic mon_reset_state ; ///< Last reset edge realtime mon_reset_assert_timestamp; ///< Reset assertion edge timestamp - + // Events uvm_event sample_cfg_e ; ///< Event to trigger functional coverage sampling of cfg uvm_event sample_cntxt_e; ///< Event to trigger functional coverage sampling of cntxt - - + + `uvm_object_utils_begin(uvma_clknrst_cntxt_c) `uvm_field_event(sample_cfg_e , UVM_DEFAULT) `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) - + `uvm_field_int (mon_clk_lock , UVM_DEFAULT ) `uvm_field_real(mon_clk_period , UVM_DEFAULT ) `uvm_field_int (mon_clk_last_val , UVM_DEFAULT ) `uvm_field_real(mon_clk_last_edge , UVM_DEFAULT ) `uvm_field_int (mon_clk_cycle_count, UVM_DEFAULT + UVM_DEC) - + `uvm_field_int (mon_reset_state , UVM_DEFAULT) `uvm_field_real(mon_reset_assert_timestamp, UVM_DEFAULT) `uvm_object_utils_end - - + + /** * Builds events. */ extern function new(string name="uvma_clknrst_cntxt"); - + /** * Resets integrals to their default values. */ extern function void reset(); - + endclass : uvma_clknrst_cntxt_c function uvma_clknrst_cntxt_c::new(string name="uvma_clknrst_cntxt"); - + super.new(name); - + sample_cfg_e = new("sample_cfg_e" ); sample_cntxt_e = new("sample_cntxt_e"); - + reset(); - + endfunction : new function void uvma_clknrst_cntxt_c::reset(); - + mon_clk_lock = 0; mon_clk_period = 0; mon_clk_last_val = 'X; mon_clk_last_edge = 0; mon_clk_cycle_count = 0; - + mon_reset_state = 0; mon_reset_assert_timestamp = 0; - + endfunction : reset diff --git a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_drv.sv b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_drv.sv index 3ada4ad43d..2acf1afcd7 100644 --- a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_drv.sv +++ b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_drv.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_CLKNRST_DRV_SV__ @@ -21,87 +21,87 @@ /** - * Component driving a Clock & Reset virtual interface (uvma_clknrst_if). + * Component driving a Clock & Reset virtual interface (uvma_clknrst_if_t). */ class uvma_clknrst_drv_c extends uvm_driver#( .REQ(uvma_clknrst_seq_item_c), .RSP(uvma_clknrst_seq_item_c) ); - + // Objects uvma_clknrst_cfg_c cfg; uvma_clknrst_cntxt_c cntxt; - + // TLM uvm_analysis_port#(uvma_clknrst_seq_item_c) ap; - - + + `uvm_component_utils_begin(uvma_clknrst_drv_c) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - - + + /** * Default constructor. */ extern function new(string name="uvma_clknrst_drv", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null. * 2. Builds ap. */ extern virtual function void build_phase(uvm_phase phase); - + /** * Obtains the reqs from the sequence item port and calls drv_req() */ extern virtual task run_phase(uvm_phase phase); - + /** * Drives the virtual interface's (cntxt.vif) signals using req's contents. */ extern task drv_req(uvma_clknrst_seq_item_c req); - + endclass : uvma_clknrst_drv_c function uvma_clknrst_drv_c::new(string name="uvma_clknrst_drv", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_clknrst_drv_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + void'(uvm_config_db#(uvma_clknrst_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") end uvm_config_db#(uvma_clknrst_cfg_c)::set(this, "*", "cfg", cfg); - + void'(uvm_config_db#(uvma_clknrst_cntxt_c)::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_fatal("CNTXT", "Context handle is null") end uvm_config_db#(uvma_clknrst_cntxt_c)::set(this, "*", "cntxt", cntxt); - + ap = new("ap", this); - + endfunction : build_phase task uvma_clknrst_drv_c::run_phase(uvm_phase phase); - + super.run_phase(phase); - + case (cfg.drv_initial_rst_value) UVMA_CLKNRST_SEQ_ITEM_INITIAL_VALUE_1: cntxt.vif.reset_n = '1; UVMA_CLKNRST_SEQ_ITEM_INITIAL_VALUE_X: cntxt.vif.reset_n = 'X; - + default: begin `uvm_error("CLKNRST", $sformatf("Illegal cfg.initial_value: %s", cfg.drv_initial_rst_value)) end @@ -114,12 +114,12 @@ task uvma_clknrst_drv_c::run_phase(uvm_phase phase); ap.write(req); seq_item_port.item_done(); end - + endtask : run_phase task uvma_clknrst_drv_c::drv_req(uvma_clknrst_seq_item_c req); - + case (req.action) UVMA_CLKNRST_SEQ_ITEM_ACTION_START_CLK: begin if (cntxt.vif.clk_active) begin @@ -137,7 +137,7 @@ task uvma_clknrst_drv_c::drv_req(uvma_clknrst_seq_item_c req); cntxt.vif.start_clk(); end end - + UVMA_CLKNRST_SEQ_ITEM_ACTION_STOP_CLK: begin if (!cntxt.vif.clk_active) begin `uvm_warning("CLKNRST", {"Attempting to stop clock generation while it is already inactive. Ignoring req:\n", req.sprint()}) @@ -165,7 +165,7 @@ task uvma_clknrst_drv_c::drv_req(uvma_clknrst_seq_item_c req); cntxt.vif.reset_n = '1; end endcase - + endtask : drv_req diff --git a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if.sv b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if.sv index 29821279cc..fd9cfd0f3e 100644 --- a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if.sv +++ b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_CLKNRST_IF_SV__ @@ -21,22 +21,22 @@ /** - * Encapsulates all signals of the Clock & Reset interface. Used by monitor + * Encapsulates all signals of the Clock & Reset interface. Used by monitor * (uvma_clknrst_mon_c) and driver (uvma_clknrst_drv_c). */ -interface uvma_clknrst_if (); +interface uvma_clknrst_if_t (); import uvm_pkg::*; - + // Signals logic clk ; logic reset_n; - + // Control fields realtime clk_period ; bit clk_active = 0; - - + + /** * Clock generation loop */ @@ -53,9 +53,9 @@ interface uvma_clknrst_if (); end end end - + always @* begin - if (clk_active && clk_period == 0.0) + if (clk_active && clk_period == 0.0) `uvm_fatal("CLKNRSTIF", $sformatf("%m: Clock is active with 0 period")) end /** @@ -65,7 +65,7 @@ interface uvma_clknrst_if (); `uvm_info("CLKNRST", $sformatf("Changing clock period to %0t", new_clk_period), UVM_LOW) clk_period = new_clk_period; endfunction : set_period - + /** * Sets clk_active to 1 */ @@ -73,7 +73,7 @@ interface uvma_clknrst_if (); `uvm_info("CLKNRST", "Starting clock generation", UVM_HIGH) if (clk_period) clk_active = 1; endfunction : start_clk - + /** * Sets clk_active to 0 */ @@ -81,8 +81,8 @@ interface uvma_clknrst_if (); `uvm_info("CLKNRST", "Stopping clock generation", UVM_HIGH) clk_active = 0; endfunction : stop_clk - -endinterface : uvma_clknrst_if + +endinterface : uvma_clknrst_if_t `endif // __UVMA_CLKNRST_IF_SV__ diff --git a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if_chk.sv b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if_chk.sv index 49fdd0649a..366d5ee57c 100644 --- a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if_chk.sv +++ b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_if_chk.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_CLKNRST_IF_CHK_SV__ @@ -24,11 +24,11 @@ * Encapsulates assertions targeting uvma_clknrst_if. */ module uvma_clknrst_if_chk( - uvma_clknrst_if clknrst_if + uvma_clknrst_if_t clknrst_if ); - + // TODO Add assertions to uvma_clknrst_if_chk - + endmodule : uvma_clknrst_if_chk diff --git a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_mon.sv b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_mon.sv index be6ad90777..26412b75fb 100644 --- a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_mon.sv +++ b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_mon.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_CLKNRST_MON_SV__ @@ -22,102 +22,102 @@ /** * Component sampling transactions from a Clock & Reset virtual interface - * (uvma_clknrst_if). + * (uvma_clknrst_if_t). */ class uvma_clknrst_mon_c extends uvm_monitor; - + // Objects uvma_clknrst_cfg_c cfg; uvma_clknrst_cntxt_c cntxt; - + // TLM uvm_analysis_port#(uvma_clknrst_mon_trn_c) ap; - - + + `uvm_component_utils_begin(uvma_clknrst_mon_c) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - - + + /** * Default constructor. */ extern function new(string name="uvma_clknrst_mon", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null. * 2. Builds ap. */ extern virtual function void build_phase(uvm_phase phase); - + /** * Oversees monitoring via monitor_clk() and monitor_reset() tasks in parallel * forks. */ extern virtual task run_phase(uvm_phase phase); - + /** * Creates trn by sampling the virtual interface's (cntxt.vif) clk signal. */ extern task monitor_clk(output uvma_clknrst_mon_trn_c trn); - + /** * Creates trn by sampling the virtual interface's (cntxt.vif) reset_n signal. */ extern task monitor_reset(output uvma_clknrst_mon_trn_c trn); - + /** * Empty, classes extending this monitor can do their intercept here. */ extern function void process_trn(ref uvma_clknrst_mon_trn_c trn); - + /** * Monitors clock signal for loss of clock, generating a transaction only if * and when this is detected. */ extern task monitor_clock_loss(output uvma_clknrst_mon_trn_c trn); - + /** * Emits a transaction once clock lock has been achieved. */ extern task lock_to_clock(output uvma_clknrst_mon_trn_c trn); - + endclass : uvma_clknrst_mon_c function uvma_clknrst_mon_c::new(string name="uvma_clknrst_mon", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_clknrst_mon_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + void'(uvm_config_db#(uvma_clknrst_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") end - + void'(uvm_config_db#(uvma_clknrst_cntxt_c)::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_fatal("CNTXT", "Context handle is null") end - + ap = new("ap", this); - + endfunction : build_phase task uvma_clknrst_mon_c::run_phase(uvm_phase phase); - + uvma_clknrst_mon_trn_c clk_trn, reset_trn; - + super.run_phase(phase); - + if (cfg.enabled) begin fork begin : clk @@ -128,7 +128,7 @@ task uvma_clknrst_mon_c::run_phase(uvm_phase phase); ap.write (clk_trn); end end - + begin : reset forever begin monitor_reset(reset_trn); @@ -139,28 +139,28 @@ task uvma_clknrst_mon_c::run_phase(uvm_phase phase); end join_none end - + endtask : run_phase task uvma_clknrst_mon_c::monitor_clk(output uvma_clknrst_mon_trn_c trn); - + if (cntxt.mon_clk_lock) begin monitor_clock_loss(trn); end else begin lock_to_clock(trn); end - + endtask : monitor_clk task uvma_clknrst_mon_c::monitor_reset(output uvma_clknrst_mon_trn_c trn); - + bit sampled_trn = 0; - + trn = uvma_clknrst_mon_trn_c::type_id::create("trn"); - + do begin @(cntxt.vif.reset_n); if (cntxt.vif.reset_n !== cntxt.mon_reset_state) begin @@ -173,7 +173,7 @@ task uvma_clknrst_mon_c::monitor_reset(output uvma_clknrst_mon_trn_c trn); trn.__timestamp_start = $realtime(); sampled_trn = 1; end - + // 0 -> 1 2'b01: begin trn.reset_pulse_length = $realtime() - cntxt.mon_reset_assert_timestamp; @@ -182,7 +182,7 @@ task uvma_clknrst_mon_c::monitor_reset(output uvma_clknrst_mon_trn_c trn); trn.__timestamp_end = $realtime(); sampled_trn = 1; end - + 2'bX0: begin cntxt.mon_reset_assert_timestamp = $realtime(); trn.event_type = UVMA_CLKNRST_MON_TRN_EVENT_RESET_ASSERTED; @@ -191,42 +191,42 @@ task uvma_clknrst_mon_c::monitor_reset(output uvma_clknrst_mon_trn_c trn); sampled_trn = 1; end endcase - + cntxt.mon_reset_state = cntxt.vif.reset_n; end end while (!sampled_trn); - + endtask : monitor_reset function void uvma_clknrst_mon_c::process_trn(ref uvma_clknrst_mon_trn_c trn); - + // Empty - + endfunction : process_trn task uvma_clknrst_mon_c::monitor_clock_loss(output uvma_clknrst_mon_trn_c trn); - + trn = uvma_clknrst_mon_trn_c::type_id::create("trn"); - + forever begin @(cntxt.vif.clk); // TODO Implement uvma_clknrst_mon_c::monitor_clock_loss() end - + endtask : monitor_clock_loss task uvma_clknrst_mon_c::lock_to_clock(output uvma_clknrst_mon_trn_c trn); - + trn = uvma_clknrst_mon_trn_c::type_id::create("trn"); - + forever begin @(cntxt.vif.clk); // TODO Implement uvma_clknrst_mon_c::lock_to_clock() end - + endtask : lock_to_clock diff --git a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_pkg.sv b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_pkg.sv index f6c9f61b49..5e2c49efea 100644 --- a/lib/uvm_agents/uvma_clknrst/uvma_clknrst_pkg.sv +++ b/lib/uvm_agents/uvma_clknrst/uvma_clknrst_pkg.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_CLKNRST_PKG_SV__ @@ -37,39 +37,39 @@ * monitoring Clock & Reset. */ package uvma_clknrst_pkg; - + import uvm_pkg ::*; import uvml_hrtbt_pkg::*; import uvml_trn_pkg ::*; import uvml_logs_pkg ::*; - + // Constants / Structs / Enums `include "uvma_clknrst_constants.sv" `include "uvma_clknrst_tdefs.sv" - + // Objects `include "uvma_clknrst_cfg.sv" `include "uvma_clknrst_cntxt.sv" - + // High-level transactions `include "uvma_clknrst_mon_trn.sv" `include "uvma_clknrst_mon_trn_logger.sv" `include "uvma_clknrst_seq_item.sv" `include "uvma_clknrst_seq_item_logger.sv" - + // Agent components `include "uvma_clknrst_cov_model.sv" `include "uvma_clknrst_drv.sv" `include "uvma_clknrst_mon.sv" `include "uvma_clknrst_sqr.sv" `include "uvma_clknrst_agent.sv" - + // Sequences `include "uvma_clknrst_base_seq.sv" `include "uvma_clknrst_stop_clk_seq.sv" `include "uvma_clknrst_restart_clk_seq.sv" `include "uvma_clknrst_seq_lib.sv" - + endpackage : uvma_clknrst_pkg diff --git a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv index afb160d1d9..b831b64a8c 100644 --- a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv +++ b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv @@ -39,8 +39,12 @@ // ISS configuration bit use_iss; + int iss_suppress_invalid_msg = 0; string iss_control_file = "ovpsim.ic"; + // Controls printing of CSR status + bit csr_print; + // RISC-V ISA Configuration rand corev_mxl_t xlen; rand int unsigned ilen; @@ -63,21 +67,32 @@ rand bit ext_zbr_supported; rand bit ext_zbs_supported; rand bit ext_zbt_supported; + rand bit ext_zca_supported; + rand bit ext_zcb_supported; + rand bit ext_zcmb_supported; + rand bit ext_zcmp_supported; + rand bit ext_zcmt_supported; rand bit ext_zifencei_supported; rand bit ext_zicsr_supported; + rand bit ext_nonstd_supported; rand bit mode_s_supported; + rand bit mode_h_supported; rand bit mode_u_supported; rand bit pmp_supported; rand bit debug_supported; rand bitmanip_version_t bitmanip_version; - + rand debug_spec_version_t debug_spec_version; rand priv_spec_version_t priv_spec_version; rand endianness_t endianness; + rand int unsigned clic_levels; + bit clic_interrupt_enable = 0; + bit basic_interrupt_enable = 1; + rand bit unaligned_access_supported; rand bit unaligned_access_amo_supported; @@ -97,6 +112,9 @@ rand bit [MAX_XLEN-1:0] mimpid; bit mimpid_plusarg_valid; + rand bit [MAX_XLEN-1:0] mimpid_patch; + bit mimpid_patch_plusarg_valid; + rand bit [MAX_XLEN-1:0] boot_addr; rand bit boot_addr_valid; bit boot_addr_plusarg_valid; @@ -147,7 +165,13 @@ `uvm_field_int( ext_zbr_supported , UVM_DEFAULT ) `uvm_field_int( ext_zbs_supported , UVM_DEFAULT ) `uvm_field_int( ext_zbt_supported , UVM_DEFAULT ) + `uvm_field_int( ext_zca_supported , UVM_DEFAULT ) + `uvm_field_int( ext_zcb_supported , UVM_DEFAULT ) + `uvm_field_int( ext_zcmb_supported , UVM_DEFAULT ) + `uvm_field_int( ext_zcmp_supported , UVM_DEFAULT ) + `uvm_field_int( ext_zcmt_supported , UVM_DEFAULT ) `uvm_field_int( mode_s_supported , UVM_DEFAULT ) + `uvm_field_int( mode_h_supported , UVM_DEFAULT ) `uvm_field_int( mode_u_supported , UVM_DEFAULT ) `uvm_field_int( pmp_supported , UVM_DEFAULT ) `uvm_field_int( debug_supported , UVM_DEFAULT ) @@ -155,11 +179,14 @@ `uvm_field_int( unaligned_access_amo_supported , UVM_DEFAULT ) `uvm_field_enum(bitmanip_version_t, bitmanip_version , UVM_DEFAULT ) `uvm_field_enum(priv_spec_version_t, priv_spec_version , UVM_DEFAULT ) + `uvm_field_enum(debug_spec_version_t, debug_spec_version , UVM_DEFAULT ) `uvm_field_enum(endianness_t, endianness , UVM_DEFAULT ) + `uvm_field_int( clic_levels , UVM_DEFAULT ) `uvm_field_int( num_mhpmcounters , UVM_DEFAULT ) `uvm_field_array_object( pma_regions , UVM_DEFAULT ) `uvm_field_int( mhartid , UVM_DEFAULT ) `uvm_field_int( mimpid , UVM_DEFAULT ) + `uvm_field_int( mimpid_patch , UVM_DEFAULT ) `uvm_field_int( boot_addr , UVM_DEFAULT ) `uvm_field_int( boot_addr_valid , UVM_DEFAULT ) `uvm_field_int( boot_addr_plusarg_valid , UVM_DEFAULT ) @@ -175,18 +202,39 @@ `uvm_field_int( nmi_addr , UVM_DEFAULT ) `uvm_field_int( nmi_addr_valid , UVM_DEFAULT ) `uvm_field_int( nmi_addr_plusarg_valid , UVM_DEFAULT ) + `uvm_field_int( csr_print , UVM_DEFAULT ) `uvm_field_utils_end constraint defaults_cons { - soft enabled == 0; - soft is_active == UVM_PASSIVE; - soft cov_model_enabled == 1; - soft trn_log_enabled == 1; + soft enabled == 0; + soft is_active == UVM_PASSIVE; + soft cov_model_enabled == 1; + soft trn_log_enabled == 1; + soft ext_nonstd_supported == 0; } constraint riscv_cons_soft { - soft priv_spec_version == PRIV_VERSION_1_11; - soft endianness == ENDIAN_LITTLE; + soft priv_spec_version == PRIV_VERSION_1_11; + soft debug_spec_version == DEBUG_VERSION_0_13_2; + soft endianness == ENDIAN_LITTLE; + soft mode_h_supported == 0; + soft ext_nonstd_supported == 0; + soft clic_levels == 0; + soft ext_zba_supported == 0; + soft ext_zbb_supported == 0; + soft ext_zbc_supported == 0; + soft ext_zbs_supported == 0; + soft ext_zbe_supported == 0; + soft ext_zbf_supported == 0; + soft ext_zbm_supported == 0; + soft ext_zbp_supported == 0; + soft ext_zbr_supported == 0; + soft ext_zbt_supported == 0; + soft ext_zca_supported == 0; + soft ext_zcb_supported == 0; + soft ext_zcmb_supported == 0; + soft ext_zcmp_supported == 0; + soft ext_zcmt_supported == 0; } constraint addr_xlen_align_cons { @@ -281,12 +329,27 @@ function uvma_core_cntrl_cfg_c::new(string name="uvme_cv_base_cfg"); if ($test$plusargs("USE_ISS")) use_iss = 1; + if ($test$plusargs("no_csr_print")) begin + csr_print = 0; + end else begin + csr_print = 1; + end + + if ($test$plusargs("iss_suppress_invalid_msg")) begin + iss_suppress_invalid_msg = 1; + end + // Read plusargs for defaults if (read_cfg_plusarg_xlen("mhartid", mhartid)) begin mhartid_plusarg_valid = 1; mhartid.rand_mode(0); end + if (read_cfg_plusarg_xlen("mimpid_patch", mimpid_patch)) begin + mimpid_patch_plusarg_valid = 1; + mimpid_patch.rand_mode(0); + end + if (read_cfg_plusarg_xlen("mimpid", mimpid)) begin mimpid_plusarg_valid = 1; mimpid.rand_mode(0); @@ -352,26 +415,27 @@ function void uvma_core_cntrl_cfg_c::do_print(uvm_printer printer); super.do_print(printer); - // Print out CSRs that are supported - printer.print_string("-----------------------------", "--------------------------------------------------------------------"); - begin - instr_csr_t csr; - - csr = csr.first(); - while (1) begin - if (unsupported_csr_mask[csr]) - printer.print_string(csr.name(), "Unsupported"); - else if (disable_all_csr_checks || disable_csr_check_mask[csr]) - printer.print_string(csr.name(), "Supported but not checked in scoreboard"); - else - printer.print_string(csr.name(), "Supported and checked in scoreboard"); - - if (csr == csr.last()) break; - csr = csr.next(); + if (csr_print) begin + // Print out CSRs that are supported + printer.print_string("-----------------------------", "--------------------------------------------------------------------"); + begin + instr_csr_t csr; + + csr = csr.first(); + while (1) begin + if (unsupported_csr_mask[csr]) + printer.print_string(csr.name(), "Unsupported"); + else if (disable_all_csr_checks || disable_csr_check_mask[csr]) + printer.print_string(csr.name(), "Supported but not checked in scoreboard"); + else + printer.print_string(csr.name(), "Supported and checked in scoreboard"); + + if (csr == csr.last()) break; + csr = csr.next(); + end end + printer.print_string("-----------------------------", "--------------------------------------------------------------------"); end - printer.print_string("-----------------------------", "--------------------------------------------------------------------"); - endfunction : do_print function void uvma_core_cntrl_cfg_c::set_unsupported_csr_mask(); @@ -391,7 +455,7 @@ function void uvma_core_cntrl_cfg_c::set_unsupported_csr_mask(); end end - // Remove S-mode CSRs is S mode not supported + // Remove S-mode CSRs if S mode not supported if (!mode_s_supported) begin unsupported_csr_mask[SSTATUS] = 1; unsupported_csr_mask[SEDELEG] = 1; @@ -405,13 +469,16 @@ function void uvma_core_cntrl_cfg_c::set_unsupported_csr_mask(); unsupported_csr_mask[STVAL] = 1; unsupported_csr_mask[SIP] = 1; unsupported_csr_mask[SATP] = 1; + if (debug_spec_version == DEBUG_VERSION_1_0_0) begin + unsupported_csr_mask[SCONTEXT] = 1; + end unsupported_csr_mask[MEDELEG] = 1; unsupported_csr_mask[MIDELEG] = 1; unsupported_csr_mask[MCOUNTEREN] = 1; end - // Remove U-mode CSRs is S mode not supported + // Remove U-mode CSRs if S mode not supported if (!mode_u_supported) begin unsupported_csr_mask[USTATUS] = 1; unsupported_csr_mask[UIE] = 1; @@ -466,7 +533,7 @@ function void uvma_core_cntrl_cfg_c::set_unsupported_csr_mask(); unsupported_csr_mask[PMPCFG1] = 1; unsupported_csr_mask[PMPCFG2] = 1; unsupported_csr_mask[PMPCFG3] = 1; - if (priv_spec_version == PRIV_VERSION_MASTER) begin + if (priv_spec_version == PRIV_VERSION_1_12) begin unsupported_csr_mask[PMPCFG4] = 1; unsupported_csr_mask[PMPCFG5] = 1; unsupported_csr_mask[PMPCFG6] = 1; @@ -496,7 +563,7 @@ function void uvma_core_cntrl_cfg_c::set_unsupported_csr_mask(); unsupported_csr_mask[PMPADDR13] = 1; unsupported_csr_mask[PMPADDR14] = 1; unsupported_csr_mask[PMPADDR15] = 1; - if (priv_spec_version == PRIV_VERSION_MASTER) begin + if (priv_spec_version == PRIV_VERSION_1_12) begin unsupported_csr_mask[PMPADDR16] = 1; unsupported_csr_mask[PMPADDR17] = 1; unsupported_csr_mask[PMPADDR18] = 1; @@ -565,11 +632,20 @@ function void uvma_core_cntrl_cfg_c::set_unsupported_csr_mask(); unsupported_csr_mask[MHPMCOUNTER3H+i] = 1; end - if (priv_spec_version != PRIV_VERSION_MASTER) begin + if (priv_spec_version != PRIV_VERSION_1_12) begin unsupported_csr_mask[MSTATUSH] = 1; unsupported_csr_mask[MCONFIGPTR] = 1; end + // Remove support for hcontext alias (mcontext) + // when hypervisor mode is not supported + if (priv_spec_version == PRIV_VERSION_1_12 && + debug_spec_version == DEBUG_VERSION_1_0_0 && + mode_h_supported == 0) + begin + unsupported_csr_mask[MCONTEXT] = 1; + end + // TODO: These needs inclusion parameter classification unsupported_csr_mask[MSECCFG] = 1; unsupported_csr_mask[MSECCFGH] = 1; @@ -671,6 +747,7 @@ function bit[MAX_XLEN-1:0] uvma_core_cntrl_cfg_c::get_misa(); if (ext_m_supported) get_misa[12] = 1; if (mode_s_supported) get_misa[18] = 1; if (mode_u_supported) get_misa[20] = 1; + if (ext_nonstd_supported) get_misa[23] = 1; endfunction : get_misa diff --git a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_pma_region.sv b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_pma_region.sv index 67fc77fd37..f2ee15c1fd 100644 --- a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_pma_region.sv +++ b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_pma_region.sv @@ -48,6 +48,9 @@ // Does this memory support atomics rand bit atomic; + // Does this memory support integrity + rand bit integrity; + `uvm_object_utils_begin(uvma_core_cntrl_pma_region_c); `uvm_field_enum(corev_mxl_t, xlen , UVM_DEFAULT | UVM_NOPRINT) `uvm_field_int( word_addr_low , UVM_DEFAULT | UVM_NOPRINT) @@ -56,6 +59,7 @@ `uvm_field_int( bufferable , UVM_DEFAULT | UVM_NOPRINT) `uvm_field_int( cacheable , UVM_DEFAULT | UVM_NOPRINT) `uvm_field_int( atomic , UVM_DEFAULT | UVM_NOPRINT) + `uvm_field_int( integrity , UVM_DEFAULT | UVM_NOPRINT) `uvm_field_utils_end constraint addr_range_cons { @@ -85,7 +89,7 @@ /** * Simple lookup if address is in region */ - extern function bit is_addr_in_region(bit [MAX_XLEN-1:0] byte_addr); + extern function bit is_addr_in_region(bit [MAX_XLEN-1:0] byte_addr, bit include_upper_word_address = 0); /** * Convert word address to byte address @@ -111,15 +115,24 @@ function void uvma_core_cntrl_pma_region_c::do_print(uvm_printer printer); printer.print_field("bufferable", bufferable, 1); printer.print_field("cacheable", cacheable, 1); printer.print_field("atomic", atomic, 1); + printer.print_field("integrity", integrity, 1); endfunction : do_print -function bit uvma_core_cntrl_pma_region_c::is_addr_in_region(bit [MAX_XLEN-1:0] byte_addr); +function bit uvma_core_cntrl_pma_region_c::is_addr_in_region(bit [MAX_XLEN-1:0] byte_addr, bit include_upper_word_address = 0); // Per User manual, do not include the upper word address - if (((byte_addr >> 2) >= word_addr_low) && - ((byte_addr >> 2) < word_addr_high)) - return 1; + if (!include_upper_word_address) begin + if (((byte_addr >> 2) >= word_addr_low) && + ((byte_addr >> 2) < word_addr_high)) begin + return 1; + end + end else begin + if (((byte_addr >> 2) >= word_addr_low) && + ((byte_addr >> 2) <= word_addr_high)) begin + return 1; + end + end return 0; diff --git a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv index 527a1d72a3..912f1cae2b 100644 --- a/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv +++ b/lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -651,12 +651,20 @@ typedef enum { } bitmanip_version_t; typedef enum { + PRIV_VERSION_1_12, PRIV_VERSION_1_11, PRIV_VERSION_1_10, PRIV_VERSION_20190405, PRIV_VERSION_MASTER } priv_spec_version_t; +typedef enum { + DEBUG_VERSION_1_0_0, + DEBUG_VERSION_0_14_0, + DEBUG_VERSION_0_13_2, + DEBUG_VERSION_UNDEFINED +} debug_spec_version_t; + typedef enum { ENDIAN_LITTLE, ENDIAN_BIG, diff --git a/lib/uvm_agents/uvma_debug/seq/uvma_debug_seq_item.sv b/lib/uvm_agents/uvma_debug/seq/uvma_debug_seq_item.sv index c324b93999..bb0d73382f 100644 --- a/lib/uvm_agents/uvma_debug/seq/uvma_debug_seq_item.sv +++ b/lib/uvm_agents/uvma_debug/seq/uvma_debug_seq_item.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,29 +23,29 @@ * Object created by Debug agent sequences extending uvma_debug_seq_base_c. */ class uvma_debug_seq_item_c extends uvml_trn_seq_item_c; - - bit debug_req; + + bit debug_req; rand int unsigned active_cycles; - + `uvm_object_utils_begin(uvma_debug_seq_item_c) `uvm_field_int(debug_req, UVM_DEFAULT) `uvm_field_int(active_cycles, UVM_DEFAULT) `uvm_object_utils_end - - + + // TODO Add uvma_debug_seq_item_c constraints // Ex: constraint default_cons { // abc inside {0,2,4,8,16,32}; // } constraint active_cons { - active_cycles > 0 && active_cycles < 100; + soft active_cycles > 0 && active_cycles < 100; } - + /** * Default constructor. */ extern function new(string name="uvma_debug_seq_item"); - + endclass : uvma_debug_seq_item_c @@ -53,9 +53,9 @@ endclass : uvma_debug_seq_item_c function uvma_debug_seq_item_c::new(string name="uvma_debug_seq_item"); - + super.new(name); - + endfunction : new diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_agent.sv b/lib/uvm_agents/uvma_debug/uvma_debug_agent.sv index 99762d9d6e..af87e63eaf 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_agent.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_agent.sv @@ -1,12 +1,12 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,11 +23,11 @@ * Capable of driving/monitoring Debug interface. */ class uvma_debug_agent_c extends uvm_agent; - + // Objects uvma_debug_cfg_c cfg; uvma_debug_cntxt_c cntxt; - + // Components uvma_debug_drv_c driver; uvma_debug_mon_c monitor; @@ -35,76 +35,76 @@ class uvma_debug_agent_c extends uvm_agent; uvma_debug_cov_model_c cov_model; uvma_debug_seq_item_logger_c seq_item_logger; uvma_debug_mon_trn_logger_c mon_trn_logger; - + // TLM uvm_analysis_port#(uvma_debug_seq_item_c) drv_ap; uvm_analysis_port#(uvma_debug_mon_trn_c ) mon_ap; - - + + `uvm_component_utils_begin(uvma_debug_agent_c) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - - + + /** * Default constructor. */ extern function new(string name="uvma_debug_agent", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null * 2. Builds all components */ extern virtual function void build_phase(uvm_phase phase); - + /** * 1. Links agent's analysis ports to sub-components' * 2. Connects coverage models and loggers */ extern virtual function void connect_phase(uvm_phase phase); - + /** * Uses uvm_config_db to retrieve cfg and hand out to sub-components. */ extern function void get_and_set_cfg(); - + /** * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. */ extern function void get_and_set_cntxt(); - + /** * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this * agent. */ extern function void retrieve_vif(); - + /** * Creates sub-components. */ extern function void create_components(); - + /** * Connects sequencer and driver's TLM port(s). */ extern function void connect_sequencer_and_driver(); - + /** * Connects agent's TLM ports to driver's and monitor's. */ extern function void connect_analysis_ports(); - + /** * Connects coverage model to monitor and driver's analysis ports. */ extern function void connect_cov_model(); - + /** * Connects transaction loggers to monitor and driver's analysis ports. */ extern function void connect_trn_loggers(); - + endclass : uvma_debug_agent_c @@ -112,43 +112,43 @@ endclass : uvma_debug_agent_c function uvma_debug_agent_c::new(string name="uvma_debug_agent", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_debug_agent_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + get_and_set_cfg (); get_and_set_cntxt(); retrieve_vif (); create_components(); - + endfunction : build_phase function void uvma_debug_agent_c::connect_phase(uvm_phase phase); - + super.connect_phase(phase); - + connect_sequencer_and_driver(); connect_analysis_ports(); - + if (cfg.cov_model_enabled) begin connect_cov_model(); end if (cfg.trn_log_enabled) begin connect_trn_loggers(); end - + endfunction: connect_phase function void uvma_debug_agent_c::get_and_set_cfg(); - + void'(uvm_config_db#(uvma_debug_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") @@ -157,75 +157,75 @@ function void uvma_debug_agent_c::get_and_set_cfg(); `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) uvm_config_db#(uvma_debug_cfg_c)::set(this, "*", "cfg", cfg); end - + endfunction : get_and_set_cfg function void uvma_debug_agent_c::get_and_set_cntxt(); - + void'(uvm_config_db#(uvma_debug_cntxt_c)::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) cntxt = uvma_debug_cntxt_c::type_id::create("cntxt"); end uvm_config_db#(uvma_debug_cntxt_c)::set(this, "*", "cntxt", cntxt); - + endfunction : get_and_set_cntxt function void uvma_debug_agent_c::retrieve_vif(); - - if (!uvm_config_db#(virtual uvma_debug_if)::get(this, "", "vif", cntxt.vif)) begin + + if (!uvm_config_db#(virtual uvma_debug_if_t)::get(this, "", "vif", cntxt.vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.vif))) end else begin `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", $typename(cntxt.vif)), UVM_DEBUG) end - + endfunction : retrieve_vif function void uvma_debug_agent_c::create_components(); - + monitor = uvma_debug_mon_c ::type_id::create("monitor" , this); sequencer = uvma_debug_sqr_c ::type_id::create("sequencer" , this); driver = uvma_debug_drv_c ::type_id::create("driver" , this); cov_model = uvma_debug_cov_model_c ::type_id::create("cov_model" , this); mon_trn_logger = uvma_debug_mon_trn_logger_c ::type_id::create("mon_trn_logger" , this); seq_item_logger = uvma_debug_seq_item_logger_c::type_id::create("seq_item_logger", this); - + endfunction : create_components function void uvma_debug_agent_c::connect_sequencer_and_driver(); - + sequencer.set_arbitration(cfg.sqr_arb_mode); driver.seq_item_port.connect(sequencer.seq_item_export); - + endfunction : connect_sequencer_and_driver function void uvma_debug_agent_c::connect_analysis_ports(); - + drv_ap = driver .ap; mon_ap = monitor.ap; - + endfunction : connect_analysis_ports function void uvma_debug_agent_c::connect_cov_model(); - + mon_ap.connect(cov_model.mon_trn_fifo .analysis_export); drv_ap.connect(cov_model.seq_item_fifo.analysis_export); - + endfunction : connect_cov_model function void uvma_debug_agent_c::connect_trn_loggers(); - + mon_ap.connect(mon_trn_logger .analysis_export); drv_ap.connect(seq_item_logger.analysis_export); - + endfunction : connect_trn_loggers diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_cntxt.sv b/lib/uvm_agents/uvma_debug/uvma_debug_cntxt.sv index e3b38adce3..7800ae612e 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_cntxt.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_cntxt.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -24,31 +24,31 @@ * (uvma_debug_agent_c) components. */ class uvma_debug_cntxt_c extends uvm_object; - + // Handle to agent interface - virtual uvma_debug_if vif; - + virtual uvma_debug_if_t vif; + // Events uvm_event sample_cfg_e; uvm_event sample_cntxt_e; - - + + `uvm_object_utils_begin(uvma_debug_cntxt_c) `uvm_field_event(sample_cfg_e , UVM_DEFAULT) `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) `uvm_object_utils_end - - + + /** * Builds events. */ extern function new(string name="uvma_debug_cntxt"); - + /** * TODO Describe uvma_debug_cntxt_c::reset() */ extern function void reset(); - + endclass : uvma_debug_cntxt_c @@ -56,19 +56,19 @@ endclass : uvma_debug_cntxt_c function uvma_debug_cntxt_c::new(string name="uvma_debug_cntxt"); - + super.new(name); - + sample_cfg_e = new("sample_cfg_e" ); sample_cntxt_e = new("sample_cntxt_e"); - + endfunction : new function void uvma_debug_cntxt_c::reset(); - + // TODO Implement uvma_debug_cntxt_c::reset() - + endfunction : reset diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_drv.sv b/lib/uvm_agents/uvma_debug/uvma_debug_drv.sv index d92837471f..88c20c2455 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_drv.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_drv.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -20,49 +20,49 @@ /** - * Component driving a Debug virtual interface (uvma_debug_if). + * Component driving a Debug virtual interface (uvma_debug_if_t). */ class uvma_debug_drv_c extends uvm_driver#( .REQ(uvma_debug_seq_item_c), .RSP(uvma_debug_seq_item_c) ); - + // Objects uvma_debug_cfg_c cfg; uvma_debug_cntxt_c cntxt; - + // TLM uvm_analysis_port#(uvma_debug_seq_item_c) ap; - - + + `uvm_component_utils_begin(uvma_debug_drv_c) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - - + + /** * Default constructor. */ extern function new(string name="uvma_debug_drv", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null. * 2. Builds ap. */ extern virtual function void build_phase(uvm_phase phase); - + /** * Oversees driving, depending on the reset state, by calling drv__reset() tasks. */ extern virtual task run_phase(uvm_phase phase); - - + + /** * Drives the virtual interface's (cntxt.vif) signals using req's contents. */ extern virtual task drv_req(uvma_debug_seq_item_c req); - + endclass : uvma_debug_drv_c @@ -70,46 +70,46 @@ endclass : uvma_debug_drv_c function uvma_debug_drv_c::new(string name="uvma_debug_drv", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_debug_drv_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + void'(uvm_config_db#(uvma_debug_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") end uvm_config_db#(uvma_debug_cfg_c)::set(this, "*", "cfg", cfg); - + void'(uvm_config_db#(uvma_debug_cntxt_c)::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_fatal("CNTXT", "Context handle is null") end uvm_config_db#(uvma_debug_cntxt_c)::set(this, "*", "cntxt", cntxt); - + ap = new("ap", this); - + endfunction : build_phase task uvma_debug_drv_c::run_phase(uvm_phase phase); - + super.run_phase(phase); - + cntxt.vif.is_active =1; - + forever begin seq_item_port.get_next_item(req); `uvml_hrtbt() drv_req(req); ap.write(req); seq_item_port.item_done(); - end + end endtask : run_phase diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_if.sv b/lib/uvm_agents/uvma_debug/uvma_debug_if.sv index d9f1d0545c..1194e74cb5 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_if.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_if.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,51 +23,54 @@ * Encapsulates all signals and clocking of Debug interface. Used by * monitor and driver. */ -interface uvma_debug_if( +interface uvma_debug_if_t( ); wire clk; wire reset_n; wire debug_req; - - bit is_active; + + bit is_active; bit debug_drv; assign debug_req = is_active ? debug_drv : 1'b0; + `ifndef FORMAL initial begin is_active = 1'b0; debug_drv = 1'b0; end + `endif // `ifndef FORMAL + /** * Used by target DUT. */ clocking dut_cb @(posedge clk or reset_n); endclocking : dut_cb - + /** * Used by uvma_debug_drv_c. */ clocking drv_cb @(posedge clk or reset_n); - // TODO Implement uvma_debug_if::drv_cb() + // TODO Implement uvma_debug_if_t::drv_cb() // Ex: output enable, // data ; output debug_drv; endclocking : drv_cb - + /** * Used by uvma_debug_mon_c. */ clocking mon_cb @(posedge clk or reset_n); input #1step debug_drv; endclocking : mon_cb - - + + modport dut_mp (clocking dut_cb); modport active_mp (clocking drv_cb); modport passive_mp(clocking mon_cb); - -endinterface : uvma_debug_if + +endinterface : uvma_debug_if_t `endif // __UVMA_DEBUG_IF_SV__ diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_if_chk.sv b/lib/uvm_agents/uvma_debug/uvma_debug_if_chk.sv index dcc6952976..c287c87f2c 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_if_chk.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_if_chk.sv @@ -1,12 +1,12 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -19,18 +19,18 @@ /** - * Encapsulates assertions targeting uvma_debug_if. + * Encapsulates assertions targeting uvma_debug_if_t. */ module uvma_debug_if_chk( - uvma_debug_if debug_if + uvma_debug_if_t debug_if ); - + `pragma protect begin - + // TODO Add assertions to uvma_debug_if_chk - + `pragma protect end - + endmodule : uvma_debug_if_chk diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_mon.sv b/lib/uvm_agents/uvma_debug/uvma_debug_mon.sv index 136cce5ffe..aeb01e13b0 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_mon.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_mon.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -21,65 +21,65 @@ /** * Component sampling transactions from a Debug virtual interface - * (uvma_debug_if). + * (uvma_debug_if_t). */ class uvma_debug_mon_c extends uvm_monitor; - + // Objects uvma_debug_cfg_c cfg; uvma_debug_cntxt_c cntxt; - + // TLM uvm_analysis_port#(uvma_debug_mon_trn_c) ap; - - + + `uvm_component_utils_begin(uvma_debug_mon_c) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - - + + /** * Default constructor. */ extern function new(string name="uvma_debug_mon", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null. * 2. Builds ap. */ extern virtual function void build_phase(uvm_phase phase); - + /** * Updates the context's reset state. */ extern virtual task observe_reset(); - + /** * Called by run_phase() while agent is in pre-reset state. */ extern virtual task mon_pre_reset(uvm_phase phase); - + /** * Called by run_phase() while agent is in reset state. */ extern virtual task mon_in_reset(uvm_phase phase); - + /** * Called by run_phase() while agent is in post-reset state. */ extern virtual task mon_post_reset(uvm_phase phase); - + /** * Creates trn by sampling the virtual interface's (cntxt.vif) signals. */ extern virtual task sample_trn(output uvma_debug_mon_trn_c trn); - + /** * TODO Describe uvma_debug_mon_c::process_trn() */ extern virtual function void process_trn(ref uvma_debug_mon_trn_c trn); - + endclass : uvma_debug_mon_c @@ -87,33 +87,33 @@ endclass : uvma_debug_mon_c function uvma_debug_mon_c::new(string name="uvma_debug_mon", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_debug_mon_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + void'(uvm_config_db#(uvma_debug_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") end - + void'(uvm_config_db#(uvma_debug_cntxt_c)::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_fatal("CNTXT", "Context handle is null") end - + ap = new("ap", this); - + endfunction : build_phase task uvma_debug_mon_c::observe_reset(); - + // TODO Implement uvma_debug_mon_c::observe_reset() // Ex: forever begin // wait (cntxt.vif.reset == 1); @@ -121,54 +121,54 @@ task uvma_debug_mon_c::observe_reset(); // wait (cntxt.vif.reset == 0); // cntxt.reset_state = UVMA_RESET_STATE_POST_RESET; // end - + // WARNING If no time is consumed by this task, a zero-delay oscillation loop will occur and stall simulation - + endtask : observe_reset task uvma_debug_mon_c::mon_pre_reset(uvm_phase phase); - + // TODO Implement uvma_debug_mon_c::mon_pre_reset() // Ex: @(cntxt.vif.mon_cb); - + // WARNING If no time is consumed by this task, a zero-delay oscillation loop will occur and stall simulation - + endtask : mon_pre_reset task uvma_debug_mon_c::mon_in_reset(uvm_phase phase); - + // TODO Implement uvma_debug_mon_c::mon_in_reset() // Ex: @(cntxt.vif.mon_cb); - + // WARNING If no time is consumed by this task, a zero-delay oscillation loop will occur and stall simulation - + endtask : mon_in_reset task uvma_debug_mon_c::mon_post_reset(uvm_phase phase); - + uvma_debug_mon_trn_c trn; - + sample_trn (trn); process_trn(trn); ap.write (trn); - + `uvml_hrtbt() - + endtask : mon_post_reset task uvma_debug_mon_c::sample_trn(output uvma_debug_mon_trn_c trn); - + bit sampled_trn = 0; - + trn = uvma_debug_mon_trn_c::type_id::create("trn"); - + do begin @(cntxt.vif.mon_cb); - + // TODO Sample trn from vif // Ex: if (cntxt.vif.reset == 0) begin // if (cntxt.vif.mon_cb.enable) begin @@ -178,17 +178,17 @@ task uvma_debug_mon_c::sample_trn(output uvma_debug_mon_trn_c trn); // trn.timestamp = $realtime(); // end // end - + // WARNING If no time is consumed by this loop, a zero-delay oscillation loop will occur and stall simulation end while (!sampled_trn); - + endtask : sample_trn function void uvma_debug_mon_c::process_trn(ref uvma_debug_mon_trn_c trn); - + // TODO Implement uvma_debug_mon_c::process_trn() - + endfunction : process_trn diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_mon_trn_logger.sv b/lib/uvm_agents/uvma_debug/uvma_debug_mon_trn_logger.sv index f39d33de53..458ab4645c 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_mon_trn_logger.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_mon_trn_logger.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -27,41 +27,41 @@ class uvma_debug_mon_trn_logger_c extends uvml_logs_mon_trn_logger_c#( .T_CFG (uvma_debug_cfg_c ), .T_CNTXT(uvma_debug_cntxt_c ) ); - + `uvm_component_utils(uvma_debug_mon_trn_logger_c) - - + + /** * Default constructor. */ function new(string name="uvma_debug_mon_trn_logger", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new - + /** * Writes contents of t to disk */ virtual function void write(uvma_debug_mon_trn_c t); - + // TODO Implement uvma_debug_mon_trn_logger_c::write() // Ex: fwrite($sformatf(" %t | %08h | %02b | %04d | %02h |", $realtime(), t.a, t.b, t.c, t.d)); - + endfunction : write - + /** * Writes log header to disk */ virtual function void print_header(); - + // TODO Implement uvma_debug_mon_trn_logger_c::print_header() // Ex: fwrite("----------------------------------------------"); // fwrite(" TIME | FIELD A | FIELD B | FIELD C | FIELD D "); // fwrite("----------------------------------------------"); - + endfunction : print_header - + endclass : uvma_debug_mon_trn_logger_c @@ -69,25 +69,25 @@ endclass : uvma_debug_mon_trn_logger_c * Component writing DEBUG monitor transactions debug data to disk as JavaScript Object Notation (JSON). */ class uvma_debug_mon_trn_logger_json_c extends uvma_debug_mon_trn_logger_c; - + `uvm_component_utils(uvma_debug_mon_trn_logger_json_c) - - + + /** * Set file extension to '.json'. */ function new(string name="uvma_debug_mon_trn_logger_json", uvm_component parent=null); - + super.new(name, parent); fextension = "json"; - + endfunction : new - + /** * Writes contents of t to disk. */ virtual function void write(uvma_debug_mon_trn_c t); - + // TODO Implement uvma_debug_mon_trn_logger_json_c::write() // Ex: fwrite({"{", // $sformatf("\"time\":\"%0t\",", $realtime()), @@ -96,18 +96,18 @@ class uvma_debug_mon_trn_logger_json_c extends uvma_debug_mon_trn_logger_c; // $sformatf("\"c\":%d," , t.c ), // $sformatf("\"d\":%h," , t.c ), // "},"}); - + endfunction : write - + /** * Empty function. */ virtual function void print_header(); - + // Do nothing: JSON files do not use headers. - + endfunction : print_header - + endclass : uvma_debug_mon_trn_logger_json_c diff --git a/lib/uvm_agents/uvma_debug/uvma_debug_pkg.sv b/lib/uvm_agents/uvma_debug/uvma_debug_pkg.sv index acafe63aeb..3c03e55253 100644 --- a/lib/uvm_agents/uvma_debug/uvma_debug_pkg.sv +++ b/lib/uvm_agents/uvma_debug/uvma_debug_pkg.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -34,37 +34,37 @@ * monitoring Debug. */ package uvma_debug_pkg; - + import uvm_pkg ::*; import uvml_hrtbt_pkg::*; import uvml_trn_pkg ::*; import uvml_logs_pkg ::*; - + // Constants / Structs / Enums `include "uvma_debug_constants.sv" `include "uvma_debug_tdefs.sv" - + // Objects `include "uvma_debug_cfg.sv" `include "uvma_debug_cntxt.sv" - + // High-level transactions `include "uvma_debug_mon_trn.sv" `include "uvma_debug_mon_trn_logger.sv" `include "uvma_debug_seq_item.sv" `include "uvma_debug_seq_item_logger.sv" - + // Agent components `include "uvma_debug_cov_model.sv" `include "uvma_debug_drv.sv" `include "uvma_debug_mon.sv" `include "uvma_debug_sqr.sv" `include "uvma_debug_agent.sv" - + // Sequences `include "uvma_debug_base_seq.sv" `include "uvma_debug_seq_lib.sv" - + endpackage : uvma_debug_pkg diff --git a/lib/uvm_agents/uvma_fencei/uvma_fencei_agent.sv b/lib/uvm_agents/uvma_fencei/uvma_fencei_agent.sv index 3b831da977..d2800421aa 100644 --- a/lib/uvm_agents/uvma_fencei/uvma_fencei_agent.sv +++ b/lib/uvm_agents/uvma_fencei/uvma_fencei_agent.sv @@ -176,7 +176,7 @@ endfunction : get_and_set_cntxt function void uvma_fencei_agent_c::retrieve_vif(); // Retrieve instruction interface - if (!uvm_config_db#(virtual uvma_fencei_if)::get(this, "", "fencei_vif", cntxt.fencei_vif)) begin + if (!uvm_config_db#(virtual uvma_fencei_if_t)::get(this, "", "fencei_vif", cntxt.fencei_vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.fencei_vif))) end diff --git a/lib/uvm_agents/uvma_fencei/uvma_fencei_cntxt.sv b/lib/uvm_agents/uvma_fencei/uvma_fencei_cntxt.sv index 4a75421d3b..53a36bcc06 100644 --- a/lib/uvm_agents/uvma_fencei/uvma_fencei_cntxt.sv +++ b/lib/uvm_agents/uvma_fencei/uvma_fencei_cntxt.sv @@ -25,7 +25,7 @@ class uvma_fencei_cntxt_c extends uvm_object; // Handle to fetch interface - virtual uvma_fencei_if fencei_vif; + virtual uvma_fencei_if_t fencei_vif; // Events uvm_event sample_cfg_e; diff --git a/lib/uvm_agents/uvma_fencei/uvma_fencei_if.sv b/lib/uvm_agents/uvma_fencei/uvma_fencei_if.sv index 600b8b9052..75a64729e9 100644 --- a/lib/uvm_agents/uvma_fencei/uvma_fencei_if.sv +++ b/lib/uvm_agents/uvma_fencei/uvma_fencei_if.sv @@ -21,7 +21,7 @@ /** * Encapsulates all signals and clocking of FENCEI flush request/acknowledge interface */ -interface uvma_fencei_if +interface uvma_fencei_if_t import uvma_fencei_pkg::*; ( input clk, @@ -57,7 +57,7 @@ interface uvma_fencei_if flush_ack; endclocking : mon_cb -endinterface : uvma_fencei_if +endinterface : uvma_fencei_if_t `endif // __UVMA_FENCEI_IF_SV__ diff --git a/lib/uvm_agents/uvma_fencei/uvma_fencei_mon.sv b/lib/uvm_agents/uvma_fencei/uvma_fencei_mon.sv index fc01e57631..15ec66aced 100644 --- a/lib/uvm_agents/uvma_fencei/uvma_fencei_mon.sv +++ b/lib/uvm_agents/uvma_fencei/uvma_fencei_mon.sv @@ -23,7 +23,7 @@ /** * Component sampling transactions from a Clock & Reset virtual interface - * (uvma_fencei_if). + * (uvma_fencei_if_t). */ class uvma_fencei_mon_c extends uvm_monitor; diff --git a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_agent.sv b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_agent.sv index a868ceeefc..392dc6ba00 100644 --- a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_agent.sv +++ b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_agent.sv @@ -174,7 +174,7 @@ endfunction : get_and_set_cntxt function void uvma_interrupt_agent_c::retrieve_vif(); - if (!uvm_config_db#(virtual uvma_interrupt_if)::get(this, "", "vif", cntxt.vif)) begin + if (!uvm_config_db#(virtual uvma_interrupt_if_t)::get(this, "", "vif", cntxt.vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.vif))) end else begin diff --git a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_cntxt.sv b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_cntxt.sv index ddd1f45430..f726d6bd35 100644 --- a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_cntxt.sv +++ b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_cntxt.sv @@ -5,9 +5,9 @@ // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -24,29 +24,29 @@ * (uvma_interrupt_agent_c) components. */ class uvma_interrupt_cntxt_c extends uvm_object; - + // Handle to agent interface - virtual uvma_interrupt_if vif; - + virtual uvma_interrupt_if_t vif; + // Events uvm_event sample_cfg_e; uvm_event sample_cntxt_e; - + `uvm_object_utils_begin(uvma_interrupt_cntxt_c) `uvm_field_event(sample_cfg_e , UVM_DEFAULT) `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) `uvm_object_utils_end - + /** * Builds events. */ extern function new(string name="uvma_interrupt_cntxt"); - + /** * TODO Describe uvma_interrupt_cntxt_c::reset() */ extern function void reset(); - + endclass : uvma_interrupt_cntxt_c @@ -54,18 +54,18 @@ endclass : uvma_interrupt_cntxt_c function uvma_interrupt_cntxt_c::new(string name="uvma_interrupt_cntxt"); - + super.new(name); - + sample_cfg_e = new("sample_cfg_e" ); sample_cntxt_e = new("sample_cntxt_e"); - + endfunction : new function void uvma_interrupt_cntxt_c::reset(); - + // TODO Implement uvma_interrupt_cntxt_c::reset() - + endfunction : reset diff --git a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_drv.sv b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_drv.sv index d8c4308c7e..e7ab6e7467 100644 --- a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_drv.sv +++ b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_drv.sv @@ -20,7 +20,7 @@ `define __UVMA_INTERRUPT_DRV_SV__ /** - * Component driving a Clock & Reset virtual interface (uvma_interrupt_if). + * Component driving a Clock & Reset virtual interface (uvma_interrupt_if_t). */ class uvma_interrupt_drv_c extends uvm_driver#( .REQ(uvma_interrupt_seq_item_c), @@ -120,7 +120,7 @@ task uvma_interrupt_drv_c::run_phase(uvm_phase phase); super.run_phase(phase); // Enable the driver in the interface - cntxt.vif.is_active = 1; + cntxt.vif.is_active = cfg.enabled; // Fork thread to deassert randomly asserted interrupts when acknowledged fork @@ -219,7 +219,7 @@ endtask : deassert_irq task uvma_interrupt_drv_c::irq_ack_clear(); while(1) begin @(cntxt.vif.mon_cb); - if (cntxt.vif.mon_cb.irq_ack) begin + if (cntxt.vif.mon_cb.irq_ack && cfg.enabled) begin // Try to get the semaphore for the irq_id, // If we can't get it, then this irq is managed by assert_irq_until_ack and we will ignore this ack // Otherwise deassert the interrupt diff --git a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_if.sv b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_if.sv index 9314377e9d..ad1eb48d5c 100644 --- a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_if.sv +++ b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_if.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,7 +23,7 @@ * Encapsulates all signals and clocking of Interrupt interface. Used by * monitor and driver. */ -interface uvma_interrupt_if +interface uvma_interrupt_if_t ( ); @@ -54,41 +54,43 @@ interface uvma_interrupt_if // Mux in driver to irq lines assign irq = is_active ? irq_drv : 1'b0; + `ifndef FORMAL initial begin is_active = 1'b0; irq_drv = '0; end + `endif // `ifndef FORMAL + - /** * Used by target DUT. */ clocking dut_cb @(posedge clk or reset_n); endclocking : dut_cb - + /** * Used by uvma_interrupt_drv_c. */ clocking drv_cb @(posedge clk or reset_n); - input #1step irq_ack, + input #1step irq_ack, irq_id; output irq_drv; endclocking : drv_cb - + /** * Used by uvma_interrupt_mon_c. */ clocking mon_cb @(posedge clk or reset_n); - input #1step irq_ack, + input #1step irq_ack, irq_id, irq_drv; endclocking : mon_cb - + modport dut_mp (clocking dut_cb); modport active_mp (clocking drv_cb); modport passive_mp(clocking mon_cb); -endinterface : uvma_interrupt_if +endinterface : uvma_interrupt_if_t `endif // __UVMA_INTERRUPT_IF_SV__ diff --git a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_mon.sv b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_mon.sv index 1aa717769b..21b1f196c3 100644 --- a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_mon.sv +++ b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_mon.sv @@ -23,7 +23,7 @@ /** * Component sampling transactions from a Clock & Reset virtual interface - * (uvma_interrupt_if). + * (uvma_interrupt_if_t). */ class uvma_interrupt_mon_c extends uvm_monitor; diff --git a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_pkg.sv b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_pkg.sv index 413def23dc..a493830bf0 100644 --- a/lib/uvm_agents/uvma_interrupt/uvma_interrupt_pkg.sv +++ b/lib/uvm_agents/uvma_interrupt/uvma_interrupt_pkg.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_INTERRUPT_PKG_SV__ @@ -33,6 +33,9 @@ * Encapsulates all the types needed for an UVM agent capable of driving and/or * monitoring Clock & Reset. */ + +//TODO: change these file names too? + package uvma_interrupt_pkg; import uvm_pkg ::*; @@ -43,28 +46,28 @@ package uvma_interrupt_pkg; // Constants / Structs / Enums `include "uvma_interrupt_constants.sv" `include "uvma_interrupt_tdefs.sv" - + // Objects `include "uvma_interrupt_cfg.sv" `include "uvma_interrupt_cntxt.sv" - + // High-level transactions `include "uvma_interrupt_mon_trn.sv" `include "uvma_interrupt_mon_trn_logger.sv" `include "uvma_interrupt_seq_item.sv" `include "uvma_interrupt_seq_item_logger.sv" - + // Agent components `include "uvma_interrupt_cov_model.sv" `include "uvma_interrupt_drv.sv" `include "uvma_interrupt_mon.sv" `include "uvma_interrupt_sqr.sv" `include "uvma_interrupt_agent.sv" - + // Sequences `include "uvma_interrupt_base_seq.sv" `include "uvma_interrupt_seq_lib.sv" - + endpackage : uvma_interrupt_pkg diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_cfg.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_cfg.sv index cb425b040f..5510d40988 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_cfg.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_cfg.sv @@ -33,6 +33,8 @@ class uvma_isacov_cfg_c extends uvm_object; rand bit reg_crosses_enabled; rand bit reg_hazards_enabled; + rand decoder_e decoder; + // Core configuration object to filter extensions, csrs, modes, supported uvma_core_cntrl_cfg_c core_cfg; @@ -48,8 +50,13 @@ class uvma_isacov_cfg_c extends uvm_object; `uvm_field_int(seq_instr_x2_enabled, UVM_DEFAULT); `uvm_field_int(reg_crosses_enabled, UVM_DEFAULT); `uvm_field_int(reg_hazards_enabled, UVM_DEFAULT); + + `uvm_field_enum(decoder_e, decoder, UVM_DEFAULT); `uvm_object_utils_end; + constraint defaults_cons { + soft decoder == SPIKE; + } extern function new(string name = "uvma_isacov_cfg"); endclass : uvma_isacov_cfg_c diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv index 21068e101f..fc9938f70c 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv @@ -26,11 +26,13 @@ class uvma_isacov_mon_c#(int ILEN=DEFAULT_ILEN, uvma_isacov_cfg_c cfg; uvm_analysis_port#(uvma_isacov_mon_trn_c) ap; instr_name_t instr_name_lookup[string]; + asm_t instr_asm; // Analysis export to receive instructions from RVFI uvm_analysis_imp_rvfi_instr#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN), uvma_isacov_mon_c) rvfi_instr_imp; extern function new(string name = "uvma_isacov_mon", uvm_component parent = null); + extern virtual function void build_phase(uvm_phase phase); /** @@ -43,6 +45,8 @@ class uvma_isacov_mon_c#(int ILEN=DEFAULT_ILEN, */ extern virtual function void write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_instr); + + endclass : uvma_isacov_mon_c @@ -75,13 +79,16 @@ function void uvma_isacov_mon_c::build_phase(uvm_phase phase); dasm_set_config(32, "rv32imc", 0); // Use the enumerations in to setup the instr_name_lookup - // convert the enums to lower-case and substitute underscore with . to match - // Spike disassembler in = in.first; repeat(in.num) begin - string instr_name_key = convert_instr_to_spike_name(in.name()); + string instr_name_key = in.name(); + if(cfg.decoder == SPIKE) begin + // convert the enums to lower-case and substitute underscore with . to match + // Spike disassembler + instr_name_key = convert_instr_to_spike_name(in.name()); + `uvm_info("ISACOV", $sformatf("Converting: %s to %s", in.name(), instr_name_key), UVM_HIGH); + end - `uvm_info("ISACOV", $sformatf("Converting: %s to %s", in.name(), instr_name_key), UVM_HIGH); instr_name_lookup[instr_name_key] = in; in = in.next; end @@ -138,12 +145,21 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL mon_trn = uvma_isacov_mon_trn_c#(.ILEN(ILEN), .XLEN(XLEN))::type_id::create("mon_trn"); mon_trn.instr = uvma_isacov_instr_c#(ILEN,XLEN)::type_id::create("mon_instr"); mon_trn.instr.rvfi = rvfi_instr; - // Mark trapped instructions from RVFI mon_trn.instr.trap = rvfi_instr.trap; - // Attempt to decode instruction with Spike DASM - instr_name = dasm_name(rvfi_instr.insn); + // Get the config + void'(uvm_config_db#(uvma_isacov_cfg_c)::get(this, "", "cfg", cfg)); + + if (cfg.decoder == SPIKE) begin + // Attempt to decode instruction with Spike DASM + instr_name = dasm_name(rvfi_instr.insn); + end else if (cfg.decoder == ISA_SUPPORT) begin + // Attempt to decode instruction with isa_support + instr_asm = decode_instr(rvfi_instr.insn); + instr_name = instr_asm.instr.name(); + end + if (instr_name_lookup.exists(instr_name)) begin mon_trn.instr.name = instr_name_lookup[instr_name]; end else begin @@ -152,48 +168,85 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL // from OpenHW core-v-verif perspective so set to UNKNOWN mon_trn.instr.name = UNKNOWN; end - `uvm_info("ISACOVMON", $sformatf("rvfi = 0x%08x %s", rvfi_instr.insn, instr_name), UVM_HIGH); - - mon_trn.instr.itype = get_instr_type(mon_trn.instr.name); mon_trn.instr.ext = get_instr_ext(mon_trn.instr.name); mon_trn.instr.group = get_instr_group(mon_trn.instr.name, rvfi_instr.mem_addr); + mon_trn.instr.itype = get_instr_type(mon_trn.instr.name); - instr = $signed(rvfi_instr.insn); - - // Disassemble the instruction using Spike (via DPI) - if (mon_trn.instr.ext == C_EXT) begin - mon_trn.instr.rs1 = dasm_rvc_rs1(instr); - mon_trn.instr.rs2 = dasm_rvc_rs2(instr); - mon_trn.instr.rd = dasm_rvc_rd(instr); - mon_trn.instr.c_rdrs1 = dasm_rvc_rd(instr); - mon_trn.instr.c_rd = mon_trn.instr.decode_rd_c(instr); - mon_trn.instr.c_rs1 = mon_trn.instr.decode_rs1_c(instr); - mon_trn.instr.c_rs2 = mon_trn.instr.decode_rs2_c(instr); - end - else begin - mon_trn.instr.rs1 = dasm_rs1(instr); - mon_trn.instr.rs2 = dasm_rs2(instr); - mon_trn.instr.rd = dasm_rd(instr); - mon_trn.instr.immi = dasm_i_imm(instr); - mon_trn.instr.imms = dasm_s_imm(instr); - mon_trn.instr.immb = dasm_sb_imm(instr) >> 1; // Because dasm gives [12:0], not [12: 1] - mon_trn.instr.immu = dasm_u_imm(instr) >> 12; // Because dasm gives [31:0], not [31:12] - mon_trn.instr.immj = dasm_uj_imm(instr) >> 1; // Because dasm gives [20:0], not [20: 1] + if (cfg.decoder == SPIKE) begin + // Attempt to decode instruction with Spike DASM + instr = $signed(rvfi_instr.insn); + + //Disassemble the instruction using Spike (via DPI) + if (mon_trn.instr.ext == C_EXT) begin + mon_trn.instr.rs1 = dasm_rvc_rs1(instr); + mon_trn.instr.rs2 = dasm_rvc_rs2(instr); + mon_trn.instr.rd = dasm_rvc_rd(instr); + mon_trn.instr.c_rdrs1 = dasm_rvc_rd(instr); + mon_trn.instr.c_rd = mon_trn.instr.decode_rd_c(instr); + mon_trn.instr.c_rs1 = mon_trn.instr.decode_rs1_c(instr); + mon_trn.instr.c_rs2 = mon_trn.instr.decode_rs2_c(instr); + end + else begin + mon_trn.instr.rs1 = dasm_rs1(instr); + mon_trn.instr.rs2 = dasm_rs2(instr); + mon_trn.instr.rd = dasm_rd(instr); + mon_trn.instr.immi = dasm_i_imm(instr); + mon_trn.instr.imms = dasm_s_imm(instr); + mon_trn.instr.immb = dasm_sb_imm(instr) >> 1; // Because dasm gives [12:0], not [12: 1] + mon_trn.instr.immu = dasm_u_imm(instr) >> 12; // Because dasm gives [31:0], not [31:12] + mon_trn.instr.immj = dasm_uj_imm(instr) >> 1; // Because dasm gives [20:0], not [20: 1] + end + + // Make instructions as illegal, + // 1. If a CSR instruction is not targeted to a valid CSR + if (mon_trn.instr.group == CSR_GROUP) begin + mon_trn.instr.csr_val = dasm_csr(instr); + if (!$cast(mon_trn.instr.csr, mon_trn.instr.csr_val) || + cfg.core_cfg.unsupported_csr_mask[mon_trn.instr.csr_val]) begin + mon_trn.instr.illegal = 1; + end + end + + end else if (cfg.decoder == ISA_SUPPORT) begin + // Attempt to decode instruction with isa_support + + // TODO: silabs-hefegran, isa decoder representation changed for compressed 'rx registers, + // we supply the old (non-translated) value to avoid having to rewrite that logic now, which + // might also interfere with the spike implementation. + // the "get_rx"-functions should no longer be needed if we supply the translated values to + // the coverage model. + mon_trn.instr.c_rdrs1 = instr_asm.rd.valid_gpr_rvc ? instr_asm.rd.gpr_rvc : instr_asm.rd.gpr; + mon_trn.instr.c_rd = instr_asm.rd.valid_gpr_rvc ? instr_asm.rd.gpr_rvc : instr_asm.rd.gpr; + mon_trn.instr.c_rs1 = instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr; + mon_trn.instr.c_rs2 = instr_asm.rs2.valid_gpr_rvc ? instr_asm.rs2.gpr_rvc : instr_asm.rs2.gpr; + mon_trn.instr.rs1 = instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr; + mon_trn.instr.rs2 = instr_asm.rs2.valid_gpr_rvc ? instr_asm.rs2.gpr_rvc : instr_asm.rs1.gpr; + mon_trn.instr.rd = instr_asm.rd.valid_gpr_rvc ? instr_asm.rd.gpr_rvc : instr_asm.rd.gpr; + mon_trn.instr.immi = instr_asm.imm.imm_raw_sorted; + mon_trn.instr.imms = instr_asm.imm.imm_raw_sorted; + mon_trn.instr.immb = instr_asm.imm.imm_raw_sorted; + mon_trn.instr.immu = instr_asm.imm.imm_raw_sorted; + mon_trn.instr.immj = instr_asm.imm.imm_raw_sorted; + + // Make instructions as illegal, + // 1. If a CSR instruction is not targeted to a valid CSR + if (mon_trn.instr.group == CSR_GROUP) begin + mon_trn.instr.csr_val = instr_asm.csr.address; + if (!$cast(mon_trn.instr.csr, mon_trn.instr.csr_val) || + cfg.core_cfg.unsupported_csr_mask[mon_trn.instr.csr_val]) begin + mon_trn.instr.illegal = 1; + end + end end // Make instructions as illegal, - // 1. If UNKNOWN (undecodable) - if (mon_trn.instr.name == UNKNOWN) + // 2. If UNKNOWN (undecodable) + if (mon_trn.instr.name == UNKNOWN) begin mon_trn.instr.illegal = 1; - // 2. If a CSR instruction is not targeted to a valid CSR - if (mon_trn.instr.group == CSR_GROUP) begin - mon_trn.instr.csr_val = dasm_csr(instr); - if (!$cast(mon_trn.instr.csr, mon_trn.instr.csr_val) || - cfg.core_cfg.unsupported_csr_mask[mon_trn.instr.csr_val]) begin - mon_trn.instr.illegal = 1; - end end + + // Make instructions as illegal, // 3. Instruction is in unsupported extension if ((mon_trn.instr.ext == A_EXT && !cfg.core_cfg.ext_a_supported) || (mon_trn.instr.ext == C_EXT && !cfg.core_cfg.ext_c_supported) || @@ -282,7 +335,13 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL endcase end - mon_trn.instr.set_valid_flags(); + if (cfg.decoder == SPIKE) begin + mon_trn.instr.set_valid_flags(); + end else begin // if ISA_DECODER + mon_trn.instr.rd_valid = instr_asm.rd.valid; + mon_trn.instr.rs1_valid = instr_asm.rs1.valid; + mon_trn.instr.rs2_valid = instr_asm.rs2.valid; + end // Set enumerations for register values as reported from RVFI if (mon_trn.instr.rs1_valid) begin @@ -302,5 +361,3 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL ap.write(mon_trn); endfunction : write_rvfi_instr - - diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_pkg.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_pkg.sv index 425048821d..f62e6aa093 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_pkg.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_pkg.sv @@ -26,10 +26,13 @@ package uvma_isacov_pkg; import uvma_core_cntrl_pkg::*; import uvma_rvfi_pkg::*; + import isa_decoder_pkg::*; + import support_pkg::*; + // DPI imports `include "dpi_dasm_imports.svh" - // Constants / Structs / Enums + // Constants / Structs / Enums `include "uvma_isacov_constants.sv" `include "uvma_isacov_tdefs.sv" diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_tdefs.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_tdefs.sv index 4f90ce5b8a..7920b531b7 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_tdefs.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_tdefs.sv @@ -18,6 +18,11 @@ `ifndef __UVMA_ISACOV_TDEFS_SV__ `define __UVMA_ISACOV_TDEFS_SV__ +typedef enum { + SPIKE, + ISA_SUPPORT +} decoder_e; + typedef enum { A_EXT, B_EXT, diff --git a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_agent.sv b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_agent.sv index d0abf92aae..97824b64b3 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_agent.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_agent.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_AGENT_SV__ @@ -25,137 +25,223 @@ * Top-level component that encapsulates, builds and connects all others. * Capable of driving/monitoring Open Bus Interface interface. */ -class uvma_obi_memory_agent_c extends uvm_agent; - +class uvma_obi_memory_agent_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvm_agent; + // Objects uvma_obi_memory_cfg_c cfg; - uvma_obi_memory_cntxt_c cntxt; - + uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) cntxt; + // Components - uvma_obi_memory_drv_c driver; - uvma_obi_memory_mon_c monitor; - uvma_obi_memory_sqr_c sequencer; - uvma_obi_memory_cov_model_c cov_model; - uvma_obi_memory_seq_item_logger_c seq_item_logger; - uvma_obi_memory_mon_trn_logger_c mon_trn_logger; - + uvma_obi_memory_drv_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) driver; + + uvma_obi_memory_mon_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) monitor; + + uvma_obi_memory_sqr_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) sequencer; + + uvma_obi_memory_cov_model_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) cov_model; + + uvma_obi_memory_seq_item_logger_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) seq_item_logger; + + uvma_obi_memory_mon_trn_logger_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) mon_trn_logger; + // TLM uvm_analysis_port#(uvma_obi_memory_mstr_seq_item_c) drv_mstr_ap; uvm_analysis_port#(uvma_obi_memory_slv_seq_item_c ) drv_slv_ap ; uvm_analysis_port#(uvma_obi_memory_mon_trn_c ) mon_ap ; - - - `uvm_component_utils_begin(uvma_obi_memory_agent_c) + + + `uvm_component_utils_begin(uvma_obi_memory_agent_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - - + + /** * Default constructor. */ extern function new(string name="uvma_obi_memory_agent", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null * 2. Builds all components */ extern virtual function void build_phase(uvm_phase phase); - + /** * 1. Links agent's analysis ports to sub-components' * 2. Connects coverage models and loggers */ extern virtual function void connect_phase(uvm_phase phase); - + /** * Uses uvm_config_db to retrieve cfg and hand out to sub-components. */ extern function void get_and_set_cfg(); - + /** * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. */ extern function void get_and_set_cntxt(); - + /** * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this * agent. */ extern function void retrieve_vif(); - + /** * Creates sub-components. */ extern function void create_components(); - + /** * Connects sequencer and driver's TLM port(s). */ extern function void connect_sequencer_and_driver(); - + /** * Connects monitor and driver's TLM port(s). */ extern function void connect_rsp_path(); - + /** * Connects agent's TLM ports to driver's and monitor's. */ extern function void connect_analysis_ports(); - + /** * Connects coverage model to monitor and driver's analysis ports. */ extern function void connect_cov_model(); - + /** * Connects transaction loggers to monitor and driver's analysis ports. */ extern function void connect_trn_loggers(); - + endclass : uvma_obi_memory_agent_c function uvma_obi_memory_agent_c::new(string name="uvma_obi_memory_agent", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_obi_memory_agent_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + get_and_set_cfg (); get_and_set_cntxt(); retrieve_vif (); create_components(); - + endfunction : build_phase function void uvma_obi_memory_agent_c::connect_phase(uvm_phase phase); - + super.connect_phase(phase); - + connect_analysis_ports (); connect_sequencer_and_driver(); connect_rsp_path (); - + if (cfg.cov_model_enabled) begin connect_cov_model(); end if (cfg.trn_log_enabled) begin connect_trn_loggers(); end - + endfunction: connect_phase function void uvma_obi_memory_agent_c::get_and_set_cfg(); - + void'(uvm_config_db#(uvma_obi_memory_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") @@ -164,25 +250,61 @@ function void uvma_obi_memory_agent_c::get_and_set_cfg(); `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "*", "cfg", cfg); end - + endfunction : get_and_set_cfg function void uvma_obi_memory_agent_c::get_and_set_cntxt(); - - void'(uvm_config_db#(uvma_obi_memory_cntxt_c)::get(this, "", "cntxt", cntxt)); + + void'(uvm_config_db#(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ))::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) - cntxt = uvma_obi_memory_cntxt_c::type_id::create("cntxt"); + cntxt = uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )::type_id::create("cntxt"); end - uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "*", "cntxt", cntxt); - + uvm_config_db#(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ))::set(this, "*", "cntxt", cntxt); + endfunction : get_and_set_cntxt function void uvma_obi_memory_agent_c::retrieve_vif(); - - if (!uvm_config_db#(virtual uvma_obi_memory_if)::get(this, "", "vif", cntxt.vif)) begin + if (!uvm_config_db#(virtual uvma_obi_memory_if_t#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH)) + )::get(this, "", "vif", cntxt.vif)) begin `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.vif))) end else begin @@ -193,71 +315,125 @@ endfunction : retrieve_vif function void uvma_obi_memory_agent_c::create_components(); - - monitor = uvma_obi_memory_mon_c ::type_id::create("monitor" , this); - cov_model = uvma_obi_memory_cov_model_c ::type_id::create("cov_model" , this); - mon_trn_logger = uvma_obi_memory_mon_trn_logger_c ::type_id::create("mon_trn_logger" , this); - seq_item_logger = uvma_obi_memory_seq_item_logger_c::type_id::create("seq_item_logger", this); - + + monitor = uvma_obi_memory_mon_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )::type_id::create("monitor" , this); + cov_model = uvma_obi_memory_cov_model_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )::type_id::create("cov_model" , this); + mon_trn_logger = uvma_obi_memory_mon_trn_logger_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )::type_id::create("mon_trn_logger" , this); + seq_item_logger = uvma_obi_memory_seq_item_logger_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )::type_id::create("seq_item_logger", this); + if (cfg.is_active) begin - sequencer = uvma_obi_memory_sqr_c::type_id::create("sequencer", this); - driver = uvma_obi_memory_drv_c::type_id::create("driver" , this); + sequencer = uvma_obi_memory_sqr_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )::type_id::create("sequencer", this); + driver = uvma_obi_memory_drv_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )::type_id::create("driver" , this); end - + endfunction : create_components function void uvma_obi_memory_agent_c::connect_analysis_ports(); - + if (cfg.is_active) begin drv_mstr_ap = driver .mstr_ap; drv_slv_ap = driver .slv_ap ; end mon_ap = monitor.ap; - + endfunction : connect_analysis_ports function void uvma_obi_memory_agent_c::connect_sequencer_and_driver(); - + if (cfg.is_active) begin sequencer.set_arbitration(cfg.sqr_arb_mode); driver.seq_item_port.connect(sequencer.seq_item_export); end - + endfunction : connect_sequencer_and_driver function void uvma_obi_memory_agent_c::connect_rsp_path(); - + if (cfg.is_active) begin // FIXME:This conenction is a memory leak (driver never drains FIFO) //monitor.ap .connect(driver .mon_trn_fifo.analysis_export); monitor.sequencer_ap.connect(sequencer.mon_trn_fifo.analysis_export); end - + endfunction : connect_rsp_path function void uvma_obi_memory_agent_c::connect_cov_model(); - + if (cfg.is_active) begin drv_mstr_ap.connect(cov_model.mstr_seq_item_fifo.analysis_export); drv_slv_ap .connect(cov_model.slv_seq_item_fifo .analysis_export); end mon_ap.connect(cov_model.mon_trn_fifo.analysis_export); - + endfunction : connect_cov_model function void uvma_obi_memory_agent_c::connect_trn_loggers(); - + //if (cfg.is_active) begin // drv_mstr_ap.connect(seq_item_logger.analysis_export); // drv_slv_ap .connect(seq_item_logger.analysis_export); //end mon_ap.connect(mon_trn_logger.analysis_export); - + endfunction : connect_trn_loggers diff --git a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv index c53baa07e8..fd6389589c 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_COV_MODEL_SV__ @@ -73,75 +73,102 @@ endgroup : cg_obi /** * Component encapsulating Open Bus Interface functional coverage model. */ -class uvma_obi_memory_cov_model_c extends uvm_component; - +class uvma_obi_memory_cov_model_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvm_component; + // Objects uvma_obi_memory_cfg_c cfg; - uvma_obi_memory_cntxt_c cntxt; - + uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) cntxt; + // TLM uvm_tlm_analysis_fifo#(uvma_obi_memory_mon_trn_c ) mon_trn_fifo ; uvm_tlm_analysis_fifo#(uvma_obi_memory_mstr_seq_item_c) mstr_seq_item_fifo; uvm_tlm_analysis_fifo#(uvma_obi_memory_slv_seq_item_c ) slv_seq_item_fifo ; - // Covergroup instances + // Covergroup instances cg_obi obi_cg; cg_obi_delay wr_delay_cg; cg_obi_delay rd_delay_cg; - `uvm_component_utils_begin(uvma_obi_memory_cov_model_c) + `uvm_component_utils_begin(uvma_obi_memory_cov_model_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - + /** * Default constructor. */ extern function new(string name="uvma_obi_memory_cov_model", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null. * 2. Builds fifos. */ extern virtual function void build_phase(uvm_phase phase); - + /** * Forks all sampling loops */ extern virtual task run_phase(uvm_phase phase); - + /** * TODO Describe uvma_obi_memory_cov_model_c::sample_cfg() */ extern function void sample_cfg(); - + /** * TODO Describe uvma_obi_memory_cov_model_c::sample_cntxt() */ extern function void sample_cntxt(); - + /** * Sample covergroups for monitored OBI transactions */ extern function void sample_mon_trn(uvma_obi_memory_mon_trn_c trn); - + /** * TODO Describe uvma_obi_memory_cov_model_c::sample_mstr_seq_item() */ extern function void sample_mstr_seq_item(); - + /** * TODO Describe uvma_obi_memory_cov_model_c::sample_slv_seq_item() */ extern function void sample_slv_seq_item(); - + endclass : uvma_obi_memory_cov_model_c function uvma_obi_memory_cov_model_c::new(string name="uvma_obi_memory_cov_model", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new @@ -151,26 +178,35 @@ endfunction : new // //@DVT_LINTER_WAIVER_START "MT20210901_1" disable SVTB.33.1.0, SVTB.33.2.0 function void uvma_obi_memory_cov_model_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + void'(uvm_config_db#(uvma_obi_memory_cfg_c)::get(this, "", "cfg", cfg)); if (cfg == null) begin `uvm_fatal("CFG", "Configuration handle is null") end - - void'(uvm_config_db#(uvma_obi_memory_cntxt_c)::get(this, "", "cntxt", cntxt)); + + void'(uvm_config_db#(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ))::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_fatal("CNTXT", "Context handle is null") end - + mon_trn_fifo = new("mon_trn_fifo" , this); mstr_seq_item_fifo = new("mstr_seq_item_fifo", this); slv_seq_item_fifo = new("slv_seq_item_fifo" , this); - + if (cfg.enabled && cfg.cov_model_enabled) begin - obi_cg = new("obi_cg", - .read_enabled(cfg.read_enabled), + obi_cg = new("obi_cg", + .read_enabled(cfg.read_enabled), .write_enabled(cfg.write_enabled), .is_1p2(cfg.version >= UVMA_OBI_MEMORY_VERSION_1P2)); if (cfg.read_enabled) rd_delay_cg = new("rd_delay_cg"); @@ -181,23 +217,23 @@ endfunction : build_phase //@DVT_LINTER_WAIVER_END "MT20210901_1" task uvma_obi_memory_cov_model_c::run_phase(uvm_phase phase); - + super.run_phase(phase); - - if (cfg.enabled && cfg.cov_model_enabled) begin + + if (cfg.enabled && cfg.cov_model_enabled) begin fork // Configuration forever begin cntxt.sample_cfg_e.wait_trigger(); sample_cfg(); end - + // Context forever begin cntxt.sample_cntxt_e.wait_trigger(); sample_cntxt(); end - + // Monitor transactions forever begin uvma_obi_memory_mon_trn_c mon_trn; @@ -205,7 +241,7 @@ task uvma_obi_memory_cov_model_c::run_phase(uvm_phase phase); mon_trn_fifo.get(mon_trn); sample_mon_trn(mon_trn); end - + // 'mstr' sequence items forever begin uvma_obi_memory_mstr_seq_item_c mstr_seq_item; @@ -213,7 +249,7 @@ task uvma_obi_memory_cov_model_c::run_phase(uvm_phase phase); mstr_seq_item_fifo.get(mstr_seq_item); sample_mstr_seq_item(); end - + // 'slv' sequence items forever begin uvma_obi_memory_slv_seq_item_c slv_seq_item; @@ -223,44 +259,44 @@ task uvma_obi_memory_cov_model_c::run_phase(uvm_phase phase); end join_none end - + endtask : run_phase function void uvma_obi_memory_cov_model_c::sample_cfg(); - + // TODO Implement uvma_obi_memory_cov_model_c::sample_cfg(); - + endfunction : sample_cfg function void uvma_obi_memory_cov_model_c::sample_cntxt(); - + // TODO Implement uvma_obi_memory_cov_model_c::sample_cntxt(); - + endfunction : sample_cntxt function void uvma_obi_memory_cov_model_c::sample_mon_trn(uvma_obi_memory_mon_trn_c trn); - + obi_cg.sample(trn); - if (cfg.write_enabled) wr_delay_cg.sample(trn); - if (cfg.read_enabled) rd_delay_cg.sample(trn); - + if (cfg.write_enabled) wr_delay_cg.sample(trn); + if (cfg.read_enabled) rd_delay_cg.sample(trn); + endfunction : sample_mon_trn function void uvma_obi_memory_cov_model_c::sample_mstr_seq_item(); - + // TODO Implement uvma_obi_memory_cov_model_c::sample_mstr_seq_item(); - + endfunction : sample_mstr_seq_item function void uvma_obi_memory_cov_model_c::sample_slv_seq_item(); - + // TODO Implement uvma_obi_memory_cov_model_c::sample_slv_seq_item(); - + endfunction : sample_slv_seq_item diff --git a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_drv.sv b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_drv.sv index dd8a222fe7..aeeaa2f4db 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_drv.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_drv.sv @@ -22,18 +22,36 @@ /** - * Component driving a Open Bus Interface virtual interface (uvma_obi_if). + * Component driving a Open Bus Interface virtual interface (uvma_obi_if_t). * @note The req & rsp's roles are switched when this driver is in 'slv' mode. * @todo Move implementation to a sequence-based approach */ -class uvma_obi_memory_drv_c extends uvm_driver#( +class uvma_obi_memory_drv_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvm_driver#( .REQ(uvma_obi_memory_base_seq_item_c), .RSP(uvma_obi_memory_mon_trn_c ) ); // Objects uvma_obi_memory_cfg_c cfg; - uvma_obi_memory_cntxt_c cntxt; + uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) cntxt; // TLM uvm_analysis_port #(uvma_obi_memory_mstr_seq_item_c) mstr_ap; @@ -41,10 +59,38 @@ class uvma_obi_memory_drv_c extends uvm_driver#( uvm_tlm_analysis_fifo #(uvma_obi_memory_mon_trn_c ) mon_trn_fifo; // Handles to virtual interface modports - virtual uvma_obi_memory_if.active_mstr_mp mstr_mp; - virtual uvma_obi_memory_if.active_slv_mp slv_mp ; - - `uvm_component_utils_begin(uvma_obi_memory_drv_c) + virtual uvma_obi_memory_if_t#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ).active_mstr_mp mstr_mp; + + virtual uvma_obi_memory_if_t#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ).active_slv_mp slv_mp ; + + `uvm_component_utils_begin(uvma_obi_memory_drv_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end @@ -156,11 +202,29 @@ function void uvma_obi_memory_drv_c::build_phase(uvm_phase phase); end uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "*", "cfg", cfg); - void'(uvm_config_db#(uvma_obi_memory_cntxt_c)::get(this, "", "cntxt", cntxt)); + void'(uvm_config_db#(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ))::get(this, "", "cntxt", cntxt)); if (cntxt == null) begin `uvm_fatal("CNTXT", "Context handle is null") end - uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "*", "cntxt", cntxt); + uvm_config_db#(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ))::set(this, "*", "cntxt", cntxt); mstr_mp = cntxt.vif.active_mstr_mp; slv_mp = cntxt.vif.active_slv_mp ; @@ -304,7 +368,7 @@ task uvma_obi_memory_drv_c::drv_slv_gnt(); // In case 0 latency was selected, we must go ahead and drive gnt (combinatorial path) if (effective_latency == 0) begin - slv_mp.drv_slv_cb.gnt <= 1'b1; + slv_mp.drv_slv_cb.gnt <= 1'b1; if (cfg.is_1p2_or_higher()) begin slv_mp.drv_slv_cb.gntpar <= 1'b0; end @@ -455,6 +519,7 @@ task uvma_obi_memory_drv_c::drv_slv_read_req(ref uvma_obi_memory_slv_seq_item_c slv_mp.drv_slv_cb.rid <= req.rid; slv_mp.drv_slv_cb.err <= req.err; slv_mp.drv_slv_cb.exokay <= req.exokay; + slv_mp.drv_slv_cb.rchk <= req.rchk; end for (int unsigned ii=0; ii= UVMA_OBI_MEMORY_VERSION_1P3) ? 1 : 0; + +endfunction : is_1p3_or_higher + `endif // __UVMA_OBI_MEMORY_CFG_SV__ diff --git a/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_cntxt.sv b/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_cntxt.sv index 623b7a74ff..dbff7e28f0 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_cntxt.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_cntxt.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_CNTXT_SV__ @@ -29,11 +29,29 @@ typedef class uvma_obi_memory_mon_trn_c; * Object encapsulating all state variables for all Open Bus Interface agent * (uvma_obi_agent_c) components. */ -class uvma_obi_memory_cntxt_c extends uvm_object; - +class uvma_obi_memory_cntxt_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvm_object; + // Handle to agent interface - virtual uvma_obi_memory_if vif; - + virtual uvma_obi_memory_if_t#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) vif; + // Handle to memory storage for active slaves uvml_mem_c mem; @@ -44,59 +62,68 @@ class uvma_obi_memory_cntxt_c extends uvm_object; int unsigned mon_rvalid_latency = 0; int unsigned mon_rready_latency = 0; int unsigned mon_rp_hold = 0; - + // Queues uvma_obi_memory_mon_trn_c mon_outstanding_reads_q[$]; - + // Events uvm_event sample_cfg_e; uvm_event sample_cntxt_e; - - - `uvm_object_utils_begin(uvma_obi_memory_cntxt_c) + + + `uvm_object_param_utils_begin(uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_enum(uvma_obi_memory_reset_state_enum, reset_state, UVM_DEFAULT) `uvm_field_enum(uvma_obi_memory_phases_enum , mon_phase , UVM_DEFAULT) - + `uvm_field_queue_object(mon_outstanding_reads_q, UVM_DEFAULT) - + `uvm_field_event(sample_cfg_e , UVM_DEFAULT) `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) `uvm_object_utils_end - - + + /** * Builds events. */ extern function new(string name="uvma_obi_memory_cntxt"); - + /** * TODO Describe uvma_obi_memory_cntxt_c::reset() */ extern function void reset(); - + endclass : uvma_obi_memory_cntxt_c function uvma_obi_memory_cntxt_c::new(string name="uvma_obi_memory_cntxt"); - + super.new(name); - + sample_cfg_e = new("sample_cfg_e" ); sample_cntxt_e = new("sample_cntxt_e"); - + endfunction : new function void uvma_obi_memory_cntxt_c::reset(); - + mon_phase = UVMA_OBI_MEMORY_PHASE_INACTIVE; mon_gnt_latency = 0; mon_rvalid_latency = 0; mon_rready_latency = 0; mon_rp_hold = 0; - + mon_outstanding_reads_q.delete(); - + endfunction : reset diff --git a/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_mon_trn.sv b/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_mon_trn.sv index e260a7b159..ccaf8b320c 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_mon_trn.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/obj/uvma_obi_memory_mon_trn.sv @@ -44,6 +44,7 @@ class uvma_obi_memory_mon_trn_c extends uvml_trn_mon_trn_c; uvma_obi_memory_prot_l_t prot ; ///< Memory access type and privilege level of transaction uvma_obi_memory_achk_l_t achk ; ///< Address signal checksum uvma_obi_memory_rchk_l_t rchk ; ///< Response signal checksum + uvma_obi_memory_dbg_l_t dbg ; ///< Transaction in debug mode // Metadata uvma_obi_memory_cfg_c cfg ; ///< Handle to agent's configuration object @@ -67,6 +68,7 @@ class uvma_obi_memory_mon_trn_c extends uvml_trn_mon_trn_c; `uvm_field_int ( prot , UVM_DEFAULT ) `uvm_field_int ( achk , UVM_DEFAULT ) `uvm_field_int ( rchk , UVM_DEFAULT ) + `uvm_field_int ( dbg , UVM_DEFAULT ) `uvm_field_int(gnt_latency , UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE) `uvm_field_int(rvalid_latency, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE) diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_base_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_base_seq.sv index 21f790fc4f..e6d4eab931 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_base_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_base_seq.sv @@ -1,19 +1,19 @@ -// +// // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_BASE_SEQ_SV__ @@ -25,45 +25,81 @@ * sequences must extend. Subclasses must be run on Open Bus Interface * sequencer (uvma_obi_sqr_c) instance. */ -class uvma_obi_memory_base_seq_c extends uvm_sequence#( +class uvma_obi_memory_base_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +)extends uvm_sequence#( .REQ(uvma_obi_memory_base_seq_item_c), .RSP(uvma_obi_memory_mon_trn_c ) ); - + // Agent handles uvma_obi_memory_cfg_c cfg; - uvma_obi_memory_cntxt_c cntxt; - - - `uvm_object_utils(uvma_obi_memory_base_seq_c) - `uvm_declare_p_sequencer(uvma_obi_memory_sqr_c) - - + uvma_obi_memory_cntxt_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) cntxt; + + + `uvm_object_param_utils(uvma_obi_memory_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) + `uvm_declare_p_sequencer(uvma_obi_memory_sqr_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) + + /** * Default constructor. */ extern function new(string name="uvma_obi_memory_base_seq"); - + /** * Assigns cfg and cntxt handles from p_sequencer. */ extern virtual task pre_start(); - + endclass : uvma_obi_memory_base_seq_c function uvma_obi_memory_base_seq_c::new(string name="uvma_obi_memory_base_seq"); - + super.new(name); - + endfunction : new task uvma_obi_memory_base_seq_c::pre_start(); - + cfg = p_sequencer.cfg; cntxt = p_sequencer.cntxt; - + endtask : pre_start diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_fw_preload_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_fw_preload_seq.sv index 17c9bf6683..8a373c8ebd 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_fw_preload_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_fw_preload_seq.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_FW_PRELOAD_SEQ_SV__ @@ -25,29 +25,56 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -class uvma_obi_memory_fw_preload_seq_c extends uvma_obi_memory_base_seq_c; +class uvma_obi_memory_fw_preload_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); string fw_file_path; - `uvm_object_utils_begin(uvma_obi_memory_fw_preload_seq_c) + `uvm_object_utils_begin(uvma_obi_memory_fw_preload_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end - + /** * Default constructor. */ extern function new(string name="uvma_obi_memory_fw_preload_seq"); - + /** * Implement the sequence using plusarg to load a firmware file */ extern virtual task body(); - + endclass : uvma_obi_memory_fw_preload_seq_c function uvma_obi_memory_fw_preload_seq_c::new(string name="uvma_obi_memory_fw_preload_seq"); - + super.new(name); - + endfunction : new task uvma_obi_memory_fw_preload_seq_c::body(); @@ -55,7 +82,7 @@ task uvma_obi_memory_fw_preload_seq_c::body(); if ($value$plusargs("firmware=%s", fw_file_path)) begin cntxt.mem.readmemh(fw_file_path); end - + endtask : body `endif // __UVMA_OBI_MEMORY_FW_PRELOAD_SEQ_SV__ diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_base_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_base_seq.sv index 4ed4e2cc54..b68591b4d6 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_base_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_base_seq.sv @@ -24,12 +24,39 @@ /** * TODO Describe uvma_obi_memory_slv_base_seq_c */ -class uvma_obi_memory_slv_base_seq_c extends uvma_obi_memory_base_seq_c; +class uvma_obi_memory_slv_base_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); // Fields - `uvm_object_utils_begin(uvma_obi_memory_slv_base_seq_c) + `uvm_object_param_utils_begin(uvma_obi_memory_slv_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end @@ -157,8 +184,18 @@ endfunction : add_ruser function void uvma_obi_memory_slv_base_seq_c::add_rchk(uvma_obi_memory_slv_seq_item_c slv_rsp); - // FIXME:need to implement this - // slv_rsp.rchk = '0; + if(cfg.chk_scheme == UVMA_OBI_MEMORY_CHK_TIED) begin + slv_rsp.rchk = '0; + end + // Checksum scheme for CV32E40S. If other schemes are required, they need to be added here, + // in addition to adding the option to enable them + else if(cfg.chk_scheme == UVMA_OBI_MEMORY_CHK_CV32E40S) begin + slv_rsp.rchk[0] = ^slv_rsp.rdata[7:0]; + slv_rsp.rchk[1] = ^slv_rsp.rdata[15:8]; + slv_rsp.rchk[2] = ^slv_rsp.rdata[23:16]; + slv_rsp.rchk[3] = ^slv_rsp.rdata[31:24]; + slv_rsp.rchk[4] = ^{slv_rsp.err, 1'b0}; // exokay signal is an optional signal that is only included for CPUs supporting the Atomic (A) extension. + end endfunction : add_rchk diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq.sv index d5c0964086..6fc3b614e8 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq.sv @@ -25,15 +25,60 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -class uvma_obi_memory_slv_seq_c extends uvma_obi_memory_slv_base_seq_c; +class uvma_obi_memory_slv_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_slv_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); // Queue of virtual peripheral sequences to spawn when this sequence is spawned - uvma_obi_memory_vp_base_seq_c vp_seq_q[$]; + uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) vp_seq_q[$]; // Lookup table to trigger sequences when bus address is detected - uvma_obi_memory_vp_base_seq_c vp_seq_table[bit[31:0]]; - - `uvm_object_utils_begin(uvma_obi_memory_slv_seq_c) + uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) vp_seq_table[bit[31:0]]; + + `uvm_object_utils_begin(uvma_obi_memory_slv_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end /** @@ -45,9 +90,18 @@ class uvma_obi_memory_slv_seq_c extends uvma_obi_memory_slv_base_seq_c; * Register sequences with a range of addresses on this OBI * Waiving Verissimo SVTB.32.2.0: Pass strings by reference unless otherwise needed */ - extern virtual function uvma_obi_memory_vp_base_seq_c register_vp_vseq(string name, //@DVT_LINTER_WAIVER "MT20211228_9" disable SVTB.32.2.0 - bit[31:0] start_address, - uvm_object_wrapper seq_type); + extern virtual function uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(uvma_obi_memory_slv_seq_c::AUSER_WIDTH), + .WUSER_WIDTH(uvma_obi_memory_slv_seq_c::WUSER_WIDTH), + .RUSER_WIDTH(uvma_obi_memory_slv_seq_c::RUSER_WIDTH), + .ADDR_WIDTH(uvma_obi_memory_slv_seq_c::ADDR_WIDTH), + .DATA_WIDTH(uvma_obi_memory_slv_seq_c::DATA_WIDTH), + .ID_WIDTH(uvma_obi_memory_slv_seq_c::ID_WIDTH), + .ACHK_WIDTH(uvma_obi_memory_slv_seq_c::ACHK_WIDTH), + .RCHK_WIDTH(uvma_obi_memory_slv_seq_c::RCHK_WIDTH) + ) register_vp_vseq(string name, //@DVT_LINTER_WAIVER "MT20211228_9" disable SVTB.32.2.0 + bit[31:0] start_address, + uvm_object_wrapper seq_type); /** * Main sequence body @@ -175,11 +229,29 @@ task uvma_obi_memory_slv_seq_c::do_mem_operation(ref uvma_obi_memory_mon_trn_c m endtask : do_mem_operation -function uvma_obi_memory_vp_base_seq_c uvma_obi_memory_slv_seq_c::register_vp_vseq(string name, - bit[31:0] start_address, - uvm_object_wrapper seq_type); - - uvma_obi_memory_vp_base_seq_c vp_seq; +function uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(uvma_obi_memory_slv_seq_c::AUSER_WIDTH), + .WUSER_WIDTH(uvma_obi_memory_slv_seq_c::WUSER_WIDTH), + .RUSER_WIDTH(uvma_obi_memory_slv_seq_c::RUSER_WIDTH), + .ADDR_WIDTH(uvma_obi_memory_slv_seq_c::ADDR_WIDTH), + .DATA_WIDTH(uvma_obi_memory_slv_seq_c::DATA_WIDTH), + .ID_WIDTH(uvma_obi_memory_slv_seq_c::ID_WIDTH), + .ACHK_WIDTH(uvma_obi_memory_slv_seq_c::ACHK_WIDTH), + .RCHK_WIDTH(uvma_obi_memory_slv_seq_c::RCHK_WIDTH) +) uvma_obi_memory_slv_seq_c::register_vp_vseq(string name, + bit[31:0] start_address, + uvm_object_wrapper seq_type); + + uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + ) vp_seq; // Create an instance of the sequence type passed in, // Ensure that the sequence type is derived from uvma_obi_memory_vp_base_seq_c diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq_item.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq_item.sv index 6f4340530d..218acd4a60 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq_item.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq_item.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_SLV_SEQ_ITEM_SV__ @@ -26,48 +26,49 @@ * uvma_obi_memory_slv_seq_base_c. */ class uvma_obi_memory_slv_seq_item_c extends uvma_obi_memory_base_seq_item_c; - + // Data rand uvma_obi_memory_data_b_t rdata ; ///< Read data. rand uvma_obi_memory_ruser_b_t ruser ; ///< Response phase User signals. Only valid for read transactions. Undefined for write transactions. rand uvma_obi_memory_id_b_t rid ; ///< Response Phase transaction identifier. rand uvma_obi_memory_err_b_t err ; ///< Error. rand uvma_obi_memory_exokay_b_t exokay ; ///< Atomic acceess response - + rand uvma_obi_memory_rchk_b_t rchk ; ///< checksum + // Metadata rand int unsigned rvalid_latency; ///< Number of clock cycles to wait before driving rvalid for a slave response uvma_obi_memory_mon_trn_c orig_trn ; ///< Monitored transaction to which this seq_item is responding - - + + `uvm_object_utils_begin(uvma_obi_memory_slv_seq_item_c) `uvm_field_int(rdata , UVM_DEFAULT) `uvm_field_int(ruser , UVM_DEFAULT) `uvm_field_int(rid , UVM_DEFAULT) `uvm_field_int(err , UVM_DEFAULT) `uvm_field_int(exokay , UVM_DEFAULT) - - `uvm_field_int(rvalid_latency, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE) - + + `uvm_field_int(rvalid_latency, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE) + `uvm_field_object(orig_trn, UVM_DEFAULT + UVM_NOCOMPARE) `uvm_object_utils_end - - + + constraint defaults_cons { - /*soft*/ err == 0; + /*soft*/ err == 0; } - + /** * Default constructor. */ extern function new(string name="uvma_obi_memory_slv_seq_item"); - + endclass : uvma_obi_memory_slv_seq_item_c function uvma_obi_memory_slv_seq_item_c::new(string name="uvma_obi_memory_slv_seq_item"); - + super.new(name); - + endfunction : new diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_base_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_base_seq.sv index 13250c90c6..e303a03031 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_base_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_base_seq.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Silicon Labs // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_VP_BASE_SEQ_SV__ `define __UVMA_OBI_MEMORY_VP_BASE_SEQ_SV__ @@ -24,23 +24,50 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -virtual class uvma_obi_memory_vp_base_seq_c extends uvma_obi_memory_slv_base_seq_c; +virtual class uvma_obi_memory_vp_base_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_slv_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); uvma_obi_memory_mon_trn_c mon_trn_q[$]; // Used to add transactions to execute (monitored requests) // Base address of this virtual peripheral, used to generated offset index for multi-register // virtual perhipeerals // Should be filled in during registration - bit [31:0] start_address; - - `uvm_field_utils_begin(uvma_obi_memory_vp_base_seq_c) + bit [31:0] start_address; + + `uvm_field_utils_begin(uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_utils_end - + /** * Default constructor. */ extern function new(string name="uvma_obi_memory_vp_base_seq_c"); - + /** * Simple loop that is triggered externally when the main slave sequence detects an address range * claimed by this virtual peripheral @@ -66,9 +93,9 @@ endclass : uvma_obi_memory_vp_base_seq_c function uvma_obi_memory_vp_base_seq_c::new(string name="uvma_obi_memory_vp_base_seq_c"); - + super.new(name); - + endfunction : new @@ -77,7 +104,7 @@ task uvma_obi_memory_vp_base_seq_c::body(); forever begin wait (mon_trn_q.size()); - vp_body(mon_trn_q.pop_front()); + vp_body(mon_trn_q.pop_front()); end endtask : body @@ -89,18 +116,18 @@ function int unsigned uvma_obi_memory_vp_base_seq_c::get_vp_index(uvma_obi_memor // Fatal error if the address in the incoming transaction is less than the configured base address if (mon_trn.address < start_address) begin - `uvm_fatal("FATAL", $sformatf("%s: get_vp_index(), mon_trn.address 0x%08x is less than start address 0x%08x", - this.get_name(), + `uvm_fatal("FATAL", $sformatf("%s: get_vp_index(), mon_trn.address 0x%08x is less than start address 0x%08x", + this.get_name(), mon_trn.address, start_address)); - end + end index = (mon_trn.address - start_address) >> 2; // Fatal if the index is greater than expected if (index >= get_num_words()) begin - `uvm_fatal("FATAL", $sformatf("%s: get_vp_index(), mon_trn.address 0x%08x base address 0x%08x, should only have %0s vp registers", - this.get_name(), + `uvm_fatal("FATAL", $sformatf("%s: get_vp_index(), mon_trn.address 0x%08x base address 0x%08x, should only have %0s vp registers", + this.get_name(), mon_trn.address, start_address, get_num_words())); diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_cycle_counter_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_cycle_counter_seq.sv index 78043dc1b2..d018d5a886 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_cycle_counter_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_cycle_counter_seq.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Silicon Labs // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_VP_CYCLE_COUNTER_SEQ_SV__ `define __UVMA_OBI_MEMORY_VP_CYCLE_COUNTER_SEQ_SV__ @@ -24,16 +24,43 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -class uvma_obi_memory_vp_cycle_counter_seq_c extends uvma_obi_memory_vp_base_seq_c; +class uvma_obi_memory_vp_cycle_counter_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); longint unsigned cycle_counter; protected bit _stop_count_cycles; - `uvm_object_utils_begin(uvma_obi_memory_vp_cycle_counter_seq_c) - `uvm_field_int(cycle_counter, UVM_DEFAULT) + `uvm_object_utils_begin(uvma_obi_memory_vp_cycle_counter_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) + `uvm_field_int(cycle_counter, UVM_DEFAULT) `uvm_object_utils_end - + /** * Default constructor. */ @@ -73,9 +100,9 @@ class uvma_obi_memory_vp_cycle_counter_seq_c extends uvma_obi_memory_vp_base_seq endclass : uvma_obi_memory_vp_cycle_counter_seq_c function uvma_obi_memory_vp_cycle_counter_seq_c::new(string name="uvma_obi_memory_vp_cycle_counter_seq_c"); - + super.new(name); - + endfunction : new @@ -96,11 +123,11 @@ function int unsigned uvma_obi_memory_vp_cycle_counter_seq_c::get_num_words(); endfunction : get_num_words task uvma_obi_memory_vp_cycle_counter_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_trn); - + uvma_obi_memory_slv_seq_item_c slv_rsp; - + `uvm_create(slv_rsp) - + slv_rsp.orig_trn = mon_trn; slv_rsp.err = 1'b0; @@ -144,16 +171,16 @@ task uvma_obi_memory_vp_cycle_counter_seq_c::rw_counter(uvma_obi_memory_mon_trn_ if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin // First stop the thread, reset counter to write data, then restart - + _stop_count_cycles = 1; wait (_stop_count_cycles == 0); cycle_counter = mon_trn.data; - fork + fork count_cycles(); join_none end - else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin + else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin slv_rsp.rdata = cycle_counter; end diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_debug_control_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_debug_control_seq.sv index 9ae6ed2131..ca739c2f22 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_debug_control_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_debug_control_seq.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Silicon Labs // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_VP_DEBUG_CONTROL_SEQ_SV__ `define __UVMA_OBI_MEMORY_VP_DEBUG_CONTROL_SEQ_SV__ @@ -24,11 +24,38 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -virtual class uvma_obi_memory_vp_debug_control_seq_c extends uvma_obi_memory_vp_base_seq_c; - - `uvm_field_utils_begin(uvma_obi_memory_vp_debug_control_seq_c) +virtual class uvma_obi_memory_vp_debug_control_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +) ; + + `uvm_field_utils_begin(uvma_obi_memory_vp_debug_control_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_utils_end - + /** * Default constructor. */ @@ -67,9 +94,9 @@ virtual class uvma_obi_memory_vp_debug_control_seq_c extends uvma_obi_memory_vp_ endclass : uvma_obi_memory_vp_debug_control_seq_c function uvma_obi_memory_vp_debug_control_seq_c::new(string name="uvma_obi_memory_vp_debug_control_seq_c"); - + super.new(name); - + endfunction : new function int unsigned uvma_obi_memory_vp_debug_control_seq_c::get_num_words(); @@ -79,16 +106,16 @@ function int unsigned uvma_obi_memory_vp_debug_control_seq_c::get_num_words(); endfunction : get_num_words task uvma_obi_memory_vp_debug_control_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_trn); - + uvma_obi_memory_slv_seq_item_c slv_rsp; `uvm_create (slv_rsp) - slv_rsp.orig_trn = mon_trn; + slv_rsp.orig_trn = mon_trn; slv_rsp.err = 1'b0; if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin - `uvm_info("VP_VSEQ", $sformatf("Call to virtual peripheral 'vp_debug_control':\n%s", mon_trn.sprint()), UVM_HIGH) + `uvm_info("VP_VSEQ", $sformatf("Call to virtual peripheral 'vp_debug_control':\n%s", mon_trn.sprint()), UVM_HIGH) debug(.dbg_req_value (mon_trn.data[31]), .request_mode (mon_trn.data[30]), .rand_pulse_duration (mon_trn.data[29]), @@ -99,7 +126,7 @@ task uvma_obi_memory_vp_debug_control_seq_c::vp_body(uvma_obi_memory_mon_trn_c m else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin slv_rsp.rdata = 0; end - + add_r_fields(mon_trn, slv_rsp); slv_rsp.set_sequencer(p_sequencer); `uvm_send(slv_rsp) diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_directed_slv_resp_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_directed_slv_resp_seq.sv index 91f531722c..8235cff2b0 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_directed_slv_resp_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_directed_slv_resp_seq.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Silicon Labs // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_VP_DIRECTED_SLV_RESP_SEQ_SV__ `define __UVMA_OBI_MEMORY_VP_DIRECTED_SLV_RESP_SEQ_SV__ @@ -24,7 +24,26 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -class uvma_obi_memory_vp_directed_slv_resp_seq_c#(OBI_PERIPHS=1) extends uvma_obi_memory_vp_base_seq_c; +class uvma_obi_memory_vp_directed_slv_resp_seq_c#( + OBI_PERIPHS=1, + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); localparam ERR_ADDR_MIN_INDEX = 0; localparam ERR_ADDR_MAX_INDEX = 1; @@ -38,14 +57,24 @@ class uvma_obi_memory_vp_directed_slv_resp_seq_c#(OBI_PERIPHS=1) extends uvma_ob // An array of OBI memory configurations // This enables a single set of virtual peripheral registers (6*OBI_PERIPHS) to control - // OBI_PERIPHS number of OBIs + // OBI_PERIPHS number of OBIs // For example, in a typical OBI-I, OBI-D configuration, only the OBI-D is writable // but we would also need to control the OBI-I as well uvma_obi_memory_cfg_c obi_cfg[]; - `uvm_object_param_utils_begin(uvma_obi_memory_vp_directed_slv_resp_seq_c#(OBI_PERIPHS)) + `uvm_object_param_utils_begin(uvma_obi_memory_vp_directed_slv_resp_seq_c#( + .OBI_PERIPHS(OBI_PERIPHS), + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end - + /** * Default constructor. */ @@ -65,15 +94,15 @@ class uvma_obi_memory_vp_directed_slv_resp_seq_c#(OBI_PERIPHS=1) extends uvma_ob endclass : uvma_obi_memory_vp_directed_slv_resp_seq_c function uvma_obi_memory_vp_directed_slv_resp_seq_c::new(string name="uvma_obi_memory_vp_directed_slv_resp_seq_c"); - + super.new(name); - + obi_cfg = new[OBI_PERIPHS]; endfunction : new function int unsigned uvma_obi_memory_vp_directed_slv_resp_seq_c::get_num_words(); - + return WORDS_PER_OBI * OBI_PERIPHS; endfunction : get_num_words @@ -83,9 +112,9 @@ task uvma_obi_memory_vp_directed_slv_resp_seq_c::vp_body(uvma_obi_memory_mon_trn int unsigned obi_index; uvma_obi_memory_slv_seq_item_c slv_rsp; - + `uvm_create(slv_rsp) - + slv_rsp.orig_trn = mon_trn; slv_rsp.err = 1'b0; diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_interrupt_timer_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_interrupt_timer_seq.sv index 472eeb92cd..011dff395b 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_interrupt_timer_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_interrupt_timer_seq.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Silicon Labs // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_VP_INTERRUPT_TIMER_SEQ_SV__ `define __UVMA_OBI_MEMORY_VP_INTERRUPT_TIMER_SEQ_SV__ @@ -24,17 +24,56 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -virtual class uvma_obi_memory_vp_interrupt_timer_seq_c extends uvma_obi_memory_vp_base_seq_c; +virtual class uvma_obi_memory_vp_interrupt_timer_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +) ; bit[31:0] interrupt_value; int unsigned interrupt_timer_value; - event interrupt_timer_start; - - `uvm_field_utils_begin(uvma_obi_memory_vp_interrupt_timer_seq_c) + event interrupt_timer_start; + + typedef struct packed { + logic irq; + logic [10:0] id; + logic [7:0] level; + logic [1:0] priv; + logic shv; + } clic_irq_bundle_t; + + clic_irq_bundle_t clic_value; + + + `uvm_field_utils_begin(uvma_obi_memory_vp_interrupt_timer_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_int(interrupt_value, UVM_DEFAULT) `uvm_field_int(interrupt_timer_value, UVM_DEFAULT) + `uvm_field_int(clic_value, UVM_DEFAULT) `uvm_field_utils_end - + /** * Default constructor. */ @@ -68,9 +107,9 @@ virtual class uvma_obi_memory_vp_interrupt_timer_seq_c extends uvma_obi_memory_v endclass : uvma_obi_memory_vp_interrupt_timer_seq_c function uvma_obi_memory_vp_interrupt_timer_seq_c::new(string name="uvma_obi_memory_vp_interrupt_timer_seq_c"); - + super.new(name); - + endfunction : new @@ -87,22 +126,26 @@ endtask : body function int unsigned uvma_obi_memory_vp_interrupt_timer_seq_c::get_num_words(); return 2; - + endfunction : get_num_words task uvma_obi_memory_vp_interrupt_timer_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_trn); - + uvma_obi_memory_slv_seq_item_c slv_rsp; `uvm_create(slv_rsp) - slv_rsp.orig_trn = mon_trn; + slv_rsp.orig_trn = mon_trn; slv_rsp.err = 1'b0; if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin `uvm_info("VP_VSEQ", $sformatf("Call to virtual peripheral 'interrupt_timer_control':\n%s", mon_trn.sprint()), UVM_HIGH) if (get_vp_index(mon_trn) == 0) begin - interrupt_value = mon_trn.data; + if (cfg.basic_interrupts_enabled) begin + interrupt_value = mon_trn.data; + end else if (cfg.clic_interrupts_enabled) begin + clic_value = mon_trn.data; + end end else if (get_vp_index(mon_trn) == 1) begin interrupt_timer_value = mon_trn.data; @@ -110,12 +153,12 @@ task uvma_obi_memory_vp_interrupt_timer_seq_c::vp_body(uvma_obi_memory_mon_trn_c end else begin `uvm_info("VP_VSEQ", $sformatf("Call to virtual peripheral 'interrupt_timer_control':\n%s", mon_trn.sprint()), UVM_HIGH) - end + end end else if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin slv_rsp.rdata = 0; end - + add_r_fields(mon_trn, slv_rsp); slv_rsp.set_sequencer(p_sequencer); `uvm_send(slv_rsp) diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_rand_num_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_rand_num_seq.sv index 644cde56d7..9f8337774e 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_rand_num_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_rand_num_seq.sv @@ -24,11 +24,38 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -class uvma_obi_memory_vp_rand_num_seq_c extends uvma_obi_memory_vp_base_seq_c; +class uvma_obi_memory_vp_rand_num_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +); rand uvma_obi_memory_data_b_t rdata; - `uvm_object_utils_begin(uvma_obi_memory_vp_rand_num_seq_c) + `uvm_object_utils_begin(uvma_obi_memory_vp_rand_num_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_object_utils_end /** diff --git a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_sig_writer_seq.sv b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_sig_writer_seq.sv index 5f3c6cdac9..f403ecd049 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_sig_writer_seq.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_sig_writer_seq.sv @@ -24,7 +24,25 @@ * Virtual sequence implementing the cv32e40x virtual peripherals. * TODO Move most of the functionality to a cv32e env base class. */ -virtual class uvma_obi_memory_vp_sig_writer_seq_c extends uvma_obi_memory_vp_base_seq_c; +virtual class uvma_obi_memory_vp_sig_writer_seq_c#( + parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. + parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. + parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. + parameter ADDR_WIDTH = `UVMA_OBI_MEMORY_ADDR_DEFAULT_WIDTH , ///< Width of the addr signal. + parameter DATA_WIDTH = `UVMA_OBI_MEMORY_DATA_DEFAULT_WIDTH , ///< Width of the rdata and wdata signals. be width is DATA_WIDTH / 8. Valid DATA_WIDTH settings are 32 and 64. + parameter ID_WIDTH = `UVMA_OBI_MEMORY_ID_DEFAULT_WIDTH , ///< Width of the aid and rid signals. + parameter ACHK_WIDTH = `UVMA_OBI_MEMORY_ACHK_DEFAULT_WIDTH , ///< Width of the achk signal. + parameter RCHK_WIDTH = `UVMA_OBI_MEMORY_RCHK_DEFAULT_WIDTH ///< Width of the rchk signal. +) extends uvma_obi_memory_vp_base_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) +) ; localparam NUM_WORDS = 3; @@ -34,7 +52,16 @@ virtual class uvma_obi_memory_vp_sig_writer_seq_c extends uvma_obi_memory_vp_bas int sig_fd = 0; bit use_sig_file = 0; - `uvm_field_utils_begin(uvma_obi_memory_vp_sig_writer_seq_c) + `uvm_field_utils_begin(uvma_obi_memory_vp_sig_writer_seq_c#( + .AUSER_WIDTH(AUSER_WIDTH), + .WUSER_WIDTH(WUSER_WIDTH), + .RUSER_WIDTH(RUSER_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .ID_WIDTH(ID_WIDTH), + .ACHK_WIDTH(ACHK_WIDTH), + .RCHK_WIDTH(RCHK_WIDTH) + )) `uvm_field_int(signature_start_address, UVM_DEFAULT) `uvm_field_int(signature_end_address, UVM_DEFAULT) `uvm_field_utils_end @@ -97,9 +124,9 @@ task uvma_obi_memory_vp_sig_writer_seq_c::vp_body(uvma_obi_memory_mon_trn_c mon_ if (mon_trn.access_type == UVMA_OBI_MEMORY_ACCESS_WRITE) begin case (get_vp_index(mon_trn)) 0: signature_start_address = mon_trn.data; - 1: signature_end_address = mon_trn.data; - 2: begin + 1: begin + signature_end_address = mon_trn.data; for (int unsigned ii=signature_start_address; ii be_inside_contiguous_be; + req && we |-> be_inside_contiguous_be; endproperty : p_be_contiguous - a_be_contiguous : assert property(p_be_contiguous) - else - `uvm_error(info_tag, $sformatf("be of 0x%0x was not contiguous", $sampled(be))); + + a_be_contiguous : assert property( + p_be_contiguous + ) else `uvm_error(info_tag, $sformatf("be of 0x%0x was not contiguous", $sampled(be))); + // R-8 Data address LSBs must be consistent with byte enables on writes - function bit [1:0] get_addr_lsb(bit[3:0] be); + function automatic bit [1:0] get_addr_lsb(bit[3:0] be); casex (be) 4'b???1: return 0; 4'b??10: return 1; diff --git a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_assert_if_wrp.sv b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_assert_if_wrp.sv index fdb4ec3f9f..0d84aadf68 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_assert_if_wrp.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_assert_if_wrp.sv @@ -14,7 +14,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -// This module facilitates easy connection of a uvma_obi_memory_if instance to the assertion module, +// This module facilitates easy connection of a uvma_obi_memory_if_t instance to the assertion module, // which has individual wire ports module uvma_obi_memory_assert_if_wrp @@ -31,7 +31,7 @@ module uvma_obi_memory_assert_if_wrp parameter bit IS_1P2 = 0 ) ( - uvma_obi_memory_if obi + uvma_obi_memory_if_t obi ); diff --git a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if.sv b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if.sv index 06014957cc..8100c6e8de 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_IF_SV__ @@ -25,7 +25,7 @@ * Encapsulates all signals and clocking of Open Bus Interface interface. Used * by monitor (uvma_obi_mon_c) and driver (uvma_obi_drv_c). */ -interface uvma_obi_memory_if #( +interface uvma_obi_memory_if_t #( parameter AUSER_WIDTH = `UVMA_OBI_MEMORY_AUSER_DEFAULT_WIDTH, ///< Width of the auser signal. RI5CY, Ibex, CV32E40* do not have the auser signal. parameter WUSER_WIDTH = `UVMA_OBI_MEMORY_WUSER_DEFAULT_WIDTH, ///< Width of the wuser signal. RI5CY, Ibex, CV32E40* do not have the wuser signal. parameter RUSER_WIDTH = `UVMA_OBI_MEMORY_RUSER_DEFAULT_WIDTH, ///< Width of the ruser signal. RI5CY, Ibex, CV32E40* do not have the ruser signal. @@ -39,7 +39,7 @@ interface uvma_obi_memory_if #( input logic clk , ///< The bus clock times all bus transfers. All signal timings are related to the rising edge of clk. input logic reset_n ///< The bus reset signal is active LOW and resets the system and the bus. This is the only active LOW signal. ); - + // 'A Channel' signals wire req ; ///< Address transfer request. req=1 signals the availability of valid address phase signals. wire gnt ; ///< Grant. Ready to accept address transfer. Address transfer is accepted on rising clk with req=1 and gnt=1. @@ -53,11 +53,12 @@ interface uvma_obi_memory_if #( wire [5:0] atop ; ///< Atomic Operation. wire [1:0] memtype; ///< Memory type attributes. wire [2:0] prot ; ///< Protection attributes. + wire dbg ; ///< debug access wire reqpar ; ///< Parity bit for req signal (odd parity). wire gntpar ; ///< Parity bit for gnt signal (odd parity). wire [(ACHK_WIDTH-1):0] achk ; ///< Checksum for address phase signals (except achk itself). - - + + // 'R Channel' signals wire rvalid ; ///< Response transfer request. rvalid=1 signals the availability of valid response phase signals. Used for both reads and writes. wire rready ; ///< Ready to accept response transfer. Response transfer is accepted on rising clk with rvalid=1 and rready=1. @@ -69,7 +70,7 @@ interface uvma_obi_memory_if #( wire rvalidpar; ///< Parity bit for rvalid signal (odd parity). wire rreadypar; ///< Parity bit for rready signal (odd parity). wire [(RCHK_WIDTH-1):0] rchk ; ///< Checksum for address phase signals (except rchk itself). - + /** * Used by DUT in 'mstr' mode. */ @@ -95,12 +96,13 @@ interface uvma_obi_memory_if #( atop , memtype , prot , + dbg , reqpar , achk , rready , rreadypar; endclocking : dut_mstr_cb - + /** * Used by DUT in 'slv' mode. */ @@ -116,6 +118,7 @@ interface uvma_obi_memory_if #( atop , memtype , prot , + dbg , reqpar , achk , rready , @@ -131,7 +134,7 @@ interface uvma_obi_memory_if #( rvalidpar, rchk ; endclocking : dut_slv_cb - + /** * Used by uvma_obi_memory_drv_c. */ @@ -157,12 +160,13 @@ interface uvma_obi_memory_if #( atop , memtype , prot , + dbg , reqpar , achk , rready , rreadypar; endclocking : drv_mstr_cb - + /** * Used by uvma_obi_memory_drv_c. */ @@ -178,6 +182,7 @@ interface uvma_obi_memory_if #( atop , memtype , prot , + dbg , reqpar , achk , rready , @@ -193,7 +198,7 @@ interface uvma_obi_memory_if #( rvalidpar, rchk ; endclocking : drv_slv_cb - + /** * Used by uvma_obi_memory_mon_c. */ @@ -210,6 +215,7 @@ interface uvma_obi_memory_if #( atop , memtype , prot , + dbg , reqpar , gntpar , achk , @@ -224,15 +230,15 @@ interface uvma_obi_memory_if #( rreadypar, rchk ; endclocking : mon_cb - - + + modport dut_mstr_mp (clocking dut_mstr_cb); ///< Used by DUT in 'mstr' mode. modport dut_slv_mp (clocking dut_slv_cb ); ///< Used by DUT in 'slv' mode. modport active_mstr_mp(clocking drv_mstr_cb); ///< Used by uvma_obi_drv_c in 'mstr' mode. modport active_slv_mp (clocking drv_slv_cb ); ///< Used by uvma_obi_drv_c in 'slv' mode. modport passive_mp (clocking mon_cb ); ///< Used by uvma_obi_mon_c. -endinterface : uvma_obi_memory_if +endinterface : uvma_obi_memory_if_t `endif // __UVMA_OBI_MEMORY_IF_SV__ diff --git a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if_chkr.sv b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if_chkr.sv index 08159e12e5..134258e93a 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if_chkr.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_if_chkr.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_IF_CHKR_SV__ @@ -25,11 +25,11 @@ * Encapsulates assertions targeting uvma_obi_if. */ module uvma_obi_memory_if_chkr( - uvma_obi_memory_if obi_memory_if + uvma_obi_memory_if_t obi_memory_if ); - + // TODO Add assertions to uvma_obi_memory_if_chkr - + endmodule : uvma_obi_memory_if_chkr diff --git a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_macros.sv b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_macros.sv index 10faf1f219..692c79fafd 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_macros.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_macros.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_MACROS_SV__ diff --git a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_tdefs.sv b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_tdefs.sv index e9bf2487a3..f2f38f9d2d 100644 --- a/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_tdefs.sv +++ b/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_tdefs.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2021 OpenHW Group // Copyright 2021 Datum Technology Corporation // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// +// // Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may // not use this file except in compliance with the License, or, at your option, // the Apache License version 2.0. You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/SHL-2.1/ -// +// // Unless required by applicable law or agreed to in writing, any work // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the // License for the specific language governing permissions and limitations // under the License. -// +// `ifndef __UVMA_OBI_MEMORY_TDEFS_SV__ @@ -34,6 +34,7 @@ typedef logic uvma_obi_memory_exoka typedef logic [5:0] uvma_obi_memory_atop_l_t ; typedef logic [1:0] uvma_obi_memory_memtype_l_t; typedef logic [2:0] uvma_obi_memory_prot_l_t ; +typedef logic uvma_obi_memory_dbg_l_t ; typedef logic [(`UVMA_OBI_MEMORY_ACHK_MAX_WIDTH -1):0] uvma_obi_memory_achk_l_t ; typedef logic [(`UVMA_OBI_MEMORY_RCHK_MAX_WIDTH -1):0] uvma_obi_memory_rchk_l_t ; @@ -50,13 +51,17 @@ typedef bit uvma_obi_memory_exokay_ typedef bit [5:0] uvma_obi_memory_atop_b_t ; typedef bit [1:0] uvma_obi_memory_memtype_b_t; typedef bit [2:0] uvma_obi_memory_prot_b_t ; +typedef bit uvma_obi_memory_dbg_b_t ; typedef bit [(`UVMA_OBI_MEMORY_ACHK_MAX_WIDTH -1):0] uvma_obi_memory_achk_b_t ; typedef bit [(`UVMA_OBI_MEMORY_RCHK_MAX_WIDTH -1):0] uvma_obi_memory_rchk_b_t ; typedef enum { UVMA_OBI_MEMORY_VERSION_1P1, - UVMA_OBI_MEMORY_VERSION_1P2 + UVMA_OBI_MEMORY_VERSION_1P2, + UVMA_OBI_MEMORY_VERSION_1P3, + UVMA_OBI_MEMORY_VERSION_1P4, + UVMA_OBI_MEMORY_VERSION_1P5 } uvma_obi_memory_version_enum; typedef enum { @@ -111,4 +116,10 @@ typedef enum { UVMA_OBI_MEMORY_DRV_SLV_EXOKAY_MODE_RANDOM } uvma_obi_memory_drv_slv_exokay_mode_enum; +typedef enum { + UVMA_OBI_MEMORY_CHK_TIED, + UVMA_OBI_MEMORY_CHK_CV32E40S +} uvma_obi_memory_checksum_scheme; + + `endif // __UVMA_OBI_MEMORY_TDEFS_SV__ diff --git a/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_mon.sv b/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_mon.sv index d8168ad361..577d28e191 100644 --- a/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_mon.sv +++ b/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_mon.sv @@ -99,7 +99,7 @@ function void uvma_pma_mon_c::process_trn(ref uvma_pma_mon_trn_c trn); trn.cfg = cfg; trn.__originator = get_full_name(); - `uvm_info("${name_uppecase}_MON", $sformatf("Sampled transaction from the virtual interface:\n%s", trn.sprint()), UVM_HIGH) + `uvm_info("PMA_MON", $sformatf("Sampled transaction from the virtual interface:\n%s", trn.sprint()), UVM_HIGH) `uvml_hrtbt() endfunction : process_trn diff --git a/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_sb.sv b/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_sb.sv index 8b3bc36ff6..35ff18d6c4 100644 --- a/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_sb.sv +++ b/lib/uvm_agents/uvma_pma/src/comps/uvma_pma_sb.sv @@ -106,6 +106,11 @@ class uvma_pma_sb_c#(int ILEN=DEFAULT_ILEN, */ extern virtual function void check_obi_d_default_region(uvma_obi_memory_mon_trn_c obi); + /** + * Check for overrides to "standard" pma regions, e.g. debug override + */ + extern virtual function int get_pma_override_region(uvma_obi_memory_mon_trn_c obi); + /** * Common print report state */ @@ -228,6 +233,19 @@ function void uvma_pma_sb_c::print_checked_stats(); endfunction : print_checked_stats +function int uvma_pma_sb_c::get_pma_override_region(uvma_obi_memory_mon_trn_c obi); + int index; + + if (obi.dbg && cfg.region_override_condition == uvma_pma_cfg_c#(ILEN,XLEN)::PMA_OVERRIDE_DEBUG) begin + index = cfg.get_pma_override_region_for_addr(obi.address); + end else begin + index = -1; + end + + return index; + +endfunction : get_pma_override_region + function void uvma_pma_sb_c::check_obi_i_deconfigured(uvma_obi_memory_mon_trn_c obi); // Check: Bufferable bit must be 0 in OBI for instruction fetches @@ -253,53 +271,111 @@ endfunction : check_obi_i_deconfigured function void uvma_pma_sb_c::check_obi_i_default_region(uvma_obi_memory_mon_trn_c obi); - // Check: Bufferable bit must be 0 in OBI for instruction fetches - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin - `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit set for PMA default region", - obi.access_type.name(), obi.address)); - end - - // Check: Cacheable bit must be 0 in OBI - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT]) begin - `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x cacheable bit set for PMA default region", - obi.access_type.name(), obi.address)); - end - - // Check: atomic attributes should be 0 - if (obi.atop) begin - `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x atop is not zero, OBI: 0x%0x", - obi.access_type.name(), obi.address, - obi.atop)); + int override_region; + + override_region = get_pma_override_region(obi); + if (override_region != -1) begin + if (!cfg.region_overrides[override_region].main) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d instruction fetch from I/O memory", + obi.access_type.name(), obi.address, override_region)); + end + + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT] != cfg.region_overrides[override_region].bufferable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit wrong for PMA override region", + obi.access_type.name(), obi.address)); + end + + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT] != cfg.region_overrides[override_region].cacheable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", + obi.access_type.name(), obi.address, override_region, + obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT], cfg.region_overrides[override_region].cacheable)); + end + + // TODO: this needs to be modified when atomics are introduced for X to preserve code compatibility + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, region: %0d atop is not zero, OBI: 0x%0x", + obi.access_type.name(), obi.address, override_region, + obi.atop)); + end + end else begin + // Check: Bufferable bit must be 0 in OBI for instruction fetches + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit set for PMA default region", + obi.access_type.name(), obi.address)); + end + + // Check: Cacheable bit must be 0 in OBI + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT]) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x cacheable bit set for PMA default region", + obi.access_type.name(), obi.address)); + end + + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x atop is not zero, OBI: 0x%0x", + obi.access_type.name(), obi.address, + obi.atop)); + end end endfunction : check_obi_i_default_region function void uvma_pma_sb_c::check_obi_i_mapped_region(uvma_obi_memory_mon_trn_c obi, int index); - // Check: Must be main memory - if (!cfg.regions[index].main) begin - `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, region: %0d instruction fetch from I/O memory", - obi.access_type.name(), obi.address, index)); - end - - // Check: Bufferable bit must be 0 in OBI for instruction fetches - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin - `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit set for PMA default region", - obi.access_type.name(), obi.address)); - end - - // Check: Cacheable bit must match mem_type[0] in OBI - if (obi.memtype[1] != cfg.regions[index].cacheable) begin - `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", - obi.access_type.name(), obi.address, index, - obi.memtype[1], cfg.regions[index].cacheable)); - end - - // Check: atomic attributes should be 0 - if (obi.atop) begin - `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, region: %0d atop is not zero, OBI: 0x%0x", - obi.access_type.name(), obi.address, index, - obi.atop)); + int override_region; + + override_region = get_pma_override_region(obi); + if (override_region != -1) begin + if (!cfg.region_overrides[override_region].main) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d instruction fetch from I/O memory", + obi.access_type.name(), obi.address, override_region)); + end + + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT] != cfg.region_overrides[override_region].bufferable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit wrong for PMA override region", + obi.access_type.name(), obi.address)); + end + + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT] != cfg.region_overrides[override_region].cacheable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", + obi.access_type.name(), obi.address, override_region, + obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT], cfg.region_overrides[override_region].cacheable)); + end + + // TODO: this needs to be modified when atomics are introduced for X to preserve code compatibility + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d atop is not zero, OBI: 0x%0x", + obi.access_type.name(), obi.address, override_region, + obi.atop)); + end + end else begin + // Check: Must be main memory + if (!cfg.regions[index].main) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, region: %0d instruction fetch from I/O memory", + obi.access_type.name(), obi.address, index)); + end + + // Check: Bufferable bit must be 0 in OBI for instruction fetches + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit set for PMA default region", + obi.access_type.name(), obi.address)); + end + + // Check: Cacheable bit must match mem_type[0] in OBI + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT] != cfg.regions[index].cacheable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", + obi.access_type.name(), obi.address, index, + obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT], cfg.regions[index].cacheable)); + end + + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, region: %0d atop is not zero, OBI: 0x%0x", + obi.access_type.name(), obi.address, index, + obi.atop)); + end end endfunction : check_obi_i_mapped_region @@ -322,23 +398,47 @@ endfunction : check_obi_d_deconfigured function void uvma_pma_sb_c::check_obi_d_default_region(uvma_obi_memory_mon_trn_c obi); - // Check: Bufferable bit must be 0 in OBI - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin - `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x bufferable bit set for PMA default region", - obi.access_type.name(), obi.address)); - end + int override_region; + + override_region = get_pma_override_region(obi); + if (override_region != -1) begin + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT] != cfg.region_overrides[override_region].bufferable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit wrong for PMA override region", + obi.access_type.name(), obi.address)); + end + + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT] != cfg.region_overrides[override_region].cacheable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", + obi.access_type.name(), obi.address, override_region, + obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT], cfg.region_overrides[override_region].cacheable)); + end + + // TODO: this needs to be modified when atomics are introduced for X to preserve code compatibility + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d atop is not zero, OBI: 0x%0x", + obi.access_type.name(), obi.address, override_region, + obi.atop)); + end + end else begin + // Check: Bufferable bit must be 0 in OBI + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin + `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x bufferable bit set for PMA default region", + obi.access_type.name(), obi.address)); + end - // Check: Cacheable bit must be 0 in OBI - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT]) begin - `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x cacheable bit set for PMA default region", - obi.access_type.name(), obi.address)); - end + // Check: Cacheable bit must be 0 in OBI + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT]) begin + `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x cacheable bit set for PMA default region", + obi.access_type.name(), obi.address)); + end - // Check: atomic attributes should be 0 - if (obi.atop) begin - `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x atop is not zero for PMA default region, OBI: 0x%0x", - obi.access_type.name(), obi.address, - obi.atop)); + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x atop is not zero for PMA default region, OBI: 0x%0x", + obi.access_type.name(), obi.address, + obi.atop)); + end end endfunction : check_obi_d_default_region @@ -346,35 +446,58 @@ endfunction : check_obi_d_default_region function void uvma_pma_sb_c::check_obi_d_mapped_region(uvma_obi_memory_mon_trn_c obi, int index); - - if (obi.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin - // Check: Bufferable bit must be 0 in OBI for data loads - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin - `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d bufferable bit set for data load", - obi.access_type.name(), obi.address, index)); + int override_region; + + override_region = get_pma_override_region(obi); + if (override_region != -1) begin + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT] != cfg.region_overrides[override_region].bufferable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x bufferable bit wrong for PMA override region", + obi.access_type.name(), obi.address)); + end + + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT] != cfg.region_overrides[override_region].cacheable) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", + obi.access_type.name(), obi.address, override_region, + obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT], cfg.region_overrides[override_region].cacheable)); + end + + // TODO: this needs to be modified when atomics are introduced for X to preserve code compatibility + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBII", $sformatf("OBI I %s address: 0x%08x, override region: %0d atop is not zero, OBI: 0x%0x", + obi.access_type.name(), obi.address, override_region, + obi.atop)); + end + end else begin + if (obi.access_type == UVMA_OBI_MEMORY_ACCESS_READ) begin + // Check: Bufferable bit must be 0 in OBI for data loads + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT]) begin + `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d bufferable bit set for data load", + obi.access_type.name(), obi.address, index)); + end end - end - else begin - // Check: Bufferable bit must match mem_type[0] in OBI - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT] != cfg.regions[index].bufferable) begin - `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d bufferable bit mismatch, OBI: %0d, PMA: %0d", - obi.access_type.name(), obi.address, index, - obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT], cfg.regions[index].bufferable)); + else begin + // Check: Bufferable bit must match mem_type[0] in OBI + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT] != cfg.regions[index].bufferable) begin + `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d bufferable bit mismatch, OBI: %0d, PMA: %0d", + obi.access_type.name(), obi.address, index, + obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_BUFFERABLE_BIT], cfg.regions[index].bufferable)); + end end - end - // Check: Cacheable bit must match mem_type[0] in OBI - if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT] != cfg.regions[index].cacheable) begin - `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", - obi.access_type.name(), obi.address, index, - obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT], cfg.regions[index].cacheable)); - end + // Check: Cacheable bit must match mem_type[0] in OBI + if (obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT] != cfg.regions[index].cacheable) begin + `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d cacheable bit mismatch, OBI: %0d, PMA: %0d", + obi.access_type.name(), obi.address, index, + obi.memtype[UVMA_OBI_MEMORY_MEMTYPE_CACHEABLE_BIT], cfg.regions[index].cacheable)); + end - // Check: atomic attributes should be 0 - if (obi.atop) begin - `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d atop is not zero, OBI: 0x%0x", - obi.access_type.name(), obi.address, index, - obi.atop)); + // Check: atomic attributes should be 0 + if (obi.atop) begin + `uvm_error("PMAOBID", $sformatf("OBI D %s address: 0x%08x, region: %0d atop is not zero, OBI: 0x%0x", + obi.access_type.name(), obi.address, index, + obi.atop)); + end end endfunction : check_obi_d_mapped_region diff --git a/lib/uvm_agents/uvma_pma/src/obj/uvma_pma_cfg.sv b/lib/uvm_agents/uvma_pma/src/obj/uvma_pma_cfg.sv index d85905e447..5a209235db 100644 --- a/lib/uvm_agents/uvma_pma/src/obj/uvma_pma_cfg.sv +++ b/lib/uvm_agents/uvma_pma/src/obj/uvma_pma_cfg.sv @@ -19,6 +19,12 @@ class uvma_pma_cfg_c#(int ILEN=DEFAULT_ILEN, int XLEN=DEFAULT_XLEN) extends uvm_object; + typedef enum { + PMA_OVERRIDE_NONE, + PMA_OVERRIDE_CUSTOM, + PMA_OVERRIDE_DEBUG + } region_override_condition_e; + // Generic options rand bit enabled; rand uvm_active_passive_enum is_active; @@ -30,13 +36,21 @@ class uvma_pma_cfg_c#(int ILEN=DEFAULT_ILEN, // PMA regions uvma_core_cntrl_pma_region_c regions[]; + // For special cases where an override may be required + uvma_core_cntrl_pma_region_c region_overrides[]; + + // Region override cause + region_override_condition_e region_override_condition = PMA_OVERRIDE_NONE; + `uvm_object_param_utils_begin(uvma_pma_cfg_c#(ILEN,XLEN)) - `uvm_field_int ( enabled , UVM_DEFAULT) - `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT) - `uvm_field_int ( scoreboard_enabled, UVM_DEFAULT) - `uvm_field_int ( cov_model_enabled , UVM_DEFAULT) - `uvm_field_int ( trn_log_enabled , UVM_DEFAULT) - `uvm_field_array_object( regions , UVM_DEFAULT) + `uvm_field_int ( enabled , UVM_DEFAULT) + `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT) + `uvm_field_int ( scoreboard_enabled , UVM_DEFAULT) + `uvm_field_int ( cov_model_enabled , UVM_DEFAULT) + `uvm_field_int ( trn_log_enabled , UVM_DEFAULT) + `uvm_field_array_object( regions , UVM_DEFAULT) + `uvm_field_array_object( region_overrides , UVM_DEFAULT) + `uvm_field_enum(region_override_condition_e, region_override_condition, UVM_DEFAULT) `uvm_object_utils_end @@ -62,6 +76,11 @@ class uvma_pma_cfg_c#(int ILEN=DEFAULT_ILEN, */ extern virtual function int get_pma_region_for_addr(bit [XLEN-1:0] addr); + /** + * Return PMA override region index for address, returns -1 if not mapped + */ + extern virtual function int get_pma_override_region_for_addr(bit[XLEN-1:0] addr); + endclass : uvma_pma_cfg_c @@ -84,5 +103,15 @@ function int uvma_pma_cfg_c::get_pma_region_for_addr(bit[XLEN-1:0] addr); endfunction : get_pma_region_for_addr +function int uvma_pma_cfg_c::get_pma_override_region_for_addr(bit[XLEN-1:0] addr); + + for (int i = 0; i < region_overrides.size(); i++) begin + if (region_overrides[i].is_addr_in_region(addr, 1 /* include upper address boundary*/)) + return i; + end + + return -1; + +endfunction : get_pma_override_region_for_addr `endif // __UVMA_PMA_CFG_SV__ diff --git a/lib/uvm_agents/uvma_rvfi/seq/uvma_rvfi_instr_seq_item.sv b/lib/uvm_agents/uvma_rvfi/seq/uvma_rvfi_instr_seq_item.sv index 520918023b..5e108409fa 100644 --- a/lib/uvm_agents/uvma_rvfi/seq/uvma_rvfi_instr_seq_item.sv +++ b/lib/uvm_agents/uvma_rvfi/seq/uvma_rvfi_instr_seq_item.sv @@ -28,9 +28,9 @@ class uvma_rvfi_instr_seq_item_c#(int ILEN=DEFAULT_ILEN, rand bit [CYCLE_CNT_WL-1:0] cycle_cnt; rand bit [ORDER_WL-1:0] order; rand bit [ILEN-1:0] insn; - rand bit [TRAP_WL-1:0] trap; + rand rvfi_trap_t trap; rand bit halt; - rand bit intr; + rand rvfi_intr_t intr; rand uvma_rvfi_mode mode; rand bit [IXL_WL-1:0] ixl; rand bit [RVFI_DBG_WL-1:0] dbg; @@ -40,8 +40,8 @@ class uvma_rvfi_instr_seq_item_c#(int ILEN=DEFAULT_ILEN, rand bit insn_interrupt; rand int unsigned insn_interrupt_id; rand bit insn_bus_fault; - rand bit insn_nmi_store_fault; - rand bit insn_nmi_load_fault; + rand bit insn_nmi; + rand int unsigned insn_nmi_cause; rand bit [XLEN-1:0] pc_rdata; rand bit [XLEN-1:0] pc_wdata; @@ -61,11 +61,17 @@ class uvma_rvfi_instr_seq_item_c#(int ILEN=DEFAULT_ILEN, rand bit [GPR_ADDR_WL-1:0] rd2_addr; rand bit [XLEN-1:0] rd2_wdata; - rand bit [XLEN-1:0] mem_addr; - rand bit [XLEN-1:0] mem_rdata; - rand bit [XLEN-1:0] mem_rmask; - rand bit [XLEN-1:0] mem_wdata; - rand bit [XLEN-1:0] mem_wmask; + rand bit [(32*XLEN)-1:0] gpr_rdata; + rand bit [(32)-1:0] gpr_rmask; + rand bit [(32*XLEN)-1:0] gpr_wdata; + rand bit [(32)-1:0] gpr_wmask; + + + rand bit [(NMEM*XLEN)-1:0] mem_addr; + rand bit [(NMEM*XLEN)-1:0] mem_rdata; + rand bit [(NMEM*XLEN/8)-1:0] mem_rmask; + rand bit [(NMEM*XLEN)-1:0] mem_wdata; + rand bit [(NMEM*XLEN/8)-1:0] mem_wmask; uvma_rvfi_csr_seq_item_c csrs[string]; @@ -84,8 +90,8 @@ class uvma_rvfi_instr_seq_item_c#(int ILEN=DEFAULT_ILEN, `uvm_field_int(insn_interrupt, UVM_DEFAULT) `uvm_field_int(insn_interrupt_id, UVM_DEFAULT) `uvm_field_int(insn_bus_fault, UVM_DEFAULT) - `uvm_field_int(insn_nmi_load_fault, UVM_DEFAULT) - `uvm_field_int(insn_nmi_store_fault, UVM_DEFAULT) + `uvm_field_int(insn_nmi, UVM_DEFAULT) + `uvm_field_int(insn_nmi_cause, UVM_DEFAULT) `uvm_field_enum(uvma_rvfi_mode, mode, UVM_DEFAULT) `uvm_field_int(ixl, UVM_DEFAULT) `uvm_field_int(pc_rdata, UVM_DEFAULT) @@ -100,6 +106,10 @@ class uvma_rvfi_instr_seq_item_c#(int ILEN=DEFAULT_ILEN, `uvm_field_int(rd1_wdata, UVM_DEFAULT) `uvm_field_int(rd2_addr, UVM_DEFAULT) `uvm_field_int(rd2_wdata, UVM_DEFAULT) + `uvm_field_int(gpr_rmask, UVM_DEFAULT) + `uvm_field_int(gpr_rdata, UVM_DEFAULT) + `uvm_field_int(gpr_wmask, UVM_DEFAULT) + `uvm_field_int(gpr_wdata, UVM_DEFAULT) `uvm_field_int(mem_addr, UVM_DEFAULT) `uvm_field_int(mem_rmask, UVM_DEFAULT) `uvm_field_int(mem_rdata, UVM_DEFAULT) @@ -159,6 +169,46 @@ class uvma_rvfi_instr_seq_item_c#(int ILEN=DEFAULT_ILEN, */ extern function bit [TRAP_DBG_CAUSE_WL-1:0] get_trap_debug_cause(); + /* + * Return GPR wdata + */ + extern function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] get_gpr_wdata(int gpr); + + /* + * Return GPR rdata + */ + extern function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] get_gpr_rdata(int gpr); + + + /* + * Return memory transaction data + */ + extern function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] get_mem_data_word(int txn); + + /* + * Return memory transaction addr + */ + extern function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] get_mem_addr(int txn); + + /* + * Return memory transaction wmask + */ + extern function bit [(uvma_rvfi_instr_seq_item_c::XLEN/8)-1:0] get_mem_wmask(int txn); + + /* + * Return memory transaction rmask + */ + extern function bit [(uvma_rvfi_instr_seq_item_c::XLEN/8)-1:0] get_mem_rmask(int txn); + + /* + * Check memory transaction activity + * + * Checks if a position in the rvfi memory transaction list + * indicates any activity. + * return {read, write} + */ + extern function bit [1:0] check_mem_act(int txn); + endclass : uvma_rvfi_instr_seq_item_c `pragma protect begin @@ -189,10 +239,10 @@ function string uvma_rvfi_instr_seq_item_c::convert2string(); convert2string = $sformatf("%s HALT", convert2string); if (insn_interrupt) convert2string = $sformatf("%s INTR %0d", convert2string, this.insn_interrupt_id); - if (insn_nmi_load_fault) - convert2string = $sformatf("%s NMI LOAD", convert2string); - if (insn_nmi_store_fault) - convert2string = $sformatf("%s NMI STORE", convert2string); + if (insn_nmi) + convert2string = $sformatf("%s NMI DECTED", convert2string); + if (insn_nmi_cause) + convert2string = $sformatf("%s NMI CAUSE: %0d", convert2string, this.insn_nmi_cause); if (insn_bus_fault) convert2string = $sformatf("%s INSN_BUS_FAULT", convert2string); if (dbg) @@ -244,34 +294,92 @@ endfunction : is_compressed_insn function bit uvma_rvfi_instr_seq_item_c::is_trap(); - return trap[TRAP_EXCP_LSB]; + return trap.trap; endfunction : is_trap function bit uvma_rvfi_instr_seq_item_c::is_debug_entry_trap(); - return trap[TRAP_DBG_ENTRY_LSB]; + return trap.debug; endfunction : is_debug_entry_trap function bit uvma_rvfi_instr_seq_item_c::is_nondebug_entry_trap(); - return trap[TRAP_NONDBG_ENTRY_LSB]; + return trap.exception; endfunction : is_nondebug_entry_trap function bit [TRAP_CAUSE_WL-1:0] uvma_rvfi_instr_seq_item_c::get_trap_cause(); - return trap[TRAP_CAUSE_LSB +: TRAP_CAUSE_WL]; + return trap.exception_cause; endfunction : get_trap_cause function bit [TRAP_DBG_CAUSE_WL-1:0] uvma_rvfi_instr_seq_item_c::get_trap_debug_cause(); - return trap[TRAP_DBG_CAUSE_LSB +: TRAP_DBG_CAUSE_WL]; + return trap.debug_cause; endfunction : get_trap_debug_cause + + +function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] uvma_rvfi_instr_seq_item_c::get_gpr_wdata(int gpr); + return gpr_wdata[gpr*XLEN +:XLEN]; +endfunction : get_gpr_wdata + +function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] uvma_rvfi_instr_seq_item_c::get_gpr_rdata(int gpr); + return gpr_rdata[gpr*XLEN +:XLEN]; +endfunction : get_gpr_rdata + +function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] uvma_rvfi_instr_seq_item_c::get_mem_data_word(int txn); + bit [XLEN-1:0] ret; + + for (int i = 0; i < XLEN/8; i++) begin + if (mem_wmask[(txn*XLEN/8) + i]) begin + ret[i*8 +:8] = mem_wdata[((txn*XLEN) + (i*8)) +:8]; + end else begin + ret[i*8 +:8] = mem_rdata[((txn*XLEN) + (i*8)) +:8]; + end + end + + return ret; + +endfunction : get_mem_data_word + +function bit [uvma_rvfi_instr_seq_item_c::XLEN-1:0] uvma_rvfi_instr_seq_item_c::get_mem_addr(int txn); + + return mem_addr[txn*XLEN +:XLEN]; + +endfunction : get_mem_addr + +function bit [(uvma_rvfi_instr_seq_item_c::XLEN/8)-1:0] uvma_rvfi_instr_seq_item_c::get_mem_rmask(int txn); + + return mem_rmask[(txn*XLEN/8) +:(XLEN/8)]; + +endfunction : get_mem_rmask + +function bit [(uvma_rvfi_instr_seq_item_c::XLEN/8)-1:0] uvma_rvfi_instr_seq_item_c::get_mem_wmask(int txn); + + return mem_wmask[(txn*XLEN/8) +:(XLEN/8)]; + +endfunction : get_mem_wmask + +function bit [1:0] uvma_rvfi_instr_seq_item_c::check_mem_act(int txn); + static bit read = 0; + static bit write = 0; + + if (mem_rmask[(txn*XLEN/8) +:(XLEN/8)]) begin + read = 1; + end + if (mem_wmask[(txn*XLEN/8) +:(XLEN/8)]) begin + write = 1; + end + + return {read,write}; + +endfunction : check_mem_act + `pragma protect end diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_agent.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_agent.sv index 55deffff3f..9962c27666 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_agent.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_agent.sv @@ -1,4 +1,4 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. @@ -6,15 +6,15 @@ // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_RVFI_AGENT_SV__ @@ -26,122 +26,122 @@ */ class uvma_rvfi_agent_c#(int ILEN=DEFAULT_ILEN, int XLEN=DEFAULT_XLEN) extends uvm_agent; - + // Objects uvma_rvfi_cfg_c#(ILEN,XLEN) cfg; uvma_rvfi_cntxt_c#(ILEN,XLEN) cntxt; - - // Components + + // Components uvma_rvfi_instr_mon_c#(ILEN,XLEN) instr_monitor[]; uvma_rvfi_mon_trn_logger_c#(ILEN,XLEN) mon_trn_logger; - - // TLM - uvm_analysis_port#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN)) instr_mon_ap[]; - + + // TLM + uvm_analysis_port#(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN)) instr_mon_ap[]; + `uvm_component_param_utils_begin(uvma_rvfi_agent_c) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) `uvm_component_utils_end - + /** * Default constructor. */ extern function new(string name="uvma_rvfi_agent", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null * 2. Builds all components */ extern virtual function void build_phase(uvm_phase phase); - + /** * 1. Links agent's analysis ports to sub-components' * 2. Connects coverage models and loggers */ extern virtual function void connect_phase(uvm_phase phase); - + /** * Uses uvm_config_db to retrieve cfg and hand out to sub-components. */ extern function void get_and_set_cfg(); - + /** * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. */ extern function void get_and_set_cntxt(); - + /** * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this * agent. */ extern function void retrieve_vif(); - + /** * Creates sub-components. */ extern function void create_components(); - + /** * Connects sequencer and driver's TLM port(s). */ extern function void connect_sequencer_and_driver(); - + /** * Connects agent's TLM ports to driver's and monitor's. */ extern function void connect_analysis_ports(); - + /** * Connects coverage model to monitor and driver's analysis ports. */ extern function void connect_cov_model(); - + /** * Connects transaction loggers to monitor and driver's analysis ports. */ extern function void connect_trn_loggers(); - + endclass : uvma_rvfi_agent_c function uvma_rvfi_agent_c::new(string name="uvma_rvfi_agent", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_rvfi_agent_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + get_and_set_cfg (); get_and_set_cntxt(); retrieve_vif (); create_components(); - + endfunction : build_phase function void uvma_rvfi_agent_c::connect_phase(uvm_phase phase); - + super.connect_phase(phase); - + connect_sequencer_and_driver(); connect_analysis_ports(); - + if (cfg.cov_model_enabled) begin connect_cov_model(); end if (cfg.trn_log_enabled) begin connect_trn_loggers(); end - + endfunction: connect_phase function void uvma_rvfi_agent_c::get_and_set_cfg(); - + void'(uvm_config_db#(uvma_rvfi_cfg_c#(ILEN,XLEN))::get(this, "", "cfg", cfg)); if (!cfg) begin `uvm_fatal("CFG", "Configuration handle is null") @@ -150,34 +150,34 @@ function void uvma_rvfi_agent_c::get_and_set_cfg(); `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) uvm_config_db#(uvma_rvfi_cfg_c#(ILEN,XLEN))::set(this, "*", "cfg", cfg); end - - instr_mon_ap = new[cfg.nret]; + + instr_mon_ap = new[cfg.nret]; endfunction : get_and_set_cfg function void uvma_rvfi_agent_c::get_and_set_cntxt(); - + void'(uvm_config_db#(uvma_rvfi_cntxt_c#(ILEN,XLEN))::get(this, "", "cntxt", cntxt)); if (!cntxt) begin `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) cntxt = uvma_rvfi_cntxt_c#(ILEN,XLEN)::type_id::create("cntxt"); end uvm_config_db#(uvma_rvfi_cntxt_c#(ILEN,XLEN))::set(this, "*", "cntxt", cntxt); - + endfunction : get_and_set_cntxt function void uvma_rvfi_agent_c::retrieve_vif(); - + // Retrieve instruction interface cntxt.instr_vif = new[cfg.nret]; for (int i = 0; i < cfg.nret; i++) begin - if (!uvm_config_db#(virtual uvma_rvfi_instr_if#(ILEN,XLEN))::get(this, "", $sformatf("instr_vif%0d", i), cntxt.instr_vif[i])) begin - `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", + if (!uvm_config_db#(virtual uvma_rvfi_instr_if_t#(ILEN,XLEN))::get(this, "", $sformatf("instr_vif%0d", i), cntxt.instr_vif[i])) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.instr_vif[i]))) end else begin - `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", $typename(cntxt.instr_vif[i])), UVM_DEBUG) end end @@ -193,7 +193,7 @@ function void uvma_rvfi_agent_c::retrieve_vif(); cntxt.csr_vif[csr] = new[cfg.nret]; for (int i = 0; i < cfg.nret; i++) begin - if (!uvm_config_db#(virtual uvma_rvfi_csr_if#(XLEN))::get(this, "", $sformatf("csr_%s_vif%0d", csr, i), cntxt.csr_vif[csr][i])) begin + if (!uvm_config_db#(virtual uvma_rvfi_csr_if_t#(XLEN))::get(this, "", $sformatf("csr_%s_vif%0d", csr, i), cntxt.csr_vif[csr][i])) begin `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s, csr [%s] in uvm_config_db", $typename(cntxt.csr_vif[csr][i]), csr)) end else begin @@ -213,19 +213,19 @@ function void uvma_rvfi_agent_c::create_components(); for (int i = 0; i < cfg.nret; i++) begin instr_monitor[i] = uvma_rvfi_instr_mon_c#(ILEN,XLEN)::type_id::create($sformatf("instr_monitor%0d", i), this); instr_monitor[i].nret_id = i; - end - mon_trn_logger = uvma_rvfi_mon_trn_logger_c#(ILEN,XLEN)::type_id::create("mon_trn_logger" , this); - + end + mon_trn_logger = uvma_rvfi_mon_trn_logger_c#(ILEN,XLEN)::type_id::create("mon_trn_logger" , this); + endfunction : create_components function void uvma_rvfi_agent_c::connect_sequencer_and_driver(); - + endfunction : connect_sequencer_and_driver function void uvma_rvfi_agent_c::connect_analysis_ports(); - + for (int i = 0; i < cfg.nret; i++) begin instr_mon_ap[i] = instr_monitor[i].ap; end @@ -234,14 +234,14 @@ endfunction : connect_analysis_ports function void uvma_rvfi_agent_c::connect_cov_model(); - - //mon_ap.connect(cov_model.mon_trn_fifo.analysis_export); - + + //mon_ap.connect(cov_model.mon_trn_fifo.analysis_export); + endfunction : connect_cov_model function void uvma_rvfi_agent_c::connect_trn_loggers(); - + for (int i = 0; i < cfg.nret; i++) begin instr_mon_ap[i].connect(mon_trn_logger.instr_export); end diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_cntxt.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_cntxt.sv index 23c9ebf72e..d9d4629eed 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_cntxt.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_cntxt.sv @@ -27,10 +27,10 @@ class uvma_rvfi_cntxt_c#(int ILEN=DEFAULT_ILEN, // Handle to instruction retirement interface // The number of interfaces will be equal to the _nret_ value in the configuration object - virtual uvma_rvfi_instr_if#(ILEN,XLEN) instr_vif[]; + virtual uvma_rvfi_instr_if_t#(ILEN,XLEN) instr_vif[]; // Handle to CSR interfaces - virtual uvma_rvfi_csr_if#(XLEN) csr_vif[string][]; + virtual uvma_rvfi_csr_if_t#(XLEN) csr_vif[string][]; // Events uvm_event sample_cfg_e; diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_constants.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_constants.sv index 589e84d122..7862830833 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_constants.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_constants.sv @@ -18,15 +18,17 @@ `ifndef __UVMA_RVFI_CONSTANTS_SV__ `define __UVMA_RVFI_CONSTANTS_SV__ + // RVFI field widths localparam ORDER_WL = 64; localparam MODE_WL = 2; localparam IXL_WL = 2; -localparam TRAP_WL = 12; +localparam TRAP_WL = 14; localparam GPR_ADDR_WL = 5; localparam RVFI_DBG_WL = 3; localparam RVFI_NMIP_WL = 2; localparam CYCLE_CNT_WL = 32; +localparam NMEM = 128; // Fields within TRAP localparam TRAP_EXCP_LSB = 0; @@ -40,9 +42,24 @@ localparam TRAP_CAUSE_WL = 6; localparam TRAP_DBG_CAUSE_LSB = 9; localparam TRAP_DBG_CAUSE_WL = 3; +// Lengths & Sizes localparam DEFAULT_ILEN = 32; localparam DEFAULT_XLEN = 32; localparam DEFAULT_NRET = 1; +// RISC-V Constants +parameter logic[ 2:0] DBG_CAUSE_TRIGGER = 3'h 2; +parameter logic[ 1:0] PRIV_LVL_M = 2'b 11; +parameter logic[ 1:0] PRIV_LVL_U = 2'b 00; +parameter logic[10:0] EXC_CAUSE_INSTR_ACC_FAULT = 11'd 1; +parameter logic[10:0] EXC_CAUSE_ILLEGAL_INSTR = 11'd 2; +parameter logic[10:0] EXC_CAUSE_BREAKPOINT = 11'd 3; +parameter logic[10:0] EXC_CAUSE_LOAD_ACC_FAULT = 11'd 5; +parameter logic[10:0] EXC_CAUSE_STORE_ACC_FAULT = 11'd 7; +parameter logic[10:0] EXC_CAUSE_ENV_CALL_U = 11'd 8; +parameter logic[10:0] EXC_CAUSE_ENV_CALL_M = 11'd 11; +parameter logic[10:0] EXC_CAUSE_INSTR_BUS_FAULT = 11'd 24; +parameter logic[10:0] EXC_CAUSE_INSTR_INTEGRITY_FAULT = 11'd 25; + `endif // __UVMA_RVFI_CONSTANTS_SV__ diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_csr_if.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_csr_if.sv index ecc4453f60..9cea8bf5f0 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_csr_if.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_csr_if.sv @@ -1,20 +1,20 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. - +//TODO: should we change the if-defines? `ifndef __UVMA_RVFI_CSR_IF_SV__ `define __UVMA_RVFI_CSR_IF_SV__ @@ -22,9 +22,9 @@ * Encapsulates all signals and clocking of RVFI csruction interface. Used by * monitor, */ -interface uvma_rvfi_csr_if +interface uvma_rvfi_csr_if_t import uvma_rvfi_pkg::*; - #(int XLEN=DEFAULT_XLEN) + #(int XLEN=DEFAULT_XLEN) ( input clk, input reset_n, @@ -42,18 +42,18 @@ interface uvma_rvfi_csr_if // ------------------------------------------------------------------- // Begin module code // ------------------------------------------------------------------- - + /** * Used by target DUT. */ clocking dut_cb @(posedge clk or reset_n); endclocking : dut_cb - + /** * Used by uvma_rvfi_csr_mon_c. */ clocking mon_cb @(posedge clk or reset_n); - input #1step + input #1step rvfi_csr_rmask, rvfi_csr_wmask, rvfi_csr_rdata, @@ -62,7 +62,22 @@ interface uvma_rvfi_csr_if modport passive_mp (clocking mon_cb); -endinterface : uvma_rvfi_csr_if + // ------------------------------------------------------------------- + // Functions + // ------------------------------------------------------------------- + + + function automatic logic [XLEN-1:0] pre_state(); + pre_state = (rvfi_csr_rdata & rvfi_csr_rmask); + endfunction : pre_state + + + function automatic logic [XLEN-1:0] post_state(); + post_state = (rvfi_csr_rdata & rvfi_csr_rmask & ~rvfi_csr_wmask) | (rvfi_csr_wdata & rvfi_csr_wmask); + endfunction : post_state + + +endinterface : uvma_rvfi_csr_if_t `endif // __UVMA_RVFI_CSR_IF_SV__ diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv index d097dde8e3..722106c713 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv @@ -22,63 +22,524 @@ * Encapsulates all signals and clocking of RVFI Instruction interface. Used by * monitor, */ -interface uvma_rvfi_instr_if +interface uvma_rvfi_instr_if_t + import isa_decoder_pkg::*; + import uvm_pkg::*; import uvma_rvfi_pkg::*; - #(int ILEN=DEFAULT_ILEN, - int XLEN=DEFAULT_XLEN) - //import uvma_rvfi_pkg::*; + + #(int ILEN=uvma_rvfi_pkg::DEFAULT_ILEN, + int XLEN=uvma_rvfi_pkg::DEFAULT_XLEN) ( - input clk, - input reset_n, - - input rvfi_valid, - input [ORDER_WL-1:0] rvfi_order, - input [ILEN-1:0] rvfi_insn, - input [TRAP_WL-1:0] rvfi_trap, - input rvfi_halt, - input [RVFI_DBG_WL-1:0] rvfi_dbg, - input rvfi_dbg_mode, - input [RVFI_NMIP_WL-1:0] rvfi_nmip, - input rvfi_intr, - input [MODE_WL-1:0] rvfi_mode, - input [IXL_WL-1:0] rvfi_ixl, - input [XLEN-1:0] rvfi_pc_rdata, - input [XLEN-1:0] rvfi_pc_wdata, - - input [GPR_ADDR_WL-1:0] rvfi_rs1_addr, - input [XLEN-1:0] rvfi_rs1_rdata, - - input [GPR_ADDR_WL-1:0] rvfi_rs2_addr, - input [XLEN-1:0] rvfi_rs2_rdata, - - input [GPR_ADDR_WL-1:0] rvfi_rs3_addr, - input [XLEN-1:0] rvfi_rs3_rdata, - - input [GPR_ADDR_WL-1:0] rvfi_rd1_addr, - input [XLEN-1:0] rvfi_rd1_wdata, - - input [GPR_ADDR_WL-1:0] rvfi_rd2_addr, - input [XLEN-1:0] rvfi_rd2_wdata, - - input [XLEN-1:0] rvfi_mem_addr, - input [XLEN-1:0] rvfi_mem_rdata, - input [XLEN/8-1:0] rvfi_mem_rmask, - input [XLEN-1:0] rvfi_mem_wdata, - input [XLEN/8-1:0] rvfi_mem_wmask + input logic clk, + input logic reset_n, + + input logic rvfi_valid, + input logic [ORDER_WL-1:0] rvfi_order, + input logic [ILEN-1:0] rvfi_insn, + input rvfi_trap_t rvfi_trap, + input logic rvfi_halt, + input logic [RVFI_DBG_WL-1:0] rvfi_dbg, + input logic rvfi_dbg_mode, + input logic [RVFI_NMIP_WL-1:0] rvfi_nmip, + input rvfi_intr_t rvfi_intr, + input logic [MODE_WL-1:0] rvfi_mode, + input logic [IXL_WL-1:0] rvfi_ixl, + input logic [XLEN-1:0] rvfi_pc_rdata, + input logic [XLEN-1:0] rvfi_pc_wdata, + + input logic [GPR_ADDR_WL-1:0] rvfi_rs1_addr, + input logic [XLEN-1:0] rvfi_rs1_rdata, + + input logic [GPR_ADDR_WL-1:0] rvfi_rs2_addr, + input logic [XLEN-1:0] rvfi_rs2_rdata, + + input logic [GPR_ADDR_WL-1:0] rvfi_rs3_addr, + input logic [XLEN-1:0] rvfi_rs3_rdata, + + input logic [GPR_ADDR_WL-1:0] rvfi_rd1_addr, + input logic [XLEN-1:0] rvfi_rd1_wdata, + + input logic [GPR_ADDR_WL-1:0] rvfi_rd2_addr, + input logic [XLEN-1:0] rvfi_rd2_wdata, + + input logic [(32*XLEN)-1:0] rvfi_gpr_rdata, + input logic [(32)-1:0] rvfi_gpr_rmask, + input logic [(32*XLEN)-1:0] rvfi_gpr_wdata, + input logic [(32)-1:0] rvfi_gpr_wmask, + + input logic [(NMEM*XLEN)-1:0] rvfi_mem_addr, + input logic [(NMEM*XLEN)-1:0] rvfi_mem_rdata, + input logic [(NMEM*XLEN/8)-1:0] rvfi_mem_rmask, + input logic [(NMEM*XLEN)-1:0] rvfi_mem_wdata, + input logic [(NMEM*XLEN/8)-1:0] rvfi_mem_wmask, + input logic [2:0] instr_prot, + input logic [NMEM*3-1:0] mem_prot ); + typedef logic[4*NMEM-1:0] mem_mask_t; + + // ------------------------------------------------------------------- + // Local param + // ------------------------------------------------------------------- + //instruction (rvfi_instr) masks + + localparam INSTR_MASK_DIV_REM = 32'h FE00_607F; + localparam INSTR_MASK_FULL = 32'h FFFF_FFFF; + localparam INSTR_MASK_R_TYPE = 32'h FE00_707F; + localparam INSTR_MASK_AMO_TYPE = 32'h F800_707F; + localparam INSTR_MASK_I_S_B_TYPE = 32'h 0000_707F; + localparam INSTR_MASK_U_J_TYPE = 32'h 0000_007F; + localparam INSTR_MASK_CSRADDR = 32'h FFF0_0000; + localparam INSTR_MASK_CSRUIMM = 32'h 000F_8000; + localparam INSTR_MASK_CMPR = 32'h FFFF_E003; + localparam INSTR_MASK_OPCODE = 32'h 0000_007F; + localparam INSTR_MASK_ZC_PUSHPOP = 32'h FFFF_FF03; + localparam INSTR_MASK_ZC_CLBU_CSB = 32'h FFFF_FC03; + localparam INSTR_MASK_CLH_CLHU_CSH = 32'b 1111_1111_1111_1111_1111_1100_0100_0011; + + + //instruction (rvfi_instr) comparison values + localparam INSTR_OPCODE_DRET = 32'h 7B20_0073; + localparam INSTR_OPCODE_MRET = 32'h 3020_0073; + localparam INSTR_OPCODE_URET = 32'h 0020_0073; + localparam INSTR_OPCODE_WFI = 32'h 1050_0073; + localparam INSTR_OPCODE_WFE = 32'h 8C00_0073; + localparam INSTR_OPCODE_EBREAK = 32'h 0010_0073; + localparam INSTR_OPCODE_C_EBREAK = 32'h 0000_9002; + localparam INSTR_OPCODE_ECALL = 32'h 0000_0073; + localparam INSTR_OPCODE_CSLLI = 32'h 0000_0002; + + localparam INSTR_OPCODE_DIV = 32'h 0200_4033; + localparam INSTR_OPCODE_REM = 32'h 0200_6033; + + localparam INSTR_OPCODE_CSRRW = 32'h 0000_1073; + localparam INSTR_OPCODE_CSRRS = 32'h 0000_2073; + localparam INSTR_OPCODE_CSRRC = 32'h 0000_3073; + localparam INSTR_OPCODE_CSRRWI = 32'h 0000_5073; + localparam INSTR_OPCODE_CSRRSI = 32'h 0000_6073; + localparam INSTR_OPCODE_CSRRCI = 32'h 0000_7073; + + localparam INSTR_OPCODE_BEQ = 32'h0000_0063; + localparam INSTR_OPCODE_BNE = 32'h0000_1063; + localparam INSTR_OPCODE_BLT = 32'h0000_4063; + localparam INSTR_OPCODE_BGE = 32'h0000_5063; + localparam INSTR_OPCODE_BLTU = 32'h0000_6063; + localparam INSTR_OPCODE_BGEU = 32'h0000_7063; + + localparam INSTR_OPCODE_CBEQZ = 32'h 0000_C001; + localparam INSTR_OPCODE_CBNEZ = 32'h 0000_E001; + + localparam INSTR_MASK_PUSHPOP = 32'b 11111111_11111111_111_11111_0000_00_11; + + localparam INSTR_OPCODE_PUSH = 32'b 00000000_00000000_101_11000_0000_00_10; + localparam INSTR_OPCODE_POP = 32'b 00000000_00000000_101_11010_0000_00_10; + localparam INSTR_OPCODE_POPRET = 32'b 00000000_00000000_101_11110_0000_00_10; + localparam INSTR_OPCODE_POPRETZ = 32'b 00000000_00000000_101_11100_0000_00_10; + + localparam INSTR_MASK_TABLEJUMP = 32'b 11111111_11111111_111_111_00000000_11; + localparam INSTR_OPCODE_TABLEJUMP = 32'b 00000000_00000000_101_000_00000000_10; + + localparam INSTR_MASK_FENCE = 32'b 00000000000000000_111_00000_1111111; + localparam INSTR_OPCODE_FENCE = 32'b 00000000000000000_000_00000_0001111; + localparam INSTR_MASK_FENCEI = 32'b 00000000000000000_111_00000_1111111; + localparam INSTR_OPCODE_FENCEI = 32'b 00000000000000000_001_00000_0001111; + + localparam INSTR_OPCODE_LOAD = 32'b 0000_0000_0000_0000_0000_0000_0000_0011; + localparam INSTR_OPCODE_STORE = 32'b 00000000_00000000_00000000_0_0100011; + + localparam INSTR_OPCODE_LH = 32'b00000000000000000_001_00000_0000011; + localparam INSTR_OPCODE_LHU = 32'b00000000000000000_101_00000_0000011; + localparam INSTR_OPCODE_LW = 32'b00000000000000000_010_00000_0000011; + localparam INSTR_OPCODE_SH = 32'b00000000000000000_001_00000_0100011; + localparam INSTR_OPCODE_SHU = 32'b00000000000000000_001_00000_0100011; + localparam INSTR_OPCODE_SW = 32'b00000000000000000_010_00000_0100011; + localparam INSTR_OPCODE_CLW = 32'b0000000000000000_010_000000000_0000; + localparam INSTR_OPCODE_CSW = 32'b0000000000000000_110_000000000_0000; + localparam INSTR_OPCODE_CLWSP = 32'b0000000000000000_010_000000000_0010; + localparam INSTR_OPCODE_CSWSP = 32'b0000000000000000_110_000000000_0010; + localparam INSTR_OPCODE_CSH = 32'b0000000000000000_100_011_00000000_00; + localparam INSTR_OPCODE_CSB = 32'b0000000000000000_100_010_00000000_00; + localparam INSTR_OPCODE_CLBU = 32'b 00000000_00000000_100_000_000_00_000_00; + localparam INSTR_OPCODE_CLHU = 32'b 00000000_00000000_100_001_000_0_0_000_00; + localparam INSTR_OPCODE_CLH = 32'b 00000000_00000000_100_001_000_1_0_000_00; + + localparam INSTR_OPCODE_CMPOP = 32'b 00000000_00000000_101_11010_0000_00_10; + localparam INSTR_OPCODE_CMPOPRET = 32'b 00000000_00000000_101_11110_0000_00_10; + localparam INSTR_OPCODE_CMPOPRETZ = 32'b 00000000_00000000_101_11100_0000_00_10; + + localparam INSTR_OPCODE_LRW = 32'b 00010_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_SCW = 32'b 00011_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOSWAPW = 32'b 00001_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOADDW = 32'b 00000_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOXORW = 32'b 00100_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOANDW = 32'b 01100_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOORW = 32'b 01000_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOMINW = 32'b 10000_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOMAXW = 32'b 10100_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOMINUW = 32'b 11000_0_0_00000_00000_010_00000_0101111; + localparam INSTR_OPCODE_AMOMAXUW = 32'b 11100_0_0_00000_00000_010_00000_0101111; + + //positions + localparam int INSTR_CSRADDR_POS = 20; + localparam int INSTR_CSRUIMM_POS = 15; + + + localparam INTR_CAUSE_NMI_MASK = 11'h 400; + + + // ------------------------------------------------------------------- // Local variables // ------------------------------------------------------------------- - bit [CYCLE_CNT_WL-1:0] cycle_cnt = 0; + int unsigned irq_cnt; // number of taken interrupts + int unsigned nmi_instr_cnt; // number of instructions after nmi + int unsigned single_step_cnt; // number of instructions stepped + logic [CYCLE_CNT_WL-1:0] cycle_cnt; // i'th number cycle since reset + logic [CYCLE_CNT_WL-1:0] cycle_cnt_q; + + string info_tag = "RVFI_INSTR_IF"; + + logic [(32)-1:0][XLEN-1:0] gpr_rdata_array; + logic [(32)-1:0] gpr_rmask_array; + logic [(32)-1:0][XLEN-1:0] gpr_wdata_array; + logic [(32)-1:0] gpr_wmask_array; + logic [NMEM-1:0][XLEN-1:0] mem_addr_array; + logic [NMEM-1:0][XLEN-1:0] mem_rdata_array; + logic [NMEM-1:0][(XLEN/8)-1:0] mem_rmask_array; + logic [NMEM-1:0][XLEN-1:0] mem_wdata_array; + logic [NMEM-1:0][(XLEN/8)-1:0] mem_wmask_array; + + logic [(5)-1:0] csri_uimm; + logic [5:0] cslli_shamt; + logic [11:0] csr_addr; + + logic is_dret; + logic is_mret; + logic is_uret; + logic is_wfi; + logic is_wfe; + logic is_ebreak; + logic is_ebreak_compr; + logic is_ebreak_noncompr; + logic is_ecall; + logic is_branch; + logic is_div; + logic is_rem; + logic is_cslli; + logic is_nmi; + logic is_compressed; + logic is_dbg_trg; + logic is_mmode; + logic is_not_mmode; + logic is_umode; + logic is_not_umode; + logic is_pma_instr_fault; + logic is_instr_acc_fault_pmp; + logic is_instr_bus_valid; + logic is_pushpop; + logic is_split_datatrans_actual; + logic is_split_datatrans_intended; + logic is_split_instrtrans; + logic is_mem_act; + logic is_mem_act_actual; + logic is_mem_act_intended; + logic is_tablejump_raw; + logic is_pma_fault; + logic is_fencefencei; + logic is_nmi_triggered; + logic is_load_instr; + logic is_store_instr; + logic is_amo_instr; + logic is_atomic_instr; + logic is_loadstore_instr; + logic is_exception; + logic is_load_acc_fault; + logic is_store_acc_fault; + logic is_deprioritized_load_acc_fault; + logic is_deprioritized_store_acc_fault; + logic [31:0] rvfi_mem_addr_word0highbyte; + logic [31:0] rvfi_pc_upperrdata; + logic [4*NMEM-1:0] rvfi_mem_rmask_intended; + logic [4*NMEM-1:0] rvfi_mem_wmask_intended; + + asm_t instr_asm; // ------------------------------------------------------------------- // Begin module code // ------------------------------------------------------------------- - always @(posedge clk) begin - cycle_cnt <= cycle_cnt + 1; + // these signals are added to make it easier to use the signal arrays, + // and to inspect them in the waveforms + // gpr masks are redundant, but added for ease of use + assign {>>{gpr_rdata_array}} = rvfi_gpr_rdata; + assign gpr_rmask_array = rvfi_gpr_rmask; + assign {>>{gpr_wdata_array}} = rvfi_gpr_wdata; + assign gpr_wmask_array = rvfi_gpr_wmask; + + + assign {>>{mem_addr_array}} = rvfi_mem_addr; + assign {>>{mem_rdata_array}} = rvfi_mem_rdata; + assign {>>{mem_rmask_array}} = rvfi_mem_rmask; + assign {>>{mem_wdata_array}} = rvfi_mem_wdata; + assign {>>{mem_wmask_array}} = rvfi_mem_wmask; + + assign csri_uimm = rvfi_insn[19:15]; + assign cslli_shamt = {rvfi_insn[12], rvfi_insn[6:2]}; + assign csr_addr = rvfi_insn[31:20]; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + irq_cnt <= 0; + is_nmi_triggered <= 0; + nmi_instr_cnt <= 0; + single_step_cnt <= 0; + end else begin + // Detect taken nmi or pending nmi and start counting + is_nmi_triggered <= is_nmi_triggered ? 1'b1 : (is_nmi || (rvfi_nmip && rvfi_valid)); + if (is_nmi_triggered && rvfi_valid) begin + nmi_instr_cnt <= nmi_instr_cnt + 1; + end + single_step_cnt <= (rvfi_dbg[2:0] == 3'h4 && rvfi_valid) ? single_step_cnt + 1 : single_step_cnt; + irq_cnt <= ((rvfi_intr.intr == 1) && (rvfi_intr.interrupt == 1) && rvfi_valid) ? irq_cnt + 1 : irq_cnt; + end + end + + always_ff @(posedge clk) begin + cycle_cnt_q <= cycle_cnt; + end + + // assigning signal aliases to helper functions + // These signals may be have dependencies on each other, thus to + // avoid having to micromanage order of execution, they are split + // into separate always_comb blocks. Assign will not work due to + // sensitivity list issues with functions, and a single always_comb + // block will cause issues due to clause b in section 9.2.2.2.1 of + // ieee 1800-2017 + always_comb begin + instr_asm = decode_instr(rvfi_insn); + end + + always_comb begin + is_dret = is_dret_f(); + end + + always_comb begin + is_mret = is_mret_f(); + end + + always_comb begin + is_uret = is_uret_f(); + end + + always_comb begin + is_wfi = is_wfi_f(); + end + + always_comb begin + is_wfe = is_wfe_f(); + end + + always_comb begin + is_ebreak = is_ebreak_f(); + end + + always_comb begin + is_ebreak_compr = is_ebreak_compr_f(); + end + + always_comb begin + is_ebreak_noncompr = is_ebreak_noncompr_f(); + end + + always_comb begin + is_ecall = is_ecall_f(); + end + + always_comb begin + is_branch = is_branch_f(); + end + + always_comb begin + is_div = is_div_f(); + end + + always_comb begin + is_rem = is_rem_f(); + end + + always_comb begin + is_cslli = is_cslli_f(); + end + + always_comb begin + is_nmi = is_nmi_f(); + end + + always_comb begin + is_compressed = is_compressed_f(); + end + + always_comb begin + is_dbg_trg = is_dbg_trg_f(); + end + + always_comb begin + is_mmode = is_mmode_f(); + end + + always_comb begin + is_not_mmode = is_not_mmode_f(); + end + + always_comb begin + is_umode = is_umode_f(); + end + + always_comb begin + is_not_umode = is_not_umode_f(); + end + + always_comb begin + is_pma_instr_fault = is_pma_instr_fault_f(); + end + + always_comb begin + is_instr_bus_valid = is_instr_bus_valid_f(); + end + + always_comb begin + is_pushpop = is_pushpop_f(); + end + + always_comb begin + is_split_datatrans_actual = is_split_datatrans_actual_f(); + end + + always_comb begin + is_split_datatrans_intended = is_split_datatrans_intended_f(); + end + + always_comb begin + is_mem_act = is_mem_act_f(); + end + + always_comb begin + is_tablejump_raw = is_tablejump_raw_f(); + end + + always_comb begin + is_pma_fault = is_pma_fault_f(); + end + + always_comb begin + is_fencefencei = is_fencefencei_f(); + end + + always_comb begin + rvfi_mem_addr_word0highbyte = rvfi_mem_addr_word0highbyte_f(); + end + + always_comb begin + rvfi_mem_rmask_intended = rvfi_mem_rmask_intended_f(); + end + + always_comb begin + rvfi_mem_wmask_intended = rvfi_mem_wmask_intended_f(); + end + + always_comb begin + is_deprioritized_load_acc_fault = is_deprioritized_exception_f({21'd 0, EXC_CAUSE_LOAD_ACC_FAULT}); + end + + always_comb begin + is_deprioritized_store_acc_fault = is_deprioritized_exception_f({21'd 0, EXC_CAUSE_STORE_ACC_FAULT}); + end + + always_comb begin + cycle_cnt = !reset_n ? 0 : (cycle_cnt_q + 1'b 1); + end + + always_comb begin + is_load_instr = rvfi_valid && |rvfi_mem_rmask_intended; + end + + always_comb begin + is_store_instr = rvfi_valid && |rvfi_mem_wmask_intended; + end + + always_comb begin + is_amo_instr = rvfi_valid && ( + match_instr(INSTR_OPCODE_AMOSWAPW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOADDW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOXORW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOANDW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOORW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMINW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMAXW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMINUW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMAXUW, INSTR_MASK_AMO_TYPE)); + end + + always_comb begin + is_atomic_instr = rvfi_valid && (is_amo_instr || + match_instr(INSTR_OPCODE_SCW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_LRW, INSTR_MASK_AMO_TYPE)); + end + + always_comb begin + is_loadstore_instr = is_load_instr || is_store_instr; + end + + always_comb begin + is_mem_act_actual = is_mem_act; // original signal is already "actual" + end + + always_comb begin + is_mem_act_intended = rvfi_valid && (|rvfi_mem_rmask_intended || |rvfi_mem_wmask_intended); + end + + always_comb begin + rvfi_pc_upperrdata = + (rvfi_insn[1:0] == 2'b 11) ? ( + rvfi_pc_rdata + 3 + ) : ( + rvfi_pc_rdata + 1 + ); + // WARNING: Can't trust rvfi_insn if scrambled data. + // TODO:WARNING:silabs-robin Can it be modelled exact? + end + + always_comb begin + is_split_instrtrans = + rvfi_valid && + (rvfi_pc_rdata[31:2] != rvfi_pc_upperrdata[31:2]); + end + + always_comb begin + is_exception = + rvfi_valid && + rvfi_trap.trap && + rvfi_trap.exception; + end + + always_comb begin + is_instr_acc_fault_pmp = + is_exception && + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_ACC_FAULT) && + (rvfi_trap.cause_type == 'h 1); // TODO:INFO:silabs-robin Magic num + end + + always_comb begin + is_load_acc_fault = + is_exception && + (rvfi_trap.exception_cause == EXC_CAUSE_LOAD_ACC_FAULT); + end + + always_comb begin + is_store_acc_fault = + is_exception && + (rvfi_trap.exception_cause == EXC_CAUSE_STORE_ACC_FAULT); end /** @@ -93,6 +554,7 @@ interface uvma_rvfi_instr_if clocking mon_cb @(posedge clk or reset_n); input #1step cycle_cnt, + nmi_instr_cnt, rvfi_valid, rvfi_order, rvfi_insn, @@ -116,6 +578,10 @@ interface uvma_rvfi_instr_if rvfi_rd1_wdata, rvfi_rd2_addr, rvfi_rd2_wdata, + rvfi_gpr_rdata, + rvfi_gpr_rmask, + rvfi_gpr_wdata, + rvfi_gpr_wmask, rvfi_mem_addr, rvfi_mem_rdata, rvfi_mem_rmask, @@ -125,8 +591,602 @@ interface uvma_rvfi_instr_if modport passive_mp (clocking mon_cb); -endinterface : uvma_rvfi_instr_if + // ------------------------------------------------------------------- + // Functions + // ------------------------------------------------------------------- + // NOTE: All of these functions are only valid when the RVFI bus holds + // valid values, indicated by rvfi_valid == 1 -`endif // __UVMA_RVFI_INSTR_IF_SV__ + // Check if instruction is of a certain type + // Usage: instr_mask sets the parts of the instruction you want to compare, + // instr_ref is the reference to match + function automatic logic match_instr( + logic [ XLEN-1:0] instr_ref, + logic [ XLEN-1:0] instr_mask + ); + + return rvfi_valid && is_instr_bus_valid && ((rvfi_insn & instr_mask) == instr_ref); + + endfunction : match_instr + + // Check if instruction is of a certain type, without verifying the instr word is valid + // Usage: instr_mask sets the parts of the instruction you want to compare, + // instr_ref is the reference to match + function automatic logic match_instr_raw( + logic [ XLEN-1:0] instr_ref, + logic [ XLEN-1:0] instr_mask + ); + + return rvfi_valid && ((rvfi_insn & instr_mask) == instr_ref); + + endfunction : match_instr_raw + +// Match instr types +function automatic logic match_instr_r(logic [ XLEN-1:0] instr_ref); + return match_instr(instr_ref, INSTR_MASK_R_TYPE); +endfunction : match_instr_r + +function automatic logic match_instr_r_var( + logic [6:0] funct7, + logic [2:0] funct3, + logic [6:0] opcode +); + return match_instr_r({funct7, 10'b0, funct3, 5'b0, opcode}); +endfunction : match_instr_r_var + +function automatic logic match_instr_isb(logic [ XLEN-1:0] instr_ref); + return match_instr(instr_ref, INSTR_MASK_I_S_B_TYPE); +endfunction : match_instr_isb + +function automatic logic match_instr_isb_var ( + logic [2:0] funct3, + logic [6:0] opcode +); + return match_instr_isb({17'b0, funct3, 5'b0, opcode}); +endfunction : match_instr_isb_var + +function automatic logic match_instr_uj(logic [ XLEN-1:0] instr_ref); + return match_instr(instr_ref, INSTR_MASK_U_J_TYPE); +endfunction : match_instr_uj + +function automatic logic match_instr_uj_var(logic [6:0] opcode); + return match_instr_uj({25'b0, opcode}); +endfunction : match_instr_uj_var + +// Match CSR functions +// These instruction are used to check for csr activity. +// All instructions has the input csr_addr. Setting this limits the query to +// that single address, leaving the input as 0 returns any csr activity. +function automatic logic is_csr_instr(logic [11:0] csr_addr = 0); + if (csr_addr == 0) begin //not specified + return match_instr_isb(INSTR_OPCODE_CSRRW) || + match_instr_isb(INSTR_OPCODE_CSRRS) || + match_instr_isb(INSTR_OPCODE_CSRRC) || + match_instr_isb(INSTR_OPCODE_CSRRWI) || + match_instr_isb(INSTR_OPCODE_CSRRSI) || + match_instr_isb(INSTR_OPCODE_CSRRCI); + end else begin + return match_instr(32'h0 | (csr_addr << INSTR_CSRADDR_POS), INSTR_MASK_CSRADDR) && + ( match_instr_isb(INSTR_OPCODE_CSRRW) || + match_instr_isb(INSTR_OPCODE_CSRRS) || + match_instr_isb(INSTR_OPCODE_CSRRC) || + match_instr_isb(INSTR_OPCODE_CSRRWI) || + match_instr_isb(INSTR_OPCODE_CSRRSI) || + match_instr_isb(INSTR_OPCODE_CSRRCI)); + end +endfunction : is_csr_instr + +// This function follows the spec definition of a csr read +function automatic logic is_csr_read(logic [11:0] csr_addr = 0); + if ( (rvfi_rd1_addr == 0) && + ( match_instr_isb(INSTR_OPCODE_CSRRW) || + match_instr_isb(INSTR_OPCODE_CSRRWI))) begin + return 0; + end else begin + return is_csr_instr(csr_addr); + end +endfunction + +// This function follows the spec definition of a csr write +function automatic logic is_csr_write(logic [11:0] csr_addr = 0); + if ( ( (rvfi_rs1_addr == 0) && + ( match_instr_isb(INSTR_OPCODE_CSRRS) || + match_instr_isb(INSTR_OPCODE_CSRRC)) + ) || ( + ((rvfi_insn & INSTR_MASK_CSRUIMM) == 0) && + ( match_instr_isb(INSTR_OPCODE_CSRRSI) || + match_instr_isb(INSTR_OPCODE_CSRRCI)) + )) begin + return 0; + end else begin + return is_csr_instr(csr_addr); + end +endfunction + +// returns intended write data for any CSR write instruction, +// without regard for what the legal values are in the CSR +// input current value of the csr, and the csr address +// NOTE: that this will work for CSRRW with unspecified csr address, +// but CSRRS/CSRRC will give incorrect return values +function automatic logic [XLEN-1:0] csr_intended_wdata( logic [XLEN-1:0] csr_rdata, + logic [11:0] csr_addr = 0); + if (!is_csr_write(csr_addr)) begin + return 0; + end else begin + if (match_instr_isb(INSTR_OPCODE_CSRRW)) begin + return rvfi_rs1_rdata; + end else if (match_instr_isb(INSTR_OPCODE_CSRRWI)) begin + return (rvfi_insn & INSTR_MASK_CSRUIMM) >> INSTR_CSRUIMM_POS; + end else if (match_instr_isb(INSTR_OPCODE_CSRRS)) begin + return csr_rdata | rvfi_rs1_rdata; + end else if (match_instr_isb(INSTR_OPCODE_CSRRSI)) begin + return csr_rdata | ((rvfi_insn & INSTR_MASK_CSRUIMM) >> INSTR_CSRUIMM_POS); + end else if (match_instr_isb(INSTR_OPCODE_CSRRC)) begin + return csr_rdata & ~rvfi_rs1_rdata; + end else if (match_instr_isb(INSTR_OPCODE_CSRRCI)) begin + return csr_rdata & ~((rvfi_insn & INSTR_MASK_CSRUIMM) >> INSTR_CSRUIMM_POS); + end + end +endfunction + +// Return wdata of register "gpr" +function automatic logic [ XLEN-1:0] get_gpr_wdata( int gpr); + return rvfi_gpr_wdata[gpr* XLEN +: XLEN]; +endfunction : get_gpr_wdata + +// Return rdata of register "gpr" +function automatic logic [ XLEN-1:0] get_gpr_rdata( int gpr); + return rvfi_gpr_rdata[gpr* XLEN +: XLEN]; +endfunction : get_gpr_rdata + +// Return valid data of memory transaction "txn" +function automatic logic [ XLEN-1:0] get_mem_data_word( int txn); + bit [ XLEN-1:0] ret; + + for (int i = 0; i < XLEN/8; i++) begin + if (rvfi_mem_wmask[(txn* XLEN/8) + i]) begin + ret[i*8 +:8] = rvfi_mem_wdata[((txn* XLEN) + (i*8)) +:8]; + end else begin + ret[i*8 +:8] = rvfi_mem_rdata[((txn* XLEN) + (i*8)) +:8]; + end + end + + return ret; + +endfunction : get_mem_data_word + +//Return addr of memory transaction "txn" +function automatic logic [ XLEN-1:0] get_mem_addr(int txn); + + return rvfi_mem_addr[txn* XLEN +: XLEN]; + +endfunction : get_mem_addr + +//Return rmask of memory transaction "txn" +function automatic logic [( XLEN/8)-1:0] get_mem_rmask(int txn); + + return rvfi_mem_rmask[(txn* XLEN/8) +:( XLEN/8)]; + +endfunction : get_mem_rmask + +//Return wmask of memory transaction "txn" +function automatic logic [( XLEN/8)-1:0] get_mem_wmask(int txn); + + return rvfi_mem_wmask[(txn* XLEN/8) +:( XLEN/8)]; + +endfunction : get_mem_wmask + + +//Check memory transaction activity + +//Checks if a position in the rvfi memory transaction list +//indicates any activity. +//return {read, write} +function automatic logic [1:0] check_mem_act(int txn); + bit read = 0; + bit write = 0; + + if (rvfi_mem_rmask[(txn* XLEN/8) +:( XLEN/8)]) begin + read = 1; + end + if (rvfi_mem_wmask[(txn* XLEN/8) +:( XLEN/8)]) begin + write = 1; + end + + return {read,write}; + +endfunction : check_mem_act + +function automatic logic is_mem_act_f(); + return rvfi_valid && (|rvfi_mem_rmask || |rvfi_mem_wmask); +endfunction : is_mem_act_f + + +// Short functions for recognising special functions + +function automatic logic is_dret_f(); + return match_instr(INSTR_OPCODE_DRET, INSTR_MASK_FULL); +endfunction : is_dret_f + +function automatic logic is_mret_f(); + return match_instr(INSTR_OPCODE_MRET, INSTR_MASK_FULL); +endfunction : is_mret_f + +function automatic logic is_uret_f(); + return match_instr(INSTR_OPCODE_URET, INSTR_MASK_FULL); +endfunction : is_uret_f + +function automatic logic is_wfi_f(); + return match_instr(INSTR_OPCODE_WFI, INSTR_MASK_FULL); +endfunction : is_wfi_f + +function automatic logic is_wfe_f(); + return match_instr(INSTR_OPCODE_WFE, INSTR_MASK_FULL); +endfunction : is_wfe_f + +function automatic logic is_ebreak_f(); + return match_instr(INSTR_OPCODE_EBREAK, INSTR_MASK_FULL) || match_instr(INSTR_OPCODE_C_EBREAK, INSTR_MASK_FULL); +endfunction : is_ebreak_f + +function automatic logic is_ebreak_compr_f(); + return match_instr(INSTR_OPCODE_C_EBREAK, INSTR_MASK_FULL); +endfunction : is_ebreak_compr_f + +function automatic logic is_ebreak_noncompr_f(); + return match_instr(INSTR_OPCODE_EBREAK, INSTR_MASK_FULL); +endfunction : is_ebreak_noncompr_f +function automatic logic is_ecall_f(); + return match_instr(INSTR_OPCODE_ECALL, INSTR_MASK_FULL); +endfunction : is_ecall_f + +function automatic logic is_branch_f(); //TODO + return match_instr(INSTR_OPCODE_BEQ, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_BNE, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_BLT, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_BGE, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_BLTU, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_BGEU, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_CBEQZ, INSTR_MASK_CMPR) || + match_instr(INSTR_OPCODE_CBNEZ, INSTR_MASK_CMPR); +endfunction : is_branch_f + +function automatic logic is_div_f(); + return match_instr(INSTR_OPCODE_DIV, INSTR_MASK_DIV_REM); +endfunction : is_div_f + +function automatic logic is_rem_f(); + return match_instr(INSTR_OPCODE_REM, INSTR_MASK_DIV_REM); +endfunction : is_rem_f + +function automatic logic is_cslli_f(); + return match_instr(INSTR_OPCODE_CSLLI, INSTR_MASK_CMPR); +endfunction : is_cslli_f + +function automatic logic is_pushpop_f(); + return match_instr(INSTR_OPCODE_PUSH, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_POP, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_POPRET, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_POPRETZ, INSTR_MASK_ZC_PUSHPOP); +endfunction : is_pushpop_f + +function automatic logic is_tablejump_raw_f(); + return match_instr_raw(INSTR_OPCODE_TABLEJUMP, INSTR_MASK_TABLEJUMP); +endfunction : is_tablejump_raw_f + +function automatic logic is_fencefencei_f(); + return match_instr(INSTR_OPCODE_FENCE, INSTR_MASK_FENCE) || + match_instr(INSTR_OPCODE_FENCEI, INSTR_MASK_FENCEI); +endfunction : is_fencefencei_f + +function automatic logic is_nmi_f(); + return rvfi_valid && rvfi_intr.intr && (rvfi_intr.cause & INTR_CAUSE_NMI_MASK); +endfunction : is_nmi_f + +function automatic logic is_compressed_f(); + return rvfi_valid && (rvfi_insn[1:0] != 2'b11); +endfunction : is_compressed_f + +function automatic logic is_dbg_trg_f(); + return rvfi_valid && + rvfi_trap.trap && + rvfi_trap.debug && + (rvfi_trap.debug_cause == DBG_CAUSE_TRIGGER); +endfunction : is_dbg_trg_f + +function automatic logic is_mmode_f(); + return rvfi_valid && + (rvfi_mode == PRIV_LVL_M); +endfunction : is_mmode_f + +function automatic logic is_not_mmode_f(); + return rvfi_valid && + (rvfi_mode != PRIV_LVL_M); +endfunction : is_not_mmode_f + +function automatic logic is_umode_f(); + return rvfi_valid && + (rvfi_mode == PRIV_LVL_U); +endfunction : is_umode_f + +function automatic logic is_not_umode_f(); + return rvfi_valid && + (rvfi_mode != PRIV_LVL_U); +endfunction : is_not_umode_f + +function automatic logic is_pma_instr_fault_f(); + return rvfi_valid && + rvfi_trap.trap && + rvfi_trap.exception && + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_ACC_FAULT) && + (rvfi_trap.cause_type == 'h 0); +endfunction : is_pma_instr_fault_f + +function automatic logic is_pma_fault_f(); + return rvfi_valid && + rvfi_trap.trap && + rvfi_trap.exception && + (rvfi_trap.exception_cause inside { + EXC_CAUSE_INSTR_ACC_FAULT, + EXC_CAUSE_LOAD_ACC_FAULT, + EXC_CAUSE_STORE_ACC_FAULT + }) && + (rvfi_trap.cause_type == 'h 0); +endfunction : is_pma_fault_f + +function automatic logic is_instr_bus_valid_f(); + return !( (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_ACC_FAULT) || + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_INTEGRITY_FAULT) || + (rvfi_trap.exception_cause == EXC_CAUSE_INSTR_BUS_FAULT) + ); +endfunction : is_instr_bus_valid_f + +function automatic logic [31:0] rvfi_mem_addr_word0highbyte_f(); + logic [31:0] addr = rvfi_mem_addr[31:0]; + case (1) + (rvfi_mem_rmask[3] || rvfi_mem_wmask[3]): + return addr + 3; + (rvfi_mem_rmask[2] || rvfi_mem_wmask[2]): + return addr + 2; + (rvfi_mem_rmask[1] || rvfi_mem_wmask[1]): + return addr + 1; + default: + return addr; + endcase +endfunction : rvfi_mem_addr_word0highbyte_f + +function automatic logic is_split_datatrans_actual_f(); + logic [31:0] low_addr = rvfi_mem_addr[XLEN-1:0]; + logic [31:0] high_addr = rvfi_mem_addr_word0highbyte; + return is_mem_act_actual && (low_addr[31:2] != high_addr[31:2]); +endfunction : is_split_datatrans_actual_f + +function automatic logic is_split_datatrans_intended_f(); + logic [31:0] low_addr = rvfi_mem_addr[XLEN-1:0]; + logic [31:0] high_addr = rvfi_mem_addr_word0highbyte; + // TODO:ERROR:silabs-robin Create "instr_mem_addr" when decoder facilitates it + return is_mem_act_intended && (low_addr[31:2] != high_addr[31:2]); +endfunction : is_split_datatrans_intended_f + +// Shows "intended" version of rvfi_mem_wmask +function automatic logic [4*NMEM-1:0] rvfi_mem_rmask_intended_f(); + logic [NMEM-1:0][3:0] rmask = {'0}; + logic [3:0] rlist; + rlist = rvfi_insn[7:4]; + + rmask[0][3] = + match_instr(INSTR_OPCODE_LW, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_CLW, INSTR_MASK_CMPR) || + match_instr(INSTR_OPCODE_CLWSP, INSTR_MASK_CMPR) || + match_instr(INSTR_OPCODE_CMPOP, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_CMPOPRET, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_CMPOPRETZ, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_LRW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOSWAPW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOADDW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOXORW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOANDW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOORW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMINW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMAXW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMINUW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMAXUW, INSTR_MASK_AMO_TYPE); + + rmask[0][2] = rmask[0][3]; + + rmask[0][1] = rmask[0][2] || + match_instr(INSTR_OPCODE_LH, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_LHU, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_CLHU, INSTR_MASK_CLH_CLHU_CSH) || + match_instr(INSTR_OPCODE_CLH, INSTR_MASK_CLH_CLHU_CSH); + + rmask[0][0] = rmask[0][1] || + match_instr(INSTR_OPCODE_LOAD, INSTR_MASK_OPCODE) || + match_instr(INSTR_OPCODE_CLBU, INSTR_MASK_ZC_CLBU_CSB); + + if(rlist > 4 && + (match_instr(INSTR_OPCODE_CMPOP, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_CMPOPRET, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_CMPOPRETZ, INSTR_MASK_ZC_PUSHPOP))) begin + + case (rlist) + 5: begin + rmask[1:0] = '1; + end + + 6: begin + rmask[2:0] = '1; + end + + 7: begin + rmask[3:0] = '1; + end + + 8: begin + rmask[4:0] = '1; + end + + 9: begin + rmask[5:0] = '1; + end + + 10: begin + rmask[6:0] = '1; + end + + 11: begin + rmask[7:0] = '1; + end + + 12: begin + rmask[8:0] = '1; + end + + 13: begin + rmask[9:0] = '1; + end + + 14: begin + rmask[10:0] = '1; + end + + 15: begin //Does two extra memory accesses + rmask[12:0] = '1; + end + + default: rmask = '0; + endcase + end + return mem_mask_t'(rmask); +endfunction + + +// Shows "intended" version of rvfi_mem_wmask +function automatic logic [4*NMEM-1:0] rvfi_mem_wmask_intended_f(); + logic [NMEM-1:0][3:0] wmask = {'0}; + logic [3:0] rlist; + rlist = rvfi_insn[7:4]; + + wmask[0][3] = + match_instr(INSTR_OPCODE_SW, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_CSW, INSTR_MASK_CMPR) || + match_instr(INSTR_OPCODE_CSWSP, INSTR_MASK_CMPR) || + match_instr(INSTR_OPCODE_PUSH, INSTR_MASK_ZC_PUSHPOP) || + match_instr(INSTR_OPCODE_SCW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOSWAPW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOADDW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOXORW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOANDW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOORW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMINW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMAXW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMINUW, INSTR_MASK_AMO_TYPE) || + match_instr(INSTR_OPCODE_AMOMAXUW, INSTR_MASK_AMO_TYPE); + + + wmask[0][2] = wmask[0][3]; + + wmask[0][1] = wmask[0][2] || + match_instr(INSTR_OPCODE_SH, INSTR_MASK_I_S_B_TYPE) || + match_instr(INSTR_OPCODE_CSH, INSTR_MASK_CLH_CLHU_CSH); + + wmask[0][0] = wmask[0][1] || + match_instr(INSTR_OPCODE_STORE, INSTR_MASK_OPCODE) || + match_instr(INSTR_OPCODE_CSB, INSTR_MASK_ZC_CLBU_CSB); + + if(rlist > 4 && match_instr(INSTR_OPCODE_PUSH, INSTR_MASK_ZC_PUSHPOP)) begin + + case (rlist) + 5: begin + wmask[1:0] = '1; + end + + 6: begin + wmask[2:0] = '1; + end + + 7: begin + wmask[3:0] = '1; + end + + 8: begin + wmask[4:0] = '1; + end + + 9: begin + wmask[5:0] = '1; + end + + 10: begin + wmask[6:0] = '1; + end + + 11: begin + wmask[7:0] = '1; + end + + 12: begin + wmask[8:0] = '1; + end + + 13: begin + wmask[9:0] = '1; + end + + 14: begin + wmask[10:0] = '1; + end + + 15: begin //Does two extra memory accesses + wmask[12:0] = '1; + end + + default: wmask = '0; + endcase + end + return mem_mask_t'(wmask); +endfunction + +function automatic logic[31:0] get_max_exception_cause_f ( + logic[31:0] exc_a, + logic[31:0] exc_b +); + if (EXC_CAUSE_INSTR_ACC_FAULT inside {exc_a, exc_b}) begin + return EXC_CAUSE_INSTR_ACC_FAULT; + end else if (EXC_CAUSE_INSTR_INTEGRITY_FAULT inside {exc_a, exc_b}) begin + return EXC_CAUSE_INSTR_INTEGRITY_FAULT; + end else if (EXC_CAUSE_INSTR_BUS_FAULT inside {exc_a, exc_b}) begin + return EXC_CAUSE_INSTR_BUS_FAULT; + end else if (EXC_CAUSE_ILLEGAL_INSTR inside {exc_a, exc_b}) begin + return EXC_CAUSE_ILLEGAL_INSTR; + end else if (EXC_CAUSE_ENV_CALL_U inside {exc_a, exc_b}) begin + return EXC_CAUSE_ENV_CALL_U; + end else if (EXC_CAUSE_ENV_CALL_M inside {exc_a, exc_b}) begin + return EXC_CAUSE_ENV_CALL_M; + end else if (EXC_CAUSE_BREAKPOINT inside {exc_a, exc_b}) begin + return EXC_CAUSE_BREAKPOINT; + end else if (EXC_CAUSE_STORE_ACC_FAULT inside {exc_a, exc_b}) begin + return EXC_CAUSE_STORE_ACC_FAULT; + end else if (EXC_CAUSE_LOAD_ACC_FAULT inside {exc_a, exc_b}) begin + return EXC_CAUSE_LOAD_ACC_FAULT; + end else begin + `uvm_error(info_tag, "unhandled 'max' exception cause"); + return '0; + end +endfunction : get_max_exception_cause_f + +function automatic logic is_deprioritized_exception_f (logic[31:0] exc_cause); + return ( + rvfi_valid && + rvfi_trap.exception && + (rvfi_trap.exception_cause != exc_cause) && + (rvfi_trap.exception_cause == + get_max_exception_cause_f({26'd0, rvfi_trap.exception_cause}, exc_cause) + ) + ); +endfunction + +endinterface : uvma_rvfi_instr_if_t + +`endif // __UVMA_RVFI_INSTR_IF_SV__ diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_mon.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_mon.sv index d34767d095..82df7dba0f 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_mon.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_mon.sv @@ -23,7 +23,7 @@ /** * Component sampling transactions from a Clock & Reset virtual interface - * (uvma_rvfi_instr_if). + * (uvma_rvfi_instr_if_t). */ class uvma_rvfi_instr_mon_c#(int ILEN=DEFAULT_ILEN, int XLEN=DEFAULT_XLEN) extends uvm_monitor; @@ -168,6 +168,11 @@ task uvma_rvfi_instr_mon_c::monitor_rvfi_instr(); mon_trn.mem_wdata = cntxt.instr_vif[nret_id].mon_cb.rvfi_mem_wdata; mon_trn.mem_wmask = cntxt.instr_vif[nret_id].mon_cb.rvfi_mem_wmask; + mon_trn.gpr_rdata = cntxt.instr_vif[nret_id].mon_cb.rvfi_gpr_rdata; + mon_trn.gpr_rmask = cntxt.instr_vif[nret_id].mon_cb.rvfi_gpr_rmask; + mon_trn.gpr_wdata = cntxt.instr_vif[nret_id].mon_cb.rvfi_gpr_wdata; + mon_trn.gpr_wmask = cntxt.instr_vif[nret_id].mon_cb.rvfi_gpr_wmask; + // Get the CSRs foreach (cntxt.csr_vif[csr]) begin uvma_rvfi_csr_seq_item_c csr_trn = uvma_rvfi_csr_seq_item_c#(XLEN)::type_id::create({csr, "_trn"}); @@ -182,26 +187,19 @@ task uvma_rvfi_instr_mon_c::monitor_rvfi_instr(); mon_trn.csrs[csr] = csr_trn; end - // Decode interrupts that need to be communicated to ISS (external or NMI bus faults) - if (mon_trn.intr) begin - // The cause of the interrupt should be in the "rdata" field of the mcause CSR RVFI port - bit [XLEN-1:0] csr_mcause = mon_trn.csrs["mcause"].rdata; - + //TODO:MT update with parity for 40S + mon_trn.insn_nmi = 0; + if (mon_trn.intr.intr) begin + // NMI detected + if ((cfg.nmi_load_fault_enabled && mon_trn.intr.cause == cfg.nmi_load_fault_cause) || + (cfg.nmi_store_fault_enabled && mon_trn.intr.cause == cfg.nmi_store_fault_cause)) begin + mon_trn.insn_nmi = 1; + mon_trn.insn_nmi_cause = mon_trn.intr.cause; + end // External interrupt - if (csr_mcause[31]) begin - // NMI - Load fault - if (cfg.nmi_load_fault_enabled && csr_mcause[XLEN-2:0] == cfg.nmi_load_fault_cause) begin - mon_trn.insn_nmi_load_fault = 1; - end - // NMI - Store fault - else if (cfg.nmi_store_fault_enabled && csr_mcause[XLEN-2:0] == cfg.nmi_store_fault_cause) begin - mon_trn.insn_nmi_store_fault = 1; - end - // External interrupt - else begin - mon_trn.insn_interrupt = 1; - mon_trn.insn_interrupt_id = { 1'b0, csr_mcause[XLEN-2:0] }; - end + else begin + mon_trn.insn_interrupt = 1; + mon_trn.insn_interrupt_id = { 1'b0, mon_trn.intr.cause }; end end if (mon_trn.csrs.exists("dcsr")) begin @@ -213,12 +211,14 @@ task uvma_rvfi_instr_mon_c::monitor_rvfi_instr(); mon_trn.nmip[0] && dcsr_ret_data[3]) begin - `uvm_info("RVFIMON", $sformatf("Debug NMIP"), UVM_LOW); + `uvm_info("RVFIMON", $sformatf("Debug NMIP"), UVM_LOW) if (mon_trn.nmip[1] == 0) begin - mon_trn.insn_nmi_load_fault = 1; + mon_trn.insn_nmi = 1; + mon_trn.insn_nmi_cause = cfg.nmi_load_fault_cause; end else begin - mon_trn.insn_nmi_store_fault = 1; + mon_trn.insn_nmi = 1; + mon_trn.insn_nmi_cause = cfg.nmi_store_fault_cause; end end @@ -243,3 +243,4 @@ endtask : monitor_rvfi_instr `endif // __UVMA_RVFI_INSTR_MON_SV__ + diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_mon_trn_logger.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_mon_trn_logger.sv index 9c6dd10cf3..3428ad18ec 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_mon_trn_logger.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_mon_trn_logger.sv @@ -161,10 +161,10 @@ class uvma_rvfi_mon_trn_logger_c#(int ILEN=DEFAULT_ILEN, if (t.insn_interrupt) instr = $sformatf("%s INTR %0d", instr, t.insn_interrupt_id); - if (t.insn_nmi_load_fault) - instr = $sformatf("%s NMI LOAD", instr); - if (t.insn_nmi_store_fault) - instr = $sformatf("%s NMI STORE", instr); + if (t.insn_nmi) + instr = $sformatf("%s NMI FAULT", instr); + if (t.insn_nmi_cause) + instr = $sformatf("%s NMI CAUSE: %0d", instr, t.insn_nmi_cause); if (t.dbg) instr = $sformatf("%s DEBUG", instr); diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_pkg.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_pkg.sv index f968573013..deb510c71f 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_pkg.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_pkg.sv @@ -1,20 +1,20 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_RVFI_PKG_SV__ @@ -37,28 +37,28 @@ package uvma_rvfi_pkg; import uvml_trn_pkg ::*; import uvml_logs_pkg ::*; import uvma_core_cntrl_pkg::*; - + // Analysis implementation declarations `uvm_analysis_imp_decl(_rvfi_instr) // Constants / Structs / Enums `include "uvma_rvfi_constants.sv" `include "uvma_rvfi_tdefs.sv" - + // Objects `include "uvma_rvfi_cfg.sv" `include "uvma_rvfi_cntxt.sv" - + // High-level transactions - `include "seq/uvma_rvfi_csr_seq_item.sv" + `include "seq/uvma_rvfi_csr_seq_item.sv" `include "seq/uvma_rvfi_instr_seq_item.sv" `include "seq/uvma_rvfi_instr_table_seq_item.sv" - - // Agent components + + // Agent components `include "uvma_rvfi_mon_trn_logger.sv" - `include "uvma_rvfi_instr_mon.sv" + `include "uvma_rvfi_instr_mon.sv" `include "uvma_rvfi_agent.sv" - + endpackage : uvma_rvfi_pkg // Interface(s) / Module(s) / Checker(s) diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_tdefs.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_tdefs.sv index 3a283d7fd9..81dfce7be4 100644 --- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_tdefs.sv +++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_tdefs.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -25,6 +25,23 @@ typedef enum bit[MODE_WL-1:0] { UVMA_RVFI_M_MODE = 3 } uvma_rvfi_mode; +typedef struct packed { + logic [10:0] cause; + logic interrupt; + logic exception; + logic intr; +} rvfi_intr_t; + +typedef struct packed { + logic clicptr; + logic [1:0] cause_type; + logic [2:0] debug_cause; + logic [5:0] exception_cause; + logic debug; + logic exception; + logic trap; +} rvfi_trap_t; + function string get_mode_str(uvma_rvfi_mode mode); case (mode) UVMA_RVFI_U_MODE: return "U"; diff --git a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_agent.sv b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_agent.sv index 608441873b..c3e0ce1d6e 100644 --- a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_agent.sv +++ b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_agent.sv @@ -1,4 +1,4 @@ -// +// // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. @@ -6,15 +6,15 @@ // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -// +// `ifndef __UVMA_RVVI_AGENT_SV__ @@ -24,40 +24,40 @@ * Top-level component that encapsulates, builds and connects all others. * Capable of driving/monitoring Clock & Reset interface. */ -class uvma_rvvi_agent_c#(int ILEN=DEFAULT_ILEN, +class uvma_rvvi_agent_c#(int ILEN=DEFAULT_ILEN, int XLEN=DEFAULT_XLEN) extends uvm_agent; - + // Objects uvma_rvvi_cfg_c#(ILEN,XLEN) cfg; uvma_rvvi_cntxt_c#(ILEN,XLEN) cntxt; - - // Components + + // Components uvma_rvvi_state_mon_c#(ILEN,XLEN) state_monitor; uvma_rvvi_mon_trn_logger_c#(ILEN,XLEN) mon_trn_logger; uvma_rvvi_sqr_c#(ILEN,XLEN) sequencer; uvma_rvvi_drv_c#(ILEN,XLEN) driver; - - // TLM + + // TLM uvm_analysis_port#(uvma_rvvi_state_seq_item_c#(ILEN,XLEN)) state_mon_ap; - + string log_tag = "RVVIAGT"; `uvm_component_param_utils_begin(uvma_rvvi_agent_c#(ILEN,XLEN)) `uvm_field_object(cfg , UVM_DEFAULT) `uvm_field_object(cntxt, UVM_DEFAULT) - `uvm_component_utils_end - + `uvm_component_utils_end + /** * Default constructor. */ extern function new(string name="uvma_rvvi_agent", uvm_component parent=null); - + /** * 1. Ensures cfg & cntxt handles are not null * 2. Builds all components */ extern virtual function void build_phase(uvm_phase phase); - + /** * 1. Links agent's analysis ports to sub-components' * 2. Connects coverage models and loggers @@ -74,79 +74,80 @@ class uvma_rvvi_agent_c#(int ILEN=DEFAULT_ILEN, * Uses uvm_config_db to retrieve cfg and hand out to sub-components. */ extern virtual function void get_and_set_cfg(); - + /** * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. */ extern virtual function void get_and_set_cntxt(); - + /** * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this * agent. */ extern virtual function void retrieve_vif(); - + /** * Creates sub-components. */ extern virtual function void create_components(); - + /** * Connects sequencer and driver's TLM port(s). */ extern virtual function void connect_sequencer_and_driver(); - + /** * Connects agent's TLM ports to driver's and monitor's. */ extern virtual function void connect_analysis_ports(); - + /** * Connects coverage model to monitor and driver's analysis ports. */ extern virtual function void connect_cov_model(); - + /** * Connects transaction loggers to monitor and driver's analysis ports. */ extern virtual function void connect_trn_loggers(); - + endclass : uvma_rvvi_agent_c +/////////IMPLEMENTATION BEGINS////////////////////////////////////////////////// function uvma_rvvi_agent_c::new(string name="uvma_rvvi_agent", uvm_component parent=null); - + super.new(name, parent); - + endfunction : new function void uvma_rvvi_agent_c::build_phase(uvm_phase phase); - + super.build_phase(phase); - + get_and_set_cfg (); get_and_set_cntxt(); retrieve_vif (); create_components(); - + endfunction : build_phase function void uvma_rvvi_agent_c::connect_phase(uvm_phase phase); - + super.connect_phase(phase); - + connect_sequencer_and_driver(); connect_analysis_ports(); - + if (cfg.cov_model_enabled) begin connect_cov_model(); end if (cfg.trn_log_enabled) begin connect_trn_loggers(); end - + endfunction: connect_phase task uvma_rvvi_agent_c::run_phase(uvm_phase phase); @@ -154,7 +155,7 @@ task uvma_rvvi_agent_c::run_phase(uvm_phase phase); endtask : run_phase function void uvma_rvvi_agent_c::get_and_set_cfg(); - + void'(uvm_config_db#(uvma_rvvi_cfg_c#(ILEN,XLEN))::get(this, "", "cfg", cfg)); if (!cfg) begin `uvm_fatal("CFG", "Configuration handle is null") @@ -163,43 +164,53 @@ function void uvma_rvvi_agent_c::get_and_set_cfg(); `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) uvm_config_db#(uvma_rvvi_cfg_c#(ILEN,XLEN))::set(this, "*", "cfg", cfg); end - + endfunction : get_and_set_cfg function void uvma_rvvi_agent_c::get_and_set_cntxt(); - + void'(uvm_config_db#(uvma_rvvi_cntxt_c#(ILEN,XLEN))::get(this, "", "cntxt", cntxt)); if (!cntxt) begin `uvm_info("CNTXT", "Context handle is null; creating.", UVM_LOW) cntxt = uvma_rvvi_cntxt_c#(ILEN,XLEN)::type_id::create("cntxt"); end uvm_config_db#(uvma_rvvi_cntxt_c#(ILEN,XLEN))::set(this, "*", "cntxt", cntxt); - + endfunction : get_and_set_cntxt function void uvma_rvvi_agent_c::retrieve_vif(); - // State monitor - if (!uvm_config_db#(virtual RVVI_state#(ILEN,XLEN))::get(this, "", $sformatf("state_vif"), cntxt.state_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", - $typename(cntxt.state_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", - $typename(cntxt.state_vif)), UVM_DEBUG) - end - - // Control interface - if (!uvm_config_db#(virtual RVVI_control)::get(this, "", $sformatf("control_vif"), cntxt.control_vif)) begin - `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", - $typename(cntxt.control_vif))) - end - else begin - `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", - $typename(cntxt.control_vif)), UVM_DEBUG) - end + case (cfg.rvvi_version) + UVMA_RVVI_V1: begin + // State monitor + if (!uvm_config_db#(virtual RVVI_state#(ILEN,XLEN))::get(this, "", $sformatf("state_vif"), cntxt.state_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", + $typename(cntxt.state_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", + $typename(cntxt.state_vif)), UVM_DEBUG) + end + + // Control interface + if (!uvm_config_db#(virtual RVVI_control)::get(this, "", $sformatf("control_vif"), cntxt.control_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", + $typename(cntxt.control_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", + $typename(cntxt.control_vif)), UVM_DEBUG) + end + end + UVMA_RVVI_V2: begin + `uvm_fatal("VIF", "RVVI_V2 not yet supported") + end + default: begin + `uvm_fatal("VIF", $sformatf("Unknown RVVI_VERSION %s in uvm_config_db", cfg.rvvi_version)) + end + endcase endfunction : retrieve_vif @@ -208,7 +219,7 @@ function void uvma_rvvi_agent_c::create_components(); state_monitor = uvma_rvvi_state_mon_c#(ILEN,XLEN) ::type_id::create("state_monitor" , this); mon_trn_logger = uvma_rvvi_mon_trn_logger_c#(ILEN,XLEN)::type_id::create("mon_trn_logger" , this); - + if (cfg.is_active == UVM_ACTIVE) begin sequencer = uvma_rvvi_sqr_c#(ILEN,XLEN)::type_id::create("sequencer", this); end @@ -217,27 +228,27 @@ endfunction : create_components function void uvma_rvvi_agent_c::connect_sequencer_and_driver(); if (cfg.is_active == UVM_ACTIVE) begin - driver.seq_item_port.connect(sequencer.seq_item_export); + driver.seq_item_port.connect(sequencer.seq_item_export); end endfunction : connect_sequencer_and_driver function void uvma_rvvi_agent_c::connect_analysis_ports(); - + state_mon_ap = state_monitor.ap; endfunction : connect_analysis_ports function void uvma_rvvi_agent_c::connect_cov_model(); - - //mon_ap.connect(cov_model.mon_trn_fifo.analysis_export); - + + //mon_ap.connect(cov_model.mon_trn_fifo.analysis_export); + endfunction : connect_cov_model function void uvma_rvvi_agent_c::connect_trn_loggers(); - + state_mon_ap.connect(mon_trn_logger.state_export); endfunction : connect_trn_loggers diff --git a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cfg.sv b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cfg.sv index df2b653ce4..3be4bfbe25 100644 --- a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cfg.sv +++ b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cfg.sv @@ -39,6 +39,7 @@ class uvma_rvvi_cfg_c#(int ILEN=DEFAULT_ILEN, // Common options rand bit enabled; rand uvm_active_passive_enum is_active; + rand uvma_rvvi_version_enum rvvi_version; rand bit cov_model_enabled; rand bit trn_log_enabled; @@ -48,6 +49,7 @@ class uvma_rvvi_cfg_c#(int ILEN=DEFAULT_ILEN, `uvm_object_utils_begin(uvma_rvvi_cfg_c) `uvm_field_int ( enabled , UVM_DEFAULT) `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT) + `uvm_field_enum(uvma_rvvi_version_enum, rvvi_version , UVM_DEFAULT) `uvm_field_int ( cov_model_enabled , UVM_DEFAULT) `uvm_field_int ( trn_log_enabled , UVM_DEFAULT) `uvm_object_utils_end @@ -55,6 +57,7 @@ class uvma_rvvi_cfg_c#(int ILEN=DEFAULT_ILEN, constraint defaults_cons { soft enabled == 1; soft is_active == UVM_PASSIVE; + soft rvvi_version == UVMA_RVVI_V1; soft cov_model_enabled == 0; soft trn_log_enabled == 1; } @@ -82,6 +85,8 @@ class uvma_rvvi_cfg_c#(int ILEN=DEFAULT_ILEN, endclass : uvma_rvvi_cfg_c +/////////IMPLEMENTATION BEGINS////////////////////////////////////////////////// + function uvma_rvvi_cfg_c::new(string name="uvma_rvvi_cfg"); super.new(name); diff --git a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cntxt.sv b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cntxt.sv index a446f6e676..f5b0bb308c 100644 --- a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cntxt.sv +++ b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_cntxt.sv @@ -32,6 +32,9 @@ class uvma_rvvi_cntxt_c#(int ILEN=DEFAULT_ILEN, // Control RVVI interface virtual RVVI_control control_vif; + // V2 interface + virtual rvviTrace rvvi_vif; + // Events uvm_event sample_cfg_e; uvm_event sample_cntxt_e; @@ -53,9 +56,7 @@ class uvma_rvvi_cntxt_c#(int ILEN=DEFAULT_ILEN, endclass : uvma_rvvi_cntxt_c - -`pragma protect begin - +/////////IMPLEMENTATION BEGINS////////////////////////////////////////////////// function uvma_rvvi_cntxt_c::new(string name="uvma_rvvi_cntxt"); @@ -71,7 +72,4 @@ function void uvma_rvvi_cntxt_c::reset(); endfunction : reset -`pragma protect end - - `endif // __UVMA_RVVI_CNTXT_SV__ diff --git a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_tdefs.sv b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_tdefs.sv index 679b6a95c4..8c6dcb79fe 100644 --- a/lib/uvm_agents/uvma_rvvi/uvma_rvvi_tdefs.sv +++ b/lib/uvm_agents/uvma_rvvi/uvma_rvvi_tdefs.sv @@ -1,13 +1,13 @@ // Copyright 2020 OpenHW Group // Copyright 2020 Datum Technology Corporation // Copyright 2020 Silicon Labs, Inc. -// +// // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// +// // https://solderpad.org/licenses/ -// +// // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -31,15 +31,20 @@ typedef enum int unsigned { UVMA_RVVI_HALT = 2 } uvma_rvvi_rm_action; +typedef enum int unsigned { + UVMA_RVVI_V1 = 0, + UVMA_RVVI_V2 = 1 +} uvma_rvvi_version_enum; + function string get_mode_str(uvma_rvvi_mode mode); case (mode) UVMA_RVVI_U_MODE: return "U"; UVMA_RVVI_M_MODE: return "M"; - UVMA_RVVI_S_MODE: return "S"; + UVMA_RVVI_S_MODE: return "S"; endcase return "?"; - + endfunction : get_mode_str `endif // __UVMA_RVVI_TDEFS_SV__ diff --git a/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq.sv b/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq.sv index 1d70711927..ea7c72a2ea 100644 --- a/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq.sv +++ b/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq.sv @@ -66,8 +66,8 @@ task uvma_rvvi_ovpsim_control_seq_c::step_rm(uvma_rvfi_instr_seq_item_c#(ILEN,XL intr_id == rvfi_instr.insn_interrupt_id; insn_bus_fault == rvfi_instr.insn_bus_fault; - nmi_load_fault == rvfi_instr.insn_nmi_load_fault; - nmi_store_fault == rvfi_instr.insn_nmi_store_fault; + nmi == rvfi_instr.insn_nmi; + nmi_cause == rvfi_instr.insn_nmi_cause; dbg_req == (rvfi_instr.dbg_mode && rvfi_instr.dbg inside {3,5}); dbg_mode == rvfi_instr.dbg_mode; @@ -76,6 +76,11 @@ task uvma_rvvi_ovpsim_control_seq_c::step_rm(uvma_rvfi_instr_seq_item_c#(ILEN,XL rd1_addr == rvfi_instr.rd1_addr; rd1_wdata == rvfi_instr.rd1_wdata; + gpr_rdata == rvfi_instr.gpr_rdata; + gpr_rmask == rvfi_instr.gpr_rmask; + gpr_wdata == rvfi_instr.gpr_wdata; + gpr_wmask == rvfi_instr.gpr_wmask; + mem_addr == rvfi_instr.mem_addr; mem_rdata == rvfi_instr.mem_rdata; mem_rmask == rvfi_instr.mem_rmask; diff --git a/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq_item.sv b/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq_item.sv index 7a6c628a7e..8b53dff9b7 100644 --- a/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq_item.sv +++ b/lib/uvm_agents/uvma_rvvi_ovpsim/seq/uvma_rvvi_ovpsim_control_seq_item.sv @@ -37,11 +37,17 @@ class uvma_rvvi_ovpsim_control_seq_item_c#(int ILEN=uvma_rvvi_pkg::DEFAULT_ILEN, // Set to signal in debug mode rand bit dbg_mode; - // Set to signal nmi load fault - rand bit nmi_load_fault; + // Set to signal nmi + rand bit nmi; - // Set to signal nmi store fault - rand bit nmi_store_fault; + // Set to signal nmi cause + rand bit [XLEN-1:0] nmi_cause; + + // Set to signal nmi load parity fault + rand bit nmi_load_parity_fault; + + // Set to signal nmi store parity fault + rand bit nmi_store_parity_fault; // Set to signal instruction bus error rand bit insn_bus_fault; @@ -54,12 +60,19 @@ class uvma_rvvi_ovpsim_control_seq_item_c#(int ILEN=uvma_rvvi_pkg::DEFAULT_ILEN, rand bit [GPR_ADDR_WL-1:0] rd1_addr; rand bit [XLEN-1:0] rd1_wdata; + // Backdoor hint of register writes in the case of + // an interrupted multi-operation instruction + rand bit [(32*XLEN)-1:0] gpr_rdata; + rand bit [(32)-1:0] gpr_rmask; + rand bit [(32*XLEN)-1:0] gpr_wdata; + rand bit [(32)-1:0] gpr_wmask; + // Backdoor hint of memory transaction for ensuring memory model is updated with volatile read data - rand bit [XLEN-1:0] mem_addr; - rand bit [XLEN-1:0] mem_rdata; - rand bit [XLEN-1:0] mem_wdata; - rand bit [XLEN/8-1:0] mem_rmask; - rand bit [XLEN/8-1:0] mem_wmask; + rand bit [(NMEM*XLEN)-1:0] mem_addr; + rand bit [(NMEM*XLEN)-1:0] mem_rdata; + rand bit [(NMEM*XLEN/8)-1:0] mem_rmask; + rand bit [(NMEM*XLEN)-1:0] mem_wdata; + rand bit [(NMEM*XLEN/8)-1:0] mem_wmask; static protected string _log_format_string = "0x%08x %s 0x%01x 0x%08x"; @@ -67,13 +80,17 @@ class uvma_rvvi_ovpsim_control_seq_item_c#(int ILEN=uvma_rvvi_pkg::DEFAULT_ILEN, `uvm_field_int(intr, UVM_DEFAULT) `uvm_field_int(dbg_req, UVM_DEFAULT) `uvm_field_int(dbg_mode, UVM_DEFAULT) - `uvm_field_int(nmi_load_fault, UVM_DEFAULT) - `uvm_field_int(nmi_store_fault, UVM_DEFAULT) + `uvm_field_int(nmi, UVM_DEFAULT) + `uvm_field_int(nmi_cause, UVM_DEFAULT) `uvm_field_int(insn_bus_fault, UVM_DEFAULT) `uvm_field_int(mip, UVM_DEFAULT) `uvm_field_int(intr_id, UVM_DEFAULT) `uvm_field_int(rd1_addr, UVM_DEFAULT) `uvm_field_int(rd1_wdata, UVM_DEFAULT) + `uvm_field_int(gpr_rmask, UVM_DEFAULT) + `uvm_field_int(gpr_rdata, UVM_DEFAULT) + `uvm_field_int(gpr_wmask, UVM_DEFAULT) + `uvm_field_int(gpr_wdata, UVM_DEFAULT) `uvm_field_int(mem_addr, UVM_DEFAULT) `uvm_field_int(mem_rdata, UVM_DEFAULT) `uvm_field_int(mem_rmask, UVM_DEFAULT) @@ -91,6 +108,46 @@ class uvma_rvvi_ovpsim_control_seq_item_c#(int ILEN=uvma_rvvi_pkg::DEFAULT_ILEN, */ extern function string convert2string(); + /* + * Return GPR wdata + */ + extern function bit [XLEN-1:0] get_gpr_wdata(int gpr); + + /* + * Return GPR rdata + */ + extern function bit [XLEN-1:0] get_gpr_rdata(int gpr); + + + /* + * Return memory transaction data + */ + extern function bit [XLEN-1:0] get_mem_data_word(int txn); + + /* + * Return memory transaction addr + */ + extern function bit [XLEN-1:0] get_mem_addr(int txn); + + /* + * Return memory transaction wmask + */ + extern function bit [(XLEN/8)-1:0] get_mem_wmask(int txn); + + /* + * Return memory transaction rmask + */ + extern function bit [(XLEN/8)-1:0] get_mem_rmask(int txn); + + /* + * Check memory transaction activity + * + * Checks if a position in the rvfi memory transaction list + * indicates any activity. + * return {read, write} + */ + extern function bit [1:0] check_mem_act(int txn); + endclass : uvma_rvvi_ovpsim_control_seq_item_c `pragma protect begin @@ -108,6 +165,64 @@ function string uvma_rvvi_ovpsim_control_seq_item_c::convert2string(); endfunction : convert2string + +function bit [XLEN-1:0] uvma_rvvi_ovpsim_control_seq_item_c::get_gpr_wdata(int gpr); + return gpr_wdata[gpr*XLEN +:XLEN]; +endfunction : get_gpr_wdata + +function bit [XLEN-1:0] uvma_rvvi_ovpsim_control_seq_item_c::get_gpr_rdata(int gpr); + return gpr_rdata[gpr*XLEN +:XLEN]; +endfunction : get_gpr_rdata + +function bit [XLEN-1:0] uvma_rvvi_ovpsim_control_seq_item_c::get_mem_data_word(int txn); + bit [XLEN-1:0] ret; + + for (int i = 0; i < XLEN/8; i++) begin + if (mem_wmask[(txn*XLEN/8) + i]) begin + ret[i*8 +:8] = mem_wdata[((txn*XLEN) + (i*8)) +:8]; + end else begin + ret[i*8 +:8] = mem_rdata[((txn*XLEN) + (i*8)) +:8]; + end + end + + return ret; + +endfunction : get_mem_data_word + +function bit [XLEN-1:0] uvma_rvvi_ovpsim_control_seq_item_c::get_mem_addr(int txn); + + return mem_addr[txn*XLEN +:XLEN]; + +endfunction : get_mem_addr + +function bit [(XLEN/8)-1:0] uvma_rvvi_ovpsim_control_seq_item_c::get_mem_rmask(int txn); + + return mem_rmask[(txn*XLEN/8) +:(XLEN/8)]; + +endfunction : get_mem_rmask + +function bit [(XLEN/8)-1:0] uvma_rvvi_ovpsim_control_seq_item_c::get_mem_wmask(int txn); + + return mem_wmask[(txn*XLEN/8) +:(XLEN/8)]; + +endfunction : get_mem_wmask + +function bit [1:0] uvma_rvvi_ovpsim_control_seq_item_c::check_mem_act(int txn); + static bit read = 0; + static bit write = 0; + + if (mem_rmask[(txn*XLEN/8) +:(XLEN/8)]) begin + read = 1; + end + if (mem_wmask[(txn*XLEN/8) +:(XLEN/8)]) begin + write = 1; + end + + return {read,write}; + +endfunction : check_mem_act + + `pragma protect end diff --git a/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_agent.sv b/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_agent.sv index 70ef58718b..284df9084b 100644 --- a/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_agent.sv +++ b/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_agent.sv @@ -103,55 +103,103 @@ function void uvma_rvvi_ovpsim_agent_c::configure_iss(); // and populates any configuration YAML defined options // Note that such use shoulbe be for testing only and nearly all ovpsim.ic switches should be integrated to this method - int fh; + int fh; // file handle ISS control file (typically ovpsim.ic). + string refpath; // root of config path in ISS control file. + + if (cfg.core_cfg.use_iss) begin + refpath = "root/cpu"; // path for OVPsim + end + else begin + refpath = "cpu"; // path for ImperasDV + end fh = $fopen(cfg.core_cfg.iss_control_file, "a"); // ------------------------------------------------------------------------------------- // ISA Extension support // ------------------------------------------------------------------------------------- - $fwrite(fh, $sformatf("--override root/cpu/misa_Extensions=0x%06x\n", cfg.core_cfg.get_misa())); - // TODO: cv32e40x: Remove when correct setting is applied to ovpsim - if (cfg.core_cfg.core_name == "CV32E40X") begin - $fwrite(fh, $sformatf("--override root/cpu/tcontrol_undefined=0\n")); - end + $fwrite(fh, $sformatf("--override %s/misa_Extensions=0x%06x\n", refpath, cfg.core_cfg.get_misa())); + + // TODO silabs-hfegran: cv32e40x: Remove when correct setting is applied to ovpsim, + // settings that need to remain should be moved to core-specific config, this file needs + // to stay generic + if (cfg.core_cfg.core_name == "CV32E40X" || cfg.core_cfg.core_name == "CV32E40S") begin + $fwrite(fh, $sformatf("--override %s/tcontrol_undefined=0\n", refpath)); + $fwrite(fh, $sformatf("--override %s/mtvec_mask=0xffffff81\n", refpath)); + $fwrite(fh, $sformatf("--override %s/instret_undefined=0\n", refpath)); + $fwrite(fh, $sformatf("--override %s/mcontext_undefined=T\n", refpath)); + $fwrite(fh, $sformatf("--override %s/mscontext_undefined=T\n", refpath)); + $fwrite(fh, $sformatf("--override %s/scontext_undefined=T\n", refpath)); + $fwrite(fh, $sformatf("--override %s/ecode_mask=2047\n", refpath)); + end + + // TODO:silabs-robin remove after rtl/iss has synched up at a stable versioning scheme + if (cfg.core_cfg.core_name == "CV32E40S") begin + $fwrite(fh, $sformatf("--override %s/Zcb=0\n", refpath)); + end + + // TODO silabs-hfegran: Check that this is on by default in 40S model when ISS v0.4.0 is implemented + // Already in rtl, so to match, it will be enabled now + if (cfg.core_cfg.core_name == "CV32E40S") begin + $fwrite(fh, $sformatf("--override %s/Smstateen=T\n", refpath)); + end + + // TODO hf: Find a better way to put this in the 40x/40s-structure + if (cfg.core_cfg.core_name == "CV32E40X" || cfg.core_cfg.core_name == "CV32E40S") begin + $fwrite(fh, $sformatf("--override %s/scontext_undefined=1\n", refpath)); + $fwrite(fh, $sformatf("--override %s/ecode_mask=0x7ff\n", refpath)); + $fwrite(fh, $sformatf("--override %s/mtvec_mask=0xffffff81\n", refpath)); + $fwrite(fh, $sformatf("--override %s/Zca=1\n", refpath)); + $fwrite(fh, $sformatf("--override %s/Zcb=0\n", refpath)); + $fwrite(fh, $sformatf("--override %s/Zcmp=0\n", refpath)); + $fwrite(fh, $sformatf("--override %s/Zcmb=0\n", refpath)); + $fwrite(fh, $sformatf("--override %s/Zcmt=0\n", refpath)); + + end if (cfg.core_cfg.is_ext_b_supported()) begin // Bitmanip version case (cfg.core_cfg.bitmanip_version) - BITMANIP_VERSION_0P90: $fwrite(fh, $sformatf("--override root/cpu/bitmanip_version=0.90\n")); - BITMANIP_VERSION_0P91: $fwrite(fh, $sformatf("--override root/cpu/bitmanip_version=0.91\n")); - BITMANIP_VERSION_0P92: $fwrite(fh, $sformatf("--override root/cpu/bitmanip_version=0.92\n")); - BITMANIP_VERSION_0P93: $fwrite(fh, $sformatf("--override root/cpu/bitmanip_version=0.93\n")); - BITMANIP_VERSION_0P93_DRAFT: $fwrite(fh, $sformatf("--override root/cpu/bitmanip_version=0.93-draft\n")); - BITMANIP_VERSION_0P94: $fwrite(fh, $sformatf("--override root/cpu/bitmanip_version=0.94\n")); - BITMANIP_VERSION_1P00: $fwrite(fh, $sformatf("--override root/cpu/bitmanip_version=1.0.0\n")); + BITMANIP_VERSION_0P90: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.90\n", refpath)); + BITMANIP_VERSION_0P91: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.91\n", refpath)); + BITMANIP_VERSION_0P92: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.92\n", refpath)); + BITMANIP_VERSION_0P93: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.93\n", refpath)); + BITMANIP_VERSION_0P93_DRAFT: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.93-draft\n", refpath)); + BITMANIP_VERSION_0P94: $fwrite(fh, $sformatf("--override %s/bitmanip_version=0.94\n", refpath)); + BITMANIP_VERSION_1P00: $fwrite(fh, $sformatf("--override %s/bitmanip_version=1.0.0\n", refpath)); endcase // Bitmanip extensions - $fwrite(fh, $sformatf("--override root/cpu/Zba=%0d\n", cfg.core_cfg.ext_zba_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbb=%0d\n", cfg.core_cfg.ext_zbb_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbc=%0d\n", cfg.core_cfg.ext_zbc_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbe=%0d\n", cfg.core_cfg.ext_zbe_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbf=%0d\n", cfg.core_cfg.ext_zbf_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbm=%0d\n", cfg.core_cfg.ext_zbm_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbp=%0d\n", cfg.core_cfg.ext_zbp_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbr=%0d\n", cfg.core_cfg.ext_zbr_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbs=%0d\n", cfg.core_cfg.ext_zbs_supported)); - $fwrite(fh, $sformatf("--override root/cpu/Zbt=%0d\n", cfg.core_cfg.ext_zbt_supported)); + $fwrite(fh, $sformatf("--override %s/Zba=%0d\n", refpath, cfg.core_cfg.ext_zba_supported)); + $fwrite(fh, $sformatf("--override %s/Zbb=%0d\n", refpath, cfg.core_cfg.ext_zbb_supported)); + $fwrite(fh, $sformatf("--override %s/Zbc=%0d\n", refpath, cfg.core_cfg.ext_zbc_supported)); + $fwrite(fh, $sformatf("--override %s/Zbe=%0d\n", refpath, cfg.core_cfg.ext_zbe_supported)); + $fwrite(fh, $sformatf("--override %s/Zbf=%0d\n", refpath, cfg.core_cfg.ext_zbf_supported)); + $fwrite(fh, $sformatf("--override %s/Zbm=%0d\n", refpath, cfg.core_cfg.ext_zbm_supported)); + $fwrite(fh, $sformatf("--override %s/Zbp=%0d\n", refpath, cfg.core_cfg.ext_zbp_supported)); + $fwrite(fh, $sformatf("--override %s/Zbr=%0d\n", refpath, cfg.core_cfg.ext_zbr_supported)); + $fwrite(fh, $sformatf("--override %s/Zbs=%0d\n", refpath, cfg.core_cfg.ext_zbs_supported)); + $fwrite(fh, $sformatf("--override %s/Zbt=%0d\n", refpath, cfg.core_cfg.ext_zbt_supported)); end + case(cfg.core_cfg.debug_spec_version) + DEBUG_VERSION_0_13_2: $fwrite(fh, $sformatf("--override %s/debug_version=0.13.2-DRAFT\n", refpath)); + DEBUG_VERSION_0_14_0: $fwrite(fh, $sformatf("--override %s/debug_version=0.14.0-DRAFT\n", refpath)); + DEBUG_VERSION_1_0_0: $fwrite(fh, $sformatf("--override %s/debug_version=1.0.0-STABLE\n", refpath)); + endcase + case(cfg.core_cfg.priv_spec_version) - PRIV_VERSION_MASTER: $fwrite(fh, $sformatf("--override root/cpu/priv_version=master\n")); - PRIV_VERSION_1_10: $fwrite(fh, $sformatf("--override root/cpu/priv_version=1.10\n")); - PRIV_VERSION_1_11: $fwrite(fh, $sformatf("--override root/cpu/priv_version=1.11\n")); - PRIV_VERSION_20190405: $fwrite(fh, $sformatf("--override root/cpu/priv_version=20190405\n")); + PRIV_VERSION_MASTER: $fwrite(fh, $sformatf("--override %s/priv_version=master\n", refpath)); + PRIV_VERSION_1_10: $fwrite(fh, $sformatf("--override %s/priv_version=1.10\n", refpath)); + PRIV_VERSION_1_11: $fwrite(fh, $sformatf("--override %s/priv_version=1.11\n", refpath)); + PRIV_VERSION_1_12: $fwrite(fh, $sformatf("--override %s/priv_version=1.12\n", refpath)); + PRIV_VERSION_20190405: $fwrite(fh, $sformatf("--override %s/priv_version=20190405\n", refpath)); endcase - if (cfg.core_cfg.priv_spec_version == PRIV_VERSION_MASTER) begin + if (cfg.core_cfg.priv_spec_version == PRIV_VERSION_1_12) begin case(cfg.core_cfg.endianness) - ENDIAN_LITTLE, ENDIAN_BIG: $fwrite(fh, $sformatf("--override root/cpu/endianFixed=1\n")); - ENDIAN_MIXED: $fwrite(fh, $sformatf("--override root/cpu/endianFixed=0\n")); + ENDIAN_LITTLE, ENDIAN_BIG: $fwrite(fh, $sformatf("--override %s/endianFixed=1\n", refpath)); + ENDIAN_MIXED: $fwrite(fh, $sformatf("--override %s/endianFixed=0\n", refpath)); endcase end @@ -159,33 +207,35 @@ function void uvma_rvvi_ovpsim_agent_c::configure_iss(); // ------------------------------------------------------------------------------------- // Boot strap pins // ------------------------------------------------------------------------------------- - $fwrite(fh, $sformatf("--override root/cpu/mhartid=%0d\n", cfg.core_cfg.mhartid)); - $fwrite(fh, $sformatf("--override root/cpu/mimpid=%0d\n", cfg.core_cfg.mimpid)); - $fwrite(fh, $sformatf("--override root/cpu/startaddress=0x%08x\n", cfg.core_cfg.boot_addr)); + $fwrite(fh, $sformatf("--override %s/mhartid=%0d\n", refpath, cfg.core_cfg.mhartid)); + $fwrite(fh, $sformatf("--override %s/mimpid=%0d\n", refpath, cfg.core_cfg.mimpid)); + $fwrite(fh, $sformatf("--override %s/startaddress=0x%08x\n", refpath, cfg.core_cfg.boot_addr)); // Specification forces mtvec[0] high at reset regardless of bootstrap pin state of mtvec_addr_i]0] - $fwrite(fh, $sformatf("--override root/cpu/mtvec=0x%08x\n", cfg.core_cfg.mtvec_addr| 32'h1)); - $fwrite(fh, $sformatf("--override root/cpu/nmi_address=0x%08x\n", cfg.core_cfg.nmi_addr)); - $fwrite(fh, $sformatf("--override root/cpu/debug_address=0x%08x\n", cfg.core_cfg.dm_halt_addr)); - $fwrite(fh, $sformatf("--override root/cpu/dexc_address=0x%08x\n", cfg.core_cfg.dm_exception_addr)); + $fwrite(fh, $sformatf("--override %s/mtvec=0x%08x\n", refpath, cfg.core_cfg.mtvec_addr | 32'b1)); + $fwrite(fh, $sformatf("--override %s/nmi_address=0x%08x\n", refpath, cfg.core_cfg.nmi_addr)); + $fwrite(fh, $sformatf("--override %s/debug_address=0x%08x\n", refpath, cfg.core_cfg.dm_halt_addr)); + $fwrite(fh, $sformatf("--override %s/dexc_address=0x%08x\n", refpath, cfg.core_cfg.dm_exception_addr)); // ------------------------------------------------------------------------------------- // Parameters // ------------------------------------------------------------------------------------- // NUM_MHPMCOUNTERS - Set zero in the noinhibit_mask to enable a counter, starting from index 3 - $fwrite(fh, $sformatf("--override root/cpu/noinhibit_mask=0x%08x\n", cfg.core_cfg.get_noinhibit_mask())); + $fwrite(fh, $sformatf("--override %s/noinhibit_mask=0x%08x\n", refpath, cfg.core_cfg.get_noinhibit_mask())); // PMA Regions - $fwrite(fh, $sformatf("--override root/cpu/extension/PMA_NUM_REGIONS=%0d\n", cfg.core_cfg.pma_regions.size())); + $fwrite(fh, $sformatf("--override %s/extension_*/PMA_NUM_REGIONS=%0d\n", refpath, cfg.core_cfg.pma_regions.size())); foreach (cfg.core_cfg.pma_regions[i]) begin - $fwrite(fh, $sformatf("--override root/cpu/extension/word_addr_low%0d=0x%08x\n", i, cfg.core_cfg.pma_regions[i].word_addr_low)); - $fwrite(fh, $sformatf("--override root/cpu/extension/word_addr_high%0d=0x%08x\n", i, cfg.core_cfg.pma_regions[i].word_addr_high)); - $fwrite(fh, $sformatf("--override root/cpu/extension/main%0d=%0d\n", i, cfg.core_cfg.pma_regions[i].main)); - $fwrite(fh, $sformatf("--override root/cpu/extension/bufferable%0d=%0d\n", i, cfg.core_cfg.pma_regions[i].bufferable)); - $fwrite(fh, $sformatf("--override root/cpu/extension/cacheable%0d=%0d\n", i, cfg.core_cfg.pma_regions[i].cacheable)); - $fwrite(fh, $sformatf("--override root/cpu/extension/atomic%0d=%0d\n", i, cfg.core_cfg.pma_regions[i].atomic)); + $fwrite(fh, $sformatf("--override %s/extension_*/word_addr_low%0d=0x%08x\n", refpath, i, cfg.core_cfg.pma_regions[i].word_addr_low)); + $fwrite(fh, $sformatf("--override %s/extension_*/word_addr_high%0d=0x%08x\n", refpath, i, cfg.core_cfg.pma_regions[i].word_addr_high)); + $fwrite(fh, $sformatf("--override %s/extension_*/main%0d=%0d\n", refpath, i, cfg.core_cfg.pma_regions[i].main)); + $fwrite(fh, $sformatf("--override %s/extension_*/bufferable%0d=%0d\n", refpath, i, cfg.core_cfg.pma_regions[i].bufferable)); + $fwrite(fh, $sformatf("--override %s/extension_*/cacheable%0d=%0d\n", refpath, i, cfg.core_cfg.pma_regions[i].cacheable)); + $fwrite(fh, $sformatf("--override %s/extension_*/atomic%0d=%0d\n", refpath, i, cfg.core_cfg.pma_regions[i].atomic)); end + // Enable use of hw reg names instead of abi + $fwrite(fh, $sformatf("--override %s/use_hw_reg_names=T\n", refpath)); $fclose(fh); endfunction : configure_iss diff --git a/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_drv.sv b/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_drv.sv index 3031aa0a83..d08451f029 100644 --- a/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_drv.sv +++ b/lib/uvm_agents/uvma_rvvi_ovpsim/uvma_rvvi_ovpsim_drv.sv @@ -88,24 +88,19 @@ class uvma_rvvi_ovpsim_drv_c#(int ILEN=uvma_rvvi_pkg::DEFAULT_ILEN, extern virtual task halt(REQ req); /** - * Special RVVI step to signal an external interrupt is to be taken - */ - extern virtual task stepi_ext_intr(int unsigned intr_id); - - /** - * Special RVVI step to signal a load fault NMI + * Special RVVI step to signal debug is to be taken */ - extern virtual task stepi_nmi_load_fault(); + extern virtual task stepi_debug(bit nmi, bit intr, int unsigned nmi_cause, int unsigned intr_id); /** - * Special RVVI step to signal a store fault NMI + * Special RVVI step to signal an external interrupt is to be taken */ - extern virtual task stepi_nmi_store_fault(); + extern virtual task stepi_ext_intr(int unsigned intr_id); /** - * Special RVVI step to signal an external debug request + * Special RVVI step to signal an NMI */ - extern virtual task stepi_haltreq(); + extern virtual task stepi_nmi(int unsigned cause); /** * Special RVVI step to signal an instruction bus fault @@ -161,6 +156,9 @@ task uvma_rvvi_ovpsim_drv_c::stepi(REQ req); bit[31:0] mem_val_update = 0; bit[31:0] mem_val_prev = 0; bit[XLEN-1:0] mask = 'h0; + bit[XLEN-1:0] mem_addr = 0; + bit[(XLEN/8)-1:0] mem_rmask = 0; + uvma_rvvi_ovpsim_control_seq_item_c#(ILEN,XLEN) rvvi_ovpsim_seq_item; @@ -179,46 +177,51 @@ task uvma_rvvi_ovpsim_drv_c::stepi(REQ req); // Check for read of volatile memory locations, backdoor init the RVVI memory when found to ensure // the ISS sees the same data as the DUT - if (rvvi_ovpsim_seq_item.mem_rmask && cfg.is_mem_addr_volatile(rvvi_ovpsim_seq_item.mem_addr)) begin + for (int i = 0; i < NMEM; i++) begin - // handle misaligned case - mem_val_update = rvvi_ovpsim_seq_item.mem_rdata; - if (rvvi_ovpsim_seq_item.mem_addr[1:0] != 0) begin - mem_val_update <<= 8*rvvi_ovpsim_seq_item.mem_addr[1:0]; - end + if ((rvvi_ovpsim_seq_item.check_mem_act(i) & 'b10) && cfg.is_mem_addr_volatile(rvvi_ovpsim_seq_item.get_mem_addr(i))) begin + mem_addr = rvvi_ovpsim_seq_item.get_mem_addr(i); + mem_rmask = rvvi_ovpsim_seq_item.get_mem_rmask(i); - for (int i=0; i < XLEN/8; i++) - begin - bit [7:0] mask_val; - mask_val = rvvi_ovpsim_seq_item.mem_rmask[i] ? 8'hFF : 8'h00; - mask[(i+1)*8-1-:8] = mask_val; - end + // handle misaligned case + mem_val_update = rvvi_ovpsim_seq_item.get_mem_data_word(i); + if (mem_addr[1:0] != 0) begin + mem_val_update <<= 8*mem_addr[1:0]; + end - mem_val_prev = rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[rvvi_ovpsim_seq_item.mem_addr >> 2]; - rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[rvvi_ovpsim_seq_item.mem_addr >> 2] = (mem_val_prev & ~mask) | (mem_val_update & mask); + for (int i=0; i < XLEN/8; i++) + begin + bit [7:0] mask_val; + mask_val = mem_rmask[i] ? 8'hFF : 8'h00; + mask[(i+1)*8-1-:8] = mask_val; + end - `uvm_info("RVVIDRV", $sformatf("Setting volatile bus read data @ 0x%08x to 0x%08x", - rvvi_ovpsim_seq_item.mem_addr, - (mem_val_prev & ~mask) | (mem_val_update & mask)), UVM_HIGH); + mem_val_prev = rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[mem_addr >> 2]; + rvvi_ovpsim_cntxt.ovpsim_mem_vif.mem[mem_addr >> 2] = (mem_val_prev & ~mask) | (mem_val_update & mask); - end + `uvm_info("RVVIDRV", $sformatf("Setting volatile bus read data @ 0x%08x to 0x%08x", + mem_addr, + (mem_val_prev & ~mask) | (mem_val_update & mask)), UVM_HIGH); - // Signal a NMI to the ISS in M-mode - if (rvvi_ovpsim_seq_item.nmi_load_fault) begin - stepi_nmi_load_fault(); - end - else if (rvvi_ovpsim_seq_item.nmi_store_fault) begin - stepi_nmi_store_fault(); - end + end - // Signal an interrupt to the ISS if mcause and rvfi_intr signals external interrupt - if (rvvi_ovpsim_seq_item.intr) begin - stepi_ext_intr(rvvi_ovpsim_seq_item.intr_id); end - // External halt request to debug mode + // Signal a debug to ISS. Interrupts that was not retired due to debug + // are also signaled here if (rvvi_ovpsim_seq_item.dbg_req) begin - stepi_haltreq(); + stepi_debug(rvvi_ovpsim_seq_item.nmi, rvvi_ovpsim_seq_item.intr, rvvi_ovpsim_seq_item.nmi_cause, rvvi_ovpsim_seq_item.intr_id); + end else begin + + // Signal a NMI to the ISS in M-mode + if (rvvi_ovpsim_seq_item.nmi) begin + stepi_nmi(rvvi_ovpsim_seq_item.nmi_cause); + end + + // Signal an interrupt to the ISS if mcause and rvfi_intr signals external interrupt + if (rvvi_ovpsim_seq_item.intr) begin + stepi_ext_intr(rvvi_ovpsim_seq_item.intr_id); + end end // Signal instruction bus fault @@ -226,13 +229,19 @@ task uvma_rvvi_ovpsim_drv_c::stepi(REQ req); stepi_insn_bus_fault(); end - // Update irq_i to match mip CSR + // Update irq_i to match mip CSRF1 harassment + rvvi_ovpsim_cntxt.ovpsim_io_vif.irq_i = rvvi_ovpsim_seq_item.mip; // If the RVFI instruction wrote to a GPR, update it in the volatile backdoor register back // so the ISS can update voltaile reads (e.g. mcycle, I/O registers, etc.) - if (rvvi_ovpsim_seq_item.rd1_addr != 0) - rvvi_ovpsim_cntxt.state_vif.GPR_rtl[rvvi_ovpsim_seq_item.rd1_addr] = rvvi_ovpsim_seq_item.rd1_wdata; + if (rvvi_ovpsim_seq_item.gpr_wmask) begin + for (int i = 1; i < 32; i++) begin + if (rvvi_ovpsim_seq_item.gpr_wmask[i]) begin + rvvi_ovpsim_cntxt.state_vif.GPR_rtl[i] = rvvi_ovpsim_seq_item.get_gpr_wdata(i); + end + end + end // -------------------------------------------------------------------------------- // Step the ISS to get to the next instruction and wait for ISS to complete @@ -275,58 +284,62 @@ task uvma_rvvi_ovpsim_drv_c::restart_clknrst(); endtask : restart_clknrst -task uvma_rvvi_ovpsim_drv_c::stepi_haltreq(); - +task uvma_rvvi_ovpsim_drv_c::stepi_debug(bit nmi, bit intr, int unsigned nmi_cause, int unsigned intr_id); + rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b0; rvvi_ovpsim_cntxt.ovpsim_io_vif.haltreq = 1'b1; + if (nmi) begin + rvvi_ovpsim_cntxt.ovpsim_io_vif.nmi = 1'b1; + rvvi_ovpsim_cntxt.ovpsim_io_vif.nmi_cause = nmi_cause; + end + + if (intr) begin + rvvi_ovpsim_cntxt.ovpsim_io_vif.irq_i = 1 << (intr_id); + rvvi_ovpsim_cntxt.ovpsim_io_vif.intr = 1'b1; + end + rvvi_ovpsim_cntxt.control_vif.stepi(); @(rvvi_ovpsim_cntxt.state_vif.notify); - rvvi_ovpsim_cntxt.ovpsim_io_vif.haltreq = 1'b0; - @(posedge rvvi_ovpsim_cntxt.ovpsim_bus_vif.Clk); + rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b1; + rvvi_ovpsim_cntxt.ovpsim_io_vif.haltreq = 1'b0; + rvvi_ovpsim_cntxt.ovpsim_io_vif.intr = 1'b0; + + rvvi_ovpsim_cntxt.ovpsim_io_vif.nmi = 1'b0; -endtask : stepi_haltreq + @(posedge rvvi_ovpsim_cntxt.ovpsim_bus_vif.Clk); +endtask : stepi_debug task uvma_rvvi_ovpsim_drv_c::stepi_ext_intr(int unsigned intr_id); rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b0; rvvi_ovpsim_cntxt.ovpsim_io_vif.irq_i = 1 << (intr_id); + rvvi_ovpsim_cntxt.ovpsim_io_vif.intr = 1'b1; rvvi_ovpsim_cntxt.control_vif.stepi(); @(rvvi_ovpsim_cntxt.state_vif.notify); rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b1; + rvvi_ovpsim_cntxt.ovpsim_io_vif.intr = 1'b0; @(posedge rvvi_ovpsim_cntxt.ovpsim_bus_vif.Clk); endtask : stepi_ext_intr -task uvma_rvvi_ovpsim_drv_c::stepi_nmi_load_fault(); +task uvma_rvvi_ovpsim_drv_c::stepi_nmi(int unsigned cause); rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b0; - rvvi_ovpsim_cntxt.ovpsim_io_vif.LoadBusFaultNMI = 1'b1; + rvvi_ovpsim_cntxt.ovpsim_io_vif.nmi_cause = cause; + rvvi_ovpsim_cntxt.ovpsim_io_vif.nmi = 1'b1; rvvi_ovpsim_cntxt.control_vif.stepi(); @(rvvi_ovpsim_cntxt.state_vif.notify); rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b1; - rvvi_ovpsim_cntxt.ovpsim_io_vif.LoadBusFaultNMI = 1'b0; + rvvi_ovpsim_cntxt.ovpsim_io_vif.nmi = 1'b0; @(posedge rvvi_ovpsim_cntxt.ovpsim_bus_vif.Clk); -endtask : stepi_nmi_load_fault - -task uvma_rvvi_ovpsim_drv_c::stepi_nmi_store_fault(); - - rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b0; - rvvi_ovpsim_cntxt.ovpsim_io_vif.StoreBusFaultNMI = 1'b1; - - rvvi_ovpsim_cntxt.control_vif.stepi(); - @(rvvi_ovpsim_cntxt.state_vif.notify); - - rvvi_ovpsim_cntxt.ovpsim_io_vif.deferint = 1'b1; - rvvi_ovpsim_cntxt.ovpsim_io_vif.StoreBusFaultNMI = 1'b0; - @(posedge rvvi_ovpsim_cntxt.ovpsim_bus_vif.Clk); +endtask : stepi_nmi -endtask : stepi_nmi_store_fault task uvma_rvvi_ovpsim_drv_c::stepi_insn_bus_fault(); diff --git a/lib/uvm_agents/uvma_wfe_wu/cov/uvma_wfe_wu_cov_model.sv b/lib/uvm_agents/uvma_wfe_wu/cov/uvma_wfe_wu_cov_model.sv new file mode 100644 index 0000000000..4807651417 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/cov/uvma_wfe_wu_cov_model.sv @@ -0,0 +1,165 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_COV_MODEL_SV__ +`define __UVMA_WFE_WU_COV_MODEL_SV__ + + +/** + * Component encapsulating wfe wakeup functional coverage model. + */ +class uvma_wfe_wu_cov_model_c extends uvm_component; + + // Objects + uvma_wfe_wu_cfg_c cfg; + uvma_wfe_wu_cntxt_c cntxt; + uvma_wfe_wu_mon_trn_c mon_trn; + uvma_wfe_wu_seq_item_c seq_item; + + // TLM + uvm_tlm_analysis_fifo#(uvma_wfe_wu_mon_trn_c ) mon_trn_fifo; + uvm_tlm_analysis_fifo#(uvma_wfe_wu_seq_item_c) seq_item_fifo; + + + `uvm_component_utils_begin(uvma_wfe_wu_cov_model_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_cov_model", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null. + * 2. Builds fifos. + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Forks all sampling loops + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Describe uvma_wfe_wu_cov_model_c::sample_cfg() + */ + extern virtual function void sample_cfg(); + + /** + * Describe uvma_wfe_wu_cov_model_c::sample_cntxt() + */ + extern virtual function void sample_cntxt(); + + /** + * Describe uvma_wfe_wu_cov_model_c::sample_mon_trn() + */ + extern virtual function void sample_mon_trn(); + + /** + * Describe uvma_wfe_wu_cov_model_c::sample_seq_item() + */ + extern virtual function void sample_seq_item(); + +endclass : uvma_wfe_wu_cov_model_c + + +function uvma_wfe_wu_cov_model_c::new(string name="uvma_wfe_wu_cov_model", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_wfe_wu_cov_model_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_wfe_wu_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_wfe_wu_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + mon_trn_fifo = new("mon_trn_fifo" , this); + seq_item_fifo = new("seq_item_fifo", this); + +endfunction : build_phase + + +task uvma_wfe_wu_cov_model_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + if (cfg.enabled && cfg.cov_model_enabled) begin + fork + // Configuration + forever begin + cntxt.sample_cfg_e.wait_trigger(); + sample_cfg(); + end + + // Context + forever begin + cntxt.sample_cntxt_e.wait_trigger(); + sample_cntxt(); + end + + // Monitor transactions + forever begin + mon_trn_fifo.get(mon_trn); + sample_mon_trn(); + end + + // Sequence items + forever begin + seq_item_fifo.get(seq_item); + sample_seq_item(); + end + join_none + end + +endtask : run_phase + + +function void uvma_wfe_wu_cov_model_c::sample_cfg(); + +endfunction : sample_cfg + + +function void uvma_wfe_wu_cov_model_c::sample_cntxt(); + +endfunction : sample_cntxt + + +function void uvma_wfe_wu_cov_model_c::sample_mon_trn(); + +endfunction : sample_mon_trn + + +function void uvma_wfe_wu_cov_model_c::sample_seq_item(); + +endfunction : sample_seq_item + + +`endif // __UVMA_WFE_WU_COV_MODEL_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_base_seq.sv b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_base_seq.sv new file mode 100644 index 0000000000..83cdf451d1 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_base_seq.sv @@ -0,0 +1,50 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_BASE_SEQ_SV__ +`define __UVMA_WFE_WU_BASE_SEQ_SV__ + + +/** + * Abstract object from which all other wfe wakeup agent sequences must extend. + * Subclasses must be run on wfe wakeup sequencer (uvma_wfe_wu_sqr_c) instance. + */ +class uvma_wfe_wu_base_seq_c extends uvm_sequence#( + .REQ(uvma_wfe_wu_seq_item_c), + .RSP(uvma_wfe_wu_seq_item_c) +); + + `uvm_object_utils(uvma_wfe_wu_base_seq_c) + `uvm_declare_p_sequencer(uvma_wfe_wu_sqr_c) + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_base_seq"); + +endclass : uvma_wfe_wu_base_seq_c + + +function uvma_wfe_wu_base_seq_c::new(string name="uvma_wfe_wu_base_seq"); + + super.new(name); + +endfunction : new + + +`endif // __UVMA_WFE_WU_BASE_SEQ_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_item.sv b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_item.sv new file mode 100644 index 0000000000..eb100b9cd7 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_item.sv @@ -0,0 +1,56 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_SEQ_ITEM_SV__ +`define __UVMA_WFE_WU_SEQ_ITEM_SV__ + + +/** + * Object created by wfe wakeup agent sequences extending + * uvma_wfe_wu_seq_base_c. + */ +class uvma_wfe_wu_seq_item_c extends uvml_trn_seq_item_c; + + bit wfe_wu_req; + rand int unsigned active_cycles; + + rand uvma_wfe_wu_seq_item_action_e action ; ///< What operation to perform + + `uvm_object_utils_begin(uvma_wfe_wu_seq_item_c) + `uvm_field_enum(uvma_wfe_wu_seq_item_action_e, action , UVM_DEFAULT) + + `uvm_field_int(wfe_wu_req , UVM_DEFAULT) + `uvm_field_int(active_cycles, UVM_DEFAULT) + `uvm_object_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_seq_item"); + +endclass : uvma_wfe_wu_seq_item_c + + +function uvma_wfe_wu_seq_item_c::new(string name="uvma_wfe_wu_seq_item"); + + super.new(name); + +endfunction : new + + +`endif // __UVMA_WFE_WU_SEQ_ITEM_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_item_logger.sv b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_item_logger.sv new file mode 100644 index 0000000000..2849540431 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_item_logger.sv @@ -0,0 +1,96 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_SEQ_ITEM_LOGGER_SV__ +`define __UVMA_WFE_WU_SEQ_ITEM_LOGGER_SV__ + + +/** + * Component writing wfe wakeup sequence items debug data to disk as plain + * text. + */ +class uvma_wfe_wu_seq_item_logger_c extends uvml_logs_seq_item_logger_c#( + .T_TRN (uvma_wfe_wu_seq_item_c), + .T_CFG (uvma_wfe_wu_cfg_c ), + .T_CNTXT(uvma_wfe_wu_cntxt_c ) +); + + `uvm_component_utils(uvma_wfe_wu_seq_item_logger_c) + + + /** + * Default constructor. + */ + function new(string name="uvma_wfe_wu_seq_item_logger", uvm_component parent=null); + + super.new(name, parent); + + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_wfe_wu_seq_item_c t); + endfunction : write + + /** + * Writes log header to disk. + */ + virtual function void print_header(); + endfunction : print_header + +endclass : uvma_wfe_wu_seq_item_logger_c + + +/** + * Component writing Clock & Reset monitor transactions debug data to disk as + * JavaScript Object Notation (JSON). + */ +class uvma_wfe_wu_seq_item_logger_json_c extends uvma_wfe_wu_seq_item_logger_c; + + `uvm_component_utils(uvma_wfe_wu_seq_item_logger_json_c) + + + /** + * Set file extension to '.json'. + */ + function new(string name="uvma_wfe_wu_seq_item_logger_json", uvm_component parent=null); + + super.new(name, parent); + fextension = "json"; + + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_wfe_wu_seq_item_c t); + endfunction : write + + /** + * Empty function. + */ + virtual function void print_header(); + + // Do nothing: JSON files do not use headers. + + endfunction : print_header + +endclass : uvma_wfe_wu_seq_item_logger_json_c + + +`endif // __UVMA_WFE_WU_SEQ_ITEM_LOGGER_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_lib.sv b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_lib.sv new file mode 100644 index 0000000000..a9e9b965ee --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/seq/uvma_wfe_wu_seq_lib.sv @@ -0,0 +1,50 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_SEQ_LIB_SV__ +`define __UVMA_WFE_WU_SEQ_LIB_SV__ + + +/** + * Object holding sequence library for wfe wakeup agent. + */ +class uvma_wfe_wu_seq_lib_c extends uvm_sequence_library#( + .REQ(uvma_wfe_wu_seq_item_c), + .RSP(uvma_wfe_wu_seq_item_c) +); + + `uvm_object_utils (uvma_wfe_wu_seq_lib_c) + `uvm_sequence_library_utils(uvma_wfe_wu_seq_lib_c) + + + /** + * Initializes sequence library + */ + extern function new(string name="uvma_wfe_wu_seq_lib"); + +endclass : uvma_wfe_wu_seq_lib_c + + +function uvma_wfe_wu_seq_lib_c::new(string name="uvma_wfe_wu_seq_lib"); + + super.new(name); + init_sequence_library(); + +endfunction : new + + +`endif // __UVMA_WFE_WU_SEQ_LIB_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_agent.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_agent.sv new file mode 100644 index 0000000000..aa99f1fb49 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_agent.sv @@ -0,0 +1,232 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_AGENT_SV__ +`define __UVMA_WFE_WU_AGENT_SV__ + + +/** + * Top-level component that encapsulates, builds and connects all others. + * Capable of driving/monitoring wfe wakeup interface. + */ +class uvma_wfe_wu_agent_c extends uvm_agent; + + // Objects + uvma_wfe_wu_cfg_c cfg; + uvma_wfe_wu_cntxt_c cntxt; + + // Components + uvma_wfe_wu_drv_c driver; + uvma_wfe_wu_mon_c monitor; + uvma_wfe_wu_sqr_c sequencer; + uvma_wfe_wu_cov_model_c cov_model; + uvma_wfe_wu_seq_item_logger_c seq_item_logger; + uvma_wfe_wu_mon_trn_logger_c mon_trn_logger; + + // TLM + uvm_analysis_port#(uvma_wfe_wu_seq_item_c) drv_ap; + uvm_analysis_port#(uvma_wfe_wu_mon_trn_c ) mon_ap; + + + `uvm_component_utils_begin(uvma_wfe_wu_agent_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_agent", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null + * 2. Builds all components + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * 1. Links agent's analysis ports to sub-components' + * 2. Connects coverage models and loggers + */ + extern virtual function void connect_phase(uvm_phase phase); + + /** + * Uses uvm_config_db to retrieve cfg and hand out to sub-components. + */ + extern function void get_and_set_cfg(); + + /** + * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. + */ + extern function void get_and_set_cntxt(); + + /** + * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this + * agent. + */ + extern function void retrieve_vif(); + + /** + * Creates sub-components. + */ + extern function void create_components(); + + /** + * Connects sequencer and driver's TLM port(s). + */ + extern function void connect_sequencer_and_driver(); + + /** + * Connects agent's TLM ports to driver's and monitor's. + */ + extern function void connect_analysis_ports(); + + /** + * Connects coverage model to monitor and driver's analysis ports. + */ + extern function void connect_cov_model(); + + /** + * Connects transaction loggers to monitor and driver's analysis ports. + */ + extern function void connect_trn_loggers(); + +endclass : uvma_wfe_wu_agent_c + + +function uvma_wfe_wu_agent_c::new(string name="uvma_wfe_wu_agent", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_wfe_wu_agent_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + get_and_set_cfg (); + get_and_set_cntxt(); + retrieve_vif (); + create_components(); + +endfunction : build_phase + + +function void uvma_wfe_wu_agent_c::connect_phase(uvm_phase phase); + + super.connect_phase(phase); + + connect_sequencer_and_driver(); + connect_analysis_ports(); + + if (cfg.cov_model_enabled) begin + connect_cov_model(); + end + if (cfg.trn_log_enabled) begin + connect_trn_loggers(); + end + +endfunction: connect_phase + + +function void uvma_wfe_wu_agent_c::get_and_set_cfg(); + + void'(uvm_config_db#(uvma_wfe_wu_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + else begin + `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) + uvm_config_db#(uvma_wfe_wu_cfg_c)::set(this, "*", "cfg", cfg); + end + +endfunction : get_and_set_cfg + + +function void uvma_wfe_wu_agent_c::get_and_set_cntxt(); + + void'(uvm_config_db#(uvma_wfe_wu_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) + cntxt = uvma_wfe_wu_cntxt_c::type_id::create("cntxt"); + end + uvm_config_db#(uvma_wfe_wu_cntxt_c)::set(this, "*", "cntxt", cntxt); + +endfunction : get_and_set_cntxt + + +function void uvma_wfe_wu_agent_c::retrieve_vif(); + + if (!uvm_config_db#(virtual uvma_wfe_wu_if_t)::get(this, "", "vif", cntxt.vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(cntxt.vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", $typename(cntxt.vif)), UVM_DEBUG) + end + +endfunction : retrieve_vif + + +function void uvma_wfe_wu_agent_c::create_components(); + + monitor = uvma_wfe_wu_mon_c ::type_id::create("monitor" , this); + cov_model = uvma_wfe_wu_cov_model_c ::type_id::create("cov_model" , this); + mon_trn_logger = uvma_wfe_wu_mon_trn_logger_c ::type_id::create("mon_trn_logger" , this); + if (cfg.is_active == UVM_ACTIVE) begin + sequencer = uvma_wfe_wu_sqr_c ::type_id::create("sequencer" , this); + driver = uvma_wfe_wu_drv_c ::type_id::create("driver" , this); + seq_item_logger = uvma_wfe_wu_seq_item_logger_c::type_id::create("seq_item_logger", this); + end + +endfunction : create_components + + +function void uvma_wfe_wu_agent_c::connect_sequencer_and_driver(); + + sequencer.set_arbitration(cfg.sqr_arb_mode); + driver.seq_item_port.connect(sequencer.seq_item_export); + +endfunction : connect_sequencer_and_driver + + +function void uvma_wfe_wu_agent_c::connect_analysis_ports(); + + drv_ap = driver .ap; + mon_ap = monitor.ap; + +endfunction : connect_analysis_ports + + +function void uvma_wfe_wu_agent_c::connect_cov_model(); + + mon_ap.connect(cov_model.mon_trn_fifo .analysis_export); + drv_ap.connect(cov_model.seq_item_fifo.analysis_export); + +endfunction : connect_cov_model + + +function void uvma_wfe_wu_agent_c::connect_trn_loggers(); + + mon_ap.connect(mon_trn_logger .analysis_export); + drv_ap.connect(seq_item_logger.analysis_export); + +endfunction : connect_trn_loggers + + +`endif // __UVMA_WFE_WU_AGENT_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_cfg.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_cfg.sv new file mode 100644 index 0000000000..66d770dc78 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_cfg.sv @@ -0,0 +1,67 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_CFG_SV__ +`define __UVMA_WFE_WU_CFG_SV__ + + +/** + * Object encapsulating all parameters for creating, connecting and running all + * wfe wakeup agent (uvma_wfe_wu_agent_c) components. + */ +class uvma_wfe_wu_cfg_c extends uvm_object; + + // Common options + rand bit enabled; + rand uvm_active_passive_enum is_active; + rand uvm_sequencer_arb_mode sqr_arb_mode; + rand bit cov_model_enabled; + rand bit trn_log_enabled; + + `uvm_object_utils_begin(uvma_wfe_wu_cfg_c) + `uvm_field_int ( enabled , UVM_DEFAULT) + `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT) + `uvm_field_enum(uvm_sequencer_arb_mode , sqr_arb_mode , UVM_DEFAULT) + `uvm_field_int ( cov_model_enabled, UVM_DEFAULT) + `uvm_field_int ( trn_log_enabled , UVM_DEFAULT) + `uvm_object_utils_end + + + constraint defaults_cons { + soft enabled == 1; + soft is_active == UVM_PASSIVE; + soft sqr_arb_mode == UVM_SEQ_ARB_FIFO; + soft cov_model_enabled == 0; + soft trn_log_enabled == 1; + } + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_cfg"); + +endclass : uvma_wfe_wu_cfg_c + + +function uvma_wfe_wu_cfg_c::new(string name="uvma_wfe_wu_cfg"); + + super.new(name); + +endfunction : new + + +`endif // __UVMA_WFE_WU_CFG_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_cntxt.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_cntxt.sv new file mode 100644 index 0000000000..fc94769b77 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_cntxt.sv @@ -0,0 +1,72 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_CNTXT_SV__ +`define __UVMA_WFE_WU_CNTXT_SV__ + + +/** + * Object encapsulating all state variables for all wfe wakeup agent + * (uvma_wfe_wu_agent_c) components. + */ +class uvma_wfe_wu_cntxt_c extends uvm_object; + + // Handle to agent interface + virtual uvma_wfe_wu_if_t vif; + + // Events + uvm_event sample_cfg_e ; ///< Event to trigger functional coverage sampling of cfg + uvm_event sample_cntxt_e; ///< Event to trigger functional coverage sampling of cntxt + + + `uvm_object_utils_begin(uvma_wfe_wu_cntxt_c) + `uvm_field_event(sample_cfg_e , UVM_DEFAULT) + `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) + `uvm_object_utils_end + + + /** + * Builds events. + */ + extern function new(string name="uvma_wfe_wu_cntxt"); + + /** + * Resets integrals to their default values. + */ + extern function void reset(); + +endclass : uvma_wfe_wu_cntxt_c + + +function uvma_wfe_wu_cntxt_c::new(string name="uvma_wfe_wu_cntxt"); + + super.new(name); + + sample_cfg_e = new("sample_cfg_e" ); + sample_cntxt_e = new("sample_cntxt_e"); + + reset(); + +endfunction : new + + +function void uvma_wfe_wu_cntxt_c::reset(); + +endfunction : reset + + +`endif // __UVMA_WFE_WU_CNTXT_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_constants.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_constants.sv new file mode 100644 index 0000000000..f26b8b3c24 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_constants.sv @@ -0,0 +1,21 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_CONSTANTS_SV__ +`define __UVMA_WFE_WU_CONSTANTS_SV__ + +`endif // __UVMA_WFE_WU_CONSTANTS_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_drv.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_drv.sv new file mode 100644 index 0000000000..66b4544b6a --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_drv.sv @@ -0,0 +1,126 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_DRV_SV__ +`define __UVMA_WFE_WU_DRV_SV__ + + +/** + * Component driving a wfe wakeup virtual interface (uvma_wfe_wu_if_t). + */ +class uvma_wfe_wu_drv_c extends uvm_driver#( + .REQ(uvma_wfe_wu_seq_item_c), + .RSP(uvma_wfe_wu_seq_item_c) +); + + // Objects + uvma_wfe_wu_cfg_c cfg; + uvma_wfe_wu_cntxt_c cntxt; + + // TLM + uvm_analysis_port#(uvma_wfe_wu_seq_item_c) ap; + + + `uvm_component_utils_begin(uvma_wfe_wu_drv_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_drv", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null. + * 2. Builds ap. + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Obtains the reqs from the sequence item port and calls drv_req() + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Drives the virtual interface's (cntxt.vif) signals using req's contents. + */ + extern task drv_req(uvma_wfe_wu_seq_item_c req); + + +endclass : uvma_wfe_wu_drv_c + + +function uvma_wfe_wu_drv_c::new(string name="uvma_wfe_wu_drv", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_wfe_wu_drv_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_wfe_wu_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + uvm_config_db#(uvma_wfe_wu_cfg_c)::set(this, "*", "cfg", cfg); + + void'(uvm_config_db#(uvma_wfe_wu_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + uvm_config_db#(uvma_wfe_wu_cntxt_c)::set(this, "*", "cntxt", cntxt); + + ap = new("ap", this); + +endfunction : build_phase + + +task uvma_wfe_wu_drv_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + forever begin + seq_item_port.get_next_item(req); + `uvml_hrtbt() + drv_req(req); + ap.write(req); + seq_item_port.item_done(); + end + +endtask : run_phase + + +task uvma_wfe_wu_drv_c::drv_req(uvma_wfe_wu_seq_item_c req); + `uvm_info("WFE_WU", $sformatf("Driving:\n%s", req.sprint()), UVM_HIGH); + @(cntxt.vif.drv_cb); + case (req.action) + UVMA_WFE_WU_SEQ_ITEM_ACTION_ASSERT: begin + cntxt.vif.drv_cb.wfe_wu <= 1'b1; + end + UVMA_WFE_WU_SEQ_ITEM_ACTION_DEASSERT: begin + cntxt.vif.drv_cb.wfe_wu <= 1'b0; + end + endcase + +endtask : drv_req + +`endif // __UVMA_WFE_WU_DRV_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_if.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_if.sv new file mode 100644 index 0000000000..91d17ee92c --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_if.sv @@ -0,0 +1,70 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_IF_SV__ +`define __UVMA_WFE_WU_IF_SV__ + + +/** + * Encapsulates all signals of the wfe wakeup interface. Used by monitor + * (uvma_wfe_wu_mon_c) and driver (uvma_wfe_wu_drv_c). + */ +interface uvma_wfe_wu_if_t (); + + import uvm_pkg::*; + + // Signals + logic clk; + logic reset_n; + + bit is_active; + bit wfe_wu; + + `ifndef FORMAL + initial begin + is_active = 1'b0; + wfe_wu = 1'b0; + end + `endif + /** + * Used by target DUT. + */ + clocking dut_cb @(posedge clk or reset_n); + endclocking : dut_cb + + /** + * Used by uvma_wfe_wu_drv_c. + */ + clocking drv_cb @(posedge clk or reset_n); + output wfe_wu; + endclocking : drv_cb + + /** + * Used by uvma_wfe_wu_mon_c. + */ + clocking mon_cb @(posedge clk or reset_n); + input #1step wfe_wu; + endclocking : mon_cb + + modport dut_mp (clocking dut_cb); + modport active_mp (clocking drv_cb); + modport passive_mp(clocking mon_cb); + +endinterface : uvma_wfe_wu_if_t + + +`endif // __UVMA_WFE_WU_IF_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_if_chk.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_if_chk.sv new file mode 100644 index 0000000000..5f6ce05421 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_if_chk.sv @@ -0,0 +1,32 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_IF_CHK_SV__ +`define __UVMA_WFE_WU_IF_CHK_SV__ + + +/** + * Encapsulates assertions targeting uvma_wfe_wu_if. + */ +module uvma_wfe_wu_if_chk( + uvma_wfe_wu_if_t wfe_wu_if +); + +endmodule : uvma_wfe_wu_if_chk + + +`endif // __UVMA_WFE_WU_IF_CHK_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_macros.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_macros.sv new file mode 100644 index 0000000000..5de4a643f1 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_macros.sv @@ -0,0 +1,25 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_MACROS_SV__ +`define __UVMA_WFE_WU_MACROS_SV__ + + + + + +`endif // __UVMA_WFE_WU_MACROS_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon.sv new file mode 100644 index 0000000000..6bde2dc51c --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon.sv @@ -0,0 +1,133 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_MON_SV__ +`define __UVMA_WFE_WU_MON_SV__ + + +/** + * Component sampling transactions from a wfe wakeup virtual interface + * (uvma_wfe_wu_if_t). + */ +class uvma_wfe_wu_mon_c extends uvm_monitor; + + // Objects + uvma_wfe_wu_cfg_c cfg; + uvma_wfe_wu_cntxt_c cntxt; + + // TLM + uvm_analysis_port#(uvma_wfe_wu_mon_trn_c) ap; + + + `uvm_component_utils_begin(uvma_wfe_wu_mon_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_mon", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null. + * 2. Builds ap. + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Oversees monitoring + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Empty, classes extending this monitor can do their intercept here. + */ + extern function void process_trn(ref uvma_wfe_wu_mon_trn_c trn); + + extern virtual task sample_trn(output uvma_wfe_wu_mon_trn_c trn); + +endclass : uvma_wfe_wu_mon_c + + +function uvma_wfe_wu_mon_c::new(string name="uvma_wfe_wu_mon", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_wfe_wu_mon_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_wfe_wu_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_wfe_wu_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + ap = new("ap", this); + +endfunction : build_phase + + +task uvma_wfe_wu_mon_c::run_phase(uvm_phase phase); + + uvma_wfe_wu_mon_trn_c trn; + + super.run_phase(phase); + + if (cfg.enabled) begin + fork + begin : clk + forever begin + sample_trn(trn); + process_trn(trn); + ap.write (trn); + `uvml_hrtbt() + end + end + + join_none + end + +endtask : run_phase + +task uvma_wfe_wu_mon_c::sample_trn(output uvma_wfe_wu_mon_trn_c trn); + bit sampled_trn = 0; + + trn = uvma_wfe_wu_mon_trn_c::type_id::create("trn"); + + do begin + @(cntxt.vif.mon_cb); + // TODO sample trn from vif + end while (!sampled_trn); +endtask : sample_trn + +function void uvma_wfe_wu_mon_c::process_trn(ref uvma_wfe_wu_mon_trn_c trn); + + // Empty + +endfunction : process_trn + +`endif // __UVMA_WFE_WU_MON_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon_trn.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon_trn.sv new file mode 100644 index 0000000000..905b9007f2 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon_trn.sv @@ -0,0 +1,48 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_MON_TRN_SV__ +`define __UVMA_WFE_WU_MON_TRN_SV__ + + +/** + * Object rebuilt from the wfe wakeup monitor. Analog of + * uvma_wfe_wu_seq_item_c. + */ +class uvma_wfe_wu_mon_trn_c extends uvml_trn_mon_trn_c; + + + `uvm_object_utils_begin(uvma_wfe_wu_mon_trn_c) + `uvm_object_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_mon_trn"); + +endclass : uvma_wfe_wu_mon_trn_c + + +function uvma_wfe_wu_mon_trn_c::new(string name="uvma_wfe_wu_mon_trn"); + + super.new(name); + +endfunction : new + + +`endif // __UVMA_WFE_WU_MON_TRN_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon_trn_logger.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon_trn_logger.sv new file mode 100644 index 0000000000..5c2d67c6c4 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_mon_trn_logger.sv @@ -0,0 +1,96 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_MON_TRN_LOGGER_SV__ +`define __UVMA_WFE_WU_MON_TRN_LOGGER_SV__ + + +/** + * Component writing wfe wakeup monitor transactions debug data to disk as + * plain text. + */ +class uvma_wfe_wu_mon_trn_logger_c extends uvml_logs_mon_trn_logger_c#( + .T_TRN (uvma_wfe_wu_mon_trn_c), + .T_CFG (uvma_wfe_wu_cfg_c ), + .T_CNTXT(uvma_wfe_wu_cntxt_c ) +); + + `uvm_component_utils(uvma_wfe_wu_mon_trn_logger_c) + + + /** + * Default constructor. + */ + function new(string name="uvma_wfe_wu_mon_trn_logger", uvm_component parent=null); + + super.new(name, parent); + + endfunction : new + + /** + * Writes contents of t to disk + */ + virtual function void write(uvma_wfe_wu_mon_trn_c t); + endfunction : write + + /** + * Writes log header to disk + */ + virtual function void print_header(); + endfunction : print_header + +endclass : uvma_wfe_wu_mon_trn_logger_c + + +/** + * Component writing WFE_WU monitor transactions debug data to disk as + * JavaScript Object Notation (JSON). + */ +class uvma_wfe_wu_mon_trn_logger_json_c extends uvma_wfe_wu_mon_trn_logger_c; + + `uvm_component_utils(uvma_wfe_wu_mon_trn_logger_json_c) + + + /** + * Set file extension to '.json'. + */ + function new(string name="uvma_wfe_wu_mon_trn_logger_json", uvm_component parent=null); + + super.new(name, parent); + fextension = "json"; + + endfunction : new + + /** + * Writes contents of t to disk. + */ + virtual function void write(uvma_wfe_wu_mon_trn_c t); + endfunction : write + + /** + * Empty function. + */ + virtual function void print_header(); + + // Do nothing: JSON files do not use headers. + + endfunction : print_header + +endclass : uvma_wfe_wu_mon_trn_logger_json_c + + +`endif // __UVMA_WFE_WU_MON_TRN_LOGGER_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_pkg.flist b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_pkg.flist new file mode 100644 index 0000000000..dc802e024f --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_pkg.flist @@ -0,0 +1,24 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +// Directories ++incdir+${DV_UVMA_WFE_WU_PATH} ++incdir+${DV_UVMA_WFE_WU_PATH}/cov ++incdir+${DV_UVMA_WFE_WU_PATH}/seq + +// Files +${DV_UVMA_WFE_WU_PATH}/uvma_wfe_wu_pkg.sv diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_pkg.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_pkg.sv new file mode 100644 index 0000000000..882723e024 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_pkg.sv @@ -0,0 +1,74 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_PKG_SV__ +`define __UVMA_WFE_WU_PKG_SV__ + + +// Pre-processor macros +`include "uvm_macros.svh" +`include "uvml_hrtbt_macros.sv" +`include "uvma_wfe_wu_macros.sv" + +// Interface(s) / Module(s) / Checker(s) +`include "uvma_wfe_wu_if.sv" +`ifdef UVMA_WFE_WU_INC_IF_CHK +`include "uvma_wfe_wu_if_chk.sv" +`endif + + +/** + * Encapsulates all the types needed for an UVM agent capable of driving and/or + * monitoring wfe wakeup. + */ +package uvma_wfe_wu_pkg; + + import uvm_pkg ::*; + import uvml_hrtbt_pkg::*; + import uvml_trn_pkg ::*; + import uvml_logs_pkg ::*; + + // Constants / Structs / Enums + `include "uvma_wfe_wu_constants.sv" + `include "uvma_wfe_wu_tdefs.sv" + + // Objects + `include "uvma_wfe_wu_cfg.sv" + `include "uvma_wfe_wu_cntxt.sv" + + // High-level transactions + `include "uvma_wfe_wu_mon_trn.sv" + `include "uvma_wfe_wu_mon_trn_logger.sv" + `include "uvma_wfe_wu_seq_item.sv" + `include "uvma_wfe_wu_seq_item_logger.sv" + + // Agent components + `include "uvma_wfe_wu_cov_model.sv" + `include "uvma_wfe_wu_drv.sv" + `include "uvma_wfe_wu_mon.sv" + `include "uvma_wfe_wu_sqr.sv" + `include "uvma_wfe_wu_agent.sv" + + // Sequences + `include "uvma_wfe_wu_base_seq.sv" + `include "uvma_wfe_wu_seq_lib.sv" + +endpackage : uvma_wfe_wu_pkg + + +`endif // __UVMA_WFE_WU_PKG_SV__ + diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_sqr.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_sqr.sv new file mode 100644 index 0000000000..bdab535eaa --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_sqr.sv @@ -0,0 +1,79 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_SQR_SV__ +`define __UVMA_WFE_WU_SQR_SV__ + + +/** + * Component running wfe wakeup sequences extending uvma_wfe_wu_seq_base_c. + * Provides sequence items for uvma_wfe_wu_drv_c. + */ +class uvma_wfe_wu_sqr_c extends uvm_sequencer#( + .REQ(uvma_wfe_wu_seq_item_c), + .RSP(uvma_wfe_wu_seq_item_c) +); + + // Objects + uvma_wfe_wu_cfg_c cfg; + uvma_wfe_wu_cntxt_c cntxt; + + + `uvm_component_utils_begin(uvma_wfe_wu_sqr_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvma_wfe_wu_sqr", uvm_component parent=null); + + /** + * Ensures cfg & cntxt handles are not null + */ + extern virtual function void build_phase(uvm_phase phase); + +endclass : uvma_wfe_wu_sqr_c + + +function uvma_wfe_wu_sqr_c::new(string name="uvma_wfe_wu_sqr", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvma_wfe_wu_sqr_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvma_wfe_wu_cfg_c)::get(this, "", "cfg", cfg)); + if (cfg == null) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvma_wfe_wu_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (cntxt == null) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + +endfunction : build_phase + + +`endif // __UVMA_WFE_WU_SQR_SV__ diff --git a/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_tdefs.sv b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_tdefs.sv new file mode 100644 index 0000000000..a7ef0edac2 --- /dev/null +++ b/lib/uvm_agents/uvma_wfe_wu/uvma_wfe_wu_tdefs.sv @@ -0,0 +1,26 @@ +// +// Copyright 2023 Silicon Labs Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_WFE_WU_TDEFS_SV__ +`define __UVMA_WFE_WU_TDEFS_SV__ + +typedef enum { + UVMA_WFE_WU_SEQ_ITEM_ACTION_ASSERT, + UVMA_WFE_WU_SEQ_ITEM_ACTION_DEASSERT +} uvma_wfe_wu_seq_item_action_e; + +`endif // __UVMA_WFE_WU_TDEFS_SV__ diff --git a/mk/Common.mk b/mk/Common.mk index 14cc99b350..7ad0f25682 100644 --- a/mk/Common.mk +++ b/mk/Common.mk @@ -182,7 +182,7 @@ endif # SVLIB repo var end ############################################################################### -# Imperas Instruction Set Simulator +# Imperas OVPsim Instruction Set Simulator DV_OVPM_HOME = $(CORE_V_VERIF)/vendor_lib/imperas DV_OVPM_MODEL = $(DV_OVPM_HOME)/imperas_DV_COREV @@ -190,6 +190,10 @@ DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design OVP_MODEL_DPI = $(DV_OVPM_MODEL)/bin/Linux64/imperas_CV32.dpi.so #OVP_CTRL_FILE = $(DV_OVPM_DESIGN)/riscv_CV32E40P.ic +############################################################################### +# Imperas OVPsim Instruction Set Simulator +IMPERAS_DV_MODEL = $(IMPERAS_HOME)/lib/$(IMPERAS_ARCH)/ImperasLib/imperas.com/verification/riscv/1.0/model.so + ############################################################################### # Run the yaml2make scripts @@ -228,10 +232,14 @@ endif ############################################################################### # cfg CFGYAML2MAKE = $(CORE_V_VERIF)/bin/cfgyaml2make -CFG_YAML_PARSE_TARGETS=comp ldgen comp_corev-dv gen_corev-dv test hex clean_hex corev-dv sanity-veri-run bsp +CFG_YAML_PARSE_TARGETS=comp ldgen comp_corev-dv gen_corev-dv test hex clean_hex corev-dv sanity-veri-run bsp compliance ifneq ($(filter $(CFG_YAML_PARSE_TARGETS),$(MAKECMDGOALS)),) ifneq ($(CFG),) +ifneq ($(CFG_PATH_OVERRIDE),) +CFG_FLAGS_MAKE := $(shell $(CFGYAML2MAKE) --yaml=$(abspath $(CFG_PATH_OVERRIDE))/$(CFG).yaml $(YAML2MAKE_DEBUG) --prefix=CFG --core=$(CV_CORE)) +else CFG_FLAGS_MAKE := $(shell $(CFGYAML2MAKE) --yaml=$(CFG).yaml $(YAML2MAKE_DEBUG) --prefix=CFG --core=$(CV_CORE)) +endif ifeq ($(CFG_FLAGS_MAKE),) $(error ERROR Error finding or parsing configuration: $(CFG).yaml) endif diff --git a/mk/README.md b/mk/README.md index a5a1081a85..391f037e87 100644 --- a/mk/README.md +++ b/mk/README.md @@ -295,31 +295,31 @@ file against a reference signature. As with riscv-dv, the compliance test-suite is cloned by the Makefiles to `$(CV_CORE)/vendor_lib/riscv` as needed. The form of the target to run a single test-program from the compliance test suite is as follows: ``` -make compliance RISCV_ISA= COMPLIANCE_PROG= +make compliance RISCV_DEVICE= COMPLIANCE_PROG= ``` To have the signature dumped and checked: ``` -make compliance_check_sig RISCV_ISA= COMPLIANCE_PROG= +make compliance_check_sig RISCV_DEVICE= COMPLIANCE_PROG= ``` Note that running either of these targets will invoke the `all_compliance` target which clones riscv-compliance and compiles all the test-programs. Below is an example of running a specific test-program from the suite: ``` -make compliance RISCV_ISA=rv32Zifencei COMPLIANCE_PROG=I-FENCE.I-01 +make compliance RISCV_DEVICE=Zifencei COMPLIANCE_PROG=fence ``` -**Note:** There is a dependancy between RISCV_ISA and COMPLIANCE_PROG. For example, because the I-ADD-01 test-program is part of the rv32i testsuite this works: +**Note:** There is a dependancy between RISCV_DEVICE and COMPLIANCE_PROG. For example, because the add-01 test-program is part of the rv32i testsuite this works: ``` -make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ADD-01 +make compliance RISCV_DEVICE=I COMPLIANCE_PROG=add-01 ``` But this does not: ``` -make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=I-ADD-01 +make compliance RISCV_ISA=C COMPLIANCE_PROG=add-01 ``` The `compliance_check_sig` target can be used in the same way as above to run the simulation plus perform a post-simulation check of the signature file and the reference signature provided as part of the compliance test-suite.

Per-extension compliance regressions can be run using the `compliance_regression` target. For example: ``` -make compliance_regression RISCV_ISA=rv32imc +make compliance_regression RISCV_DEVICE=C ``` will run all compressed instruction tests in the compliance test-suite, diff the signature files and produce a summary report. Note that four of the test-programs in the rv32i compliance suite are deliberately ignored. See [issue #412](https://github.com/openhwgroup/core-v-verif/issues/412). diff --git a/mk/fv/fv.mk b/mk/fv/fv.mk new file mode 100644 index 0000000000..71c720bd60 --- /dev/null +++ b/mk/fv/fv.mk @@ -0,0 +1,42 @@ +# Copyright 2022 Silicon Labs, Inc. +# Copyright 2022 OpenHW Group +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may +# not use this file except in compliance with the License, or, at your option, +# the Apache License version 2.0. +# +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. + + +default_target: + @echo error: specify a make target + + +export CV_CORE_PKG ?= $(CORE_V_VERIF)/core-v-cores/$(CV_CORE) + +export DV_ISA_DECODER_PATH ?= $(CORE_V_VERIF)/lib/isa_decoder +export DV_SUPPORT_PATH ?= $(CORE_V_VERIF)/lib/support +export DV_UVM_TESTCASE_PATH ?= $(CORE_V_VERIF)/$(CV_CORE)/tests/uvmt +export DV_UVMA_PATH ?= $(CORE_V_VERIF)/lib/uvm_agents +export DV_UVME_PATH ?= $(CORE_V_VERIF)/$(CV_CORE)/env/uvme +export DV_UVMT_PATH ?= $(CORE_V_VERIF)/$(CV_CORE)/tb/uvmt + +export DESIGN_RTL_DIR ?= $(CV_CORE_PKG)/rtl + + +include $(CORE_V_VERIF)/mk/Common.mk + + +$(CV_CORE_PKG): + $(CLONE_CV_CORE_CMD) diff --git a/mk/uvmt/dsim.mk b/mk/uvmt/dsim.mk index 9470f443f0..b678261118 100644 --- a/mk/uvmt/dsim.mk +++ b/mk/uvmt/dsim.mk @@ -35,10 +35,14 @@ DSIM_CODE_COV_SCOPE ?= $(MAKE_PATH)/../tools/dsim/ccov_scopes.txt DSIM_USE_ISS ?= YES DSIM_FILE_LIST ?= -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist -DSIM_FILE_LIST += -f $(DV_UVMT_PATH)/imperas_iss.flist -DSIM_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION +DSIM_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION+UVM + +ifeq ($(CV_CORE_UC),CV32E40S) +DSIM_USER_COMPILE_ARGS = -no-sva +else +DSIM_USER_COMPILE_ARGS = +endif -DSIM_USER_COMPILE_ARGS ?= ifeq ($(USE_ISS),YES) DSIM_RUN_FLAGS += +USE_ISS else @@ -57,7 +61,7 @@ endif DSIM_PMA_INC += +incdir+$(TBSRC_HOME)/uvmt \ +incdir+$(CV_CORE_PKG)/rtl/include \ +incdir+$(CV_CORE_COREVDV_PKG)/ldgen \ - +incdir+$(abspath $(MAKE_PATH)/../../../lib/mem_region_gen) + +incdir+$(abspath $(MAKE_PATH)/../../../lib/mem_region_gen) # Seed management for constrained-random sims. This is an intentional repeat # of the root Makefile: dsim regressions use random seeds by default. @@ -146,10 +150,8 @@ comp: mk_results $(CV_CORE_PKG) $(SVLIB_PKG) $(OVP_MODEL_DPI) +$(UVM_PLUSARGS) \ -genimage $(DSIM_IMAGE) - -################################################################################ -# General test execution target "test" -# +# TODO: discuss location of ImperasDV with Imperas. +# +incdir+$(CORE_V_VERIF)/vendor_lib/ImperasDV/ImpPublic/include/host \ ################################################################################ # If the configuration specified OVPSIM arguments, generate an ovpsim.ic file and @@ -160,9 +162,65 @@ gen_ovpsim_ic: @touch $(SIM_RUN_RESULTS)/ovpsim.ic @if [ ! -z "$(CFG_OVPSIM)" ]; then \ echo "$(CFG_OVPSIM)" > $(SIM_RUN_RESULTS)/ovpsim.ic; \ + else \ + echo "--override cpu/misa_Extensions=0x001106" > $(SIM_RUN_RESULTS)/ovpsim.ic; \ fi export IMPERAS_TOOLS=$(SIM_RUN_RESULTS)/ovpsim.ic +# @rm -f $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @mkdir -p $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX); +# @touch -f $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/misa_Extensions=0x001106 " > $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/tcontrol_undefined=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/bitmanip_version=1.0.0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zba=1 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbb=1 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbc=1 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbe=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbf=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbm=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbp=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbr=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbs=1 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/Zbt=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/priv_version=master " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/endianFixed=1 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/mhartid=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/mimpid=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/startaddress=0x00000080 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/mtvec=0x00000001 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/nmi_address=0x00100000 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/debug_address=0x1a110800 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/dexc_address=0x1a111000 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/noinhibit_mask=0xfffffff0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# @echo "--override cpu/extension_*/PMA_NUM_REGIONS=0 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# +# # required for basic arithmetic test +# #@echo "--override cpu/mtvec_mask=0xffffff01 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# #@echo "--override cpu/mtvec=0x00000001 " >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# +# #@echo "--trace --tracechange --tracemode --traceshowicount --monitornetschange" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic +# +# @if [ ! -z "$(CFG_OVPSIM)" ]; then \ +# echo "$(CFG_OVPSIM)" > $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic; \ +# fi +#export IMPERAS_TOOLS=ovpsim.ic + +# @rm -f $(SIM_RUN_RESULTS)/ovpsim.ic +# @mkdir -p $(SIM_RUN_RESULTS) +# @touch $(SIM_RUN_RESULTS)/ovpsim.ic +# @if [ ! -z "$(CFG_OVPSIM)" ]; then \ +# echo "$(CFG_OVPSIM)" > $(SIM_RUN_RESULTS)/ovpsim.ic; \ +# else \ +# echo "--override cpu/misa_Extensions=0x001106" > $(SIM_RUN_RESULTS)/ovpsim.ic; \ +# fi +#export IMPERAS_TOOLS=$(SIM_RUN_RESULTS)/ovpsim.ic + + +################################################################################ +# General test execution target "test" +# + # Skip compile if COMP is specified and negative ifneq ($(call IS_NO,$(COMP)),NO) DSIM_SIM_PREREQ = comp @@ -183,6 +241,7 @@ test: $(DSIM_SIM_PREREQ) hex gen_ovpsim_ic -sv_lib $(DPI_DASM_LIB) \ -sv_lib $(abspath $(SVLIB_LIB)) \ -sv_lib $(OVP_MODEL_DPI) \ + -sv_lib $(IMPERAS_DV_MODEL) \ +UVM_TESTNAME=$(TEST_UVM_TEST) \ +firmware=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).hex \ +elf_file=$(SIM_TEST_PROGRAM_RESULTS)/$(TEST_PROGRAM)$(OPT_RUN_INDEX_SUFFIX).elf \ @@ -196,6 +255,7 @@ asm: comp $(ASM_DIR)/$(ASM_PROG).hex $(ASM_DIR)/$(ASM_PROG).elf -sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so \ -sv_lib $(DPI_DASM_LIB) \ -sv_lib $(OVP_MODEL_DPI) \ + -sv_lib $(IMPERAS_DV_MODEL) \ +UVM_TESTNAME=$(UVM_TESTNAME) \ +firmware=$(ASM_DIR)/$(ASM_PROG).hex \ +elf_file=$(ASM_DIR)/$(ASM_PROG).elf @@ -230,6 +290,7 @@ compliance: comp build_compliance -sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so \ -sv_lib $(DPI_DASM_LIB) \ -sv_lib $(OVP_MODEL_DPI) \ + -sv_lib $(IMPERAS_DV_MODEL) \ +UVM_TESTNAME=$(UVM_TESTNAME) \ +firmware=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(COMPLIANCE_PROG).hex \ +elf_file=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(COMPLIANCE_PROG).elf @@ -248,6 +309,7 @@ no-test-program: comp -sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so \ -sv_lib $(DPI_DASM_LIB) \ -sv_lib $(OVP_MODEL_DPI) \ + -sv_lib $(IMPERAS_DV_MODEL) \ +UVM_TESTNAME=$(UVM_TESTNAME) ################################################################################ @@ -262,6 +324,7 @@ dsim-firmware-unit-test: comp -sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so \ -sv_lib $(DPI_DASM_LIB) \ -sv_lib $(OVP_MODEL_DPI) \ + -sv_lib $(IMPERAS_DV_MODEL) \ +UVM_TESTNAME=uvmt_$(CV_CORE_LC)_firmware_test_c \ +firmware=$(FIRMWARE)/firmware_unit_test.hex \ +elf_file=$(FIRMWARE)/firmware_unit_test.elf diff --git a/mk/uvmt/uvmt.mk b/mk/uvmt/uvmt.mk index 4586d124a5..13c71fd134 100644 --- a/mk/uvmt/uvmt.mk +++ b/mk/uvmt/uvmt.mk @@ -85,7 +85,7 @@ export RUN_INDEX ?= 0 SIM_RESULTS ?= $(if $(CV_RESULTS),$(abspath $(CV_RESULTS))/$(SIMULATOR)_results,$(MAKE_PATH)/$(SIMULATOR)_results) SIM_CFG_RESULTS = $(SIM_RESULTS)/$(CFG) SIM_COREVDV_RESULTS = $(SIM_CFG_RESULTS)/corev-dv -SIM_LDGEN_RESULTS = $(SIM_CFG_RESULTS)/$(LDGEN) +SIM_LDGEN_RESULTS = $(if $(LDGEN),$(SIM_CFG_RESULTS)/$(LDGEN),$(SIM_CFG_RESULTS)) SIM_TEST_RESULTS = $(SIM_CFG_RESULTS)/$(TEST) SIM_RUN_RESULTS = $(SIM_TEST_RESULTS)/$(RUN_INDEX) SIM_TEST_PROGRAM_RESULTS = $(SIM_RUN_RESULTS)/test_program @@ -102,32 +102,34 @@ EMB_DEBUG_ARG = $(if $(filter $(YES_VALS),$(EMB_DEBUG)),YES,NO) # UVM Environment export DV_UVMT_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/tb/uvmt +export DV_UVM_TESTCASE_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/uvmt export DV_UVME_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/env/uvme export DV_UVML_HRTBT_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_hrtbt export DV_UVMA_CORE_CNTRL_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_core_cntrl export DV_UVMA_ISACOV_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_isacov export DV_UVMA_RVFI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_rvfi -export DV_UVMA_RVVI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_rvvi -export DV_UVMA_RVVI_OVPSIM_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_rvvi_ovpsim export DV_UVMA_CLKNRST_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_clknrst export DV_UVMA_INTERRUPT_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_interrupt +export DV_UVMA_CLIC_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_clic export DV_UVMA_DEBUG_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_debug export DV_UVMA_PMA_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_pma export DV_UVMA_OBI_MEMORY_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_obi_memory export DV_UVMA_FENCEI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_fencei +export DV_UVMA_WFE_WU_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_wfe_wu export DV_UVML_TRN_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_trn export DV_UVML_LOGS_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_logs export DV_UVML_SB_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_sb export DV_UVML_MEM_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_mem +export DV_SUPPORT_PATH = $(CORE_V_VERIF)/lib/support +export DV_ISA_DECODER_PATH = $(CORE_V_VERIF)/lib/isa_decoder -export DV_OVPM_HOME = $(CORE_V_VERIF)/vendor_lib/imperas -export DV_OVPM_MODEL = $(DV_OVPM_HOME)/imperas_DV_COREV - -export DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design +# ImperasDV +export IMPERAS_DV_HOME = $(CORE_V_VERIF)/vendor_lib/ImperasDV +# Verilab SVlib export DV_SVLIB_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/verilab -DV_UVMT_SRCS = $(wildcard $(DV_UVMT_PATH)/*.sv)) +DV_UVMT_SRCS = $(wildcard $(DV_UVMT_PATH)/*.sv)) # Testcase name: must be the CLASS name of the testcase (not the filename). # Look in ../../tests/uvmt @@ -239,9 +241,14 @@ $(SVLIB_PKG): # target to run the compiled test-program. # RISCV_ISA='rv32i|rv32im|rv32imc|rv32Zicsr|rv32Zifencei' -RISCV_ISA ?= rv32i -RISCV_TARGET ?= OpenHW -RISCV_DEVICE ?= $(CV_CORE_LC) +RISCV_ISA ?= rv32i_m +RISCV_TARGET ?= $(CV_CORE_LC) +RISCV_DEVICE ?= I +ifneq ($(RISCV_TARGET),cv32e40p) + COMPLIANCE_BITMANIP=make build_compliance RISCV_DEVICE=Bitmanip +else + COMPLIANCE_BITMANIP=echo "Bitmanip not supported, skipping" +endif clone_compliance: $(CLONE_COMPLIANCE_CMD) @@ -260,11 +267,12 @@ build_compliance: $(COMPLIANCE_PKG) # VERBOSE=1 all_compliance: $(COMPLIANCE_PKG) - make build_compliance RISCV_ISA=rv32i && \ - make build_compliance RISCV_ISA=rv32im && \ - make build_compliance RISCV_ISA=rv32imc && \ - make build_compliance RISCV_ISA=rv32Zicsr && \ - make build_compliance RISCV_ISA=rv32Zifencei + make build_compliance RISCV_DEVICE=I && \ + make build_compliance RISCV_DEVICE=M && \ + make build_compliance RISCV_DEVICE=C && \ + make build_compliance RISCV_DEVICE=Zifencei && \ + make build_compliance RISCV_DEVICE=privilege && \ + $(COMPLIANCE_BITMANIP) # "compliance" is a simulator-specific target defined in .mk COMPLIANCE_RESULTS = $(SIM_RESULTS) @@ -273,7 +281,7 @@ compliance_check_sig: compliance @echo "Checking Compliance Signature for $(RISCV_ISA)/$(COMPLIANCE_PROG)" @echo "Reference: $(REF)" @echo "Signature: $(SIG)" - @export SUITEDIR=$(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/riscv/riscv-compliance/riscv-test-suite/$(RISCV_ISA) && \ + @export SUITEDIR=$(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/riscv/riscv-compliance/riscv-test-suite/$(RISCV_ISA)/$(RISCV_DEVICE) && \ export REF=$(REF) && export SIG=$(SIG) && export COMPL_PROG=$(COMPLIANCE_PROG) && \ export RISCV_TARGET=${RISCV_TARGET} && export RISCV_DEVICE=${RISCV_DEVICE} && \ export RISCV_ISA=${RISCV_ISA} export SIG_ROOT=${SIG_ROOT} && \ @@ -282,15 +290,15 @@ compliance_check_sig: compliance compliance_check_all_sigs: @$(MKDIR_P) $(COMPLIANCE_RESULTS)/$(CFG)/$(RISCV_ISA) @echo "Checking Compliance Signature for all tests in $(CFG)/$(RISCV_ISA)" - @export SUITEDIR=$(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/riscv/riscv-compliance/riscv-test-suite/$(RISCV_ISA) && \ + export SUITEDIR=$(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/riscv/riscv-compliance/riscv-test-suite/$(RISCV_ISA)/$(RISCV_DEVICE) && \ export RISCV_TARGET=${RISCV_TARGET} && export RISCV_DEVICE=${RISCV_DEVICE} && \ export RISCV_ISA=${RISCV_ISA} export SIG_ROOT=${SIG_ROOT} && \ $(CORE_V_VERIF)/bin/diff_signatures.sh $(RISCV_ISA) | tee $(COMPLIANCE_RESULTS)/$(CFG)/$(RISCV_ISA)/diff_signatures.log compliance_regression: - make build_compliance RISCV_ISA=$(RISCV_ISA) + make build_compliance RISCV_ISA=$(RISCV_ISA) RISCV_DEVICE=$(RISCV_DEVICE) @export SIM_DIR=$(CORE_V_VERIF)/$(CV_CORE_LC)/sim/uvmt && \ - $(CORE_V_VERIF)/bin/run_compliance.sh $(RISCV_ISA) + $(CORE_V_VERIF)/bin/run_compliance.sh $(RISCV_DEVICE) make compliance_check_all_sigs RISCV_ISA=$(RISCV_ISA) dah: diff --git a/mk/uvmt/vsim.mk b/mk/uvmt/vsim.mk index b77e7d3d34..8adf3812ab 100644 --- a/mk/uvmt/vsim.mk +++ b/mk/uvmt/vsim.mk @@ -126,7 +126,7 @@ VLOG_FILE_LIST = -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist VLOG_FLAGS += $(DPILIB_VLOG_OPT) # Add the ISS to compilation -VLOG_FILE_LIST += -f $(DV_UVMT_PATH)/imperas_iss.flist +VLOG_FILE_LIST += -f $(DV_UVMT_PATH)/imperas_dv.flist VLOG_FLAGS += "+define+$(CV_CORE_UC)_TRACE_EXECUTION" VLOG_FLAGS += "+define+UVM" @@ -158,9 +158,10 @@ VSIM_SCRIPT_DIR = $(abspath $(MAKE_PATH)/../tools/vsim) VSIM_UVM_ARGS = +incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm_pkg.sv -VSIM_FLAGS += -sv_lib $(basename $(OVP_MODEL_DPI)) +VSIM_FLAGS += -sv_lib $(basename $(abspath $(IMPERAS_DV_MODEL))) ifeq ($(call IS_YES,$(USE_ISS)),YES) VSIM_FLAGS += +USE_ISS +VLOG_FLAGS += +USE_IMPERASDV else VSIM_FLAGS += +DISABLE_OVPSIM endif @@ -393,20 +394,21 @@ corev-dv: clean_riscv-dv clone_riscv-dv comp_corev-dv # Makefile of this .mk implements "all_compliance", the target that # compiles the test-programs. # -# There is a dependancy between RISCV_ISA and COMPLIANCE_PROG which *you* are -# required to know. For example, the I-ADD-01 test-program is part of the rv32i -# testsuite. +# There is a dependancy between RISCV_DEVICE and COMPLIANCE_PROG which *you* +# are required to know. For example, the add-01 test-program is part of the +# RISCV_DEVICE=I testsuite, where device denotes the ISA extension name. # So this works: -# make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ADD-01 +# make compliance RISCV_DEVICE=I COMPLIANCE_PROG=add-01 # But this does not: -# make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=I-ADD-01 +# make compliance RISCV_DEVICE=C COMPLIANCE_PROG=add-01 # -RISCV_ISA ?= rv32i -COMPLIANCE_PROG ?= I-ADD-01 +RISCV_ISA ?= rv32i_m +RISCV_DEVICE ?= I +COMPLIANCE_PROG ?= add-01 SIG_ROOT ?= $(SIM_CFG_RESULTS)/$(RISCV_ISA) SIG ?= $(SIM_CFG_RESULTS)/$(RISCV_ISA)/$(COMPLIANCE_PROG)/$(RUN_INDEX)/$(COMPLIANCE_PROG).signature_output -REF ?= $(COMPLIANCE_PKG)/riscv-test-suite/$(RISCV_ISA)/references/$(COMPLIANCE_PROG).reference_output +REF ?= $(COMPLIANCE_PKG)/riscv-test-suite/$(RISCV_ISA)/$(RISCV_DEVICE)/references/$(COMPLIANCE_PROG).reference_output COMPLIANCE_RUN_DIR = $(SIM_CFG_RESULTS)/$(RISCV_ISA)/$(COMPLIANCE_PROG)/$(RUN_INDEX) TEST_PLUSARGS ?= +signature=$(COMPLIANCE_PROG).signature_output @@ -414,6 +416,13 @@ ifneq ($(call IS_NO,$(COMP)),NO) VSIM_COMPLIANCE_PREREQ = build_compliance endif +# 40p workaround for ISS configuration +ifeq ($(CV_CORE_LC),cv32e40p) + ISS_CFG = export IMPERAS_TOOLS=$(CORE_V_VERIF)/$(CV_CORE_LC)/tests/cfg/ovpsim_no_pulp.ic +else + ISS_CFG = IMPERAS_TOOLS=$(COMPLIANCE_RUN_DIR)/ovpsim.ic +endif + # Target to run VSIM (i.e. run the simulation) compliance: $(VSIM_COMPLIANCE_PREREQ) $(VSIM_RUN_PREREQ) gen_ovpsim_ic @echo "$(BANNER)" @@ -423,6 +432,7 @@ compliance: $(VSIM_COMPLIANCE_PREREQ) $(VSIM_RUN_PREREQ) gen_ovpsim_ic mkdir -p $(COMPLIANCE_RUN_DIR) && \ cd $(COMPLIANCE_RUN_DIR) && \ $(VMAP) work $(SIM_CFG_RESULTS)/work + $(ISS_CFG) && \ cd $(COMPLIANCE_RUN_DIR) && \ $(VSIM) \ -work $(VWORK) \ @@ -433,10 +443,8 @@ compliance: $(VSIM_COMPLIANCE_PREREQ) $(VSIM_RUN_PREREQ) gen_ovpsim_ic $(RTLSRC_VOPT_TB_TOP) \ $(CFG_PLUSARGS) \ $(TEST_PLUSARGS) \ - +firmware=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(COMPLIANCE_PROG).hex \ - +elf_file=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(COMPLIANCE_PROG).elf - -compliance: export IMPERAS_TOOLS=$(CORE_V_VERIF)/$(CV_CORE_LC)/tests/cfg/ovpsim_no_pulp.ic + +firmware=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(RISCV_DEVICE)/$(COMPLIANCE_PROG).hex \ + +elf_file=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(RISCV_DEVICE)/$(COMPLIANCE_PROG).elf ################################################################################ # Questa simulation targets diff --git a/mk/uvmt/xrun.mk b/mk/uvmt/xrun.mk index 8e2ccb0082..bb1b69757d 100644 --- a/mk/uvmt/xrun.mk +++ b/mk/uvmt/xrun.mk @@ -28,7 +28,7 @@ # OS_IS_UBUNTU = $(findstring Ubuntu,$(shell lsb_release -d)) ifeq ($(OS_IS_UBUNTU),Ubuntu) - .IGNORE: hello-world comp test compliance comp_corev-dv corev-dv gen_corev-dv + .IGNORE: hello-world comp test compliance comp_corev-dv corev-dv gen_corev-dv endif # Executables @@ -37,35 +37,51 @@ SIMVISION = $(CV_TOOL_PREFIX) simvision INDAGO = $(CV_TOOL_PREFIX) indago IMC = $(CV_SIM_PREFIX) imc -XRUN_UVMHOME_ARG ?= CDNS-1.2-ML +XRUN_UVMHOME_ARG ?= CDNS-1.2-ML # Flags -XRUN_COMP_FLAGS ?= -64bit \ - -disable_sem2009 \ - -access +rwc \ - -nowarn UEXPSC \ - -lwdgen \ - -sv \ - -uvm \ - -uvmhome $(XRUN_UVMHOME_ARG) \ - $(TIMESCALE) \ - $(SV_CMP_FLAGS) - -XRUN_LDGEN_COMP_FLAGS ?= -64bit -disable_sem2009 -access +rwc \ - -nowarn UEXPSC \ - -nowarn DLCPTH \ - -sv \ - $(TIMESCALE) $(SV_CMP_FLAGS) +XRUN_COMP_FLAGS ?= \ + -64bit \ + -disable_sem2009 \ + -access +rwc \ + -nowarn UEXPSC \ + -lwdgen \ + -nocsf \ + -sv \ + -uvm \ + -uvmhome $(XRUN_UVMHOME_ARG) \ + $(TIMESCALE) \ + $(SV_CMP_FLAGS) + +XRUN_LDGEN_COMP_FLAGS ?= \ + -64bit \ + -disable_sem2009 \ + -access +rwc \ + -nocsf \ + -nowarn UEXPSC \ + -nowarn DLCPTH \ + -sv \ + -uvm \ + -uvmhome $(XRUN_UVMHOME_ARG) \ + $(TIMESCALE) \ + $(SV_CMP_FLAGS) XRUN_RUN_BASE_FLAGS ?= -64bit $(XRUN_GUI) -licqueue +UVM_VERBOSITY=$(XRUN_UVM_VERBOSITY) \ - $(XRUN_PLUSARGS) -svseed $(RNDSEED) -sv_lib $(OVP_MODEL_DPI) + $(XRUN_PLUSARGS) -svseed $(RNDSEED) XRUN_GUI ?= XRUN_SINGLE_STEP ?= -XRUN_ELAB_COV = -covdut uvmt_$(CV_CORE_LC)_tb -coverage b:e:f:u +XRUN_ELAB_COV = -covdut uvmt_$(CV_CORE_LC)_tb -coverage b:e:f:t:u XRUN_ELAB_COVFILE = -covfile $(abspath $(MAKE_PATH)/../tools/xrun/covfile.tcl) -XRUN_RUN_COV = -covscope uvmt_$(CV_CORE_LC)_tb \ - -nowarn CGDEFN -XRUN_RUN_BASE_FLAGS += -sv_lib $(DPI_DASM_LIB) +XRUN_RUN_COV = -covscope uvmt_$(CV_CORE_LC)_tb -nowarn CGDEFN +XRUN_RUN_BASE_FLAGS += -nocsf -sv_lib $(DPI_DASM_LIB) + +# Only append the IMPERAS_DV_MODEL sv_lib flag if the file actually exists) +ifneq (,$(wildcard $(IMPERAS_DV_MODEL))) + ifeq ($(call IS_YES,$(USE_ISS)),YES) + XRUN_RUN_BASE_FLAGS += -sv_lib $(IMPERAS_DV_MODEL) + endif +endif + XRUN_RUN_BASE_FLAGS += -sv_lib $(abspath $(SVLIB_LIB)) XRUN_UVM_VERBOSITY ?= UVM_MEDIUM @@ -75,7 +91,8 @@ XRUN_UVM_VERBOSITY ?= UVM_MEDIUM DPI_INCLUDE ?= $(shell dirname $(shell which xrun))/../include # Necessary libraries for the PMA generator class -XRUN_PMA_INC += +incdir+$(TBSRC_HOME)/uvmt \ +XRUN_PMA_INC += +incdir+$(DV_UVM_TESTCASE_PATH)/base-tests \ + +incdir+$(TBSRC_HOME)/uvmt \ +incdir+$(CV_CORE_PKG)/rtl/include \ +incdir+$(CV_CORE_COREVDV_PKG)/ldgen \ +incdir+$(abspath $(MAKE_PATH)/../../../lib/mem_region_gen) @@ -83,9 +100,9 @@ XRUN_PMA_INC += +incdir+$(TBSRC_HOME)/uvmt \ ############################################################################### # Common QUIET flag defaults to -quiet unless VERBOSE is set ifeq ($(call IS_YES,$(VERBOSE)),YES) -QUIET= + QUIET= else -QUIET=-quiet + QUIET=-quiet endif ################################################################################ @@ -93,11 +110,14 @@ endif # GUI=YES enables interactive mode # ADV_DEBUG=YES will enable Indago, default is to use SimVision ifeq ($(call IS_YES,$(GUI)),YES) -XRUN_GUI += -gui -XRUN_USER_COMPILE_ARGS += -linedebug -ifeq ($(call IS_YES,$(ADV_DEBUG)),YES) -XRUN_GUI += -indago -endif + XRUN_GUI += -gui + ifeq ($(call IS_YES,$(SRC_DEBUG)),YES) + XRUN_USER_COMPILE_ARGS += -linedebug -uvmlinedebug -enable_tpe -classlinedebug + XRUN_USER_RUN_FLAGS += -linedebug -uvmlinedebug -enable_tpe -classlinedebug + endif + ifeq ($(call IS_YES,$(ADV_DEBUG)),YES) + XRUN_GUI += -indago + endif endif ################################################################################ @@ -124,9 +144,9 @@ endif ################################################################################ # Waveform (post-process) command line ifeq ($(call IS_YES,$(ADV_DEBUG)),YES) -WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(INDAGO) -db ida.db + WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(INDAGO) -db ida.db else -WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(SIMVISION) waves.shm + WAVES_CMD = cd $(SIM_RUN_RESULTS) && $(SIMVISION) waves.shm endif XRUN_USER_COMPILE_ARGS += $(USER_COMPILE_FLAGS) @@ -139,31 +159,31 @@ IMC_REPORT_ARGS = -exec $(CORE_V_VERIF)/$(CV_CORE)/sim/tools/xrun/cov_report.tcl MERGED_COV_DIR ?= merged_cov ifeq ($(call IS_YES,$(COV)),YES) -XRUN_ELAB_COV_FLAGS += $(XRUN_ELAB_COV) -XRUN_ELAB_COV_FLAGS += $(XRUN_ELAB_COVFILE) -XRUN_RUN_COV_FLAGS += $(XRUN_RUN_COV) + XRUN_ELAB_COV_FLAGS += $(XRUN_ELAB_COV) + XRUN_ELAB_COV_FLAGS += $(XRUN_ELAB_COVFILE) + XRUN_RUN_COV_FLAGS += $(XRUN_RUN_COV) endif # Find command to gather ucd files COV_MERGE_FIND = find "$(SIM_CFG_RESULTS)" -type f -name "*.ucd" | grep -v d_cov | xargs dirname ifeq ($(call IS_YES,$(MERGE)),YES) -COV_MERGE = cov_merge -TEST = $(MERGED_COV_DIR) + COV_MERGE = cov_merge + TEST = $(MERGED_COV_DIR) else -COV_MERGE = + COV_MERGE = endif ifeq ($(call IS_YES,$(MERGE)),YES) -COV_DIR ?= $(XRUN_RESULTS)/$(CFG)/$(MERGED_COV_DIR)/cov_work/scope/merged + COV_DIR ?= $(XRUN_RESULTS)/$(CFG)/$(MERGED_COV_DIR)/cov_work/scope/merged else -COV_DIR ?= cov_work/uvmt_$(CV_CORE_LC)_tb/$(TEST_NAME) + COV_DIR ?= cov_work/uvmt_$(CV_CORE_LC)_tb/$(TEST_NAME) endif ifeq ($(call IS_YES,$(GUI)),YES) -COV_ARGS += -gui + COV_ARGS += -gui else -COV_ARGS += $(IMC_REPORT_ARGS) + COV_ARGS += $(IMC_REPORT_ARGS) endif ################################################################################ @@ -173,22 +193,31 @@ endif XRUN_UVM_MACROS_INC_FILE = $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC)_uvm_macros_inc.sv XRUN_FILE_LIST ?= -f $(DV_UVMT_PATH)/uvmt_$(CV_CORE_LC).flist -XRUN_FILE_LIST += -f $(DV_UVMT_PATH)/imperas_iss.flist XRUN_USER_COMPILE_ARGS += +define+$(CV_CORE_UC)_TRACE_EXECUTION XRUN_USER_COMPILE_ARGS += +define+UVM + ifeq ($(call IS_YES,$(USE_ISS)),YES) - XRUN_PLUSARGS += +USE_ISS + ifeq (,$(wildcard $(IMPERAS_HOME)/IMPERAS_LICENSE.pdf)) + export FILE_LIST_IDV_DEPS ?= -f $(DV_UVMT_PATH)/imperas_dummy_pkg.flist + else + export FILE_LIST_IDV ?= -f $(DV_UVMT_PATH)/imperas_dv.flist + export FILE_LIST_IDV_DEPS ?= -f $(DV_UVMT_PATH)/imperas_dv_deps.flist + endif + XRUN_PLUSARGS += +USE_ISS + XRUN_USER_COMPILE_ARGS += +define+USE_IMPERASDV + XRUN_USER_COMPILE_ARGS += +define+USE_ISS else - XRUN_PLUSARGS += +DISABLE_OVPSIM + XRUN_PLUSARGS += +DISABLE_OVPSIM + export FILE_LIST_IDV_DEPS ?= -f $(DV_UVMT_PATH)/imperas_dummy_pkg.flist endif ifeq ($(call IS_YES,$(USE_RVVI)),YES) - XRUN_PLUSARGS +="+USE_RVVI" + XRUN_PLUSARGS +="+USE_RVVI" endif ifeq ($(call IS_YES,$(TEST_DISABLE_ALL_CSR_CHECKS)),YES) - XRUN_PLUSARGS +="+DISABLE_ALL_CSR_CHECKS" + XRUN_PLUSARGS +="+DISABLE_ALL_CSR_CHECKS" endif ifneq ($(TEST_DISABLE_CSR_CHECK),) - XRUN_PLUSARGS += +DISABLE_CSR_CHECK=$(TEST_DISABLE_CSR_CHECK) + XRUN_PLUSARGS += +DISABLE_CSR_CHECK=$(TEST_DISABLE_CSR_CHECK) endif # Simulate using latest elab @@ -199,6 +228,10 @@ XRUN_RUN_FLAGS += $(XRUN_RUN_COV_FLAGS) XRUN_RUN_FLAGS += $(XRUN_USER_RUN_FLAGS) XRUN_RUN_FLAGS += $(USER_RUN_FLAGS) +ifneq ($(CFG_SV_INCLUDE_FILES),) +XRUN_SV_INCLUDE_FILES += +incdir+$(abspath $(CFG_SV_INCLUDE_FILES)) +endif + ############################################################################### # Xcelium warning suppression @@ -248,6 +281,22 @@ XRUN_COMP_FLAGS += -nowarn CGPIDF # deselect_coverage -all warnings XRUN_COMP_FLAGS += -nowarn CGNSWA +# Newer tool version has different fsm coverage options than old version. Ok. +XRUN_COMP_FLAGS += -nowarn COVFDP + +# Certain data types are not supported for toggle cov. Ok. +XRUN_COMP_FLAGS += -nowarn COVUTA + +# MORE toggle cov support CAN be enabled. +XRUN_COMP_FLAGS += -nowarn COVNOEN +XRUN_COMP_FLAGS += -nowarn COVMDD + +# Value Parameters without default values +XRUN_COMP_FLAGS += -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 + +# Type Parameters without default values +XRUN_COMP_FLAGS += -setenv CADENCE_ENABLE_AVSREQ_63188_PHASE_1=1 + # deselect_coverage -all warnings XRUN_COMP_COREV_DV_FLAGS += -nowarn BNDWRN XRUN_COMP_COREV_DV_FLAGS += $(CFG_COMPILE_FLAGS) @@ -264,6 +313,7 @@ XRUN_RUN_COV += -nowarn WCROSS # Un-named covergroup instances XRUN_RUN_COV += -nowarn CGDEFN + ############################################################################### # Targets @@ -292,6 +342,7 @@ XRUN_COMP = $(XRUN_COMP_FLAGS) \ $(XRUN_UVM_MACROS_INC_FILE) \ -f $(CV_CORE_MANIFEST) \ $(XRUN_FILE_LIST) \ + $(XRUN_SV_INCLUDE_FILES) \ $(UVM_PLUSARGS) comp: mk_xrun_dir $(CV_CORE_PKG) $(SVLIB_PKG) @@ -307,7 +358,7 @@ comp: mk_xrun_dir $(CV_CORE_PKG) $(SVLIB_PKG) -elaborate ifneq ($(call IS_NO,$(COMP)),NO) -XRUN_SIM_PREREQ = comp + XRUN_SIM_PREREQ = comp endif XRUN_COMP_RUN = $(XRUN_RUN_FLAGS) @@ -323,6 +374,18 @@ endif # Standalone tb that generates appropriate linker files based on a given pma # configuration. Uses same code as the generator embedded in corev-dv. +# By default, emit results to cfg run directory (Needs CFG set), +# if TEST is set, then emit results to specific test run directory + +LDGEN ?= $(if $(TEST),$(TEST)/$(RUN_INDEX)/test_program,) +WRITABLE_REGION_IDX ?= -1 +ifeq ($(call IS_YES,$(IS_ROM_RAM_LAYOUT)), YES) + ifeq ($(WRITABLE_REGION_IDX), -1) + $(error WRITABLE_REGION_IDX undefined) + endif + LDGEN_CFG_LAYOUT = +writable_region_idx=$(WRITABLE_REGION_IDX) +endif + ldgen: $(CV_CORE_PKG) @echo "$(BANNER)" @echo "* Generating linker scripts in $(SIM_LDGEN_RESULTS)" @@ -336,10 +399,13 @@ ldgen: $(CV_CORE_PKG) $(XRUN_PMA_INC) \ $(CFG_PLUSARGS) \ $(CFG_COMPILE_FLAGS) \ + $(XRUN_SV_INCLUDE_FILES) \ +ldgen_cp_test_path=$(SIM_LDGEN_RESULTS) \ + +standalone_generate=1 \ + $(LDGEN_CFG_LAYOUT) \ $(TBSRC_HOME)/ldgen/ldgen_tb.sv \ -top $(basename $(notdir $(TBSRC_HOME)/ldgen/ldgen_tb.sv)) - cp $(BSP)/link_pma.ld $(SIM_LDGEN_RESULTS)/link.ld + cp $(BSP)/link_corev-dv.ld $(SIM_LDGEN_RESULTS)/link.ld ################################################################################ # If the configuration specified OVPSIM arguments, generate an ovpsim.ic file and @@ -351,6 +417,12 @@ gen_ovpsim_ic: @if [ ! -z "$(CFG_OVPSIM)" ]; then \ echo "$(CFG_OVPSIM)" > $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic; \ fi + # add glossing of registers + @echo "--override cpu/wfi_is_nop=T" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic + #@echo "--trace --tracechange --traceshowicount --monitornetschange --tracemode --tracemem XSA" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic + #@echo "--extlib refRoot/cpu/cat=imperas.com/intercept/cpuContextAwareTracer/1.0" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic + #@echo "--override refRoot/cpu/cat/show_changes=T" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic + #@echo "--override refRoot/cpu/cat/definitions_file=${IMPERAS_HOME}/lib/$(IMPERAS_ARCH)/ImperasLib/riscv.ovpworld.org/processor/riscv/1.0/csr_context_info.lis" >> $(SIM_CFG_RESULTS)/$(TEST_NAME)/$(RUN_INDEX)/ovpsim.ic export IMPERAS_TOOLS=ovpsim.ic ################################################################################ @@ -379,38 +451,46 @@ test: $(XRUN_SIM_PREREQ) hex gen_ovpsim_ic # Makefile of this .mk implements "all_compliance", the target that # compiles the test-programs. # -# There is a dependancy between RISCV_ISA and COMPLIANCE_PROG which *you* are -# required to know. For example, the I-ADD-01 test-program is part of the rv32i -# testsuite. +# There is a dependancy between RISCV_DEVICE and COMPLIANCE_PROG which *you* +# are # required to know. For example, the add-01 test-program is part of the +# RISCV_DEVICE=I testsuite, where device denotes the ISA extension name. # So this works: -# make compliance RISCV_ISA=rv32i COMPLIANCE_PROG=I-ADD-01 +# make compliance RISCV_DEVICE=I COMPLIANCE_PROG=add-01 # But this does not: -# make compliance RISCV_ISA=rv32imc COMPLIANCE_PROG=I-ADD-01 +# make compliance RISCV_DEVICE=C COMPLIANCE_PROG=add-01 # -RISCV_ISA ?= rv32i -COMPLIANCE_PROG ?= I-ADD-01 +RISCV_ISA ?= rv32i_m +RISCV_DEVICE ?= I +COMPLIANCE_PROG ?= add-01 SIG_ROOT ?= $(SIM_CFG_RESULTS)/$(RISCV_ISA) SIG ?= $(SIM_CFG_RESULTS)/$(RISCV_ISA)/$(COMPLIANCE_PROG)/$(RUN_INDEX)/$(COMPLIANCE_PROG).signature_output -REF ?= $(COMPLIANCE_PKG)/riscv-test-suite/$(RISCV_ISA)/references/$(COMPLIANCE_PROG).reference_output +REF ?= $(COMPLIANCE_PKG)/riscv-test-suite/$(RISCV_ISA)/$(RISCV_DEVICE)/references/$(COMPLIANCE_PROG).reference_output TEST_PLUSARGS ?= +signature=$(COMPLIANCE_PROG).signature_output ifneq ($(call IS_NO,$(COMP)),NO) -XRUN_COMPLIANCE_PREREQ = comp build_compliance + XRUN_COMPLIANCE_PREREQ = comp build_compliance +endif + +# 40p workaround for ISS configuration +ifeq ($(CV_CORE_LC),cv32e40p) + ISS_CFG = export IMPERAS_TOOLS=$(CORE_V_VERIF)/$(CV_CORE_LC)/tests/cfg/ovpsim_no_pulp.ic +else + ISS_CFG = export IMPERAS_TOOLS=ovpsim.ic endif compliance: $(XRUN_COMPLIANCE_PREREQ) mkdir -p $(SIM_CFG_RESULTS)/$(RISCV_ISA)/$(COMPLIANCE_PROG)/$(RUN_INDEX) && \ cd $(SIM_CFG_RESULTS)/$(RISCV_ISA)/$(COMPLIANCE_PROG)/$(RUN_INDEX) && \ - export IMPERAS_TOOLS=$(CORE_V_VERIF)/$(CV_CORE_LC)/tests/cfg/ovpsim_no_pulp.ic && \ + $(ISS_CFG) && \ $(XRUN) -R -xmlibdirname ../../../xcelium.d \ -l xrun-$(COMPLIANCE_PROG).log \ -covtest riscv-compliance $(XRUN_COMP_RUN) \ $(TEST_PLUSARGS) \ $(XRUN_RUN_WAVES_FLAGS) \ +UVM_TESTNAME=uvmt_$(CV_CORE_LC)_firmware_test_c \ - +firmware=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(COMPLIANCE_PROG).hex \ - +elf_file=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(COMPLIANCE_PROG).elf + +firmware=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(RISCV_DEVICE)/$(COMPLIANCE_PROG).hex \ + +elf_file=$(COMPLIANCE_PKG)/work/$(RISCV_ISA)/$(RISCV_DEVICE)/$(COMPLIANCE_PROG).elf @@ -434,6 +514,7 @@ comp_corev-dv: $(RISCVDV_PKG) $(CV_CORE_PKG) +incdir+$(COREVDV_PKG) \ +incdir+$(CV_CORE_COREVDV_PKG) \ -f $(COREVDV_PKG)/manifest.f \ + $(XRUN_SV_INCLUDE_FILES) \ -l xrun.log corev-dv: clean_riscv-dv \ diff --git a/vendor_lib/imperas/design/monitor.sv b/vendor_lib/imperas/design/monitor.sv index 99511c3df2..9dfd904c94 100644 --- a/vendor_lib/imperas/design/monitor.sv +++ b/vendor_lib/imperas/design/monitor.sv @@ -15,10 +15,13 @@ * for the location of the open source models. * */ - - `include "typedefs.sv" -module MONITOR +`ifndef __IMPERAS_MONITOR_SV__ +`define __IMPERAS_MONITOR_SV__ + +`include "typedefs.sv" + +module MONITOR ( RVVI_bus bus, RVVI_io io @@ -33,12 +36,12 @@ module MONITOR watchT _test_stdout; watchT _test_exit; watchT _test_intc_machine_external; - watchT _test_intc_machine_software; - watchT _test_intc_machine_timer; + watchT _test_intc_machine_software; + watchT _test_intc_machine_timer; watchT trap_vector; - + int fd_signature, fd_stdout; - + function automatic void split_string ( output string out [$], input string in, @@ -63,20 +66,20 @@ module MONITOR end end endfunction - + function automatic void nm_get(string name_sym, ref watchT watch); if (addr_sym.exists(name_sym)) begin watch.addr = addr_sym[name_sym]; watch.enable = 1; end endfunction - + function automatic void nm_load(); int i, j; string line; string linesplit[$]; string name_sym; - + // simply return if not provided if (!($value$plusargs("nm_file=%s", fn_sym))) begin return; @@ -87,30 +90,30 @@ module MONITOR if (fd_sym == 0) begin return; end - + while ($fgets(line, fd_sym)) begin j = line.len() - 2; line = line.substr(0, j); - + split_string(linesplit, line, " ", 0); name_sym = linesplit[2]; - + addr_sym[name_sym] = linesplit[0].atohex(); type_sym[name_sym] = linesplit[1]; end $fclose(fd_sym); endfunction - + // Generate a signature dump file function automatic void dumpSignature(); automatic int addr = begin_signature.addr; automatic string sig_file = "signature.txt"; - + if (!begin_signature.enable) return; if ($value$plusargs("sig_file=%s", sig_file)) ; $display("Writing signature %s", sig_file); - + $display("Dump Signature 0x%x -> 0x%x", begin_signature.addr, end_signature.addr); fd_signature = $fopen(sig_file, "w"); @@ -119,48 +122,48 @@ module MONITOR $fwrite(fd_signature, "%x\n", ram.memory.mem[addr>>2]); addr = addr + 4; end - + $fclose(fd_signature); endfunction - + function void openStdout(); automatic string stdout_file = "stdout.txt"; if ($value$plusargs("stdout_file=%s", stdout_file)) ; $display("Opening stdout %s", stdout_file); - + fd_stdout = $fopen(stdout_file, "w"); endfunction - + function void closeStdout(); $fclose(fd_stdout); endfunction - + initial begin nm_load(); - + nm_get("trap_vector" , trap_vector); nm_get("begin_signature", begin_signature); nm_get("end_signature" , end_signature); nm_get("_test_stdout" , _test_stdout); - + nm_get("_test_intc_machine_external" , _test_intc_machine_external); nm_get("_test_intc_machine_software" , _test_intc_machine_software); nm_get("_test_intc_machine_timer" , _test_intc_machine_timer); - + nm_get("_test_exit" , _test_exit); nm_get("write_tohost" , _test_exit); // used for riscv-dv and riscv-compliance if (trap_vector.enable) $display("trap_vector=%x", trap_vector.addr); - + if (begin_signature.enable) $display("begin_signature=%x", begin_signature.addr); if (end_signature.enable) $display("end_signature=%x", end_signature.addr); - + if (_test_stdout.enable) $display("_test_stdout=%x", _test_stdout.addr); - + if (_test_intc_machine_external.enable) $display("_test_intc_machine_external=%x", _test_intc_machine_external.addr); if (_test_intc_machine_software.enable) @@ -169,10 +172,10 @@ module MONITOR $display("_test_intc_machine_timer=%x", _test_intc_machine_timer.addr); if (_test_exit.enable) $display("_test_exit=%x", _test_exit.addr); - + openStdout(); end - + bit [31:0] DAddr, IAddr; bit [31:0] DData, IData; bit [3:0] Dbe, Ibe; @@ -182,11 +185,11 @@ module MONITOR bit MTInt; bit MEInt; bit reset; - + int int_machine_external_cnt; int int_machine_software_cnt; int int_machine_timer_cnt; - + always @(*) begin DAddr = bus.DAddr; DData = bus.DData; @@ -196,7 +199,7 @@ module MONITOR IData = bus.IData; Ibe = bus.Ibe; ISize = bus.ISize; - + reset = io.reset; MSWInt = io.irq_i[3]; MTInt = io.irq_i[7]; @@ -208,7 +211,7 @@ module MONITOR RD = IF | LD; WR = ST; end - + always @(posedge bus.Clk) begin if (bus.Ird) begin // EXIT @@ -222,10 +225,10 @@ module MONITOR io.Shutdown = 1; end end - + if (bus.Drd) begin end - + if (bus.Dwr) begin // STDOUT if (_test_stdout.enable && bus.DAddr==_test_stdout.addr) begin @@ -234,7 +237,7 @@ module MONITOR $fwrite(fd_stdout, "%c", c); $fflush(fd_stdout); end - + // // Interrupt Generation // @@ -245,7 +248,7 @@ module MONITOR $display("io.irq_i[11] = 0"); io.irq_i[11] = 0; end - end + end if (_test_intc_machine_software.enable && bus.DAddr==_test_intc_machine_software.addr) begin int_machine_software_cnt = bus.DData; if (int_machine_software_cnt == 0) begin @@ -263,21 +266,21 @@ module MONITOR end end end - + // Machine External Interrupt Generation if (int_machine_external_cnt > 1) begin int_machine_external_cnt = int_machine_external_cnt - 1; end else if ((int_machine_external_cnt == 1) && (io.irq_i[11] == 0)) begin $display("io.irq_i[11] = 1"); io.irq_i[11] = 1; - end - + end + // Machine_timer Interrupt Generation if (int_machine_timer_cnt > 1) begin int_machine_timer_cnt = int_machine_timer_cnt - 1; end else if ((int_machine_timer_cnt == 1) && (io.irq_i[7] == 0)) begin $display("io.irq_i[7] = 1"); - io.irq_i[7] = 1; + io.irq_i[7] = 1; end // Machine_software Interrupt Generation @@ -285,12 +288,14 @@ module MONITOR int_machine_software_cnt = int_machine_software_cnt - 1; end else if ((int_machine_software_cnt == 1) && (io.irq_i[3] == 0)) begin $display("io.irq_i[3] = 1"); - io.irq_i[3] = 1; + io.irq_i[3] = 1; end end // always @ (posedge bus.Clk) - + final begin dumpSignature(); closeStdout(); end endmodule + +`endif // __IMPERAS_MONITOR_SV__ diff --git a/vendor_lib/imperas/design/ram.sv b/vendor_lib/imperas/design/ram.sv index b5b589f34f..01d0ba43ca 100644 --- a/vendor_lib/imperas/design/ram.sv +++ b/vendor_lib/imperas/design/ram.sv @@ -15,9 +15,12 @@ * for the location of the open source models. * */ - - `include "typedefs.sv" - + +`ifndef __IMPERAS_RAM_SV__ +`define __IMPERAS_RAM_SV__ + +`include "typedefs.sv" + interface RVVI_memory; reg [31:0] mem [bit[29:0]]; @@ -36,7 +39,7 @@ module RAM parameter int RAM_BYTE_SIZE = 'h20000 ) ( - RVVI_bus bus + RVVI_bus bus ); Uns32 daddr4, iaddr4; @@ -53,7 +56,7 @@ module RAM loRAM = hiROM + 1; hiRAM = loRAM + RAM_BYTE_SIZE - 1; end - + function automatic Uns32 byte2bit (input int ByteEn); Uns32 BitEn = 0; if (ByteEn & 'h1) BitEn |= 'h000000FF; @@ -62,14 +65,14 @@ module RAM if (ByteEn & 'h8) BitEn |= 'hFF000000; return BitEn; endfunction - + always @(posedge bus.Clk) begin isROM = (bus.IAddr>=loROM && bus.IAddr<=hiROM); isRAM = (bus.DAddr>=loRAM && bus.DAddr<=hiRAM); - + daddr4 = bus.DAddr >> 2; iaddr4 = bus.IAddr >> 2; - + // Uninitialized Memory if (!memory.mem.exists(daddr4)) memory.mem[daddr4] = 'h0; if (!memory.mem.exists(iaddr4)) memory.mem[iaddr4] = 'h0; @@ -88,10 +91,10 @@ module RAM value = memory.mem[daddr4] & ~(byte2bit(bus.Dbe)); memory.mem[daddr4] = value | (bus.DData & byte2bit(bus.Dbe)); //$display("Store %08x <= %08X", daddr4, mem[daddr4]); - + end end - + // EXEC if (isROM) begin if (bus.Ird==1) begin @@ -99,7 +102,7 @@ module RAM //$display("Fetch %08x <= [%08X]", bus.IData, iaddr4); end end - + // checkers if (bus.Ird==1 && isROM==0) begin //$display("ERROR: Fetch Address %08X does not have EXECUTE permission", bus.IAddr); @@ -116,3 +119,5 @@ module RAM end endmodule + +`endif // __IMPERAS_RAM_SV__ diff --git a/vendor_lib/imperas/imperas_DV_COREV/ChangeLog.md b/vendor_lib/imperas/imperas_DV_COREV/ChangeLog.md index 1d02f32685..aac83629dc 100644 --- a/vendor_lib/imperas/imperas_DV_COREV/ChangeLog.md +++ b/vendor_lib/imperas/imperas_DV_COREV/ChangeLog.md @@ -1,6 +1,6 @@ CV32E40P Change Log === -Copyright (c) 2005-2021 Imperas Software Ltd., www.imperas.com +Copyright (c) 2005-2022 Imperas Software Ltd., www.imperas.com This CHANGELOG contains information for the Imperas OVP OpenHW CV32E40P fixed platform which includes information of the OVP Simulator and RISCV processor model diff --git a/vendor_lib/imperas/imperas_DV_COREV/README.md b/vendor_lib/imperas/imperas_DV_COREV/README.md index 2715cab1b8..750344ccf9 100644 --- a/vendor_lib/imperas/imperas_DV_COREV/README.md +++ b/vendor_lib/imperas/imperas_DV_COREV/README.md @@ -4,8 +4,8 @@ A Complete, Fully Functional, Configurable CV32E40P Simulation Model === Author: Imperas Software, Ltd., using OVP Open Standard APIs -Date : 20211209 -Version: 20200821.475 +Date : 20220627 +Version: 20200821.675 License: Simulation Model CV32E40P licensed under [Software License Agreement for Open Virtual Platforms Technology](OVP_IMPERAS_LICENSE.pdf) RISC-V Specifications currently supported: - RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.3) diff --git a/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so b/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so index 8db90517c0..c009ad181b 100755 Binary files a/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so and b/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so differ diff --git a/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf index 00b1b91310..ec89c20993 100644 Binary files a/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf and b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf differ diff --git a/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40S.pdf b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40S.pdf index d19bcaf2c5..948ae710a6 100644 Binary files a/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40S.pdf and b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40S.pdf differ diff --git a/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X.pdf b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X.pdf index 36ff8095ec..970cded4ea 100644 Binary files a/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X.pdf and b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X.pdf differ diff --git a/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X_DEV.pdf b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X_DEV.pdf new file mode 100644 index 0000000000..9cab2e6936 Binary files /dev/null and b/vendor_lib/imperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X_DEV.pdf differ diff --git a/vendor_lib/imperas/imperas_DV_COREV/sv/imperas_CV32.sv b/vendor_lib/imperas/imperas_DV_COREV/sv/imperas_CV32.sv index 835ff8b217..86cf5f992f 100644 --- a/vendor_lib/imperas/imperas_DV_COREV/sv/imperas_CV32.sv +++ b/vendor_lib/imperas/imperas_DV_COREV/sv/imperas_CV32.sv @@ -1,6 +1,6 @@ /* * - * Copyright (c) 2005-2021 Imperas Software Ltd., www.imperas.com + * Copyright (c) 2005-2022 Imperas Software Ltd., www.imperas.com * * The contents of this file are provided under the Software License * Agreement that you accepted before downloading this file. @@ -19,14 +19,19 @@ //`define DEBUG //`define UVM +`ifndef __IMPERAS_CV32__ +`define __IMPERAS_CV32__ + `include "typedefs.sv" typedef struct { Uns64 reset; Uns64 reset_addr; + Uns64 nmi; Uns64 nmi_cause; Uns64 nmi_addr; + Uns64 MSWInterrupt; Uns64 MTimerInterrupt; Uns64 MExternalInterrupt; @@ -46,13 +51,15 @@ typedef struct { Uns64 LocalInterrupt13; Uns64 LocalInterrupt14; Uns64 LocalInterrupt15; + Uns64 haltreq; Uns64 resethaltreq; + Uns64 deferint; + Uns64 IllegalInstruction; - Uns64 LoadBusFaultNMI; - Uns64 StoreBusFaultNMI; Uns64 InstructionBusFault; + } SVData_ioT; typedef struct { @@ -74,6 +81,7 @@ typedef struct { typedef struct { // Signals from SV Uns64 cycles; + Uns64 intr; } SVData_stateT; `ifndef DMI_RAM_PATH @@ -88,18 +96,19 @@ interface RVVI_state #( // RISCV output signals // event notify; - - bit valid; // Retired instruction - bit trap; // Trapped instruction - bit halt; // Halted instruction - + + bit valid; // Retired instruction + bit trap; // Trapped instruction + bit halt; // Halted instruction + bit sleep; // Sleeiping instruction + bit intr; // Flag first instruction of trap handler bit [(XLEN-1):0] order; bit [(ILEN-1):0] insn; bit [2:0] isize; bit [1:0] mode; bit [1:0] ixl; - + string decode; bit [(XLEN-1):0] pc; @@ -110,7 +119,7 @@ interface RVVI_state #( bit [(XLEN-1):0] f[32]; bit [(XLEN-1):0] c[bit[11:0]]; bit [(XLEN-1):0] csr[string]; - + // Temporary hack for volatile CSR reads bit [31:0] GPR_rtl[32]; endinterface @@ -119,35 +128,35 @@ typedef enum { IDLE, STEPI, STOP, CONT } rvvi_c_e; interface RVVI_control; event notify; - + rvvi_c_e cmd; bit ssmode; - + bit state_idle; bit state_stepi; bit state_stop; bit state_cont; - + initial ssmode = 1; - + assign state_idle = (cmd == IDLE); assign state_stepi = (cmd == STEPI); assign state_stop = (cmd == STOP); assign state_cont = (cmd == CONT); - + function automatic void idle(); cmd = IDLE; ->notify; - endfunction + endfunction function automatic void stepi(); cmd = STEPI; ->notify; - endfunction + endfunction function automatic void stop(); ssmode = 1; cmd = STOP; ->notify; - endfunction + endfunction function automatic void cont(); ssmode = 0; cmd = CONT; @@ -156,38 +165,39 @@ interface RVVI_control; endinterface interface RVVI_io; - bit reset; - bit [31:0] reset_addr; - bit nmi; - bit [31:0] nmi_cause; - bit [31:0] nmi_addr; - - bit [31:0] irq_i; // Active high level sensitive interrupt inputs - bit irq_ack_o; // Interrupt acknowledge - bit [4:0] irq_id_o; // Interrupt index for taken interrupt - only valid on irq_ack_o = 1 - bit deferint; // Artifact signal to gate the last stage of interrupt - - bit haltreq; - bit resethaltreq; - bit DM; - - bit LoadBusFaultNMI; // signal memory interface error (E40X) - bit StoreBusFaultNMI; // signal memory interface error (E40X) - bit InstructionBusFault; // signal memory interface error (E40X) - - bit Shutdown; + bit reset; + bit [31:0] reset_addr; + bit nmi; + bit [31:0] nmi_cause; + bit [31:0] nmi_addr; + + bit [31:0] irq_i; // Active high level sensitive interrupt inputs + bit irq_ack_o; // Interrupt acknowledge + bit [10:0] irq_id_o; // Interrupt index for taken interrupt - only valid on irq_ack_o = 1 + + bit deferint; // Artifact signal to gate the last stage of interrupt/debug + bit intr; // artifact to indicate taking a double exception, delay the debugreq + + bit haltreq; + bit resethaltreq; + bit DM; + + bit IllegalInstruction; + bit InstructionBusFault; // signal memory interface error (E40X) + + bit Shutdown; endinterface interface RVVI_bus; bit Clk; - + bit [31:0] DAddr; // Data Bus Address bit [31:0] DData; // Data Bus LSU Data bit [3:0] Dbe; // Data Bus Lane enables (byte format) bit [2:0] DSize; // Data Bus Size of transfer 1-4 bytes bit Dwr; // Data Bus write bit Drd; // Data Bus read - + bit [31:0] IAddr; // Instruction Bus Address bit [31:0] IData; // Instruction Bus Data bit [3:0] Ibe; // Instruction Bus Lane enables (byte format) @@ -217,21 +227,21 @@ module CPU #( export "DPI-C" task svexp_busLoad; export "DPI-C" task svexp_busStore; export "DPI-C" task svexp_busWait; - + export "DPI-C" function svexp_setGPR; export "DPI-C" function svexp_getGPR; - + export "DPI-C" function svexp_setCSR; export "DPI-C" function svexp_pull; - + export "DPI-C" task svexp_setRESULT; export "DPI-C" function svexp_setDECODE; - + RVVI_state state(); RVVI_control control(); - + bit [31:0] cycles; - + bit initialized = 0; RMData_ioT RMData_io; @@ -252,9 +262,8 @@ module CPU #( io.deferint or io.haltreq or io.resethaltreq or - io.LoadBusFaultNMI or - io.StoreBusFaultNMI or io.InstructionBusFault or + io.intr or cycles ) begin if (initialized) svimp_netupdate(); @@ -283,7 +292,7 @@ module CPU #( `endif `endif endfunction - + function automatic void msgfatal (input string msg); `ifdef UVM `uvm_fatal(VARIANT, msg); @@ -292,7 +301,7 @@ module CPU #( $fatal; `endif endfunction - + task busStep; if (control.ssmode) begin while (control.cmd != STEPI) begin @@ -300,42 +309,54 @@ module CPU #( end end endtask - + task busWait; @(posedge bus.Clk); + if (state.valid==1) state.valid = 0; busStep; endtask - + task svexp_busWait; busWait; endtask - + // Called at end of instruction transaction task svexp_setRESULT; input int isvalid; - + control.idle(); svimp_pull(RMData_io, RMData_state); - + io.irq_ack_o = RMData_io.irq_ack_o; io.irq_id_o = RMData_io.irq_id_o; io.DM = RMData_io.DM; - - // RVVI_S - if (isvalid) begin - state.valid = 1; - state.trap = 0; - state.pc = RMData_state.retPC; - end else begin - state.valid = 0; - state.trap = 1; - state.pc = RMData_state.excPC; - end - + + state.valid = 1; + state.trap = 0; + state.sleep = 0; state.pcnext = RMData_state.nextPC; state.order = RMData_state.order; - + + // Exception + if (isvalid==0) begin + state.valid = 0; // E40P Only + state.trap = 1; + state.pc = RMData_state.excPC; + + // Sleep + end else if (isvalid==1) begin + state.sleep = 1; + state.pc = RMData_state.retPC; + + // Retire + end else if (isvalid==2) begin + state.pc = RMData_state.retPC; + + end else begin + $display("Unexpected isvalid=%0d %0t", isvalid, $time); + end + ->state.notify; endtask @@ -348,7 +369,7 @@ module CPU #( SVData_io.nmi = io.nmi; SVData_io.nmi_cause = io.nmi_cause; SVData_io.nmi_addr = io.nmi_addr; - + SVData_io.MSWInterrupt = io.irq_i[3]; SVData_io.MTimerInterrupt = io.irq_i[7]; SVData_io.MExternalInterrupt = io.irq_i[11]; @@ -373,14 +394,14 @@ module CPU #( SVData_io.haltreq = io.haltreq; SVData_io.resethaltreq = io.resethaltreq; - - SVData_io.LoadBusFaultNMI = io.LoadBusFaultNMI; - SVData_io.StoreBusFaultNMI = io.StoreBusFaultNMI; - + SVData_io.InstructionBusFault = io.InstructionBusFault; - + + SVData_io.IllegalInstruction = io.IllegalInstruction; + SVData_state.cycles = cycles; - + SVData_state.intr = io.intr; + svimp_push(SVData_io, SVData_state); initialized = 1; endfunction @@ -390,15 +411,15 @@ module CPU #( state.insn = insn; state.isize = isize; endfunction - + function automatic void svexp_getGPR (input int index, output longint value); value = state.GPR_rtl[index]; endfunction - + function automatic void svexp_setGPR (input int index, input longint value); state.x[index] = value; endfunction - + function automatic void svexp_setCSR (input string name, input int index, input longint value); state.csr[name] = value; state.c[index] = value; @@ -444,7 +465,7 @@ module CPU #( end return enable; endfunction - + function automatic Uns32 byte2bit (input int ByteEn); Uns32 BitEn = 0; if (ByteEn & 'h1) BitEn |= 'h000000FF; @@ -453,39 +474,39 @@ module CPU #( if (ByteEn & 'h8) BitEn |= 'hFF000000; return BitEn; endfunction - + // shift data based upon byte address function automatic Uns32 getData (input int address, input int data); Uns32 addr4 = address & 3; Uns32 sdata = data << (addr4 * 8); return sdata; endfunction - + // shift data based upon byte address function automatic Uns32 setData (input int address, input int data); Uns32 addr4 = address & 3; Uns32 sdata = data >> (addr4 * 8); return sdata; endfunction - + function automatic void dmiWrite(input int address, input int ble, input int data); Uns32 wValue; Uns32 idx = address >> 2; Uns32 dValue = getData(address, data); - + msginfo($sformatf("%08X = %02x", address, data)); wValue = read(idx) & ~(byte2bit(ble)); wValue |= (dValue & byte2bit(ble)); - + write(idx, wValue); endfunction - + task busStore32; input int address; input int size; input int data; input int artifact; - + automatic Uns32 ble = getBLE(address, size); automatic Uns32 dValue = getData(address, data); @@ -500,49 +521,48 @@ module CPU #( bus.Dwr = 1; bus.Dbe = ble; bus.DData = dValue; - + // wait for the transfer to complete busWait; bus.Dwr = 0; - SVData_io.StoreBusFaultNMI = io.StoreBusFaultNMI; end endtask - + task svexp_busStore; - output int fault; + output int fault; input int address; input int size; input int data; input int artifact; - + // // Are we over an address boundary ? // firstly consider 32 bit // int overflow; overflow = (address & 'h3) + (size - 1); - + fault = 0; - + // Aligned access if (overflow < 4) begin busStore32(address, size, data, artifact); - + // Misaligned access end else begin int lo, hi, address_lo, address_hi, size_lo, size_hi; - + // generate a data for 2 transactions lo = data; hi = data >> (32 - ((address & 'h3) * 8)); - + // size_lo number of bytes written to lower word size_lo = 4 - (address & 'h3); size_hi = size - size_lo; - + address_lo = address; address_hi = (address & ~('h3)) + 4; - + busStore32(address_lo, size_lo, lo, artifact); busStore32(address_hi, size_hi, hi, artifact); end @@ -551,20 +571,20 @@ module CPU #( function automatic void dmiRead(input int address, input int ble, output int data); Uns32 rValue; Uns32 idx = address >> 2; - + rValue = read(idx) & byte2bit(ble); - + data = setData(address, rValue); endfunction task busLoad32; input int address; input int size; - output int data; - input int artifact; + output int data; + input int artifact; automatic Uns32 ble = getBLE(address, size); - + if (artifact) begin dmiRead(address, ble, data); @@ -573,48 +593,46 @@ module CPU #( bus.DSize = size; bus.Dbe = ble; bus.Drd = 1; - + // Wait for the transfer to complete & ssmode busWait; data = setData(address, bus.DData); bus.Drd = 0; - SVData_io.LoadBusFaultNMI = io.LoadBusFaultNMI; - msginfo($sformatf("[%x]=>(%0d)%x Load", address, size, data)); end endtask - + task svexp_busLoad; output int fault; input int address; input int size; - output int data; - input int artifact; + output int data; + input int artifact; // // Are we over an address boundary ? // firstly consider 32 bit // - int overflow; + int overflow; overflow = (address & 'h3) + (size - 1); - + fault = 0; - + // Aligned access if (overflow < 4) begin busLoad32(address, size, data, artifact); - + // Misaligned access end else begin int lo, hi, address_lo, address_hi; - + // generate a wide data value address_lo = address & ~('h3); address_hi = address_lo + 4; busLoad32(address_lo, 4, lo, artifact); busLoad32(address_hi, 4, hi, artifact); - + data = {hi, lo} >> ((address & 'h3) * 8); end endtask @@ -627,16 +645,16 @@ module CPU #( output int fault; input int address; input int size; - output int data; - input int artifact; + output int data; + input int artifact; // word aligned address automatic Uns32 waddr = address & ~3; automatic Uns32 wdata; - + automatic Uns32 ble = getBLE(address, size); automatic int iscache = 0; - + if (artifact) begin ble = getBLE(address, size); dmiRead(address, ble, data); @@ -647,65 +665,65 @@ module CPU #( wdata = setData(address, cache_wdata); fault = cache_fault; iscache = 1; - + end else begin busStep; bus.IAddr = waddr; bus.ISize = 4; bus.Ibe = 'hF; bus.Ird = 1; - + // Wait for the transfer to complete & ssmode busWait; - + wdata = setData(address, bus.IData); fault = io.InstructionBusFault; bus.Ird = 0; - + end - + msginfo($sformatf("[%x]=>(%0d)%x Fetch", address, size, data)); - + // Save for next cached access cache_waddr = waddr; cache_wdata = wdata; cache_fault = fault; - + data = wdata & byte2bit(ble); - - //$display("busFetch32 address=%08X (iscache=%0d) cache_waddr=%08X : wdata=%08X cache_wdata=%08X data=%08X ble=%08X fault=%0d", + + //$display("busFetch32 address=%08X (iscache=%0d) cache_waddr=%08X : wdata=%08X cache_wdata=%08X data=%08X ble=%08X fault=%0d", // address, iscache, cache_waddr, wdata, cache_wdata, data, ble, fault); end endtask - + task svexp_busFetch; output int fault; input int address; input int size; - output int data; - input int artifact; - + output int data; + input int artifact; + // // Are we over an address boundary ? // firstly consider 32 bit // int overflow; overflow = (address & 'h3) + (size - 1); - + // Aligned access if (overflow < 4) begin busFetch32(fault, address, size, data, artifact); - + // Misaligned access end else begin int lo, hi, address_lo, address_hi, fault_lo, fault_hi; - + // generate a wide data value address_lo = address & ~('h3); address_hi = address_lo + 4; busFetch32(fault_lo, address_lo, 4, lo, artifact); busFetch32(fault_hi, address_hi, 4, hi, artifact); - + data = {hi, lo} >> ((address & 'h3) * 8); fault = fault_lo | fault_hi; // TODO end @@ -717,14 +735,14 @@ module CPU #( msgfatal($sformatf("+elf_file= is required")); end endfunction - + string ovpcfg; function automatic void ovpcfg_load(); ovpcfg = ""; if ($value$plusargs("ovpcfg=%s", ovpcfg)) begin end endfunction - + initial begin if (!$test$plusargs("DISABLE_OVPSIM")) begin #1; @@ -736,11 +754,13 @@ module CPU #( `endif end end - + `ifndef UVM final begin svimp_exit(); end `endif - + endmodule + +`endif // __IMPERAS_CV32__