diff --git a/FOEDAG_rs b/FOEDAG_rs
index 476265a7..4bf64a11 160000
--- a/FOEDAG_rs
+++ b/FOEDAG_rs
@@ -1 +1 @@
-Subproject commit 476265a75643eff4015da80319c6d8d2e1a17e22
+Subproject commit 4bf64a11cf9d2920050728c84c1b01e7a06593a9
diff --git a/README.md b/README.md
index e17f16b2..d9f0a21d 100644
--- a/README.md
+++ b/README.md
@@ -139,11 +139,12 @@ Tcl commands (Available in GUI or Batch console or Batch script):
      -no_adder                  : Do not infer adders
      -inferred_io               : Automatic I/O inference (Default false for eFPGA)
      -no_inferred_io            : No automatic I/O inference (Default true for FPGA)
-     -read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
-       0                        : Initialize register by '0' (default)
-       1                        : Initialize register by '1'
-       2                        : Leave register unintialized
-   set_limits <type> <int>    : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
+     -no_sat                  : Disable SAT solver
+     -init_registers <int>    : Force initialization of uninitialized registers
+       0                      : '0' value means initialize with '0' (Default '0' is used)
+       1                      : '1' value means initialize with '1'
+       2                      : '2' value means leave it uninitialized
+  set_limits <type> <int>     : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
        dsp                    : Maximum number of usable DSPs
        bram                   : Maximum number of usable BRAMs
        carry_length           : Maximum carry length
diff --git a/etc/help.txt b/etc/help.txt
index ef894cf6..4d3221c3 100644
--- a/etc/help.txt
+++ b/etc/help.txt
@@ -130,11 +130,11 @@ Tcl commands (Available in GUI or Batch console or Batch script):
      -no_adder                  : Do not infer adders
      -inferred_io               : Automatic I/O inference (Default false for eFPGA)
      -no_inferred_io            : No automatic I/O inference (Default true for FPGA)
-     -read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
-       0                        : Initialize register by '0' (default)
-       1                        : Initialize register by '1'
-       2                        : Leave register unintialized
-<engineering>
+     -no_sat                  : Disable SAT solver
+     -init_registers <int>    : Force initialization of uninitialized registers
+       0                      : '0' value means initialize with '0' (Default '0' is used)
+       1                      : '1' value means initialize with '1'
+       2                      : '2' value means leave it uninitialized<engineering>
      -clke_strategy <strategy>: Clock enable extraction strategy for FFs:
        early                  : Perform early extraction
        late                   : Perform late extraction
diff --git a/etc/settings/settings_test.json b/etc/settings/settings_test.json
index fececbb7..d0d5fa23 100644
--- a/etc/settings/settings_test.json
+++ b/etc/settings/settings_test.json
@@ -120,6 +120,19 @@
                 "stepVal": 1,
                 "arg": "carry_chain_limit"
             },
+            "init_registers_spinbox_ex": {
+                "label": "Init Registers",
+                "widgetType": "spinbox",
+                "minVal": 0,
+                "maxVal": 2,
+                "stepVal": 1,
+                "arg": "init_registers"
+            },
+            "no_sat_checkbox": {
+                "label": "No Sat",
+                "widgetType": "checkbox",
+                "arg": "no_sat"
+            },
             "fast_checkbox": {
                 "label": "Fast Synthesis",
                 "widgetType": "checkbox",