Timing Violation in FPU

[AD738560581]

Hello, I meet some problem which confuse me too many days. I want to evaluate the area of ara under 22nm technology and worst case, which is same with your parer, but we use the Genus to synthesize. We only provide the clock and IO constraint with the 1GHz, but we meet timing violation in FPU module which is about 607ps. However, it is too far from 1GHz. Then I use retiming in FPU module, which timing violation will reach about 300ps, which only get 800MHz.

So, I want ask is there a problem with my operation? Could I refer to your synthesize script for our project？
If you could spare some time to answer my doubts, I would greatly appreciate it. I would like to express my gratitude to you on behalf of our team.

[mp-17]

Hello @AD738560581,

Are you considering the worst corner? We achieve ~950 MHz in the slowest corner, and we need to retime our FPUs, too.
Anyhow, 800 MHz seems anyway still far. Unluckily, I don't know which libraries you are using, and we also use a different synthesis tool.
BTW, are you using the default configuration we use in the main branch of the repo for the FPU configuration? Where is your critical path?

Best,
Matteo