All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog and this project adheres to Semantic Versioning.
- Added Support for Single-Data-Rate (SDR) PHY
- Removed ternary statement in
serial_link_physicalfor better EDA tool compatibility.
- The DDR output data is now muxed by a normal signal instead of a clock signal. Some tools infer a clock gate when a clock signal is used as a mux select signal.
- Renamed clock division configuration registers to deliberately introduce breaking changes when using the old incorrect configuration registers.
- SW Clock division configuration
- Added
NoRegCdcparameter toserial_linkmodule to disable the CDC between the RegBus Clock and the System Clock
- Initial release