Sobel/roberts accelerator or AES256.
- Study of memory management
- Study of communication management (DMA)
- Brief description of DMA and its interface
- Vivado schematic
- svg schematic
- Custom ip block
- AXIS interface
- Creating a custom IP
- Integrate IP and interface (make connections)
- How to use the xdc + link xdc
- Synth, Impl, Bitstream (.bin version, remember to check the setting option)
- Create the C app to use DMA
- Integrate the interface for AES256
- MDC backend MDC compatible with UltraScale+
Profiling on the software part of the Sopil Segmentation heterogeneous system to decide what to implement for FPGA and what not.
- Running the software code on UltraScale+
- Behavioural test on PC
- Timing test on PC
- Behavioural test on UltraScale+
- Timing test on UltraScale+
- Latencies table of the different parts
- Identification of critical parts
The critical part should be the median filter.
- Extract the algorithm of Python function and make a C working implementation
- Hardware implementation
App integration on the UltraScale+
- Reading camera integration (Software management)
- Depending on the application chosen, comparison of the image cores genrated by bitbake --> table of the different implementations: What changes? Why?