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drm/vc4: Disable the 2pixel/clock odd timings workaround for interlaced
Whilst BCM2712 does fix using odd horizontal timings, it doesn't work with interlaced modes. Drop the workaround for interlaced modes and revert to the same behaviour as BCM2711. #6281 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
1 parent e1f3c92 commit b034113

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4 files changed

+30
-4
lines changed

4 files changed

+30
-4
lines changed

‎drivers/gpu/drm/vc4/vc4_crtc.c

+17-3
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,9 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
361361
bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
362362
bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
363363
u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
364-
u8 ppc = pv_data->pixels_per_clock;
364+
u8 ppc = (mode->flags & DRM_MODE_FLAG_INTERLACE) ?
365+
pv_data->pixels_per_clock_int :
366+
pv_data->pixels_per_clock;
365367

366368
u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
367369
u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
@@ -426,7 +428,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
426428
*/
427429
CRTC_WRITE(PV_V_CONTROL,
428430
PV_VCONTROL_CONTINUOUS |
429-
(vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |
431+
(vc4->gen >= VC4_GEN_6_C && ppc == 1 ?
432+
PV_VCONTROL_ODD_TIMING : 0) |
430433
(is_dsi ? PV_VCONTROL_DSI : 0) |
431434
PV_VCONTROL_INTERLACE |
432435
(odd_field_first
@@ -438,7 +441,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
438441
} else {
439442
CRTC_WRITE(PV_V_CONTROL,
440443
PV_VCONTROL_CONTINUOUS |
441-
(vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |
444+
(vc4->gen >= VC4_GEN_6_C && ppc == 1 ?
445+
PV_VCONTROL_ODD_TIMING : 0) |
442446
(is_dsi ? PV_VCONTROL_DSI : 0));
443447
CRTC_WRITE(PV_VSYNCD_EVEN, 0);
444448
}
@@ -1208,6 +1212,7 @@ const struct vc4_pv_data bcm2835_pv0_data = {
12081212
},
12091213
.fifo_depth = 64,
12101214
.pixels_per_clock = 1,
1215+
.pixels_per_clock_int = 1,
12111216
.encoder_types = {
12121217
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
12131218
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
@@ -1223,6 +1228,7 @@ const struct vc4_pv_data bcm2835_pv1_data = {
12231228
},
12241229
.fifo_depth = 64,
12251230
.pixels_per_clock = 1,
1231+
.pixels_per_clock_int = 1,
12261232
.encoder_types = {
12271233
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
12281234
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
@@ -1238,6 +1244,7 @@ const struct vc4_pv_data bcm2835_pv2_data = {
12381244
},
12391245
.fifo_depth = 64,
12401246
.pixels_per_clock = 1,
1247+
.pixels_per_clock_int = 1,
12411248
.encoder_types = {
12421249
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
12431250
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
@@ -1253,6 +1260,7 @@ const struct vc4_pv_data bcm2711_pv0_data = {
12531260
},
12541261
.fifo_depth = 64,
12551262
.pixels_per_clock = 1,
1263+
.pixels_per_clock_int = 1,
12561264
.encoder_types = {
12571265
[0] = VC4_ENCODER_TYPE_DSI0,
12581266
[1] = VC4_ENCODER_TYPE_DPI,
@@ -1268,6 +1276,7 @@ const struct vc4_pv_data bcm2711_pv1_data = {
12681276
},
12691277
.fifo_depth = 64,
12701278
.pixels_per_clock = 1,
1279+
.pixels_per_clock_int = 1,
12711280
.encoder_types = {
12721281
[0] = VC4_ENCODER_TYPE_DSI1,
12731282
[1] = VC4_ENCODER_TYPE_SMI,
@@ -1283,6 +1292,7 @@ const struct vc4_pv_data bcm2711_pv2_data = {
12831292
},
12841293
.fifo_depth = 256,
12851294
.pixels_per_clock = 2,
1295+
.pixels_per_clock_int = 2,
12861296
.encoder_types = {
12871297
[0] = VC4_ENCODER_TYPE_HDMI0,
12881298
},
@@ -1297,6 +1307,7 @@ const struct vc4_pv_data bcm2711_pv3_data = {
12971307
},
12981308
.fifo_depth = 64,
12991309
.pixels_per_clock = 1,
1310+
.pixels_per_clock_int = 1,
13001311
.encoder_types = {
13011312
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
13021313
},
@@ -1311,6 +1322,7 @@ const struct vc4_pv_data bcm2711_pv4_data = {
13111322
},
13121323
.fifo_depth = 64,
13131324
.pixels_per_clock = 2,
1325+
.pixels_per_clock_int = 2,
13141326
.encoder_types = {
13151327
[0] = VC4_ENCODER_TYPE_HDMI1,
13161328
},
@@ -1324,6 +1336,7 @@ const struct vc4_pv_data bcm2712_pv0_data = {
13241336
},
13251337
.fifo_depth = 64,
13261338
.pixels_per_clock = 1,
1339+
.pixels_per_clock_int = 2,
13271340
.encoder_types = {
13281341
[0] = VC4_ENCODER_TYPE_HDMI0,
13291342
},
@@ -1337,6 +1350,7 @@ const struct vc4_pv_data bcm2712_pv1_data = {
13371350
},
13381351
.fifo_depth = 64,
13391352
.pixels_per_clock = 1,
1353+
.pixels_per_clock_int = 2,
13401354
.encoder_types = {
13411355
[0] = VC4_ENCODER_TYPE_HDMI1,
13421356
},

‎drivers/gpu/drm/vc4/vc4_drv.h

+2
Original file line numberDiff line numberDiff line change
@@ -568,6 +568,8 @@ struct vc4_pv_data {
568568

569569
/* Number of pixels output per clock period */
570570
u8 pixels_per_clock;
571+
/* Number of pixels output per clock period when in an interlaced mode */
572+
u8 pixels_per_clock_int;
571573

572574
enum vc4_encoder_type encoder_types[4];
573575
};

‎drivers/gpu/drm/vc4/vc4_hdmi.c

+7-1
Original file line numberDiff line numberDiff line change
@@ -1737,7 +1737,9 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
17371737
unsigned long long tmds_char_rate = mode->clock * 1000;
17381738
unsigned long long tmds_bit_rate;
17391739

1740-
if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1740+
if (vc4_hdmi->variant->unsupported_odd_h_timings ||
1741+
(vc4_hdmi->variant->unsupported_int_odd_h_timings &&
1742+
(mode->flags & DRM_MODE_FLAG_INTERLACE))) {
17411743
if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
17421744
/* Only try to fixup DBLCLK modes to get 480i and 576i
17431745
* working.
@@ -3368,6 +3370,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
33683370
PHY_LANE_CK,
33693371
},
33703372
.unsupported_odd_h_timings = true,
3373+
.unsupported_int_odd_h_timings = true,
33713374
.external_irq_controller = true,
33723375

33733376
.init_resources = vc5_hdmi_init_resources,
@@ -3397,6 +3400,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
33973400
PHY_LANE_2,
33983401
},
33993402
.unsupported_odd_h_timings = true,
3403+
.unsupported_int_odd_h_timings = true,
34003404
.external_irq_controller = true,
34013405

34023406
.init_resources = vc5_hdmi_init_resources,
@@ -3426,6 +3430,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
34263430
PHY_LANE_CK,
34273431
},
34283432
.unsupported_odd_h_timings = false,
3433+
.unsupported_int_odd_h_timings = true,
34293434
.external_irq_controller = true,
34303435

34313436
.init_resources = vc5_hdmi_init_resources,
@@ -3453,6 +3458,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
34533458
PHY_LANE_CK,
34543459
},
34553460
.unsupported_odd_h_timings = false,
3461+
.unsupported_int_odd_h_timings = true,
34563462
.external_irq_controller = true,
34573463

34583464
.init_resources = vc5_hdmi_init_resources,

‎drivers/gpu/drm/vc4/vc4_hdmi.h

+4
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,10 @@ struct vc4_hdmi_variant {
4646

4747
/* The BCM2711 cannot deal with odd horizontal pixel timings */
4848
bool unsupported_odd_h_timings;
49+
/* The BCM2712 can handle odd horizontal pixel timings, but not in
50+
* interlaced modes
51+
*/
52+
bool unsupported_int_odd_h_timings;
4953

5054
/*
5155
* The BCM2711 CEC/hotplug IRQ controller is shared between the

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