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.gitignore
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# Object files
*.o
*.ko
*.obj
*.elf
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
*.pyc
# Debug files
*.dSYM/
*.pyc
*.pyc
/sim/verilog/*.bin
/sim/verilog/*.vmem
/sim/verilog/*.vmem32
/sim/verilog/*.lst
/sim/verilog/*.hex
/sim/verilog/*.hex2
/sim/verilog/*.log
/sim/verilog/*.map
/synt/fpga/*.jou
/sim/verilog/gpio_toggle_infinite.bit
/sim/verilog/rv32ui.regression.txt
/sim/verilog/tb_nanorv32.vcd
/sim/verilog/test.S
/sim/verilog/webtalk.jou
/sim/verilog/webtalk_5746.backup.jou
/sim/verilog/work.tb_nanorv32#work.glbl.wdb
/sim/verilog/xelab.pb
/sim/verilog/xsim.dir/
/sim/verilog/xsim.jou
/sim/verilog/xsim_5811.backup.jou
/sim/verilog/xsim_6785.backup.jou
/sim/verilog/xsim_6945.backup.jou
/sim/verilog/xvlog.pb
/synt/fpga/.Xil/
/synt/fpga/chip_layout.sdf
/synt/fpga/chip_layout.v
/synt/fpga/cortexm0.mmi
/synt/fpga/debug.txt
/synt/fpga/fsm_encoding.os
/synt/fpga/post_opt_loops.rpt
/synt/fpga/post_place_loops.rpt
/synt/fpga/post_synt_loops.rpt
/synt/fpga/rpt/clock_util.rpt
/synt/fpga/rpt/post_imp_drc.rpt
/synt/fpga/rpt/post_place.dcp
/synt/fpga/rpt/post_place_timing_summary.rpt
/synt/fpga/rpt/post_place_util.rpt
/synt/fpga/rpt/post_route.dcp
/synt/fpga/rpt/post_route_power.rpt
/synt/fpga/rpt/post_route_status.rpt
/synt/fpga/rpt/post_route_timing_summary.rpt
/synt/fpga/test.mmi
/synt/fpga/test2.mmi
/synt/fpga/updatemem.log
/synt/fpga/updatemem_16710.backup.log
/synt/fpga/vivado_13254.backup.log
/synt/fpga/vivado_15944.backup.log
/synt/fpga/vivado_20197.backup.log
/synt/fpga/vivado_20483.backup.log
/synt/fpga/vivado_22337.backup.log
/synt/fpga/vivado_pid16852.str
/ctests/gpio_toggle/Makefile
/ctests/gpio_toggle/gpio_toggle.bin
/ctests/gpio_toggle/gpio_toggle.hex2
/ctests/gpio_toggle/gpio_toggle.lst
/ctests/gpio_toggle/gpio_toggle.map
/ctests/gpio_toggle/gpio_toggle.vmem
/ctests/gpio_toggle/gpio_toggle.vmem32
/ctests/printk/Makefile
/ctests/printk/printk.bin
/ctests/printk/printk.hex2
/ctests/printk/printk.lst
/ctests/printk/printk.map
/ctests/printk/printk.vmem
/ctests/printk/printk.vmem32
/ctests/gpio_toggle/trace.txt
/ctests/printk/trace.txt
ctests/*/*.log
ctests/*/*.jou
ctests/*/xvlog.pb
ctests/*/xsim.dir
ctests/*/xelab.pb
ctests/*/work.tb_nanorv32#work.glbl.wdb
ctests/*/*.vmem
ctests/*/*.vmem2
ctests/*/*.hex
ctests/*/*.hex2
ctests/*/*.lst
ctests/*/*.map
/ctests/uart_simple/Makefile
/ctests/uart_simple/iverilog_file_list.txt
/ctests/uart_simple/tb_nanorv32.vcd
/ctests/uart_simple/trace.txt
/ctests/uart_simple/uart_simple.bin
/ctests/uart_simple/uart_simple.vmem32
*~
*.vcd
/ctests/gpio_toggle/iverilog_file_list.txt
/*.ihex