Cannot translate literal to SMT: undefined : %bv

[fahadausaf]

This compilation error occurred when trying to generate System Verilog code for Arm LDR(Literal) instruction. I am using the release version of the sail compiler

Also note that I commented out parts of the code where the following line of code was used as it was generating endianness related issue reported here #884

overload BigEndianReverse = {reverse_endianness}