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Bender.yml
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# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: snitch_cluster
authors:
- Florian Zaruba <zarubaf@iis.ee.ethz.ch>
- Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
- Paul Scheffler <paulsc@iis.ee.ethz.ch> # current maintainer
- Thomas Benz <tbenz@iis.ee.ethz.ch>
- Gianna Paulin <pauling@iis.ee.ethz.ch>
- Tim Fischer <fischeti@iis.ee.ethz.ch>
- Noah Huetter <huettern@ethz.ch>
- Luca Colagrande <colluca@iis.ee.ethz.ch>
- Samuel Riedel <sriedel@iis.ee.ethz.ch>
- Nils Wistoff <nwistoff@iis.ee.ethz.ch>
- Luca Bertaccini <lbertaccini@iis.ee.ethz.ch>
- Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
dependencies:
axi: { git: https://github.com/pulp-platform/axi, version: 0.39.0-beta.4 }
axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics, version: 0.6.0 }
common_cells: { git: https://github.com/pulp-platform/common_cells, version: 1.28.0 }
FPnew: { git: https://github.com/openhwgroup/cvfpu, rev: 1202ca3 } # TODO: Update to next release
register_interface: { git: https://github.com/pulp-platform/register_interface, version: 0.3.3 }
tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version: 0.2.11 }
riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg, rev: ec0d92fa5fdaaf611e5b8a4cc8ee84017ff98710 }
# Note: used to vendor-in the musl sources, but cannot be used consistently
# until this issue is solved https://github.com/pulp-platform/bender/issues/133
vendor_package:
- name: musl
target_dir: sw/math
upstream: { git: https://github.com/kraj/musl.git, rev: 7a43f6fea9081bdd53d8a11cef9e9fab0348c53d } # v1.2.4
patch_dir: sw/deps/patches/musl
include_from_upstream:
- "COPYRIGHT"
- "Makefile"
- ".gitignore"
- "README"
- "src/math/tanh.c"
- "src/math/expm1.c"
- "src/internal/libm.h"
- "src/include/features.h"
- "include/endian.h"
- "include/math.h"
- "include/features.h"
- "include/alltypes.h.in"
- "arch/riscv64/bits/alltypes.h.in"
- "arch/riscv64/bits/float.h"
- "tools/mkalltypes.sed"
- "arch/generic/fp_arch.h"
export_include_dirs:
- hw/reqrsp_interface/include
- hw/mem_interface/include
- hw/tcdm_interface/include
- hw/snitch/include
- hw/snitch_ssr/include
sources:
# future
- files:
# Level 0
- hw/future/src/mem_to_axi_lite.sv
- hw/future/src/idma_reg64_frontend_reg_pkg.sv
- hw/future/src/idma_tf_id_gen.sv
- hw/future/src/dma/axi_dma_data_path.sv
- hw/future/src/axi_interleaved_xbar.sv
# Level 1
- hw/future/src/axi_zero_mem.sv
- hw/future/src/idma_reg64_frontend_reg_top.sv
# Level 2
- hw/future/src/idma_reg64_frontend.sv
- hw/future/src/dma/axi_dma_data_mover.sv
- hw/future/src/dma/axi_dma_burst_reshaper.sv
# Level 3
- hw/future/src/dma/axi_dma_backend.sv
- target: test
files:
- hw/future/test/fixture_axi_dma_backend.sv
- hw/future/test/tb_axi_dma_backend.sv
# reqrsp_interface
- files:
# Level 0
- hw/reqrsp_interface/src/reqrsp_pkg.sv
# Level 1
- hw/reqrsp_interface/src/reqrsp_intf.sv
# Level 2
- hw/reqrsp_interface/src/axi_to_reqrsp.sv
- hw/reqrsp_interface/src/reqrsp_cut.sv
- hw/reqrsp_interface/src/reqrsp_demux.sv
- hw/reqrsp_interface/src/reqrsp_iso.sv
- hw/reqrsp_interface/src/reqrsp_mux.sv
- hw/reqrsp_interface/src/reqrsp_to_axi.sv
- target: simulation
files:
- hw/reqrsp_interface/src/reqrsp_test.sv
- target: test
files:
- hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv
- hw/reqrsp_interface/test/reqrsp_demux_tb.sv
- hw/reqrsp_interface/test/reqrsp_idempotent_tb.sv
- hw/reqrsp_interface/test/reqrsp_mux_tb.sv
- hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv
# mem_interface
- files:
- hw/mem_interface/src/mem_wide_narrow_mux.sv
- hw/mem_interface/src/mem_interface.sv
- target: simulation
files:
- hw/mem_interface/src/mem_test.sv
- target: test
files:
- hw/mem_interface/test/mem_wide_narrow_mux_tb.sv
# tcdm_interface
- files:
# Level 0
- hw/tcdm_interface/src/tcdm_interface.sv
# Level 1
- hw/tcdm_interface/src/axi_to_tcdm.sv
- hw/tcdm_interface/src/reqrsp_to_tcdm.sv
- hw/tcdm_interface/src/tcdm_mux.sv
- target: simulation
files:
- hw/tcdm_interface/src/tcdm_test.sv
- target: test
files:
- hw/tcdm_interface/test/reqrsp_to_tcdm_tb.sv
- hw/tcdm_interface/test/tcdm_mux_tb.sv
# snitch
- files:
# Level 0
- hw/snitch/src/snitch_pma_pkg.sv
- hw/snitch/src/riscv_instr.sv
# Level 1
- hw/snitch/src/snitch_pkg.sv
# Level 2
- hw/snitch/src/snitch_regfile_ff.sv
- hw/snitch/src/snitch_lsu.sv
- hw/snitch/src/snitch_l0_tlb.sv
- target: not(disable_pmcs)
defines:
SNITCH_ENABLE_PERF:
files:
- hw/snitch/src/snitch.sv
# Disable the performance monitoring counters to save area.
- target: disable_pmcs
files:
- hw/snitch/src/snitch.sv
- target: test
files:
- hw/snitch/test/snitch_l0_tlb_tb.sv
# snitch_vm
- files:
- hw/snitch_vm/src/snitch_ptw.sv
# snitch_dma
- files:
# Level 0
- hw/snitch_dma/src/axi_dma_pkg.sv
# Level 1
- hw/snitch_dma/src/axi_dma_error_handler.sv
- hw/snitch_dma/src/axi_dma_perf_counters.sv
- hw/snitch_dma/src/axi_dma_twod_ext.sv
# Level 2:
- hw/snitch_dma/src/axi_dma_tc_snitch_fe.sv
# snitch_icache
- files:
# Level 0
- hw/snitch_icache/src/snitch_icache_pkg.sv
# Level 1
- hw/snitch_icache/src/snitch_icache_l0.sv
- hw/snitch_icache/src/snitch_icache_refill.sv
- hw/snitch_icache/src/snitch_icache_lfsr.sv
- hw/snitch_icache/src/snitch_icache_lookup.sv
# Level 2
- hw/snitch_icache/src/snitch_icache_handler.sv
# Level 3
- hw/snitch_icache/src/snitch_icache.sv
- target: test
files:
- hw/snitch_icache/test/snitch_icache_l0_tb.sv
# snitch_ipu
- files:
# Level 0
- hw/snitch_ipu/src/snitch_ipu_pkg.sv
# Level 1
- hw/snitch_ipu/src/snitch_ipu_alu.sv
# Level 2
- hw/snitch_ipu/src/snitch_int_ss.sv
# snitch_ssr
- files:
# Level 0
- hw/snitch_ssr/src/snitch_ssr_pkg.sv
- hw/snitch_ssr/src/snitch_ssr_switch.sv
- hw/snitch_ssr/src/snitch_ssr_credit_counter.sv
# Level 1
- hw/snitch_ssr/src/snitch_ssr_indirector.sv
- hw/snitch_ssr/src/snitch_ssr_intersector.sv
# Level 2
- hw/snitch_ssr/src/snitch_ssr_addr_gen.sv
# Level 3
- hw/snitch_ssr/src/snitch_ssr.sv
# Level 4
- hw/snitch_ssr/src/snitch_ssr_streamer.sv
- target: test
files:
# Level 0
- hw/snitch_ssr/test/fixture_ssr.sv
- hw/snitch_ssr/test/fixture_ssr_streamer.sv
# Level 1
- hw/snitch_ssr/test/tb_simple_ssr.sv
- hw/snitch_ssr/test/tb_simple_ssr_streamer.sv
# snitch_cluster
- files:
# Level 0
- hw/snitch_cluster/src/snitch_amo_shim.sv
- hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv
- hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv
- hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv
- hw/snitch_cluster/src/snitch_fpu.sv
- hw/snitch_cluster/src/snitch_sequencer.sv
- hw/snitch_cluster/src/snitch_tcdm_interconnect.sv
# Level 1
- hw/snitch_cluster/src/snitch_barrier.sv
- hw/snitch_cluster/src/snitch_fp_ss.sv
- hw/snitch_cluster/src/snitch_shared_muldiv.sv
# Level 2
- hw/snitch_cluster/src/snitch_cc.sv
- hw/snitch_cluster/src/snitch_clkdiv2.sv
# Level 3
- hw/snitch_cluster/src/snitch_hive.sv
# Level 4
- hw/snitch_cluster/src/snitch_cluster.sv
- target: test
files:
- hw/snitch_cluster/test/snitch_tcdm_interconnect_tb.sv
# target/common
- target: any(simulation, verilator)
files:
- target/common/test/tb_memory_regbus.sv
- target/common/test/tb_memory_axi.sv
- target: test
files:
- target/common/test/tb_bin.sv
# target/snitch_cluster
- target: snitch_cluster
files:
- target/snitch_cluster/generated/snitch_cluster_wrapper.sv
- target: all(snitch_cluster, any(simulation, verilator))
files:
- target/snitch_cluster/test/testharness.sv