2023-10-02

What's Changed

• A-ext chapter: 64-bit word => doubleword; 32-bit word => word by @ved-rivos in #1052
• fix satp.asid width by @nananapo in #1055
• Fix format errors in c-st-ext.adoc by @nananapo in #1058
• Change "Reserved" to "Designated" in RVC HINT instructions table by @nananapo in #1059
• Update reg-based-ldnstr.adoc by @tariqkurd-repo in #1066
• fix missing " in misa description by @nananapo in #1065
• fix formatting by @tariqkurd-repo in #1069
• Make "Conditional Branches" wavdrom consistent by @charlie-rivos in #1071
• Correct Name of LR/SC Instructions rl bit by @charlie-rivos in #1073
• Make "Integer Register-Immediate Operations" Consistent by @charlie-rivos in #1072
• Resolve incorrect formatting in CS format by @charlie-rivos in #1074
• priv-1.13: clarify that MXLEN >= SXLEN; constrain SXLEN >= UXLEN by @aswaterman in #1028
• Zmmul is now version 1.0 (ratified) by @a4lg in #1077
• C.XOR is not RV64/RV128 only by @a4lg in #1076
• Fix C.ADDI16SP immediate by @charlie-rivos in #1079
• Counters are now ratified (with version 2.0) by @a4lg in #1083
• Add *.html to build/.gitignore by @a4lg in #1089
• Add *.pdf.tmp to build/.gitignore by @a4lg in #1091
• Mark Zfa as Frozen and Version 1.0 by @palmer-dabbelt in #1096
• Update supervisor.adoc by @tariqkurd-repo in #1101
• Update f-st-ext.adoc by @fourcolor in #1106
• Add OP-V to base opcode map (AsciiDoc port) by @a4lg in #1118
• Clarify ordering rules when PBMT=IO is used on main-memory regions by @aswaterman in #1112
• Add missing words by @KubaO in #1122
• Clarify REM wording by @hdelassus in #1123
• apply compression for adoc pdf outputs by @jnk0le in #1125
• Fix MIE register bitfield caption by @KubaO in #1126
• update marchid.md for cve2 by @davideschiavone in #1130
• Standardize on no hyphen in illegal instruction exception by @aswaterman in #1131
• Hyphenate "virtual-/illegal-instruction exception" by @aswaterman in #1133
• M implies Zmmul by @nick-knight in #1121
• Don't describe WFI as a hint by @aswaterman in #1107
• Allow Misaligned Stores with Page Fault to partially succeed by @ingallsj in #1119
• Fix typos by @kianmeng in #1136

New Contributors

• @nananapo made their first contribution in #1055
• @charlie-rivos made their first contribution in #1071
• @fourcolor made their first contribution in #1106
• @KubaO made their first contribution in #1122
• @hdelassus made their first contribution in #1123
• @jnk0le made their first contribution in #1125
• @kianmeng made their first contribution in #1136

Full Changelog: riscv-isa-release-1239329-2023-05-23...2023-10-02

2023-05-23

This release was created by: rpsene
Release Notes: 2023-05-23

2023-04-27

This release was created by: wmat
Release Notes: First release after unpriv move to asciidoc src.

Release for riscv-privileged-449cd0c.pdf and riscv-spec-449cd0c.pdf

isa-449cd0c

Release for riscv-privileged-449cd0c.pdf and riscv-spec-449cd0c.pdf

Unprivileged ISA PDF from asciidoc 11152022

What's Changed

• zihintpause: Annotate notes and correct instruction encoding by @adurbin-rivos in #746
• riscv-isa-unpriv.adoc by @ved-rivos in #749
• Improvements to Intro and RV32I chapters by @aswaterman in #750
• unpriv-chapter-12 by @ved-rivos in #751
• Various RVWMO adoc fixes by @daniellustig in #753
• Chapter 24 - Extending by @ved-rivos in #754
• Chapter 23 : RV32/64G Instruction Set Listings by @ved-rivos in #755
• Fix labels for bits 25 and 26, clean up wavedrom file by @hbrausen in #775
• Add yaml file for build automation by @cetola in #801
• Pulling master changes into riscv-isa-branch by @wmat in #912
• Add marchid for Fraunhofer-IMS AIRISC (#913) by @wmat in #914

New Contributors

• @adurbin-rivos made their first contribution in #746
• @ved-rivos made their first contribution in #749
• @hbrausen made their first contribution in #775
• @wmat made their first contribution in #912

Full Changelog: draft-20221110-33c63c7...riscv-unpriv-pdf-from-asciidoc-15112022

Privileged Architecture v1.12, Ratified

This release, version 20211203, contains the following ratified versions of these RISC-V ISA modules:

• Machine ISA, v1.12
• Supervisor ISA, v1.12
• Svnapot extension, v1.0
• Svpbmt extension, v1.0
• Svinval extension, v1.0
• Hypervisor ISA, v1.0

RISC-V Privileged Architecture, version 20210915-Public-Review-draftn

This is a draft of the RISC-V Privileged Architecture for public review of version 1.12 of the Machine and Supervisor modules and Version 1.0 of the Hypervisor module.

Draft of Zihintpause extension for public review

zihintpause-public-review-draft-20201013

Update zihintpause.tex

Ratified versions of the RV32I and RV64I base ISAs and MAFDQC standard extensions

Main change in this release is that the A extension, v2.1, has been ratified.

RISC-V Specification Archive

This is an archive of older versions of the RISC-V specifications.

These specifications are out of date! For the most recent ratified versions of the spec, please click here. For the most recent unratified drafts, please click here.

Note that these archived PDFs are static artifacts, and the source code to rebuild them is not included as part of this release.