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Should we push armv8r-none-eabihf to Tier 2?The https://doc.rust-lang.org/nightly/rustc/target-tier-policy.html#tier-2-target-policy says:
It is of value to people who want to play with Armv8-R architecture in QEMU, or program one of a number of upcoming SoCs that use that architecture.
I propose that the EDWG Arm Team would be the maintainers, although https://doc.rust-lang.org/nightly/rustc/platform-support/armv8r-none-eabihf.html says it is currently Chris Copeland. If Arm wants to contribute here, they can join the team.
I find it hard to imagine something that a Rust project contributor might break in armv8r-none-eabihf but that doesn't also break armv7r-none-eabihf (which is Tier 2). So the additional burden seems low.
https://doc.rust-lang.org/nightly/rustc/platform-support/armv8r-none-eabihf.html exists already.
Unclear where this is documented, but it doesn't seem to be a problem given that only two processors (Cortex-R52 and Cortex-R52+) implement the architecture currently.
It's an updated revision of the Architecture, and that warrants a new target (see the M-Profile targets).
It does not, AFAIK.
It does not, AFAIK.
It does.
It does in Ferrocene.
They do in Ferrocene.
It should be the same as armv7r-none-eabihf, and being no_std, it doesn't take long.
It's a cross-compiled target.
Pretty sure it is no different to armv7r-none-eabihf in this regard.
Pretty sure it is no different to armv7r-none-eabihf in this regard.
TIL! |
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New Arm Team member: #831 |
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@jonathanpallant and I (totally separately!) are making appearances this week, and are looking for "where has embedded rust been shipped?" I have a running list here: https://bsky.app/profile/did:plc:rqm4qgf6jdmb35mxatuzi6cq/post/3lmajebv2n22u, if anyone is aware of other good public cases, happy to have them! I plan to make a blog post afterwards to save others the trouble from hunting for presentations, press items, etc. |
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This is the agenda for the next meeting. Please add anything you'd like to discuss below!
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