Skip to content

Commit a9887d1

Browse files
lu-zeroAmanieu
authored andcommitted
Add vec_sel
1 parent 1940d10 commit a9887d1

File tree

1 file changed

+120
-0
lines changed

1 file changed

+120
-0
lines changed

crates/core_arch/src/powerpc/altivec.rs

+120
Original file line numberDiff line numberDiff line change
@@ -478,6 +478,15 @@ macro_rules! t_t_s {
478478
}
479479

480480
macro_rules! t_u {
481+
(vector_bool_char) => {
482+
vector_unsigned_char
483+
};
484+
(vector_bool_short) => {
485+
vector_unsigned_short
486+
};
487+
(vector_bool_int) => {
488+
vector_unsigned_int
489+
};
481490
(vector_unsigned_char) => {
482491
vector_unsigned_char
483492
};
@@ -496,6 +505,42 @@ macro_rules! t_u {
496505
(vector_signed_int) => {
497506
vector_unsigned_int
498507
};
508+
(vector_float) => {
509+
vector_unsigned_int
510+
};
511+
}
512+
513+
macro_rules! t_b {
514+
(vector_bool_char) => {
515+
vector_bool_char
516+
};
517+
(vector_bool_short) => {
518+
vector_bool_short
519+
};
520+
(vector_bool_int) => {
521+
vector_bool_int
522+
};
523+
(vector_signed_char) => {
524+
vector_bool_char
525+
};
526+
(vector_signed_short) => {
527+
vector_bool_short
528+
};
529+
(vector_signed_int) => {
530+
vector_bool_int
531+
};
532+
(vector_unsigned_char) => {
533+
vector_bool_char
534+
};
535+
(vector_unsigned_short) => {
536+
vector_bool_short
537+
};
538+
(vector_unsigned_int) => {
539+
vector_bool_int
540+
};
541+
(vector_float) => {
542+
vector_bool_int
543+
};
499544
}
500545

501546
macro_rules! impl_from {
@@ -2572,6 +2617,62 @@ mod sealed {
25722617

25732618
impl_vec_trait! { [VectorNand vec_nand]+ 2b (vec_vnandsb, vec_vnandsh, vec_vnandsw) }
25742619

2620+
#[inline]
2621+
#[target_feature(enable = "altivec")]
2622+
#[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vsel))]
2623+
#[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxsel))]
2624+
pub unsafe fn vec_vsel(
2625+
a: vector_signed_char,
2626+
b: vector_signed_char,
2627+
c: vector_signed_char,
2628+
) -> vector_signed_char {
2629+
let a: i8x16 = transmute(a);
2630+
let b: i8x16 = transmute(b);
2631+
let c: i8x16 = transmute(c);
2632+
let not_c = simd_xor(c, i8x16::splat(!0));
2633+
2634+
transmute(simd_or(simd_and(a, not_c), simd_and(b, c)))
2635+
}
2636+
2637+
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
2638+
pub trait VectorSel<Mask> {
2639+
unsafe fn vec_sel(self, b: Self, c: Mask) -> Self;
2640+
}
2641+
2642+
macro_rules! vector_sel {
2643+
($ty: ty, $m: ty) => {
2644+
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
2645+
impl VectorSel<$m> for $ty {
2646+
#[inline]
2647+
#[target_feature(enable = "altivec")]
2648+
unsafe fn vec_sel(self, b: Self, c: $m) -> Self {
2649+
let a = transmute(self);
2650+
let b = transmute(b);
2651+
let c = transmute(c);
2652+
2653+
transmute(vec_vsel(a, b, c))
2654+
}
2655+
}
2656+
};
2657+
($ty: ident) => {
2658+
vector_sel! { $ty, t_b!{ $ty } }
2659+
vector_sel! { $ty, t_u!{ $ty } }
2660+
vector_sel! { t_u!{ $ty }, t_b!{ $ty } }
2661+
vector_sel! { t_u!{ $ty }, t_u!{ $ty } }
2662+
vector_sel! { t_b!{ $ty }, t_b!{ $ty } }
2663+
vector_sel! { t_b!{ $ty }, t_u!{ $ty } }
2664+
};
2665+
(- $ty: ident) => {
2666+
vector_sel! { $ty, t_b!{ $ty } }
2667+
vector_sel! { $ty, t_u!{ $ty } }
2668+
};
2669+
}
2670+
2671+
vector_sel! { vector_signed_char }
2672+
vector_sel! { vector_signed_short }
2673+
vector_sel! { vector_signed_int }
2674+
vector_sel! {- vector_float }
2675+
25752676
#[inline]
25762677
#[target_feature(enable = "altivec")]
25772678
#[cfg_attr(test, assert_instr(vcfsx, IMM5 = 1))]
@@ -4188,6 +4289,25 @@ pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> ve
41884289
vnmsubfp(a, b, c)
41894290
}
41904291

4292+
/// Vector Select
4293+
///
4294+
/// ## Purpose
4295+
/// Returns a vector selecting bits from two source vectors depending on the corresponding
4296+
/// bit values of a third source vector.
4297+
///
4298+
/// ## Result value
4299+
/// Each bit of r has the value of the corresponding bit of a if the corresponding
4300+
/// bit of c is 0. Otherwise, the bit of r has the value of the corresponding bit of b.
4301+
#[inline]
4302+
#[target_feature(enable = "altivec")]
4303+
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
4304+
pub unsafe fn vec_sel<T, U>(a: T, b: T, c: U) -> T
4305+
where
4306+
T: sealed::VectorSel<U>,
4307+
{
4308+
a.vec_sel(b, c)
4309+
}
4310+
41914311
/// Vector Sum Across Partial (1/4) Saturated
41924312
#[inline]
41934313
#[target_feature(enable = "altivec")]

0 commit comments

Comments
 (0)