From 566fad8c14fd738a02d44f421e51b71e03d6b105 Mon Sep 17 00:00:00 2001 From: Saurabh Singh Date: Sun, 10 Mar 2024 15:51:31 -0400 Subject: [PATCH] xmsend: Fix FPGA interbyte delay --- scripts/xmsend.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/xmsend.py b/scripts/xmsend.py index e3f43023..c6ecb07c 100644 --- a/scripts/xmsend.py +++ b/scripts/xmsend.py @@ -8,7 +8,7 @@ InterByteDelay_simt = 0.2 # SIM_WITH_TRACE: simulation with trace InterByteDelay_sim = 0.005 # NORMAL SIM: 0.001 works, for safety we chose this -InterByteDelay_fpga = 0.001 # FPGA +InterByteDelay_fpga = 0 # FPGA InterByteDelay = 0