-
Notifications
You must be signed in to change notification settings - Fork 2
/
z80.c
1285 lines (1192 loc) · 30.5 KB
/
z80.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* Copyright (c) 2008, 2017 Stephen Checkoway
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <string.h>
#include <assert.h>
#include <zel/z80.h>
#include <zel/z80_instructions.h>
#include "z80_types.h"
struct Z80_t
{
/* C guarantees consecutive layout */
word word_reg[13];
byte *byte_reg;
bool iff1;
bool iff2;
bool can_handle_interrupt;
int interrupt_mode;
bool interrupt;
bool nmi;
bool halt;
bool restart_io;
byte (*ReadMem)(word, bool, Z80);
void (*WriteMem)(word, byte, Z80);
byte (*ReadInterruptData)(word, Z80);
byte (*ReadIO)(word, Z80);
void (*WriteIO)(word, byte, Z80);
void (*InterruptComplete)(Z80);
void (*ControlFlow)(word, word, ControlFlowType, Z80);
};
// short cuts
#define WORD_REG (cpu->word_reg)
#define BYTE_REG (cpu->byte_reg)
#define SP (cpu->word_reg[REG_SP])
#define PC (cpu->word_reg[REG_PC])
#define PCH (cpu->byte_reg[REG_PCH])
#define PCL (cpu->byte_reg[REG_PCL])
#define BC (cpu->word_reg[REG_BC])
#define DE (cpu->word_reg[REG_DE])
#define HL (cpu->word_reg[REG_HL])
#define AF (cpu->word_reg[REG_AF])
#define B (cpu->byte_reg[REG_B])
#define C (cpu->byte_reg[REG_C])
#define D (cpu->byte_reg[REG_D])
#define E (cpu->byte_reg[REG_E])
#define H (cpu->byte_reg[REG_H])
#define L (cpu->byte_reg[REG_L])
#define A (cpu->byte_reg[REG_A])
#define FlagIsSet(f) (!FlagIsReset((f)))
#define FlagIsReset(f) (!(cpu->byte_reg[REG_F]&(1<<(f))))
#define SetFlag(f) (void)(cpu->byte_reg[REG_F]|=(1<<(f)))
#define ResetFlag(f) (void)(cpu->byte_reg[REG_F]&=~(1<<(f)))
#define SetFlagValue(f,v) \
(void)(cpu->byte_reg[REG_F] = (cpu->byte_reg[REG_F] & ~(1<<(f))) | (!!(v)<<(f)))
#define CondIsMet(c) ( ((c)>=0 && FlagIsSet((c))) || ((c)<0 && FlagIsReset(-(c+1))) )
void IgnoreControlFlow( word pc, word target, ControlFlowType cf, Z80 cpu ) { }
Z80 Z80_New( const Z80FunctionBlock *blk )
{
Z80 cpu = malloc( sizeof(struct Z80_t) );
assert( cpu != NULL );
memset( cpu, 0, sizeof(struct Z80_t) );
cpu->byte_reg = (byte*)cpu->word_reg;
SP = 0xffff;
AF = 0xffff;
cpu->can_handle_interrupt = true;
#define REQUIRE(x) assert(blk->x); cpu->x = blk->x
REQUIRE(ReadMem);
REQUIRE(WriteMem);
REQUIRE(ReadInterruptData);
REQUIRE(ReadIO);
REQUIRE(WriteIO);
REQUIRE(InterruptComplete);
#undef REQUIRE
cpu->ControlFlow = blk->ControlFlow? blk->ControlFlow:IgnoreControlFlow;
return cpu;
}
void Z80_Free( Z80 cpu )
{
/* nothing special needed */
free( cpu );
}
static byte ReadInstructionMemory( word address, void *data )
{
Z80 cpu = data;
return (cpu->ReadMem)( address, true, cpu );
}
static inline bool ParityIsEven( uint_fast8_t a )
{
uint_fast8_t b = a & 0x55;
uint_fast8_t c = (a>>1) & 0x55;
a = b + c;
b = a & 0x33;
c = (a>>2) & 0x33;
a = b + c;
b = a & 0x0f;
c = (a>>4) & 0x0f;
return !((b + c)&1);
}
int Z80_Step( word *outPC, Z80 cpu )
{
Instruction inst;
uint_fast8_t r;
const uint_fast16_t oldPC = PC;
int ticks = 0;
cpu->restart_io = false;
if( cpu->nmi ||
(cpu->can_handle_interrupt && cpu->interrupt && cpu->iff1) )
{
cpu->halt = false;
// Any interrupt increases R by one.
r = BYTE_REG[REG_R];
r = ((r + 1) & 0x7f) | (r & 0x80);
BYTE_REG[REG_R] = r;
if( cpu->nmi )
{
cpu->nmi = false;
cpu->iff1 = false; /* Disable interrupts. */
// 5 cycles fetching and ignoring the opcode
// This can cause another nmi.
(void)(cpu->ReadMem)( PC, true, cpu );
// 6 cycles writing the PC
(cpu->WriteMem)( --SP, PCH, cpu );
(cpu->WriteMem)( --SP, PCL, cpu );
PC = 0x0066; // Fixed location
(cpu->ControlFlow)( oldPC, PC, CF_NMI, cpu );
ticks = 11;
goto interrupt_exit;
}
cpu->interrupt = false;
// This depends on the mode
switch( cpu->interrupt_mode )
{
case 0:
// interrupting device supplies instruction.
IF_ID( &inst, 0, (byte (*)(word, void*))cpu->ReadInterruptData, cpu );
inst.additional_tstates += 2; // 2 wait states add to M1 cycle
(cpu->ControlFlow)( oldPC, 0xffff, CF_INTERRUPT, cpu );
break;
case 1:
// Insert a restart instruction + 2 cycles.
// Handle it here since we know exactly what
// it is supposed to do.
(cpu->WriteMem)( --SP, PCH, cpu );
(cpu->WriteMem)( --SP, PCL, cpu );
PC = 0x0038; // Fixed location
(cpu->ControlFlow)( oldPC, PC, CF_INTERRUPT, cpu );
ticks = 13;
goto interrupt_exit;
case 2:
// 7 cycles to read the 7 bits from the
// interrupting device, 6 to push the PC, and
// 6 to load the jump address.
(cpu->WriteMem)( --SP, PCH, cpu );
(cpu->WriteMem)( --SP, PCL, cpu );
word address = ((word)BYTE_REG[REG_I]) << 8;
address |= (cpu->ReadInterruptData)( 0, cpu ) & 0xfe;
PCL = (cpu->ReadMem)( address, true, cpu );
PCH = (cpu->ReadMem)( address+1, true, cpu );
(cpu->ControlFlow)( oldPC, PC, CF_INTERRUPT, cpu );
ticks = 19;
goto interrupt_exit;
}
}
else
{
// ei re-enables iff1 but interrupts cannot be handled
// for another instruction.
cpu->can_handle_interrupt = true;
// Fetch the next instruction from memory.
if( !cpu->halt )
{
PC += IF_ID( &inst, PC, ReadInstructionMemory, cpu );
}
else
{
inst.additional_tstates = 0;
inst.offset = 0;
inst.immediate = 0;
inst.r_increment = 1;
inst.IT = &Unprefixed[0x76]; // NOP
}
}
#define OP1 (inst.IT->operand1)
#define OP2 (inst.IT->operand2)
#define OFFSET (inst.offset)
#define IMM (inst.immediate)
uint_fast32_t op1 = 0;
uint_fast32_t op2 = 0;
uint_fast32_t carry = 0;
uint_fast32_t result = 0;
int i = 0;
bool took_branch = true;
switch( inst.IT->type )
{
/* 8-Bit Load Group */
case LD_I_N:
case LD_MRR_N:
(cpu->WriteMem)( WORD_REG[OP1]+OFFSET, IMM, cpu );
break;
case LD_I_R:
case LD_MRR_R:
(cpu->WriteMem)( WORD_REG[OP1]+OFFSET, BYTE_REG[OP2], cpu );
break;
case LD_MNN_R:
(cpu->WriteMem)( IMM, BYTE_REG[OP2], cpu );
break;
case LD_R_I:
case LD_R_MRR:
result = (cpu->ReadMem)( WORD_REG[OP2]+OFFSET, false, cpu );
BYTE_REG[OP1] = result;
break;
case LD_R_MNN:
BYTE_REG[OP1] = (cpu->ReadMem)( IMM, false, cpu );
break;
case LD_R_N:
BYTE_REG[OP1] = IMM;
break;
case LD_R_R:
result = BYTE_REG[OP2];
BYTE_REG[OP1] = result;
if( OP2 == REG_I || OP2 == REG_R )
{
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !result );
SetFlagValue( FLAG_Y, result & 0x20 );
ResetFlag( FLAG_H );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, cpu->iff2 );
ResetFlag( FLAG_N );
}
break;
/* 16-Bit Load Group */
case LD_RR_MNN:
result = (cpu->ReadMem)( IMM, false, cpu );
result |= (cpu->ReadMem)( IMM+1, false, cpu ) << 8;
WORD_REG[OP1] = result;
break;
case LD_RR_NN:
WORD_REG[OP1] = IMM;
break;
case LD_RR_RR:
WORD_REG[OP1] = WORD_REG[OP2];
break;
case LD_MNN_RR:
result = WORD_REG[OP2];
(cpu->WriteMem)( IMM, result & 0xff, cpu );
(cpu->WriteMem)( IMM+1, result >> 8, cpu );
break;
case POP_RR:
result = (cpu->ReadMem)( SP++, false, cpu );
result |= (cpu->ReadMem)( SP++, false, cpu ) << 8;
WORD_REG[OP1] = result;
break;
case PUSH_RR:
result = WORD_REG[OP1];
(cpu->WriteMem)( --SP, result >> 8, cpu );
(cpu->WriteMem)( --SP, result & 0xff, cpu );
break;
/* Exchange, Block Transfer, Search Group */
case CPD:
carry = -1;
goto cpx;
case CPI:
carry = 1;
cpx:
op1 = A;
op2 = (cpu->ReadMem)( HL, false, cpu );
HL += carry;
--BC;
result = op1 - op2;
goto cp_flags;
case CPDR:
carry = -1;
goto cpxr;
case CPIR:
carry = 1;
cpxr:
op1 = A;
op2 = (cpu->ReadMem)( HL, false, cpu );
HL += carry;
--BC;
result = op1 - op2;
if( (result&0xff) && BC )
PC -= 2;
cp_flags:
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !(result&0xff) );
result -= FlagIsSet( FLAG_H );
SetFlagValue( FLAG_H, (op1&0x03) < (op2&0x03) );
SetFlagValue( FLAG_P, BC != 0 );
SetFlag( FLAG_N );
SetFlagValue( FLAG_Y, result & 0x02 ); // bit 1
SetFlagValue( FLAG_X, result & 0x08 ); // bit 3
break;
case EX_MRR_RR:
result = WORD_REG[OP1];
op1 = (cpu->ReadMem)( result, false, cpu );
op1 |= (cpu->ReadMem)( result+1, false, cpu ) << 8;
op2 = WORD_REG[OP2];
(cpu->WriteMem)( result, op2&0xff, cpu );
(cpu->WriteMem)( result+1, op2>>8, cpu );
WORD_REG[OP2] = op1;
break;
case EX_RR_RR:
result = WORD_REG[OP1];
WORD_REG[OP1] = WORD_REG[OP2];
WORD_REG[OP2] = result;
break;
case EXX:
op1 = BC;
op2 = DE;
result = HL;
BC = WORD_REG[REG_BCP];
DE = WORD_REG[REG_DEP];
HL = WORD_REG[REG_HLP];
WORD_REG[REG_BCP] = op1;
WORD_REG[REG_DEP] = op2;
WORD_REG[REG_HLP] = result;
break;
case LDD:
carry = -1;
goto ldx;
case LDI:
carry = 1;
ldx:
result = (cpu->ReadMem)( HL, false, cpu );
(cpu->WriteMem)( DE, result, cpu );
HL += carry;
DE += carry;
--BC;
goto ld_flags;
case LDDR:
carry = -1;
goto ldxr;
case LDIR:
carry = 1;
ldxr:
result = (cpu->ReadMem)( HL, false, cpu );
(cpu->WriteMem)( DE, result, cpu );
HL += carry;
DE += carry;
if( --BC )
PC -= 2;
ld_flags:
// Very strange here
op2 = result + A;
SetFlagValue( FLAG_Y, op2&0x02 ); // bit 1
ResetFlag( FLAG_H );
SetFlagValue( FLAG_X, op2&0x08 ); // bit 3
SetFlagValue( FLAG_P, BC != 0 );
ResetFlag( FLAG_N );
break;
/* 8-Bit Arithmetic and Logical Group */
case ADC_R_I:
case ADC_R_MRR:
op2 = (cpu->ReadMem)( WORD_REG[OP2]+OFFSET, false, cpu );
goto adc_r;
case ADC_R_N:
op2 = IMM;
goto adc_r;
case ADC_R_R:
op2 = BYTE_REG[OP2];
goto adc_r;
case ADD_R_I:
case ADD_R_MRR:
op2 = (cpu->ReadMem)( WORD_REG[OP2]+OFFSET, false, cpu );
goto add_r;
case ADD_R_N:
op2 = IMM;
goto add_r;
case ADD_R_R:
op2 = BYTE_REG[OP2];
goto add_r;
adc_r:
carry = FlagIsSet( FLAG_C );
add_r:
op1 = BYTE_REG[OP1];
result = op1 + op2 + carry;
BYTE_REG[OP1] = result & 0xff;
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !(result & 0xff) );
SetFlagValue( FLAG_Y, result & 0x20 ); // bit 5
SetFlagValue( FLAG_H, (op1&0x0f)+(op2&0x0f)+carry>0x0f );
SetFlagValue( FLAG_X, result & 0x08 ); // bit 3
SetFlagValue( FLAG_P, (op2 == 0x7f && carry) ||
((op1&0x80)==(op1&0x80) &&
(op1&0x80)!=(result&0x80)) );
ResetFlag( FLAG_N );
SetFlagValue( FLAG_C, result > 0xff );
break;
case SBC_R_I:
case SBC_R_MRR:
op2 = (cpu->ReadMem)( WORD_REG[OP2]+OFFSET, false, cpu );
goto sbc_r;
case SBC_R_N:
op2 = IMM;
goto sbc_r;
case SBC_R_R:
op2 = BYTE_REG[OP2];
goto sbc_r;
case SUB_I:
case SUB_MRR:
op2 = (cpu->ReadMem)( WORD_REG[OP1]+OFFSET, false, cpu );
goto sub_r;
case SUB_N:
op2 = IMM;
goto sub_r;
case SUB_R:
op2 = BYTE_REG[OP1];
goto sub_r;
sbc_r:
carry = FlagIsSet( FLAG_C );
sub_r:
op1 = A;
result = op1 - op2 - carry;
A = result & 0xff;
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !(result & 0xff) );
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlagValue( FLAG_H, (op1&0x0f) < (op2&0x0f)+carry );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, (carry && op1-op2 == 0x80) ||
((op1&0x80) != (op2&0x80) &&
(op1&0x80) != (result&0x80)) );
SetFlagValue( FLAG_C, op1 < op2 + carry );
break;
case DEC_I:
case DEC_MRR:
result = (cpu->ReadMem)( WORD_REG[OP1]+OFFSET, false, cpu );
carry = result;
--result;
(cpu->WriteMem)( WORD_REG[OP1]+OFFSET, result & 0xff, cpu );
goto dec_x;
case DEC_R:
result = BYTE_REG[OP1];
carry = result;
BYTE_REG[OP1] = --result;
dec_x:
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !(result&0xff) );
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlagValue( FLAG_H, !(carry&0x0f) );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, carry == 0x80 );
SetFlag( FLAG_N );
break;
case INC_I:
case INC_MRR:
result = (cpu->ReadMem)( WORD_REG[OP1]+OFFSET, false, cpu );
carry = result;
++result;
(cpu->WriteMem)( WORD_REG[OP1]+OFFSET, result, cpu );
goto inc_x;
case INC_R:
result = BYTE_REG[OP1];
carry = result;
++result;
BYTE_REG[OP1] = result;
inc_x:
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !(result&0xff) );
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlagValue( FLAG_H, (carry&0x0f)+1 > 0x0f );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, carry & 0x7f );
ResetFlag( FLAG_N );
break;
case CP_I:
case CP_MRR:
op2 = (cpu->ReadMem)( WORD_REG[OP1]+OFFSET, false, cpu );
goto cp;
case CP_N:
op2 = IMM;
goto cp;
case CP_R:
op2 = BYTE_REG[OP1];
cp:
op1 = A;
result = op1 - op2;
SetFlagValue( FLAG_S, result&0x80 );
SetFlagValue( FLAG_Z, !(result&0xff) );
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlagValue( FLAG_H, (op1&0x0f) < (op2&0x0f) );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, (op1&0x80) != (op2&0x80) &&
(op1&0x80) != (result&0x80) );
SetFlag( FLAG_N );
SetFlagValue( FLAG_C, op1 < op2 );
break;
case AND_I:
case AND_MRR:
result = A &= (cpu->ReadMem)( WORD_REG[OP1]+OFFSET, false, cpu );
SetFlag( FLAG_H );
goto logical_flags;
case AND_N:
result = A &= IMM;
SetFlag( FLAG_H );
goto logical_flags;
case AND_R:
result = A &= BYTE_REG[OP1];
SetFlag( FLAG_H );
goto logical_flags;
case OR_I:
case OR_MRR:
result = A | (cpu->ReadMem)( WORD_REG[OP1]+OFFSET, false, cpu );
ResetFlag( FLAG_H );
goto logical_flags; /* Same flags as and */
case OR_N:
result = A | IMM;
ResetFlag( FLAG_H );
goto logical_flags;
case OR_R:
result = A | BYTE_REG[OP1];
ResetFlag( FLAG_H );
goto logical_flags;
case XOR_I:
case XOR_MRR:
result = A ^ (cpu->ReadMem)( WORD_REG[OP1]+OFFSET, false, cpu );
ResetFlag( FLAG_H );
goto logical_flags;
case XOR_N:
result = A ^ IMM;
ResetFlag( FLAG_H );
goto logical_flags;
case XOR_R:
result = A ^ BYTE_REG[OP1];
ResetFlag( FLAG_H );
logical_flags:
A = result;
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !result );
SetFlagValue( FLAG_Y, result & 0x02 );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, ParityIsEven(result) );
ResetFlag( FLAG_N );
ResetFlag( FLAG_C );
break;
/* General-Purpose Arithmetic and CPU Control Group */
case CCF:
result = FlagIsSet( FLAG_C );
SetFlagValue( FLAG_Y, A & 0x20 );
SetFlagValue( FLAG_H, result );
SetFlagValue( FLAG_X, A & 0x08 );
ResetFlag( FLAG_N );
SetFlagValue( FLAG_C, !result );
break;
case CPL:
result = ~A;
A = result;
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlag( FLAG_H );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlag( FLAG_N );
break;
case DAA:
op1 = FlagIsSet( FLAG_N );
op2 = FlagIsSet( FLAG_H );
carry = FlagIsSet( FLAG_C );
result = A;
static const uint8_t daa_table[13][9] =
{
/*N C hi hi H lo lo add C */
{ 0, 0, 0x0, 0x9, 0, 0x0, 0x9, 0x00, 0 },
{ 0, 0, 0x0, 0x8, 0, 0xA, 0xF, 0x06, 0 },
{ 0, 0, 0x0, 0x9, 1, 0x0, 0x3, 0x06, 0 },
{ 0, 0, 0xA, 0xF, 0, 0x0, 0x9, 0x60, 1 },
{ 0, 0, 0x9, 0xF, 0, 0xA, 0xF, 0x66, 1 },
{ 0, 0, 0xA, 0xF, 1, 0x0, 0x3, 0x66, 1 },
{ 0, 1, 0x0, 0x2, 0, 0x0, 0x9, 0x60, 1 },
{ 0, 1, 0x0, 0x2, 0, 0xA, 0xF, 0x66, 1 },
{ 0, 1, 0x0, 0x3, 1, 0x0, 0x3, 0x66, 1 },
{ 1, 0, 0x0, 0x9, 0, 0x0, 0x9, 0x00, 0 },
{ 1, 0, 0x0, 0x8, 1, 0x6, 0xF, 0xFA, 0 },
{ 1, 1, 0x7, 0xF, 0, 0x0, 0x9, 0xA0, 1 },
{ 1, 1, 0x6, 0xF, 1, 0x6, 0xF, 0x9A, 1 },
};
for( i = 0; i < 13; ++i )
{
if( daa_table[i][0] == op1 &&
daa_table[i][1] == carry &&
daa_table[i][2] <= result >> 4 &&
daa_table[i][3] >= result >> 4 &&
daa_table[i][4] == op2 &&
daa_table[i][5] <= (result & 0x0f) &&
daa_table[i][6] >= (result & 0x0f) )
{
result = (result + daa_table[i][7]) & 0xff;
SetFlagValue( FLAG_C, daa_table[i][7] );
break;
}
}
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !result );
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, ParityIsEven(result) );
break;
case DI:
cpu->iff1 = false;
cpu->iff2 = false;
break;
case EI:
cpu->iff1 = true;
cpu->iff2 = true;
cpu->can_handle_interrupt = false;
break;
case HALT:
cpu->halt = true;
(cpu->ControlFlow)( oldPC, PC, CF_HALT, cpu );
break;
case IM:
cpu->interrupt_mode = OP1;
break;
case NEG: // This does A <- 0 - A, flags set accordingly.
result = -A;
A = result & 0xff;
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !result );
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlagValue( FLAG_H, result & 0x0f );
SetFlagValue( FLAG_X, result & 0x08 );
SetFlagValue( FLAG_P, (result&0xff) == 0x80 );
SetFlag( FLAG_N );
SetFlagValue( FLAG_C, !result );
break;
case NOP:
break;
case SCF:
SetFlagValue( FLAG_Y, A & 0x20 );
ResetFlag( FLAG_H );
SetFlagValue( FLAG_X, A & 0x08 );
ResetFlag( FLAG_N );
SetFlag( FLAG_C );
break;
/* 16-Bit Arithmetic Group */
case ADD_RR_RR:
op1 = WORD_REG[OP1];
op2 = WORD_REG[OP2];
result = op1 + op2;
goto add_rr_flags;
case ADC_RR_RR:
op1 = WORD_REG[OP1];
op2 = WORD_REG[OP2];
carry = FlagIsSet( FLAG_C );
result = op1 + op2 + carry;
SetFlagValue( FLAG_S, result & 0x8000 );
SetFlagValue( FLAG_Z, !(result & 0xffff) );
SetFlagValue( FLAG_P, (op2 == 0x7fff && carry) ||
((op1&0x8000) == ((op2+carry)&0x8000) &&
(op1&0x8000) != (result&0x8000)) );
add_rr_flags:
SetFlagValue( FLAG_Y, result & 0x2000 ); // bit 13
SetFlagValue( FLAG_H, (op1&0x0fff)+(op2&0x0fff)+carry>0x0fff );
SetFlagValue( FLAG_X, result & 0x0800 ); // bit 11
ResetFlag( FLAG_N );
SetFlagValue( FLAG_C, result > 0xffff );
WORD_REG[OP1] = result & 0xffff;
break;
case DEC_RR:
--WORD_REG[OP1];
break;
case INC_RR:
++WORD_REG[OP1];
break;
case SBC_RR_RR:
op1 = WORD_REG[OP1];
op2 = WORD_REG[OP2];
carry = FlagIsSet( FLAG_C );
result = op1 - op2 - carry;
WORD_REG[OP1] = result & 0xffff;
SetFlagValue( FLAG_S, result & 0x8000 );
SetFlagValue( FLAG_Z, !(result & 0xffff) );
SetFlagValue( FLAG_Y, result & 0x2000 );
SetFlagValue( FLAG_H, (op1&0x0fff) < (op2&0x0fff)+carry );
SetFlagValue( FLAG_X, result & 0x0800 );
SetFlagValue( FLAG_P, (carry && op1-op2 == 0x8000) ||
((op1&0x8000) != (op2&0x8000) &&
(op1&0x8000) != (result&0x8000)) );
SetFlagValue( FLAG_C, op1 < op2 + carry );
break;
/* Rotate and Shift Group
* Almost all flags are set the same so jump to a common block
* of flag setting. */
case RLCA:
result = A;
carry = result >> 7;
result = (result << 1) | carry;
A = result & 0xff;
goto rotate_accum_flags;
case RLA:
result = A;
carry = result >> 7;
result = (result << 1) | FlagIsSet(FLAG_C);
A = result & 0xff;
goto rotate_accum_flags;
case RRCA:
result = A;
carry = result & 0x1;
result = (result >> 1) | (carry << 7);
A = result;
goto rotate_accum_flags;
case RRA:
result = A;
carry = result & 0x1;
result = (result >> 1) | (FlagIsSet(FLAG_C) << 7);
A = result;
goto rotate_accum_flags;
case RLC_I:
case RLC_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu );
carry = result >> 7;
result = (result << 1) | carry;
(cpu->WriteMem)( op1, result & 0xff, cpu );
goto shift_flags;
case RLC_R:
result = BYTE_REG[OP1];
carry = result >> 7;
result = (result << 1) | carry;
BYTE_REG[OP1] = result;
goto shift_flags;
case RL_I:
case RL_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu );
carry = result >> 7;
result = (result << 1) | FlagIsSet(FLAG_C);
(cpu->WriteMem)( op1, result & 0xff, cpu );
goto shift_flags;
case RL_R:
result = BYTE_REG[OP1];
carry = result >> 7;
result = (result << 1) | FlagIsSet(FLAG_C);
BYTE_REG[OP1] = result & 0xff;
goto shift_flags;
case RRC_I:
case RRC_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu );
carry = result & 0x1;
result = (result >> 1) | (carry << 7);
(cpu->WriteMem)( op1, result, cpu );
goto shift_flags;
case RRC_R:
result = BYTE_REG[OP1];
carry = result & 0x1;
result = (result >> 1) | (carry << 7);
BYTE_REG[OP1] = result;
goto shift_flags;
case RR_I:
case RR_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu );
carry = result & 0x1;
result = (result >> 1) | (FlagIsSet(FLAG_C) << 7);
(cpu->WriteMem)( op1, result, cpu );
goto shift_flags;
case RR_R:
result = BYTE_REG[OP1];
carry = result & 0x1;
result = (result >> 1) | (FlagIsSet(FLAG_C) << 7);
BYTE_REG[OP1] = result;
goto shift_flags;
case SLA_I:
case SLA_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu );
carry = result >> 7;
result <<= 1;
(cpu->WriteMem)( op1, result & 0xff, cpu );
goto shift_flags;
case SLA_R:
result = BYTE_REG[OP1];
carry = result >> 7;
result <<= 1;
BYTE_REG[OP1] = result & 0xff;
goto shift_flags;
case SLL_I:
case SLL_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu);
carry = result >> 7;
result = (result << 1) | 0x1;
(cpu->WriteMem)( op1, result & 0xff, cpu );
goto shift_flags;
case SLL_R:
result = BYTE_REG[OP1];
carry = result >> 7;
result = (result << 1) | 0x1;
BYTE_REG[OP1] = result & 0xff;
goto shift_flags;
case SRA_I:
case SRA_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu );
carry = result & 0x1;
result = (result & 0x80) | (result >> 1);
(cpu->WriteMem)( op1, result, cpu );
goto shift_flags;
case SRA_R:
result = BYTE_REG[OP1];
carry = result & 0x1;
result = (result & 0x80) | (result >> 1);
BYTE_REG[OP1] = result;
goto shift_flags;
case SRL_I:
case SRL_MRR:
op1 = WORD_REG[OP1]+OFFSET;
result = (cpu->ReadMem)( op1, false, cpu );
carry = result & 0x1;
result >>= 1;
(cpu->WriteMem)( op1, result, cpu );
goto shift_flags;
case SRL_R:
result = BYTE_REG[OP1];
carry = result & 0x1;
result >>= 1;
BYTE_REG[OP1] = result;
goto shift_flags;
case RLD:
op1 = (cpu->ReadMem)( HL, false, cpu );
op2 = A;
result = (op2 & 0xf0) | (op1 >> 4);
op1 = (op1 << 4) | (op2 & 0x0f);
(cpu->WriteMem)( HL, op1 & 0xff, cpu );
A = result;
carry = FlagIsSet( FLAG_C ); // makes code simpler
goto shift_flags;
case RRD:
op1 = (cpu->ReadMem)( HL, false, cpu );
op2 = A;
result = (op2 & 0xf0) | (op1 & 0x0f);
op1 = (op1 >> 4) | (op2 << 4);
(cpu->WriteMem)( HL, op1 & 0xff, cpu );
A = result;
carry = FlagIsSet( FLAG_C ); // simpler code
shift_flags:
SetFlagValue( FLAG_S, result & 0x80 );
SetFlagValue( FLAG_Z, !result );
SetFlagValue( FLAG_P, ParityIsEven(result) );
rotate_accum_flags:
SetFlagValue( FLAG_Y, result & 0x20 );
ResetFlag( FLAG_H );
SetFlagValue( FLAG_X, result & 0x08 );
ResetFlag( FLAG_N );
SetFlagValue( FLAG_C, carry );
break;
/* Bit Set, Reset, and Test Group
* In this group, the first operand is the bit to
* set/reset/test. */
case BIT_I:
case BIT_MRR:
op2 = (cpu->ReadMem)( WORD_REG[OP2]+OFFSET, false, cpu );
result = op2 & (0x1<<OP1);
// XXX: This is wrong for BIT_MRR, but right for BIT_I
// Does anyone know what the right thing for BIT_MRR
// is?
SetFlagValue( FLAG_Y, (WORD_REG[OP2]+OFFSET)&0x20 );
SetFlagValue( FLAG_X, (WORD_REG[OP2]+OFFSET)&0x08 );
goto bit;
case BIT_R:
op2 = BYTE_REG[OP2];
result = op2 & (0x1<<OP1);
SetFlagValue( FLAG_Y, result & 0x20 );
SetFlagValue( FLAG_X, result & 0x08 );
bit:
SetFlagValue( FLAG_S, OP1==7 && result );
SetFlagValue( FLAG_Z, !result );
SetFlag( FLAG_H );
SetFlagValue( FLAG_P, !result );
ResetFlag( FLAG_N );
break;
case RES_I:
case RES_MRR:
op2 = WORD_REG[OP2] + OFFSET;
result = (cpu->ReadMem)( op2, false, cpu ) & ~(1<<OP1);
(cpu->WriteMem)( op2, result, cpu );
if( inst.IT->extra != INV )
BYTE_REG[inst.IT->extra] = result;
break;
case RES_R:
result = BYTE_REG[OP2] & ~(1<<OP1);
BYTE_REG[OP2] = result;
if( inst.IT->extra != INV )
BYTE_REG[inst.IT->extra] = result;
break;
case SET_I:
case SET_MRR:
op2 = WORD_REG[OP2] + OFFSET;
result = (cpu->ReadMem)( op2, false, cpu ) | (1<<OP1);
(cpu->WriteMem)( op2, result, cpu );
if( inst.IT->extra != INV )
BYTE_REG[inst.IT->extra] = result;
break;
case SET_R:
result = BYTE_REG[OP2] | (1<<OP1);
BYTE_REG[OP2] = result;
if( inst.IT->extra != INV )
BYTE_REG[inst.IT->extra] = result;
break;
/* Jump Group */
case DJNZ:
if( --B )
PC += OFFSET;
else
took_branch = false;
break;
case JP_C_MNN:
if( !CondIsMet(OP1) )
{
took_branch = false;
break; // condition isn't met