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Notice how we perform a read-modify-write sequence without anything preventing the same thing being done to another pin in the same port.
As far as I can see, I believe we would need either a critical section or exclusive access to some sort of token to guarantee exclusive access. A critical section would cause a slight bit of overhead but would otherwise be non-breaking API-wise, I think.
The text was updated successfully, but these errors were encountered:
I think that you are correct, there is a potential race condition here.
It looks like the stm32g4 supports bit-banding on peripherals, so that would give you atomic writes of single bits without needing critical sections or API changes.
But writing the bits one at a time would on the other hand cause potentialy bad things to happen since the write would be split up into multiple writes.
For example looking at PUPD[15:0][1:0] in the RM, changing from 01: Pull-up to 10: Pull-down would be
Store 1 to left bit at bit banding address <-- We now have 11 which is reserved
I hope I am wrong, but I think there might be a race condition in the gpio's
into_{x}
methods.stm32g4xx-hal/src/gpio.rs
Line 386 in f8b6ff8
Notice how we perform a read-modify-write sequence without anything preventing the same thing being done to another pin in the same port.
As far as I can see, I believe we would need either a critical section or exclusive access to some sort of token to guarantee exclusive access. A critical section would cause a slight bit of overhead but would otherwise be non-breaking API-wise, I think.
The text was updated successfully, but these errors were encountered: