From 1ff0655790c51d39968b6f68a204871f55ac87b4 Mon Sep 17 00:00:00 2001
From: stnolting <stnolting@gmail.com>
Date: Sat, 4 Jan 2025 20:04:22 +0100
Subject: [PATCH] add A ISA support

---
 README.md                       | 1 +
 plugin-neorv32/neorv32_isa.yaml | 6 +++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 73f34a7..45f2987 100644
--- a/README.md
+++ b/README.md
@@ -12,6 +12,7 @@ This repository is a port of the "**RISCOF** RISC-V Architectural Test Framework
 user and privileged ISA specifications. **Sail RISC-V** is used as reference model.
 Currently, the following tests are supported:
 
+- [x] `rv32i_m\A` - atomic memory operations (`Zaamo` only)
 - [x] `rv32i_m\B` - bit-manipulation (`Zba` + `Zbb` + `Zbs`)
 - [x] `rv32i_m\C` - compressed instructions
 - [x] `rv32i_m\I` - base integer ISA
diff --git a/plugin-neorv32/neorv32_isa.yaml b/plugin-neorv32/neorv32_isa.yaml
index 073286a..9b21855 100644
--- a/plugin-neorv32/neorv32_isa.yaml
+++ b/plugin-neorv32/neorv32_isa.yaml
@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMCUZicsr_Zicond_Zifencei_Zba_Zbb_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksh_Zksed
+  ISA: RV32IMACUZicsr_Zicond_Zifencei_Zba_Zbb_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksh_Zksed
   physical_addr_sz: 32
   User_Spec_Version: "2.3"
   Privilege_Spec_Version: "1.11"
@@ -8,7 +8,7 @@ hart0:
   pmp_granularity: 4
   supported_xlen: [32]
   misa:
-    reset-val: 0x40101104
+    reset-val: 0x40101105
     rv32:
       accessible: true
       mxl:
@@ -26,6 +26,6 @@ hart0:
             warl:
                dependency_fields: []
                legal:
-                 - extensions[25:0] in [0x0101104]
+                 - extensions[25:0] in [0x0101105]
                wr_illegal:
                  - unchanged