From 3624785edc7ae9e0ad2fe6b0910599f0b44d5849 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 23 Dec 2024 03:30:23 +0000 Subject: [PATCH 1/2] [Dependabot]: Bump neorv32 from `3d986cb` to `fc0034f` Bumps [neorv32](https://github.com/stnolting/neorv32) from `3d986cb` to `fc0034f`. - [Release notes](https://github.com/stnolting/neorv32/releases) - [Commits](https://github.com/stnolting/neorv32/compare/3d986cb7924d1ae76341e9bd444234c57c54c4e1...fc0034f787914fc7622836a56a6b044925732e66) --- updated-dependencies: - dependency-name: neorv32 dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- neorv32 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/neorv32 b/neorv32 index 3d986cb..fc0034f 160000 --- a/neorv32 +++ b/neorv32 @@ -1 +1 @@ -Subproject commit 3d986cb7924d1ae76341e9bd444234c57c54c4e1 +Subproject commit fc0034f787914fc7622836a56a6b044925732e66 From 702431b7fe32b5d60f25a32fb421f64403a6cb39 Mon Sep 17 00:00:00 2001 From: stnolting Date: Mon, 23 Dec 2024 07:34:43 +0100 Subject: [PATCH 2/2] [sim] update core generics --- sim/neorv32_riscof_tb.vhd | 52 +++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/sim/neorv32_riscof_tb.vhd b/sim/neorv32_riscof_tb.vhd index 56ceaaf..4583699 100644 --- a/sim/neorv32_riscof_tb.vhd +++ b/sim/neorv32_riscof_tb.vhd @@ -139,38 +139,38 @@ begin neorv32_top_inst: neorv32_top generic map ( -- Processor Clocking -- - CLOCK_FREQUENCY => 100_000_000, + CLOCK_FREQUENCY => 100_000_000, -- Boot Configuration -- - BOOT_MODE_SELECT => 1, -- boot from BOOT_ADDR_CUSTOM - BOOT_ADDR_CUSTOM => x"00000000", + BOOT_MODE_SELECT => 1, -- boot from BOOT_ADDR_CUSTOM + BOOT_ADDR_CUSTOM => x"00000000", -- RISC-V CPU Extensions -- - RISCV_ISA_C => true, - RISCV_ISA_M => true, - RISCV_ISA_U => true, - RISCV_ISA_Zba => true, - RISCV_ISA_Zbb => true, - RISCV_ISA_Zbkb => true, - RISCV_ISA_Zbkc => true, - RISCV_ISA_Zbkx => true, - RISCV_ISA_Zbs => true, - RISCV_ISA_Zicntr => true, - RISCV_ISA_Zicond => true, - RISCV_ISA_Zknd => true, - RISCV_ISA_Zkne => true, - RISCV_ISA_Zknh => true, - RISCV_ISA_Zksed => true, - RISCV_ISA_Zksh => true, + RISCV_ISA_C => true, + RISCV_ISA_M => true, + RISCV_ISA_U => true, + RISCV_ISA_Zba => true, + RISCV_ISA_Zbb => true, + RISCV_ISA_Zbkb => true, + RISCV_ISA_Zbkc => true, + RISCV_ISA_Zbkx => true, + RISCV_ISA_Zbs => true, + RISCV_ISA_Zicntr => true, + RISCV_ISA_Zicond => true, + RISCV_ISA_Zknd => true, + RISCV_ISA_Zkne => true, + RISCV_ISA_Zknh => true, + RISCV_ISA_Zksed => true, + RISCV_ISA_Zksh => true, -- Tuning Options -- - FAST_MUL_EN => true, - FAST_SHIFT_EN => true, + CPU_FAST_MUL_EN => true, + CPU_FAST_SHIFT_EN => true, -- Internal Instruction memory -- - MEM_INT_IMEM_EN => false, + MEM_INT_IMEM_EN => false, -- Internal Data memory -- - MEM_INT_DMEM_EN => false, + MEM_INT_DMEM_EN => false, -- External bus interface -- - XBUS_EN => true, - XBUS_TIMEOUT => 7, - XBUS_REGSTAGE_EN => false + XBUS_EN => true, + XBUS_TIMEOUT => 7, + XBUS_REGSTAGE_EN => false ) port map ( -- Global control --